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`include "DEF.v"
module rs(clock, rs_free, rs_lok, rs_sok, rg_ok, rg_num, rg_check, in_op, in_address, in_reg, in_reg2, write, out_dst, out_dst_data, write_dst, in_databus, out_databus, write_databus);
input clock;
input [4:0] rg_num;
input [31:0] in_op;
input [31:0] in_address;
input [4:0] in_reg, in_reg2;
input rg_check;
input write;
input [63:0] in_databus;
output [4:0] out_dst;
output [31:0] out_dst_data;
output write_dst;
output [63:0] out_databus;
output write_databus;
output rs_lok, rs_sok;
output rs_free;
output rg_ok;
reg rs_load_busy [3:0];
reg [31:0] rs_load_address [3:0];
reg [4:0] rs_load_reg [3:0];
reg [4:0] rs_load_reg2 [3:0];
reg rs_store_busy [3:0];
reg [31:0] rs_store_address [3:0];
reg [4:0] rs_store_reg [3:0];
reg [4:0] rs_store_reg2 [3:0];
reg [3:0] reg_status [31:0]; /* need to be set to 0 initially */
reg r_rs_lok, r_rs_sok; /* need to be set to 1 initially */
reg r_rs_free; /* need to be set to 1 initially */
reg r_rg_ok;
assign rg_ok = r_rg_ok;
assign rs_lok = r_rs_lok;
assign rs_sok = r_rs_sok;
assign rs_free = r_rs_free;
task update_rsok;
begin
if(rs_store_busy[0] === 1 && rs_store_busy[1] === 1 &&
rs_store_busy[2] === 1 && rs_store_busy[3] === 1)
begin
r_rs_sok <= 0;
end
else
begin
r_rs_sok <= 1;
end
if(rs_load_busy[0] === 1 && rs_load_busy[1] === 1 &&
rs_load_busy[2] === 1 && rs_load_busy[3] === 1)
begin
r_rs_lok <= 0;
end
else
begin
r_rs_lok <= 1;
end
if((rs_store_busy[0] === 0) && (rs_store_busy[1] === 0) &&
(rs_store_busy[2] === 0) && (rs_store_busy[3] === 0) &&
(rs_load_busy[0] === 0) && (rs_load_busy[1] === 0) &&
(rs_load_busy[2] === 0) && (rs_load_busy[3] === 0))
begin
r_rs_free <= 1;
end
else
begin
r_rs_free <= 0;
end
end
endtask
always @(posedge rg_check)
begin
if(reg_status[rg_num] === 0)
begin
r_rg_ok <= 0;
end
else
begin
r_rg_ok <= 1; //not ok
end
end
always @(posedge clock)
begin
/*
$display("%d %d %d %d %d %d %d %d %d %d [%d %d %d %d]\
", rs_load_busy[0],
rs_load_busy[1], rs_load_busy[2], rs_load_busy[3],
rs_store_busy[0], rs_store_busy[1], rs_store_busy[2], rs_store_busy[3], in_databus, in_databus[31:0], rs_store_address[0], rs_store_address[1], rs_store_address[2], rs_store_address[3]);
$display("0:%d 1:%d 2:%d 3:%d 4:%d 5:%d 6:%d 7:%d\
",
reg_status[0], reg_status[1], reg_status[2], reg_status[3], reg_status[4], reg_status[5], reg_status[6], reg_status[7]);
$display("8:%d 9:%d 10:%d 11:%d 12:%d 13:%d 14:%d 15:%d\
",
reg_status[8], reg_status[9], reg_status[10], reg_status[11], reg_status[12], reg_status[13], reg_status[14], reg_status[15]);
$display("16:%d 17:%d 18:%d 19:%d 20:%d 21:%d 22:%d 23:%d\
",
reg_status[16], reg_status[17], reg_status[18], reg_status[19], reg_status[20], reg_status[21], reg_status[22], reg_status[23]);
$display("24:%d 25:%d 26:%d 27:%d 28:%d 29:%d 30:%d 31:%d\
",
reg_status[24], reg_status[25], reg_status[26], reg_status[27], reg_status[28], reg_status[29], reg_status[30], reg_status[31]);
*/
if(in_databus[63:48] === 16\'b0000_0000_0000_0001)
begin
/*$display("got it\
"); $stop;*/
if(rs_load_busy[0] === 1 && rs_load_address[0] === in_databus[31:0])
begin
rs_load_busy[0] <= 0;
reg_status[rs_load_reg[0]] <= reg_status[rs_load_reg[0]] - 1;
#0.001 reg_status[rs_load_reg2[0]] <= reg_status[rs_load_reg2[0]] - 1;
end
if(rs_load_busy[1] === 1 && rs_load_address[1] === in_databus[31:0])
begin
rs_load_busy[1] <= 0;
reg_status[rs_load_reg[1]] <= reg_status[rs_load_reg[1]] - 1;
#0.001 reg_status[rs_load_reg2[1]] <= reg_status[rs_load_reg2[1]] - 1;
end
if(rs_load_busy[2] === 1 && rs_load_address[2] === in_databus[31:0])
begin
rs_load_busy[2] <= 0;
reg_status[rs_load_reg[2]] <= reg_status[rs_load_reg[2]] - 1;
#0.001 reg_status[rs_load_reg2[2]] <= reg_status[rs_load_reg2[2]] - 1;
end
if(rs_load_busy[3] === 1 && rs_load_address[3] === in_databus[31:0])
begin
rs_load_busy[3] <= 0;
reg_status[rs_load_reg[3]] <= reg_status[rs_load_reg[3]] - 1;
#0.001 reg_status[rs_load_reg2[3]] <= reg_status[rs_load_reg2[3]] - 1;
end
end
if(in_databus[63:48] === 16\'b0000_0000_0000_0010)
begin
/*$display("got it!\
"); $stop;*/
if(rs_store_busy[0] === 1 && rs_store_address[0] === in_databus[31:0])
begin
rs_store_busy[0] <= 0;
reg_status[rs_store_reg[0]] <= reg_status[rs_store_reg[0]] - 1;
#0.001 reg_status[rs_store_reg2[0]] <= reg_status[rs_store_reg2[0]] - 1;
end
if(rs_store_busy[1] === 1 && rs_store_address[1] === in_databus[31:0])
begin
rs_store_busy[1] <= 0;
reg_status[rs_store_reg[1]] <= reg_status[rs_store_reg[1]] - 1;
#0.001 reg_status[rs_store_reg2[1]] <= reg_status[rs_store_reg2[1]] - 1;
end
if(rs_store_busy[2] === 1 && rs_store_address[2] === in_databus[31:0])
begin
rs_store_busy[2] <= 0;
reg_status[rs_store_reg[2]] <= reg_status[rs_store_reg[2]] - 1;
#0.001 reg_status[rs_store_reg2[2]] <= reg_status[rs_store_reg2[2]] - 1;
end
if(rs_store_busy[3] === 1 && rs_store_address[3] === in_databus[31:0])
begin
rs_store_busy[3] <= 0;
reg_status[rs_store_reg[3]] <= reg_status[rs_store_reg[3]] - 1;
#0.001 reg_status[rs_store_reg2[3]] <= reg_status[rs_store_reg2[3]] - 1;
end
end
#0.001 update_rsok;
end
always @(posedge write)
begin
if(in_op === 9) //lw
begin
reg_status[in_reg] <= reg_status[in_reg] + 1;
#0.001
reg_status[in_reg2] <= reg_status[in_reg2] + 1;
if(rs_load_busy[0] === 1)
begin
if(rs_load_busy[1] === 1)
begin
if(rs_load_busy[2] === 1)
begin
rs_load_busy[3] <= 1;
rs_load_address[3] <= in_address;
rs_load_reg[3] <= in_reg;
rs_load_reg2[3] <= in_reg2;
end
else
begin
rs_load_busy[2] <= 1;
rs_load_address[2] <= in_address;
rs_load_reg[2] <= in_reg;
rs_load_reg2[2] <= in_reg2;
end
end
else
begin
rs_load_busy[1] <= 1;
rs_load_address[1] <= in_address;
rs_load_reg[1] <= in_reg;
rs_load_reg2[1] <= in_reg2;
end
end
else
begin
rs_load_busy[0] <= 1;
rs_load_address[0] <= in_address;
rs_load_reg[0] <= in_reg;
rs_load_reg2[0] <= in_reg2;
end
end
else if(in_op === 10)
begin
reg_status[in_reg] <= reg_status[in_reg] + 1;
#0.001
reg_status[in_reg2] <= reg_status[in_reg2] + 1;
if(rs_store_busy[0] === 1)
begin
if(rs_store_busy[1] === 1)
begin
if(rs_store_busy[2] === 1)
begin
rs_store_busy[3] <= 1;
rs_store_address[3] <= in_address;
rs_store_reg[3] <= in_reg;
rs_store_reg2[3] <= in_reg2;
end
else
begin
rs_store_busy[2] <= 1;
rs_store_address[2] <= in_address;
rs_store_reg[2] <= in_reg;
rs_store_reg2[2] <= in_reg2;
end
end
else
begin
rs_store_busy[1] <= 1;
rs_store_address[1] <= in_address;
rs_store_reg[1] <= in_reg;
rs_store_reg2[1] <= in_reg2;
end
end
else
begin
rs_store_busy[0] <= 1;
rs_store_address[0] <= in_address;
rs_store_reg[0] <= in_reg;
rs_store_reg2[0] <= in_reg2;
end
end
else
begin
reg_status[in_reg] <= reg_status[in_reg] + 1;
#0.001
reg_status[in_reg2] <= reg_status[in_reg2] + 1;
end
#0.001 update_rsok;
end
endmodule
|
`include "DEF.v"
/*
ICACHE_BLOCK_SIZE 64*4 byte
ICACHE_SIZE 16\'h10000 byte
IMEMORY_SIZE 24\'h1000000 byte
*/
module imemory(address, data, /*enable,*/ read);
input [31:0] address;
output [127:0] data;
//input enable;
input read;
reg [127:0] imemory [20\'hFFFFF:0];
assign data = (/*enable &&*/ read) ? imemory[address] : 128\'hz;
endmodule
|
`include "DEF.v"
module pc(pc_address, nxt_address, write/*, reset*/);
output [31:0] pc_address;
input [31:0] nxt_address;
input write/*, reset*/;
reg [31:0] r_pc_address;
assign pc_address = r_pc_address;
always @(posedge write /*or posedge reset*/)
begin
/*if(reset)
pc_address <= 31\'b0;
else*/
r_pc_address <= nxt_address;
end
endmodule
|
always @(negedge reset or posedge clk) begin
if (reset == 0) begin
d_out <= 16'h0000;
d_out_mem[resetcount] <= d_out;
laststoredvalue <= d_out;
end else begin
d_out <= d_out + 1'b1;
end
end
always @(bufreadaddr)
bufreadval = d_out_mem[bufreadaddr];
|
`timescale 1 ns / 1 ps
// This component will read in a column of interest, and hash the value.
module hash_phase (
input clk,
input rst,
output done,
input [63:0] hash_mask_in,
output afull_out,
input write_en_in,
input [63:0] value_in,
output empty_out,
input read_en_in,
output [63:0] value_out,
output [63:0] hash_out
);
wire function_valid_out_s;
wire [63:0] function_data_out_s;
hash_function FUNCTION (
.clk (clk),
.rst (rst),
.valid_in (write_en_in),
.data_in ({32'd0, value_in[63:32]}),
.valid_out (function_valid_out_s),
.data_out (function_data_out_s)
);
wire [1:0] fifo_afull_s;
wire fifo_empty_s;
wire [63:0] hash_fifo_data_out_s;
sync_2_fifo FIFO (
.clk (clk),
.rst (rst),
.afull_out (fifo_afull_s),
.write_en_in ({write_en_in, function_valid_out_s}),
.data_1_in (value_in),
.data_0_in (function_data_out_s),
.empty_out (fifo_empty_s),
.read_en_in (read_en_in),
.data_1_out (value_out),
.data_0_out (hash_fifo_data_out_s)
);
assign hash_out = hash_fifo_data_out_s & hash_mask_in;
assign afull_out = (fifo_afull_s != 2'd0);
assign empty_out = fifo_empty_s;
assign done = fifo_empty_s;
endmodule
|
`timescale 1 ns / 1 ps
module engine (
input clk,
input rst,
output done,
input [63:0] num_rows_in,
input [63:0] rows_size_in, // size is passed in bytes
input [63:0] row_start_in, // what row should it start at
input [63:0] row_skip_in, // how many rows should be skipped when
// incrementing
input [63:0] hash_table_mask,
input row_rq_stall_in,
output row_rq_vld_out,
output [47:0] row_rq_vadr_out,
output row_rs_stall_out,
input row_rs_vld_in,
input [63:0] row_rs_data_in,
input ll_afull_in,
output ll_write_en_out,
output [47:0] ll_address_out,
output [63:0] ll_payload_out,
input ht_rq_afull_in,
output ht_rq_read_en_out,
output [47:0] ht_rq_address_out,
output [63:0] ht_rq_data_out,
output ht_rs_afull_out,
input ht_rs_write_en_in,
input [63:0] ht_rs_data_in,
input ll_update_afull_in,
output ll_update_write_en_out,
output [47:0] ll_update_addr_out,
output [63:0] ll_update_data_out,
input ll_rs_write_en_in
);
wire rows_done_s;
wire rows_output_empty_s;
wire [63:0] rows_output_value_s;
wire rows_read_en_s;
wire build_done_s;
wire build_row_afull_s;
stream_rows ROWS (
.clk (clk),
.rst (rst),
.done (rows_done_s),
.num_rows_in (num_rows_in),
.rows_size_in (rows_size_in),
.row_start_in (row_start_in),
.row_skip_in (row_skip_in),
.output_empty_out (rows_output_empty_s),
.output_read_en_in (rows_read_en_s),
.output_value_out (rows_output_value_s),
.row_rq_stall_in (row_rq_stall_in),
.row_rq_vld_out (row_rq_vld_out),
.row_rq_vadr_out (row_rq_vadr_out),
.row_rs_stall_out (row_rs_stall_out),
.row_rs_vld_in (row_rs_vld_in),
.row_rs_data_in (row_rs_data_in)
);
assign rows_read_en_s = !rows_output_empty_s && !build_row_afull_s;
build_phase BUILD (
.clk (clk),
.rst (rst),
.done (build_done_s),
.row_start_in (row_start_in),
.row_skip_in (row_skip_in),
.hash_table_mask (hash_table_mask),
.row_afull_out (build_row_afull_s),
.row_write_en_in (rows_read_en_s),
.row_value_in (rows_output_value_s),
.ll_afull_in (ll_afull_in),
.ll_write_en_out (ll_write_en_out),
.ll_address_out (ll_address_out),
.ll_payload_out (ll_payload_out),
.ht_rq_afull_in (ht_rq_afull_in),
.ht_rq_read_en_out (ht_rq_read_en_out),
.ht_rq_address_out (ht_rq_address_out),
.ht_rq_data_out (ht_rq_data_out),
.ht_rs_afull_out (ht_rs_afull_out),
.ht_rs_write_en_in (ht_rs_write_en_in),
.ht_rs_data_in (ht_rs_data_in),
.ll_update_afull_in (ll_update_afull_in),
.ll_update_write_en_out (ll_update_write_en_out),
.ll_update_addr_out (ll_update_addr_out),
.ll_update_data_out (ll_update_data_out),
.ll_rs_write_en_in (ll_rs_write_en_in)
);
assign done = rows_done_s && build_done_s;
endmodule
|
`timescale 1ns / 1ps
module probe_phase (
input clk,
input rst,
output done,
output row_afull_out,
input row_write_en_in,
input [63:0] row_value_in,
input [63:0] row_hash_value_in,
input ht_rq_afull_in,
output ht_rq_vld_out,
output [47:0] ht_rq_address_out,
output ht_rs_afull_out,
input ht_rs_write_en_in,
input [63:0] ht_rs_data_in,
input ll_rq_0_afull_in,
output ll_rq_0_vld_out,
output [47:0] ll_rq_0_address_out,
output ll_rs_0_afull_out,
input ll_rs_0_write_en_in,
input [63:0] ll_rs_0_data_in,
input ll_rq_1_afull_in,
output ll_rq_1_vld_out,
output [47:0] ll_rq_1_address_out,
output ll_rs_1_afull_out,
input ll_rs_1_write_en_in,
input [63:0] ll_rs_1_data_in,
output output_empty_out,
input output_read_en_in,
output [63:0] output_dim_table_out,
output [63:0] output_fact_table_out
);
wire [1:0] row_fifo_afull_s;
wire row_fifo_empty_s;
wire row_fifo_read_en_s;
wire [63:0] row_fifo_value_s;
wire [63:0] row_fifo_hash_value_s;
wire [1:0] new_job_afull_s;
wire new_job_empty_s;
wire [63:0] new_job_row_value_s;
wire [63:0] new_job_row_ptr_s;
wire search_new_job_read_en_s;
wire search_done_s;
sync_2_fifo ROW_FIFO (
.clk (clk),
.rst (rst),
.afull_out (row_fifo_afull_s),
.write_en_in ({row_write_en_in, row_write_en_in}),
.data_1_in (row_value_in),
.data_0_in (row_hash_value_in),
.empty_out (row_fifo_empty_s),
.read_en_in (row_fifo_read_en_s),
.data_1_out (row_fifo_value_s),
.data_0_out (row_fifo_hash_value_s)
);
assign row_afull_out = (row_fifo_afull_s != 2'd0);
// Phase 1 -- Read the hash table to get the head pointer. This is a new
// job that can enter the engine.
assign row_fifo_read_en_s = !row_fifo_empty_s && !ht_rq_afull_in && !new_job_afull_s[1];
assign ht_rq_vld_out = row_fifo_read_en_s;
assign ht_rq_address_out = row_fifo_hash_value_s[47:0];
sync_2_fifo NEW_JOBS (
.clk (clk),
.rst (rst),
.afull_out (new_job_afull_s),
.write_en_in ({row_fifo_read_en_s, ht_rs_write_en_in}),
.data_1_in (row_fifo_value_s),
.data_0_in (ht_rs_data_in),
.empty_out (new_job_empty_s),
.read_en_in (search_new_job_read_en_s),
.data_1_out (new_job_row_value_s),
.data_0_out (new_job_row_ptr_s)
);
assign ht_rs_afull_out = new_job_afull_s[0];
wire new_job_rq_out_done_s;
outstanding_requests NEW_JOB_RQ_OUT (
.clk (clk),
.rst (rst),
.done (new_job_rq_out_done_s),
.rq_vld_in (row_fifo_read_en_s),
.rs_vld_in (ht_rs_write_en_in)
);
// Phase 2 -- Search through the linked list for a match
search_list SEARCH (
.clk (clk),
.rst (rst),
.done (search_done_s),
.new_job_empty_in (new_job_empty_s),
.new_job_read_en_out (search_new_job_read_en_s),
.new_job_value_in (new_job_row_value_s),
.new_job_pointer_in (new_job_row_ptr_s),
.ll_rq_0_afull_in (ll_rq_0_afull_in),
.ll_rq_0_vld_out (ll_rq_0_vld_out),
.ll_rq_0_address_out (ll_rq_0_address_out),
.ll_rs_0_afull_out (ll_rs_0_afull_out),
.ll_rs_0_write_en_in (ll_rs_0_write_en_in),
.ll_rs_0_data_in (ll_rs_0_data_in),
.ll_rq_1_afull_in (ll_rq_1_afull_in),
.ll_rq_1_vld_out (ll_rq_1_vld_out),
.ll_rq_1_address_out (ll_rq_1_address_out),
.ll_rs_1_afull_out (ll_rs_1_afull_out),
.ll_rs_1_write_en_in (ll_rs_1_write_en_in),
.ll_rs_1_data_in (ll_rs_1_data_in),
.output_empty_out (output_empty_out),
.output_read_en_in (output_read_en_in),
.output_dim_table_out (output_dim_table_out),
.output_fact_table_out (output_fact_table_out)
);
assign done = row_fifo_empty_s && new_job_empty_s && new_job_rq_out_done_s && search_done_s;
endmodule
|
`timescale 1 ns / 1 ps
module outstanding_requests (
input clk,
input rst,
output done,
input rq_vld_in,
input rs_vld_in
);
reg [63:0] rq_count_s;
reg [63:0] rs_count_s;
always @(posedge clk)
begin
if (rst == 1) rq_count_s <= 64'd0;
else if (rq_vld_in == 1) rq_count_s <= rq_count_s + 64'd1;
if (rst == 1) rs_count_s <= 64'd0;
else if (rs_vld_in == 1) rs_count_s <= rs_count_s + 64'd1;
end
assign done = (rq_count_s == rs_count_s);
endmodule
|
`timescale 1 ns / 1 ps
// This component will be given the number of rows, and the size of each row
// (assume each row is the same size). With this information it will request
// all rows, and filter out the column of interest.
module filter_rows (
input clk,
input rst,
output done,
input [63:0] num_rows_in,
input [63:0] row_start_in,
input [63:0] row_skip_in,
input [63:0] rows_size_in, // size is passed in bytes
input [63:0] hash_mask_in,
output output_empty_out,
input output_read_en_in,
output [63:0] output_value_out,
output [63:0] output_hash_out,
input row_rq_stall_in,
output row_rq_vld_out,
output [47:0] row_rq_vadr_out,
output row_rs_stall_out,
input row_rs_vld_in,
input [63:0] row_rs_data_in
);
wire rows_done_s;
wire rows_output_empty_s;
wire [63:0] rows_output_value_s;
wire rows_read_en_s;
wire hash_done_s;
wire hash_afull_s;
stream_rows ROWS_0 (
.clk (clk),
.rst (rst),
.done (rows_done_s),
.num_rows_in (num_rows_in),
.rows_size_in (rows_size_in), // size is passed in bytes
.row_start_in (row_start_in),
.row_skip_in (row_skip_in),
.output_empty_out (rows_output_empty_s),
.output_read_en_in (rows_read_en_s),
.output_value_out (rows_output_value_s),
.row_rq_stall_in (row_rq_stall_in),
.row_rq_vld_out (row_rq_vld_out),
.row_rq_vadr_out (row_rq_vadr_out),
.row_rs_stall_out (row_rs_stall_out),
.row_rs_vld_in (row_rs_vld_in),
.row_rs_data_in (row_rs_data_in)
);
assign rows_read_en_s = !hash_afull_s && !rows_output_empty_s;
hash_phase HASH (
.clk (clk),
.rst (rst),
.done (hash_done_s),
.hash_mask_in (hash_mask_in),
.afull_out (hash_afull_s),
.write_en_in (rows_read_en_s),
.value_in (rows_output_value_s),
.empty_out (output_empty_out),
.read_en_in (output_read_en_in),
.value_out (output_value_out),
.hash_out (output_hash_out)
);
assign done = rows_done_s && hash_done_s;
endmodule
|
`timescale 1 ns / 1 ps
module sync_2_fifo (
input clk,
input rst,
output [1:0] afull_out,
input [1:0] write_en_in,
input [63:0] data_1_in,
input [63:0] data_0_in,
output empty_out,
input read_en_in,
output [63:0] data_1_out,
output [63:0] data_0_out
);
wire [1:0] fifo_empty_s;
fifo_64x512 FIFO_0 (
.clk (clk),
.rst (rst),
.din (data_0_in),
.wr_en (write_en_in[0]),
.rd_en (read_en_in),
.dout (data_0_out),
.full (),
.empty (fifo_empty_s[0]),
.prog_full (afull_out[0])
);
fifo_64x512 FIFO_1 (
.clk (clk),
.rst (rst),
.din (data_1_in),
.wr_en (write_en_in[1]),
.rd_en (read_en_in),
.dout (data_1_out),
.full (),
.empty (fifo_empty_s[1]),
.prog_full (afull_out[1])
);
assign empty_out = (fifo_empty_s != 2'd0);
endmodule
|
`timescale 1 ns / 1 ps
// Steps for the build phase
//
// 1.) Stream in the row pointers
// 2.) Write all pointers, sequentally, to the linked-list
// 3.) Update the hash table with an atomic read (ATOM_EXCH)
// 4.) Update the linked-list based on what was returned from
// the hash table update.
module build_phase(
input clk,
input rst,
output done,
input [63:0] row_start_in,
input [63:0] row_skip_in,
input [63:0] hash_table_mask,
// During the build phase row's that pass the predicate
// evaluation will be written into our hash table structure.
// These rows will be continually streamed while there is
// room.
output row_afull_out,
input row_write_en_in,
input [63:0] row_value_in,
// Our hash table will use a linked-list for conflict
// resolution. Here we write the values to the linked list
input ll_afull_in,
output ll_write_en_out,
output [47:0] ll_address_out,
output [63:0] ll_payload_out,
// Atomic read for the hash table. This will update the head
// pointer stored in the hash table. It will also return
// the old head value so we can update the linked list.
input ht_rq_afull_in,
output ht_rq_read_en_out,
output [47:0] ht_rq_address_out,
output [63:0] ht_rq_data_out,
output ht_rs_afull_out,
input ht_rs_write_en_in,
input [63:0] ht_rs_data_in,
// Update the linked list based on the values returned by
// the hash table udpate.
input ll_update_afull_in,
output ll_update_write_en_out,
output [47:0] ll_update_addr_out,
output [63:0] ll_update_data_out,
input ll_rs_write_en_in
);
wire hash_valid_s;
wire [63:0] hash_data_out_s;
wire [63:0] hash_masked_value_s;
wire [1:0] phase_1_fifo_afull_s;
wire phase_1_fifo_empty_s;
wire [63:0] phase_1_fifo_payload_s;
wire [63:0] phase_1_fifo_hash_value_s;
wire phase_1_fifo_read_en_s;
// Phase 1 hash the value
hash_function HASH (
.clk (clk),
.rst (rst),
.valid_in (row_write_en_in),
.data_in ({32'd0, row_value_in[63:32]}),
.valid_out (hash_valid_s),
.data_out (hash_data_out_s)
);
assign hash_masked_value_s = hash_data_out_s & hash_table_mask;
sync_2_fifo PHASE_1_FIFO (
.clk (clk),
.rst (rst),
.afull_out (phase_1_fifo_afull_s),
.write_en_in ({row_write_en_in, hash_valid_s}),
.data_1_in (row_value_in),
.data_0_in (hash_masked_value_s),
.empty_out (phase_1_fifo_empty_s),
.read_en_in (phase_1_fifo_read_en_s),
.data_1_out (phase_1_fifo_payload_s),
.data_0_out (phase_1_fifo_hash_value_s)
);
assign row_afull_out = (phase_1_fifo_afull_s != 2'd0);
// Phase 2 Write to the linked list, and the hash table
reg [63:0] phase_2_addr_count_s;
wire outstanding_ht_rq_done_s;
assign phase_1_fifo_read_en_s = !phase_1_fifo_empty_s && !ll_afull_in && !ht_rq_afull_in;
always @(posedge clk)
begin
if (rst == 1'd1)
phase_2_addr_count_s <= row_start_in;
else if (phase_1_fifo_read_en_s)
phase_2_addr_count_s <= phase_2_addr_count_s + row_skip_in;
end
assign ll_write_en_out = phase_1_fifo_read_en_s;
assign ll_address_out = phase_2_addr_count_s[47:0] * 48'd2;
assign ll_payload_out = phase_1_fifo_payload_s;
assign ht_rq_read_en_out = phase_1_fifo_read_en_s;
assign ht_rq_address_out = phase_1_fifo_hash_value_s[47:0];
assign ht_rq_data_out = phase_2_addr_count_s;
outstanding_requests OUTSTANDING_HT_REQ (
.clk (clk),
.rst (rst),
.done (outstanding_ht_rq_done_s),
.rq_vld_in (phase_1_fifo_read_en_s),
.rs_vld_in (ht_rs_write_en_in)
);
// Phase 3 Update the linked list
wire phase_3_fifo_empty_s;
wire phase_3_fifo_read_en_s;
wire [63:0] phase_3_fifo_data_out_s;
reg [63:0] phase_3_addr_count_s;
wire outstanding_ll_rq_done_s;
fifo_64x512 PHASE_3_FIFO (
.clk (clk),
.rst (rst),
.din (ht_rs_data_in),
.wr_en (ht_rs_write_en_in),
.rd_en (phase_3_fifo_read_en_s),
.dout (phase_3_fifo_data_out_s),
.full (),
.empty (phase_3_fifo_empty_s),
.prog_full (ht_rs_afull_out)
);
assign phase_3_fifo_read_en_s = !phase_3_fifo_empty_s && !ll_update_afull_in;
always @(posedge clk)
begin
if (rst == 1'd1)
phase_3_addr_count_s <= row_start_in;
else if (phase_3_fifo_read_en_s)
phase_3_addr_count_s <= phase_3_addr_count_s + row_skip_in;
end
assign ll_update_write_en_out = phase_3_fifo_read_en_s;
assign ll_update_addr_out = (phase_3_addr_count_s[47:0] * 48'd2) + 48'd1;
assign ll_update_data_out = phase_3_fifo_data_out_s;
outstanding_requests OUTSTANDING_LL_REQ (
.clk (clk),
.rst (rst),
.done (outstanding_ll_rq_done_s),
.rq_vld_in (phase_3_fifo_read_en_s),
.rs_vld_in (ll_rs_write_en_in)
);
assign done = phase_1_fifo_empty_s && outstanding_ht_rq_done_s && phase_3_fifo_empty_s &&
outstanding_ll_rq_done_s;
endmodule
|
`timescale 1 ns / 1 ps
// This component will be given the number of rows, and the size of each row
// (assume each row is the same size). With this information it will request
// all rows, and filter out the column of interest.
module stream_rows (
input clk,
input rst,
output done,
input [63:0] num_rows_in,
input [63:0] rows_size_in, // size is passed in bytes
input [63:0] row_start_in, // what row should it start at
input [63:0] row_skip_in, // how many rows should be skipped when
// incrementing
output output_empty_out,
input output_read_en_in,
output [63:0] output_value_out,
input row_rq_stall_in,
output row_rq_vld_out,
output [47:0] row_rq_vadr_out,
output row_rs_stall_out,
input row_rs_vld_in,
input [63:0] row_rs_data_in
);
wire curr_row_done_s;
reg [7:0] curr_row_done_hold_s;
wire curr_row_read_en_s;
wire [63:0] curr_row_data_out_s;
wire req_fifo_afull_s;
wire req_fifo_empty_s;
wire [47:0] row_base_address_s;
wire mem_rq_vld_s;
wire [47:0] mem_rq_addr_s;
wire mem_rq_out_done_s;
wire row_fifo_empty_s;
// The counter will tell us how many rows we need to request.
generic_counter CURR_ROW (
.clk (clk),
.rst (rst),
.done (curr_row_done_s),
.start_in (row_start_in),
.end_in (num_rows_in),
.step_in (row_skip_in),
.read_in (curr_row_read_en_s),
.count_out (curr_row_data_out_s)
);
assign curr_row_read_en_s = !rst && !req_fifo_afull_s && !curr_row_done_s;
always @(posedge clk)
begin
curr_row_done_hold_s <= {curr_row_done_hold_s[6:0], curr_row_done_s};
end
wire curr_row_read_en_reg;
wire [47:0] curr_row_data_out_reg;
wire [47:0] curr_row_size_out_reg;
generic_register_chain #(
.DATA_WIDTH (1),
.CHAIN_LENGTH (6)
) RE_CHAIN (
.clk (clk),
.rst (rst),
.data_in (curr_row_read_en_s),
.data_out (curr_row_read_en_reg)
);
generic_register_chain #(
.DATA_WIDTH (48),
.CHAIN_LENGTH (5)
) DATA_CHAIN (
.clk (clk),
.rst (rst),
.data_in (curr_row_data_out_s[47:0]),
.data_out (curr_row_data_out_reg)
);
// generic_register_chain #(
// .DATA_WIDTH (48),
// .CHAIN_LENGTH (5)
// ) SIZE_CHAIN (
// .clk (clk),
// .rst (rst),
// .data_in (rows_size_in[47:0]),
// .data_out (curr_row_size_out_reg)
// );
// For each row we need to compute where it starts from. For simplicity
// I calculate the base address in Bytes. However, the memory request has
// to be word addressable (64-bits).
mul_48 ROW_BASE (
.clk (clk),
.a (curr_row_data_out_reg),
.b (rows_size_in[47:0]),
.p (row_base_address_s)
);
generic_fifo #(
.DATA_WIDTH (48),
.DATA_DEPTH (32),
.AFULL_POS (12)
) REQ_FIFO (
.clk (clk),
.rst (rst),
.afull_out (req_fifo_afull_s),
.write_en_in (curr_row_read_en_reg),
.data_in ({3'd0, row_base_address_s[47:3]}),
.empty_out (req_fifo_empty_s),
.read_en_in (mem_rq_vld_s),
.data_out (mem_rq_addr_s)
);
assign mem_rq_vld_s = !req_fifo_empty_s && !row_rq_stall_in;
outstanding_requests MEM_RQ_OUT (
.clk (clk),
.rst (rst),
.done (mem_rq_out_done_s),
.rq_vld_in (mem_rq_vld_s),
.rs_vld_in (row_rs_vld_in)
);
assign row_rq_vld_out = mem_rq_vld_s;
assign row_rq_vadr_out = mem_rq_addr_s;
generic_fifo #(
.DATA_WIDTH (64),
.DATA_DEPTH (32),
.AFULL_POS (24)
) ROW_FIFO (
.clk (clk),
.rst (rst),
.afull_out (row_rs_stall_out),
.write_en_in (row_rs_vld_in),
.data_in (row_rs_data_in),
.empty_out (row_fifo_empty_s),
.read_en_in (output_read_en_in),
.data_out (output_value_out)
);
assign output_empty_out = row_fifo_empty_s;
assign done = (curr_row_done_hold_s == 8'hFF) && req_fifo_empty_s &&
mem_rq_out_done_s && row_fifo_empty_s;
endmodule
|
`timescale 1 ns / 1 ps
module generic_counter (
input clk,
input rst,
output done,
input [63:0] start_in,
input [63:0] end_in,
input [63:0] step_in,
input read_in,
output [63:0] count_out
);
reg [63:0] counter_s;
always @(posedge clk)
begin
if (rst == 'd1)
counter_s <= start_in;
else if (read_in == 'd1)
counter_s <= counter_s + step_in;
end
assign count_out = counter_s;
assign done = counter_s >= end_in;
endmodule
|
`timescale 1 ns / 1 ps
module search_list (
input clk,
input rst,
output done,
input new_job_empty_in,
output new_job_read_en_out,
input [63:0] new_job_value_in,
input [63:0] new_job_pointer_in,
input ll_rq_0_afull_in,
output ll_rq_0_vld_out,
output [47:0] ll_rq_0_address_out,
output ll_rs_0_afull_out,
input ll_rs_0_write_en_in,
input [63:0] ll_rs_0_data_in,
input ll_rq_1_afull_in,
output ll_rq_1_vld_out,
output [47:0] ll_rq_1_address_out,
output ll_rs_1_afull_out,
input ll_rs_1_write_en_in,
input [63:0] ll_rs_1_data_in,
output output_empty_out,
input output_read_en_in,
output [63:0] output_dim_table_out,
output [63:0] output_fact_table_out
);
// Searching though the Linked list will start with new jobs. Here we look
// at the incomming jobs, and decide if the pointer location is valid. The
// only invalid pointer location is 64'hFFFF_FFFF_FFFF_FFFF.
localparam LL_IDLE = 3'd0,
LL_READ_OLD = 3'd1,
LL_READ_NEW = 3'd2;
reg [2:0] ll_rq_curr_state;
reg [2:0] ll_rq_next_state;
// reg [2:0] ll_rs_curr_state;
// reg [2:0] ll_rs_next_state;
wire new_job_valid_s;
wire new_job_ready_s;
wire ll_rq_read_en_s;
wire [47:0] ll_rq_address_s;
wire [63:0] ll_rq_value_s;
// reg [47:0] ll_addr_base_s;
// reg [47:0] ll_addr_offset_s;
//
// wire curr_job_rq_valid_s;
// reg [63:0] curr_job_rq_id_s;
// reg [63:0] curr_job_rq_value_s;
wire rq_0_out_done_s;
wire rq_1_out_done_s;
wire [2:0] out_jobs_afull_s;
wire out_jobs_empty_s;
wire out_jobs_read_en_s;
wire [63:0] out_jobs_dim_value_s;
wire [63:0] out_jobs_ptr_s;
wire [63:0] out_jobs_fact_value_s;
// reg [63:0] ll_reg_id_s;
// reg [63:0] ll_reg_val_s;
// reg [63:0] ll_reg_ptr_s;
//
wire decide_match_s;
wire decide_last_element_s;
wire [1:0] rec_jobs_afull_s;
wire rec_jobs_write_en_s;
wire rec_jobs_empty_s;
wire [63:0] rec_jobs_value_s;
wire [63:0] rec_jobs_ptr_s;
wire rec_jobs_read_en_s;
wire [1:0] match_jobs_afull_s;
wire match_jobs_write_en_s;
wire match_jobs_empty_s;
wire done_s;
reg [3:0] done_hold_s;
assign new_job_valid_s = (new_job_pointer_in != 64'hFFFF_FFFF_FFFF_FFFF);
assign new_job_ready_s = !new_job_empty_in && new_job_valid_s;
assign new_job_read_en_out = (!new_job_empty_in && !new_job_valid_s) || (ll_rq_next_state == LL_READ_NEW);
// Here is the multithreadded portion. Jobs are sent out to search though
// the linked list. The only question is if the job is new, or is recycled
// from a job that did not find a match.
always @(posedge clk)
begin
if (rst == 1'd1) ll_rq_curr_state <= LL_IDLE;
else ll_rq_curr_state <= ll_rq_next_state;
end
always @*
begin
if (ll_rq_0_afull_in || ll_rq_1_afull_in || out_jobs_afull_s[2])
ll_rq_next_state <= LL_IDLE;
else if (!rec_jobs_empty_s)
ll_rq_next_state <= LL_READ_OLD;
else if (new_job_ready_s)
ll_rq_next_state <= LL_READ_NEW;
else
ll_rq_next_state <= LL_IDLE;
end
assign ll_rq_read_en_s = (ll_rq_next_state != LL_IDLE);
assign ll_rq_address_s = (ll_rq_next_state == LL_READ_OLD)? rec_jobs_ptr_s[47:0] : new_job_pointer_in[47:0];
assign ll_rq_value_s = (ll_rq_next_state == LL_READ_OLD)? rec_jobs_value_s : new_job_value_in;
assign ll_rq_0_vld_out = ll_rq_read_en_s;
assign ll_rq_0_address_out = ll_rq_address_s * 'd2;
outstanding_requests RQ_0_OUT (
.clk (clk),
.rst (rst),
.done (rq_0_out_done_s),
.rq_vld_in (ll_rq_read_en_s),
.rs_vld_in (ll_rs_0_write_en_in)
);
assign ll_rq_1_vld_out = ll_rq_read_en_s;
assign ll_rq_1_address_out = (ll_rq_address_s * 'd2) + 48'd1;
outstanding_requests RQ_1_OUT (
.clk (clk),
.rst (rst),
.done (rq_1_out_done_s),
.rq_vld_in (ll_rq_read_en_s),
.rs_vld_in (ll_rs_1_write_en_in)
);
// A data request will keep the fact table tuple, and make 2 requests
// to the linked list. One for the dim tuple, and another for the next
// pointer. All this data has to be synchronized, then we can decide what
// to do.
sync_3_fifo OUT_JOBS (
.clk (clk),
.rst (rst),
.afull_out (out_jobs_afull_s),
.write_en_in ({ll_rq_read_en_s, ll_rs_1_write_en_in, ll_rs_0_write_en_in}),
.data_2_in (ll_rq_value_s),
.data_1_in (ll_rs_1_data_in),
.data_0_in (ll_rs_0_data_in),
.empty_out (out_jobs_empty_s),
.read_en_in (out_jobs_read_en_s),
.data_2_out (out_jobs_fact_value_s),
.data_1_out (out_jobs_ptr_s),
.data_0_out (out_jobs_dim_value_s)
);
assign ll_rs_0_afull_out = out_jobs_afull_s[0];
assign ll_rs_1_afull_out = out_jobs_afull_s[1];
assign decide_match_s = (out_jobs_dim_value_s[63:32] == out_jobs_fact_value_s[63:32]);
assign decide_last_element_s = (out_jobs_ptr_s == 64'hffff_ffff_ffff_ffff);
// If jobs do not match then we need to recycle them back, and search the
// next node in the linked list. If they do not match, and they are the
// last element then we can drop them.
assign out_jobs_read_en_s = !out_jobs_empty_s;
assign rec_jobs_write_en_s = out_jobs_read_en_s && // !decide_match_s &&
!decide_last_element_s && (rec_jobs_afull_s == 2'd0);
assign rec_jobs_read_en_s = (ll_rq_next_state == LL_READ_OLD);
sync_2_fifo REC_JOBS (
.clk (clk),
.rst (rst),
.afull_out (rec_jobs_afull_s),
.write_en_in ({rec_jobs_write_en_s, rec_jobs_write_en_s}),
.data_1_in (out_jobs_fact_value_s),
.data_0_in (out_jobs_ptr_s),
.empty_out (rec_jobs_empty_s),
.read_en_in (rec_jobs_read_en_s),
.data_1_out (rec_jobs_value_s),
.data_0_out (rec_jobs_ptr_s)
);
// If jobs do match then we output them to the next stage of the pipeline.
assign match_jobs_write_en_s = out_jobs_read_en_s && decide_match_s && (match_jobs_afull_s == 2'd0);
sync_2_fifo MATCH_JOBS (
.clk (clk),
.rst (rst),
.afull_out (match_jobs_afull_s),
.write_en_in ({match_jobs_write_en_s, match_jobs_write_en_s}),
.data_1_in (out_jobs_dim_value_s),
.data_0_in (out_jobs_fact_value_s),
.empty_out (match_jobs_empty_s),
.read_en_in (output_read_en_in),
.data_1_out (output_dim_table_out),
.data_0_out (output_fact_table_out)
);
assign output_empty_out = match_jobs_empty_s;
assign done_s = new_job_empty_in && rq_0_out_done_s && rq_1_out_done_s &&
out_jobs_empty_s && match_jobs_empty_s;
always @(posedge clk)
begin
done_hold_s <= {done_hold_s[2:0], done_s};
end
assign done = (done_hold_s == 4'hF);
//
//
// always @*
// begin
// case (ll_rq_curr_state)
// LL_IDLE:
// if (out_jobs_afull_s != 2'd0 || ll_rq_afull_in)
// ll_rq_next_state <= LL_IDLE;
// else if (!rec_jobs_empty_s)
// ll_rq_next_state <= LL_READ_OLD;
// else if (new_job_curr_state == NEW_JOB_VLD)
// ll_rq_next_state <= LL_READ_NEW;
// else
// ll_rq_next_state <= LL_IDLE;
//
// LL_READ_OLD:
// ll_rq_next_state <= LL_READ_ID;
//
// LL_READ_NEW:
// ll_rq_next_state <= LL_READ_ID;
//
// LL_READ_ID:
// ll_rq_next_state <= LL_READ_VAL;
//
// LL_READ_VAL:
// ll_rq_next_state <= LL_READ_PTR;
//
// LL_READ_PTR:
// ll_rq_next_state <= LL_IDLE;
//
// default:
// ll_rq_next_state <= LL_IDLE;
//
// endcase
// end
//
// always @*
// begin
// if (ll_rq_curr_state == LL_READ_OLD) begin
// curr_job_rq_id_s <= rec_jobs_id_s;
// curr_job_rq_value_s <= rec_jobs_val_s;
// end
// else begin // ll_rq_curr_state == LL_READ_NEW
// curr_job_rq_id_s <= new_job_id_in;
// curr_job_rq_value_s <= new_job_value_in;
// end
//
// end
//
// assign curr_job_rq_valid_s = (ll_rq_curr_state == LL_READ_OLD) || (ll_rq_curr_state == LL_READ_NEW);
// assign ll_read_en_s = (ll_rq_curr_state == LL_READ_ID) || (ll_rq_curr_state == LL_READ_VAL) ||
// (ll_rq_curr_state == LL_READ_PTR);
//
//
// // Get the base address based on if we read a new job, or an old (recycled)
// // job
// wire [47:0] old_base_ptr_s;
// wire [47:0] new_base_ptr_s;
// mul_48 OLD_BASE (
// .clk (clk),
// .a (rec_jobs_ptr_s[47:0]),
// .b (48'd3),
// .p (old_base_ptr_s)
// );
//
// mul_48 NEW_BASE (
// .clk (clk),
// .a (new_job_pointer_in[47:0]),
// .b (48'd3),
// .p (new_base_ptr_s)
// );
//
// //assign ll_addr_base_s = (ll_rq_curr_state == LL_READ_OLD)? old_base_ptr_s : new_base_ptr_s;
//// always @*
//// begin
//// ll_addr_base_s <= ll_addr_base_s;
//// case (ll_rq_curr_state)
//// LL_READ_OLD: ll_addr_base_s <= old_base_ptr_s;
//// LL_READ_NEW: ll_addr_base_s <= new_base_ptr_s;
//// endcase
//// end
//
// always @(posedge clk)
// begin
// if (ll_rq_curr_state == LL_READ_OLD)
// ll_addr_base_s <= old_base_ptr_s;
// else if (ll_rq_curr_state == LL_READ_NEW)
// ll_addr_base_s <= new_base_ptr_s;
// end
//
// reg [47:0] delete_me_0;
// always @(posedge clk)
// begin
// if (ll_rq_curr_state == LL_READ_OLD)
// delete_me_0 <= old_base_ptr_s;
// else if (ll_rq_curr_state == LL_READ_NEW)
// delete_me_0 <= new_base_ptr_s;
// end
//
//// always @(clk)
//// begin
//// if (ll_rq_curr_state == LL_READ_OLD) begin
//// ll_addr_base_s <= 48'd3 * rec_jobs_ptr_s;
//// end
//// else if (ll_rq_curr_state == LL_READ_NEW) begin
//// ll_addr_base_s <= 48'd3 * new_job_pointer_in;
//// end
//// end
//
// // offset is based on the state
// always @*
// case (ll_rq_curr_state)
// LL_READ_ID: ll_addr_offset_s <= 48'd0;
// LL_READ_VAL: ll_addr_offset_s <= 48'd1;
// LL_READ_PTR: ll_addr_offset_s <= 48'd2;
// default: ll_addr_offset_s <= 48'd0;
// endcase
//
//
// assign ll_rq_vld_out = ll_read_en_s;
// assign ll_rq_address_out = ll_addr_base_s + ll_addr_offset_s;
// assign ll_rs_afull_out = 1'd0;
//
//
// // There is too much information that needs to be kept for each job to send
// // it out with the request. We need to keep track of the Value, and the Row
// // ID. These are temporarillay stored in this FIFO until the job requests
// // are returned.
// sync_2_fifo OUT_JOBS (
// .clk (clk),
// .rst (rst),
// .afull_out (out_jobs_afull_s),
// .write_en_in ({curr_job_rq_valid_s, curr_job_rq_valid_s}),
// .data_1_in (curr_job_rq_id_s),
// .data_0_in (curr_job_rq_value_s),
// .empty_out (out_jobs_empty_s),
// .read_en_in (out_jobs_read_en_s),
// .data_1_out (out_jobs_id_s),
// .data_0_out (out_jobs_val_s)
// );
//
// outstanding_requests RQ_OUT (
// .clk (clk),
// .rst (rst),
// .done (rq_out_done_s),
// .rq_vld_in (ll_read_en_s),
// .rs_vld_in (ll_rs_write_en_in)
// );
//
// always @(posedge clk)
// begin
// if (rst == 1) ll_rs_curr_state <= LL_READ_ID;
// else ll_rs_curr_state <= ll_rs_next_state;
// end
//
//
// always @*
// begin
// case (ll_rs_curr_state)
// LL_READ_ID: if (ll_rs_write_en_in) ll_rs_next_state <= LL_READ_VAL;
// else ll_rs_next_state <= LL_READ_ID;
//
// LL_READ_VAL: if (ll_rs_write_en_in) ll_rs_next_state <= LL_READ_PTR;
// else ll_rs_next_state <= LL_READ_VAL;
//
// LL_READ_PTR: if (ll_rs_write_en_in) ll_rs_next_state <= LL_READ_ID;
// else ll_rs_next_state <= LL_READ_PTR;
//
// default: ll_rs_next_state <= LL_READ_ID;
// endcase
// end
//
// // Hash results are read from memory, and registered until all 3 data
// // points are returned.
// always @(posedge clk)
// begin
// if (ll_rs_write_en_in && ll_rs_curr_state == LL_READ_ID) ll_reg_id_s <= ll_rs_data_in;
// else if (ll_rs_write_en_in && ll_rs_curr_state == LL_READ_VAL) ll_reg_val_s <= ll_rs_data_in;
// else if (ll_rs_write_en_in && ll_rs_curr_state == LL_READ_PTR) ll_reg_ptr_s <= ll_rs_data_in;
// end
//
// always @(posedge clk)
// begin
// decide_valid_s = (ll_rs_curr_state == LL_READ_PTR) && (ll_rs_next_state == LL_READ_ID);
// end
//
// assign out_jobs_read_en_s = decide_valid_s;
// assign decide_match_s = out_jobs_val_s == ll_reg_val_s;
// assign decide_last_element_s = ll_reg_ptr_s == 64'hffff_ffff_ffff_ffff;
//
// reg didnt_write_row_s;
// always @(posedge clk)
// begin
// if (rst == 1'd1)
// didnt_write_row_s <= 1'd0;
// else if (decide_valid_s && !decide_match_s && !decide_last_element_s && rec_jobs_afull_s != 3'd0)
// didnt_write_row_s <= 1'd1;
// else if (decide_valid_s && decide_match_s && match_jobs_afull_s == 2'd0)
// didnt_write_row_s <= 1'd1;
// end
// assign error_dropped_row_out = didnt_write_row_s;
//
// // After the decision is made we will store the fifo in
// assign rec_jobs_write_en_s = decide_valid_s && !decide_match_s && !decide_last_element_s && (rec_jobs_afull_s == 3'd0);
// assign rec_jobs_read_en_s = (ll_rq_curr_state == LL_READ_OLD);
// sync_3_fifo REC_JOBS (
// .clk (clk),
// .rst (rst),
// .afull_out (rec_jobs_afull_s),
// .write_en_in ({rec_jobs_write_en_s, rec_jobs_write_en_s, rec_jobs_write_en_s}),
// .data_2_in (out_jobs_id_s),
// .data_1_in (out_jobs_val_s),
// .data_0_in (ll_reg_ptr_s),
// .empty_out (rec_jobs_empty_s),
// .read_en_in (rec_jobs_read_en_s),
// .data_2_out (rec_jobs_id_s),
// .data_1_out (rec_jobs_val_s),
// .data_0_out (rec_jobs_ptr_s)
// );
//
// assign match_jobs_write_en_s = decide_valid_s && decide_match_s && (match_jobs_afull_s == 2'd0);
// sync_2_fifo MATCH_JOBS (
// .clk (clk),
// .rst (rst),
// .afull_out (match_jobs_afull_s),
// .write_en_in ({match_jobs_write_en_s, match_jobs_write_en_s}),
// .data_1_in (out_jobs_id_s),
// .data_0_in (ll_reg_id_s),
// .empty_out (match_jobs_empty_s),
// .read_en_in (output_read_en_in),
// .data_1_out (output_dim_table_out),
// .data_0_out (output_fact_table_out)
// );
// assign output_empty_out = match_jobs_empty_s;
//
//
// wire done_s;
// assign done_s = out_jobs_empty_s && rq_out_done_s && rec_jobs_empty_s && match_jobs_empty_s;
//
// reg [7:0] done_count_s;
// always @(posedge clk)
// begin
// done_count_s <= {done_count_s[6:0], done_s};
// end
//
// assign done = (done_count_s == 8'hFF);
endmodule
|
`timescale 1 ns / 1 ps
module sync_3_fifo (
input clk,
input rst,
output [2:0] afull_out,
input [2:0] write_en_in,
input [63:0] data_2_in,
input [63:0] data_1_in,
input [63:0] data_0_in,
output empty_out,
input read_en_in,
output [63:0] data_2_out,
output [63:0] data_1_out,
output [63:0] data_0_out
);
// localparam FIFO_DEPTH = 512;
wire [2:0] fifo_empty_s;
// generic_fifo #(
// .DATA_WIDTH (64),
// .DATA_DEPTH (FIFO_DEPTH),
// .AFULL_POS (FIFO_DEPTH-12)
// ) FIFO_0 (
// .clk (clk),
// .rst (rst),
// .afull_out (afull_out[0]),
// .write_en_in (write_en_in[0]),
// .data_in (data_0_in),
// .empty_out (fifo_empty_s[0]),
// .read_en_in (read_en_in),
// .data_out (data_0_out)
// );
// generic_fifo #(
// .DATA_WIDTH (64),
// .DATA_DEPTH (FIFO_DEPTH),
// .AFULL_POS (FIFO_DEPTH-12)
// ) FIFO_1 (
// .clk (clk),
// .rst (rst),
// .afull_out (afull_out[1]),
// .write_en_in (write_en_in[1]),
// .data_in (data_1_in),
// .empty_out (fifo_empty_s[1]),
// .read_en_in (read_en_in),
// .data_out (data_1_out)
// );
// generic_fifo #(
// .DATA_WIDTH (64),
// .DATA_DEPTH (FIFO_DEPTH),
// .AFULL_POS (FIFO_DEPTH-12)
// ) FIFO_2 (
// .clk (clk),
// .rst (rst),
// .afull_out (afull_out[2]),
// .write_en_in (write_en_in[2]),
// .data_in (data_2_in),
// .empty_out (fifo_empty_s[2]),
// .read_en_in (read_en_in),
// .data_out (data_2_out)
// );
fifo_64x512 FIFO_0 (
.clk (clk),
.rst (rst),
.din (data_0_in),
.wr_en (write_en_in[0]),
.rd_en (read_en_in),
.dout (data_0_out),
.full (),
.empty (fifo_empty_s[0]),
.prog_full (afull_out[0])
);
fifo_64x512 FIFO_1 (
.clk (clk),
.rst (rst),
.din (data_1_in),
.wr_en (write_en_in[1]),
.rd_en (read_en_in),
.dout (data_1_out),
.full (),
.empty (fifo_empty_s[1]),
.prog_full (afull_out[1])
);
fifo_64x512 FIFO_2 (
.clk (clk),
.rst (rst),
.din (data_2_in),
.wr_en (write_en_in[2]),
.rd_en (read_en_in),
.dout (data_2_out),
.full (),
.empty (fifo_empty_s[2]),
.prog_full (afull_out[2])
);
assign empty_out = (fifo_empty_s != 3'd0);
endmodule
|
`timescale 1 ns / 1 ps
module sync_2_fifo (
input clk,
input rst,
output [1:0] afull_out,
input [1:0] write_en_in,
input [63:0] data_1_in,
input [63:0] data_0_in,
output empty_out,
input read_en_in,
output [63:0] data_1_out,
output [63:0] data_0_out
);
wire [1:0] fifo_empty_s;
fifo_64x512 FIFO_0 (
.clk (clk),
.rst (rst),
.din (data_0_in),
.wr_en (write_en_in[0]),
.rd_en (read_en_in),
.dout (data_0_out),
.full (),
.empty (fifo_empty_s[0]),
.prog_full (afull_out[0])
);
fifo_64x512 FIFO_1 (
.clk (clk),
.rst (rst),
.din (data_1_in),
.wr_en (write_en_in[1]),
.rd_en (read_en_in),
.dout (data_1_out),
.full (),
.empty (fifo_empty_s[1]),
.prog_full (afull_out[1])
);
assign empty_out = (fifo_empty_s != 2'd0);
endmodule
|
`timescale 1 ns / 1 ps
module generic_counter (
input clk,
input rst,
output done,
input [63:0] start_in,
input [63:0] end_in,
input [63:0] step_in,
input read_in,
output [63:0] count_out
);
reg [63:0] counter_s;
always @(posedge clk)
begin
if (rst == 1'd1)
counter_s <= start_in;
else if (read_in == 1'd1)
counter_s <= counter_s + step_in;
end
assign count_out = counter_s;
assign done = counter_s >= end_in;
endmodule
|
`timescale 1 ns / 1 ps
module outstanding_requests (
input clk,
input rst,
output done,
input rq_vld_in,
input rs_vld_in
);
reg [63:0] rq_count_s;
reg [63:0] rs_count_s;
always @(posedge clk)
begin
if (rst == 1) rq_count_s <= 64'd0;
else if (rq_vld_in == 1) rq_count_s <= rq_count_s + 64'd1;
if (rst == 1) rs_count_s <= 64'd0;
else if (rs_vld_in == 1) rs_count_s <= rs_count_s + 64'd1;
end
assign done = (rq_count_s == rs_count_s);
endmodule
|
`timescale 1 ns / 1 ps
module hash_function (
input clk,
input rst,
input valid_in,
input [63:0] data_in,
output valid_out,
output [63:0] data_out
);
wire [47:0] prime_0_s = 48'h00001E698F65;
wire [47:0] prime_1_s = 48'h000024820C8D;
wire [47:0] data_in_0_s;
wire [47:0] data_in_1_s;
wire [47:0] mul_0_s;
wire [47:0] mul_1_s;
wire [47:0] add_s;
reg valid_out_s;
assign data_in_0_s = {16'd0, data_in[63:32]};
assign data_in_1_s = {16'd0, data_in[31:0]};
mul_48 MUL_0 (
.clk (clk),
.a (prime_0_s),
.b (data_in_0_s),
.p (mul_0_s)
);
mul_48 MUL_1 (
.clk (clk),
.a (prime_1_s),
.b (data_in_1_s),
.p (mul_1_s)
);
assign add_s = mul_0_s + mul_1_s;
always @(posedge clk)
begin
if (rst == 1'd1) begin
valid_out_s <= 1'd0;
end else begin
valid_out_s <= valid_in;
end
end
assign valid_out = valid_out_s;
assign data_out = {33'd0, add_s[30:0]};
endmodule
|
`timescale 1 ns / 1 ps
module engine (
input clk,
input rst,
output done,
input [63:0] num_rows_in,
input [63:0] row_start_in,
input [63:0] row_skip_in,
input [63:0] rows_size_in, // size is passed in bytes
input [63:0] hash_mask_in,
input row_rq_stall_in,
output row_rq_vld_out,
output [47:0] row_rq_vadr_out,
output row_rs_stall_out,
input row_rs_vld_in,
input [63:0] row_rs_data_in,
input ht_rq_afull_in,
output ht_rq_vld_out,
output [47:0] ht_rq_address_out,
output ht_rs_afull_out,
input ht_rs_write_en_in,
input [63:0] ht_rs_data_in,
input ll_rq_0_afull_in,
output ll_rq_0_vld_out,
output [47:0] ll_rq_0_address_out,
output ll_rs_0_afull_out,
input ll_rs_0_write_en_in,
input [63:0] ll_rs_0_data_in,
input ll_rq_1_afull_in,
output ll_rq_1_vld_out,
output [47:0] ll_rq_1_address_out,
output ll_rs_1_afull_out,
input ll_rs_1_write_en_in,
input [63:0] ll_rs_1_data_in,
output output_empty_out,
input output_read_en_in,
output [63:0] output_dim_table_out,
output [63:0] output_fact_table_out
);
wire stream_done_s;
wire stream_empty_s;
wire stream_read_en_s;
wire [63:0] stream_value_s;
wire [63:0] stream_hash_s;
wire [47:0] stream_rq_vadr_s;
wire probe_phase_done_s;
wire probe_phase_afull_s;
wire [47:0] probe_phase_ht_rq_addr_s;
wire [47:0] probe_phase_ll_rq_addr_s;
wire probe_phase_output_empty_s;
wire probe_phase_output_read_en_s;
wire [63:0] probe_phase_output_dim_table_s;
wire [63:0] probe_phase_output_fact_table_s;
filter_rows STREAM (
.clk (clk),
.rst (rst),
.done (stream_done_s),
.num_rows_in (num_rows_in),
.row_start_in (row_start_in),
.row_skip_in (row_skip_in),
.rows_size_in (rows_size_in),
.hash_mask_in (hash_mask_in),
.output_empty_out (stream_empty_s),
.output_read_en_in (stream_read_en_s),
.output_value_out (stream_value_s),
.output_hash_out (stream_hash_s),
.row_rq_stall_in (row_rq_stall_in),
.row_rq_vld_out (row_rq_vld_out),
.row_rq_vadr_out (row_rq_vadr_out),
.row_rs_stall_out (row_rs_stall_out),
.row_rs_vld_in (row_rs_vld_in),
.row_rs_data_in (row_rs_data_in)
);
assign stream_read_en_s = !stream_empty_s && !probe_phase_afull_s;
probe_phase PROBE_PHASE (
.clk (clk),
.rst (rst),
.done (probe_phase_done_s),
.row_afull_out (probe_phase_afull_s),
.row_write_en_in (stream_read_en_s),
.row_value_in (stream_value_s),
.row_hash_value_in (stream_hash_s),
.ht_rq_afull_in (ht_rq_afull_in),
.ht_rq_vld_out (ht_rq_vld_out),
.ht_rq_address_out (ht_rq_address_out),
.ht_rs_afull_out (ht_rs_afull_out),
.ht_rs_write_en_in (ht_rs_write_en_in),
.ht_rs_data_in (ht_rs_data_in),
.ll_rq_0_afull_in (ll_rq_0_afull_in),
.ll_rq_0_vld_out (ll_rq_0_vld_out),
.ll_rq_0_address_out (ll_rq_0_address_out),
.ll_rs_0_afull_out (ll_rs_0_afull_out),
.ll_rs_0_write_en_in (ll_rs_0_write_en_in),
.ll_rs_0_data_in (ll_rs_0_data_in),
.ll_rq_1_afull_in (ll_rq_1_afull_in),
.ll_rq_1_vld_out (ll_rq_1_vld_out),
.ll_rq_1_address_out (ll_rq_1_address_out),
.ll_rs_1_afull_out (ll_rs_1_afull_out),
.ll_rs_1_write_en_in (ll_rs_1_write_en_in),
.ll_rs_1_data_in (ll_rs_1_data_in),
.output_empty_out (output_empty_out),
.output_read_en_in (output_read_en_in),
.output_dim_table_out (output_dim_table_out),
.output_fact_table_out (output_fact_table_out)
);
assign done = stream_done_s && probe_phase_done_s;
endmodule
|
`timescale 1 ns / 1 ps
module hash_function (
input clk,
input rst,
input valid_in,
input [63:0] data_in,
output valid_out,
output [63:0] data_out
);
wire [47:0] prime_0_s = 48'h00001E698F65;
wire [47:0] prime_1_s = 48'h000024820C8D;
wire [47:0] data_in_0_s;
wire [47:0] data_in_1_s;
wire [47:0] mul_0_s;
wire [47:0] mul_1_s;
wire [47:0] add_s;
reg valid_out_s;
assign data_in_0_s = {16'd0, data_in[63:32]};
assign data_in_1_s = {16'd0, data_in[31:0]};
mul_48 MUL_0 (
.clk (clk),
.a (prime_0_s),
.b (data_in_0_s),
.p (mul_0_s)
);
mul_48 MUL_1 (
.clk (clk),
.a (prime_1_s),
.b (data_in_1_s),
.p (mul_1_s)
);
assign add_s = mul_0_s + mul_1_s;
always @(posedge clk)
begin
if (rst == 1'd1) begin
valid_out_s <= 1'd0;
end else begin
valid_out_s <= valid_in;
end
end
assign valid_out = valid_out_s;
assign data_out = {33'd0, add_s[30:0]};
endmodule
|
`timescale 1 ns / 1 ps
// This component will be given the number of rows, and the size of each row
// (assume each row is the same size). With this information it will request
// all rows, and filter out the column of interest.
module stream_rows (
input clk,
input rst,
output done,
input [63:0] num_rows_in,
input [63:0] rows_size_in, // size is passed in bytes
input [63:0] row_start_in, // what row should it start at
input [63:0] row_skip_in, // how many rows should be skipped when
// incrementing
output output_empty_out,
input output_read_en_in,
output [63:0] output_value_out,
input row_rq_stall_in,
output row_rq_vld_out,
output [47:0] row_rq_vadr_out,
output row_rs_stall_out,
input row_rs_vld_in,
input [63:0] row_rs_data_in
);
wire curr_row_done_s;
reg [7:0] curr_row_done_hold_s;
wire curr_row_read_en_s;
wire [63:0] curr_row_data_out_s;
wire req_fifo_afull_s;
wire req_fifo_empty_s;
wire [47:0] row_base_address_s;
wire mem_rq_vld_s;
wire [47:0] mem_rq_addr_s;
wire mem_rq_out_done_s;
wire row_fifo_empty_s;
// The counter will tell us how many rows we need to request.
generic_counter CURR_ROW (
.clk (clk),
.rst (rst),
.done (curr_row_done_s),
.start_in (row_start_in),
.end_in (num_rows_in),
.step_in (row_skip_in),
.read_in (curr_row_read_en_s),
.count_out (curr_row_data_out_s)
);
assign curr_row_read_en_s = !rst && !req_fifo_afull_s && !curr_row_done_s;
always @(posedge clk)
begin
curr_row_done_hold_s <= {curr_row_done_hold_s[6:0], curr_row_done_s};
end
wire curr_row_read_en_reg;
wire [47:0] curr_row_data_out_reg;
wire [47:0] curr_row_size_out_reg;
generic_register_chain #(
.DATA_WIDTH (1),
.CHAIN_LENGTH (6)
) RE_CHAIN (
.clk (clk),
.rst (rst),
.data_in (curr_row_read_en_s),
.data_out (curr_row_read_en_reg)
);
generic_register_chain #(
.DATA_WIDTH (48),
.CHAIN_LENGTH (5)
) DATA_CHAIN (
.clk (clk),
.rst (rst),
.data_in (curr_row_data_out_s[47:0]),
.data_out (curr_row_data_out_reg)
);
// generic_register_chain #(
// .DATA_WIDTH (48),
// .CHAIN_LENGTH (5)
// ) SIZE_CHAIN (
// .clk (clk),
// .rst (rst),
// .data_in (rows_size_in[47:0]),
// .data_out (curr_row_size_out_reg)
// );
// For each row we need to compute where it starts from. For simplicity
// I calculate the base address in Bytes. However, the memory request has
// to be word addressable (64-bits).
mul_48 ROW_BASE (
.clk (clk),
.a (curr_row_data_out_reg),
.b (rows_size_in[47:0]),
.p (row_base_address_s)
);
generic_fifo #(
.DATA_WIDTH (48),
.DATA_DEPTH (32),
.AFULL_POS (12)
) REQ_FIFO (
.clk (clk),
.rst (rst),
.afull_out (req_fifo_afull_s),
.write_en_in (curr_row_read_en_reg),
.data_in ({3'd0, row_base_address_s[47:3]}),
.empty_out (req_fifo_empty_s),
.read_en_in (mem_rq_vld_s),
.data_out (mem_rq_addr_s)
);
assign mem_rq_vld_s = !req_fifo_empty_s && !row_rq_stall_in;
outstanding_requests MEM_RQ_OUT (
.clk (clk),
.rst (rst),
.done (mem_rq_out_done_s),
.rq_vld_in (mem_rq_vld_s),
.rs_vld_in (row_rs_vld_in)
);
assign row_rq_vld_out = mem_rq_vld_s;
assign row_rq_vadr_out = mem_rq_addr_s;
generic_fifo #(
.DATA_WIDTH (64),
.DATA_DEPTH (32),
.AFULL_POS (24)
) ROW_FIFO (
.clk (clk),
.rst (rst),
.afull_out (row_rs_stall_out),
.write_en_in (row_rs_vld_in),
.data_in (row_rs_data_in),
.empty_out (row_fifo_empty_s),
.read_en_in (output_read_en_in),
.data_out (output_value_out)
);
assign output_empty_out = row_fifo_empty_s;
assign done = (curr_row_done_hold_s == 8'hFF) && req_fifo_empty_s &&
mem_rq_out_done_s && row_fifo_empty_s;
endmodule
|
//==================================================================================================
// Filename : vendingmachine.v
// Created On : 2015-05-05 08:17:43
// Last Modified : 2015-05-07 19:37:31
// Author : Danny Dutton
// Class : ECE3544
// Project : Project 4
// Description : Vending machine state machine. The FSM increments the count of the change
// inside the vending machine until reaching 65c. Then a product will dispense and
// change given, starting from dimes to nickels, if needed.
//
//==================================================================================================
module vendingmachine(clock, enable, reset, coin, mode, quarter_counter, dime_counter, nickel_counter, dimenickelLEDon, dimeLEDon, nickelLEDon, vendLEDon);
\tinput clock;\t\t\t// Clock used for timing the LEDs
\tinput enable;\t\t\t// KEY[1] in the top module, serves as a user controlled clock pulse
\tinput reset;\t\t\t// KEY[0] in top module, resets values
\tinput[1:0] coin;\t\t// SW[1:0] sets which coin is to be inserted on enable high
\tinput mode;\t\t\t\t// SW[2] sets if vending machine should be in normal mode (1) or maintenance mode (0).
\t\t\t\t\t\t\t// It sets if we wish to increment "count" or not.
\toutput reg [7:0] quarter_counter, dime_counter, nickel_counter;\t // Total numbers of each coin in the machine to be used as change
\toutput reg dimeLEDon, nickelLEDon, vendLEDon;\t\t\t\t\t\t\t// Controls when LEDs should light up for returning coins or vending item
\toutput dimenickelLEDon;
\treg [7:0] count; \t\t// Total in cents of change inserted when trying to make a purchase
\treg [27:0] LEDcounter;\t\t\t\t\t// Counter for how long an LED is on
\treg nickelLED, nickelLED2, nickelLED3, nickelLED4, dimeLED, dimeLED2, vendLED, LEDon;\t// Current state of an LED;
\treg countreset;
\treg nickelinc, dimeinc, quarterinc;\t\t// Flags for incrementing
\treg dispense;
\treg venddec, nickeldec, nickeldec2, nickeldec3, nickeldec4, dimedec, dimedec2;\t// Flags for decrementing nickels and dimes
\t
\t// Nickel counter
\talways @(posedge clock or negedge reset) begin
\t\tif(!reset)
\t\t\tnickel_counter <= 8\'d0;
\t\telse if(nickelinc)
\t\t\tnickel_counter <= nickel_counter + 8\'d1;
\t\telse if(nickeldec)
\t\t\tnickel_counter <= nickel_counter - 8\'d1;
\t\telse if(nickeldec2)
\t\t\tnickel_counter <= nickel_counter - 8\'d2;
\t\telse if(nickeldec3)
\t\t\tnickel_counter <= nickel_counter - 8\'d3;
\t\telse if(nickeldec4)
\t\t\tnickel_counter <= nickel_counter - 8\'d4;
\t\telse
\t\t\tnickel_counter <= nickel_counter;
\tend
\t// Dime counter
\talways @(posedge clock or negedge reset) begin
\t\tif(!reset)\t\t\tdime_counter <= 8\'d0;
\t\telse if(dimeinc)
\t\t\tdime_counter <= dime_counter + 8\'d1;
\t\telse if(dimedec)
\t\t\tdime_counter <= dime_counter - 8\'d1;
\t\telse if(dimedec2)
\t\t\tdime_counter <= dime_counter - 8\'d2;
\t\telse
\t\t\tdime_counter <= dime_counter;
\tend
\t// Quarter counter
\talways @(posedge clock or negedge reset) begin
\t\tif(!reset)
\t\t\tquarter_counter <= 8\'d0;
\t\telse if(quarterinc)
\t\t\tquarter_counter <= quarter_counter + 8\'d1;
\t\telse
\t\t\tquarter_counter <= quarter_counter;
\tend
\t// Change counter
\talways @(posedge clock or negedge reset) begin
\t\tif(!reset)
\t\t\tcount <= 8\'d0;
\t\telse if(countreset)
\t\t\tcount <= 8\'d0;
\t\telse if(nickelinc && mode)
\t\t\tcount <= count + 8\'d5;
\t\telse if(dimeinc && mode)
\t\t\tcount <= count + 8\'d10;
\t\telse if(quarterinc && mode)
\t\t\tcount <= count + 8\'d25;
\t\telse if(venddec) begin
\t\t\tif(dimedec && nickeldec)
\t\t\t\tcount <= count - 8\'d75;
\t\t\telse if(dimedec && nickeldec2)
\t\t\t\tcount <= count - 8\'d80;
\t\t\telse if(nickeldec)
\t\t\t\tcount <= count - 8\'d65;
\t\t\telse if(nickeldec2)
\t\t\t\tcount <= count - 8\'d70;
\t\t\telse if(dimedec)
\t\t\t\tcount <= count - 8\'d70;
\t\t\telse if(nickeldec3)
\t\t\t\tcount <= count - 8\'d75;
\t\t\telse if(dimedec2)
\t\t\t\tcount <= count - 8\'d80;
\t\t\telse if(nickeldec4)
\t\t\t\tcount <= count - 8\'d80;
\t\t\telse begin
\t\t\t\tcount <= count - 8\'d60;
\t\t\tend
\t\tend
\t\telse
\t\t\tcount <= count;
\tend
\t// Deposit
\talways @(posedge clock) begin
\t\t// Coin inserted, increment counters
\t\tif(enable) begin
\t\t\tcase(coin)
\t\t\t\t// Nickel
\t\t\t\t2\'b01: begin
\t\t\t\t\tnickelinc <= 1\'b1;
\t\t\t\tend
\t\t\t\t// Dime
\t\t\t\t2\'b10: begin
\t\t\t\t\tdimeinc <= 1\'b1;
\t\t\t\tend
\t\t\t\t// Quarter
\t\t\t\t2\'b11: begin
\t\t\t\t\tquarterinc <= 1\'b1;
\t\t\t\tend
\t\t\t\t// SW[1:0] = 2\'b00 or something else so dont do anything
\t\t\t\tdefault: begin
\t\t\t\t\tnickelinc <= 1\'b0;
\t\t\t\t\tdimeinc <= 1\'b0;
\t\t\t\t\tquarterinc <= 1\'b0;
\t\t\t\tend
\t\t\tendcase
\t\tend
\t\t// No coins inserted
\t\telse begin
\t\t\tnickelinc <= 1\'b0;
\t\t\tdimeinc <= 1\'b0;
\t\t\tquarterinc <= 1\'b0;
\t\tend
\t\tif(count > 60) begin
\t\t\tdispense <= 1;
\t\tend
\t\telse begin
\t\t\tdispense <= 0;
\t\tend
\tend
\t// Dispense when count >= 60. Set venddec and dime/nickel/2/3dec if we need to
\talways @(dispense) begin
\t\t// Need to vend product
\t\tif(count == 60) begin
\t\t\tvenddec <= 1\'b1;
\t\t\tdimedec <= 1\'b0;
\t\t\tdimedec2 <= 1\'b0;
\t\t\tnickeldec <= 1\'b0;
\t\t\tnickeldec2 <= 1\'b0;
\t\t\tnickeldec3 <= 1\'b0;
\t\t\tnickeldec4 <= 1\'b0;
\t\t\tdispense <= 0;
\t\tend
\t\t// Do we need to return coins as well?
\t\telse if(count > 60) begin
\t\t\tvenddec <= 1\'b1;
\t\t\tdispense <= 0;
\t\t\t// Need to only return a nickel if we have any
\t\t\tif((count == 65) && (nickel_counter > 0))
\t\t\t\tnickeldec <= 1\'b1;
\t\t\t// Need to return 10
\t\t\tif(count == 70) begin
\t\t\t\t// Return a dime if we have any
\t\t\t\tif(dime_counter > 0)
\t\t\t\t\tdimedec <= 1\'b1;
\t\t\t\t// Return 2 nickels instead
\t\t\t\telse if(nickel_counter > 1)
\t\t\t\t\tnickeldec2 <= 1\'b1;
\t\t\t\t// Return 1 nickel since thats all we have
\t\t\t\telse if(nickel_counter == 1)
\t\t\t\t\tnickeldec <= 1\'b1;
\t\t\tend
\t\t\t// Need to return 15
\t\t\tif(count == 75) begin
\t\t\t\t// Return a dime if we have one
\t\t\t\tif(dime_counter > 0) begin
\t\t\t\t\tdimedec <= 1\'b1;
\t\t\t\t\t// Return a nickel too if we have one
\t\t\t\t\tif(nickel_counter > 0)
\t\t\t\t\t\tnickeldec <= 1\'b1;
\t\t\t\tend
\t\t\t\t// No dimes so give back 3 nickels
\t\t\t\telse if(nickel_counter > 2)
\t\t\t\t\tnickeldec3 <= 1\'b1;
\t\t\t\t// Not enough nickels so give 2
\t\t\t\telse if(nickel_counter > 1)
\t\t\t\t\tnickeldec2 <= 1\'b1;
\t\t\t\t// Not enough nickels so give 1
\t\t\t\telse if(nickel_counter == 1)
\t\t\t\t\tnickeldec <= 1\'b1;
\t\t\tend
\t\t\t// Need to return 20
\t\t\tif(count == 80) begin
\t\t\t\t// Return 2 dimes if we have some
\t\t\t\tif(dime_counter > 1)
\t\t\t\t\tdimedec2 <= 1\'b1;
\t\t\t\t// Not enough dimes so give back 1 dime and and 2 nickels
\t\t\t\telse if(dime_counter > 0) begin
\t\t\t\t\tdimedec <= 1\'b1;
\t\t\t\t\t// Give 2 nickels if we have enough
\t\t\t\t\tif(nickel_counter > 1)
\t\t\t\t\t\tnickeldec2 <= 1\'b1;
\t\t\t\t\t// Give one nickel if we dont have enough
\t\t\t\t\telse if(nickel_counter > 0)
\t\t\t\t\t\tnickeldec <= 1\'b1;
\t\t\t\tend
\t\t\t\t// Not enough dimes so give 4 nickels
\t\t\t\telse if(nickel_counter > 1)
\t\t\t\t\tnickeldec4 <= 1\'b1;
\t\t\t\t// Not enough nickels so give 3
\t\t\t\telse if(nickel_counter > 1)
\t\t\t\t\tnickeldec2 <= 1\'b1;
\t\t\t\t// Not enough nickels so give 1
\t\t\t\telse if(nickel_counter == 1)
\t\t\t\t\tnickeldec <= 1\'b1;
\t\t\tend
\t\tend
\t\telse begin
\t\t\tdimedec <= 1\'b0;
\t\t\tdimedec2 <= 1\'b0;
\t\t\tnickeldec <= 1\'b0;
\t\t\tnickeldec2 <= 1\'b0;
\t\t\tnickeldec3 <= 1\'b0;
\t\t\tnickeldec4 <= 1\'b0;
\t\t\tvenddec <= 1\'b0;
\t\tend
\tend
\t// LEDs
\talways @(posedge clock) begin
\t\t// Select correct LED sequences for dispensing product and coins
\t\tif(nickeldec || nickeldec2 || nickeldec3 || nickeldec4 || dimedec || dimedec2 || venddec) begin
\t\t\tif(nickeldec || nickeldec2 || nickeldec3 || nickeldec4) begin
\t\t\t\tif(nickeldec)
\t\t\t\t\tnickelLED <= 1;
\t\t\t\telse if(nickeldec2)
\t\t\t\t\tnickelLED2 <= 1;
\t\t\t\telse if(nickeldec3)
\t\t\t\t\tnickelLED3 <= 1;
\t\t\t\telse if(nickeldec4)
\t\t\t\t\tnickelLED4 <= 1;
\t\t\tend
\t\t\t
\t\t\tif(dimedec)
\t\t\t\tdimeLED <= 1;
\t\t\t
\t\t\tif(dimedec2)
\t\t\t\tdimeLED2 <= 1;
\t\t\t
\t\t\tif(venddec)
\t\t\t\tvendLED <= 1;
\t\t\t// Need to reset the count since we might have extra leftover if we didnt have enough change to give back.
\t\t\t// This needs to be done here since we cant reset the count to zero while we are subtracting from it.
\t\t\tcountreset <= 1;
\t\tend
\t\t// // Otherwise, if LED lock is on, keep current state of LEDs
\t\t// // If the lock is on, keep the LEDs on that should be
\t\telse if(LEDon) begin
\t\t\tnickelLED <= nickelLED;
\t\t\tnickelLED2 <= nickelLED2;
\t\t\tnickelLED3 <= nickelLED3;
\t\t\tnickelLED4 <= nickelLED4;
\t\t\tdimeLED <= dimeLED;
\t\t\tvendLED <= vendLED;
\t\t\tLEDcounter <= LEDcounter + 28\'d1;
\t\tend
\t\telse begin
\t\t\tnickelLED <= 0;
\t\t\tnickelLED2 <= 0;
\t\t\tnickelLED3 <= 0;
\t\t\tnickelLED4 <= 0;
\t\t\tdimeLED <= 0;
\t\t\tdimeLED2 <= 0;
\t\t\tvendLED <= 0;
\t\t\tLEDcounter = 28\'d0;
\t\t\tcountreset <= 0;
\t\tend
\tend
\t// LED output machine
\talways @(nickelLED or nickelLED2 or nickelLED3 or nickelLED4 or dimeLED or dimeLED2 or vendLED or LEDcounter or LEDon) begin
\t\t// Turn on the lock so we can keep this always block running until we dont need it anymore
\t\tLEDon = 1;
\t\t// Need to dispense product and a dime
\t\tif(dimeLED2) begin
\t\t\tvendLEDon = 1;
\t\t\tif(LEDcounter >= 50000000) begin
\t\t\t\tvendLEDon = 0;
\t\t\t\tdimeLEDon = 1;
\t\t\t\tif(LEDcounter >= 150000000) begin
\t\t\t\t\tdimeLEDon = 0;
\t\t\t\t\tLEDon = 0;
\t\t\t\tend
\t\t\tend
\t\tend
\t\t// Need to dispense product, dime, then 2 nickels
\t\telse if(dimeLED && nickelLED2) begin
\t\t\tvendLEDon = 1;
\t\t\tif(LEDcounter >= 50000000) begin
\t\t\t\tvendLEDon = 0;
\t\t\t\tdimeLEDon = 1;
\t\t\t\tif(LEDcounter >= 100000000) begin
\t\t\t\t\tdimeLEDon = 0;
\t\t\t\t\tnickelLEDon = 1;
\t\t\t\t\tif(LEDcounter >= 200000000) begin
\t\t\t\t\t\tnickelLEDon = 0;
\t\t\t\t\t\tLEDon = 0;
\t\t\t\t\tend
\t\t\t\tend
\t\t\tend
\t\tend
\t\t// Need to dispense product, dime, then nickel
\t\telse if(dimeLED && nickelLED) begin
\t\t\tvendLEDon = 1;
\t\t\tif(LEDcounter >= 50000000) begin
\t\t\t\tvendLEDon = 0;
\t\t\t\tdimeLEDon = 1;
\t\t\t\tif(LEDcounter >= 100000000) begin
\t\t\t\t\tdimeLEDon = 0;
\t\t\t\t\tnickelLEDon = 1;
\t\t\t\t\tif(LEDcounter >= 150000000) begin
\t\t\t\t\t\tnickelLEDon = 0;
\t\t\t\t\t\tLEDon = 0;
\t\t\t\t\tend
\t\t\t\tend
\t\t\tend
\t\tend
\t\t// Need to dispense product and a dime
\t\telse if(dimeLED) begin
\t\t\tvendLEDon = 1;
\t\t\tif(LEDcounter >= 50000000) begin
\t\t\t\tvendLEDon = 0;
\t\t\t\tdimeLEDon = 1;
\t\t\t\tif(LEDcounter >= 100000000) begin
\t\t\t\t\tdimeLEDon = 0;
\t\t\t\t\tLEDon = 0;
\t\t\t\tend
\t\t\tend
\t\tend
\t\t// Need to dispense product and 4 nickels
\t\telse if(nickelLED4) begin
\t\t\tvendLEDon = 1;
\t\t\tif(LEDcounter >= 50000000) begin
\t\t\t\tvendLEDon = 0;
\t\t\t\tnickelLEDon = 1;
\t\t\t\tif(LEDcounter >= 250000000) begin
\t\t\t\t\tnickelLEDon = 0;
\t\t\t\t\tLEDon = 0;
\t\t\t\tend
\t\t\tend
\t\tend
\t\t// Need to dispense product and 3 nickels
\t\telse if(nickelLED3) begin
\t\t\tvendLEDon = 1;
\t\t\tif(LEDcounter >= 50000000) begin
\t\t\t\tvendLEDon = 0;
\t\t\t\tnickelLEDon = 1;
\t\t\t\tif(LEDcounter >= 200000000) begin
\t\t\t\t\tnickelLEDon = 0;
\t\t\t\t\tLEDon = 0;
\t\t\t\tend
\t\t\tend
\t\tend
\t\t// Need to dispense product and 2 nickels
\t\telse if(nickelLED2) begin
\t\t\tvendLEDon = 1;
\t\t\tif(LEDcounter >= 50000000) begin
\t\t\t\tvendLEDon = 0;
\t\t\t\tnickelLEDon = 1;
\t\t\t\tif(LEDcounter == 150000000) begin
\t\t\t\t\tnickelLEDon\t= 0;
\t\t\t\t\tLEDon = 0;
\t\t\t\tend
\t\t\tend
\t\tend
\t\t// Need to dispense product and a nickel
\t\telse if(nickelLED) begin
\t\t\tvendLEDon = 1;
\t\t\tif(LEDcounter >= 50000000) begin
\t\t\t\tvendLEDon = 0;
\t\t\t\tnickelLEDon = 1;
\t\t\t\tif(LEDcounter >= 100000000) begin
\t\t\t\t\tnickelLEDon = 0;
\t\t\t\t\tLEDon = 0;
\t\t\t\tend
\t\t\tend
\t\tend
\t\t// Need to dispense product only
\t\telse if(vendLED) begin
\t\t\tvendLEDon = 1;
\t\t\tif(LEDcounter >= 50000000) begin
\t\t\t\tvendLEDon = 0;
\t\t\t\tLEDon = 0;
\t\t\tend
\t\tend
\t\telse begin
\t\t\tnickelLEDon = 0;
\t\t\tdimeLEDon = 0;
\t\t\tvendLEDon = 0;
\t\t\tLEDon = 0;
\t\tend
\tend
\t// Continuous assignment for the dime/nickel count LED
\tassign dimenickelLEDon = (dime_counter == 0) && (nickel_counter == 0);
endmodule
|
// Filename: keypressed.v
// Author: Tom Martin
// Date: 10/24/2013
// Version: 1
// Description: This FSM generates an enable pulse that lasts for one clock period each time the pushbutton is pressed
// and released.
// Updated on 18 March 2013 by J.S. Thweatt
// Commented to describe state machine structure
module keypressed(clock, reset, enable_in, enable_out);
\tinput clock;\t\t\t// The on-board clock, default 50 MHz
\tinput\treset;\t\t\t// Reset is active low. Should be connected to pushbutton 0.
\tinput enable_in;\t\t// Should be connected to pushbutton 1.
\toutput enable_out;\t// The output is high for one FPGA clock cycle each time pushbutton 1 is pressed and released.
\t
// Variables for keeping track of the state.
\treg [1:0] key_state, next_key_state;
\treg enable_out;
// Set up parameters for "state" of the pushbutton.
// Since there are three states, we are using 2-bits to represent the state in a so-called "dense" assignment.
\tparameter [1:0] KEY_FREE = 2\'b00, KEY_PRESSED = 2\'b01, KEY_RELEASED = 2\'b10;
// The following always block represents sequential logic, and therefore uses non-blocking assignments.
// This always block is sensitized to the clock input and the reset input. You should picture this always block as a 2-bit
// register with an active-low asynchronous clear.
\talways @(posedge clock or negedge reset) begin
\t
\t// If reset = 0, there must have been a negative edge on the reset.
\t// Since the effect of the reset occurs in the absence of a clock pulse, the reset is ASYNCHRONOUS.
\t\tif (reset == 1\'b0)
\t\t\tkey_state <= KEY_FREE;
\t\t
\t// If reset !=0 but this always block is executing, there must have been a positive clock edge.
\t// On each positive clock edge, the next state becomes the present state.
\t\telse
\t\t\tkey_state <= next_key_state;
\tend
// The following always block represents combinational logic. It uses blocking assignments.
// This always block is sensitized to changes in the present state and enable input. You should picture this block as
// a combinational circuit that feeds the register inputs. It determines the next state based on the current state and
// the enable input.
\talways @(key_state, enable_in) begin
\t
\t// To be safe, assign values to the next_key_state and enable_out. That way, if none of the paths in the case
\t// statement apply, these variables have known values.
\t\tnext_key_state = key_state;
\t\tenable_out = 1\'b0;
\t\t
\t// Use the present state to determine the next state.
\t\tcase (key_state)
\t\t
\t\t// If the key is free (i.e., is unpressed and was not just released):
\t\t\tKEY_FREE: begin
\t\t\t
\t\t\t// If the enable input button is down, make the next state KEY_PRESSED.
\t\t\t\tif (enable_in == 1\'b0)
\t\t\t\t\tnext_key_state = KEY_PRESSED;
\t\t\tend
\t\t
\t\t// If the key is pressed:
\t\t\tKEY_PRESSED: begin
\t\t\t
\t\t\t// If the enable button is up, make the next state KEY_RELEASED.
\t\t\t\tif (enable_in == 1\'b1)
\t\t\t\t\tnext_key_state = KEY_RELEASED;
\t\t\tend
\t\t\t
\t\t// If the key is released (i.e., the button has just gone from being pressed to being released):
\t\t\tKEY_RELEASED: begin
\t\t\t
\t\t\t// Take the output high.
\t\t\t\tenable_out = 1\'b1;
\t\t\t
\t\t\t// Make the next state KEY_FREE. Note that this state transition always happens and is independent of
\t\t\t// the input
\t\t\t\tnext_key_state = KEY_FREE;
\t\t\tend
\t\t\t
\t\t// If none of the above - something that should never happen - make the next state and output unknown.
\t\t\tdefault: begin
\t\t\t\tnext_key_state = 2\'bxx;
\t\t\t\tenable_out = 1\'bx;
\t\t\tend
\t\t\t
\t\tendcase
\t\t
\tend
\t
endmodule
|
////////////////////////////////////////////////////////////////////////////////
//
// Filename: project4.v
// Author: Danny Dutton
// Date: May 7 2014
// Revision: 0
//
// Description:
// This is the top level module for ECE 3544 Project 4.
// Do not modify the module declarations or ports in this file.
// When synthesizing to the DE1-SoC, this file should be used with the provided
// Quartus project so that the FPGA pin assignments are made correctly.
//
// YOU MUST MAKE THE PIN ASSIGNMENTS FOR THE INPUTS AND OUTPUTS OF THI MODULE.
// FOLLOW THE INSTRUCTIONS THAT YOU USED IN PROJECT 3.
// CONSULT THE MANUAL FOR INFORMATION ON THE PIN LOCATIONS.
//
// Modified for use with the DE1-SoC
//==========================================================
// This code is generated by Terasic System Builder
//==========================================================
// Do NOT modify the module declaration.
module project4(CLOCK_50, KEY, SW, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0, LED);
//==========================================================
// PORT declarations: Do NOT modify these declarations.
//==========================================================
// You must use this clock for the clock of all of your sequential hardware.
\tinput CLOCK_50;
// KEY[0] should be used as reset, active low.
// KEY[1] should be used to enter operation codes and operands.
// The KEY pushbuttons are 1 when not pressed and 0 when pressed.
\tinput[1:0] KEY;
// SW[2] controls the mode.
// SW [1:0] represents a coin input.
\tinput[2:0] SW;
// The hex display outputs drive the seven segment displays.
// The LED output drives the LEDs.
\t
\toutput [0:6] HEX5, HEX4, HEX3, HEX2, HEX1, HEX0;
\toutput [7:0] LED;
// You should add your reg/wire/parameter declarations here.
\twire enable;
\twire[7:0] nickel_counter, dime_counter, quarter_counter;
\t
//=======================================================
// Module instantiantons
//=======================================================
\t
// This is an instantiation of the keypressed module from Project 3.\t
\t
\tkeypressed K1(.clock(CLOCK_50),.reset(KEY[0]),.enable_in(KEY[1]),.enable_out(enable));
// You should add your module instantions here.
\tvendingmachine V1 (.clock(CLOCK_50),
\t\t\t\t\t\t\t.enable(enable),
\t\t\t\t\t\t\t.reset(KEY[0]),
\t\t\t\t\t\t\t.coin(SW[1:0]),
\t\t\t\t\t\t\t.mode(SW[2]),
\t\t\t\t\t\t\t.quarter_counter(quarter_counter),
\t\t\t\t\t\t\t.dime_counter(dime_counter),
\t\t\t\t\t\t\t.nickel_counter(nickel_counter),
\t\t\t\t\t\t\t.dimenickelLEDon(LED[3]),
\t\t\t\t\t\t\t.dimeLEDon(LED[1]),
\t\t\t\t\t\t\t.nickelLEDon(LED[0]),
\t\t\t\t\t\t\t.vendLEDon(LED[2]));
\tsevensegdecoder_always S0 (.digit(nickel_counter[3:0]),
\t\t\t\t\t\t\t\t\t\t.drivers(HEX0));
\t\t\t\t\t\t\t\t\t\t
\tsevensegdecoder_always S1 (.digit(nickel_counter[7:4]),
\t\t\t\t\t\t\t\t\t\t.drivers(HEX1));
\t\t\t\t\t\t\t\t\t\t
\tsevensegdecoder_always S2 (.digit(dime_counter[3:0]),
\t\t\t\t\t\t\t\t\t\t.drivers(HEX2));
\t\t\t\t\t\t\t\t\t\t
\tsevensegdecoder_always S3 (.digit(dime_counter[7:4]),
\t\t\t\t\t\t\t\t\t\t.drivers(HEX3));
\tsevensegdecoder_always S4 (.digit(quarter_counter[3:0]),
\t\t\t\t\t\t\t\t\t\t.drivers(HEX4));
\t\t\t\t\t\t\t\t\t\t
\tsevensegdecoder_always S5 (.digit(quarter_counter[7:4]),
\t\t\t\t\t\t\t\t\t\t.drivers(HEX5));
\t\t\t\t\t
endmodule
|
// Filename: sevensegmentdecoder_assign.v
// Author: Danny Dutton
// Date: 03/03/15
// Version: 1
// Description: Decode 4-bit input and drive a seven segment using assignment
module sevensegdecoder_always(digit, drivers);
input [3:0] digit;
output [6:0] drivers;\t// Take a to be the MSB of the vector.
reg [6:0] drivers;
always @(digit) begin
\tif(digit == 4'h0)
\t\tbegin
\t\t\tdrivers = 7'b0000001;
\t\tend
\t\telse if(digit == 4'h1)
\t\tbegin
\t\t\tdrivers = 7'b1001111;
\t\tend
\t\telse if(digit == 4'h2)
\t\tbegin
\t\t\tdrivers = 7'b0010010;
\t\tend
\t\telse if(digit == 4'h3)
\t\tbegin
\t\t\tdrivers = 7'b0000110;
\t\tend
\t\telse if(digit == 4'h4)
\t\tbegin
\t\t\tdrivers = 7'b1001100;
\t\tend
\t\telse if(digit == 4'h5)
\t\tbegin
\t\t\tdrivers = 7'b0100100;
\t\tend
\t\telse if(digit == 4'h6)
\t\tbegin
\t\t\tdrivers = 7'b0100000;
\t\tend
\t\telse if(digit == 4'h7)
\t\tbegin
\t\t\tdrivers = 7'b0001101;
\t\tend
\t\telse if(digit == 4'h8)
\t\tbegin
\t\t\tdrivers = 7'b0000000;
\t\tend
\t\telse if(digit == 4'h9)
\t\tbegin
\t\t\tdrivers = 7'b0000100;
\t\tend
\t\telse if(digit == 4'hA)
\t\tbegin
\t\t\tdrivers = 7'b0001000;
\t\tend
\t\telse if(digit == 4'hB)
\t\tbegin
\t\t\tdrivers = 7'b1100000;
\t\tend
\t\telse if(digit == 4'hC)
\t\tbegin
\t\t\tdrivers = 7'b0110001;
\t\tend
\t\telse if(digit == 4'hD)
\t\tbegin
\t\t\tdrivers = 7'b1000010;
\t\tend
\t\telse if(digit == 4'hE)
\t\tbegin
\t\t\tdrivers = 7'b0110000;
\t\tend
\t\telse if(digit == 4'hF)
\t\tbegin
\t\t\tdrivers = 7'b0111000;
\t\tend
end
endmodule
|
module rpi_spi (
\tinput clk,
\tinput cs,
\tinput mosi,
\toutput miso,
\tinput sck,
\toutput done,
\tinput sw,
\toutput [15:0] dout);
\twire [15:0] in = {15'b000000000000000, sw};
\twire rst = 0;
\tspi_slave #(16, 6) spi(clk, rst, cs, mosi, miso, sck, done, in, dout);
//\tspi_slave_simpler2 #(8) spi(clk, cs, mosi, miso, sck, done, in, dout);
endmodule
|
module spi_slave_simpler(clk, cs, mosi, miso, sck, done, din, dout);
\tparameter bc=8;\t// bit count
\t
\tinput clk;
\tinput cs;
\tinput mosi;
\toutput reg miso;
\tinput sck;
\toutput reg done;
\tinput [bc-1:0] din;
\toutput reg [bc-1:0] dout;
\t
\treg [bc-1:0] shift_reg;
\treg prev_cs, prev_sck;
\treg [3:0]shift_count;
\t
//\tassign miso = shift_reg[bc-1];
\talways @(*) begin
\t\tif (~cs) begin
\t\t\t// enabled
\t\t\tmiso = shift_reg[bc-1];
\t\tend
\tend
\talways @(posedge clk) begin
\t\tif (~cs) begin
\t\t\tif (prev_cs) begin
\t\t\t\t// falling cs edge - start spi transfer
\t\t\t\tdone <= 0;
\t\t\t\tshift_reg[bc-1:0] <= din[bc-1:0];
\t\t\t\tshift_count <= bc;
\t\t\tend
\t\t\tif (~done && sck && ~prev_sck) begin
\t\t\t\t\t// rising sck edge - shift in/out one bit
\t\t\t\t\tshift_reg[bc-1:0] <= {shift_reg[bc-2:0], mosi};
\t\t\t\t\tshift_count <= shift_count - 1'b1;
\t\t\t\t\tif (shift_count == 1'b0) begin
\t\t\t\t\t\tdout <= shift_reg;
\t\t\t\t\t\tdone <= 1;
\t\t\t\t\tend
\t\t\tend
\t\tend else begin
\t\t\tdone <= 1;
\t\tend
\t\tprev_cs <= cs;
\t\tprev_sck <= sck;
\tend
endmodule
|
module spi_slave_simpler2(clk, cs, mosi, miso, sck, done, din, dout);
\tparameter bc=8;\t// bit count
\t
\tinput clk;
\tinput cs;\t// active low
\tinput mosi;
\toutput miso;
\tinput sck;
\toutput reg done;
\tinput [bc-1:0] din;
\toutput reg [bc-1:0] dout;
\t
\treg [bc-1:0] shift_reg;
\treg prev_cs, prev_sck;
\treg mosi_sample;
\treg [7:0] shift_count;
\t
\tassign miso = shift_reg[bc-1];
\talways @(posedge clk) begin
\t\tif (~cs) begin
\t\t\tif (prev_cs) begin
\t\t\t\t// falling cs edge - start spi transfer
\t\t\t\tdone <= 0;
\t\t\t\tshift_reg[bc-1:0] <= 8'h23; //din[bc-1:0];
\t\t\t\tshift_count <= 0;
\t\t\tend else begin
\t\t\t\tif (~prev_sck && sck) begin
\t\t\t\t\t// rising sck edge - sample mosi
\t\t\t\t\tmosi_sample <= mosi;
\t\t\t\t\tif (shift_count == bc-1) begin
\t\t\t\t\t\tdout <= {shift_reg[bc-2:0], mosi};
\t\t\t\t\t\tdone <= 1;
\t\t\t\t\tend
\t\t\t\tend
\t\t\t\tif (prev_sck && ~sck) begin
\t\t\t\t\t// falling sck edge - shift in/out one bit
\t\t\t\t\tshift_reg[bc-1:0] <= {shift_reg[bc-2:0], mosi_sample};
\t\t\t\t\tshift_count <= shift_count + 1;
\t\t\t\tend
\t\t\tend
\t\tend else begin
\t\t\tdone <= 1;
\t\tend
\t\tprev_cs <= cs;
\t\tprev_sck <= sck;
\tend
endmodule
|
module spi_slave(input clk, input rst, input ss, input mosi, output miso, input sck, output done, input [bc-1:0] din, output [bc-1:0] dout);
parameter bc=8;\t// bit count
parameter counter_bits = 6;
\t
reg mosi_d, mosi_q;
reg ss_d, ss_q;
reg sck_d, sck_q;
reg sck_old_d, sck_old_q;
reg [bc-1:0] data_d, data_q;
reg done_d, done_q;
reg [counter_bits-1:0] bit_ct_d, bit_ct_q;
reg [bc-1:0] dout_d, dout_q;
reg miso_d, miso_q;
assign miso = miso_q;
assign done = done_q;
assign dout = dout_q;
always @(*) begin
\tss_d = ss;
\tmosi_d = mosi;
\tmiso_d = miso_q;
\tsck_d = sck;
\tsck_old_d = sck_q;
\tdata_d = data_q;
\tdone_d = 1'b0;
\tbit_ct_d = bit_ct_q;
\tdout_d = dout_q;
\tif (ss_q) begin\t// if slave select is high (deselcted)
\t\tbit_ct_d = 0; // reset bit counter
\t\tdata_d = din; // read in data
\t\tmiso_d = data_q[bc-1]; // output MSB
\tend else begin // else slave select is low (selected)
\t\tif (!sck_old_q && sck_q) begin // rising edge
\t\t\tdata_d = {data_q[bc-2:0], mosi_q}; // read data in and shift
\t\t\tbit_ct_d = bit_ct_q + 1'b1; // increment the bit counter
\t\t\tif (bit_ct_q == bc-1) begin // if we are on the last bit
\t\t\t\tdout_d = {data_q[bc-2:0], mosi_q}; // output the byte
\t\t\t\tdone_d = 1'b1; // set transfer done flag
\t\t\t\tdata_d = din; // read in new byte
\t\t\tend
\t\tend else if (sck_old_q && !sck_q) begin // falling edge
\t\t\tmiso_d = data_q[bc-1]; // output MSB
\t\tend
\tend
end
always @(posedge clk) begin
\tif (rst) begin
\t\tdone_q <= 1'b0;
\t\tbit_ct_q <= 3'b0;
\t\tdout_q <= 8'b0;
\t\tmiso_q <= 1'b1;
\tend else begin
\t\tdone_q <= done_d;
\t\tbit_ct_q <= bit_ct_d;
\t\tdout_q <= dout_d;
\t\tmiso_q <= miso_d;
\tend
\tsck_q <= sck_d;
\tmosi_q <= mosi_d;
\tss_q <= ss_d;
\tdata_q <= data_d;
\tsck_old_q <= sck_old_d;
end
endmodule
|
LIBAVDEVICE_$MAJOR {
global: avdevice_*; av_*;
local: *;
};
|
LIBSWRESAMPLE_$MAJOR {
global: swr_*; swresample_*;
local: *;
};
|
LIBAVFILTER_$MAJOR {
global: avfilter_*; av_*;
local: *;
};
|
LIBPOSTPROC_$MAJOR {
global: postproc_*; pp_*;
local: *;
};
|
LIBAVRESAMPLE_$MAJOR {
global: av*;
local: *;
};
|
LIBAVCODEC_$MAJOR {
global: av*;
#deprecated, remove after next bump
audio_resample;
audio_resample_close;
local: *;
};
|
LIBAVFORMAT_$MAJOR {
global: av*;
#FIXME those are for ffserver
ff_inet_aton;
ff_socket_nonblock;
ff_rtsp_parse_line;
ff_rtp_get_local_rtp_port;
ff_rtp_get_local_rtcp_port;
ffio_open_dyn_packet_buf;
ffio_set_buf_size;
ffurl_close;
ffurl_open;
ffurl_write;
#those are deprecated, remove on next bump
url_feof;
local: *;
};
|
LIBSWSCALE_$MAJOR {
global: swscale_*; sws_*;
local: *;
};
|
LIBAVUTIL_$MAJOR {
global: av*;
local: *;
};
|
Module SyntaxError.
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
S O => false
| S (S n') => evenb n'
end.
End SyntaxError.
|
Module Error.
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => 1
end.
End Error.
|
module verilog_verilator_warning;
reg val;
endmodule
|
module verilog_verilator_error;
initial begin
forever begin
i = $fopen("test.log");
end
end
endmodule
|
/*\r
* Linear mode graphics for VGA\r
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>\r
*\r
* VGA FML support\r
* Copyright (C) 2013 Charley Picker <[email protected]>\r
*\r
* This file is part of the Zet processor. This processor is free\r
* hardware; you can redistribute it and/or modify it under the terms of\r
* the GNU General Public License as published by the Free Software\r
* Foundation; either version 3, or (at your option) any later version.\r
*\r
* Zet is distrubuted in the hope that it will be useful, but WITHOUT\r
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public\r
* License for more details.\r
*\r
* You should have received a copy of the GNU General Public License\r
* along with Zet; see the file COPYING. If not, see\r
* <http://www.gnu.org/licenses/>.\r
*/\r
\r
module vga_linear_fml (\r
input clk,\r
input rst,\r
\r
input enable,\r
\r
// CSR slave interface for reading\r
output [17:1] fml_adr_o,\r
input [15:0] fml_dat_i,\r
output fml_stb_o,\r
\r
input [9:0] h_count,\r
input [9:0] v_count,\r
input horiz_sync_i,\r
input video_on_h_i,\r
output video_on_h_o,\r
\r
output [7:0] color,\r
output horiz_sync_o\r
);\r
\r
// Registers\r
reg [ 9:0] row_addr;\r
reg [ 6:0] col_addr;\r
reg [14:1] word_offset;\r
reg [ 1:0] plane_addr;\r
reg [ 1:0] plane_addr0;\r
reg [ 7:0] color_l;\r
\r
reg [ 15:0] fml1_dat;\r
reg [ 15:0] fml2_dat;\r
reg [ 15:0] fml3_dat;\r
reg [ 15:0] fml4_dat;\r
reg [ 15:0] fml5_dat;\r
reg [ 15:0] fml6_dat;\r
reg [ 15:0] fml7_dat;\r
\r
reg [4:0] video_on_h;\r
reg [4:0] horiz_sync;\r
reg [18:0] pipe; \r
\r
// Continous assignments \r
assign fml_adr_o = { 1'b0, word_offset, plane_addr };\r
assign fml_stb_o = pipe[1];\r
\r
assign color = pipe[4] ? fml_dat_i[7:0] : color_l; \r
\r
assign video_on_h_o = video_on_h[4];\r
assign horiz_sync_o = horiz_sync[4];\r
\r
// Behaviour\r
// FML 8x16 pipeline count\r
always @(posedge clk)\r
if (rst)\r
begin\r
pipe <= 18'b0; \r
end\r
else\r
if (enable)\r
begin\r
pipe <= { pipe[17:0], (h_count[3:0]==4'h0) };\r
end\r
\r
// Load FML 8x16 burst\r
always @(posedge clk)\r
if (enable)\r
begin\r
fml1_dat <= pipe[5] ? fml_dat_i[15:0] : fml1_dat;\r
fml2_dat <= pipe[6] ? fml_dat_i[15:0] : fml2_dat;\r
fml3_dat <= pipe[7] ? fml_dat_i[15:0] : fml3_dat;\r
fml4_dat <= pipe[8] ? fml_dat_i[15:0] : fml4_dat;\r
fml5_dat <= pipe[9] ? fml_dat_i[15:0] : fml5_dat;\r
fml6_dat <= pipe[10] ? fml_dat_i[15:0] : fml6_dat;\r
fml7_dat <= pipe[11] ? fml_dat_i[15:0] : fml7_dat;\r
end\r
\r
// video_on_h\r
always @(posedge clk)\r
if (rst)\r
begin\r
video_on_h <= 5'b0;\r
end\r
else\r
if (enable)\r
begin\r
video_on_h <= { video_on_h[3:0], video_on_h_i };\r
end\r
\r
// horiz_sync\r
always @(posedge clk)\r
if (rst)\r
begin\r
horiz_sync <= 5'b0;\r
end\r
else\r
if (enable)\r
begin\r
horiz_sync <= { horiz_sync[3:0], horiz_sync_i };\r
end\r
\r
// Address generation\r
always @(posedge clk)\r
if (rst)\r
begin\r
row_addr <= 10'h0;\r
col_addr <= 7'h0;\r
plane_addr0 <= 2'b00;\r
word_offset <= 14'h0;\r
plane_addr <= 2'b00;\r
end\r
else\r
if (enable)\r
begin\r
// Loading new row_addr and col_addr when h_count[3:0]==4'h0\r
// v_count * 5 * 32\r
row_addr <= { v_count[8:1], 2'b00 } + v_count[8:1];\r
col_addr <= h_count[9:3];\r
plane_addr0 <= h_count[2:1];\r
\r
word_offset <= { row_addr + col_addr[6:4], col_addr[3:0] };\r
plane_addr <= plane_addr0;\r
end\r
\r
// color_l\r
always @(posedge clk)\r
if (rst)\r
begin\r
color_l <= 8'h0;\r
end\r
else\r
if (enable)\r
begin\r
if (pipe[4])\r
color_l <= fml_dat_i[7:0];\r
else\r
if (pipe[5])\r
color_l <= fml_dat_i[7:0];\r
else\r
if (pipe[7])\r
color_l <= fml2_dat[7:0];\r
else\r
if (pipe[9])\r
color_l <= fml3_dat[7:0];\r
else\r
if (pipe[11])\r
color_l <= fml4_dat[7:0];\r
else\r
if (pipe[13])\r
color_l <= fml5_dat[7:0];\r
else\r
if (pipe[15])\r
color_l <= fml6_dat[7:0];\r
else\r
if (pipe[17])\r
color_l <= fml7_dat[7:0];\r
end\r
\r
endmodule\r
|
/*
* PC speaker module using WM8731 codec
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module speaker (
// Clocks
input clk,
input rst,
// Wishbone slave interface
input [7:0] wb_dat_i,
output reg [7:0] wb_dat_o,
input wb_we_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// Clocks
input clk_100M,
input clk_25M,
input timer2,
// I2C pad signals
output i2c_sclk_,
inout i2c_sdat_,
// Audio codec pad signals
input aud_adcdat_,
input aud_daclrck_,
output aud_dacdat_,
input aud_bclk_
);
// Net declaration
wire [15:0] audio_r;
wire [15:0] audio_l;
wire write;
wire spk;
// Module instances
speaker_iface iface (
.clk_i (clk_100M),
.rst_i (rst),
.datal_i (audio_l),
.datar_i (audio_r),
.datal_o (),
.datar_o (),
.ready_o (),
.aud_bclk_i (aud_bclk_),
.aud_daclrck_i (aud_daclrck_),
.aud_dacdat_o (aud_dacdat_),
.aud_adcdat_i (aud_adcdat_)
);
speaker_i2c_av_config i2c_av_config (
// Host Side
.clk_i (clk_25M),
.rst_i (rst),
// I2C Side
.i2c_sclk (i2c_sclk_),
.i2c_sdat (i2c_sdat_)
);
// Combinatorial logic
// System speaker
assign spk = timer2 & wb_dat_o[1];
// System speaker audio output
assign audio_l = {spk, 15'h4000};
assign audio_r = {spk, 15'h4000};
// Wishbone signals
assign wb_ack_o = wb_stb_i && wb_cyc_i;
assign write = wb_stb_i && wb_cyc_i && wb_we_i;
// Sequential logic
always @(posedge clk)
wb_dat_o <= rst ? 8'h0 : (write ? wb_dat_i : wb_dat_o);
endmodule
|
/*
* PS2 Mouse Interface
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module ps2_mouse (
input clk, // Clock Input
input reset, // Reset Input
inout ps2_clk, // PS2 Clock, Bidirectional
inout ps2_dat, // PS2 Data, Bidirectional
input inhibit,
input [7:0] the_command, // Command to send to mouse
input send_command, // Signal to send
output command_was_sent, // Signal command finished sending
output error_communication_timed_out,
output [7:0] received_data, // Received data
output received_data_en, // If 1 - new data has been received
output start_receiving_data,
output wait_for_incoming_data
);
// --------------------------------------------------------------------
// Internal wires and registers Declarations
// --------------------------------------------------------------------
wire ps2_clk_posedge; // Internal Wires
wire ps2_clk_negedge;
reg [7:0] idle_counter; // Internal Registers
reg ps2_clk_reg;
reg ps2_data_reg;
reg last_ps2_clk;
reg [2:0] ns_ps2_transceiver; // State Machine Registers
reg [2:0] s_ps2_transceiver;
// --------------------------------------------------------------------
// Constant Declarations
// --------------------------------------------------------------------
localparam PS2_STATE_0_IDLE = 3'h0, // states
PS2_STATE_1_DATA_IN = 3'h1,
PS2_STATE_2_COMMAND_OUT = 3'h2,
PS2_STATE_3_END_TRANSFER = 3'h3,
PS2_STATE_4_END_DELAYED = 3'h4;
// --------------------------------------------------------------------
// Finite State Machine(s)
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) s_ps2_transceiver <= PS2_STATE_0_IDLE;
else s_ps2_transceiver <= ns_ps2_transceiver;
end
always @(*) begin
ns_ps2_transceiver = PS2_STATE_0_IDLE; // Defaults
case (s_ps2_transceiver)
PS2_STATE_0_IDLE:
begin
if((idle_counter == 8'hFF) && (send_command == 1'b1))
ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
else ns_ps2_transceiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_DATA_IN:
begin
// if((received_data_en == 1'b1) && (ps2_clk_posedge == 1'b1))
if((received_data_en == 1'b1)) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
end
PS2_STATE_2_COMMAND_OUT:
begin
if((command_was_sent == 1'b1) || (error_communication_timed_out == 1'b1))
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
else ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
end
PS2_STATE_3_END_TRANSFER:
begin
if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else if((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
PS2_STATE_4_END_DELAYED:
begin
if(received_data_en == 1'b1) begin
if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
else ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
end
default:
ns_ps2_transceiver = PS2_STATE_0_IDLE;
endcase
end
// --------------------------------------------------------------------
// Sequential logic
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) begin
last_ps2_clk <= 1'b1;
ps2_clk_reg <= 1'b1;
ps2_data_reg <= 1'b1;
end
else begin
last_ps2_clk <= ps2_clk_reg;
ps2_clk_reg <= ps2_clk;
ps2_data_reg <= ps2_dat;
end
end
always @(posedge clk) begin
if(reset == 1'b1) idle_counter <= 6'h00;
else if((s_ps2_transceiver == PS2_STATE_0_IDLE) && (idle_counter != 8'hFF))
idle_counter <= idle_counter + 6'h01;
else if (s_ps2_transceiver != PS2_STATE_0_IDLE)
idle_counter <= 6'h00;
end
// --------------------------------------------------------------------
// Combinational logic
// --------------------------------------------------------------------
assign ps2_clk_posedge = ((ps2_clk_reg == 1'b1) && (last_ps2_clk == 1'b0)) ? 1'b1 : 1'b0;
assign ps2_clk_negedge = ((ps2_clk_reg == 1'b0) && (last_ps2_clk == 1'b1)) ? 1'b1 : 1'b0;
assign start_receiving_data = (s_ps2_transceiver == PS2_STATE_1_DATA_IN);
assign wait_for_incoming_data = (s_ps2_transceiver == PS2_STATE_3_END_TRANSFER);
// --------------------------------------------------------------------
// Internal Modules
// --------------------------------------------------------------------
ps2_mouse_cmdout mouse_cmdout (
.clk (clk), // Inputs
.reset (reset),
.the_command (the_command),
.send_command (send_command),
.inhibit (inhibit),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_clk (ps2_clk), // Bidirectionals
.ps2_dat (ps2_dat),
.command_was_sent (command_was_sent), // Outputs
.error_communication_timed_out (error_communication_timed_out)
);
ps2_mouse_datain mouse_datain (
.clk (clk), // Inputs
.reset (reset),
.wait_for_incoming_data (wait_for_incoming_data),
.start_receiving_data (start_receiving_data),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_data (ps2_data_reg),
.received_data (received_data), // Outputs
.received_data_en (received_data_en)
);
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// \t\t\taltpll
//
// Simulation Library Files(s):
// \t\t\taltera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation\'s design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
\tinclk0,
\tc0,
\tc2,
\tlocked);
\tinput\t inclk0;
\toutput\t c0;
\toutput\t c2;
\toutput\t locked;
\twire sub_wire0;
\twire [5:0] sub_wire1;
\twire [0:0] sub_wire6 = 1\'h0;
\twire locked = sub_wire0;
\twire [2:2] sub_wire3 = sub_wire1[2:2];
\twire [0:0] sub_wire2 = sub_wire1[0:0];
\twire c0 = sub_wire2;
\twire c2 = sub_wire3;
\twire sub_wire4 = inclk0;
\twire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
\taltpll\taltpll_component (
\t\t\t\t.inclk (sub_wire5),
\t\t\t\t.locked (sub_wire0),
\t\t\t\t.clk (sub_wire1),
\t\t\t\t.activeclock (),
\t\t\t\t.areset (1\'b0),
\t\t\t\t.clkbad (),
\t\t\t\t.clkena ({6{1\'b1}}),
\t\t\t\t.clkloss (),
\t\t\t\t.clkswitch (1\'b0),
\t\t\t\t.configupdate (1\'b0),
\t\t\t\t.enable0 (),
\t\t\t\t.enable1 (),
\t\t\t\t.extclk (),
\t\t\t\t.extclkena ({4{1\'b1}}),
\t\t\t\t.fbin (1\'b1),
\t\t\t\t.fbmimicbidir (),
\t\t\t\t.fbout (),
\t\t\t\t.fref (),
\t\t\t\t.icdrclk (),
\t\t\t\t.pfdena (1\'b1),
\t\t\t\t.phasecounterselect ({4{1\'b1}}),
\t\t\t\t.phasedone (),
\t\t\t\t.phasestep (1\'b1),
\t\t\t\t.phaseupdown (1\'b1),
\t\t\t\t.pllena (1\'b1),
\t\t\t\t.scanaclr (1\'b0),
\t\t\t\t.scanclk (1\'b0),
\t\t\t\t.scanclkena (1\'b1),
\t\t\t\t.scandata (1\'b0),
\t\t\t\t.scandataout (),
\t\t\t\t.scandone (),
\t\t\t\t.scanread (1\'b0),
\t\t\t\t.scanwrite (1\'b0),
\t\t\t\t.sclkout0 (),
\t\t\t\t.sclkout1 (),
\t\t\t\t.vcooverrange (),
\t\t\t\t.vcounderrange ());
\tdefparam
\t\taltpll_component.clk0_divide_by = 1,
\t\taltpll_component.clk0_duty_cycle = 50,
\t\taltpll_component.clk0_multiply_by = 2,
\t\taltpll_component.clk0_phase_shift = "-2917",
\t\taltpll_component.clk2_divide_by = 4,
\t\taltpll_component.clk2_duty_cycle = 50,
\t\taltpll_component.clk2_multiply_by = 1,
\t\taltpll_component.clk2_phase_shift = "0",
\t\taltpll_component.compensate_clock = "CLK0",
\t\taltpll_component.gate_lock_counter = 1048575,
\t\taltpll_component.gate_lock_signal = "YES",
\t\taltpll_component.inclk0_input_frequency = 20000,
\t\taltpll_component.intended_device_family = "Cyclone II",
\t\taltpll_component.invalid_lock_multiplier = 5,
\t\taltpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
\t\taltpll_component.lpm_type = "altpll",
\t\taltpll_component.operation_mode = "NORMAL",
\t\taltpll_component.port_activeclock = "PORT_UNUSED",
\t\taltpll_component.port_areset = "PORT_UNUSED",
\t\taltpll_component.port_clkbad0 = "PORT_UNUSED",
\t\taltpll_component.port_clkbad1 = "PORT_UNUSED",
\t\taltpll_component.port_clkloss = "PORT_UNUSED",
\t\taltpll_component.port_clkswitch = "PORT_UNUSED",
\t\taltpll_component.port_configupdate = "PORT_UNUSED",
\t\taltpll_component.port_fbin = "PORT_UNUSED",
\t\taltpll_component.port_inclk0 = "PORT_USED",
\t\taltpll_component.port_inclk1 = "PORT_UNUSED",
\t\taltpll_component.port_locked = "PORT_USED",
\t\taltpll_component.port_pfdena = "PORT_UNUSED",
\t\taltpll_component.port_phasecounterselect = "PORT_UNUSED",
\t\taltpll_component.port_phasedone = "PORT_UNUSED",
\t\taltpll_component.port_phasestep = "PORT_UNUSED",
\t\taltpll_component.port_phaseupdown = "PORT_UNUSED",
\t\taltpll_component.port_pllena = "PORT_UNUSED",
\t\taltpll_component.port_scanaclr = "PORT_UNUSED",
\t\taltpll_component.port_scanclk = "PORT_UNUSED",
\t\taltpll_component.port_scanclkena = "PORT_UNUSED",
\t\taltpll_component.port_scandata = "PORT_UNUSED",
\t\taltpll_component.port_scandataout = "PORT_UNUSED",
\t\taltpll_component.port_scandone = "PORT_UNUSED",
\t\taltpll_component.port_scanread = "PORT_UNUSED",
\t\taltpll_component.port_scanwrite = "PORT_UNUSED",
\t\taltpll_component.port_clk0 = "PORT_USED",
\t\taltpll_component.port_clk1 = "PORT_UNUSED",
\t\taltpll_component.port_clk2 = "PORT_USED",
\t\taltpll_component.port_clk3 = "PORT_UNUSED",
\t\taltpll_component.port_clk4 = "PORT_UNUSED",
\t\taltpll_component.port_clk5 = "PORT_UNUSED",
\t\taltpll_component.port_clkena0 = "PORT_UNUSED",
\t\taltpll_component.port_clkena1 = "PORT_UNUSED",
\t\taltpll_component.port_clkena2 = "PORT_UNUSED",
\t\taltpll_component.port_clkena3 = "PORT_UNUSED",
\t\taltpll_component.port_clkena4 = "PORT_UNUSED",
\t\taltpll_component.port_clkena5 = "PORT_UNUSED",
\t\taltpll_component.port_extclk0 = "PORT_UNUSED",
\t\taltpll_component.port_extclk1 = "PORT_UNUSED",
\t\taltpll_component.port_extclk2 = "PORT_UNUSED",
\t\taltpll_component.port_extclk3 = "PORT_UNUSED",
\t\taltpll_component.valid_lock_multiplier = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "4"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.500000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "10000000.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-2.91666700"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-2917"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "4"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: GATE_LOCK_COUNTER NUMERIC "1048575"
// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "YES"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/*
* Fetch & Decode module for Zet
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/10ps
`include "defines.v"
module zet_fetch (
input clk,
input rst,
// to decode
output [7:0] opcode,
output [7:0] modrm,
output rep,
output exec_st,
output ld_base,
output reg [2:0] sop_l,
// from decode
input need_modrm,
input need_off,
input need_imm,
input off_size,
input imm_size,
input ext_int,
input end_seq,
// to microcode
output reg [15:0] off_l,
output reg [15:0] imm_l,
// from microcode
input [5:0] ftype,
// to exec
output [15:0] imm_f,
input [15:0] cs,
input [15:0] ip,
input of,
input zf,
input cx_zero,
input [15:0] data,
output [19:0] pc,
output bytefetch,
input block,
input div_exc,
input tflm,
output wr_ip0,
input intr,
input iflm,
input nmir,
input iflss
);
// Registers, nets and parameters
parameter opcod_st = 3\'h0;
parameter modrm_st = 3\'h1;
parameter offse_st = 3\'h2;
parameter immed_st = 3\'h3;
parameter execu_st = 3\'h4;
reg [2:0] state;
wire [2:0] next_state;
wire prefix, repz_pr, sovr_pr, lock_pr;
wire next_in_opco, next_in_exec;
reg [7:0] opcode_l, modrm_l;
reg [1:0] pref_l;
reg lock_l;
// Module instantiation
zet_next_or_not next_or_not(pref_l, opcode[7:1], cx_zero, zf, ext_int, next_in_opco,
next_in_exec);
zet_nstate nstate (state, prefix, need_modrm, need_off, need_imm, end_seq,
ftype, of, next_in_opco, next_in_exec, block, div_exc,
tflm, intr, iflm, nmir, iflss, next_state);
// Assignments
assign pc = (cs << 4) + ip;
assign opcode = (state == opcod_st) ? data[7:0] : opcode_l;
assign modrm = (state == modrm_st) ? data[7:0] : modrm_l;
assign bytefetch = (state == offse_st) ? ~off_size
: ((state == immed_st) ? ~imm_size : 1\'b1);
assign exec_st = (state == execu_st);
assign imm_f = ((state == offse_st) & off_size
| (state == immed_st) & imm_size) ? 16\'d2
: 16\'d1;
assign wr_ip0 = (state == opcod_st) && !pref_l[1] && !sop_l[2] && !lock_l;
assign sovr_pr = (opcode[7:5]==3\'b001 && opcode[2:0]==3\'b110);
assign repz_pr = (opcode[7:1]==7\'b1111_001);
assign lock_pr = (opcode[7:0]==8\'b1111_0000);
assign prefix = sovr_pr || repz_pr || lock_pr;
assign ld_base = (next_state == execu_st);
assign rep = pref_l[1];
// Behaviour
always @(posedge clk)
if (rst)
begin
state <= execu_st;
opcode_l <= `OP_NOP;
end
else if (!block)
case (next_state)
default: // opcode or prefix
begin
case (state)
opcod_st:
begin // There has been a prefix
pref_l <= repz_pr ? { 1\'b1, opcode[0] }
// clear prefixes on next instr
: next_in_opco ? 2\'b0 : pref_l;
sop_l <= sovr_pr ? { 1\'b1, opcode[4:3] }
// clear prefixes on next instr
: next_in_opco ? 3\'b0 : sop_l;
lock_l <= lock_pr ? 1\'b1
// clear prefixes on next instr
: next_in_opco ? 1\'b0 : lock_l;
end
default: begin pref_l <= 2\'b0; sop_l <= 3\'b0; lock_l <= 1\'b0; end
endcase
state <= opcod_st;
off_l <= 16\'d0;
modrm_l <= 8\'b0000_0110;
end
modrm_st: // modrm
begin
opcode_l <= data[7:0];
state <= modrm_st;
end
offse_st: // offset
begin
case (state)
opcod_st: opcode_l <= data[7:0];
default: modrm_l <= data[7:0];
endcase
state <= offse_st;
end
immed_st: // immediate
begin
case (state)
opcod_st: opcode_l <= data[7:0];
modrm_st: modrm_l <= data[7:0];
default: off_l <= data;
endcase
state <= immed_st;
end
execu_st: // execute
begin
case (state)
opcod_st: opcode_l <= data[7:0];
modrm_st: modrm_l <= data[7:0];
offse_st: off_l <= data;
immed_st: imm_l <= data;
endcase
state <= execu_st;
end
endcase
endmodule
|
/*
* Add / substract unit for Zet
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_addsub (
input [15:0] x,
input [15:0] y,
output [15:0] out,
input [ 2:0] f,
input word_op,
input cfi,
output cfo,
output afo,
output ofo
);
// Net declarations
wire [15:0] op2;
wire ci;
wire cfoadd;
wire xs, ys, os;
// Module instances
zet_fulladd16 fulladd16 ( // We instantiate only one adder
.x (x), // to have less hardware
.y (op2),
.ci (ci),
.co (cfoadd),
.z (out),
.s (f[2])
);
// Assignments
assign op2 = f[2] ? ~y
: ((f[1:0]==2'b11) ? { 8'b0, y[7:0] } : y);
assign ci = f[2] & f[1] | f[2] & ~f[0] & ~cfi
| f[2] & f[0] | (f==3'b0) & cfi;
assign afo = f[1] ? (f[2] ? &out[3:0] : ~|out[3:0] )
: (x[4] ^ y[4] ^ out[4]);
assign cfo = f[1] ? cfi /* inc, dec */
: (word_op ? cfoadd : (x[8]^y[8]^out[8]));
assign xs = word_op ? x[15] : x[7];
assign ys = word_op ? y[15] : y[7];
assign os = word_op ? out[15] : out[7];
assign ofo = f[2] ? (~xs & ys & os | xs & ~ys & ~os)
: (~xs & ~ys & os | xs & ys & ~os);
endmodule
|
/*
* Copyright (c) 2009 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/10ps
module test_sdspi;
// Registers and nets
wire sclk;
reg miso;
wire mosi;
wire ss;
reg clk;
reg rst;
reg [8:0] dat_i;
wire [7:0] dat_o;
reg we;
reg [1:0] sel;
reg stb;
wire ack;
reg [7:0] data;
reg [7:0] st;
// Module instantiations
sdspi sdspi (
// Serial pad signal
.sclk (sclk),
.miso (miso),
.mosi (mosi),
.ss (ss),
// Wishbone slave interface
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_i (dat_i),
.wb_dat_o (dat_o),
.wb_we_i (we),
.wb_sel_i (sel),
.wb_stb_i (stb),
.wb_cyc_i (stb),
.wb_ack_o (ack)
);
// Behaviour
always @(posedge clk)
if (rst)
begin
dat_i <= 9'h0;
we <= 1'b0;
sel <= 2'b00;
stb <= 1'b0;
st <= 8'h0;
end
else
case (st)
8'h0:
begin
dat_i <= 9'h55;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'h1;
end
8'h1:
if (ack) begin
dat_i <= 9'hff;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'h2;
end
8'h2:
if (ack) begin
dat_i <= 9'h0ff;
we <= 1'b1;
sel <= 2'b11;
stb <= 1'b1;
st <= 8'h3;
end
8'h3:
if (ack) begin
dat_i <= 9'h40;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'h4;
end
8'h4:
if (ack) begin
dat_i <= 9'h00;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'h14;
end
8'h14:
if (ack) begin
dat_i <= 9'h00;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b0;
st <= 8'h5;
end
8'h5:
begin
dat_i <= 9'h00;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'h6;
end
8'h6:
if (ack) begin
dat_i <= 9'h00;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'h7;
end
8'h7:
if (ack) begin
dat_i <= 9'h00;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'h8;
end
8'h8:
if (ack) begin
dat_i <= 9'h95;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'h9;
end
8'h9:
if (ack) begin
dat_i <= 9'hff;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'd10;
end
8'd10:
if (ack) begin
dat_i <= 9'hff;
we <= 1'b0;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'd11;
end
8'd11:
if (ack) begin
dat_i <= 9'hff;
we <= 1'b0;
sel <= 2'b01;
stb <= 1'b0;
st <= 8'd12;
data <= dat_o;
end
endcase
always #40 clk <= !clk;
initial
begin
clk <= 1'b0;
rst <= 1'b1;
miso <= 1'b1;
sdspi.clk_div <= 2'b00;
#400 rst <= 1'b0;
end
initial
begin
#26440 miso <= 1'b1;
#320 miso <= 1'b1;
#320 miso <= 1'b1;
#320 miso <= 1'b0;
#320 miso <= 1'b1;
#320 miso <= 1'b0;
#320 miso <= 1'b1;
#320 miso <= 1'b1;
end
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// \t\t\taltpll
//
// Simulation Library Files(s):
// \t\t\taltera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation\'s design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
\tinclk0,
\tc0,
\tc2,
\tlocked);
\tinput\t inclk0;
\toutput\t c0;
\toutput\t c2;
\toutput\t locked;
\twire sub_wire0;
\twire [5:0] sub_wire1;
\twire [0:0] sub_wire6 = 1\'h0;
\twire locked = sub_wire0;
\twire [2:2] sub_wire3 = sub_wire1[2:2];
\twire [0:0] sub_wire2 = sub_wire1[0:0];
\twire c0 = sub_wire2;
\twire c2 = sub_wire3;
\twire sub_wire4 = inclk0;
\twire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
\taltpll\taltpll_component (
\t\t\t\t.inclk (sub_wire5),
\t\t\t\t.locked (sub_wire0),
\t\t\t\t.clk (sub_wire1),
\t\t\t\t.activeclock (),
\t\t\t\t.areset (1\'b0),
\t\t\t\t.clkbad (),
\t\t\t\t.clkena ({6{1\'b1}}),
\t\t\t\t.clkloss (),
\t\t\t\t.clkswitch (1\'b0),
\t\t\t\t.configupdate (1\'b0),
\t\t\t\t.enable0 (),
\t\t\t\t.enable1 (),
\t\t\t\t.extclk (),
\t\t\t\t.extclkena ({4{1\'b1}}),
\t\t\t\t.fbin (1\'b1),
\t\t\t\t.fbmimicbidir (),
\t\t\t\t.fbout (),
\t\t\t\t.fref (),
\t\t\t\t.icdrclk (),
\t\t\t\t.pfdena (1\'b1),
\t\t\t\t.phasecounterselect ({4{1\'b1}}),
\t\t\t\t.phasedone (),
\t\t\t\t.phasestep (1\'b1),
\t\t\t\t.phaseupdown (1\'b1),
\t\t\t\t.pllena (1\'b1),
\t\t\t\t.scanaclr (1\'b0),
\t\t\t\t.scanclk (1\'b0),
\t\t\t\t.scanclkena (1\'b1),
\t\t\t\t.scandata (1\'b0),
\t\t\t\t.scandataout (),
\t\t\t\t.scandone (),
\t\t\t\t.scanread (1\'b0),
\t\t\t\t.scanwrite (1\'b0),
\t\t\t\t.sclkout0 (),
\t\t\t\t.sclkout1 (),
\t\t\t\t.vcooverrange (),
\t\t\t\t.vcounderrange ());
\tdefparam
\t\taltpll_component.clk0_divide_by = 1,
\t\taltpll_component.clk0_duty_cycle = 50,
\t\taltpll_component.clk0_multiply_by = 2,
\t\taltpll_component.clk0_phase_shift = "-2920",
\t\taltpll_component.clk2_divide_by = 4,
\t\taltpll_component.clk2_duty_cycle = 50,
\t\taltpll_component.clk2_multiply_by = 1,
\t\taltpll_component.clk2_phase_shift = "0",
\t\taltpll_component.compensate_clock = "CLK0",
\t\taltpll_component.gate_lock_counter = 1048575,
\t\taltpll_component.gate_lock_signal = "YES",
\t\taltpll_component.inclk0_input_frequency = 20000,
\t\taltpll_component.intended_device_family = "Cyclone II",
\t\taltpll_component.invalid_lock_multiplier = 5,
\t\taltpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
\t\taltpll_component.lpm_type = "altpll",
\t\taltpll_component.operation_mode = "NORMAL",
\t\taltpll_component.port_activeclock = "PORT_UNUSED",
\t\taltpll_component.port_areset = "PORT_UNUSED",
\t\taltpll_component.port_clkbad0 = "PORT_UNUSED",
\t\taltpll_component.port_clkbad1 = "PORT_UNUSED",
\t\taltpll_component.port_clkloss = "PORT_UNUSED",
\t\taltpll_component.port_clkswitch = "PORT_UNUSED",
\t\taltpll_component.port_configupdate = "PORT_UNUSED",
\t\taltpll_component.port_fbin = "PORT_UNUSED",
\t\taltpll_component.port_inclk0 = "PORT_USED",
\t\taltpll_component.port_inclk1 = "PORT_UNUSED",
\t\taltpll_component.port_locked = "PORT_USED",
\t\taltpll_component.port_pfdena = "PORT_UNUSED",
\t\taltpll_component.port_phasecounterselect = "PORT_UNUSED",
\t\taltpll_component.port_phasedone = "PORT_UNUSED",
\t\taltpll_component.port_phasestep = "PORT_UNUSED",
\t\taltpll_component.port_phaseupdown = "PORT_UNUSED",
\t\taltpll_component.port_pllena = "PORT_UNUSED",
\t\taltpll_component.port_scanaclr = "PORT_UNUSED",
\t\taltpll_component.port_scanclk = "PORT_UNUSED",
\t\taltpll_component.port_scanclkena = "PORT_UNUSED",
\t\taltpll_component.port_scandata = "PORT_UNUSED",
\t\taltpll_component.port_scandataout = "PORT_UNUSED",
\t\taltpll_component.port_scandone = "PORT_UNUSED",
\t\taltpll_component.port_scanread = "PORT_UNUSED",
\t\taltpll_component.port_scanwrite = "PORT_UNUSED",
\t\taltpll_component.port_clk0 = "PORT_USED",
\t\taltpll_component.port_clk1 = "PORT_UNUSED",
\t\taltpll_component.port_clk2 = "PORT_USED",
\t\taltpll_component.port_clk3 = "PORT_UNUSED",
\t\taltpll_component.port_clk4 = "PORT_UNUSED",
\t\taltpll_component.port_clk5 = "PORT_UNUSED",
\t\taltpll_component.port_clkena0 = "PORT_UNUSED",
\t\taltpll_component.port_clkena1 = "PORT_UNUSED",
\t\taltpll_component.port_clkena2 = "PORT_UNUSED",
\t\taltpll_component.port_clkena3 = "PORT_UNUSED",
\t\taltpll_component.port_clkena4 = "PORT_UNUSED",
\t\taltpll_component.port_clkena5 = "PORT_UNUSED",
\t\taltpll_component.port_extclk0 = "PORT_UNUSED",
\t\taltpll_component.port_extclk1 = "PORT_UNUSED",
\t\taltpll_component.port_extclk2 = "PORT_UNUSED",
\t\taltpll_component.port_extclk3 = "PORT_UNUSED",
\t\taltpll_component.valid_lock_multiplier = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "4"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.500000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "10000000.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-2.92000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-2920"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "4"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: GATE_LOCK_COUNTER NUMERIC "1048575"
// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "YES"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/*
* Next state calculation for fetch FSM
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_nstate (
input [2:0] state,
input prefix,
input need_modrm,
input need_off,
input need_imm,
input end_seq,
input [5:0] ftype,
input of,
input next_in_opco,
input next_in_exec,
input block,
input div_exc,
input tflm,
input intr,
input iflm,
input nmir,
input iflss,
output [2:0] next_state
);
// Net declarations
parameter opcod_st = 3'h0;
parameter modrm_st = 3'h1;
parameter offse_st = 3'h2;
parameter immed_st = 3'h3;
parameter execu_st = 3'h4;
wire into, end_instr, end_into;
wire [2:0] n_state;
wire intr_iflm;
wire intrs_tni;
// Assignments
assign into = (ftype==6'b111_010);
assign end_into = into ? ~of : end_seq;
assign end_instr = !div_exc && !intrs_tni && end_into && !next_in_exec;
assign intr_iflm = intr & iflm;
assign intrs_tni = (tflm | nmir | intr_iflm) & iflss;
assign n_state = (state == opcod_st) ? (prefix ? opcod_st
: (next_in_opco ? opcod_st
: (need_modrm ? modrm_st
: (need_off ? offse_st
: (need_imm ? immed_st : execu_st)))))
: (state == modrm_st) ? (need_off ? offse_st
: (need_imm ? immed_st : execu_st))
: (state == offse_st) ? (need_imm ? immed_st : execu_st)
: (state == immed_st) ? (execu_st)
/* state == execu_st */ : (end_instr ? opcod_st : execu_st);
assign next_state = block ? state : n_state;
endmodule
|
/*
* Copyright (c) 2009 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module sdspi (
// Serial pad signal
output reg sclk,
input miso,
output reg mosi,
output reg ss,
// Wishbone slave interface
input wb_clk_i,
input wb_rst_i,
input [8:0] wb_dat_i,
output reg [7:0] wb_dat_o,
input wb_we_i,
input [1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output reg wb_ack_o
);
// Registers and nets
wire op;
wire start;
wire send;
reg [7:0] tr;
reg st;
reg [7:0] sft;
reg [1:0] clk_div;
// Continuous assignments
assign op = wb_stb_i & wb_cyc_i;
assign start = !st & op;
assign send = start & wb_we_i & wb_sel_i[0];
// Behaviour
// mosi
always @(posedge wb_clk_i)
mosi <= wb_rst_i ? 1'b1
: (clk_div==2'b10 ? (send ? wb_dat_i[7] : tr[7]) : mosi);
// tr
always @(posedge wb_clk_i)
tr <= wb_rst_i ? 8'hff
: (clk_div==2'b10 ? { (send ?
wb_dat_i[6:0] : tr[6:0]), 1'b1 } : tr);
// wb_ack_o
always @(posedge wb_clk_i)
wb_ack_o <= wb_rst_i ? 1'b0
: (wb_ack_o ? 1'b0 : (sft[0] && clk_div==2'b00));
// sft
always @(posedge wb_clk_i)
sft <= wb_rst_i ? 8'h0
: (clk_div==2'b10 ? { start, sft[7:1] } : sft);
// st
always @(posedge wb_clk_i)
st <= wb_rst_i ? 1'b0 : (st ? !sft[0] : op && clk_div==2'b10);
// wb_dat_o
always @(posedge wb_clk_i)
wb_dat_o <= wb_rst_i ? 8'h0
: ((op && clk_div==2'b0) ?
{ wb_dat_o[6:0], miso } : wb_dat_o);
// sclk
always @(posedge wb_clk_i)
sclk <= wb_rst_i ? 1'b1
: (clk_div[0] ? sclk : !(op & clk_div[1]));
// ss
always @(negedge wb_clk_i)
ss <= wb_rst_i ? 1'b1
: ((op & wb_we_i & wb_sel_i[1]) ? wb_dat_i[8] : ss);
// clk_div
always @(posedge wb_clk_i) clk_div <= clk_div - 2'd1;
endmodule
|
// IS61LV25616 Asynchronous SRAM, 256K x 16 = 4M; speed: 10ns.
// Note; 1) Please include "+define+ OEb" in running script if you want to check
// timing in the case of OE_ being set.
// 2) Please specify access time by defining tAC_10 or tAC_12.
`define OEb
`define tAC_10 //tAC_10 or tAC_12 defines different parameters
`timescale 1ns/1ns
module is61lv25616 (A, IO, CE_, OE_, WE_, LB_, UB_);
parameter dqbits = 16;
parameter memdepth = 262143;
parameter addbits = 18;
parameter Toha = 2;
parameter Tsa = 2;
`ifdef tAC_10 //if "`define tAC_10 " at beginning,sentences below are compiled
parameter Taa = 10,
Thzce = 3,
Thzwe = 5;
`endif
`ifdef tAC_12 //if "`define tAC_12 " at beginning,sentences below are compiled
parameter Taa = 12,
Thzce = 5,
Thzwe = 6;
`endif
input CE_, OE_, WE_, LB_, UB_;
input [(addbits - 1) : 0] A;
inout [(dqbits - 1) : 0] IO;
wire [(dqbits - 1) : 0] dout;
reg [(dqbits/2 - 1) : 0] bank0 [0 : memdepth];
reg [(dqbits/2 - 1) : 0] bank1 [0 : memdepth];
//array to simulate SRAM
// wire [(dqbits - 1) : 0] memprobe = {bank1[A], bank0[A]};
wire r_en = WE_ & (~CE_) & (~OE_); //WE=1,CE=OE=0 Read
wire w_en = (~WE_) & (~CE_) & ((~LB_) | (~UB_)); //WE=CE=0,LB or UB="0",OE=x Write
assign #(r_en ? Taa : Thzce) IO = r_en ? dout : 16\'bz;
initial
$timeformat (-9, 0.1, " ns", 10); //show current simulation time
assign dout [(dqbits/2 - 1) : 0] = LB_ ? 8\'bz : bank0[A];
assign dout [(dqbits - 1) : (dqbits/2)] = UB_ ? 8\'bz : bank1[A];
always @(A or w_en)
begin
#Tsa //address setup time
if (w_en)
#Thzwe
begin
bank0[A] = LB_ ? bank0[A] : IO [(dqbits/2 - 1) : 0];
bank1[A] = UB_ ? bank1[A] : IO [(dqbits - 1) : (dqbits/2)];
end
end
// Timing Check
`ifdef tAC_10
specify //sepcify delay
specparam
tSA = 0,
tAW = 8,
tSCE = 8,
tSD = 6,
tPWE2 = 10,
tPWE1 = 8,
tPBW = 8;
`else
`ifdef tAC_12
specify
specparam
tSA = 0,
tAW = 8,
tSCE = 8,
tSD = 6,
tPWE2 = 12,
tPWE1 = 8,
tPBW = 8;
`endif
`endif
$setup (A, negedge CE_, tSA);
$setup (A, posedge CE_, tAW);
$setup (IO, posedge CE_, tSD);
$setup (A, negedge WE_, tSA);
$setup (IO, posedge WE_, tSD);
$setup (A, negedge LB_, tSA);
$setup (A, negedge UB_, tSA);
$width (negedge CE_, tSCE);
$width (negedge LB_, tPBW);
$width (negedge UB_, tPBW);
`ifdef OEb
$width (negedge WE_, tPWE1);
`else
$width (negedge WE_, tPWE2);
`endif
endspecify
endmodule
|
/*
* Arithmetic and logical operations for Zet
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_arlog (
input [15:0] x,
input [15:0] y,
input [ 2:0] f,
output [15:0] o,
input word_op,
input cfi,
output cfo,
output afo,
output ofo
);
// Net declarations
wire [15:0] op2;
wire [15:0] outadd;
wire [15:0] outlog;
wire ci;
wire cfoadd;
wire log;
wire xs;
wire ys;
wire os;
// Module instances
zet_fulladd16 fulladd16 ( // We instantiate only one adder
.x (x), // to have less hardware
.y (op2),
.ci (ci),
.co (cfoadd),
.z (outadd),
.s (f[0])
);
// Assignemnts
assign op2 = f[0] ? ~y /* sbb,sub,cmp */
: y; /* add, adc */
assign ci = f[2] | ~f[2] & f[1] & (!f[0] & cfi
| f[0] & ~cfi);
assign log = f[2:0]==3'd1 || f[2:0]==3'd4 || f[2:0]==3'd6;
assign afo = !log & (x[4] ^ y[4] ^ outadd[4]);
assign cfo = !log & (word_op ? cfoadd : (x[8]^y[8]^outadd[8]));
assign xs = word_op ? x[15] : x[7];
assign ys = word_op ? y[15] : y[7];
assign os = word_op ? outadd[15] : outadd[7];
assign ofo = !log &
(f[0] ? (~xs & ys & os | xs & ~ys & ~os)
: (~xs & ~ys & os | xs & ys & ~os));
assign outlog = f[2] ? (f[1] ? x^y : x&y) : x|y;
assign o = log ? outlog : outadd;
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
* adjusted to FML 8x16 by Zeus Gomez Marmolejo <[email protected]>
* updated to include Direct Cache Bus by Charley Picker <[email protected]>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module fmlbrg_tagmem #(
\tparameter depth = 2,
\tparameter width = 2
) (
\tinput sys_clk,
\t/* Primary port (read-write) */
\tinput [depth-1:0] a,
\tinput we,
\tinput [width-1:0] di,
\toutput [width-1:0] dout,
\t/* Secondary port (read-only) */
\tinput [depth-1:0] a2,
\toutput [width-1:0] do2
);
reg [width-1:0] tags[0:(1 << depth)-1];
reg [depth-1:0] a_r;
reg [depth-1:0] a2_r;
always @(posedge sys_clk) begin
\ta_r <= a;
\ta2_r <= a2;
end
always @(posedge sys_clk) begin
\tif(we)
\t\ttags[a] <= di;
end
assign dout = tags[a_r];
assign do2 = tags[a2_r];
// synthesis translate_off
integer i;
initial begin
\tfor(i=0;i<(1 << depth);i=i+1)
\t\ttags[i] = 0;
end
// synthesis translate_on
endmodule
|
/*
* This module sends commands to the PS2 interface
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module ps2_mouse_cmdout (
input clk,
input reset,
input [7:0] the_command,
input send_command,
input ps2_clk_posedge,
input ps2_clk_negedge,
input inhibit,
inout ps2_clk,
inout ps2_dat,
output reg command_was_sent,
output reg error_communication_timed_out
);
// --------------------------------------------------------------------
// Parameter Declarations , 1/12.5mhz => 0.08us
// --------------------------------------------------------------------
parameter CLOCK_CYCLES_FOR_101US = 1262; // Timing info for initiating
parameter NUMBER_OF_BITS_FOR_101US = 13; // Host-to-Device communication
parameter COUNTER_INCREMENT_FOR_101US = 13'h0001; // when using a 12.5MHz system clock
parameter CLOCK_CYCLES_FOR_15MS = 187500; // Timing info for start of
parameter NUMBER_OF_BITS_FOR_15MS = 20; // transmission error when
parameter COUNTER_INCREMENT_FOR_15MS = 20'h00001; // using a 12.5MHz system clock
parameter CLOCK_CYCLES_FOR_2MS = 25000; // Timing info for sending
parameter NUMBER_OF_BITS_FOR_2MS = 17; // data error when
parameter COUNTER_INCREMENT_FOR_2MS = 17'h00001; // using a 12.5MHz system clock
// --------------------------------------------------------------------
// Constant Declarations
// --------------------------------------------------------------------
parameter PS2_STATE_0_IDLE = 3'h0,
PS2_STATE_1_INITIATE_COMMUNICATION = 3'h1,
PS2_STATE_2_WAIT_FOR_CLOCK = 3'h2,
PS2_STATE_3_TRANSMIT_DATA = 3'h3,
PS2_STATE_4_TRANSMIT_STOP_BIT = 3'h4,
PS2_STATE_5_RECEIVE_ACK_BIT = 3'h5,
PS2_STATE_6_COMMAND_WAS_SENT = 3'h6,
PS2_STATE_7_TRANSMISSION_ERROR = 3'h7;
// --------------------------------------------------------------------
// Internal wires and registers Declarations
// --------------------------------------------------------------------
reg [3:0] cur_bit; // Internal Registers
reg [8:0] ps2_command;
reg [NUMBER_OF_BITS_FOR_101US:1] command_initiate_counter;
reg [NUMBER_OF_BITS_FOR_15MS:1] waiting_counter;
reg [NUMBER_OF_BITS_FOR_2MS:1] transfer_counter;
reg [2:0] ns_ps2_transmitter; // State Machine Registers
reg [2:0] s_ps2_transmitter;
// --------------------------------------------------------------------
// Finite State Machine(s)
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) s_ps2_transmitter <= PS2_STATE_0_IDLE;
else s_ps2_transmitter <= ns_ps2_transmitter;
end
always @(*) begin // Defaults
ns_ps2_transmitter = PS2_STATE_0_IDLE;
case (s_ps2_transmitter)
PS2_STATE_0_IDLE:
begin
if (send_command == 1'b1) ns_ps2_transmitter = PS2_STATE_1_INITIATE_COMMUNICATION;
else ns_ps2_transmitter = PS2_STATE_0_IDLE;
end
PS2_STATE_1_INITIATE_COMMUNICATION:
begin
if (command_initiate_counter == CLOCK_CYCLES_FOR_101US)
ns_ps2_transmitter = PS2_STATE_2_WAIT_FOR_CLOCK;
else
ns_ps2_transmitter = PS2_STATE_1_INITIATE_COMMUNICATION;
end
PS2_STATE_2_WAIT_FOR_CLOCK:
begin
if (ps2_clk_negedge == 1'b1)
ns_ps2_transmitter = PS2_STATE_3_TRANSMIT_DATA;
else if (waiting_counter == CLOCK_CYCLES_FOR_15MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_2_WAIT_FOR_CLOCK;
end
PS2_STATE_3_TRANSMIT_DATA:
begin
if ((cur_bit == 4'd8) && (ps2_clk_negedge == 1'b1))
ns_ps2_transmitter = PS2_STATE_4_TRANSMIT_STOP_BIT;
else if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_3_TRANSMIT_DATA;
end
PS2_STATE_4_TRANSMIT_STOP_BIT:
begin
if (ps2_clk_negedge == 1'b1)
ns_ps2_transmitter = PS2_STATE_5_RECEIVE_ACK_BIT;
else if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_4_TRANSMIT_STOP_BIT;
end
PS2_STATE_5_RECEIVE_ACK_BIT:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_transmitter = PS2_STATE_6_COMMAND_WAS_SENT;
else if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_5_RECEIVE_ACK_BIT;
end
PS2_STATE_6_COMMAND_WAS_SENT:
begin
if (send_command == 1'b0)
ns_ps2_transmitter = PS2_STATE_0_IDLE;
else
ns_ps2_transmitter = PS2_STATE_6_COMMAND_WAS_SENT;
end
PS2_STATE_7_TRANSMISSION_ERROR:
begin
if (send_command == 1'b0)
ns_ps2_transmitter = PS2_STATE_0_IDLE;
else
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
end
default:
begin
ns_ps2_transmitter = PS2_STATE_0_IDLE;
end
endcase
end
// --------------------------------------------------------------------
// Sequential logic
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) ps2_command <= 9'h000;
else if(s_ps2_transmitter == PS2_STATE_0_IDLE)
ps2_command <= {(^the_command) ^ 1'b1, the_command};
end
always @(posedge clk) begin
if(reset == 1'b1) command_initiate_counter <= {NUMBER_OF_BITS_FOR_101US{1'b0}};
else if((s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) &&
(command_initiate_counter != CLOCK_CYCLES_FOR_101US))
command_initiate_counter <=
command_initiate_counter + COUNTER_INCREMENT_FOR_101US;
else if(s_ps2_transmitter != PS2_STATE_1_INITIATE_COMMUNICATION)
command_initiate_counter <= {NUMBER_OF_BITS_FOR_101US{1'b0}};
end
always @(posedge clk) begin
if(reset == 1'b1) waiting_counter <= {NUMBER_OF_BITS_FOR_15MS{1'b0}};
else if((s_ps2_transmitter == PS2_STATE_2_WAIT_FOR_CLOCK) &&
(waiting_counter != CLOCK_CYCLES_FOR_15MS))
waiting_counter <= waiting_counter + COUNTER_INCREMENT_FOR_15MS;
else if(s_ps2_transmitter != PS2_STATE_2_WAIT_FOR_CLOCK)
waiting_counter <= {NUMBER_OF_BITS_FOR_15MS{1'b0}};
end
always @(posedge clk) begin
if(reset == 1'b1) transfer_counter <= {NUMBER_OF_BITS_FOR_2MS{1'b0}};
else begin
if((s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) ||
(s_ps2_transmitter == PS2_STATE_4_TRANSMIT_STOP_BIT) ||
(s_ps2_transmitter == PS2_STATE_5_RECEIVE_ACK_BIT))
begin
if(transfer_counter != CLOCK_CYCLES_FOR_2MS)
transfer_counter <= transfer_counter + COUNTER_INCREMENT_FOR_2MS;
end
else transfer_counter <= {NUMBER_OF_BITS_FOR_2MS{1'b0}};
end
end
always @(posedge clk) begin
if(reset == 1'b1) cur_bit <= 4'h0;
else if((s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) &&
(ps2_clk_negedge == 1'b1))
cur_bit <= cur_bit + 4'h1;
else if(s_ps2_transmitter != PS2_STATE_3_TRANSMIT_DATA)
cur_bit <= 4'h0;
end
always @(posedge clk) begin
if(reset == 1'b1) command_was_sent <= 1'b0;
else if(s_ps2_transmitter == PS2_STATE_6_COMMAND_WAS_SENT)
command_was_sent <= 1'b1;
else if(send_command == 1'b0) command_was_sent <= 1'b0;
end
always @(posedge clk) begin
if(reset == 1'b1) error_communication_timed_out <= 1'b0;
else if(s_ps2_transmitter == PS2_STATE_7_TRANSMISSION_ERROR)
error_communication_timed_out <= 1'b1;
else if(send_command == 1'b0)
error_communication_timed_out <= 1'b0;
end
// --------------------------------------------------------------------
// Combinational logic
// --------------------------------------------------------------------
assign ps2_clk = (s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION || inhibit) ? 1'b0 : 1'bz;
assign ps2_dat = (s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) ? ps2_command[cur_bit] :
(s_ps2_transmitter == PS2_STATE_2_WAIT_FOR_CLOCK) ? 1'b0 :
((s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) &&
(command_initiate_counter[NUMBER_OF_BITS_FOR_101US] == 1'b1)) ? 1'b0 : 1'bz;
endmodule
|
/*\r
* Zet SoC top level file for Altera DE2 board\r
* Copyright (C) 2009, 2010 Zeus Gomez Marmolejo <[email protected]>\r
*\r
* This file is part of the Zet processor. This processor is free\r
* hardware; you can redistribute it and/or modify it under the terms of\r
* the GNU General Public License as published by the Free Software\r
* Foundation; either version 3, or (at your option) any later version.\r
*\r
* Zet is distrubuted in the hope that it will be useful, but WITHOUT\r
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public\r
* License for more details.\r
*\r
* You should have received a copy of the GNU General Public License\r
* along with Zet; see the file COPYING. If not, see\r
* <http://www.gnu.org/licenses/>.\r
*/\r
\r
module kotku (\r
// Clock input\r
input clk_50_,\r
\r
// General purpose IO\r
input [7:0] sw_,\r
input key_,\r
output [6:0] hex0_,\r
output [6:0] hex1_,\r
output [6:0] hex2_,\r
output [6:0] hex3_,\r
output [9:0] ledr_,\r
output [7:0] ledg_,\r
\r
// flash signals\r
output [21:0] flash_addr_,\r
input [ 7:0] flash_data_,\r
output flash_oe_n_,\r
output flash_ce_n_,\r
\r
// sdram signals\r
output [11:0] sdram_addr_,\r
inout [15:0] sdram_data_,\r
output [ 1:0] sdram_ba_,\r
output sdram_ras_n_,\r
output sdram_cas_n_,\r
output sdram_ce_,\r
output sdram_clk_,\r
output sdram_we_n_,\r
output sdram_cs_n_,\r
\r
// VGA signals\r
output [ 3:0] tft_lcd_r_,\r
output [ 3:0] tft_lcd_g_,\r
output [ 3:0] tft_lcd_b_,\r
output tft_lcd_hsync_,\r
output tft_lcd_vsync_,\r
output tft_lcd_clk_,\r
\r
// UART signals\r
output uart_txd_,\r
\r
// PS2 signals\r
input ps2_kclk_, // PS2 keyboard Clock\r
inout ps2_kdat_, // PS2 Keyboard Data\r
inout ps2_mclk_, // PS2 Mouse Clock\r
inout ps2_mdat_, // PS2 Mouse Data\r
\r
// SD card signals\r
output sd_sclk_,\r
input sd_miso_,\r
output sd_mosi_,\r
output sd_ss_,\r
\r
// I2C for audio codec\r
inout i2c_sdat_,\r
output i2c_sclk_,\r
\r
// Audio codec signals\r
input aud_daclrck_,\r
output aud_dacdat_,\r
input aud_bclk_,\r
output aud_xck_\r
);\r
\r
// Registers and nets\r
wire clk;\r
wire rst_lck;\r
wire [15:0] dat_o;\r
wire [15:0] dat_i;\r
wire [19:1] adr;\r
wire we;\r
wire tga;\r
wire [ 1:0] sel;\r
wire stb;\r
wire cyc;\r
wire ack;\r
wire lock;\r
\r
// wires to BIOS ROM\r
wire [15:0] rom_dat_o;\r
wire [15:0] rom_dat_i;\r
wire rom_tga_i;\r
wire [19:1] rom_adr_i;\r
wire [ 1:0] rom_sel_i;\r
wire rom_we_i;\r
wire rom_cyc_i;\r
wire rom_stb_i;\r
wire rom_ack_o;\r
\r
// wires to flash controller\r
wire [15:0] fl_dat_o;\r
wire [15:0] fl_dat_i;\r
wire fl_tga_i;\r
wire [19:1] fl_adr_i;\r
wire [ 1:0] fl_sel_i;\r
wire fl_we_i;\r
wire fl_cyc_i;\r
wire fl_stb_i;\r
wire fl_ack_o;\r
\r
// Unused outputs\r
wire flash_we_n_;\r
wire flash_rst_n_;\r
wire [1:0] sdram_dqm_;\r
wire [2:0] s19_17;\r
\r
// Unused inputs\r
wire uart_rxd_;\r
wire aud_adcdat_;\r
\r
// wires to vga controller\r
wire [15:0] vga_dat_o;\r
wire [15:0] vga_dat_i;\r
wire vga_tga_i;\r
wire [19:1] vga_adr_i;\r
wire [ 1:0] vga_sel_i;\r
wire vga_we_i;\r
wire vga_cyc_i;\r
wire vga_stb_i;\r
wire vga_ack_o;\r
\r
// cross clock domain synchronized signals\r
wire [15:0] vga_dat_o_s;\r
wire [15:0] vga_dat_i_s;\r
wire vga_tga_i_s;\r
wire [19:1] vga_adr_i_s;\r
wire [ 1:0] vga_sel_i_s;\r
wire vga_we_i_s;\r
wire vga_cyc_i_s;\r
wire vga_stb_i_s;\r
wire vga_ack_o_s;\r
\r
// wires to uart controller\r
wire [15:0] uart_dat_o;\r
wire [15:0] uart_dat_i;\r
wire uart_tga_i;\r
wire [19:1] uart_adr_i;\r
wire [ 1:0] uart_sel_i;\r
wire uart_we_i;\r
wire uart_cyc_i;\r
wire uart_stb_i;\r
wire uart_ack_o;\r
\r
// wires to keyboard controller\r
wire [15:0] keyb_dat_o;\r
wire [15:0] keyb_dat_i;\r
wire keyb_tga_i;\r
wire [19:1] keyb_adr_i;\r
wire [ 1:0] keyb_sel_i;\r
wire keyb_we_i;\r
wire keyb_cyc_i;\r
wire keyb_stb_i;\r
wire keyb_ack_o;\r
\r
// wires to timer controller\r
wire [15:0] timer_dat_o;\r
wire [15:0] timer_dat_i;\r
wire timer_tga_i;\r
wire [19:1] timer_adr_i;\r
wire [ 1:0] timer_sel_i;\r
wire timer_we_i;\r
wire timer_cyc_i;\r
wire timer_stb_i;\r
wire timer_ack_o;\r
\r
// wires to sd controller\r
wire [19:1] sd_adr_i;\r
wire [ 7:0] sd_dat_o;\r
wire [15:0] sd_dat_i;\r
wire sd_tga_i;\r
wire [ 1:0] sd_sel_i;\r
wire sd_we_i;\r
wire sd_cyc_i;\r
wire sd_stb_i;\r
wire sd_ack_o;\r
\r
// wires to sd bridge\r
wire [19:1] sd_adr_i_s;\r
wire [15:0] sd_dat_o_s;\r
wire [15:0] sd_dat_i_s;\r
wire sd_tga_i_s;\r
wire [ 1:0] sd_sel_i_s;\r
wire sd_we_i_s;\r
wire sd_cyc_i_s;\r
wire sd_stb_i_s;\r
wire sd_ack_o_s;\r
\r
// wires to gpio controller\r
wire [15:0] gpio_dat_o;\r
wire [15:0] gpio_dat_i;\r
wire gpio_tga_i;\r
wire [19:1] gpio_adr_i;\r
wire [ 1:0] gpio_sel_i;\r
wire gpio_we_i;\r
wire gpio_cyc_i;\r
wire gpio_stb_i;\r
wire gpio_ack_o;\r
\r
// wires to SDRAM controller\r
wire [19:1] fmlbrg_adr_s;\r
wire [15:0] fmlbrg_dat_w_s;\r
wire [15:0] fmlbrg_dat_r_s;\r
wire [ 1:0] fmlbrg_sel_s;\r
wire fmlbrg_cyc_s;\r
wire fmlbrg_stb_s;\r
wire fmlbrg_tga_s;\r
wire fmlbrg_we_s;\r
wire fmlbrg_ack_s;\r
\r
wire [19:1] fmlbrg_adr;\r
wire [15:0] fmlbrg_dat_w;\r
wire [15:0] fmlbrg_dat_r;\r
wire [ 1:0] fmlbrg_sel;\r
wire fmlbrg_cyc;\r
wire fmlbrg_stb;\r
wire fmlbrg_tga;\r
wire fmlbrg_we;\r
wire fmlbrg_ack;\r
\r
wire [19:1] csrbrg_adr_s;\r
wire [15:0] csrbrg_dat_w_s;\r
wire [15:0] csrbrg_dat_r_s;\r
wire [ 1:0] csrbrg_sel_s;\r
wire csrbrg_cyc_s;\r
wire csrbrg_stb_s;\r
wire csrbrg_tga_s;\r
wire csrbrg_we_s;\r
wire csrbrg_ack_s;\r
\r
wire [19:1] csrbrg_adr;\r
wire [15:0] csrbrg_dat_w;\r
wire [15:0] csrbrg_dat_r;\r
wire [ 1:0] csrbrg_sel;\r
wire csrbrg_tga;\r
wire csrbrg_cyc;\r
wire csrbrg_stb;\r
wire csrbrg_we;\r
wire csrbrg_ack;\r
\r
wire sb_cyc_i;\r
wire sb_stb_i;\r
\r
wire [ 2:0] csr_a;\r
wire csr_we;\r
wire [15:0] csr_dw;\r
wire [15:0] csr_dr_hpdmc;\r
\r
// wires to hpdmc slave interface \r
wire [22:0] fml_adr;\r
wire fml_stb;\r
wire fml_we;\r
wire fml_ack;\r
wire [ 1:0] fml_sel;\r
wire [15:0] fml_di;\r
wire [15:0] fml_do;\r
\r
// wires to fml bridge master interface \r
wire [19:0] fml_fmlbrg_adr;\r
wire fml_fmlbrg_stb;\r
wire fml_fmlbrg_we;\r
wire fml_fmlbrg_ack;\r
wire [ 1:0] fml_fmlbrg_sel;\r
wire [15:0] fml_fmlbrg_di;\r
wire [15:0] fml_fmlbrg_do;\r
\r
// wires to VGA CPU FML master interface\r
wire [19:0] vga_cpu_fml_adr; // 1MB Memory Address range\r
wire vga_cpu_fml_stb;\r
wire vga_cpu_fml_we;\r
wire vga_cpu_fml_ack;\r
wire [1:0] vga_cpu_fml_sel;\r
wire [15:0] vga_cpu_fml_do;\r
wire [15:0] vga_cpu_fml_di;\r
\r
// wires to VGA LCD FML master interface\r
wire [19:0] vga_lcd_fml_adr; // 1MB Memory Address range\r
wire vga_lcd_fml_stb;\r
wire vga_lcd_fml_we;\r
wire vga_lcd_fml_ack;\r
wire [1:0] vga_lcd_fml_sel;\r
wire [15:0] vga_lcd_fml_do;\r
wire [15:0] vga_lcd_fml_di;\r
\r
// wires to default stb/ack\r
wire def_cyc_i;\r
wire def_stb_i;\r
wire [15:0] sw_dat_o;\r
wire sdram_clk;\r
wire vga_clk;\r
\r
wire [ 7:0] intv;\r
wire [ 2:0] iid;\r
wire intr;\r
wire inta;\r
\r
wire nmi_pb;\r
wire nmi;\r
wire nmia;\r
\r
wire [19:0] pc;\r
reg [16:0] rst_debounce;\r
\r
wire timer_clk;\r
wire timer2_o;\r
\r
// Audio only signals\r
wire [ 7:0] aud_dat_o;\r
wire aud_cyc_i;\r
wire aud_ack_o;\r
wire aud_sel_cond;\r
\r
// Keyboard-audio shared signals\r
wire [ 7:0] kaud_dat_o;\r
wire kaud_cyc_i;\r
wire kaud_ack_o;\r
\r
`ifndef SIMULATION\r
/*\r
* Debounce it (counter holds reset for 10.49ms),\r
* and generate power-on reset.\r
*/\r
initial rst_debounce <= 17'h1FFFF;\r
reg rst;\r
initial rst <= 1'b1;\r
always @(posedge clk) begin\r
if(~rst_lck) /* reset is active low */\r
rst_debounce <= 17'h1FFFF;\r
else if(rst_debounce != 17'd0)\r
rst_debounce <= rst_debounce - 17'd1;\r
rst <= rst_debounce != 17'd0;\r
end\r
`else\r
wire rst;\r
assign rst = !rst_lck;\r
`endif\r
\r
// Module instantiations\r
pll pll (\r
.inclk0 (clk_50_),\r
.c0 (sdram_clk), // 100 Mhz\r
.c1 (), // 25 Mhz\r
.c2 (clk), // 12.5 Mhz\r
.locked (lock)\r
);\r
\r
clk_gen #(\r
.res (21),\r
.phase (21'd100091)\r
) timerclk (\r
.clk_i (vga_clk), // 25 MHz\r
.rst_i (rst),\r
.clk_o (timer_clk) // 1.193178 MHz (required 1.193182 MHz)\r
);\r
\r
clk_gen #(\r
.res (18),\r
.phase (18'd29595)\r
) audioclk (\r
.clk_i (sdram_clk), // 100 MHz (use highest freq to minimize jitter)\r
.rst_i (rst),\r
.clk_o (aud_xck_) // 11.28960 MHz (required 11.28960 MHz)\r
);\r
\r
bootrom bootrom (\r
.clk (clk), // Wishbone slave interface\r
.rst (rst),\r
.wb_dat_i (rom_dat_i),\r
.wb_dat_o (rom_dat_o),\r
.wb_adr_i (rom_adr_i),\r
.wb_we_i (rom_we_i ),\r
.wb_tga_i (rom_tga_i),\r
.wb_stb_i (rom_stb_i),\r
.wb_cyc_i (rom_cyc_i),\r
.wb_sel_i (rom_sel_i),\r
.wb_ack_o (rom_ack_o)\r
);\r
\r
flash8 flash8 (\r
// Wishbone slave interface\r
.wb_clk_i (clk), // Main Clock\r
.wb_rst_i (rst), // Reset Line\r
.wb_adr_i (fl_adr_i[1]), // Address lines\r
.wb_sel_i (fl_sel_i), // Select lines\r
.wb_dat_i (fl_dat_i), // Command to send\r
.wb_dat_o (fl_dat_o), // Received data\r
.wb_cyc_i (fl_cyc_i), // Cycle\r
.wb_stb_i (fl_stb_i), // Strobe\r
.wb_we_i (fl_we_i), // Write enable\r
.wb_ack_o (fl_ack_o), // Normal bus termination\r
\r
// Pad signals\r
.flash_addr_ (flash_addr_),\r
.flash_data_ (flash_data_),\r
.flash_we_n_ (flash_we_n_),\r
.flash_oe_n_ (flash_oe_n_),\r
.flash_ce_n_ (flash_ce_n_),\r
.flash_rst_n_ (flash_rst_n_)\r
);\r
\r
wb_abrgr wb_fmlbrg (\r
.sys_rst (rst),\r
\r
// Wishbone slave interface\r
.wbs_clk_i (clk),\r
.wbs_adr_i (fmlbrg_adr_s),\r
.wbs_dat_i (fmlbrg_dat_w_s),\r
.wbs_dat_o (fmlbrg_dat_r_s),\r
.wbs_sel_i (fmlbrg_sel_s),\r
.wbs_tga_i (fmlbrg_tga_s),\r
.wbs_stb_i (fmlbrg_stb_s),\r
.wbs_cyc_i (fmlbrg_cyc_s),\r
.wbs_we_i (fmlbrg_we_s),\r
.wbs_ack_o (fmlbrg_ack_s),\r
\r
// Wishbone master interface\r
.wbm_clk_i (sdram_clk),\r
.wbm_adr_o (fmlbrg_adr),\r
.wbm_dat_o (fmlbrg_dat_w),\r
.wbm_dat_i (fmlbrg_dat_r),\r
.wbm_sel_o (fmlbrg_sel),\r
.wbm_tga_o (fmlbrg_tga),\r
.wbm_stb_o (fmlbrg_stb),\r
.wbm_cyc_o (fmlbrg_cyc),\r
.wbm_we_o (fmlbrg_we),\r
.wbm_ack_i (fmlbrg_ack)\r
);\r
\r
fmlbrg #(\r
.fml_depth (20), // 8086 can only address 1 MB\r
.cache_depth (10) // 1 Kbyte cache\r
) fmlbrg (\r
.sys_clk (sdram_clk),\r
.sys_rst (rst),\r
\r
// Wishbone slave interface\r
.wb_adr_i (fmlbrg_adr),\r
.wb_cti_i(3'b0),\r
.wb_dat_i (fmlbrg_dat_w),\r
.wb_dat_o (fmlbrg_dat_r),\r
.wb_sel_i (fmlbrg_sel),\r
.wb_cyc_i (fmlbrg_cyc),\r
.wb_stb_i (fmlbrg_stb),\r
.wb_tga_i (fmlbrg_tga),\r
.wb_we_i (fmlbrg_we),\r
.wb_ack_o (fmlbrg_ack),\r
\r
// FML master 1 interface\r
.fml_adr (fml_fmlbrg_adr),\r
.fml_stb (fml_fmlbrg_stb),\r
.fml_we (fml_fmlbrg_we),\r
.fml_ack (fml_fmlbrg_ack),\r
.fml_sel (fml_fmlbrg_sel),\r
.fml_do (fml_fmlbrg_do),\r
.fml_di (fml_fmlbrg_di),\r
\r
// Direct Cache Bus\r
.dcb_stb(1'b0),\r
.dcb_adr(20'b0),\r
.dcb_dat(),\r
.dcb_hit()\r
\r
);\r
\r
wb_abrgr wb_csrbrg (\r
.sys_rst (rst),\r
\r
// Wishbone slave interface\r
.wbs_clk_i (clk),\r
.wbs_adr_i (csrbrg_adr_s),\r
.wbs_dat_i (csrbrg_dat_w_s),\r
.wbs_dat_o (csrbrg_dat_r_s),\r
.wbs_sel_i (csrbrg_sel_s),\r
.wbs_tga_i (csrbrg_tga_s),\r
.wbs_stb_i (csrbrg_stb_s),\r
.wbs_cyc_i (csrbrg_cyc_s),\r
.wbs_we_i (csrbrg_we_s),\r
.wbs_ack_o (csrbrg_ack_s),\r
\r
// Wishbone master interface\r
.wbm_clk_i (sdram_clk),\r
.wbm_adr_o (csrbrg_adr),\r
.wbm_dat_o (csrbrg_dat_w),\r
.wbm_dat_i (csrbrg_dat_r),\r
.wbm_sel_o (csrbrg_sel),\r
.wbm_tga_o (csrbrg_tga),\r
.wbm_stb_o (csrbrg_stb),\r
.wbm_cyc_o (csrbrg_cyc),\r
.wbm_we_o (csrbrg_we),\r
.wbm_ack_i (csrbrg_ack)\r
);\r
\r
csrbrg csrbrg (\r
.sys_clk (sdram_clk),\r
.sys_rst (rst),\r
\r
// Wishbone slave interface\r
.wb_adr_i (csrbrg_adr[3:1]),\r
.wb_dat_i (csrbrg_dat_w),\r
.wb_dat_o (csrbrg_dat_r),\r
.wb_cyc_i (csrbrg_cyc),\r
.wb_stb_i (csrbrg_stb),\r
.wb_we_i (csrbrg_we),\r
.wb_ack_o (csrbrg_ack),\r
\r
// CSR master interface\r
.csr_a (csr_a),\r
.csr_we (csr_we),\r
.csr_do (csr_dw),\r
.csr_di (csr_dr_hpdmc)\r
);\r
\r
fmlarb #(\r
.fml_depth (23)\r
) fmlarb (\r
.sys_clk (sdram_clk),\r
.sys_rst (rst),\r
\r
// Master 0 interface - VGA LCD FML (Reserved video memory port has highest priority)\r
.m0_adr ({3'b001, vga_lcd_fml_adr}), // 1 - 2 MB Addressable memory range\r
.m0_stb (vga_lcd_fml_stb),\r
.m0_we (vga_lcd_fml_we),\r
.m0_ack (vga_lcd_fml_ack),\r
.m0_sel (vga_lcd_fml_sel),\r
.m0_di (vga_lcd_fml_do),\r
.m0_do (vga_lcd_fml_di),\r
\r
// Master 1 interface - Wishbone FML bridge\r
.m1_adr ({3'b000, fml_fmlbrg_adr}), // 0 - 1 MB Addressable memory range\r
.m1_stb (fml_fmlbrg_stb),\r
.m1_we (fml_fmlbrg_we),\r
.m1_ack (fml_fmlbrg_ack),\r
.m1_sel (fml_fmlbrg_sel),\r
.m1_di (fml_fmlbrg_do),\r
.m1_do (fml_fmlbrg_di),\r
\r
// Master 2 interface - VGA CPU FML\r
.m2_adr ({3'b001, vga_cpu_fml_adr}), // 1 - 2 MB Addressable memory range\r
.m2_stb (vga_cpu_fml_stb),\r
.m2_we (vga_cpu_fml_we),\r
.m2_ack (vga_cpu_fml_ack),\r
.m2_sel (vga_cpu_fml_sel),\r
.m2_di (vga_cpu_fml_do),\r
.m2_do (vga_cpu_fml_di),\r
\r
// Master 3 interface - not connected\r
.m3_adr ({3'b010, 20'b0}), // 2 - 3 MB Addressable memory range\r
.m3_stb (1'b0),\r
.m3_we (1'b0),\r
.m3_ack (),\r
.m3_sel (2'b00),\r
.m3_di (16'h0000),\r
.m3_do (),\r
\r
// Master 4 interface - not connected\r
.m4_adr ({3'b011, 20'b0}), // 3 - 4 MB Addressable memory range\r
.m4_stb (1'b0),\r
.m4_we (1'b0),\r
.m4_ack (),\r
.m4_sel (2'b00),\r
.m4_di (16'h0000),\r
.m4_do (),\r
\r
// Master 5 interface - not connected\r
.m5_adr ({3'b100, 20'b0}), // 4 - 5 MB Addressable memory range\r
.m5_stb (1'b0),\r
.m5_we (1'b0),\r
.m5_ack (),\r
.m5_sel (2'b00),\r
.m5_di (16'h0000),\r
.m5_do (),\r
\r
// Arbitrer Slave interface - connected to hpdmc\r
.s_adr (fml_adr),\r
.s_stb (fml_stb),\r
.s_we (fml_we),\r
.s_ack (fml_ack),\r
.s_sel (fml_sel),\r
.s_di (fml_di),\r
.s_do (fml_do)\r
);\r
\r
hpdmc #(\r
.csr_addr (1'b0),\r
.sdram_depth (23),\r
.sdram_columndepth (8)\r
) hpdmc (\r
.sys_clk (sdram_clk),\r
.sys_rst (rst),\r
\r
// CSR slave interface\r
.csr_a (csr_a),\r
.csr_we (csr_we),\r
.csr_di (csr_dw),\r
.csr_do (csr_dr_hpdmc),\r
\r
// FML slave interface\r
.fml_adr (fml_adr),\r
.fml_stb (fml_stb),\r
.fml_we (fml_we),\r
.fml_ack (fml_ack),\r
.fml_sel (fml_sel),\r
.fml_di (fml_do),\r
.fml_do (fml_di),\r
\r
// SDRAM pad signals\r
.sdram_cke (sdram_ce_),\r
.sdram_cs_n (sdram_cs_n_),\r
.sdram_we_n (sdram_we_n_),\r
.sdram_cas_n (sdram_cas_n_),\r
.sdram_ras_n (sdram_ras_n_),\r
.sdram_dqm (sdram_dqm_),\r
.sdram_adr (sdram_addr_),\r
.sdram_ba (sdram_ba_),\r
.sdram_dq (sdram_data_)\r
);\r
\r
wb_abrgr vga_brg (\r
.sys_rst (rst),\r
\r
// Wishbone slave interface\r
.wbs_clk_i (clk),\r
.wbs_adr_i (vga_adr_i_s),\r
.wbs_dat_i (vga_dat_i_s),\r
.wbs_dat_o (vga_dat_o_s),\r
.wbs_sel_i (vga_sel_i_s),\r
.wbs_tga_i (vga_tga_i_s),\r
.wbs_stb_i (vga_stb_i_s),\r
.wbs_cyc_i (vga_cyc_i_s),\r
.wbs_we_i (vga_we_i_s),\r
.wbs_ack_o (vga_ack_o_s),\r
\r
// Wishbone master interface\r
.wbm_clk_i (sdram_clk),\r
.wbm_adr_o (vga_adr_i),\r
.wbm_dat_o (vga_dat_i),\r
.wbm_dat_i (vga_dat_o),\r
.wbm_sel_o (vga_sel_i),\r
.wbm_tga_o (vga_tga_i),\r
.wbm_stb_o (vga_stb_i),\r
.wbm_cyc_o (vga_cyc_i),\r
.wbm_we_o (vga_we_i),\r
.wbm_ack_i (vga_ack_o)\r
);\r
\r
vga_fml #(\r
.fml_depth (20) // 1MB Memory Address range\r
) vga (\r
.wb_rst_i (rst),\r
\r
// Wishbone slave interface\r
.wb_clk_i (sdram_clk), // 100MHz VGA clock\r
.wb_dat_i (vga_dat_i),\r
.wb_dat_o (vga_dat_o),\r
.wb_adr_i (vga_adr_i[16:1]), // 128K\r
.wb_we_i (vga_we_i),\r
.wb_tga_i (vga_tga_i),\r
.wb_sel_i (vga_sel_i),\r
.wb_stb_i (vga_stb_i),\r
.wb_cyc_i (vga_cyc_i),\r
.wb_ack_o (vga_ack_o),\r
\r
// VGA pad signals\r
.vga_red_o (tft_lcd_r_),\r
.vga_green_o (tft_lcd_g_),\r
.vga_blue_o (tft_lcd_b_),\r
.horiz_sync (tft_lcd_hsync_),\r
.vert_sync (tft_lcd_vsync_),\r
\r
// VGA CPU FML master interface\r
.vga_cpu_fml_adr(vga_cpu_fml_adr),\r
.vga_cpu_fml_stb(vga_cpu_fml_stb),\r
.vga_cpu_fml_we(vga_cpu_fml_we),\r
.vga_cpu_fml_ack(vga_cpu_fml_ack),\r
.vga_cpu_fml_sel(vga_cpu_fml_sel),\r
.vga_cpu_fml_do(vga_cpu_fml_do),\r
.vga_cpu_fml_di(vga_cpu_fml_di),\r
\r
// VGA LCD FML master interface\r
.vga_lcd_fml_adr(vga_lcd_fml_adr),\r
.vga_lcd_fml_stb(vga_lcd_fml_stb),\r
.vga_lcd_fml_we(vga_lcd_fml_we),\r
.vga_lcd_fml_ack(vga_lcd_fml_ack),\r
.vga_lcd_fml_sel(vga_lcd_fml_sel),\r
.vga_lcd_fml_do(vga_lcd_fml_do),\r
.vga_lcd_fml_di(vga_lcd_fml_di),\r
\r
.vga_clk(vga_clk)\r
\r
);\r
\r
// RS232 COM1 Port\r
serial com1 (\r
.wb_clk_i (clk), // Main Clock\r
.wb_rst_i (rst), // Reset Line\r
.wb_adr_i (uart_adr_i[2:1]), // Address lines\r
.wb_sel_i (uart_sel_i), // Select lines\r
.wb_dat_i (uart_dat_i), // Command to send\r
.wb_dat_o (uart_dat_o),\r
.wb_we_i (uart_we_i), // Write enable\r
.wb_stb_i (uart_stb_i),\r
.wb_cyc_i (uart_cyc_i),\r
.wb_ack_o (uart_ack_o),\r
.wb_tgc_o (intv[4]), // Interrupt request\r
\r
.rs232_tx (uart_txd_), // UART signals\r
.rs232_rx (uart_rxd_) // serial input/output\r
);\r
\r
ps2 ps2 (\r
.wb_clk_i (clk), // Main Clock\r
.wb_rst_i (rst), // Reset Line\r
.wb_adr_i (keyb_adr_i[2:1]), // Address lines\r
.wb_sel_i (keyb_sel_i), // Select lines\r
.wb_dat_i (keyb_dat_i), // Command to send to Ethernet\r
.wb_dat_o (keyb_dat_o),\r
.wb_we_i (keyb_we_i), // Write enable\r
.wb_stb_i (keyb_stb_i),\r
.wb_cyc_i (keyb_cyc_i),\r
.wb_ack_o (keyb_ack_o),\r
.wb_tgk_o (intv[1]), // Keyboard Interrupt request\r
.wb_tgm_o (intv[3]), // Mouse Interrupt request\r
\r
.ps2_kbd_clk_ (ps2_kclk_),\r
.ps2_kbd_dat_ (ps2_kdat_),\r
.ps2_mse_clk_ (ps2_mclk_),\r
.ps2_mse_dat_ (ps2_mdat_)\r
);\r
\r
`ifndef SIMULATION\r
/*\r
* Seems that we have a serious bug in Modelsim that prevents\r
* from simulating when this core is present\r
*/\r
speaker speaker (\r
.clk (clk),\r
.rst (rst),\r
\r
.wb_dat_i (keyb_dat_i[15:8]),\r
.wb_dat_o (aud_dat_o),\r
.wb_we_i (keyb_we_i),\r
.wb_stb_i (keyb_stb_i),\r
.wb_cyc_i (aud_cyc_i),\r
.wb_ack_o (aud_ack_o),\r
\r
.clk_100M (sdram_clk),\r
.clk_25M (vga_clk),\r
.timer2 (timer2_o),\r
\r
.i2c_sclk_ (i2c_sclk_),\r
.i2c_sdat_ (i2c_sdat_),\r
\r
.aud_adcdat_ (aud_adcdat_),\r
.aud_daclrck_ (aud_daclrck_),\r
.aud_dacdat_ (aud_dacdat_),\r
.aud_bclk_ (aud_bclk_)\r
);\r
`else\r
assign aud_dat_o = 16'h0;\r
assign aud_ack_o = keyb_stb_i & aud_cyc_i;\r
`endif\r
\r
// Selection logic between keyboard and audio ports (port 65h: audio)\r
assign aud_sel_cond = keyb_adr_i[2:1]==2'b00 && keyb_sel_i[1];\r
assign aud_cyc_i = kaud_cyc_i && aud_sel_cond;\r
assign keyb_cyc_i = kaud_cyc_i && !aud_sel_cond;\r
assign kaud_ack_o = aud_cyc_i & aud_ack_o | keyb_cyc_i & keyb_ack_o;\r
assign kaud_dat_o = {8{aud_cyc_i}} & aud_dat_o\r
| {8{keyb_cyc_i}} & keyb_dat_o[15:8];\r
\r
timer timer (\r
.wb_clk_i (clk),\r
.wb_rst_i (rst),\r
.wb_adr_i (timer_adr_i[1]),\r
.wb_sel_i (timer_sel_i),\r
.wb_dat_i (timer_dat_i),\r
.wb_dat_o (timer_dat_o),\r
.wb_stb_i (timer_stb_i),\r
.wb_cyc_i (timer_cyc_i),\r
.wb_we_i (timer_we_i),\r
.wb_ack_o (timer_ack_o),\r
.wb_tgc_o (intv[0]),\r
.tclk_i (timer_clk), // 1.193182 MHz = (14.31818/12) MHz\r
.gate2_i (aud_dat_o[0]),\r
.out2_o (timer2_o)\r
);\r
\r
simple_pic pic0 (\r
.clk (clk),\r
.rst (rst),\r
.intv (intv),\r
.inta (inta),\r
.intr (intr),\r
.iid (iid)\r
);\r
\r
wb_abrgr sd_brg (\r
.sys_rst (rst),\r
\r
// Wishbone slave interface\r
.wbs_clk_i (clk),\r
.wbs_adr_i (sd_adr_i_s),\r
.wbs_dat_i (sd_dat_i_s),\r
.wbs_dat_o (sd_dat_o_s),\r
.wbs_sel_i (sd_sel_i_s),\r
.wbs_tga_i (sd_tga_i_s),\r
.wbs_stb_i (sd_stb_i_s),\r
.wbs_cyc_i (sd_cyc_i_s),\r
.wbs_we_i (sd_we_i_s),\r
.wbs_ack_o (sd_ack_o_s),\r
\r
// Wishbone master interface\r
.wbm_clk_i (sdram_clk),\r
.wbm_adr_o (sd_adr_i),\r
.wbm_dat_o (sd_dat_i),\r
.wbm_dat_i ({8'h0,sd_dat_o}),\r
.wbm_tga_o (sd_tga_i),\r
.wbm_sel_o (sd_sel_i),\r
.wbm_stb_o (sd_stb_i),\r
.wbm_cyc_o (sd_cyc_i),\r
.wbm_we_o (sd_we_i),\r
.wbm_ack_i (sd_ack_o)\r
);\r
\r
sdspi sdspi (\r
// Serial pad signal\r
.sclk (sd_sclk_),\r
.miso (sd_miso_),\r
.mosi (sd_mosi_),\r
.ss (sd_ss_),\r
\r
// Wishbone slave interface\r
.wb_clk_i (sdram_clk),\r
.wb_rst_i (rst),\r
.wb_dat_i (sd_dat_i[8:0]),\r
.wb_dat_o (sd_dat_o),\r
.wb_we_i (sd_we_i),\r
.wb_sel_i (sd_sel_i),\r
.wb_stb_i (sd_stb_i),\r
.wb_cyc_i (sd_cyc_i),\r
.wb_ack_o (sd_ack_o)\r
);\r
\r
// Switches and leds\r
sw_leds sw_leds (\r
.wb_clk_i (clk),\r
.wb_rst_i (rst),\r
\r
// Wishbone slave interface\r
.wb_adr_i (gpio_adr_i[1]),\r
.wb_dat_o (gpio_dat_o),\r
.wb_dat_i (gpio_dat_i),\r
.wb_sel_i (gpio_sel_i),\r
.wb_we_i (gpio_we_i),\r
.wb_stb_i (gpio_stb_i),\r
.wb_cyc_i (gpio_cyc_i),\r
.wb_ack_o (gpio_ack_o),\r
\r
// GPIO inputs/outputs\r
.leds_ ({ledr_,ledg_[7:4]}),\r
.sw_ (sw_),\r
.pb_ (key_),\r
.tick (intv[0]),\r
.nmi_pb (nmi_pb) // NMI from pushbutton\r
);\r
\r
hex_display hex16 (\r
.num (pc[19:4]),\r
.en (1'b1),\r
\r
.hex0 (hex0_),\r
.hex1 (hex1_),\r
.hex2 (hex2_),\r
.hex3 (hex3_)\r
);\r
\r
zet zet (\r
.pc (pc),\r
\r
// Wishbone master interface\r
.wb_clk_i (clk),\r
.wb_rst_i (rst),\r
.wb_dat_i (dat_i),\r
.wb_dat_o (dat_o),\r
.wb_adr_o (adr),\r
.wb_we_o (we),\r
.wb_tga_o (tga),\r
.wb_sel_o (sel),\r
.wb_stb_o (stb),\r
.wb_cyc_o (cyc),\r
.wb_ack_i (ack),\r
.wb_tgc_i (intr),\r
.wb_tgc_o (inta),\r
.nmi (nmi),\r
.nmia (nmia)\r
);\r
\r
wb_switch #(\r
.s0_addr_1 (20'b0_1111_1111_1111_0000_000), // bios boot mem 0xfff00 - 0xfffff\r
.s0_mask_1 (20'b1_1111_1111_1111_0000_000), // bios boot ROM Memory\r
\r
.s1_addr_1 (20'b0_1010_0000_0000_0000_000), // mem 0xa0000 - 0xbffff\r
.s1_mask_1 (20'b1_1110_0000_0000_0000_000), // VGA\r
\r
.s1_addr_2 (20'b1_0000_0000_0011_1100_000), // io 0x3c0 - 0x3df\r
.s1_mask_2 (20'b1_0000_1111_1111_1110_000), // VGA IO\r
\r
.s2_addr_1 (20'b1_0000_0000_0011_1111_100), // io 0x3f8 - 0x3ff\r
.s2_mask_1 (20'b1_0000_1111_1111_1111_100), // RS232 IO\r
\r
.s3_addr_1 (20'b1_0000_0000_0000_0110_000), // io 0x60, 0x64\r
.s3_mask_1 (20'b1_0000_1111_1111_1111_101), // Keyboard / Mouse IO\r
\r
.s4_addr_1 (20'b1_0000_0000_0001_0000_000), // io 0x100 - 0x101\r
.s4_mask_1 (20'b1_0000_1111_1111_1111_111), // SD Card IO\r
\r
.s5_addr_1 (20'b1_0000_1111_0001_0000_000), // io 0xf100 - 0xf103\r
.s5_mask_1 (20'b1_0000_1111_1111_1111_110), // GPIO\r
\r
.s6_addr_1 (20'b1_0000_1111_0010_0000_000), // io 0xf200 - 0xf20f\r
.s6_mask_1 (20'b1_0000_1111_1111_1111_000), // CSR Bridge SDRAM Control\r
\r
.s7_addr_1 (20'b1_0000_0000_0000_0100_000), // io 0x40 - 0x43\r
.s7_mask_1 (20'b1_0000_1111_1111_1111_110), // Timer control port\r
\r
.s8_addr_1 (20'b1_0000_0000_0010_0011_100), // io 0x0238 - 0x023b\r
.s8_mask_1 (20'b1_0000_1111_1111_1111_110), // Flash IO port\r
\r
.s9_addr_1 (20'b1_0000_0000_0010_0001_000), // io 0x0210 - 0x021F\r
.s9_mask_1 (20'b1_0000_1111_1111_1111_000), // Sound Blaster\r
\r
.sA_addr_1 (20'b1_0000_1111_0011_0000_000), // io 0xf300 - 0xf3ff\r
.sA_mask_1 (20'b1_0000_1111_1111_0000_000), // SDRAM Control\r
.sA_addr_2 (20'b0_0000_0000_0000_0000_000), // mem 0x00000 - 0xfffff\r
.sA_mask_2 (20'b1_0000_0000_0000_0000_000) // Base RAM\r
\r
) wbs (\r
\r
// Master interface\r
.m_dat_i (dat_o),\r
.m_dat_o (sw_dat_o),\r
.m_adr_i ({tga,adr}),\r
.m_sel_i (sel),\r
.m_we_i (we),\r
.m_cyc_i (cyc),\r
.m_stb_i (stb),\r
.m_ack_o (ack),\r
\r
// Slave 0 interface - bios rom\r
.s0_dat_i (rom_dat_o),\r
.s0_dat_o (rom_dat_i),\r
.s0_adr_o ({rom_tga_i,rom_adr_i}),\r
.s0_sel_o (rom_sel_i),\r
.s0_we_o (rom_we_i),\r
.s0_cyc_o (rom_cyc_i),\r
.s0_stb_o (rom_stb_i),\r
.s0_ack_i (rom_ack_o),\r
\r
// Slave 1 interface - vga\r
.s1_dat_i (vga_dat_o_s),\r
.s1_dat_o (vga_dat_i_s),\r
.s1_adr_o ({vga_tga_i_s,vga_adr_i_s}),\r
.s1_sel_o (vga_sel_i_s),\r
.s1_we_o (vga_we_i_s),\r
.s1_cyc_o (vga_cyc_i_s),\r
.s1_stb_o (vga_stb_i_s),\r
.s1_ack_i (vga_ack_o_s),\r
\r
// Slave 2 interface - uart\r
.s2_dat_i (uart_dat_o),\r
.s2_dat_o (uart_dat_i),\r
.s2_adr_o ({uart_tga_i,uart_adr_i}),\r
.s2_sel_o (uart_sel_i),\r
.s2_we_o (uart_we_i),\r
.s2_cyc_o (uart_cyc_i),\r
.s2_stb_o (uart_stb_i),\r
.s2_ack_i (uart_ack_o),\r
\r
// Slave 3 interface - keyb\r
.s3_dat_i ({kaud_dat_o,keyb_dat_o[7:0]}),\r
.s3_dat_o (keyb_dat_i),\r
.s3_adr_o ({keyb_tga_i,keyb_adr_i}),\r
.s3_sel_o (keyb_sel_i),\r
.s3_we_o (keyb_we_i),\r
.s3_cyc_o (kaud_cyc_i),\r
.s3_stb_o (keyb_stb_i),\r
.s3_ack_i (kaud_ack_o),\r
\r
// Slave 4 interface - sd\r
.s4_dat_i (sd_dat_o_s),\r
.s4_dat_o (sd_dat_i_s),\r
.s4_adr_o ({sd_tga_i_s,sd_adr_i_s}),\r
.s4_sel_o (sd_sel_i_s),\r
.s4_we_o (sd_we_i_s),\r
.s4_cyc_o (sd_cyc_i_s),\r
.s4_stb_o (sd_stb_i_s),\r
.s4_ack_i (sd_ack_o_s),\r
\r
// Slave 5 interface - gpio\r
.s5_dat_i (gpio_dat_o),\r
.s5_dat_o (gpio_dat_i),\r
.s5_adr_o ({gpio_tga_i,gpio_adr_i}),\r
.s5_sel_o (gpio_sel_i),\r
.s5_we_o (gpio_we_i),\r
.s5_cyc_o (gpio_cyc_i),\r
.s5_stb_o (gpio_stb_i),\r
.s5_ack_i (gpio_ack_o),\r
\r
// Slave 6 interface - csr bridge\r
.s6_dat_i (csrbrg_dat_r_s),\r
.s6_dat_o (csrbrg_dat_w_s),\r
.s6_adr_o ({csrbrg_tga_s,csrbrg_adr_s}),\r
.s6_sel_o (csrbrg_sel_s),\r
.s6_we_o (csrbrg_we_s),\r
.s6_cyc_o (csrbrg_cyc_s),\r
.s6_stb_o (csrbrg_stb_s),\r
.s6_ack_i (csrbrg_ack_s),\r
\r
// Slave 7 interface - timer\r
.s7_dat_i (timer_dat_o),\r
.s7_dat_o (timer_dat_i),\r
.s7_adr_o ({timer_tga_i,timer_adr_i}),\r
.s7_sel_o (timer_sel_i),\r
.s7_we_o (timer_we_i),\r
.s7_cyc_o (timer_cyc_i),\r
.s7_stb_o (timer_stb_i),\r
.s7_ack_i (timer_ack_o),\r
\r
// Slave 8 interface - flash\r
.s8_dat_i (fl_dat_o),\r
.s8_dat_o (fl_dat_i),\r
.s8_adr_o ({fl_tga_i,fl_adr_i}),\r
.s8_sel_o (fl_sel_i),\r
.s8_we_o (fl_we_i),\r
.s8_cyc_o (fl_cyc_i),\r
.s8_stb_o (fl_stb_i),\r
.s8_ack_i (fl_ack_o),\r
\r
// Slave 9 interface - not connected\r
.s9_dat_i (),\r
.s9_dat_o (),\r
.s9_adr_o (),\r
.s9_sel_o (),\r
.s9_we_o (),\r
.s9_cyc_o (sb_cyc_i),\r
.s9_stb_o (sb_stb_i),\r
.s9_ack_i (sb_cyc_i && sb_stb_i),\r
\r
// Slave A interface - sdram\r
.sA_dat_i (fmlbrg_dat_r_s),\r
.sA_dat_o (fmlbrg_dat_w_s),\r
.sA_adr_o ({fmlbrg_tga_s,fmlbrg_adr_s}),\r
.sA_sel_o (fmlbrg_sel_s),\r
.sA_we_o (fmlbrg_we_s),\r
.sA_cyc_o (fmlbrg_cyc_s),\r
.sA_stb_o (fmlbrg_stb_s),\r
.sA_ack_i (fmlbrg_ack_s),\r
\r
// Slave B interface - default\r
.sB_dat_i (16'h0000),\r
.sB_dat_o (),\r
.sB_adr_o (),\r
.sB_sel_o (),\r
.sB_we_o (),\r
.sB_cyc_o (def_cyc_i),\r
.sB_stb_o (def_stb_i),\r
.sB_ack_i (def_cyc_i & def_stb_i)\r
);\r
\r
// Continuous assignments\r
assign rst_lck = !sw_[0] & lock;\r
\r
assign nmi = nmi_pb;\r
assign dat_i = nmia ? 16'h0002 :\r
(inta ? { 13'b0000_0000_0000_1, iid } :\r
sw_dat_o);\r
\r
assign sdram_clk_ = sdram_clk;\r
\r
// Required de2 adv7123 vga dac clock\r
assign\ttft_lcd_clk_ = vga_clk;\r
\r
assign ledg_[3:0] = pc[3:0];\r
\r
endmodule\r
|
/*\r
* Wishbone to FML 8x16 bridge\r
* Milkymist SoC\r
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq\r
* adjusted to FML 8x16 by Zeus Gomez Marmolejo <[email protected]>\r
* updated to include Direct Cache Bus by Charley Picker <[email protected]>\r
*\r
* This program is free software: you can redistribute it and/or modify\r
* it under the terms of the GNU General Public License as published by\r
* the Free Software Foundation, version 3 of the License.\r
*\r
* This program is distributed in the hope that it will be useful,\r
* but WITHOUT ANY WARRANTY; without even the implied warranty of\r
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
* GNU General Public License for more details.\r
*\r
* You should have received a copy of the GNU General Public License\r
* along with this program. If not, see <http://www.gnu.org/licenses/>.\r
*/\r
\r
module fmlbrg #(\r
\tparameter fml_depth = 23,\r
\tparameter cache_depth = 9 // 512 byte cache\t\r
) (\r
\tinput sys_clk,\r
\tinput sys_rst,\r
\t\r
\tinput [fml_depth-1:1] wb_adr_i,\r
\tinput [2:0] wb_cti_i,\r
\tinput [15:0] wb_dat_i,\r
\toutput [15:0] wb_dat_o,\r
\tinput [1:0] wb_sel_i,\r
\tinput wb_cyc_i,\r
\tinput wb_stb_i,\r
\tinput wb_tga_i,\r
\tinput wb_we_i,\r
\toutput reg wb_ack_o,\r
\t\r
\toutput reg [fml_depth-1:0] fml_adr,\r
\toutput reg fml_stb,\r
\toutput reg fml_we,\r
\tinput fml_ack,\r
\toutput [1:0] fml_sel,\r
\toutput [15:0] fml_do,\r
\tinput [15:0] fml_di,\r
\r
\t/* Direct Cache Bus */\r
\tinput dcb_stb,\r
\tinput [fml_depth-1:0] dcb_adr,\r
\toutput [15:0] dcb_dat,\r
\toutput dcb_hit\r
);\r
\r
/*\r
* Line length is the burst length, that is 8*16 bits, or 16 bytes\r
* Address split up :\r
*\r
* | TAG | INDEX | OFFSET |\r
* |fml_depth-1 cache_depth|cache_depth-1 4|3 0|\r
*\r
*/\r
\r
wire [3:1] offset = wb_adr_i[3:1];\r
wire [cache_depth-1-4:0] index = wb_adr_i[cache_depth-1:4];\r
wire [fml_depth-cache_depth-1:0] tag = wb_adr_i[fml_depth-1:cache_depth];\r
\r
wire [3:1] dcb_offset = dcb_adr[3:1];\r
wire [cache_depth-1-4:0] dcb_index = dcb_adr[cache_depth-1:4];\r
wire [fml_depth-cache_depth-1:0] dcb_tag = dcb_adr[fml_depth-1:cache_depth];\r
\r
wire coincidence = index == dcb_index;\r
\r
/*\r
* TAG MEMORY\r
*\r
* Addressed by index (length cache_depth-5)\r
* Contains valid bit + dirty bit + tag\r
*/\r
\r
wire [cache_depth-1-4:0] tagmem_a;\r
reg tagmem_we;\r
wire [fml_depth-cache_depth-1+2:0] tagmem_di;\r
wire [fml_depth-cache_depth-1+2:0] tagmem_do;\r
\r
wire [cache_depth-1-4:0] tagmem_a2;\r
wire [fml_depth-cache_depth-1+2:0] tagmem_do2;\r
\r
fmlbrg_tagmem #(\r
\t.depth(cache_depth-4),\r
\t.width(fml_depth-cache_depth+2)\r
) tagmem (\r
\t.sys_clk(sys_clk),\r
\r
\t.a(tagmem_a),\r
\t.we(tagmem_we),\r
\t.di(tagmem_di),\r
\t.dout(tagmem_do),\r
\r
\t.a2(tagmem_a2),\r
\t.do2(tagmem_do2)\r
);\r
\r
reg index_load;\r
reg [cache_depth-1-4:0] index_r;\r
always @(posedge sys_clk) begin\r
if(index_load)\r
index_r <= index;\r
end\r
\r
assign tagmem_a = index;\r
\r
assign tagmem_a2 = dcb_index;\r
\r
reg di_valid;\r
reg di_dirty;\r
assign tagmem_di = {di_valid, di_dirty, tag};\r
\r
wire do_valid;\r
wire do_dirty;\r
wire [fml_depth-cache_depth-1:0] do_tag;\r
wire cache_hit;\r
\r
wire do2_valid;\r
wire [fml_depth-cache_depth-1:0] do2_tag;\r
\r
assign do_valid = tagmem_do[fml_depth-cache_depth-1+2];\r
assign do_dirty = tagmem_do[fml_depth-cache_depth-1+1];\r
assign do_tag = tagmem_do[fml_depth-cache_depth-1:0];\r
\r
assign do2_valid = tagmem_do2[fml_depth-cache_depth-1+2];\r
assign do2_tag = tagmem_do2[fml_depth-cache_depth-1:0];\r
\r
always @(posedge sys_clk)\r
\tfml_adr <= {do_tag, index, offset, 1\'b0};\r
\r
/*\r
* DATA MEMORY\r
*\r
* Addressed by index+offset in 16-bit words (length cache_depth-1)\r
* 16-bit memory with 8-bit write granularity\r
*/\r
\r
wire [cache_depth-1-1:0] datamem_a;\r
reg [1:0] datamem_we;\r
reg [15:0] datamem_di;\r
wire [15:0] datamem_do;\r
\r
wire [cache_depth-1-1:0] datamem_a2;\r
wire [15:0] datamem_do2;\r
\r
fmlbrg_datamem #(\r
\t.depth(cache_depth-1)\r
) datamem (\r
\t.sys_clk(sys_clk),\r
\t\r
\t.a(datamem_a),\r
\t.we(datamem_we),\r
\t.di(datamem_di),\r
\t.dout(datamem_do),\r
\r
\t.a2(datamem_a2),\r
\t.do2(datamem_do2)\r
);\r
\r
reg [2:0] bcounter;\r
reg [2:0] bcounter_next;\r
always @(posedge sys_clk) begin\r
\tif(sys_rst)\r
\t\tbcounter <= 3\'d0;\r
\telse\r
\t\tbcounter <= bcounter_next;\r
end\r
\r
reg [1:0] bcounter_sel;\r
\r
localparam BCOUNTER_RESET\t= 2\'d0;\r
localparam BCOUNTER_KEEP\t= 2\'d1;\r
localparam BCOUNTER_LOAD\t= 2\'d2;\r
localparam BCOUNTER_INC\t\t= 2\'d3;\r
\r
always @(*) begin\r
\tcase(bcounter_sel)\r
\t\tBCOUNTER_RESET: bcounter_next <= 3\'d0;\r
\t\tBCOUNTER_KEEP: bcounter_next <= bcounter;\r
\t\tBCOUNTER_LOAD: bcounter_next <= offset;\r
\t\tBCOUNTER_INC: bcounter_next <= bcounter + 3\'d1;\r
\t\tdefault: bcounter_next <= 3\'bxxx;\r
\tendcase\r
end\r
\r
assign datamem_a = { index_load ? index : index_r, bcounter_next };\r
\r
assign datamem_a2 = {dcb_index, dcb_offset};\r
\r
reg datamem_we_wb;\r
reg datamem_we_fml;\r
\r
always @(*) begin\r
\tif(datamem_we_fml)\r
\t\tdatamem_we = 2\'b11;\r
\telse if(datamem_we_wb)\r
\t\t datamem_we = {wb_sel_i};\r
\t\t else datamem_we = 2\'b00;\r
end\r
\r
always @(*) begin\r
datamem_di = fml_di;\r
if(datamem_we_wb) begin\r
if(wb_sel_i[0])\r
datamem_di[7:0] = wb_dat_i[7:0];\r
if(wb_sel_i[1])\r
datamem_di[15:8] = wb_dat_i[15:8];\r
end\r
end\r
\r
assign wb_dat_o = datamem_do;\r
assign fml_do = datamem_do;\r
assign fml_sel = 2\'b11;\r
assign dcb_dat = datamem_do2;\r
\r
/* FSM */\r
\r
reg [fml_depth-cache_depth-1:0] tag_r;\r
always @(posedge sys_clk)\r
\ttag_r = tag;\r
assign cache_hit = do_valid & (do_tag == tag_r);\r
\r
reg [4:0] state;\r
reg [4:0] next_state;\r
\r
localparam [4:0]\r
IDLE = 5\'d0,\r
TEST_HIT = 5\'d1,\r
\r
WB_BURST = 5\'d2,\r
\r
EVICT = 5\'d3,\r
EVICT2 = 5\'d4,\r
EVICT3 = 5\'d5,\r
EVICT4 = 5\'d6,\r
EVICT5 = 5\'d7,\r
EVICT6 = 5\'d8,\r
EVICT7 = 5\'d9,\r
EVICT8 = 5\'d10,\r
\r
REFILL = 5\'d11,\r
REFILL_WAIT = 5\'d12,\r
REFILL1 = 5\'d13,\r
REFILL2 = 5\'d14,\r
REFILL3 = 5\'d15,\r
REFILL4 = 5\'d16,\r
REFILL5 = 5\'d17,\r
REFILL6 = 5\'d18,\r
REFILL7 = 5\'d19,\r
REFILL8 = 5\'d20,\r
\r
TEST_INVALIDATE = 5\'d21,\r
INVALIDATE = 5\'d22;\r
\r
always @(posedge sys_clk) begin\r
\tif(sys_rst)\r
\t\tstate <= IDLE;\r
\telse begin\r
\t\t//$display("state: %d -> %d", state, next_state);\r
\t\tstate <= next_state;\r
\tend\r
end\r
\r
always @(*) begin\r
\ttagmem_we = 1\'b0;\r
\tdi_valid = 1\'b0;\r
\tdi_dirty = 1\'b0;\r
\t\r
\tbcounter_sel = BCOUNTER_KEEP;\r
\t\r
\tindex_load = 1\'b1;\r
\t\t\r
\tdatamem_we_wb = 1\'b0;\r
\tdatamem_we_fml = 1\'b0;\r
\t\r
\twb_ack_o = 1\'b0;\r
\t\r
\tfml_stb = 1\'b0;\r
\tfml_we = 1\'b0;\r
\t\r
\tnext_state = state;\r
\t\r
\tcase(state)\r
\t\tIDLE: begin\r
\t\t\tbcounter_sel = BCOUNTER_LOAD;\r
\t\t\tif(wb_cyc_i & wb_stb_i) begin\r
\t\t\t\tif(wb_tga_i)\r
\t\t\t\t\tnext_state = TEST_INVALIDATE;\r
\t\t\t\telse\r
\t\t\t\t\tnext_state = TEST_HIT;\r
\t\t\tend\r
\t\tend\r
\t\tTEST_HIT: begin\r
\t\t\tif(cache_hit) begin\r
\t\t\t\twb_ack_o = 1\'b1;\r
\t\t\t\tif(wb_we_i) begin\r
\t\t\t\t\tdi_valid = 1\'b1;\r
\t\t\t\t\tdi_dirty = 1\'b1;\r
\t\t\t\t\ttagmem_we = 1\'b1;\r
\t\t\t\t\tdatamem_we_wb = 1\'b1;\r
\t\t\t\tend\r
\t\t\t\tif(wb_cti_i == 3\'b010)\r
\t\t\t\t\tnext_state = WB_BURST;\r
\t\t\t\telse\r
\t\t\t\t\tnext_state = IDLE;\r
\t\t\tend else begin\r
\t\t\t\tif(do_dirty)\r
\t\t\t\t\tnext_state = EVICT;\r
\t\t\t\telse\r
\t\t\t\t\tnext_state = REFILL;\r
\t\t\tend\r
\t\tend\r
\t\t\r
\t\tWB_BURST: begin\r
\t\t\tbcounter_sel = BCOUNTER_INC;\r
\t\t\tif(wb_we_i)\r
\t\t\t\tdatamem_we_wb = 1\'b1;\r
\t\t\twb_ack_o = 1\'b1;\r
\t\t\tif(wb_cti_i != 3\'b010)\r
\t\t\t\tnext_state = IDLE;\r
\t\tend\r
\t\t\r
/*\r
* Burst counter has already been loaded.\r
* Yes, we evict lines in different order depending\r
* on the critical word position of the cache miss\r
* inside the line, but who cares :)\r
*/\t\t\r
\t\tEVICT: begin\r
\t\t $display("Evict");\r
\t\t\tfml_stb = 1\'b1;\r
\t\t\tfml_we = 1\'b1;\r
\t\t\tif(fml_ack) begin\r
\t\t\t\tbcounter_sel = BCOUNTER_INC;\r
\t\t\t\tnext_state = EVICT2;\r
\t\t\tend\r
\t\tend\r
\t\tEVICT2: begin\r
\t\t\tbcounter_sel = BCOUNTER_INC;\r
\t\t\tnext_state = EVICT3;\r
\t\tend\r
\t\tEVICT3: begin\r
\t\t\tbcounter_sel = BCOUNTER_INC;\r
\t\t\tnext_state = EVICT4;\r
\t\tend\r
\t\tEVICT4: begin\r
\t\t\tbcounter_sel = BCOUNTER_INC;\r
\t\t\tnext_state = EVICT5;\r
\t\tend\r
\t\tEVICT5: begin\r
\t\t\tbcounter_sel = BCOUNTER_INC;\r
\t\t\tnext_state = EVICT6;\r
\t\tend\r
\t\tEVICT6: begin\r
\t\t\tbcounter_sel = BCOUNTER_INC;\r
\t\t\tnext_state = EVICT7;\r
\t\tend\r
\t\tEVICT7: begin\r
\t\t\tbcounter_sel = BCOUNTER_INC;\r
\t\t\tnext_state = EVICT8;\r
\t\tend\r
\t\tEVICT8: begin\r
\t\t\tbcounter_sel = BCOUNTER_INC;\r
\t\t\tif(wb_tga_i)\r
\t\t\t\tnext_state = INVALIDATE;\r
\t\t\telse\r
\t\t\t\tnext_state = REFILL;\r
\t\tend\r
\t\t\r
\t\tREFILL: begin\r
\t\t /* Write the tag first. This will also set the FML address. */\r
\t\t\tdi_valid = 1\'b1;\r
\t\t\tif(wb_we_i)\r
\t\t\t\tdi_dirty = 1\'b1;\r
\t\t\telse\r
\t\t\t\tdi_dirty = 1\'b0;\r
\t\t\tif(~(dcb_stb & coincidence)) begin\r
\t\t\t\ttagmem_we = 1\'b1;\r
\t\t\t\tnext_state = REFILL_WAIT;\r
\t\t\tend\r
\t\tend\r
\t\tREFILL_WAIT: next_state = REFILL1; /* one cycle latency for the FML address */\r
\t\tREFILL1: begin\r
\t\t\tbcounter_sel = BCOUNTER_LOAD;\r
\t\t\tfml_stb = 1\'b1;\r
/* Asserting both\r
* datamem_we_fml and\r
* datamem_we_wb, WB has priority\r
*/\r
\t\t\tdatamem_we_fml = 1\'b1;\r
\t\t\tif(wb_we_i)\r
datamem_we_wb = 1\'b1;\r
\t\t\tif(fml_ack)\r
\t\t\t\tnext_state = REFILL2;\r
\t\tend\r
\t\tREFILL2: begin\r
\t\t/*\r
* For reads, the critical word has just been written to the datamem\r
* so by acking the cycle now we get the correct result (because the\r
* datamem is a write-first SRAM).\r
* For writes, we could have acked the cycle before but it\'s simpler this way.\r
* Otherwise, we have the case of a master releasing WE just after ACK,\r
* and we must add a reg to tell whether we have a read or a write in REFILL2...\r
*/\r
wb_ack_o = 1\'b1;\r
/* Now we must use our copy of index, as the WISHBONE\r
* address may change.\r
*/\r
index_load = 1\'b0;\r
\t\t datamem_we_fml = 1\'b1;\r
\t\t bcounter_sel = BCOUNTER_INC;\r
\t\t next_state = REFILL3;\r
\t\tend\r
\t\tREFILL3: begin\r
\t\t index_load = 1\'b0;\r
\t\t\tdatamem_we_fml = 1\'b1;\r
\t\t\tbcounter_sel = BCOUNTER_INC;\r
\t\t\tnext_state = REFILL4;\r
\t\tend\r
\t\tREFILL4: begin\r
\t\t index_load = 1\'b0;\r
\t\t\tdatamem_we_fml = 1\'b1;\r
\t\t\tbcounter_sel = BCOUNTER_INC;\r
\t\t\tnext_state = REFILL5;\r
\t\tend\r
\t\tREFILL5: begin\r
\t\t index_load = 1\'b0;\r
\t\t\tdatamem_we_fml = 1\'b1;\r
\t\t\tbcounter_sel = BCOUNTER_INC;\r
\t\t\tnext_state = REFILL6;\r
\t\tend\r
\t\tREFILL6: begin\r
\t\t index_load = 1\'b0;\r
\t\t\tdatamem_we_fml = 1\'b1;\r
\t\t\tbcounter_sel = BCOUNTER_INC;\r
\t\t\tnext_state = REFILL7;\r
\t\tend\r
\t\tREFILL7: begin\r
\t\t$display("Refill 7");\r
\t\t index_load = 1\'b0;\r
\t\t\tdatamem_we_fml = 1\'b1;\r
\t\t\tbcounter_sel = BCOUNTER_INC;\r
\t\t\tnext_state = REFILL8;\r
\t\tend\r
\t\tREFILL8: begin\r
\t\t index_load = 1\'b0;\r
\t\t\tdatamem_we_fml = 1\'b1;\r
\t\t\tbcounter_sel = BCOUNTER_INC;\r
\t\t\tnext_state = IDLE;\r
\t\tend\r
\t\t\r
\t\tTEST_INVALIDATE: begin\r
\t\t\tif(do_dirty)\r
\t\t\t\tnext_state = EVICT;\r
\t\t\telse\r
\t\t\t\tnext_state = INVALIDATE;\r
\t\tend\r
\t\tINVALIDATE: begin\r
\t\t\tdi_valid = 1\'b0;\r
\t\t\tdi_dirty = 1\'b0;\r
\t\t\ttagmem_we = 1\'b1;\r
\t\t\twb_ack_o = 1\'b1;\r
\t\t\tnext_state = IDLE;\r
\t\tend\r
\tendcase\r
end\r
\r
/* Do not hit on a line being refilled */\r
reg dcb_can_hit;\r
\r
always @(posedge sys_clk) begin\r
\tdcb_can_hit <= 1\'b0;\r
\tif(dcb_stb) begin\r
\t\tif((state != REFILL_WAIT)\r
\t\t|| (state != REFILL2)\r
\t\t|| (state != REFILL3)\r
\t\t|| (state != REFILL4)\r
\t\t|| (state != REFILL5)\r
\t\t|| (state != REFILL6)\r
\t\t|| (state != REFILL7)\r
\t\t|| (state != REFILL8))\r
\t\t\tdcb_can_hit <= 1\'b1;\r
\t\tif(~coincidence)\r
\t\t\tdcb_can_hit <= 1\'b1;\r
\tend\r
end\r
\r
reg [fml_depth-cache_depth-1:0] dcb_tag_r;\r
always @(posedge sys_clk)\r
\tdcb_tag_r = dcb_tag;\r
\r
assign dcb_hit = dcb_can_hit & do2_valid & (do2_tag == dcb_tag_r);\r
\r
endmodule\r
|
/*
* Character ROM for text mode fonts
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
// altera message_off 10030
// get rid of the warning about
// not initializing the ROM
module vdu_char_rom (
input clk,
input [11:0] addr,
output reg [ 7:0] q
);
// Registers, nets and parameters
reg [7:0] rom[0:4095];
// Behaviour
always @(posedge clk) q <= rom[addr];
initial $readmemh("char_rom.dat", rom);
endmodule
|
/*
* Wishbone Compatible Text only VGA core
* Copyright (c) 2008,2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vdu (
input wb_clk_i, // 25 Mhz VDU clock
// Wishbone slave interface
input wb_rst_i,
input [15:0] wb_dat_i,
output reg [15:0] wb_dat_o,
input [19:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// VGA pad signals
output reg [ 1:0] vga_red_o,
output reg [ 1:0] vga_green_o,
output reg [ 1:0] vga_blue_o,
output reg horiz_sync,
output reg vert_sync
);
// Net, registers and parameters
// Synchronization constants, these values are taken from:
// http://tinyvga.com/vga-timing/640x400@70Hz
parameter HOR_DISP_END = 10'd639; // Last horizontal pixel displayed
parameter HOR_SYNC_BEG = 10'd655; // Start of horizontal synch pulse
parameter HOR_SYNC_END = 10'd751; // End of Horizontal Synch pulse
parameter HOR_SCAN_END = 10'd799; // Last pixel in scan line
parameter HOR_DISP_CHR = 80; // Number of characters displayed per row
parameter HOR_VIDEO_ON = 10'd7; // When to start displaying characters
parameter HOR_VIDEO_OFF = 10'd647; // When to stop displaying characters
parameter VER_DISP_END = 9'd400; // last row displayed
parameter VER_SYNC_BEG = 9'd411; // start of vertical synch pulse
parameter VER_SYNC_END = 9'd413; // end of vertical synch pulse
parameter VER_SCAN_END = 9'd448; // Last scan row in the frame
parameter VER_DISP_CHR = 5'd25; // Number of character rows displayed
reg cursor_on_v;
reg cursor_on_h;
reg video_on_v;
reg video_on_h;
reg [9:0] h_count;
reg [8:0] v_count; // 0 to VER_SCAN_END
reg [22:0] blink_count;
// Character generator ROM
wire [11:0] char_addr;
wire [7:0] char_data_out;
// Control registers
reg [3:0] reg_adr;
reg [6:0] reg_hcursor; // 80 columns
reg [4:0] reg_vcursor; // 25 rows
reg [3:0] reg_cur_start;
reg [3:0] reg_cur_end;
wire wr_adr;
wire wr_reg;
wire write;
wire wr_hcursor;
wire wr_vcursor;
wire wr_cur_start;
wire wr_cur_end;
// Video shift register
reg [7:0] vga_shift;
reg [2:0] vga_fg_colour;
reg [2:0] vga_bg_colour;
reg cursor_on;
wire cursor_on1;
reg video_on;
wire video_on1;
// vga character ram access bus
reg [6:0] col_addr; // 0 to 79
reg [4:0] row_addr; // 0 to 49 (25 * 2 -1)
reg [6:0] col1_addr; // 0 to 79
reg [4:0] row1_addr; // 0 to 49 (25 * 2 - 1)
reg [6:0] hor_addr; // 0 to 79
reg [6:0] ver_addr; // 0 to 124
reg vga0_we;
reg vga0_rw, vga1_rw, vga2_rw, vga3_rw, vga4_rw, vga5_rw;
reg vga1_we;
reg vga2_we;
reg buff_we;
reg [7:0] buff_data_in;
reg attr_we;
reg [7:0] attr_data_in;
reg [10:0] buff_addr;
reg [10:0] attr0_addr;
reg attr0_we;
reg [10:0] buff0_addr;
reg buff0_we;
reg [10:0] attr_addr;
reg intense;
wire [7:0] vga_data_out;
wire [7:0] attr_data_out;
wire [10:0] vga_addr; // 2K byte character buffer
wire [15:0] out_data;
wire fg_or_bg;
wire stb;
wire brown_bg;
wire brown_fg;
wire [15:0] status_reg1;
wire vh_retrace;
wire v_retrace;
// Module instantiation
vdu_char_rom char_rom (
.clk (wb_clk_i),
.addr (char_addr),
.q (char_data_out)
);
vdu_ram_2k_char ram_2k_char (
.clk (wb_clk_i),
.rst (wb_rst_i),
.we (buff_we),
.addr (buff_addr),
.wdata (buff_data_in),
.rdata (vga_data_out)
);
vdu_ram_2k_attr ram_2k_attr (
.clk (wb_clk_i),
.rst (wb_rst_i),
.we (attr_we),
.addr (attr_addr),
.wdata (attr_data_in),
.rdata (attr_data_out)
);
// Assignments
assign video_on1 = video_on_h && video_on_v;
assign cursor_on1 = cursor_on_h && cursor_on_v;
assign char_addr = { vga_data_out, v_count[3:0] };
assign vga_addr = { 4'b0, hor_addr} + { ver_addr, 4'b0 };
assign out_data = {attr_data_out, vga_data_out};
assign stb = wb_stb_i && wb_cyc_i;
assign fg_or_bg = vga_shift[7] ^ cursor_on;
assign brown_fg = (vga_fg_colour==3'd6) && !intense;
assign brown_bg = (vga_bg_colour==3'd6);
// Control registers
assign write = wb_tga_i & wb_stb_i & wb_cyc_i & wb_we_i;
assign wr_adr = write & wb_sel_i[0];
assign wr_reg = write & wb_sel_i[1];
assign wr_hcursor = wr_reg & (reg_adr==4'hf);
assign wr_vcursor = wr_reg & (reg_adr==4'he);
assign wr_cur_start = wr_reg & (reg_adr==4'ha);
assign wr_cur_end = wr_reg & (reg_adr==4'hb);
assign v_retrace = !video_on_v;
assign vh_retrace = v_retrace | !video_on_h;
assign status_reg1 = { 11'b0, v_retrace, 3'b0, vh_retrace };
assign wb_ack_o = stb & (wb_tga_i ? 1'b1 : vga5_rw);
// Behaviour - CPU write interface
always @(posedge wb_clk_i)
if(wb_rst_i) begin
attr0_addr <= 11'b0;
attr0_we <= 1'b0;
attr_data_in <= 8'h0;
buff0_addr <= 11'b0;
buff0_we <= 1'b0;
buff_data_in <= 8'h0;
end
else begin
if(stb && !wb_tga_i) begin
// 1111 1111 1100 0000 0000
// 0xa0000 - 0xbffff 9876 5432 1098 7654 3210
// if(wb_adr_i[19:12] & 8'h18) begin
// 0xB8000 - 0xBFFFF = 1011_1000_xxxx_xxxx_xxxs
attr0_addr <= wb_adr_i[11:1];
buff0_addr <= wb_adr_i[11:1];
attr0_we <= wb_we_i & wb_sel_i[1];
buff0_we <= wb_we_i & wb_sel_i[0];
// end
attr_data_in <= wb_dat_i[15:8];
buff_data_in <= wb_dat_i[7:0];
end
end
// CPU read interface
always @(posedge wb_clk_i)
wb_dat_o <= wb_rst_i ? 16'h0 : (wb_tga_i ? status_reg1
: (vga4_rw ? out_data : wb_dat_o));
// Control registers
always @(posedge wb_clk_i)
reg_adr <= wb_rst_i ? 4'h0
: (wr_adr ? wb_dat_i[3:0] : reg_adr);
always @(posedge wb_clk_i)
reg_hcursor <= wb_rst_i ? 7'h0
: (wr_hcursor ? wb_dat_i[14:8] : reg_hcursor);
always @(posedge wb_clk_i)
reg_vcursor <= wb_rst_i ? 5'h0
: (wr_vcursor ? wb_dat_i[12:8] : reg_vcursor);
always @(posedge wb_clk_i)
reg_cur_start <= wb_rst_i ? 4'he
: (wr_cur_start ? wb_dat_i[11:8] : reg_cur_start);
always @(posedge wb_clk_i)
reg_cur_end <= wb_rst_i ? 4'hf
: (wr_cur_end ? wb_dat_i[11:8] : reg_cur_end);
// Sync generation & timing process
// Generate horizontal and vertical timing signals for video signal
always @(posedge wb_clk_i)
if(wb_rst_i) begin
h_count <= 10'b0;
horiz_sync <= 1'b1;
v_count <= 9'b0;
vert_sync <= 1'b1;
video_on_h <= 1'b1;
video_on_v <= 1'b1;
cursor_on_h <= 1'b0;
cursor_on_v <= 1'b0;
blink_count <= 22'b0;
end
else begin
h_count <= (h_count==HOR_SCAN_END) ? 10'b0 : h_count + 10'b1;
horiz_sync <= (h_count==HOR_SYNC_BEG) ? 1'b0 : ((h_count==HOR_SYNC_END) ? 1'b1 : horiz_sync);
v_count <= (v_count==VER_SCAN_END && h_count==HOR_SCAN_END) ? 9'b0 : ((h_count==HOR_SYNC_END) ? v_count + 9'b1 : v_count);
vert_sync <= (v_count==VER_SYNC_BEG) ? 1'b0 : ((v_count==VER_SYNC_END) ? 1'b1 : vert_sync);
video_on_h <= (h_count==HOR_VIDEO_ON) ? 1'b1 : ((h_count==HOR_VIDEO_OFF) ? 1'b0 : video_on_h);
video_on_v <= (v_count==9'h0) ? 1'b1 : ((v_count==VER_DISP_END) ? 1'b0 : video_on_v);
cursor_on_h <= (h_count[9:3] == reg_hcursor[6:0]);
cursor_on_v <= (v_count[8:4] == reg_vcursor[4:0]) && (v_count[3:0] >= reg_cur_start) && (v_count[3:0] <= reg_cur_end);
blink_count <= blink_count + 22'd1;
end
// Video memory access
always @(posedge wb_clk_i)
if(wb_rst_i) begin
vga0_we <= 1'b0;
vga0_rw <= 1'b1;
row_addr <= 5'b0;
col_addr <= 7'b0;
vga1_we <= 1'b0;
vga1_rw <= 1'b1;
row1_addr <= 5'b0;
col1_addr <= 7'b0;
vga2_we <= 1'b0;
vga2_rw <= 1'b0;
vga3_rw <= 1'b0;
vga4_rw <= 1'b0;
vga5_rw <= 1'b0;
ver_addr <= 7'b0;
hor_addr <= 7'b0;
buff_addr <= 10'b0;
attr_addr <= 10'b0;
buff_we <= 1'b0;
attr_we <= 1'b0;
end
else begin // on h_count = 0 initiate character write
case (h_count[2:0]) // all other cycles are reads
3'b000: // pipeline character write
begin
vga0_we <= wb_we_i;
vga0_rw <= stb;
end
default: // other 6 cycles free
begin
vga0_we <= 1'b0;
vga0_rw <= 1'b0;
col_addr <= h_count[9:3];
row_addr <= v_count[8:4];
end
endcase
// on vdu_clk + 1 round off row address
// row1_addr = (row_addr % 80)
vga1_we <= vga0_we;
vga1_rw <= vga0_rw;
row1_addr <= (row_addr < VER_DISP_CHR) ? row_addr : row_addr - VER_DISP_CHR;
col1_addr <= col_addr;
// on vdu_clk + 2 calculate vertical address
// ver_addr = (row_addr % 80) x 5
vga2_we <= vga1_we;
vga2_rw <= vga1_rw;
ver_addr <= { 2'b00, row1_addr } + { row1_addr, 2'b00 }; // x5
hor_addr <= col1_addr;
// on vdu_clk + 3 calculate memory address
// vga_addr = (row_addr % 80) * 80 + hor_addr
buff_addr <= vga2_rw ? buff0_addr : vga_addr;
attr_addr <= vga2_rw ? attr0_addr : vga_addr;
buff_we <= vga2_rw ? (buff0_we & vga2_we) : 1'b0;
attr_we <= vga2_rw ? (attr0_we & vga2_we) : 1'b0;
vga3_rw <= vga2_rw;
vga4_rw <= vga3_rw;
vga5_rw <= vga4_rw;
end
// Video shift register
always @(posedge wb_clk_i)
if(wb_rst_i) begin
video_on <= 1'b0;
cursor_on <= 1'b0;
vga_bg_colour <= 3'b000;
vga_fg_colour <= 3'b111;
vga_shift <= 8'b00000000;
vga_red_o <= 1'b0;
vga_green_o <= 1'b0;
vga_blue_o <= 1'b0;
end
else begin
if(h_count[2:0] == 3'b000) begin
video_on <= video_on1;
cursor_on <= (cursor_on1 | attr_data_out[7]) & blink_count[22];
vga_fg_colour <= attr_data_out[2:0];
vga_bg_colour <= attr_data_out[6:4];
intense <= attr_data_out[3];
vga_shift <= char_data_out;
end
else vga_shift <= { vga_shift[6:0], 1'b0 };
// Colour mask is
// 7 6 5 4 3 2 1 0
// X BR BG BB X FR FG FB
vga_blue_o <= video_on ? (fg_or_bg ? { vga_fg_colour[0], intense } : { vga_bg_colour[0], 1'b0 }) : 2'b0;
// Green color exception with color brown
// http://en.wikipedia.org/wiki/Color_Graphics_Adapter#With_an_RGBI_monitor
vga_green_o <= video_on ? (fg_or_bg ? (brown_fg ? 2'b01 : { vga_fg_colour[1], intense })
: (brown_bg ? 2'b01 : { vga_bg_colour[1], 1'b0 })) : 2'b0;
vga_red_o <= video_on ? (fg_or_bg ? { vga_fg_colour[2], intense } : { vga_bg_colour[2], 1'b0 }) : 2'b0;
end
endmodule
|
/*
* Module for performing other ALU operations
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_othop (x, y, seg, off, iflags, func, word_op, out, oflags);
// IO ports
input [15:0] x, y, off, seg, iflags;
input [2:0] func;
input word_op;
output [19:0] out;
output [8:0] oflags;
// Net declarations
wire [15:0] deff, deff2, outf, clcm, setf, intf, strf;
wire [19:0] dcmp, dcmp2;
wire dfi;
// Module instantiations
zet_mux8_16 mux8_16 (func, dcmp[15:0], dcmp2[15:0], deff, outf, clcm, setf,
intf, strf, out[15:0]);
assign out[19:16] = func ? dcmp2[19:16] : dcmp[19:16];
// Assignments
assign dcmp = (seg << 4) + deff;
assign dcmp2 = (seg << 4) + deff2;
assign deff = x + y + off;
assign deff2 = x + y + off + 16'd2;
assign outf = y;
assign clcm = y[2] ? (y[1] ? /* -1: clc */ {iflags[15:1], 1'b0}
: /* 4: cld */ {iflags[15:11], 1'b0, iflags[9:0]})
: (y[1] ? /* 2: cli */ {iflags[15:10], 1'b0, iflags[8:0]}
: /* 0: cmc */ {iflags[15:1], ~iflags[0]});
assign setf = y[2] ? (y[1] ? /* -1: stc */ {iflags[15:1], 1'b1}
: /* 4: std */ {iflags[15:11], 1'b1, iflags[9:0]})
: (y[1] ? /* 2: sti */ {iflags[15:10], 1'b1, iflags[8:0]}
: /* 0: outf */ iflags);
assign intf = {iflags[15:10], 2'b0, iflags[7:0]};
assign dfi = iflags[10];
assign strf = dfi ? (x - y) : (x + y);
assign oflags = word_op ? { out[11:6], out[4], out[2], out[0] }
: { iflags[11:8], out[7:6], out[4], out[2], out[0] };
endmodule
|
/*
* PS2 Wishbone 8042 compatible keyboard controller
* Copyright (c) 2009 Zeus Gomez Marmolejo <[email protected]>
* adapted from the opencores keyboard controller from John Clayton
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
// altera message_off 10030
// get rid of the warning about
// not initializing the ROM
module ps2_keyb_xtcodes (
// input clk,
input [6:0] at_code,
output [6:0] xt_code
);
// Registers, nets and parameters
reg [7:0] rom[0:2**7-1];
assign xt_code = rom[at_code][6:0];
// Behaviour
/*
always @(posedge clk)
xt_code <= rom[at_code][6:0];
*/
initial $readmemh("xt_codes.dat", rom);
endmodule
|
/*
* 16-bit full adder
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_fulladd16 (
input [15:0] x,
input [15:0] y,
input ci,
output co,
output [15:0] z,
input s
);
// Continuous assignments
assign {co,z} = {1'b0, x} + {s, y} + ci;
endmodule
|
/*
* Wishbone asynchronous bridge with TGA and WE regslice
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module wb_abrgr (
input sys_rst,
// Wishbone slave interface
input wbs_clk_i,
input [19:1] wbs_adr_i,
input [15:0] wbs_dat_i,
output reg [15:0] wbs_dat_o,
input [ 1:0] wbs_sel_i,
input wbs_tga_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
output wbs_ack_o,
// Wishbone master interface
input wbm_clk_i,
output reg [19:1] wbm_adr_o,
output reg [15:0] wbm_dat_o,
input [15:0] wbm_dat_i,
output reg [ 1:0] wbm_sel_o,
output reg wbm_tga_o,
output wbm_stb_o,
output wbm_cyc_o,
output reg wbm_we_o,
input wbm_ack_i
);
// Registers and nets
wire wbs_stb;
wire init_tr;
reg wbm_stb;
reg [2:0] sync_stb;
reg [2:0] sync_ack;
reg ft_stb;
reg ft_ack;
reg stb_r;
reg ack_r;
reg [19:1] wbm_adr_o_r;
reg [15:0] wbm_dat_o_r;
reg [ 1:0] wbm_sel_o_r;
reg wbs_tga_i_r;
reg wbm_tga_o_r;
reg wbs_we_i_r;
reg wbm_we_o_r;
reg [15:0] wbs_dat_o_r;
reg [15:0] wbm_dat_i_r;
// Continous assignments
assign wbs_stb = wbs_stb_i & wbs_cyc_i;
// recreate the flag from the level change
assign wbs_ack_o = (sync_ack[2] ^ sync_ack[1]);
assign wbm_stb_o = wbm_stb;
assign wbm_cyc_o = wbm_stb;
/*
* A new wishbone transaction is issued:
* . by changing stb from 0 to 1
* . by continue asserting stb after ack is received
*/
assign init_tr = ~stb_r & wbs_stb | ack_r & ~wbs_ack_o & wbs_stb;
// Behaviour
// wbm_stb
always @(posedge wbm_clk_i)
wbm_stb <= sys_rst ? 1'b0
: (wbm_stb ? ~wbm_ack_i : sync_stb[2] ^ sync_stb[1]);
// old stb and ack state
always @(posedge wbs_clk_i) stb_r <= wbs_stb;
always @(posedge wbs_clk_i) ack_r <= wbs_ack_o;
always @(posedge wbs_clk_i)
ft_stb <= sys_rst ? 1'b0 : (init_tr ? ~ft_stb : ft_stb);
// synchronize the last level change
always @(posedge wbm_clk_i)
sync_stb <= sys_rst ? 3'h0 : {sync_stb[1:0], ft_stb};
// this changes level when a flag is seen
always @(posedge wbm_clk_i)
ft_ack <= sys_rst ? 1'b0 : (wbm_ack_i ? ~ft_ack : ft_ack);
// which can then be synched to wbs_clk_i
always @(posedge wbs_clk_i)
sync_ack <= sys_rst ? 3'h0 : {sync_ack[1:0], ft_ack};
// rest of the wishbone signals
always @(posedge wbm_clk_i)
{wbm_adr_o, wbm_adr_o_r} <= {wbm_adr_o_r, wbs_adr_i};
always @(posedge wbm_clk_i)
{wbm_dat_o, wbm_dat_o_r} <= {wbm_dat_o_r, wbs_dat_i};
always @(posedge wbm_clk_i)
{wbm_sel_o, wbm_sel_o_r} <= {wbm_sel_o_r, wbs_sel_i};
always @(posedge wbs_clk_i) wbs_we_i_r <= wbs_we_i;
always @(posedge wbm_clk_i)
{wbm_we_o, wbm_we_o_r} <= {wbm_we_o_r, wbs_we_i_r};
always @(posedge wbs_clk_i) wbs_tga_i_r <= wbs_tga_i;
always @(posedge wbm_clk_i)
{wbm_tga_o, wbm_tga_o_r} <= {wbm_tga_o_r, wbs_tga_i_r};
/*
* Register input coming from the slave as that can change
* after the ack is received
*/
always @(posedge wbm_clk_i)
wbm_dat_i_r <= wbm_ack_i ? wbm_dat_i : wbm_dat_i_r;
always @(posedge wbs_clk_i)
{wbs_dat_o, wbs_dat_o_r} <= {wbs_dat_o_r, wbm_dat_i_r};
endmodule
|
/*
* Planar mode graphics for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga_planar (
input clk,
input rst,
// CSR slave interface for reading
output [17:1] csr_adr_o,
input [15:0] csr_dat_i,
output csr_stb_o,
// Controller registers
input [3:0] attr_plane_enable,
input x_dotclockdiv2,
input [9:0] h_count,
input [9:0] v_count,
input horiz_sync_i,
input video_on_h_i,
output video_on_h_o,
output reg [3:0] attr,
output horiz_sync_o
);
// Registers and net
reg [11:0] row_addr;
reg [ 5:0] col_addr;
reg [14:0] word_offset;
reg [ 1:0] plane_addr0;
reg [ 1:0] plane_addr;
reg [15:0] plane0;
reg [15:0] plane0_tmp;
reg [15:0] plane1;
reg [15:0] plane1_tmp;
reg [15:0] plane2;
reg [15:0] plane2_tmp;
reg [15:0] plane3;
reg [ 7:0] bit_mask0;
reg [ 7:0] bit_mask1;
wire [15:0] bit_mask;
wire v_count0;
wire bit3, bit2, bit1, bit0;
reg [9:0] video_on_h;
reg [9:0] horiz_sync;
reg [7:0] pipe;
// Continous assignments
assign csr_adr_o = { word_offset, plane_addr };
assign bit_mask = { bit_mask1, bit_mask0 };
assign bit0 = |(bit_mask & plane0);
assign bit1 = |(bit_mask & plane1);
assign bit2 = |(bit_mask & plane2);
assign bit3 = |(bit_mask & plane3);
assign video_on_h_o = video_on_h[9];
assign horiz_sync_o = horiz_sync[9];
assign csr_stb_o = |pipe[4:1];
assign v_count0 = x_dotclockdiv2 ? 1'b0 : v_count[0];
// Behaviour
// Pipeline count
always @(posedge clk)
pipe <= rst ? 8'b0 : { pipe[6:0],
x_dotclockdiv2 ? (h_count[4:0]==5'h0) : (h_count[3:0]==4'h0) };
// video_on_h
always @(posedge clk)
video_on_h <= rst ? 10'b0 : { video_on_h[8:0], video_on_h_i };
// horiz_sync
always @(posedge clk)
horiz_sync <= rst ? 10'b0 : { horiz_sync[8:0], horiz_sync_i };
// Address generation
always @(posedge clk)
if (rst)
begin
row_addr <= 12'h0;
col_addr <= 6'h0;
plane_addr0 <= 2'b00;
word_offset <= 15'h0;
plane_addr <= 2'b00;
end
else
begin
// Loading new row_addr and col_addr when h_count[3:0]==4'h0
// v_count * 40 or 22 (depending on x_dotclockdiv2)
row_addr <= { v_count[9:1], v_count0, 2'b00 } + { v_count[9:1], v_count0 }
+ (x_dotclockdiv2 ? v_count[9:1] : 9'h0);
col_addr <= x_dotclockdiv2 ? h_count[9:5] : h_count[9:4];
plane_addr0 <= h_count[1:0];
// Load new word_offset at +1
word_offset <= (x_dotclockdiv2 ? { row_addr, 1'b0 }
: { row_addr, 3'b000 }) + col_addr;
plane_addr <= plane_addr0;
end
// Temporary plane data
always @(posedge clk)
if (rst)
begin
plane0_tmp <= 16'h0;
plane1_tmp <= 16'h0;
plane2_tmp <= 16'h0;
end
else
begin
// Load plane0 when pipe == 4
plane0_tmp <= pipe[4] ? csr_dat_i : plane0_tmp;
plane1_tmp <= pipe[5] ? csr_dat_i : plane1_tmp;
plane2_tmp <= pipe[6] ? csr_dat_i : plane2_tmp;
end
// Plane data
always @(posedge clk)
if (rst)
begin
plane0 <= 16'h0;
plane1 <= 16'h0;
plane2 <= 16'h0;
plane3 <= 16'h0;
end
else
begin
plane0 <= pipe[7] ? plane0_tmp : plane0;
plane1 <= pipe[7] ? plane1_tmp : plane1;
plane2 <= pipe[7] ? plane2_tmp : plane2;
plane3 <= pipe[7] ? csr_dat_i : plane3;
end
// Bit masks
always @(posedge clk)
if (rst)
begin
bit_mask0 <= 8'h0;
bit_mask1 <= 8'h0;
end
else
begin
bit_mask0 <= (h_count[0] & x_dotclockdiv2) ? bit_mask0
: { pipe[7], bit_mask0[7:1] };
bit_mask1 <= (h_count[0] & x_dotclockdiv2) ? bit_mask1
: { bit_mask0[0], bit_mask1[7:1] };
end
// attr
always @(posedge clk)
attr <= rst ? 4'h0 : (attr_plane_enable & { bit3, bit2, bit1, bit0 });
endmodule
|
/*\r
* LCD controller for VGA\r
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>\r
*\r
* VGA FML support\r
* Copyright (C) 2013 Charley Picker <[email protected]>\r
*\r
* Portions of code borrowed from Milkymist SoC \r
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq\r
*\r
* This file is part of the Zet processor. This processor is free\r
* hardware; you can redistribute it and/or modify it under the terms of\r
* the GNU General Public License as published by the Free Software\r
* Foundation; either version 3, or (at your option) any later version.\r
*\r
* Zet is distrubuted in the hope that it will be useful, but WITHOUT\r
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public\r
* License for more details.\r
*\r
* You should have received a copy of the GNU General Public License\r
* along with Zet; see the file COPYING. If not, see\r
* <http://www.gnu.org/licenses/>.\r
*/\r
\r
module vga_lcd_fml #(\r
parameter fml_depth = 20 // 1MB Video Memory\r
) (\r
input clk, // 100 Mhz clock\r
input rst,\r
\r
input shift_reg1, // if set: 320x200\r
input graphics_alpha, // if not set: 640x400 text mode\r
\r
// VGA LCD FML master interface\r
output reg [fml_depth-1:0] fml_adr,\r
output reg fml_stb,\r
input fml_we,\r
input fml_ack,\r
output [1:0] fml_sel,\r
output [15:0] fml_do,\r
input [15:0] fml_di,\r
\r
// VGA LCD Direct Cache Bus\r
output reg dcb_stb,\r
output [fml_depth-1:0] dcb_adr,\r
input [15:0] dcb_dat,\r
input dcb_hit,\r
\r
// attribute_ctrl\r
input [3:0] pal_addr,\r
input pal_we,\r
output [7:0] pal_read,\r
input [7:0] pal_write,\r
\r
// dac_regs\r
input dac_we,\r
input [1:0] dac_read_data_cycle,\r
input [7:0] dac_read_data_register,\r
output [3:0] dac_read_data,\r
input [1:0] dac_write_data_cycle,\r
input [7:0] dac_write_data_register,\r
input [3:0] dac_write_data,\r
\r
// VGA pad signals\r
output [3:0] vga_red_o,\r
output [3:0] vga_green_o,\r
output [3:0] vga_blue_o,\r
output horiz_sync,\r
output vert_sync,\r
\r
// Base address of video memory\r
input [15:0] start_addr,\r
\r
// CRTC\r
input [5:0] cur_start,\r
input [5:0] cur_end,\r
input [4:0] vcursor,\r
input [6:0] hcursor,\r
\r
input [6:0] horiz_total,\r
input [6:0] end_horiz,\r
input [6:0] st_hor_retr,\r
input [4:0] end_hor_retr,\r
input [9:0] vert_total,\r
input [9:0] end_vert,\r
input [9:0] st_ver_retr,\r
input [3:0] end_ver_retr,\r
\r
input x_dotclockdiv2,\r
\r
// retrace signals\r
output v_retrace,\r
output vh_retrace,\r
\r
output vga_clk\r
\r
);\r
\r
// Registers and nets\r
// Hookup crtc output stage to sequencer input stage \r
wire [9:0] h_count; // Horizontal pipeline delay is 2 cycles\r
wire horiz_sync_i;\r
wire [9:0] v_count; // 0 to VER_SCAN_END\r
wire vert_sync_crtc_o;\r
wire video_on_h_i;\r
wire video_on_v;\r
\r
// Hookup sequencer output stage to fifo input stage \r
wire [11:0] fb_dat_i;\r
wire horiz_sync_seq_o;\r
wire vert_sync_seq_o;\r
wire video_on_h_seq_o;\r
wire video_on_v_seq_o;\r
wire [7:0] character_seq_o;\r
\r
// Hookup fifo output stage to pal_dac input stage\r
wire [11:0] fb_dat_o;\r
wire fb_horiz_sync_seq_o;\r
wire fb_vert_sync_seq_o;\r
wire fb_video_on_h_seq_o;\r
wire fb_video_on_v_seq_o;\r
wire [7:0] fb_character_seq_o;\r
\r
// Pixel buffer control\r
wire read_fifo;\r
wire fill_fifo;\r
// Number of words stored in the FIFO, 0-63 (64 possible values)\r
wire [9:0] fifo_level;\r
wire fifo_empty;\r
wire fifo_full;\r
\r
// Each stage is controlled by enable signals\r
wire en_crtc;\r
wire en_sequencer;\r
wire en_pal_dac;\r
\r
reg next_crtc_seq_cyc;\r
reg next_pal_dac_cyc;\r
\r
// Pixel clock counter \r
reg [1:0] pixel_clk_counter;\r
\r
// LCD FSM Registers\r
reg fifo_source_cache;\r
wire can_burst;\r
wire [17:1] lcd_adr;\r
wire lcd_stb;\r
\r
// Module instances\r
vga_crtc_fml crtc (\r
.clk (clk), // 100 Mhz clock\r
.rst (rst),\r
\r
.enable_crtc (en_crtc),\r
\r
// CRTC configuration signals\r
\r
.cur_start (cur_start),\r
.cur_end (cur_end),\r
.vcursor (vcursor),\r
.hcursor (hcursor),\r
\r
.horiz_total (horiz_total),\r
.end_horiz (end_horiz),\r
.st_hor_retr (st_hor_retr),\r
.end_hor_retr (end_hor_retr),\r
.vert_total (vert_total),\r
.end_vert (end_vert),\r
.st_ver_retr (st_ver_retr),\r
.end_ver_retr (end_ver_retr),\r
\r
// CRTC output signals\r
\r
.h_count (h_count),\r
.horiz_sync_i (horiz_sync_i),\r
\r
.v_count (v_count),\r
.vert_sync (vert_sync_crtc_o),\r
\r
.video_on_h_i (video_on_h_i),\r
.video_on_v (video_on_v)\r
\r
);\r
\r
vga_sequencer_fml sequencer (\r
.clk (clk), // 100 Mhz clock\r
.rst (rst),\r
\r
.enable_sequencer (en_sequencer),\r
\r
// Sequencer input signals\r
\r
.h_count (h_count),\r
.horiz_sync_i (horiz_sync_i),\r
\r
.v_count (v_count),\r
.vert_sync (vert_sync_crtc_o),\r
\r
.video_on_h_i (video_on_h_i),\r
.video_on_v (video_on_v),\r
\r
// Sequencer configuration signals\r
\r
.shift_reg1 (shift_reg1), // if set: 320x200\r
.graphics_alpha (graphics_alpha), // if not set: 640x400 text mode\r
\r
// CSR slave interface for reading\r
.fml_adr_o (lcd_adr),\r
.fml_dat_i (fifo_source_cache ? dcb_dat : fml_di),\r
.fml_stb_o (lcd_stb),\r
\r
// CRTC\r
.cur_start (cur_start),\r
.cur_end (cur_end),\r
.vcursor (vcursor),\r
.hcursor (hcursor),\r
\r
.x_dotclockdiv2 (x_dotclockdiv2),\r
\r
// Sequencer output signals\r
\r
.horiz_sync_seq_o (horiz_sync_seq_o),\r
.vert_sync_seq_o (vert_sync_seq_o),\r
.video_on_h_seq_o (video_on_h_seq_o),\r
.video_on_v_seq_o (video_on_v_seq_o),\r
.character_seq_o (character_seq_o) \r
\r
);\r
\r
// video-data buffer (temporary store data read from video memory)\r
// We want to store at least one scan line (512 pixels x 12 bits per pixel) in the buffer\r
vga_fifo #(9, 12) data_fifo (\r
.clk ( clk ),\r
.aclr ( 1'b1 ),\r
.sclr ( rst ),\r
.d ( fb_dat_i ),\r
.wreq ( fill_fifo ),\r
.q ( fb_dat_o ),\r
.rreq ( read_fifo ),\r
.nword ( fifo_level ),\r
.empty ( fifo_empty ),\r
.full ( fifo_full ),\r
.aempty ( ),\r
.afull ( )\r
);\r
\r
vga_pal_dac_fml pal_dac (\r
.clk (clk), // 100 Mhz clock\r
.rst (rst),\r
\r
.enable_pal_dac (en_pal_dac),\r
\r
// VGA PAL/DAC input signals\r
\r
.horiz_sync_pal_dac_i (fb_horiz_sync_seq_o),\r
.vert_sync_pal_dac_i (fb_vert_sync_seq_o),\r
.video_on_h_pal_dac_i (fb_video_on_h_seq_o),\r
.video_on_v_pal_dac_i (fb_video_on_v_seq_o),\r
.character_pal_dac_i (fb_character_seq_o),\r
\r
// VGA PAL/DAC configuration signals\r
\r
.shift_reg1 (shift_reg1), // if set: 320x200\r
.graphics_alpha (graphics_alpha), // if not set: 640x400 text mode\r
\r
// attribute_ctrl\r
.pal_addr (pal_addr),\r
.pal_we (pal_we),\r
.pal_read (pal_read),\r
.pal_write (pal_write),\r
\r
// dac_regs\r
.dac_we (dac_we),\r
.dac_read_data_cycle (dac_read_data_cycle),\r
.dac_read_data_register (dac_read_data_register),\r
.dac_read_data (dac_read_data),\r
.dac_write_data_cycle (dac_write_data_cycle),\r
.dac_write_data_register (dac_write_data_register),\r
.dac_write_data (dac_write_data),\r
\r
// VGA PAL/DAC output signals\r
\r
// VGA pad signals\r
.vga_red_o (vga_red_o),\r
.vga_green_o (vga_green_o),\r
.vga_blue_o (vga_blue_o),\r
.horiz_sync (horiz_sync),\r
.vert_sync (vert_sync),\r
\r
// retrace signals\r
.v_retrace (v_retrace),\r
.vh_retrace (vh_retrace)\r
);\r
\r
// Continuous assignments\r
\r
// The lcd is read only device and these control signals are not used\r
assign fml_sel = 2'b11;\r
assign fml_do = 16'b0;\r
\r
// Pack sequencer stage output into one wire group\r
assign fb_dat_i = { horiz_sync_seq_o,\r
vert_sync_seq_o,\r
video_on_h_seq_o,\r
video_on_v_seq_o,\r
character_seq_o[7:0] };\r
\r
// Unpack fb_dat_o back into seperate wires\r
assign fb_horiz_sync_seq_o = fb_dat_o [11];\r
assign fb_vert_sync_seq_o = fb_dat_o [10];\r
assign fb_video_on_h_seq_o = fb_dat_o [9];\r
assign fb_video_on_v_seq_o = fb_dat_o [8];\r
assign fb_character_seq_o = fb_dat_o [7:0];\r
\r
// Wait until the fifo level is <= 300 (enough room for a 212 pixel burst)\r
assign can_burst = fifo_level <= 10'd300;\r
\r
// These signals enable and control when the next crtc/sequencer cycle should occur \r
assign en_crtc = next_crtc_seq_cyc;\r
assign en_sequencer = next_crtc_seq_cyc;\r
\r
// When the next_crtc_seq_cyc occurs we should place another pixel in fifo\r
assign fill_fifo = next_crtc_seq_cyc;\r
\r
// This signal enables and controls when we should read from the fifo\r
// We must first wait until something is in the fifo!!!\r
assign read_fifo = next_pal_dac_cyc & !fifo_empty;\r
\r
// This signal enables and controls when the next pal_dac cycle should occure\r
// We must first wait until something is in the fifo!!!\r
assign en_pal_dac = next_pal_dac_cyc & !fifo_empty; // 100 Mhz version\r
\r
// This is the vga_clk signal\r
// No matter what happens, we must keep the vga_clk going!!!\r
assign vga_clk = next_pal_dac_cyc;\r
\r
// Behaviour\r
\r
/* FML ADDRESS GENERATOR */\r
wire next_address;\r
\r
always @(posedge clk) begin\r
if(rst) begin\r
fml_adr <= {fml_depth{1'b0}};\r
end else begin\r
if(next_address) begin\r
fml_adr[19:0] <= { (lcd_adr + { start_addr[15:1], 2'b00 }), 1'b0 };\r
end\r
end\r
end\r
\r
/* DCB ADDRESS GENERATOR */\r
reg [2:0] dcb_index;\r
\r
always @(posedge clk) begin\r
if(dcb_stb)\r
dcb_index <= dcb_index + 3'd1;\r
else\r
dcb_index <= fml_adr[2:0];\r
end\r
\r
assign dcb_adr = { fml_adr + ( { dcb_index, 1'b0 } ) };\r
\r
\r
/* CONTROLLER */\r
reg [4:0] state;\r
reg [4:0] next_state;\r
localparam [4:0]\r
IDLE = 5'd0,\r
DELAY = 5'b1, \r
TRYCACHE = 5'd2,\r
CACHE1 = 5'd3,\r
CACHE2 = 5'd4,\r
CACHE3 = 5'd5,\r
CACHE4 = 5'd6,\r
CACHE5 = 5'd7,\r
CACHE6 = 5'd8,\r
CACHE7 = 5'd9,\r
CACHE8 = 5'd10,\r
FML1 = 5'd11,\r
FML2 = 5'd12,\r
FML3 = 5'd13,\r
FML4 = 5'd14,\r
FML5 = 5'd15,\r
FML6 = 5'd16,\r
FML7 = 5'd17,\r
FML8 = 5'd18;\r
\r
always @(posedge clk) begin\r
if(rst)\r
state <= IDLE; \r
else\r
state <= next_state;\r
end\r
\r
reg next_burst;\r
\r
assign next_address = next_burst;\r
\r
always @(*) begin\r
next_state = state;\r
\r
next_crtc_seq_cyc = 1'b0;\r
next_burst = 1'b0;\r
\r
fml_stb = 1'b0;\r
\r
dcb_stb = 1'b0;\r
fifo_source_cache = 1'b0;\r
\r
case(state)\r
IDLE: begin\r
if (can_burst & !fifo_full) begin\r
if (lcd_stb) begin\r
/* LCD is requesting another fml burst ! */\r
next_burst = 1'b1; // This also calculates final address\r
next_crtc_seq_cyc = 1'b1;\r
next_state = DELAY;\r
end else\r
next_crtc_seq_cyc = 1'b1;\r
end\r
end\r
DELAY: begin\r
next_crtc_seq_cyc = 1'b1;\r
next_state = TRYCACHE;\r
end\r
/* Try to fetch from L2 first */\r
TRYCACHE: begin\r
dcb_stb = 1'b1;\r
next_crtc_seq_cyc = 1'b1;\r
next_state = CACHE1;\r
end\r
CACHE1: begin\r
fifo_source_cache = 1'b1;\r
if(dcb_hit) begin\r
dcb_stb = 1'b1;\r
next_crtc_seq_cyc = 1'b1;\r
next_state = CACHE2;\r
end else\r
next_state = FML1; /* Not in L2 cache, fetch from DRAM */\r
end\r
/* No need to check for cache hits anymore:\r
* - we fetched from the beginning of a line\r
* - we fetch exactly a line\r
* - we do not release dcb_stb so the cache controller locks the line\r
* Therefore, next 7 fetchs always are cache hits.\r
*/\r
CACHE2: begin\r
dcb_stb = 1'b1;\r
fifo_source_cache = 1'b1;\r
next_crtc_seq_cyc = 1'b1;\r
next_state = CACHE3;\r
end\r
CACHE3: begin\r
dcb_stb = 1'b1;\r
fifo_source_cache = 1'b1;\r
next_crtc_seq_cyc = 1'b1;\r
next_state = CACHE4;\r
end\r
CACHE4: begin\r
dcb_stb = 1'b1;\r
fifo_source_cache = 1'b1;\r
next_crtc_seq_cyc = 1'b1;\r
next_state = CACHE5;\r
end\r
CACHE5: begin\r
dcb_stb = 1'b1;\r
fifo_source_cache = 1'b1;\r
next_crtc_seq_cyc = 1'b1;\r
next_state = CACHE6;\r
end\r
CACHE6: begin\r
dcb_stb = 1'b1;\r
fifo_source_cache = 1'b1;\r
next_crtc_seq_cyc = 1'b1;\r
next_state = CACHE7;\r
end\r
CACHE7: begin\r
dcb_stb = 1'b1;\r
fifo_source_cache = 1'b1;\r
next_crtc_seq_cyc = 1'b1;\r
next_state = CACHE8;\r
end\r
CACHE8: begin\r
fifo_source_cache = 1'b1;\r
next_crtc_seq_cyc = 1'b1;\r
next_state = IDLE;\r
end\r
FML1: begin\r
fml_stb = 1'b1;\r
if(fml_ack) begin\r
next_crtc_seq_cyc = 1'b1;\r
next_state = FML2;\r
end\r
end\r
FML2: begin\r
next_crtc_seq_cyc = 1'b1;\r
next_state = FML3;\r
end\r
FML3: begin\r
next_crtc_seq_cyc = 1'b1;\r
next_state = FML4;\r
end\r
FML4: begin\r
next_crtc_seq_cyc = 1'b1;\r
next_state = FML5;\r
end\r
FML5: begin\r
next_crtc_seq_cyc = 1'b1;\r
next_state = FML6;\r
end\r
FML6: begin\r
next_crtc_seq_cyc = 1'b1;\r
next_state = FML7;\r
end\r
FML7: begin\r
next_crtc_seq_cyc = 1'b1;\r
next_state = FML8;\r
end\r
FML8: begin\r
next_crtc_seq_cyc = 1'b1;\r
next_state = IDLE;\r
end\r
endcase\r
end\r
\r
// Provide counter for pal_dac stage\r
always @(posedge clk)\r
if (rst)\r
begin\r
pixel_clk_counter <= 2'b00;\r
end\r
else\r
begin\r
if (pixel_clk_counter == 2'd00) // Toggle next_pal_dac_cyc\r
next_pal_dac_cyc <=1'b1;\r
else next_pal_dac_cyc <= 1'b0;\r
\r
pixel_clk_counter <= pixel_clk_counter + 2'b01; // Roll over every four cycles\r
end\r
\r
endmodule\r
|
/*
* PC speaker module without any codec
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module speaker (
// Clocks
input clk,
input rst,
// Wishbone slave interface
input [7:0] wb_dat_i,
output reg [7:0] wb_dat_o,
input wb_we_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// Timer clock
input timer2,
// Speaker pad signal
output speaker_
);
// Net declarations
wire write;
wire spk;
// Combinatorial logic
// System speaker
assign speaker_ = timer2 & wb_dat_o[1];
// Wishbone signals
assign wb_ack_o = wb_stb_i && wb_cyc_i;
assign write = wb_stb_i && wb_cyc_i && wb_we_i;
// Sequential logic
always @(posedge clk)
wb_dat_o <= rst ? 8'h0 : (write ? wb_dat_i : wb_dat_o);
endmodule
|
// --------------------------------------------------------------------
// Copyright (c) 2005 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altrea Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL or Verilog source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email: [email protected]
//
// --------------------------------------------------------------------
//
// Major Functions:i2c controller
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Joe Yang :| 05/07/10 :| Initial Revision
// --------------------------------------------------------------------
module speaker_i2c_controller (
\tCLOCK,
\tI2C_SCLK,//I2C CLOCK
\tI2C_SDAT,//I2C DATA
\tI2C_DATA,//DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
\tGO, //GO transfor
\tEND, //END transfor
\tW_R, //W_R
\tACK, //ACK
\tRESET
);
\tinput CLOCK;
\tinput [23:0]I2C_DATA;\t
\tinput GO;
\tinput RESET;\t
\tinput W_R;
\tinout I2C_SDAT;\t
\toutput I2C_SCLK;
\toutput END;\t
\toutput ACK;
reg SDO;
reg SCLK;
reg END;
reg [23:0]SD;
reg [5:0]SD_COUNTER;
wire I2C_SCLK=SCLK | ( ((SD_COUNTER >= 4) & (SD_COUNTER <=30))? ~CLOCK :1'b0 );
wire I2C_SDAT=SDO?1'bz:1'b0 ;
reg ACK1,ACK2,ACK3;
wire ACK=ACK1 | ACK2 |ACK3;
//--I2C COUNTER
always @(posedge CLOCK)begin
if (RESET)
SD_COUNTER <= 6'b111111;
else
begin
if (!GO)
SD_COUNTER <= 6'd0;
else
if (SD_COUNTER < 6'b111111) SD_COUNTER <= SD_COUNTER + 6'b1;
end
end
//----
always @(posedge CLOCK)
begin
if (RESET)
begin
SCLK <= 1'b1;
SDO <= 1'b1;
ACK1 <= 1'b0;
ACK2 <= 1'b0;
ACK3 <= 1'b0;
END <= 1'b1;
end
else
case (SD_COUNTER)
6'd0:
begin
ACK1 <= 1'b0;
ACK2 <= 1'b0;
ACK3 <= 1'b0;
END <= 1'b0;
SDO <= 1'b1;
SCLK <= 1'b1;
end
//start
6'd1:
begin
SD <= I2C_DATA;
SDO <= 1'b0;
end
6'd2: SCLK <= 1'b0;
//SLAVE ADDR
6'd3: SDO <= SD[23];
\t6'd4 : SDO<=SD[22];
\t6'd5 : SDO<=SD[21];
\t6'd6 : SDO<=SD[20];
\t6'd7 : SDO<=SD[19];
\t6'd8 : SDO<=SD[18];
\t6'd9 : SDO<=SD[17];
\t6'd10 : SDO<=SD[16];\t
\t6'd11 : SDO<=1'b1;//ACK
\t//SUB ADDR
\t6'd12 : begin SDO<=SD[15]; ACK1<=I2C_SDAT; end
\t6'd13 : SDO<=SD[14];
\t6'd14 : SDO<=SD[13];
\t6'd15 : SDO<=SD[12];
\t6'd16 : SDO<=SD[11];
\t6'd17 : SDO<=SD[10];
\t6'd18 : SDO<=SD[9];
\t6'd19 : SDO<=SD[8];
\t6'd20 : SDO<=1'b1;//ACK
\t//DATA
\t6'd21 : begin SDO<=SD[7]; ACK2<=I2C_SDAT; end
\t6'd22 : SDO<=SD[6];
\t6'd23 : SDO<=SD[5];
\t6'd24 : SDO<=SD[4];
\t6'd25 : SDO<=SD[3];
\t6'd26 : SDO<=SD[2];
\t6'd27 : SDO<=SD[1];
\t6'd28 : SDO<=SD[0];
\t6'd29 : SDO<=1'b1;//ACK
\t
\t//stop
6'd30 : begin SDO<=1'b0;\tSCLK<=1'b0; ACK3<=I2C_SDAT; end\t
6'd31 : SCLK<=1'b1;
6'd32 : begin SDO<=1'b1; END<=1; end
endcase
end
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
* adjusted to FML 8x16 by Zeus Gomez Marmolejo <[email protected]>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc #(
parameter csr_addr = 1\'b0,
/*
* The depth of the SDRAM array, in bytes.
* Capacity (in bytes) is 2^sdram_depth.
*/
parameter sdram_depth = 23,
/*
* The number of column address bits of the SDRAM.
*/
parameter sdram_columndepth = 8,
/*
* Address Mapping :
* | ROW ADDRESS | BANK NUMBER | COL ADDRESS | for 16-bit words
* |depth-1 coldepth+2|coldepth+1 coldepth|coldepth-1 0|
* (depth for 16-bit words, which is sdram_depth-1)
*/
parameter sdram_addrdepth = sdram_depth-1-1-(sdram_columndepth+2)+1
)(
input sys_clk,
\tinput sys_rst,
\t
\t/* Control interface */
\tinput [2:0] csr_a,
\tinput csr_we,
\tinput [15:0] csr_di,
\toutput [15:0] csr_do,
\t
\t/* Simple FML 8x16 interface to the memory contents */
\tinput [sdram_depth-1:0] fml_adr,
\tinput fml_stb,
\tinput fml_we,
\toutput fml_ack,
\tinput [1:0] fml_sel,
\tinput [15:0] fml_di,
\toutput [15:0] fml_do,
\t
\t/* SDRAM interface.
\t * The SDRAM clock should be driven synchronously to the system clock.
\t * It is not generated inside this core so you can take advantage of
\t * architecture-dependent clocking resources to generate a clean
\t * differential clock.
\t */
\toutput reg sdram_cke,
\toutput reg sdram_cs_n,
\toutput reg sdram_we_n,
\toutput reg sdram_cas_n,
\toutput reg sdram_ras_n,
\toutput reg [sdram_addrdepth-1:0] sdram_adr,
\toutput reg [1:0] sdram_ba,
\t
\toutput [1:0] sdram_dqm,
\tinout [15:0] sdram_dq
);
/* Register all control signals, leaving the possibility to use IOB registers */
wire sdram_cke_r;
wire sdram_cs_n_r;
wire sdram_we_n_r;
wire sdram_cas_n_r;
wire sdram_ras_n_r;
wire [sdram_addrdepth-1:0] sdram_adr_r;
wire [1:0] sdram_ba_r;
always @(posedge sys_clk) begin
\tsdram_cke <= sdram_cke_r;
\tsdram_cs_n <= sdram_cs_n_r;
\tsdram_we_n <= sdram_we_n_r;
\tsdram_cas_n <= sdram_cas_n_r;
\tsdram_ras_n <= sdram_ras_n_r;
\tsdram_ba <= sdram_ba_r;
\tsdram_adr <= sdram_adr_r;
end
/* Mux the control signals according to the "bypass" selection.
* CKE always comes from the control interface.
*/
wire bypass;
wire sdram_cs_n_bypass;
wire sdram_we_n_bypass;
wire sdram_cas_n_bypass;
wire sdram_ras_n_bypass;
wire [sdram_addrdepth-1:0] sdram_adr_bypass;
wire [1:0] sdram_ba_bypass;
wire sdram_cs_n_mgmt;
wire sdram_we_n_mgmt;
wire sdram_cas_n_mgmt;
wire sdram_ras_n_mgmt;
wire [sdram_addrdepth-1:0] sdram_adr_mgmt;
wire [1:0] sdram_ba_mgmt;
assign sdram_cs_n_r = bypass ? sdram_cs_n_bypass : sdram_cs_n_mgmt;
assign sdram_we_n_r = bypass ? sdram_we_n_bypass : sdram_we_n_mgmt;
assign sdram_cas_n_r = bypass ? sdram_cas_n_bypass : sdram_cas_n_mgmt;
assign sdram_ras_n_r = bypass ? sdram_ras_n_bypass : sdram_ras_n_mgmt;
assign sdram_adr_r = bypass ? sdram_adr_bypass : sdram_adr_mgmt;
assign sdram_ba_r = bypass ? sdram_ba_bypass : sdram_ba_mgmt;
/* Control interface */
wire sdram_rst;
wire [2:0] tim_rp;
wire [2:0] tim_rcd;
wire tim_cas;
wire [10:0] tim_refi;
wire [3:0] tim_rfc;
wire [1:0] tim_wr;
hpdmc_ctlif #(
\t.csr_addr (csr_addr),
\t.sdram_addrdepth (sdram_addrdepth)
) ctlif (
\t.sys_clk(sys_clk),
\t.sys_rst(sys_rst),
\t
\t.csr_a(csr_a),
\t.csr_we(csr_we),
\t.csr_di(csr_di),
\t.csr_do(csr_do),
\t
\t.bypass(bypass),
\t.sdram_rst(sdram_rst),
\t
\t.sdram_cke(sdram_cke_r),
\t.sdram_cs_n(sdram_cs_n_bypass),
\t.sdram_we_n(sdram_we_n_bypass),
\t.sdram_cas_n(sdram_cas_n_bypass),
\t.sdram_ras_n(sdram_ras_n_bypass),
\t.sdram_adr(sdram_adr_bypass),
\t.sdram_ba(sdram_ba_bypass),
\t
\t.tim_rp(tim_rp),
\t.tim_rcd(tim_rcd),
\t.tim_cas(tim_cas),
\t.tim_refi(tim_refi),
\t.tim_rfc(tim_rfc),
\t.tim_wr(tim_wr)
);
/* SDRAM management unit */
wire mgmt_stb;
wire mgmt_we;
wire [sdram_depth-1-1:0] mgmt_address;
wire mgmt_ack;
wire read;
wire write;
wire [3:0] concerned_bank;
wire read_safe;
wire write_safe;
wire [3:0] precharge_safe;
hpdmc_mgmt #(
\t.sdram_depth(sdram_depth),
\t.sdram_columndepth(sdram_columndepth)
) mgmt (
\t.sys_clk(sys_clk),
\t.sdram_rst(sdram_rst),
\t
\t.tim_rp(tim_rp),
\t.tim_rcd(tim_rcd),
\t.tim_refi(tim_refi),
\t.tim_rfc(tim_rfc),
\t
\t.stb(mgmt_stb),
\t.we(mgmt_we),
\t.address(mgmt_address),
\t.ack(mgmt_ack),
\t
\t.read(read),
\t.write(write),
\t.concerned_bank(concerned_bank),
\t.read_safe(read_safe),
\t.write_safe(write_safe),
\t.precharge_safe(precharge_safe),
\t
\t.sdram_cs_n(sdram_cs_n_mgmt),
\t.sdram_we_n(sdram_we_n_mgmt),
\t.sdram_cas_n(sdram_cas_n_mgmt),
\t.sdram_ras_n(sdram_ras_n_mgmt),
\t.sdram_adr(sdram_adr_mgmt),
\t.sdram_ba(sdram_ba_mgmt)
);
/* Bus interface */
wire data_ack;
hpdmc_busif #(
\t.sdram_depth(sdram_depth)
) busif (
\t.sys_clk(sys_clk),
\t.sdram_rst(sdram_rst),
\t
\t.fml_adr(fml_adr),
\t.fml_stb(fml_stb),
\t.fml_we(fml_we),
\t.fml_ack(fml_ack),
\t
\t.mgmt_stb(mgmt_stb),
\t.mgmt_we(mgmt_we),
\t.mgmt_address(mgmt_address),
\t.mgmt_ack(mgmt_ack),
\t
\t.data_ack(data_ack)
);
/* Data path controller */
wire direction;
wire direction_r;
hpdmc_datactl datactl(
\t.sys_clk(sys_clk),
\t.sdram_rst(sdram_rst),
\t
\t.read(read),
\t.write(write),
\t.concerned_bank(concerned_bank),
\t.read_safe(read_safe),
\t.write_safe(write_safe),
\t.precharge_safe(precharge_safe),
\t
\t.ack(data_ack),
\t.direction(direction),
\t.direction_r(direction_r),
\t
\t.tim_cas(tim_cas),
\t.tim_wr(tim_wr)
);
/* Data path */
hpdmc_sdrio sdrio(
\t.sys_clk(sys_clk),
\t
\t.direction(direction),
\t.direction_r(direction_r),
\t/* Bit meaning is the opposite between
\t * the FML selection signal and SDRAM DQM pins.
\t */
\t.mo(~fml_sel),
\t.dout(fml_di),
\t.di(fml_do),
\t
\t.sdram_dqm(sdram_dqm),
\t.sdram_dq(sdram_dq)
);
endmodule
|
/*
* Microcode execution stage for Zet
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/10ps
`include "defines.v"
module zet_exec (
input clk,
input rst,
input [`IR_SIZE-1:0] ir,
input [15:0] off,
input [15:0] imm,
output [15:0] cs,
output [15:0] ip,
output of,
output zf,
output cx_zero,
input [15:0] memout,
output [15:0] wr_data,
output [19:0] addr,
output we,
output m_io,
output byteop,
input block,
output div_exc,
input wrip0,
output ifl,
output tfl,
output wr_ss
);
// Net declarations
wire [15:0] c;
wire [15:0] omemalu;
wire [ 3:0] addr_a;
wire [ 3:0] addr_c;
wire [ 3:0] addr_d;
wire [ 8:0] flags;
wire [15:0] a, b, s, alu_iflags, bus_b;
wire [31:0] aluout;
wire [3:0] addr_b;
wire [2:0] t, func;
wire [1:0] addr_s;
wire wrfl, high, memalu, r_byte, c_byte;
wire wr, wr_reg;
wire wr_cnd;
wire jmp;
wire b_imm;
wire [8:0] iflags, oflags;
wire [4:0] logic_flags;
wire alu_word;
wire a_byte;
wire b_byte;
wire wr_high;
wire dive;
// Module instances
zet_alu alu( {c, a }, bus_b, aluout, t, func, alu_iflags, oflags,
alu_word, s, off, clk, dive);
zet_regfile regfile (
a, b, c, cs, ip, {aluout[31:16], omemalu}, s, flags, wr_reg, wrfl,
wr_high, clk, rst, addr_a, addr_b, addr_c, addr_d, addr_s, iflags,
~byteop, a_byte, b_byte, c_byte, cx_zero, wrip0);
zet_jmp_cond jmp_cond (logic_flags, addr_b, addr_c[0], c, jmp);
// Assignments
assign addr_s = ir[1:0];
assign addr_a = ir[5:2];
assign addr_b = ir[9:6];
assign addr_c = ir[13:10];
assign addr_d = ir[17:14];
assign wrfl = ir[18];
assign we = ir[19];
assign wr = ir[20];
assign wr_cnd = ir[21];
assign high = ir[22];
assign t = ir[25:23];
assign func = ir[28:26];
assign byteop = ir[29];
assign memalu = ir[30];
assign m_io = ir[32];
assign b_imm = ir[33];
assign r_byte = ir[34];
assign c_byte = ir[35];
assign omemalu = memalu ? aluout[15:0] : memout;
assign bus_b = b_imm ? imm : b;
assign addr = aluout[19:0];
assign wr_data = c;
assign wr_reg = (wr | (jmp & wr_cnd)) && !block && !div_exc;
assign wr_high = high && !block && !div_exc;
assign of = flags[8];
assign ifl = flags[6];
assign tfl = flags[5];
assign zf = flags[3];
assign iflags = oflags;
assign alu_iflags = { 4\'b1111, flags[8:3], 1\'b0, flags[2], 1\'b0, flags[1],
1\'b1, flags[0] };
assign logic_flags = { flags[8], flags[4], flags[3], flags[1], flags[0] };
assign alu_word = (t==3\'b011) ? ~r_byte : ~byteop;
assign a_byte = (t==3\'b011 && func[1]) ? 1\'b0 : r_byte;
assign b_byte = r_byte;
assign div_exc = dive && wr;
assign wr_ss = (addr_d == 4\'b1010) && wr;
endmodule
|
// --------------------------------------------------------------------
// Copyright (c) 2005 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altrea Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL or Verilog source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email: [email protected]
//
// --------------------------------------------------------------------
//`define I2C_VIDEO
module speaker_i2c_av_config ( // Host Side
clk_i,
rst_i,
// I2C Side
i2c_sclk,
i2c_sdat );
// Host Side
input clk_i;
input rst_i;
// I2C Side
output i2c_sclk;
inout i2c_sdat;
// Internal Registers/Wires
reg [15:0] mI2C_CLK_DIV;
reg [23:0] mI2C_DATA;
reg mI2C_CTRL_CLK;
reg mI2C_GO;
wire mI2C_END;
wire mI2C_ACK;
reg [15:0] LUT_DATA;
reg [5:0] LUT_INDEX;
reg [3:0] mSetup_ST;
// Clock Setting
parameter CLK_Freq = 25000000; // 25 MHz
parameter I2C_Freq = 20000; // 20 KHz
// LUT Data Number
`ifdef I2C_VIDEO
parameter LUT_SIZE = 50;
`else
parameter LUT_SIZE = 10;
`endif
// Audio Data Index
parameter SET_LIN_L = 0;
parameter SET_LIN_R = 1;
parameter SET_HEAD_L = 2;
parameter SET_HEAD_R = 3;
parameter A_PATH_CTRL = 4;
parameter D_PATH_CTRL = 5;
parameter POWER_ON = 6;
parameter SET_FORMAT = 7;
parameter SAMPLE_CTRL = 8;
parameter SET_ACTIVE = 9;
`ifdef I2C_VIDEO
// Video Data Index
parameter SET_VIDEO = 10;
`endif
///////////////////// I2C Control Clock ////////////////////////
always@(posedge clk_i)
begin
if(rst_i)
begin
mI2C_CTRL_CLK <= 0;
mI2C_CLK_DIV <= 0;
end
else
begin
if( mI2C_CLK_DIV < (CLK_Freq/I2C_Freq) )
mI2C_CLK_DIV <= mI2C_CLK_DIV+16'h1;
else
begin
mI2C_CLK_DIV <= 0;
mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK;
end
end
end
////////////////////////////////////////////////////////////////////
speaker_i2c_controller i2c_controller ( .CLOCK(mI2C_CTRL_CLK), // Controller Work Clock
.I2C_SCLK(i2c_sclk), // I2C CLOCK
.I2C_SDAT(i2c_sdat), // I2C DATA
.I2C_DATA(mI2C_DATA), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
.GO(mI2C_GO), // GO transfor
.END(mI2C_END), // END transfor
.ACK(mI2C_ACK), // ACK
.RESET(rst_i),
.W_R (1'b0)
);
////////////////////////////////////////////////////////////////////
////////////////////// Config Control ////////////////////////////
always@(posedge mI2C_CTRL_CLK)
begin
if(rst_i)
begin
LUT_INDEX <= 0;
mSetup_ST <= 0;
mI2C_GO <= 0;
end
else
begin
if(LUT_INDEX<LUT_SIZE)
begin
case(mSetup_ST)
0: begin
`ifdef I2C_VIDEO
if(LUT_INDEX>=SET_VIDEO)
mI2C_DATA <= {8'h40,LUT_DATA};
else
`endif
mI2C_DATA <= {8'h34,LUT_DATA};
mI2C_GO <= 1;
mSetup_ST <= 1;
end
1: begin
if(mI2C_END)
begin
if(!mI2C_ACK)
mSetup_ST <= 2;
else
mSetup_ST <= 0;
mI2C_GO <= 0;
end
end
2: begin
LUT_INDEX <= LUT_INDEX+6'h1;
mSetup_ST <= 0;
end
endcase
end
end
end
////////////////////////////////////////////////////////////////////
///////////////////// Config Data LUT //////////////////////////
always
begin
case(LUT_INDEX)
// Audio Config Data
SET_LIN_L : LUT_DATA <= 16'h001A;
SET_LIN_R : LUT_DATA <= 16'h021A;
SET_HEAD_L : LUT_DATA <= 16'h047B;
SET_HEAD_R : LUT_DATA <= 16'h067B;
A_PATH_CTRL : LUT_DATA <= 16'h08F8;
D_PATH_CTRL : LUT_DATA <= 16'h0A06;
POWER_ON : LUT_DATA <= 16'h0C00;
SET_FORMAT : LUT_DATA <= 16'h0E42;
SAMPLE_CTRL : LUT_DATA <= 16'h107C;
SET_ACTIVE : LUT_DATA <= 16'h1201;
`ifdef I2C_VIDEO
// Video Config Data
SET_VIDEO+0 : LUT_DATA <= 16'h1500;
SET_VIDEO+1 : LUT_DATA <= 16'h1741;
SET_VIDEO+2 : LUT_DATA <= 16'h3a16;
SET_VIDEO+3 : LUT_DATA <= 16'h5004;
SET_VIDEO+4 : LUT_DATA <= 16'hc305;
SET_VIDEO+5 : LUT_DATA <= 16'hc480;
SET_VIDEO+6 : LUT_DATA <= 16'h0e80;
SET_VIDEO+7 : LUT_DATA <= 16'h5020;
SET_VIDEO+8 : LUT_DATA <= 16'h5218;
SET_VIDEO+9 : LUT_DATA <= 16'h58ed;
SET_VIDEO+10: LUT_DATA <= 16'h77c5;
SET_VIDEO+11: LUT_DATA <= 16'h7c93;
SET_VIDEO+12: LUT_DATA <= 16'h7d00;
SET_VIDEO+13: LUT_DATA <= 16'hd048;
SET_VIDEO+14: LUT_DATA <= 16'hd5a0;
SET_VIDEO+15: LUT_DATA <= 16'hd7ea;
SET_VIDEO+16: LUT_DATA <= 16'he43e;
SET_VIDEO+17: LUT_DATA <= 16'hea0f;
SET_VIDEO+18: LUT_DATA <= 16'h3112;
SET_VIDEO+19: LUT_DATA <= 16'h3281;
SET_VIDEO+20: LUT_DATA <= 16'h3384;
SET_VIDEO+21: LUT_DATA <= 16'h37A0;
SET_VIDEO+22: LUT_DATA <= 16'he580;
SET_VIDEO+23: LUT_DATA <= 16'he603;
SET_VIDEO+24: LUT_DATA <= 16'he785;
SET_VIDEO+25: LUT_DATA <= 16'h5000;
SET_VIDEO+26: LUT_DATA <= 16'h5100;
SET_VIDEO+27: LUT_DATA <= 16'h0050;
SET_VIDEO+28: LUT_DATA <= 16'h1000;
SET_VIDEO+29: LUT_DATA <= 16'h0402;
SET_VIDEO+30: LUT_DATA <= 16'h0b00;
SET_VIDEO+31: LUT_DATA <= 16'h0a20;
SET_VIDEO+32: LUT_DATA <= 16'h1100;
SET_VIDEO+33: LUT_DATA <= 16'h2b00;
SET_VIDEO+34: LUT_DATA <= 16'h2c8c;
SET_VIDEO+35: LUT_DATA <= 16'h2df2;
SET_VIDEO+36: LUT_DATA <= 16'h2eee;
SET_VIDEO+37: LUT_DATA <= 16'h2ff4;
SET_VIDEO+38: LUT_DATA <= 16'h30d2;
SET_VIDEO+39: LUT_DATA <= 16'h0e05;
`endif
default: LUT_DATA <= 16'h0000;
endcase
end
////////////////////////////////////////////////////////////////////
endmodule
|
/*
* Wishbone Compatible BIOS ROM core using megafunction ROM
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
// The following is to get rid of the warning about not initializing the ROM
// altera message_off 10030
module bootrom (
input clk,
input rst,
// Wishbone slave interface
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [19:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input wb_stb_i,
input wb_cyc_i,
input [ 1:0] wb_sel_i,
output wb_ack_o
);
// Net declarations
reg [15:0] rom[0:127]; // Instantiate the ROM
wire [ 6:0] rom_addr;
wire stb;
// Combinatorial logic
assign rom_addr = wb_adr_i[7:1];
assign stb = wb_stb_i & wb_cyc_i;
assign wb_ack_o = stb;
assign wb_dat_o = rom[rom_addr];
initial $readmemh("bootrom.dat", rom);
endmodule
|
/*
* DE1/DE2 Audio Interface (WM8731 audio chip)
* Copyright (c) 2010 YS <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
/*
* - aud_xck should be generated and sent to audio chip externally
* - Setup in I2C_AV_Config.v:
* SET_FORMAT: 16'h0E42 (Slave / I2S / 16 bit)
* - aud_xck = 11.2896 MHz
* MCLK = aud_xck = 11.2896 MHz
* SAMPLE_CTRL: 16'h1020 (fs=44.1kHz / MCLK=256fs)
* - aud_xck = 5.6448 MHz
* MCLK = aud_xck = 5.6448 MHz
* SAMPLE_CTRL: 16'h103C (fs=44.1kHz / MCLK=128fs)
* - aud_xck = 11.2896 MHz
* MCLK = aud_xck/2 = 5.6448 MHz
* SAMPLE_CTRL: 16'h107C (fs=44.1kHz / MCLK=128fs)
* - clk_i should be much faster than aud_bclk_i
* - suppose in slave mode aud_daclrck_i == aud_adclrck_i, otherwise
* aud_adclrck_i may need separate processing and ready_o should
* be splitted into readydac_o and readyadc_o
* - ADC part is not tested
*/
module speaker_iface
(
// Main system interface
input clk_i,
input rst_i,
input signed [15:0] datal_i,
input signed [15:0] datar_i,
output reg signed [15:0] datal_o,
output reg signed [15:0] datar_o,
output reg ready_o,
// output reg readydac_o, // not used
// output reg readyadc_o, // not used
// Audio interface
input aud_bclk_i,
input aud_daclrck_i,
output reg aud_dacdat_o,
input aud_adcdat_i
);
reg fBCLK_HL;
// reg fBCLK_LH;
reg bCurrentClk;
reg bFilterClk1;
reg bFilterClk2;
reg bDACLRCK_old;
reg bDACLRCK;
reg [15:0] rDAC;
reg [15:0] rADC;
reg fADCReady;
// Synchronizing BCLK with clk_i
always @(posedge clk_i or posedge rst_i)
begin
if (rst_i)
begin
fBCLK_HL <= 1'b0;
// fBCLK_LH <= 1'b0;
bCurrentClk <= 1'b0;
bFilterClk1 <= 1'b0;
bFilterClk2 <= 1'b0;
end
else
begin
bFilterClk1 <= aud_bclk_i;
bFilterClk2 <= bFilterClk1;
if ((bFilterClk1 == bFilterClk2) && (bCurrentClk != bFilterClk2))
begin
bCurrentClk <= bFilterClk2;
if (bCurrentClk == 1'b1)
fBCLK_HL <= 1'b1; // falling edge of aud_bclk_i
// else
// fBCLK_LH <= 1'b1; // rising edge of aud_bclk_i
end
if (fBCLK_HL)
fBCLK_HL <= 1'b0; // 1 clock pulse fBCLK_HL
// if (fBCLK_LH)
// fBCLK_LH <= 1'b0; // 1 clock pulse fBCLK_LH
end
end
// Filtering aud_daclrck_i
always @(posedge clk_i)
bDACLRCK <= aud_daclrck_i;
// Processsing BCLK
always @(posedge clk_i)
begin
if (fBCLK_HL)
begin
bDACLRCK_old <= bDACLRCK;
if (bDACLRCK != bDACLRCK_old)
begin
// DAC write
rDAC <= (bDACLRCK) ? datar_i : datal_i;
aud_dacdat_o <= 1'b0;
// ADC read
if (bDACLRCK)
datal_o <= rADC;
else
datar_o <= rADC;
rADC <= 16'h0001;
fADCReady <= 1'b0;
// ready pulse
ready_o <= ~bDACLRCK;
end
else
begin
//DAC shift
{ aud_dacdat_o, rDAC } <= { rDAC, 1'b0 };
// ADC shift
if (!fADCReady)
{ fADCReady, rADC} <= { rADC, aud_adcdat_i };
end
end
else if (ready_o)
ready_o <= 1'b0; // 1 clock ready_o pulse
end
endmodule
|
/*
* Write memory interface for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga_write_iface (
// Wishbone common signals
input wb_clk_i,
input wb_rst_i,
// Wishbone slave write interface
input [16:1] wbs_adr_i,
input [ 1:0] wbs_sel_i,
input [15:0] wbs_dat_i,
input wbs_stb_i,
output wbs_ack_o,
// Wishbone master write to SRAM
output [17:1] wbm_adr_o,
output [ 1:0] wbm_sel_o,
output [15:0] wbm_dat_o,
output wbm_stb_o,
input wbm_ack_i,
// VGA configuration registers
input memory_mapping1,
input [ 1:0] write_mode,
input [ 1:0] raster_op,
input [ 7:0] bitmask,
input [ 3:0] set_reset,
input [ 3:0] enable_set_reset,
input [ 3:0] map_mask,
input [7:0] latch0,
input [7:0] latch1,
input [7:0] latch2,
input [7:0] latch3
);
// Registers and nets
wire [15:0] latch0_16;
wire [15:0] latch1_16;
wire [15:0] latch2_16;
wire [15:0] latch3_16;
wire [15:0] lb0;
wire [15:0] lb1;
wire [15:0] lb2;
wire [15:0] lb3;
wire [15:0] nlb0;
wire [15:0] nlb1;
wire [15:0] nlb2;
wire [15:0] nlb3;
wire [15:0] alb0;
wire [15:0] alb1;
wire [15:0] alb2;
wire [15:0] alb3;
wire [15:0] olb0;
wire [15:0] olb1;
wire [15:0] olb2;
wire [15:0] olb3;
wire [15:0] xlb0;
wire [15:0] xlb1;
wire [15:0] xlb2;
wire [15:0] xlb3;
wire [15:0] set0;
wire [15:0] set1;
wire [15:0] set2;
wire [15:0] set3;
wire [15:0] no_set0;
wire [15:0] no_set1;
wire [15:0] no_set2;
wire [15:0] no_set3;
wire [15:0] no_en0;
wire [15:0] no_en1;
wire [15:0] no_en2;
wire [15:0] no_en3;
wire [15:0] new_val0;
wire [15:0] new_val1;
wire [15:0] new_val2;
wire [15:0] new_val3;
/*
wire [ 7:0] wr2_d0_0;
wire [ 7:0] wr2_d0_1;
wire [ 7:0] wr2_d0_2;
wire [ 7:0] wr2_d0_3;
wire [ 7:0] wr2_d1_0;
wire [ 7:0] wr2_d1_1;
wire [ 7:0] wr2_d1_2;
wire [ 7:0] wr2_d1_3;
*/
wire [15:0] val0_write0, val0_write1, val0_write2, val0_write3;
wire [15:0] val1_write0, val1_write1, val1_write2, val1_write3;
wire [15:0] val0_or0, val0_or1, val0_or2, val0_or3;
wire [15:0] val1_or0, val1_or1, val1_or2, val1_or3;
wire [15:0] final_wr0, final_wr1, final_wr2, final_wr3;
wire [15:1] offset;
wire [15:0] bitmask16;
wire [15:0] dat_mask;
wire write_en;
wire cont;
reg [ 1:0] plane;
reg [ 3:0] plane_dec;
// Continuous assignments
assign bitmask16 = { bitmask, bitmask };
assign dat_mask = wbs_dat_i & bitmask16;
assign latch0_16 = { latch0, latch0 };
assign latch1_16 = { latch1, latch1 };
assign latch2_16 = { latch2, latch2 };
assign latch3_16 = { latch3, latch3 };
assign new_val0 = latch0_16 & ~bitmask16;
assign new_val1 = latch1_16 & ~bitmask16;
assign new_val2 = latch2_16 & ~bitmask16;
assign new_val3 = latch3_16 & ~bitmask16;
assign lb0 = latch0_16 & bitmask16;
assign lb1 = latch1_16 & bitmask16;
assign lb2 = latch2_16 & bitmask16;
assign lb3 = latch3_16 & bitmask16;
assign nlb0 = ~latch0_16 & bitmask16;
assign nlb1 = ~latch1_16 & bitmask16;
assign nlb2 = ~latch2_16 & bitmask16;
assign nlb3 = ~latch3_16 & bitmask16;
assign alb0 = (wbs_dat_i & latch0_16) & bitmask16;
assign alb1 = (wbs_dat_i & latch1_16) & bitmask16;
assign alb2 = (wbs_dat_i & latch2_16) & bitmask16;
assign alb3 = (wbs_dat_i & latch3_16) & bitmask16;
assign olb0 = (wbs_dat_i | latch0_16) & bitmask16;
assign olb1 = (wbs_dat_i | latch1_16) & bitmask16;
assign olb2 = (wbs_dat_i | latch2_16) & bitmask16;
assign olb3 = (wbs_dat_i | latch3_16) & bitmask16;
assign xlb0 = (wbs_dat_i ^ latch0_16) & bitmask16;
assign xlb1 = (wbs_dat_i ^ latch1_16) & bitmask16;
assign xlb2 = (wbs_dat_i ^ latch2_16) & bitmask16;
assign xlb3 = (wbs_dat_i ^ latch3_16) & bitmask16;
// write mode 0
assign set0 = raster_op[0] ? (raster_op[1] ? nlb0 : lb0 ) : bitmask16;
assign set1 = raster_op[0] ? (raster_op[1] ? nlb1 : lb1 ) : bitmask16;
assign set2 = raster_op[0] ? (raster_op[1] ? nlb2 : lb2 ) : bitmask16;
assign set3 = raster_op[0] ? (raster_op[1] ? nlb3 : lb3 ) : bitmask16;
assign no_set0 = raster_op[1] ? lb0 : 16'h0;
assign no_set1 = raster_op[1] ? lb1 : 16'h0;
assign no_set2 = raster_op[1] ? lb2 : 16'h0;
assign no_set3 = raster_op[1] ? lb3 : 16'h0;
assign no_en0 = raster_op[1] ? (raster_op[0] ? xlb0 : olb0)
: (raster_op[0] ? alb0 : dat_mask);
assign no_en1 = raster_op[1] ? (raster_op[0] ? xlb1 : olb1)
: (raster_op[0] ? alb1 : dat_mask);
assign no_en2 = raster_op[1] ? (raster_op[0] ? xlb2 : olb2)
: (raster_op[0] ? alb2 : dat_mask);
assign no_en3 = raster_op[1] ? (raster_op[0] ? xlb3 : olb3)
: (raster_op[0] ? alb3 : dat_mask);
assign val0_or0 = enable_set_reset[0] ?
(set_reset[0] ? set0 : no_set0) : no_en0;
assign val0_or1 = enable_set_reset[1] ?
(set_reset[1] ? set1 : no_set1) : no_en1;
assign val0_or2 = enable_set_reset[2] ?
(set_reset[2] ? set2 : no_set2) : no_en2;
assign val0_or3 = enable_set_reset[3] ?
(set_reset[3] ? set3 : no_set3) : no_en3;
assign val0_write0 = new_val0 | val0_or0;
assign val0_write1 = new_val1 | val0_or1;
assign val0_write2 = new_val2 | val0_or2;
assign val0_write3 = new_val3 | val0_or3;
// write mode 2
/*
assign wr2_d0_0 = raster_op[1] ? lb0[7:0] : 8'h0;
assign wr2_d0_1 = raster_op[1] ? lb1[7:0] : 8'h0;
assign wr2_d0_2 = raster_op[1] ? lb2[7:0] : 8'h0;
assign wr2_d0_3 = raster_op[1] ? lb3[7:0] : 8'h0;
assign wr2_d1_0 = raster_op[0] ? (raster_op[1] ? nlb0[7:0] : lb0[7:0])
: bitmask;
assign wr2_d1_1 = raster_op[0] ? (raster_op[1] ? nlb1[7:0] : lb1[7:0])
: bitmask;
assign wr2_d1_2 = raster_op[0] ? (raster_op[1] ? nlb2[7:0] : lb2[7:0])
: bitmask;
assign wr2_d1_3 = raster_op[0] ? (raster_op[1] ? nlb3[7:0] : lb3[7:0])
: bitmask;
assign val1_or0[ 7:0] = wbs_dat_i[ 0] ? wr2_d1_0 : wr2_d0_0;
assign val1_or1[ 7:0] = wbs_dat_i[ 1] ? wr2_d1_1 : wr2_d0_1;
assign val1_or2[ 7:0] = wbs_dat_i[ 2] ? wr2_d1_2 : wr2_d0_2;
assign val1_or3[ 7:0] = wbs_dat_i[ 3] ? wr2_d1_3 : wr2_d0_3;
assign val1_or0[15:8] = wbs_dat_i[ 8] ? wr2_d1_0 : wr2_d0_0;
assign val1_or1[15:8] = wbs_dat_i[ 9] ? wr2_d1_1 : wr2_d0_1;
assign val1_or2[15:8] = wbs_dat_i[10] ? wr2_d1_2 : wr2_d0_2;
assign val1_or3[15:8] = wbs_dat_i[11] ? wr2_d1_3 : wr2_d0_3;
*/
assign val1_or0[ 7:0] = wbs_dat_i[ 0] ? bitmask : 8'h0;
assign val1_or1[ 7:0] = wbs_dat_i[ 1] ? bitmask : 8'h0;
assign val1_or2[ 7:0] = wbs_dat_i[ 2] ? bitmask : 8'h0;
assign val1_or3[ 7:0] = wbs_dat_i[ 3] ? bitmask : 8'h0;
assign val1_or0[15:8] = wbs_dat_i[ 8] ? bitmask : 8'h0;
assign val1_or1[15:8] = wbs_dat_i[ 9] ? bitmask : 8'h0;
assign val1_or2[15:8] = wbs_dat_i[10] ? bitmask : 8'h0;
assign val1_or3[15:8] = wbs_dat_i[11] ? bitmask : 8'h0;
assign val1_write0 = new_val0 | val1_or0;
assign val1_write1 = new_val1 | val1_or1;
assign val1_write2 = new_val2 | val1_or2;
assign val1_write3 = new_val3 | val1_or3;
// Final write
assign final_wr0 = write_mode[1] ? val1_write0
: (write_mode[0] ? latch0_16 : val0_write0);
assign final_wr1 = write_mode[1] ? val1_write1
: (write_mode[0] ? latch1_16 : val0_write1);
assign final_wr2 = write_mode[1] ? val1_write2
: (write_mode[0] ? latch2_16 : val0_write2);
assign final_wr3 = write_mode[1] ? val1_write3
: (write_mode[0] ? latch3_16 : val0_write3);
assign offset = memory_mapping1 ? { 1'b0, wbs_adr_i[14:1] }
: wbs_adr_i[15:1];
assign wbm_adr_o = { offset, plane };
assign wbs_ack_o = (plane==2'b11 && cont);
assign wbm_dat_o = plane[1] ? (plane[0] ? final_wr3 : final_wr2)
: (plane[0] ? final_wr1 : final_wr0);
assign write_en = plane[1] ? (plane[0] ? map_mask[3] : map_mask[2])
: (plane[0] ? map_mask[1] : map_mask[0]);
assign wbm_sel_o = wbs_sel_i;
assign cont = (wbm_ack_i | !write_en) & wbs_stb_i;
assign wbm_stb_o = write_en & wbs_stb_i;
// plane
always @(posedge wb_clk_i)
plane <= wb_rst_i ? 2'b00 : (cont ? (plane + 2'b01) : plane);
endmodule
|
//////////////////////////////////////////////////////////////////////////////
// File name : s29al032d_00.v
//////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2005 Spansion, LLC.
//
// MODIFICATION HISTORY :
//
//
// version: | author: | mod date: | changes made:
// V1.0 D.Lukovic 05 May 17 Initial release
//
//////////////////////////////////////////////////////////////////////////////
//
// PART DESCRIPTION:
//
// Library: FLASH
// Technology: Flash memory
// Part: s29al032d_00
//
// Description: 32Mbit (4M x 8-Bit) Flash Memory
//
//
//
///////////////////////////////////////////////////////////////////////////////
// Known Bugs:
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ns
module s29al032d_00
(
A21 ,
A20 ,
A19 ,
A18 ,
A17 ,
A16 ,
A15 ,
A14 ,
A13 ,
A12 ,
A11 ,
A10 ,
A9 ,
A8 ,
A7 ,
A6 ,
A5 ,
A4 ,
A3 ,
A2 ,
A1 ,
A0 ,
DQ7 ,
DQ6 ,
DQ5 ,
DQ4 ,
DQ3 ,
DQ2 ,
DQ1 ,
DQ0 ,
CENeg ,
OENeg ,
WENeg ,
RESETNeg ,
ACC ,
RY
);
////////////////////////////////////////////////////////////////////////
// Port / Part Pin Declarations
////////////////////////////////////////////////////////////////////////
input A21 ;
input A20 ;
input A19 ;
input A18 ;
input A17 ;
input A16 ;
input A15 ;
input A14 ;
input A13 ;
input A12 ;
input A11 ;
input A10 ;
input A9 ;
input A8 ;
input A7 ;
input A6 ;
input A5 ;
input A4 ;
input A3 ;
input A2 ;
input A1 ;
input A0 ;
inout DQ7 ;
inout DQ6 ;
inout DQ5 ;
inout DQ4 ;
inout DQ3 ;
inout DQ2 ;
inout DQ1 ;
inout DQ0 ;
input CENeg ;
input OENeg ;
input WENeg ;
input RESETNeg ;
input ACC ;
output RY ;
// interconnect path delay signals
wire A21_ipd ;
wire A20_ipd ;
wire A19_ipd ;
wire A18_ipd ;
wire A17_ipd ;
wire A16_ipd ;
wire A15_ipd ;
wire A14_ipd ;
wire A13_ipd ;
wire A12_ipd ;
wire A11_ipd ;
wire A10_ipd ;
wire A9_ipd ;
wire A8_ipd ;
wire A7_ipd ;
wire A6_ipd ;
wire A5_ipd ;
wire A4_ipd ;
wire A3_ipd ;
wire A2_ipd ;
wire A1_ipd ;
wire A0_ipd ;
wire [21 : 0] A;
assign A = {
A21_ipd,
A20_ipd,
A19_ipd,
A18_ipd,
A17_ipd,
A16_ipd,
A15_ipd,
A14_ipd,
A13_ipd,
A12_ipd,
A11_ipd,
A10_ipd,
A9_ipd,
A8_ipd,
A7_ipd,
A6_ipd,
A5_ipd,
A4_ipd,
A3_ipd,
A2_ipd,
A1_ipd,
A0_ipd };
wire DQ7_ipd ;
wire DQ6_ipd ;
wire DQ5_ipd ;
wire DQ4_ipd ;
wire DQ3_ipd ;
wire DQ2_ipd ;
wire DQ1_ipd ;
wire DQ0_ipd ;
wire [7 : 0 ] DIn;
assign DIn = {DQ7_ipd,
DQ6_ipd,
DQ5_ipd,
DQ4_ipd,
DQ3_ipd,
DQ2_ipd,
DQ1_ipd,
DQ0_ipd };
wire [7 : 0 ] DOut;
assign DOut = {DQ7,
DQ6,
DQ5,
DQ4,
DQ3,
DQ2,
DQ1,
DQ0 };
wire CENeg_ipd ;
wire OENeg_ipd ;
wire WENeg_ipd ;
wire RESETNeg_ipd ;
wire ACC_ipd ;
wire VIO_ipd ;
// internal delays
reg HANG_out ; // Program/Erase Timing Limit
reg HANG_in ;
reg START_T1 ; // Start TimeOut
reg START_T1_in ;
reg CTMOUT ; // Sector Erase TimeOut
reg CTMOUT_in ;
reg READY_in ;
reg READY ; // Device ready after reset
reg [7 : 0] DOut_zd;
wire DQ7_Pass ;
wire DQ6_Pass ;
wire DQ5_Pass ;
wire DQ4_Pass ;
wire DQ3_Pass ;
wire DQ2_Pass ;
wire DQ1_Pass ;
wire DQ0_Pass ;
reg [7 : 0] DOut_Pass;
assign {DQ7_Pass,
DQ6_Pass,
DQ5_Pass,
DQ4_Pass,
DQ3_Pass,
DQ2_Pass,
DQ1_Pass,
DQ0_Pass } = DOut_Pass;
reg RY_zd;
parameter UserPreload = 1\'b0;
parameter mem_file_name = "none";
parameter prot_file_name = "none";
parameter secsi_file_name = "none";
parameter TimingModel = "DefaultTimingModel";
parameter DelayValues = "FROM_PLI";
parameter PartID = "s29al032d";
parameter MaxData = 255;
parameter SecSize = 65535;
parameter SecNum = 63;
parameter HiAddrBit = 21;
parameter SecSiSize = 255;
// powerup
reg PoweredUp;
//FSM control signals
reg ULBYPASS ; ////Unlock Bypass Active
reg ESP_ACT ; ////Erase Suspend
reg OTP_ACT ; ////SecSi Access
reg PDONE ; ////Prog. Done
reg PSTART ; ////Start Programming
//Program location is in protected sector
reg PERR ;
reg EDONE ; ////Ers. Done
reg ESTART ; ////Start Erase
reg ESUSP ; ////Suspend Erase
reg ERES ; ////Resume Erase
//All sectors selected for erasure are protected
reg EERR ;
//Sectors selected for erasure
reg [SecNum:0] Ers_queue; // = SecNum\'b0;
//Command Register
reg write ;
reg read ;
//Sector Address
integer SecAddr = 0;
integer SA = 0;
//Address within sector
integer Address = 0;
integer MemAddress = 0;
integer SecSiAddr = 0;
integer AS_ID = 0;
integer AS_SecSi_FP = 0;
integer AS_ID2 = 0;
//A19:A11 Don\'t Care
integer Addr ;
//glitch protection
wire gWE_n ;
wire gCE_n ;
wire gOE_n ;
reg RST ;
reg reseted ;
integer Mem[0:(SecNum+1)*(SecSize+1)-1];
//Sector Protection Status
reg [SecNum:0] Sec_Prot;
// timing check violation
reg Viol = 1\'b0;
// CFI query address
integer SecSi[0:SecSiSize];
integer CFI_array[16:79];
reg FactoryProt = 0;
integer WBData;
integer WBAddr;
reg oe = 1\'b0;
event oe_event;
event initOK;
event MergeE;
//Status reg.
reg[15:0] Status = 8\'b0;
reg[7:0] old_bit, new_bit;
integer old_int, new_int;
integer wr_cnt;
reg[7:0] temp;
integer S_ind = 0;
integer ind = 0;
integer i,j,k;
integer Debug;
//TPD_XX_DATA
time OEDQ_t;
time CEDQ_t;
time ADDRDQ_t;
time OENeg_event;
time CENeg_event;
time OENeg_posEvent;
time CENeg_posEvent;
time ADDR_event;
reg FROMOE;
reg FROMCE;
reg FROMADDR;
integer OEDQ_01;
integer CEDQ_01;
integer ADDRDQ_01;
reg[7:0] TempData;
///////////////////////////////////////////////////////////////////////////////
//Interconnect Path Delay Section
///////////////////////////////////////////////////////////////////////////////
buf (A21_ipd, A21);
buf (A20_ipd, A20);
buf (A19_ipd, A19);
buf (A18_ipd, A18);
buf (A17_ipd, A17);
buf (A16_ipd, A16);
buf (A15_ipd, A15);
buf (A14_ipd, A14);
buf (A13_ipd, A13);
buf (A12_ipd, A12);
buf (A11_ipd, A11);
buf (A10_ipd, A10);
buf (A9_ipd , A9 );
buf (A8_ipd , A8 );
buf (A7_ipd , A7 );
buf (A6_ipd , A6 );
buf (A5_ipd , A5 );
buf (A4_ipd , A4 );
buf (A3_ipd , A3 );
buf (A2_ipd , A2 );
buf (A1_ipd , A1 );
buf (A0_ipd , A0 );
buf (DQ7_ipd , DQ7 );
buf (DQ6_ipd , DQ6 );
buf (DQ5_ipd , DQ5 );
buf (DQ4_ipd , DQ4 );
buf (DQ3_ipd , DQ3 );
buf (DQ2_ipd , DQ2 );
buf (DQ1_ipd , DQ1 );
buf (DQ0_ipd , DQ0 );
buf (CENeg_ipd , CENeg );
buf (OENeg_ipd , OENeg );
buf (WENeg_ipd , WENeg );
buf (RESETNeg_ipd , RESETNeg );
buf (ACC_ipd , ACC );
///////////////////////////////////////////////////////////////////////////////
// Propagation delay Section
///////////////////////////////////////////////////////////////////////////////
nmos (DQ7 , DQ7_Pass , 1);
nmos (DQ6 , DQ6_Pass , 1);
nmos (DQ5 , DQ5_Pass , 1);
nmos (DQ4 , DQ4_Pass , 1);
nmos (DQ3 , DQ3_Pass , 1);
nmos (DQ2 , DQ2_Pass , 1);
nmos (DQ1 , DQ1_Pass , 1);
nmos (DQ0 , DQ0_Pass , 1);
nmos (RY , 1\'b0 , ~RY_zd);
wire deg;
//VHDL VITAL CheckEnable equivalents
// Address setup/hold near WE# falling edge
wire CheckEnable_A0_WE;
assign CheckEnable_A0_WE = ~CENeg && OENeg;
// Data setup/hold near WE# rising edge
wire CheckEnable_DQ0_WE;
assign CheckEnable_DQ0_WE = ~CENeg && OENeg && deg;
// Address setup/hold near CE# falling edge
wire CheckEnable_A0_CE;
assign CheckEnable_A0_CE = ~WENeg && OENeg;
// Data setup/hold near CE# rising edge
wire CheckEnable_DQ0_CE;
assign CheckEnable_DQ0_CE = ~WENeg && OENeg && deg;
specify
// tipd delays: interconnect path delays , mapped to input port delays.
// In Verilog is not necessary to declare any tipd_ delay variables,
// they can be taken from SDF file
// With all the other delays real delays would be taken from SDF file
// tpd delays
specparam tpd_RESETNeg_DQ0 =1;
specparam tpd_A0_DQ0 =1;//tacc ok
specparam tpd_CENeg_DQ0 =1;//ok
//(tCE,tCE,tDF,-,tDF,-)
specparam tpd_OENeg_DQ0 =1;//ok
//(tOE,tOE,tDF,-,tDF,-)
specparam tpd_WENeg_RY =1; //tBUSY
specparam tpd_CENeg_RY =1; //tBUSY
// tsetup values: setup time
specparam tsetup_A0_WENeg =1; //tAS edge \\
specparam tsetup_DQ0_WENeg =1; //tDS edge /
// thold values: hold times
specparam thold_A0_WENeg =1; //tAH edge \\
specparam thold_DQ0_CENeg =1; //tDH edge /
specparam thold_OENeg_WENeg =1; //tOEH edge /
specparam thold_CENeg_RESETNeg =1; //tRH edge /
specparam thold_WENeg_OENeg =1; //tGHVL edge /
// tpw values: pulse width
specparam tpw_RESETNeg_negedge =1; //tRP
specparam tpw_WENeg_negedge =1; //tWP
specparam tpw_WENeg_posedge =1; //tWPH
specparam tpw_CENeg_negedge =1; //tCP
specparam tpw_CENeg_posedge =1; //tCEPH
specparam tpw_A0_negedge =1; //tWC tRC ok
specparam tpw_A0_posedge =1; //tWC tRC ok
// tdevice values: values for internal delays
//Program Operation
specparam tdevice_POB = 9000; //9 us;
//Sector Erase Operation
specparam tdevice_SEO = 700000000; //700 ms;
//Timing Limit Exceeded
specparam tdevice_HANG = 400000000; //400 ms;
//Erase suspend time
specparam tdevice_START_T1 = 20000; //20 us;
//sector erase command sequence timeout
specparam tdevice_CTMOUT = 50000; //50 us;
//device ready after Hardware reset(during embeded algorithm)
specparam tdevice_READY = 20000; //20 us; //tReady
// If tpd values are fetched from specify block, these parameters
// must change along with SDF values, SDF values change will NOT
// imlicitly apply here !
// If you want tpd values to be fetched by the model itself, please
// use the PLI routine approach but be shure to set parameter
// DelayValues to "FROM_PLI" as default
///////////////////////////////////////////////////////////////////////////////
// Input Port Delays don\'t require Verilog description
///////////////////////////////////////////////////////////////////////////////
// Path delays //
///////////////////////////////////////////////////////////////////////////////
//for DQ signals
if (FROMCE)
( CENeg => DQ0 ) = tpd_CENeg_DQ0;
if (FROMCE)
( CENeg => DQ1 ) = tpd_CENeg_DQ0;
if (FROMCE)
( CENeg => DQ2 ) = tpd_CENeg_DQ0;
if (FROMCE)
( CENeg => DQ3 ) = tpd_CENeg_DQ0;
if (FROMCE)
( CENeg => DQ4 ) = tpd_CENeg_DQ0;
if (FROMCE)
( CENeg => DQ5 ) = tpd_CENeg_DQ0;
if (FROMCE)
( CENeg => DQ6 ) = tpd_CENeg_DQ0;
if (FROMCE)
( CENeg => DQ7 ) = tpd_CENeg_DQ0;
if (FROMOE)
( OENeg => DQ0 ) = tpd_OENeg_DQ0;
if (FROMOE)
( OENeg => DQ1 ) = tpd_OENeg_DQ0;
if (FROMOE)
( OENeg => DQ2 ) = tpd_OENeg_DQ0;
if (FROMOE)
( OENeg => DQ3 ) = tpd_OENeg_DQ0;
if (FROMOE)
( OENeg => DQ4 ) = tpd_OENeg_DQ0;
if (FROMOE)
( OENeg => DQ5 ) = tpd_OENeg_DQ0;
if (FROMOE)
( OENeg => DQ6 ) = tpd_OENeg_DQ0;
if (FROMOE)
( OENeg => DQ7 ) = tpd_OENeg_DQ0;
if (FROMADDR)
( A0 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A0 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A0 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A0 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A0 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A0 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A0 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A0 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A1 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A1 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A1 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A1 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A1 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A1 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A1 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A1 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A2 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A2 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A2 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A2 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A2 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A2 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A2 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A2 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A3 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A3 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A3 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A3 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A3 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A3 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A3 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A3 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A4 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A4 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A4 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A4 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A4 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A4 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A4 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A4 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A5 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A5 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A5 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A5 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A5 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A5 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A5 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A5 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A6 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A6 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A6 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A6 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A6 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A6 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A6 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A6 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A7 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A7 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A7 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A7 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A7 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A7 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A7 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A7 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A8 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A8 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A8 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A8 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A8 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A8 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A8 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A8 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A9 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A9 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A9 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A9 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A9 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A9 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A9 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A9 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A10 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A10 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A10 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A10 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A10 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A10 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A10 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A10 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A11 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A11 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A11 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A11 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A11 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A11 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A11 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A11 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A12 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A12 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A12 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A12 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A12 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A12 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A12 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A12 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A13 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A13 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A13 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A13 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A13 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A13 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A13 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A13 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A14 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A14 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A14 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A14 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A14 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A14 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A14 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A14 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A15 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A15 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A15 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A15 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A15 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A15 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A15 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A15 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A16 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A16 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A16 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A16 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A16 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A16 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A16 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A16 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A17 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A17 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A17 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A17 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A17 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A17 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A17 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A17 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A18 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A18 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A18 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A18 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A18 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A18 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A18 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A18 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A19 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A19 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A19 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A19 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A19 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A19 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A19 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A19 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A20 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A20 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A20 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A20 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A20 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A20 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A20 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A20 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A21 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A21 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A21 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A21 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A21 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A21 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A21 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A21 => DQ7 ) = tpd_A0_DQ0;
if (~RESETNeg)
( RESETNeg => DQ0 ) = tpd_RESETNeg_DQ0;
if (~RESETNeg)
( RESETNeg => DQ1 ) = tpd_RESETNeg_DQ0;
if (~RESETNeg)
( RESETNeg => DQ2 ) = tpd_RESETNeg_DQ0;
if (~RESETNeg)
( RESETNeg => DQ3 ) = tpd_RESETNeg_DQ0;
if (~RESETNeg)
( RESETNeg => DQ4 ) = tpd_RESETNeg_DQ0;
if (~RESETNeg)
( RESETNeg => DQ5 ) = tpd_RESETNeg_DQ0;
if (~RESETNeg)
( RESETNeg => DQ6 ) = tpd_RESETNeg_DQ0;
if (~RESETNeg)
( RESETNeg => DQ7 ) = tpd_RESETNeg_DQ0;
//for RY signal
(WENeg => RY) = tpd_WENeg_RY;
(CENeg => RY) = tpd_CENeg_RY;
////////////////////////////////////////////////////////////////////////////////
// Timing Violation //
////////////////////////////////////////////////////////////////////////////////
$setup ( A0 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A1 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A2 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A3 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A4 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A5 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A6 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A7 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A8 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A9 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A10, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A11, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A12, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A13, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A14, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A15, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A16, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A17, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A18, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A19, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A20, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A21, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A0 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A1 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A2 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A3 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A4 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A5 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A6 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A7 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A8 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A9 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A10, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A11, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A12, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A13, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A14, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A15, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A16, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A17, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A18, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A19, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A20, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A21, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( DQ0, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ1, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ2, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ3, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ4, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ5, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ6, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ7, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ0, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ1, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ2, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ3, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ4, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ5, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ6, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ7, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
$hold ( posedge RESETNeg&&&(CENeg===1), CENeg, thold_CENeg_RESETNeg, Viol);
$hold ( posedge RESETNeg&&&(OENeg===1), OENeg, thold_CENeg_RESETNeg, Viol);
$hold ( posedge RESETNeg&&&(WENeg===1), WENeg, thold_CENeg_RESETNeg, Viol);
$hold ( posedge OENeg, WENeg, thold_WENeg_OENeg, Viol);
$hold ( posedge WENeg, OENeg, thold_OENeg_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A0 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A1 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A2 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A3 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A4 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A5 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A6 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A7 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A9 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A10 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A11 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A12 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A13 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A14 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A15 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A16 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A17 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A18 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A19 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A20 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A21 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A0 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A1 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A2 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A3 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A4 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A5 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A6 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A7 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A8 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A9 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A10 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A11 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A12 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A13 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A14 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A15 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A16 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A17 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A18 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A19 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A20 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A21 , thold_A0_WENeg, Viol);
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ0, thold_DQ0_CENeg, Viol);
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ1, thold_DQ0_CENeg, Viol);
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ2, thold_DQ0_CENeg, Viol);
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ3, thold_DQ0_CENeg, Viol);
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ4, thold_DQ0_CENeg, Viol);
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ5, thold_DQ0_CENeg, Viol);
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ6, thold_DQ0_CENeg, Viol);
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ7, thold_DQ0_CENeg, Viol);
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ0, thold_DQ0_CENeg, Viol);
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ1, thold_DQ0_CENeg, Viol);
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ2, thold_DQ0_CENeg, Viol);
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ3, thold_DQ0_CENeg, Viol);
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ4, thold_DQ0_CENeg, Viol);
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ5, thold_DQ0_CENeg, Viol);
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ6, thold_DQ0_CENeg, Viol);
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ7, thold_DQ0_CENeg, Viol);
$width (negedge RESETNeg, tpw_RESETNeg_negedge);
$width (posedge WENeg, tpw_WENeg_posedge);
$width (negedge WENeg, tpw_WENeg_negedge);
$width (posedge CENeg, tpw_CENeg_posedge);
$width (negedge CENeg, tpw_CENeg_negedge);
$width (negedge A0, tpw_A0_negedge);//ok
$width (negedge A1, tpw_A0_negedge);//ok
$width (negedge A2, tpw_A0_negedge);//ok
$width (negedge A3, tpw_A0_negedge);//ok
$width (negedge A4, tpw_A0_negedge);//ok
$width (negedge A5, tpw_A0_negedge);//ok
$width (negedge A6, tpw_A0_negedge);//ok
$width (negedge A7, tpw_A0_negedge);//ok
$width (negedge A8, tpw_A0_negedge);//ok
$width (negedge A9, tpw_A0_negedge);//ok
$width (negedge A10, tpw_A0_negedge);//ok
$width (negedge A11, tpw_A0_negedge);//ok
$width (negedge A12, tpw_A0_negedge);//ok
$width (negedge A13, tpw_A0_negedge);//ok
$width (negedge A14, tpw_A0_negedge);//ok
$width (negedge A15, tpw_A0_negedge);//ok
$width (negedge A16, tpw_A0_negedge);//ok
$width (negedge A17, tpw_A0_negedge);//ok
$width (negedge A18, tpw_A0_negedge);//ok
$width (negedge A19, tpw_A0_negedge);//ok
$width (negedge A20, tpw_A0_negedge);//ok
$width (negedge A21, tpw_A0_negedge);//ok
$width (posedge A0, tpw_A0_posedge);//ok
$width (posedge A1, tpw_A0_posedge);//ok
$width (posedge A2, tpw_A0_posedge);//ok
$width (posedge A3, tpw_A0_posedge);//ok
$width (posedge A4, tpw_A0_posedge);//ok
$width (posedge A5, tpw_A0_posedge);//ok
$width (posedge A6, tpw_A0_posedge);//ok
$width (posedge A7, tpw_A0_posedge);//ok
$width (posedge A8, tpw_A0_posedge);//ok
$width (posedge A9, tpw_A0_posedge);//ok
$width (posedge A10, tpw_A0_posedge);//ok
$width (posedge A11, tpw_A0_posedge);//ok
$width (posedge A12, tpw_A0_posedge);//ok
$width (posedge A13, tpw_A0_posedge);//ok
$width (posedge A14, tpw_A0_posedge);//ok
$width (posedge A15, tpw_A0_posedge);//ok
$width (posedge A16, tpw_A0_posedge);//ok
$width (posedge A17, tpw_A0_posedge);//ok
$width (posedge A18, tpw_A0_posedge);//ok
$width (posedge A19, tpw_A0_posedge);//ok
$width (posedge A20, tpw_A0_posedge);//ok
$width (posedge A21, tpw_A0_posedge);//ok
endspecify
////////////////////////////////////////////////////////////////////////////////
// Main Behavior Block //
////////////////////////////////////////////////////////////////////////////////
// FSM states
parameter RESET =6\'d0;
parameter Z001 =6\'d1;
parameter PREL_SETBWB =6\'d2;
parameter PREL_ULBYPASS =6\'d3;
parameter PREL_ULBYPASS_RESET =6\'d4;
parameter AS =6\'d5;
parameter A0SEEN =6\'d6;
parameter OTP =6\'d7;
parameter OTP_Z001 =6\'d8;
parameter OTP_PREL =6\'d9;
parameter OTP_AS =6\'d10;
parameter OTP_AS_CFI =6\'d11;
parameter OTP_A0SEEN =6\'d12;
parameter C8 =6\'d13;
parameter C8_Z001 =6\'d14;
parameter C8_PREL =6\'d15;
parameter ERS =6\'d16;
parameter SERS =6\'d17;
parameter ESPS =6\'d18;
parameter SERS_EXEC =6\'d19;
parameter ESP =6\'d20;
parameter ESP_Z001 =6\'d21;
parameter ESP_PREL =6\'d22;
parameter ESP_A0SEEN =6\'d23;
parameter ESP_AS =6\'d24;
parameter PGMS =6\'d25;
parameter CFI =6\'d26;
parameter AS_CFI =6\'d27;
parameter ESP_CFI =6\'d28;
parameter ESP_AS_CFI =6\'d29;
reg [5:0] current_state;
reg [5:0] next_state;
reg deq;
always @(DIn, DOut)
begin
if (DIn==DOut)
deq=1\'b1;
else
deq=1\'b0;
end
// check when data is generated from model to avoid setuphold check in
// those occasion
assign deg =deq;
// initialize memory and load preoload files if any
initial
begin : NBlck
integer i,j;
integer tmp1,tmp2,tmp3;
integer secure_silicon[0:SecSiSize];
reg sector_prot[0:SecNum];
for (i=0;i<=((SecNum+1)*(SecSize+1)-1);i=i+1)
begin
Mem[i]=MaxData;
end
for (i=0;i<=SecSiSize;i=i+1)
begin
secure_silicon[i]=MaxData;
end
for (i=0;i<=SecNum;i=i+1)
begin
sector_prot[i]=0;
end
if (UserPreload && !(prot_file_name == "none"))
begin
//s29al032d_00_prot sector protect file
// // - comment
// @aa - <aa> stands for sector address
// (aa is incremented at every load)
// b - <b> is 1 for protected sector <aa>, 0 for unprotect.
$readmemb(prot_file_name,sector_prot);
end
if (UserPreload && !(mem_file_name == "none"))
begin
//s29al032d_00_memory preload file
// @aaaaaa - <aaaaaa> stands for address within last defined sector
// dd - <dd> is byte to be written at Mem(nn)(aaaaaa++)
// (aaaaaa is incremented at every load)
$readmemh(mem_file_name,Mem);
end
if (UserPreload && !(secsi_file_name == "none"))
begin
//s29al032d_00_secsi memory preload file
// @aaaa - <aaaa> stands for address within last defined sector
// dd - <dd> is byte to be written at Mem(nn)(aaaa++)
// (aaaa is incremented at every load)
$readmemh(secsi_file_name,secure_silicon);
end
for (i=0;i<=SecSiSize;i=i+1)
begin
SecSi[i] = secure_silicon[i];
end
for (i=0;i<=SecNum;i=i+1)
Ers_queue[i] = 0;
// every 4-group sectors protect bit must equel
for (i=0;i<=SecNum;i=i+1)
Sec_Prot[i] = sector_prot[i];
if ((Sec_Prot[3:0] != 4\'h0 && Sec_Prot[3:0] != 4\'hF)
|| (Sec_Prot[7:4] != 4\'h0 && Sec_Prot[7:4] != 4\'hF)
|| (Sec_Prot[11:8] != 4\'h0 && Sec_Prot[11:8] != 4\'hF)
|| (Sec_Prot[15:12] != 4\'h0 && Sec_Prot[15:12] != 4\'hF)
|| (Sec_Prot[19:16] != 4\'h0 && Sec_Prot[19:16] != 4\'hF)
|| (Sec_Prot[23:20] != 4\'h0 && Sec_Prot[23:20] != 4\'hF)
|| (Sec_Prot[27:24] != 4\'h0 && Sec_Prot[27:24] != 4\'hF)
|| (Sec_Prot[31:28] != 4\'h0 && Sec_Prot[31:28] != 4\'hF)
|| (Sec_Prot[35:32] != 4\'h0 && Sec_Prot[35:32] != 4\'hF)
|| (Sec_Prot[39:36] != 4\'h0 && Sec_Prot[39:36] != 4\'hF)
|| (Sec_Prot[43:40] != 4\'h0 && Sec_Prot[43:40] != 4\'hF)
|| (Sec_Prot[47:44] != 4\'h0 && Sec_Prot[47:44] != 4\'hF)
|| (Sec_Prot[51:48] != 4\'h0 && Sec_Prot[51:48] != 4\'hF)
|| (Sec_Prot[55:52] != 4\'h0 && Sec_Prot[55:52] != 4\'hF)
|| (Sec_Prot[59:56] != 4\'h0 && Sec_Prot[59:56] != 4\'hF)
|| (Sec_Prot[63:60] != 4\'h0 && Sec_Prot[63:60] != 4\'hF))
$display("Bad sector protect group preload");
WBData = -1;
end
//Power Up time 100 ns;
initial
begin
PoweredUp = 1\'b0;
#100 PoweredUp = 1\'b1;
end
always @(RESETNeg)
begin
RST <= #499 RESETNeg;
end
initial
begin
write = 1\'b0;
read = 1\'b0;
Addr = 0;
ULBYPASS = 1\'b0;
ESP_ACT = 1\'b0;
OTP_ACT = 1\'b0;
PDONE = 1\'b1;
PSTART = 1\'b0;
PERR = 1\'b0;
EDONE = 1\'b1;
ESTART = 1\'b0;
ESUSP = 1\'b0;
ERES = 1\'b0;
EERR = 1\'b0;
READY_in = 1\'b0;
READY = 1\'b0;
end
always @(posedge START_T1_in)
begin:TESTARTT1r
#tdevice_START_T1 START_T1 = START_T1_in;
end
always @(negedge START_T1_in)
begin:TESTARTT1f
#1 START_T1 = START_T1_in;
end
always @(posedge CTMOUT_in)
begin:TCTMOUTr
#tdevice_CTMOUT CTMOUT = CTMOUT_in;
end
always @(negedge CTMOUT_in)
begin:TCTMOUTf
#1 CTMOUT = CTMOUT_in;
end
always @(posedge READY_in)
begin:TREADYr
#tdevice_READY READY = READY_in;
end
always @(negedge READY_in)
begin:TREADYf
#1 READY = READY_in;
end
////////////////////////////////////////////////////////////////////////////
//// obtain \'LAST_EVENT information
////////////////////////////////////////////////////////////////////////////
always @(negedge OENeg)
begin
OENeg_event = $time;
end
always @(negedge CENeg)
begin
CENeg_event = $time;
end
always @(posedge OENeg)
begin
OENeg_posEvent = $time;
end
always @(posedge CENeg)
begin
CENeg_posEvent = $time;
end
always @(A)
begin
ADDR_event = $time;
end
////////////////////////////////////////////////////////////////////////////
//// sequential process for reset control and FSM state transition
////////////////////////////////////////////////////////////////////////////
always @(negedge RST)
begin
ESP_ACT = 1\'b0;
ULBYPASS = 1\'b0;
OTP_ACT = 1\'b0;
end
reg R;
reg E;
always @(RESETNeg)
begin
if (PoweredUp)
begin
//Hardware reset timing control
if (~RESETNeg)
begin
E = 1\'b0;
if (~PDONE || ~EDONE)
begin
//if program or erase in progress
READY_in = 1\'b1;
R = 1\'b1;
end
else
begin
READY_in = 1\'b0;
R = 1\'b0; //prog or erase not in progress
end
end
else if (RESETNeg && RST)
begin
//RESET# pulse < tRP
READY_in = 1\'b0;
R = 1\'b0;
E = 1\'b1;
end
end
end
always @(next_state or RESETNeg or CENeg or RST or
READY or PoweredUp)
begin: StateTransition
if (PoweredUp)
begin
if (RESETNeg && (~R || (R && READY)))
begin
current_state = next_state;
READY_in = 1\'b0;
E = 1\'b0;
R = 1\'b0;
reseted = 1\'b1;
end
else if ((~R && ~RESETNeg && ~RST) ||
(R && ~RESETNeg && ~RST && ~READY) ||
(R && RESETNeg && ~RST && ~READY))
begin
//no state transition while RESET# low
current_state = RESET; //reset start
reseted = 1\'b0;
end
end
else
begin
current_state = RESET; // reset
reseted = 1\'b0;
E = 1\'b0;
R = 1\'b0;
end
end
// /////////////////////////////////////////////////////////////////////////
// //Glitch Protection: Inertial Delay does not propagate pulses <5ns
// /////////////////////////////////////////////////////////////////////////
assign #5 gWE_n = WENeg_ipd;
assign #5 gCE_n = CENeg_ipd;
assign #5 gOE_n = OENeg_ipd;
///////////////////////////////////////////////////////////////////////////
//Process that reports warning when changes on signals WE#, CE#, OE# are
//discarded
///////////////////////////////////////////////////////////////////////////
always @(WENeg)
begin: PulseWatch1
if (gWE_n == WENeg)
$display("Glitch on WE#");
end
always @(CENeg)
begin: PulseWatch2
if (gCE_n == CENeg)
$display("Glitch on CE#");
end
always @(OENeg)
begin: PulseWatch3
if (gOE_n == OENeg)
$display("Glitch on OE#");
end
//latch address on rising edge and data on falling edge of write
always @(gWE_n or gCE_n or gOE_n )
begin: write_dc
if (RESETNeg!=1\'b0)
begin
if (~gWE_n && ~gCE_n && gOE_n)
write = 1\'b1;
else
write = 1\'b0;
end
if (gWE_n && ~gCE_n && ~gOE_n)
read = 1\'b1;
else
read = 1\'b0;
end
///////////////////////////////////////////////////////////////////////////
////Latch address on falling edge of WE# or CE# what ever comes later
////Latch data on rising edge of WE# or CE# what ever comes first
//// also Write cycle decode
////////////////////////////////////////////////////////////////////////////
integer A_tmp ;
integer SA_tmp ;
integer A_tmp1 ;
integer Mem_tmp;
integer AS_addr;
reg CE;
always @(WENeg_ipd)
begin
if (reseted)
begin
if (~WENeg_ipd && ~CENeg_ipd && OENeg_ipd )
begin
A_tmp = A[10:0];
SA_tmp = A[HiAddrBit:16];
A_tmp1 = A[15:0];
Mem_tmp = A;
AS_addr = A[21];
end
end
end
always @(CENeg_ipd)
begin
if (reseted)
begin
if (~CENeg_ipd && (WENeg_ipd != OENeg_ipd) )
begin
A_tmp = A[10:0];
SA_tmp = A[HiAddrBit:16];
A_tmp1 = A[15:0];
Mem_tmp = A;
AS_addr = A[21];
end
if (~CENeg_ipd && WENeg_ipd && ~OENeg_ipd)
begin
SecAddr = SA_tmp;
Address = A_tmp1;
MemAddress = Mem_tmp;
Addr = A_tmp;
end
end
end
always @(negedge OENeg_ipd )
begin
if (reseted)
begin
if (~OENeg_ipd && WENeg_ipd && ~CENeg_ipd)
begin
A_tmp = A[10:0];
SA_tmp = A[HiAddrBit:16];
A_tmp1 = A[15:0];
Mem_tmp = A;
SecAddr = SA_tmp;
Address = A_tmp1;
MemAddress = Mem_tmp;
Addr = A_tmp;
AS_addr = A[21];
end
SecAddr = SA_tmp;
Address = A_tmp1;
MemAddress = Mem_tmp;
CE = CENeg;
Addr = A_tmp;
end
end
always @(A)
begin
if (reseted)
if (WENeg_ipd && ~CENeg_ipd && ~OENeg_ipd)
begin
A_tmp = A[10:0];
SA_tmp = A[HiAddrBit:16];
A_tmp1 = A[15:0];
Mem_tmp = A;
AS_addr = A[21];
SecAddr = SA_tmp;
Address = A_tmp1;
MemAddress = Mem_tmp;
Addr = A_tmp;
CE = CENeg;
end
end
always @(posedge write)
begin
SecAddr = SA_tmp;
Address = A_tmp1;
MemAddress = Mem_tmp;
Addr = A_tmp;
CE = CENeg;
end
///////////////////////////////////////////////////////////////////////////
// Timing control for the Program Operations
///////////////////////////////////////////////////////////////////////////
integer cnt_write = 0;
//time elapsed_write ;
time duration_write ;
//time start_write ;
event pdone_event;
always @(posedge reseted)
begin
PDONE = 1\'b1;
end
always @(reseted or PSTART)
begin
if (reseted)
begin
if (PSTART && PDONE)
begin
if ((~FactoryProt && OTP_ACT)||
( ~Sec_Prot[SA] &&(~Ers_queue[SA] || ~ESP_ACT )&& ~OTP_ACT))
begin
duration_write = tdevice_POB + 5;
PDONE = 1\'b0;
->pdone_event;
end
else
begin
PERR = 1\'b1;
PERR <= #1005 1\'b0;
end
end
end
end
always @(pdone_event)
begin:pdone_process
PDONE = 1\'b0;
#duration_write PDONE = 1\'b1;
end
/////////////////////////////////////////////////////////////////////////
// Timing control for the Erase Operations
/////////////////////////////////////////////////////////////////////////
integer cnt_erase = 0;
time elapsed_erase;
time duration_erase;
time start_erase;
always @(posedge reseted)
begin
disable edone_process;
EDONE = 1\'b1;
end
event edone_event;
always @(reseted or ESTART)
begin: erase
integer i;
if (reseted)
begin
if (ESTART && EDONE)
begin
cnt_erase = 0;
for (i=0;i<=SecNum;i=i+1)
begin
if ((Ers_queue[i]==1\'b1) && (Sec_Prot[i]!=1\'b1))
cnt_erase = cnt_erase + 1;
end
if (cnt_erase>0)
begin
elapsed_erase = 0;
duration_erase = cnt_erase* tdevice_SEO + 4;
->edone_event;
start_erase = $time;
end
else
begin
EERR = 1\'b1;
EERR <= #100005 1\'b0;
end
end
end
end
always @(edone_event)
begin : edone_process
EDONE = 1\'b0;
#duration_erase EDONE = 1\'b1;
end
always @(reseted or ESUSP)
begin
if (reseted)
if (ESUSP && ~EDONE)
begin
disable edone_process;
elapsed_erase = $time - start_erase;
duration_erase = duration_erase - elapsed_erase;
EDONE = 1\'b0;
end
end
always @(reseted or ERES)
begin
if (reseted)
if (ERES && ~EDONE)
begin
start_erase = $time;
EDONE = 1\'b0;
->edone_event;
end
end
// /////////////////////////////////////////////////////////////////////////
// // Main Behavior Process
// // combinational process for next state generation
// /////////////////////////////////////////////////////////////////////////
reg PATTERN_1 = 1\'b0;
reg PATTERN_2 = 1\'b0;
reg A_PAT_1 = 1\'b0;
reg A_PAT_2 = 1\'b0;
reg A_PAT_3 = 1\'b0;
integer DataByte ;
always @(negedge write)
begin
DataByte = DIn;
PATTERN_1 = DataByte==8\'hAA ;
PATTERN_2 = DataByte==8\'h55 ;
A_PAT_1 = 1\'b1;
A_PAT_2 = Address==16\'hAAA ;
A_PAT_3 = Address==16\'h555 ;
end
always @(write or reseted)
begin: StateGen1
if (reseted!=1\'b1)
next_state 'b'= current_state;
else
if (~write)
case (current_state)
RESET :
begin
if (PATTERN_1)
next_state = Z001;
else if ((Addr==8\'h55) && (DataByte==8\'h98))
next_state = CFI;
else
next_state = RESET;
end
CFI:
begin
if (DataByte==8\'hF0)
next_state = RESET;
else
next_state = CFI;
end
Z001 :
begin
if (PATTERN_2)
next_state = PREL_SETBWB;
else
next_state = RESET;
end
PREL_SETBWB :
begin
if (A_PAT_1 && (DataByte==16\'h20))
next_state = PREL_ULBYPASS;
else if (A_PAT_1 && (DataByte==16\'h90))
next_state = AS;
else if (A_PAT_1 && (DataByte==16\'hA0))
next_state = A0SEEN;
else if (A_PAT_1 && (DataByte==16\'h80))
next_state = C8;
else if (A_PAT_1 && (DataByte==16\'h88))
next_state = OTP;
else
next_state = RESET;
end
PREL_ULBYPASS :
begin
if (DataByte == 16\'h90 )
next_state <= PREL_ULBYPASS_RESET;
if (A_PAT_1 && (DataByte == 16\'hA0))
next_state = A0SEEN;
else
next_state = PREL_ULBYPASS;
end
PREL_ULBYPASS_RESET :
begin
if (DataByte == 16\'h00 )
if (ESP_ACT)
next_state = ESP;
else
next_state = RESET;
else
next_state <= PREL_ULBYPASS;
end
AS :
begin
if (DataByte==16\'hF0)
next_state = RESET;
else if ((Addr==8\'h55) && (DataByte==8\'h98))
next_state = AS_CFI;
else
next_state = AS;
end
AS_CFI:
begin
if (DataByte==8\'hF0)
next_state = AS;
else
next_state = AS_CFI;
end
A0SEEN :
begin
next_state = PGMS;
end
OTP :
begin
if (PATTERN_1)
next_state = OTP_Z001;
else
next_state = OTP;
end
OTP_Z001 :
begin
if (PATTERN_2)
next_state = OTP_PREL;
else
next_state = OTP;
end
OTP_PREL :
begin
if (A_PAT_1 && (DataByte == 16\'h90))
next_state = OTP_AS;
else if (A_PAT_1 && (DataByte == 16\'hA0))
next_state = OTP_A0SEEN;
else
next_state = OTP;
end
OTP_AS:
begin
if (DataByte == 16\'h00)
if (ESP_ACT)
next_state = ESP;
else
next_state = RESET;
else if (DataByte == 16\'hF0)
next_state = OTP;
else if (DataByte == 16\'h98)
next_state = OTP_AS_CFI;
else
next_state = OTP_AS;
end
OTP_AS_CFI:
begin
if (DataByte == 16\'hF0)
next_state = OTP_AS;
else
next_state = OTP_AS_CFI;
end
OTP_A0SEEN :
begin
if ((SecAddr == 16\'h3F) && (Address <= 16\'hFFFF) &&
(Address >= 16\'hFF00))
next_state = PGMS;
else
next_state = OTP;
end
C8 :
begin
if (PATTERN_1)
next_state = C8_Z001;
else
next_state = RESET;
end
C8_Z001 :
begin
if (PATTERN_2)
next_state = C8_PREL;
else
next_state = RESET;
end
C8_PREL :
begin
if (A_PAT_1 && (DataByte==16\'h10))
next_state = ERS;
else if (DataByte==16\'h30)
next_state = SERS;
else
next_state = RESET;
end
ERS :
begin
end
SERS :
begin
if (~CTMOUT && DataByte == 16\'hB0)
next_state = ESP; // ESP according to datasheet
else if (DataByte==16\'h30)
next_state = SERS;
else
next_state = RESET;
end
SERS_EXEC :
begin
end
ESP :
begin
if (DataByte == 16\'h30)
next_state = SERS_EXEC;
else
begin
if (PATTERN_1)
next_state = ESP_Z001;
if (Addr == 8\'h55 && DataByte == 8\'h98)
next_state = ESP_CFI;
end
end
ESP_CFI:
begin
if (DataByte == 8\'hF0)
next_state = ESP;
else
next_state = ESP_CFI;
end
ESP_Z001 :
begin
if (PATTERN_2)
next_state = ESP_PREL;
else
next_state = ESP;
end
ESP_PREL :
begin
if (A_PAT_1 && DataByte == 16\'hA0)
next_state = ESP_A0SEEN;
else if (A_PAT_1 && DataByte == 16\'h20)
next_state <= PREL_ULBYPASS;
else if (A_PAT_1 && DataByte == 16\'h88)
next_state <= OTP;
else if (A_PAT_1 && DataByte == 16\'h90)
next_state = ESP_AS;
else
next_state = ESP;
end
ESP_A0SEEN :
begin
next_state = PGMS; //set ESP
end
ESP_AS :
begin
if (DataByte == 16\'hF0)
next_state = ESP;
else if ((Addr==8\'h55) && (DataByte==8\'h98))
next_state = ESP_AS_CFI;
end
ESP_AS_CFI:
begin
if (DataByte == 8\'hF0)
next_state = ESP_AS;
else
next_state = ESP_AS_CFI;
end
endcase
end
always @(posedge PDONE or negedge PERR)
begin: StateGen6
if (reseted!=1\'b1)
next_state = current_state;
else
begin
if (current_state==PGMS && ULBYPASS)
next_state = PREL_ULBYPASS;
else if (current_state==PGMS && OTP_ACT)
next_state = OTP;
else if (current_state==PGMS && ESP_ACT)
next_state = ESP;
else if (current_state==PGMS)
next_state = RESET;
end
end
always @(posedge EDONE or negedge EERR)
begin: StateGen2
if (reseted!=1\'b1)
next_state = current_state;
else
begin
if ((current_state==ERS) || (current_state==SERS_EXEC))
next_state = RESET;
end
end
always @(negedge write or reseted)
begin: StateGen7 //ok
integer i,j;
if (reseted!=1\'b1)
next_state = current_state;
else
begin
if (current_state==SERS_EXEC && (write==1\'b0) && (EERR!=1\'b1))
if (DataByte==16\'hB0)
begin
next_state = ESPS;
ESUSP = 1\'b1;
ESUSP <= #1 1\'b0;
end
end
end
always @(CTMOUT or reseted)
begin: StateGen4
if (reseted!=1\'b1)
next_state = current_state;
else
begin
if (current_state==SERS && CTMOUT) next_state = SERS_EXEC;
end
end
always @(posedge START_T1 or reseted)
begin: StateGen5
if (reseted!=1\'b1)
next_state = current_state;
else
if (current_state==ESPS && START_T1) next_state = ESP;
end
///////////////////////////////////////////////////////////////////////////
//FSM Output generation and general funcionality
///////////////////////////////////////////////////////////////////////////
always @(posedge read)
begin
->oe_event;
end
always @(MemAddress)
begin
if (read)
->oe_event;
end
always @(oe_event)
begin
oe = 1\'b1;
#1 oe = 1\'b0;
end
always @(DOut_zd)
begin : OutputGen
if (DOut_zd[0] !== 1\'bz)
begin
CEDQ_t = CENeg_event + CEDQ_01;
OEDQ_t = OENeg_event + OEDQ_01;
ADDRDQ_t = ADDR_event + ADDRDQ_01;
FROMCE = ((CEDQ_t >= OEDQ_t) && ( CEDQ_t >= $time));
FROMOE = ((OEDQ_t >= CEDQ_t) && ( OEDQ_t >= $time));
FROMADDR = 1\'b1;
if ((ADDRDQ_t > $time )&&
(((ADDRDQ_t>OEDQ_t)&&FROMOE) ||
((ADDRDQ_t>CEDQ_t)&&FROMCE)))
begin
TempData = DOut_zd;
FROMADDR = 1\'b0;
DOut_Pass = 8\'bx;
#(ADDRDQ_t - $time) DOut_Pass = TempData;
end
else
begin
DOut_Pass = DOut_zd;
end
end
end
always @(DOut_zd)
begin
if (DOut_zd[0] === 1\'bz)
begin
disable OutputGen;
FROMCE = 1\'b1;
FROMOE = 1\'b1;
if ((CENeg_posEvent <= OENeg_posEvent) &&
( CENeg_posEvent + 5 >= $time))
FROMOE = 1\'b0;
if ((OENeg_posEvent < CENeg_posEvent) &&
( OENeg_posEvent + 5 >= $time))
FROMCE = 1\'b0;
FROMADDR = 1\'b0;
DOut_Pass = DOut_zd;
end
end
always @(oe or reseted or current_state)
begin
if (reseted)
begin
case (current_state)
RESET :
begin
if (oe)
MemRead(DOut_zd);
end
AS, ESP_AS, OTP_AS :
begin
if (oe)
begin
if (AS_addr == 1\'b0)
begin
end
else
AS_ID = 1\'b0;
if ((Address[7:0] == 0) && (AS_ID == 1\'b1))
DOut_zd = 1;
else if ((Address[7:0] == 1) && (AS_ID == 1\'b1))
DOut_zd = 8\'hA3;
else if ((Address[7:0] == 2) &&
(((SecAddr < 32 ) && (AS_ID == 1\'b1))
|| ((SecAddr > 31 ) && (AS_ID2 == 1\'b1))))
begin
DOut_zd = 8\'b00000000;
DOut_zd[0] = Sec_Prot[SecAddr];
end
else if ((Address[7:0] == 6) && (AS_SecSi_FP == 1\'b1))
begin
DOut_zd = 8\'b0;
if (FactoryProt)
DOut_zd = 16\'h99;
else
DOut_zd = 16\'h19;
end
else
DOut_zd = 8\'bz;
end
end
OTP :
begin
if (oe)
begin
if ((SecAddr == 16\'h3F) && (Address <= 16\'hFFFF) &&
(Address >= 16\'hFF00))
begin
SecSiAddr = Address%(SecSiSize +1);
if (SecSi[SecSiAddr]==-1)
DOut_zd = 8\'bx;
else
DOut_zd = SecSi[SecSiAddr];
end
else
$display ("Invalid SecSi query address");
end
end
CFI, AS_CFI, ESP_CFI, ESP_AS_CFI, OTP_AS_CFI :
begin
if (oe)
begin
DOut_zd = 8\'bZ;
if (((MemAddress>=16\'h10) && (MemAddress <= 16\'h3C)) ||
((MemAddress>=16\'h40) && (MemAddress <= 16\'h4F)))
begin
DOut_zd = CFI_array[MemAddress];
end
else
begin
$display ("Invalid CFI query address");
end
end
end
ERS :
begin
if (oe)
begin
///////////////////////////////////////////////////////////
// read status / embeded erase algorithm - Chip Erase
///////////////////////////////////////////////////////////
Status[7] = 1\'b0;
Status[6] = ~Status[6]; //toggle
Status[5] = 1\'b0;
Status[3] = 1\'b1;
Status[2] = ~Status[2]; //toggle
DOut_zd = Status;
end
end
SERS :
begin
if (oe)
begin
///////////////////////////////////////////////////////////
//read status - sector erase timeout
///////////////////////////////////////////////////////////
Status[3] = 1\'b0;
Status[7] = 1\'b1;
DOut_zd = Status;
end
end
ESPS :
begin
if (oe)
begin
///////////////////////////////////////////////////////////
//read status / erase suspend timeout - stil erasing
///////////////////////////////////////////////////////////
if (Ers_queue[SecAddr]==1\'b1)
begin
Status[7] = 1\'b0;
Status[2] = ~Status[2]; //toggle
end
else
Status[7] = 1\'b1;
Status[6] = ~Status[6]; //toggle
Status[5] = 1\'b0;
Status[3] = 1\'b1;
DOut_zd = Status;
end
end
SERS_EXEC:
begin
if (oe)
begin
///////////////////////////////////////////////////
//read status erase
///////////////////////////////////////////////////
if (Ers_queue[SecAddr]==1\'b1)
begin
Status[7] = 1\'b0;
Status[2] = ~Status[2]; //toggle
end
else
Status[7] = 1\'b1;
Status[6] = ~Status[6]; //toggle
Status[5] = 1\'b0;
Status[3] = 1\'b1;
DOut_zd = Status;
end
end
ESP :
begin
if (oe)
begin
///////////////////////////////////////////////////////////
//read
///////////////////////////////////////////////////////////
if (Ers_queue[SecAddr]!=1\'b1)
begin
MemRead(DOut_zd);
end
else
begin
///////////////////////////////////////////////////////
//read status
///////////////////////////////////////////////////////
Status[7] = 1\'b1;
// Status[6) No toggle
Status[5] = 1\'b0;
Status[2] = ~Status[2]; //toggle
DOut_zd = Status;
end
end
end
PGMS :
begin
if (oe)
begin
///////////////////////////////////////////////////////////
//read status
///////////////////////////////////////////////////////////
Status[6] = ~Status[6]; //toggle
Status[5] = 1\'b0;
//Status[2) no toggle
Status[1] = 1\'b0;
DOut_zd = Status;
if (SecAddr == SA)
DOut_zd[7] = Status[7];
else
DOut_zd[7] = ~Status[7];
end
end
endcase
end
end
always @(write or reseted)
begin : Output_generation
if (reseted)
begin
case (current_state)
RESET :
begin
ESP_ACT = 1\'b0;
ULBYPASS = 1\'b0;
OTP_ACT = 1\'b0;
if (~write)
if (A_PAT_2 && PATTERN_1)
AS_SecSi_FP = 1\'b1;
else
AS_SecSi_FP = 1\'b0;
end
Z001 :
begin
if (~write)
if (A_PAT_3 && PATTERN_2)
begin
end
else
AS_SecSi_FP = 1\'b0;
end
PREL_SETBWB :
begin
if (~write)
begin
if (A_PAT_1 && (DataByte==16\'h20))
ULBYPASS = 1\'b1;
else if (A_PAT_1 && (DataByte==16\'h90))
begin
ULBYPASS = 1\'b0;
if (A_PAT_2)
begin
end
else
AS_SecSi_FP = 1\'b0;
if (AS_addr == 1\'b0)
begin
AS_ID = 1\'b1;
AS_ID2= 1\'b0;
end
else
begin
AS_ID = 1\'b0;
AS_ID2= 1\'b1;
end
end
else if (A_PAT_1 && (DataByte==16\'h88))
begin
OTP_ACT = 1;
ULBYPASS = 1\'b0;
end
end
end
PREL_ULBYPASS :
begin
if (~write)
begin
ULBYPASS = 1\'b1;
if (A_PAT_1 && (DataByte==16\'h90))
ULBYPASS = 1\'b0;
end
end
PREL_ULBYPASS_RESET :
if ((~write) && (DataByte != 16\'h00 ))
ULBYPASS = 1\'b1;
OTP_A0SEEN :
begin
if (~write)
begin
if ((SecAddr == 16\'h3F) && (Address <= 16\'hFFFF) &&
(Address >= 16\'hFF00))
begin
SecSiAddr = Address%(SecSiSize +1);
OTP_ACT = 1;
PSTART = 1\'b1;
PSTART <= #1 1\'b0;
WBAddr = SecSiAddr;
SA = SecAddr;
temp = DataByte;
Status[7] = ~temp[7];
WBData = DataByte;
end
else
$display ("Invalid program address in SecSi region:"
,Address);
end
end
OTP_PREL :
begin
if (~write)
if (A_PAT_1 && (DataByte==16\'h90))
begin
ULBYPASS = 1\'b0;
if (A_PAT_2)
begin
end
else
AS_SecSi_FP = 1\'b0;
if (AS_addr == 1\'b0)
begin
AS_ID = 1\'b1;
AS_ID2= 1\'b0;
end
else
begin
AS_ID = 1\'b0;
AS_ID2= 1\'b1;
end
end
end
OTP_Z001 :
begin
if (~write)
if (A_PAT_3 && PATTERN_2)
begin
end
else
AS_SecSi_FP = 1\'b0;
end
OTP :
begin
if (~write)
if (A_PAT_2 && PATTERN_1)
AS_SecSi_FP = 1\'b1;
else
AS_SecSi_FP = 1\'b0;
RY_zd = 1;
end
AS :
begin
if (~write)
if (DataByte==16\'hF0)
begin
AS_SecSi_FP = 1\'b0;
AS_ID = 1\'b0;
AS_ID2 = 1\'b0;
end
end
A0SEEN :
begin
if (~write)
begin
PSTART = 1\'b1;
PSTART <= #1 1\'b0;
WBData = DataByte;
WBAddr = Address;
SA = SecAddr;
Status[7] = ~DataByte[7];
end
end
C8 :
begin
end
C8_Z001 :
begin
end
C8_PREL :
begin
if (~write)
if (A_PAT_1 && (DataByte==16\'h10))
begin
//Start Chip Erase
ESTART = 1\'b1;
ESTART <= #1 1\'b0;
ESUSP = 1\'b0;
ERES = 1\'b0;
Ers_queue = ~(0);
Status = 8\'b00001000;
end
else if (DataByte==16\'h30)
begin
//put selected sector to sec. ers. queue
//start timeout
Ers_queue = 0;
Ers_queue[SecAddr] = 1\'b1;
disable TCTMOUTr;
CTMOUT_in = 1\'b0;
#1 CTMOUT_in <= 1\'b1;
end
end
ERS :
begin
end
SERS :
begin
if (~write && ~CTMOUT)
begin
if (DataByte == 16\'hB0)
begin
//need to start erase process prior to suspend
ESTART = 1\'b1;
ESTART = #1 1\'b0;
ESUSP = #1 1\'b0;
ESUSP = #1 1\'b1;
ESUSP <= #2 1\'b0;
ERES = 1\'b0;
end
else if (DataByte==16\'h30)
begin
disable TCTMOUTr;
CTMOUT_in = 1\'b0;
#1 CTMOUT_in <= 1\'b1;
Ers_queue[SecAddr] = 1\'b1;
end
end
end
SERS_EXEC :
begin
if (~write)
if (~EDONE && (EERR!=1\'b1) && DataByte==16\'hB0)
START_T1_in = 1\'b1;
end
ESP :
begin
if (~write)
begin
if (A_PAT_2 && PATTERN_1)
AS_SecSi_FP = 1\'b1;
else
AS_SecSi_FP = 1\'b0;
if (DataByte == 16\'h30)
begin
ERES = 1\'b1;
ERES <= #1 1\'b0;
end
end
end
ESP_Z001 :
begin
if (~write)
if (A_PAT_3 && PATTERN_2)
begin
end
else
AS_SecSi_FP = 1\'b0;
end
ESP_PREL :
begin
if (~write)
if (A_PAT_1 && (DataByte==16\'h90))
begin
ULBYPASS = 1\'b0;
if (A_PAT_2)
begin
end
else
AS_SecSi_FP = 1\'b0;
if (AS_addr == 1\'b0)
begin
AS_ID = 1\'b1;
AS_ID2= 1\'b0;
end
else
begin
AS_ID = 1\'b0;
AS_ID2= 1\'b1;
end
end
end
ESP_A0SEEN :
begin
if (~write)
begin
ESP_ACT = 1\'b1;
PSTART = 1\'b1;
PSTART <= #1 1\'b0;
WBData = DataByte;
WBAddr = Address;
SA = SecAddr;
Status[7] = ~DataByte[7];
end
end
ESP_AS :
begin
end
endcase
end
end
initial
begin
///////////////////////////////////////////////////////////////////////
//CFI array data
///////////////////////////////////////////////////////////////////////
//CFI query identification string
for (i=16;i<92;i=i+1)
CFI_array[i] = -1;
CFI_array[16\'h10] = 16\'h51;
CFI_array[16\'h11] = 16\'h52;
CFI_array[16\'h12] = 16\'h59;
CFI_array[16\'h13] = 16\'h02;
CFI_array[16\'h14] = 16\'h00;
CFI_array[16\'h15] = 16\'h40;
CFI_array[16\'h16] = 16\'h00;
CFI_array[16\'h17] = 16\'h00;
CFI_array[16\'h18] = 16\'h00;
CFI_array[16\'h19] = 16\'h00;
CFI_array[16\'h1A] = 16\'h00;
//system interface string
CFI_array[16\'h1B] = 16\'h27;
CFI_array[16\'h1C] = 16\'h36;
CFI_array[16\'h1D] = 16\'h00;
CFI_array[16\'h1E] = 16\'h00;
CFI_array[16\'h1F] = 16\'h04;
CFI_array[16\'h20] = 16\'h00;
CFI_array[16\'h21] = 16\'h0A;
CFI_array[16\'h22] = 16\'h00;
CFI_array[16\'h23] = 16\'h05;
CFI_array[16\'h24] = 16\'h00;
CFI_array[16\'h25] = 16\'h04;
CFI_array[16\'h26] = 16\'h00;
//device geometry definition
CFI_array[16\'h27] = 16\'h16;
CFI_array[16\'h28] = 16\'h00;
CFI_array[16\'h29] = 16\'h00;
CFI_array[16\'h2A] = 16\'h00;
CFI_array[16\'h2B] = 16\'h00;
CFI_array[16\'h2C] = 16\'h01;
CFI_array[16\'h2D] = 16\'h3F;
CFI_array[16\'h2E] = 16\'h00;
CFI_array[16\'h2F] = 16\'h00;
CFI_array[16\'h30] = 16\'h01;
CFI_array[16\'h31] = 16\'h00;
CFI_array[16\'h32] = 16\'h00;
CFI_array[16\'h33] = 16\'h00;
CFI_array[16\'h34] = 16\'h00;
CFI_array[16\'h35] = 16\'h00;
CFI_array[16\'h36] = 16\'h00;
CFI_array[16\'h37] = 16\'h00;
CFI_array[16\'h38] = 16\'h00;
CFI_array[16\'h39] = 16\'h00;
CFI_array[16\'h3A] = 16\'h00;
CFI_array[16\'h3B] = 16\'h00;
CFI_array[16\'h3C] = 16\'h00;
//primary vendor-specific extended query
CFI_array[16\'h40] = 16\'h50;
CFI_array[16\'h41] = 16\'h52;
CFI_array[16\'h42] = 16\'h49;
CFI_array[16\'h43] = 16\'h31;
CFI_array[16\'h44] = 16\'h31;
CFI_array[16\'h45] = 16\'h01;
CFI_array[16\'h46] = 16\'h02;
CFI_array[16\'h47] = 16\'h01;
CFI_array[16\'h48] = 16\'h01;
CFI_array[16\'h49] = 16\'h04;
CFI_array[16\'h4A] = 16\'h00;
CFI_array[16\'h4B] = 16\'h00;
CFI_array[16\'h4C] = 16\'h00;
CFI_array[16\'h4D] = 16\'hB5;
CFI_array[16\'h4E] = 16\'hC5;
CFI_array[16\'h4F] = 16\'h00;
end
always @(current_state or reseted)
begin
if (reseted)
if (current_state==RESET) RY_zd = 1\'b1;
if (current_state==PREL_ULBYPASS) RY_zd = 1\'b1;
if (current_state==A0SEEN) RY_zd = 1\'b1;
if (current_state==ERS) RY_zd = 1\'b0;
if (current_state==SERS) RY_zd = 1\'b0;
if (current_state==ESPS) RY_zd = 1\'b0;
if (current_state==SERS_EXEC) RY_zd = 1\'b0;
if (current_state==ESP) RY_zd = 1\'b1;
if (current_state==OTP) RY_zd = 1\'b1;
if (current_state==ESP_A0SEEN) RY_zd = 1\'b1;
if (current_state==PGMS) RY_zd = 1\'b0;
end
always @(EERR or EDONE or current_state)
begin : ERS2
integer i;
integer j;
if (current_state==ERS && EERR!=1\'b1)
for (i=0;i<=SecNum;i=i+1)
begin
if (Sec_Prot[i]!=1\'b1)
for (j=0;j<=SecSize;j=j+1)
Mem[sa(i)+j] = -1;
end
if (current_state==ERS && EDONE)
for (i=0;i<=SecNum;i=i+1)
begin
if (Sec_Prot[i]!=1\'b1)
for (j=0;j<=SecSize;j=j+1)
Mem[sa(i)+j] = MaxData;
end
end
always @(CTMOUT or current_state)
begin : SERS2
if (current_state==SERS && CTMOUT)
begin
CTMOUT_in = 1\'b0;
START_T1_in = 1\'b0;
ESTART = 1\'b1;
ESTART <= #1 1\'b0;
ESUSP = 1\'b0;
ERES = 1\'b0;
end
end
always @(START_T1 or current_state)
begin : ESPS2
if (current_state==ESPS && START_T1)
begin
ESP_ACT = 1\'b1;
START_T1_in = 1\'b0;
end
end
always @(EERR or EDONE or current_state)
begin: SERS_EXEC2
integer i,j;
if (current_state==SERS_EXEC)
begin
if (EERR!=1\'b1)
begin
for (i=0;i<=SecNum;i=i+1)
begin
if (Sec_Prot[i]!=1\'b1 && Ers_queue[i])
for (j=0;j<=SecSize;j=j+1)
Mem[sa(i)+j] = -1;
if (EDONE)
for (i=0;i<=SecNum;i=i+1)
begin
if (Sec_Prot[i]!=1\'b1 && Ers_queue[i])
for (j=0;j<=SecSize;j=j+1)
Mem[sa(i)+j] = MaxData;
end
end
end
end
end
always @(current_state or posedge PDONE)
begin: PGMS2
integer i,j;
if (current_state==PGMS)
begin
if (PERR!=1\'b1)
begin
new_int = WBData;
if (OTP_ACT!=1\'b1) //mem write
old_int=Mem[sa(SA) + WBAddr];
else
old_int=SecSi[WBAddr];
new_bit = new_int;
if (old_int>-1)
begin
old_bit = old_int;
for(j=0;j<=7;j=j+1)
if (~old_bit[j])
new_bit[j]=1\'b0;
new_int=new_bit;
end
WBData = new_int;
if (OTP_ACT!=1\'b1) //mem write
Mem[sa(SA) + WBAddr] = -1;
else
SecSi[WBAddr] = -1;
if (PDONE && ~PSTART)
begin
if (OTP_ACT!=1\'b1) //mem write
Mem[sa(SA) + WBAddr] = WBData;
else
SecSi[WBAddr] = WBData;
WBData= -1;
end
end
end
end
always @(gOE_n or gCE_n or RESETNeg or RST )
begin
//Output Disable Control
if (gOE_n || gCE_n || (~RESETNeg && ~RST))
DOut_zd = 8\'bZ;
end
reg BuffInOE , BuffInCE , BuffInADDR;
wire BuffOutOE, BuffOutCE, BuffOutADDR;
BUFFER BUFOE (BuffOutOE, BuffInOE);
BUFFER BUFCE (BuffOutCE, BuffInCE);
BUFFER BUFADDR (BuffOutADDR, BuffInADDR);
initial
begin
BuffInOE = 1\'b1;
BuffInCE = 1\'b1;
BuffInADDR = 1\'b1;
end
always @(posedge BuffOutOE)
begin
OEDQ_01 = $time;
end
always @(posedge BuffOutCE)
begin
CEDQ_01 = $time;
end
always @(posedge BuffOutADDR)
begin
ADDRDQ_01 = $time;
end
function integer sa;
input [7:0] sect;
begin
sa = sect * (SecSize + 1);
end
endfunction
task MemRead;
inout[7:0] DOut_zd;
begin
if (Mem[sa(SecAddr)+Address]==-1)
DOut_zd = 8\'bx;
else
DOut_zd = Mem[sa(SecAddr)+Address];
end
endtask
endmodule
module BUFFER (OUT,IN);
input IN;
output OUT;
buf ( OUT, IN);
endmodule
|
/*
* Palette register file for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga_palette_regs (
input clk,
// VGA read interface
input [3:0] attr,
output reg [7:0] index,
// CPU interface
input [3:0] address,
input write,
output reg [7:0] read_data,
input [7:0] write_data
);
// Registers
reg [7:0] palette [0:15];
// Behaviour
// VGA read interface
always @(posedge clk) index <= palette[attr];
// CPU read interface
always @(posedge clk) read_data <= palette[address];
// CPU write interface
always @(posedge clk)
if (write) palette[address] <= write_data;
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
`define ENABLE_VCD
module tb_fmlbrg();
reg clk;
initial clk = 1\'b0;
always #5 clk = ~clk;
reg rst;
reg [19:1] wb_adr_i;
reg [2:0] wb_cti_i;
reg [15:0] wb_dat_i;
wire [15:0] wb_dat_o;
reg [1:0] wb_sel_i;
reg wb_cyc_i;
reg wb_stb_i;
reg wb_we_i;
wire wb_ack_o;
wire [19:0] fml_adr;
wire fml_stb;
wire fml_we;
reg fml_ack;
wire [1:0] fml_sel;
wire [15:0] fml_dw;
reg [15:0] fml_dr;
reg dcb_stb;
reg [19:0] dcb_adr;
wire [15:0] dcb_dat;
wire dcb_hit;
/* Process FML requests */
reg [2:0] fml_wcount;
reg [2:0] fml_rcount;
initial begin
\tfml_ack = 1\'b0;
\tfml_wcount = 0;
\tfml_rcount = 0;
end
always @(posedge clk) begin
\tif(fml_stb & (fml_wcount == 0) & (fml_rcount == 0)) begin
\t\tfml_ack <= 1\'b1;
\t\tif(fml_we) begin
\t\t\t$display("%t FML W addr %x data %x", $time, fml_adr, fml_dw);
\t\t\tfml_wcount <= 7;
\t\tend else begin
\t\t\tfml_dr = 16\'hbeef;
\t\t\t$display("%t FML R addr %x data %x", $time, fml_adr, fml_dr);
\t\t\tfml_rcount <= 7;
\t\tend
\tend else
\t\tfml_ack <= 1\'b0;
\tif(fml_wcount != 0) begin
\t\t#1 $display("%t FML W continuing %x / %d", $time, fml_dw, fml_wcount);
\t\tfml_wcount <= fml_wcount - 1;
\tend
\tif(fml_rcount != 0) begin
\t\tfml_dr = #1 {13\'h1eba, fml_rcount};
\t\t$display("%t FML R continuing %x / %d", $time, fml_dr, fml_rcount);
\t\tfml_rcount <= fml_rcount - 1;
\tend
end
fmlbrg #(
.fml_depth (20), // 8086 can only address 1 MB
.cache_depth (10) // 1 Kbyte cache
) dut (
\t.sys_clk(clk),
\t.sys_rst(rst),
\t
\t.wb_adr_i(wb_adr_i),
\t.wb_cti_i(wb_cti_i),
\t.wb_dat_i(wb_dat_i),
\t.wb_dat_o(wb_dat_o),
\t.wb_sel_i(wb_sel_i),
\t.wb_cyc_i(wb_cyc_i),
\t.wb_stb_i(wb_stb_i),
\t.wb_we_i(wb_we_i),
\t.wb_ack_o(wb_ack_o),
\t
\t.fml_adr(fml_adr),
\t.fml_stb(fml_stb),
\t.fml_we(fml_we),
\t.fml_ack(fml_ack),
\t.fml_sel(fml_sel),
\t.fml_do(fml_dw),
\t.fml_di(fml_dr),
\t.dcb_stb(dcb_stb),
\t.dcb_adr(dcb_adr),
\t.dcb_dat(dcb_dat),
\t.dcb_hit(dcb_hit)
\t
);
task waitclock;
begin
\t@(posedge clk);
\t#1;
end
endtask
task wbwrite;
input [19:1] address;
input [1:0] sel;
input [15:0] data;
integer i;
begin
\twb_adr_i = address;
\twb_cti_i = 3\'b000;
\twb_dat_i = data;
\twb_sel_i = sel;
\twb_cyc_i = 1\'b1;
\twb_stb_i = 1\'b1;
\twb_we_i = 1\'b1;
\ti = 0;
\twhile(~wb_ack_o) begin
\t\ti = i+1;
\t\twaitclock;
\tend
\twaitclock;
\t$display("WB Write: %x=%x sel=%b acked in %d clocks", address, data, sel, i);
\twb_adr_i = 19\'hx;
\twb_cyc_i = 1\'b0;
\twb_stb_i = 1\'b0;
\twb_we_i = 1\'b0;
end
endtask
task wbread;
input [19:1] address;
integer i;
begin
\twb_adr_i = address;\t
\twb_cti_i = 3\'b000;
\twb_cyc_i = 1\'b1;
\twb_stb_i = 1\'b1;
\twb_we_i = 1\'b0;
\ti = 0;
\twhile(~wb_ack_o) begin
\t\ti = i+1;
\t\twaitclock;
\tend
\t$display("WB Read : %x=%x acked in %d clocks", address, wb_dat_o, i);
\twaitclock;
\twb_adr_i = 19\'hx;
\twb_cyc_i = 1\'b0;
\twb_stb_i = 1\'b0;
\twb_we_i = 1\'b0;
end
endtask
task wbwriteburst;
input [19:1] address;
input [15:0] data;
integer i;
begin
\twb_adr_i = address;
\twb_cti_i = 3\'b010;
\twb_dat_i = data;
\twb_sel_i = 2\'b11;
\twb_cyc_i = 1\'b1;
\twb_stb_i = 1\'b1;
\twb_we_i = 1\'b1;
\ti = 0;
\twhile(~wb_ack_o) begin
\t\ti = i+1;
\t\twaitclock;
\tend
\twaitclock;
\t$display("WB Write: %x=%x acked in %d clocks", address, data, i);
\twb_dat_i = data+1;
\twaitclock;
\twb_dat_i = data+2;
\twaitclock;
\twb_dat_i = data+3;
\twb_cti_i = 3\'b111;
\twaitclock;
\twb_adr_i = 19\'hx;
\twb_cti_i = 3\'b000;
\twb_cyc_i = 1\'b0;
\twb_stb_i = 1\'b0;
\twb_we_i = 1\'b0;
end
endtask
task wbreadburst;
input [19:1] address;
integer i;
begin
\twb_adr_i = address;
\twb_cti_i = 3\'b010;
\twb_cyc_i = 1\'b1;
\twb_stb_i = 1\'b1;
\twb_we_i = 1\'b0;
\ti = 0;
\twhile(~wb_ack_o) begin
\t\ti = i+1;
\t\twaitclock;
\tend
\t$display("WB Read : %x=%x acked in %d clocks", address, wb_dat_o, i);
\twaitclock;
\t$display("read burst(1): %x", wb_dat_o);
\twaitclock;
\t$display("read burst(2): %x", wb_dat_o);
\twaitclock;
\twb_cti_i = 3\'b111;
\t$display("read burst(3): %x", wb_dat_o);
\twaitclock;
\twb_adr_i = 19\'hx;
\twb_cti_i = 3\'b000;
\twb_cyc_i = 1\'b0;
\twb_stb_i = 1\'b0;
\twb_we_i = 1\'b0;
end
endtask
always begin
`ifdef ENABLE_VCD
\t$dumpfile("fmlbrg.vcd");
\t$dumpvars(0, dut);
`endif
\trst = 1\'b1;
\t
\twb_adr_i = 19\'d0;
\twb_dat_i = 16\'d0;
\twb_cyc_i = 1\'b0;
\twb_stb_i = 1\'b0;
\twb_we_i = 1\'b0;
\tdcb_stb = 1\'b0;
\tdcb_adr = 20\'d0;
\t
\twaitclock;
\t
\trst = 1\'b0;
\t
\twaitclock;
\t
\t$display("Testing: read miss");
\twbread(19\'h0);
\t$display("Testing: write hit");
\twbwrite(19\'h0, 2\'b11, 16\'h5678);
\twbread(19\'h0);
\t$display("Testing: read miss on a dirty line");
\twbread(19\'h01000);
\t
\t$display("Testing: read hit");
\twbread(19\'h01004);
\t
\t$display("Testing: write miss");
\twbwrite(19\'h0, 2\'b11, 16\'hface);
\twbread(27\'h0);
\twbread(27\'h4);
\t
\t$display("Testing: read burst");
\twbreadburst(19\'h40);
\t
\t$display("Testing: write burst");
\twbwriteburst(19\'h40, 16\'hcaf0);
\t
\t$display("Testing: read burst");
\twbreadburst(19\'h40);
\t$display("Testing: DCB miss");
\tdcb_adr = 20\'hfeba;
\tdcb_stb = 1\'b1;
\twaitclock;
\t$display("Result: hit=%b dat=%x", dcb_hit, dcb_dat);
\t$display("Testing: DCB hit");
\tdcb_adr = 20\'h0;
\tdcb_stb = 1\'b1;
\twaitclock;
\t$display("Result: hit=%b dat=%x", dcb_hit, dcb_dat);
\t
\t$display("Testing: DCB hit");
\tdcb_adr = 20\'h0;
\tdcb_stb = 1\'b1;
\twaitclock;
\t$display("Result: hit=%b dat=%x", dcb_hit, dcb_dat);
\t
\t$display("Testing: DCB hit");
\tdcb_adr = 20\'h1;
\tdcb_stb = 1\'b1;
\twaitclock;
\t$display("Result: hit=%b dat=%x", dcb_hit, dcb_dat);
\t
\t$display("Testing: DCB hit");
\tdcb_adr = 20\'h2;
\tdcb_stb = 1\'b1;
\twaitclock;
\t$display("Result: hit=%b dat=%x", dcb_hit, dcb_dat);
\t
\t$stop;
end
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
* adjusted to FML 8x16 by Zeus Gomez Marmolejo <[email protected]>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_datactl(
\tinput sys_clk,
\tinput sdram_rst,
\t
\tinput read,
\tinput write,
\tinput [3:0] concerned_bank,
\toutput reg read_safe,
\toutput reg write_safe,
\toutput [3:0] precharge_safe,
\t
\toutput reg ack,
\toutput reg direction,
\toutput direction_r,
\t
\tinput tim_cas,
\tinput [1:0] tim_wr
);
/*
* read_safe: whether it is safe to register a Read command
* into the SDRAM at the next cycle.
*/
reg [2:0] read_safe_counter;
always @(posedge sys_clk) begin
\tif(sdram_rst) begin
\t\tread_safe_counter <= 3'd0;
\t\tread_safe <= 1'b1;
\tend else begin
\t\tif(read) begin
\t\t\tread_safe_counter <= 3'd7;
\t\t\tread_safe <= 1'b0;
\t\tend else if(write) begin
\t\t\t/* after a write, read is unsafe for 9-CL cycles, therefore we load :
\t\t\t * 7 at CAS Latency 2 (tim_cas = 0)
\t\t\t * 6 at CAS Latency 3 (tim_cas = 1)
\t\t\t */
\t\t\tread_safe_counter <= {2'b11, ~tim_cas};
\t\t\tread_safe <= 1'b0;
\t\tend else begin
\t\t\tif(read_safe_counter == 3'd1)
\t\t\t\tread_safe <= 1'b1;
\t\t\tif(~read_safe)
\t\t\t\tread_safe_counter <= read_safe_counter - 3'd1;
\t\tend
\tend
end
/*
* write_safe: whether it is safe to register a Write command
* into the SDRAM at the next cycle.
*/
reg [3:0] write_safe_counter;
always @(posedge sys_clk) begin
\tif(sdram_rst) begin
\t\twrite_safe_counter <= 4'd0;
\t\twrite_safe <= 1'b1;
\tend else begin
\t\tif(read) begin
\t\t\twrite_safe_counter <= {3'b100, ~tim_cas};
\t\t\twrite_safe <= 1'b0;
\t\tend else if(write) begin
\t\t\twrite_safe_counter <= 4'd7;
\t\t\twrite_safe <= 1'b0;
\t\tend else begin
\t\t\tif(write_safe_counter == 4'd1)
\t\t\t\twrite_safe <= 1'b1;
\t\t\tif(~write_safe)
\t\t\t\twrite_safe_counter <= write_safe_counter - 4'd1;
\t\tend
\tend
end
/* Generate ack signal.
* After write is asserted, it should pulse after 2 cycles.
* After read is asserted, it should pulse after CL+2 cycles, that is
* 4 cycles when tim_cas = 0
* 5 cycles when tim_cas = 1
*/
reg ack_read2;
reg ack_read1;
reg ack_read0;
always @(posedge sys_clk) begin
\tif(sdram_rst) begin
\t\tack_read2 <= 1'b0;
\t\tack_read1 <= 1'b0;
\t\tack_read0 <= 1'b0;
\tend else begin
\t\tif(tim_cas) begin
\t\t\tack_read2 <= read;
\t\t\tack_read1 <= ack_read2;
\t\t\tack_read0 <= ack_read1;
\t\tend else begin
\t\t\tack_read1 <= read;
\t\t\tack_read0 <= ack_read1;
\t\tend
\tend
end
reg ack0;
always @(posedge sys_clk) begin
\tif(sdram_rst) begin
\t\tack0 <= 1'b0;
\t\tack <= 1'b0;
\tend else begin
\t\tack0 <= ack_read0;
\t\tack <= ack0|write;
\tend
end
/* during a 8-word write, we drive the pins for 9 cycles
* and 1 cycle in advance (first word is invalid)
* so that we remove glitches on DQS without resorting
* to asynchronous logic.
*/
/* direction must be glitch-free, as it directly drives the
* tri-state enable for DQ and DQS.
*/
reg [3:0] counter_writedirection;
always @(posedge sys_clk) begin
\tif(sdram_rst) begin
\t\tcounter_writedirection <= 4'd0;
\t\tdirection <= 1'b0;
\tend else begin
\t\tif(write) begin
\t\t\tcounter_writedirection <= 4'b1001;
\t\t\tdirection <= 1'b1;
\t\tend else begin
\t\t\tif(counter_writedirection == 4'b0001)
\t\t\t\tdirection <= 1'b0;
\t\t\tif(direction)
\t\t\t\tcounter_writedirection <= counter_writedirection - 4'd1;
\t\tend
\tend
end
assign direction_r = write|(|counter_writedirection);
/* Counters that prevent a busy bank from being precharged */
hpdmc_banktimer banktimer0(
\t.sys_clk(sys_clk),
\t.sdram_rst(sdram_rst),
\t
\t.tim_cas(tim_cas),
\t.tim_wr(tim_wr),
\t
\t.read(read & concerned_bank[0]),
\t.write(write & concerned_bank[0]),
\t.precharge_safe(precharge_safe[0])
);
hpdmc_banktimer banktimer1(
\t.sys_clk(sys_clk),
\t.sdram_rst(sdram_rst),
\t
\t.tim_cas(tim_cas),
\t.tim_wr(tim_wr),
\t
\t.read(read & concerned_bank[1]),
\t.write(write & concerned_bank[1]),
\t.precharge_safe(precharge_safe[1])
);
hpdmc_banktimer banktimer2(
\t.sys_clk(sys_clk),
\t.sdram_rst(sdram_rst),
\t
\t.tim_cas(tim_cas),
\t.tim_wr(tim_wr),
\t
\t.read(read & concerned_bank[2]),
\t.write(write & concerned_bank[2]),
\t.precharge_safe(precharge_safe[2])
);
hpdmc_banktimer banktimer3(
\t.sys_clk(sys_clk),
\t.sdram_rst(sdram_rst),
\t
\t.tim_cas(tim_cas),
\t.tim_wr(tim_wr),
\t
\t.read(read & concerned_bank[3]),
\t.write(write & concerned_bank[3]),
\t.precharge_safe(precharge_safe[3])
);
endmodule
|
/*
* Zet synthesis stub for timing analysis
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module fpga_zet_top (
// Wishbone master interface
input clk_i,
input rst_i,
input [15:0] wb_dat_i,
output reg [15:0] wb_dat_o,
output reg [19:1] wb_adr_o,
output reg wb_we_o,
output reg wb_tga_o, // io/mem
output reg [ 1:0] wb_sel_o,
output reg wb_stb_o,
output reg wb_cyc_o,
input wb_ack_i,
input intr,
output reg inta,
input [ 3:0] iid,
output reg [19:0] pc
);
// Registers and nets
reg [15:0] wb_dat_i_l;
wire [15:0] wb_dat_o_l;
wire [19:1] wb_adr_o_l;
wire wb_we_o_l;
wire wb_tga_o_l; // io/mem
wire [ 1:0] wb_sel_o_l;
wire wb_stb_o_l;
wire wb_cyc_o_l;
reg wb_ack_i_l;
reg intr_l; // intr
wire inta_l; // inta
reg [ 3:0] iid_l;
wire [19:0] pc_l;
// Module instances
zet zet (
.clk_i (clk_i),
.rst_i (rst_i),
// Wishbone master interface
.wb_dat_i (wb_dat_i_l),
.wb_dat_o (wb_dat_o_l),
.wb_adr_o (wb_adr_o_l),
.wb_we_o (wb_we_o_l),
.wb_tga_o (wb_tga_o_l), // io/mem
.wb_sel_o (wb_sel_o_l),
.wb_stb_o (wb_stb_o_l),
.wb_cyc_o (wb_cyc_o_l),
.wb_ack_i (wb_ack_i_l),
.intr (intr_l), // intr
.inta (inta_l), // inta
.iid (iid_l),
.pc (pc_l)
);
always @(posedge clk_i)
begin
wb_dat_i_l <= wb_dat_i;
wb_dat_o <= wb_dat_o_l;
wb_adr_o <= wb_adr_o_l;
wb_we_o <= wb_we_o_l;
wb_tga_o <= wb_tga_o_l;
wb_sel_o <= wb_sel_o_l;
wb_stb_o <= wb_stb_o_l;
wb_cyc_o <= wb_cyc_o_l;
wb_ack_i_l <= wb_ack_i;
intr_l <= intr;
inta <= inta_l;
iid_l <= iid;
pc <= pc_l;
end
endmodule
|
/*
* Wishbone asynchronous bridge
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module wb_abrg (
input sys_rst,
// Wishbone slave interface
input wbs_clk_i,
input [19:1] wbs_adr_i,
input [15:0] wbs_dat_i,
output reg [15:0] wbs_dat_o,
input [ 1:0] wbs_sel_i,
input wbs_tga_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
output wbs_ack_o,
// Wishbone master interface
input wbm_clk_i,
output reg [19:1] wbm_adr_o,
output reg [15:0] wbm_dat_o,
input [15:0] wbm_dat_i,
output reg [ 1:0] wbm_sel_o,
output reg wbm_tga_o,
output wbm_stb_o,
output wbm_cyc_o,
output reg wbm_we_o,
input wbm_ack_i
);
// Registers and nets
wire wbs_stb;
wire init_tr;
reg wbm_stb;
reg [2:0] sync_stb;
reg [2:0] sync_ack;
reg ft_stb;
reg ft_ack;
reg stb_r;
reg ack_r;
reg [19:1] wbm_adr_o_r;
reg [15:0] wbm_dat_o_r;
reg [ 1:0] wbm_sel_o_r;
reg wbm_tga_o_r;
reg wbm_we_o_r;
reg [15:0] wbs_dat_o_r;
reg [15:0] wbm_dat_i_r;
// Continous assignments
assign wbs_stb = wbs_stb_i & wbs_cyc_i;
// recreate the flag from the level change
assign wbs_ack_o = (sync_ack[2] ^ sync_ack[1]);
assign wbm_stb_o = wbm_stb;
assign wbm_cyc_o = wbm_stb;
/*
* A new wishbone transaction is issued:
* . by changing stb from 0 to 1
* . by continue asserting stb after ack is received
*/
assign init_tr = ~stb_r & wbs_stb | ack_r & ~wbs_ack_o & wbs_stb;
// Behaviour
// wbm_stb
always @(posedge wbm_clk_i)
wbm_stb <= sys_rst ? 1'b0
: (wbm_stb ? ~wbm_ack_i : sync_stb[2] ^ sync_stb[1]);
// old stb and ack state
always @(posedge wbs_clk_i) stb_r <= wbs_stb;
always @(posedge wbs_clk_i) ack_r <= wbs_ack_o;
always @(posedge wbs_clk_i)
ft_stb <= sys_rst ? 1'b0 : (init_tr ? ~ft_stb : ft_stb);
// synchronize the last level change
always @(posedge wbm_clk_i)
sync_stb <= sys_rst ? 3'h0 : {sync_stb[1:0], ft_stb};
// this changes level when a flag is seen
always @(posedge wbm_clk_i)
ft_ack <= sys_rst ? 1'b0 : (wbm_ack_i ? ~ft_ack : ft_ack);
// which can then be synched to wbs_clk_i
always @(posedge wbs_clk_i)
sync_ack <= sys_rst ? 3'h0 : {sync_ack[1:0], ft_ack};
// rest of the wishbone signals
always @(posedge wbm_clk_i)
{wbm_adr_o, wbm_adr_o_r} <= {wbm_adr_o_r, wbs_adr_i};
always @(posedge wbm_clk_i)
{wbm_dat_o, wbm_dat_o_r} <= {wbm_dat_o_r, wbs_dat_i};
always @(posedge wbm_clk_i)
{wbm_sel_o, wbm_sel_o_r} <= {wbm_sel_o_r, wbs_sel_i};
always @(posedge wbm_clk_i)
{wbm_we_o, wbm_we_o_r} <= {wbm_we_o_r, wbs_we_i};
always @(posedge wbm_clk_i)
{wbm_tga_o, wbm_tga_o_r} <= {wbm_tga_o_r, wbs_tga_i};
/*
* Register input coming from the slave as that can change
* after the ack is received
*/
always @(posedge wbm_clk_i)
wbm_dat_i_r <= wbm_ack_i ? wbm_dat_i : wbm_dat_i_r;
always @(posedge wbs_clk_i)
{wbs_dat_o, wbs_dat_o_r} <= {wbs_dat_o_r, wbm_dat_i_r};
endmodule
|
/*\r
* PAL/DAC controller for VGA\r
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>\r
*\r
* VGA FML support\r
* Copyright (C) 2013 Charley Picker <[email protected]>\r
*\r
* This file is part of the Zet processor. This processor is free\r
* hardware; you can redistribute it and/or modify it under the terms of\r
* the GNU General Public License as published by the Free Software\r
* Foundation; either version 3, or (at your option) any later version.\r
*\r
* Zet is distrubuted in the hope that it will be useful, but WITHOUT\r
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public\r
* License for more details.\r
*\r
* You should have received a copy of the GNU General Public License\r
* along with Zet; see the file COPYING. If not, see\r
* <http://www.gnu.org/licenses/>.\r
*/\r
\r
module vga_pal_dac_fml (\r
input clk, // 100 Mhz clock\r
input rst,\r
\r
input enable_pal_dac,\r
\r
// VGA PAL/DAC input signals\r
\r
input horiz_sync_pal_dac_i,\r
input vert_sync_pal_dac_i,\r
input video_on_h_pal_dac_i,\r
input video_on_v_pal_dac_i,\r
input [7:0] character_pal_dac_i,\r
\r
// VGA PAL/DAC configuration signals\r
\r
input shift_reg1, // if set: 320x200\r
input graphics_alpha, // if not set: 640x400 text mode\r
\r
// attribute_ctrl\r
input [3:0] pal_addr,\r
input pal_we,\r
output [7:0] pal_read,\r
input [7:0] pal_write,\r
\r
// dac_regs\r
input dac_we,\r
input [1:0] dac_read_data_cycle,\r
input [7:0] dac_read_data_register,\r
output [3:0] dac_read_data,\r
input [1:0] dac_write_data_cycle,\r
input [7:0] dac_write_data_register,\r
input [3:0] dac_write_data,\r
\r
// VGA PAL/DAC output signals\r
\r
// VGA pad signals\r
output reg [3:0] vga_red_o,\r
output reg [3:0] vga_green_o,\r
output reg [3:0] vga_blue_o,\r
output reg horiz_sync,\r
output vert_sync,\r
\r
// retrace signals\r
output v_retrace,\r
output vh_retrace\r
);\r
\r
// Registers and nets\r
wire video_on_v;\r
reg [1:0] video_on_h_p;\r
\r
wire video_on;\r
\r
wire [3:0] attr;\r
wire [7:0] index;\r
wire [7:0] index_pal;\r
reg [7:0] index_gm;\r
\r
wire video_on_h;\r
\r
reg [1:0] horiz_sync_p;\r
\r
wire [3:0] red;\r
wire [3:0] green;\r
wire [3:0] blue;\r
\r
// Module instances\r
\r
vga_palette_regs_fml palette_regs (\r
.clk (clk),\r
\r
.attr (attr),\r
.index (index_pal),\r
\r
.address (pal_addr),\r
.write (pal_we),\r
.read_data (pal_read),\r
.write_data (pal_write)\r
);\r
\r
vga_dac_regs_fml dac_regs (\r
.clk (clk),\r
\r
.index (index),\r
.red (red),\r
.green (green),\r
.blue (blue),\r
\r
.write (dac_we),\r
\r
.read_data_cycle (dac_read_data_cycle),\r
.read_data_register (dac_read_data_register),\r
.read_data (dac_read_data),\r
\r
.write_data_cycle (dac_write_data_cycle),\r
.write_data_register (dac_write_data_register),\r
.write_data (dac_write_data)\r
);\r
\r
// Continuous assignments\r
assign video_on_v = video_on_v_pal_dac_i;\r
assign vert_sync = vert_sync_pal_dac_i;\r
\r
assign video_on = video_on_h && video_on_v;\r
\r
assign attr = character_pal_dac_i[3:0];\r
assign index = (graphics_alpha & shift_reg1) ? index_gm : index_pal;\r
\r
assign video_on_h = video_on_h_p[1];\r
\r
assign v_retrace = !video_on_v;\r
assign vh_retrace = v_retrace | !video_on_h;\r
\r
// index_gm\r
always @(posedge clk)\r
if (rst)\r
begin\r
index_gm <= 8'h0;\r
end\r
else\r
if (enable_pal_dac)\r
begin\r
index_gm <= character_pal_dac_i;\r
end\r
\r
// Horiz sync\r
always @(posedge clk)\r
if (rst)\r
begin\r
{ horiz_sync, horiz_sync_p } <= 3'b0;\r
end\r
else\r
if (enable_pal_dac)\r
begin\r
{ horiz_sync, horiz_sync_p } <= { horiz_sync_p[1:0], horiz_sync_pal_dac_i }; \r
end\r
\r
// Video_on pipe\r
always @(posedge clk)\r
if (rst)\r
begin\r
video_on_h_p <= 2'b0;\r
end\r
else\r
if (enable_pal_dac)\r
begin\r
video_on_h_p <= { video_on_h_p[0], video_on_h_pal_dac_i };\r
end\r
\r
// Colour signals\r
always @(posedge clk)\r
if (rst)\r
begin\r
vga_red_o <= 4'b0;\r
vga_green_o <= 4'b0;\r
vga_blue_o <= 4'b0;\r
end\r
else\r
if (enable_pal_dac)\r
begin\r
vga_blue_o <= video_on ? blue : 4'h0;\r
vga_green_o <= video_on ? green : 4'h0;\r
vga_red_o <= video_on ? red : 4'h0;\r
end\r
\r
endmodule\r
|
/*\r
* DAC register file for VGA\r
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>\r
*\r
* VGA FML support\r
* Copyright (C) 2013 Charley Picker <[email protected]>\r
*\r
* This file is part of the Zet processor. This processor is free\r
* hardware; you can redistribute it and/or modify it under the terms of\r
* the GNU General Public License as published by the Free Software\r
* Foundation; either version 3, or (at your option) any later version.\r
*\r
* Zet is distrubuted in the hope that it will be useful, but WITHOUT\r
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public\r
* License for more details.\r
*\r
* You should have received a copy of the GNU General Public License\r
* along with Zet; see the file COPYING. If not, see\r
* <http://www.gnu.org/licenses/>.\r
*/\r
\r
module vga_dac_regs_fml (\r
input clk,\r
\r
// VGA read interface\r
input [7:0] index,\r
output reg [3:0] red,\r
output reg [3:0] green,\r
output reg [3:0] blue,\r
\r
// CPU interface\r
input write,\r
\r
// CPU read interface\r
input [1:0] read_data_cycle,\r
input [7:0] read_data_register,\r
output reg [3:0] read_data,\r
\r
// CPU write interface\r
input [1:0] write_data_cycle,\r
input [7:0] write_data_register,\r
input [3:0] write_data\r
);\r
\r
// Registers, nets and parameters\r
reg [3:0] red_dac [0:255];\r
reg [3:0] green_dac [0:255];\r
reg [3:0] blue_dac [0:255];\r
\r
// Behaviour\r
// VGA read interface\r
always @(posedge clk)\r
begin\r
red <= red_dac[index];\r
green <= green_dac[index];\r
blue <= blue_dac[index];\r
end\r
\r
// CPU read interface\r
always @(posedge clk)\r
case (read_data_cycle)\r
2'b00: read_data <= red_dac[read_data_register];\r
2'b01: read_data <= green_dac[read_data_register];\r
2'b10: read_data <= blue_dac[read_data_register];\r
default: read_data <= 4'h0;\r
endcase\r
\r
// CPU write interface\r
always @(posedge clk)\r
if (write)\r
case (write_data_cycle)\r
2'b00: red_dac[write_data_register] <= write_data;\r
2'b01: green_dac[write_data_register] <= write_data;\r
2'b10: blue_dac[write_data_register] <= write_data;\r
endcase\r
\r
endmodule\r
|
/*\r
* DUT VGA Address Generation\r
*\r
* VGA FML support\r
* Copyright (C) 2013 Charley Picker <[email protected]>\r
*\r
* This file is part of the Zet processor. This processor is free\r
* hardware; you can redistribute it and/or modify it under the terms of\r
* the GNU General Public License as published by the Free Software\r
* Foundation; either version 3, or (at your option) any later version.\r
*\r
* Zet is distrubuted in the hope that it will be useful, but WITHOUT\r
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public\r
* License for more details.\r
*\r
* You should have received a copy of the GNU General Public License\r
* along with Zet; see the file COPYING. If not, see\r
* <http://www.gnu.org/licenses/>.\r
*/\r
\r
//`timescale 1ns/10ps\r
`timescale 1ns/1ps\r
\r
module tb_vga_linear_fml;\r
\r
// Registers and nets\r
reg clk_50;\r
reg rst;\r
\r
reg enable_sequencer;\r
reg enable_crtc;\r
\r
// Sequencer input signals\r
\r
reg [9:0] h_count;\r
reg horiz_sync_i;\r
\r
reg [9:0] v_count;\r
reg vert_sync;\r
\r
reg video_on_h_i;\r
reg video_on_v;\r
\r
// CRTC configuration signals\r
\r
reg [6:0] horiz_total;\r
reg [6:0] end_horiz;\r
reg [6:0] st_hor_retr;\r
reg [4:0] end_hor_retr;\r
reg [9:0] vert_total;\r
reg [9:0] end_vert;\r
reg [9:0] st_ver_retr;\r
reg [3:0] end_ver_retr; \r
\r
// CSR slave interface for reading\r
wire [17:1] csr_adr_o;\r
reg [15:0] csr_dat_i;\r
reg csr_ack;\r
wire csr_stb_o;\r
\r
// FML slave interface for reading\r
wire [17:1] fml_adr_o;\r
reg [15:0] fml_dat_i;\r
wire fml_stb_o;\r
reg fml_ack;\r
wire fml_we = 1\'b0;\r
wire fml_dw = 16\'h1234;\r
\r
wire [7:0] fml_color;\r
wire [7:0] color;\r
\r
wire video_on_h_gm;\r
wire fml_video_on_h_gm; \r
\r
wire horiz_sync_gm;\r
wire fml_horiz_sync_gm; \r
\r
wire [17:1] csr_gm_adr_o;\r
wire [17:1] fml_gm_adr_o;\r
wire csr_gm_stb_o;\r
\r
wire fml_gm_stb_o;\r
\r
wire [9:0] hor_disp_end;\r
wire [9:0] hor_scan_end;\r
wire [9:0] ver_disp_end;\r
wire [9:0] ver_sync_beg;\r
wire [3:0] ver_sync_end;\r
wire [9:0] ver_scan_end;\r
\r
/* Process FML requests */\r
reg [2:0] fml_wcount;\r
reg [2:0] fml_rcount;\r
reg [3:0] fml_pipe;\r
initial begin\r
\t fml_ack = 1\'b0;\r
\t fml_wcount = 0;\r
\t fml_rcount = 0;\r
end\r
\r
always @(posedge clk_50)\r
fml_pipe <= rst ? 4\'b0 : { fml_pipe[2:0], fml_gm_stb_o };\r
\r
always @(posedge clk_50) begin\r
\t if(fml_pipe[1] & (fml_wcount == 0) & (fml_rcount == 0)) begin\r
\t\t fml_ack <= 1\'b1;\r
\t\t if(fml_we) begin\r
\t\t\t //$display("%t FML W addr %x data %x", $time, fml_gm_adr_o, fml_dw);\r
\t\t\t fml_wcount <= 7;\r
\t\t end else begin\r
\t\t\t //fml_dat_i = 16\'hbeef;\r
\t\t\t fml_dat_i <= 16\'hbeef;\r
\t\t\t //$display("%t FML R addr %x data %x", $time, fml_gm_adr_o, fml_dat_i);\r
\t\t\t fml_rcount <= 7;\r
\t\t end\r
\t end else\r
\t\t fml_ack <= 1\'b0;\r
\t if(fml_wcount != 0) begin\r
\t\t //#1 $display("%t FML W continuing %x / %d", $time, fml_dw, fml_wcount);\r
\t\t fml_wcount <= fml_wcount - 1;\r
\t end\r
\t if(fml_rcount != 0) begin\r
\t\t //fml_dat_i = #1 {13\'h1eba, fml_rcount};\r
\t\t fml_dat_i <= {13\'h1eba, fml_rcount};\r
\t\t //$display("%t FML R continuing %x / %d", $time, fml_dat_i, fml_rcount);\r
\t\t fml_rcount <= fml_rcount - 1;\r
\t end\r
end\r
\r
/* Process CSR requests */\r
reg [15:0] csr_dat;\r
reg [2:0] csr_rcount;\r
reg [3:0] csr_pipe;\r
initial begin\r
\t csr_ack = 1\'b0;\t \r
\t csr_rcount = 0;\r
end\r
\r
always @(posedge clk_50)\r
csr_pipe <= rst ? 4\'b0 : { csr_pipe[2:0], csr_gm_stb_o };\r
\r
always @(posedge clk_50) begin\r
//if (csr_gm_adr_o)\r
//$display("%t CSR R addr %x", $time, csr_gm_adr_o);\r
if (csr_pipe[1] & (csr_rcount == 0))\r
begin\r
csr_ack <= 1\'b1;\r
\t\t //csr_dat_i = 16\'hbeef;\r
\t\t csr_dat_i <= 16\'hbeef;\r
\t\t\t //$display("%t CSR R data %x", $time, csr_dat_i);\r
\t\t\t csr_rcount <= 7;\r
\t\t end else\r
\t\t csr_ack <= 1\'b0;\t\t\r
\t if(csr_pipe[1] & (csr_rcount != 0)) begin\r
\t\t //csr_dat_i = #1 {13\'h1eba, csr_rcount};\r
\t\t csr_dat_i <= {13\'h1eba, csr_rcount};\r
\t\t //$display("%t CSR R continuing %x / %d", $time, csr_dat_i, csr_rcount);\r
\t\t csr_rcount <= csr_rcount - 1;\r
\t end\t \r
end\r
\r
// Module instantiations\r
vga_linear linear (\r
.clk (clk_50),\r
.rst (rst),\r
\r
//.enable (enable_sequencer),\r
\r
// CSR slave interface for reading\r
.csr_adr_o (csr_gm_adr_o),\r
.csr_dat_i (csr_dat_i),\r
.csr_stb_o (csr_gm_stb_o),\r
\r
.h_count (h_count),\r
.v_count (v_count),\r
.horiz_sync_i (horiz_sync_i),\r
.video_on_h_i (video_on_h_i),\r
.video_on_h_o (video_on_h_gm),\r
\r
.color (color),\r
.horiz_sync_o (horiz_sync_gm)\r
);\r
\r
vga_linear_fml linear_fml (\r
.clk (clk_50),\r
.rst (rst),\r
\r
.enable (enable_sequencer),\r
\r
// CSR slave interface for reading\r
.fml_adr_o (fml_gm_adr_o),\r
.fml_dat_i (fml_dat_i),\r
.fml_stb_o (fml_gm_stb_o),\r
\r
.h_count (h_count),\r
.v_count (v_count),\r
.horiz_sync_i (horiz_sync_i),\r
.video_on_h_i (video_on_h_i),\r
.video_on_h_o (fml_video_on_h_gm),\r
\r
.color (fml_color),\r
.horiz_sync_o (fml_horiz_sync_gm)\r
);\r
\r
\r
// Continuous assignments\r
// assign hor_scan_end = { horiz_total[6:2] + 1\'b1, horiz_total[1:0], 3\'h7 };\r
assign hor_scan_end = 10\'d799;\r
\r
// assign hor_disp_end = { end_horiz, 3\'h7 };\r
assign hor_disp_end = 10\'d639;\r
\r
// assign ver_scan_end = vert_total + 10\'d1;\r
assign ver_scan_end = 10\'d448;\r
\r
// assign ver_disp_end = end_vert + 10\'d1;\r
assign ver_disp_end = 10\'d400;\r
\r
assign ver_sync_beg = st_ver_retr;\r
\r
assign ver_sync_end = end_ver_retr + 4\'d1;\r
\r
// Behaviour\r
// Clock generation\r
//always #10 clk_50 <= !clk_50;\r
initial clk_50 = 1\'b0;\r
always #5 clk_50 = ~clk_50;\r
\r
task waitclock;\r
begin\r
\t@(posedge clk_50);\r
\t#1;\r
end\r
endtask\r
\r
always @(posedge clk_50) begin\r
if (rst) begin\r
h_count = 10\'b0;\r
horiz_sync_i = 1\'b1;\r
v_count = 10\'b0;\r
vert_sync = 1\'b1;\r
video_on_h_i = 1\'b1;\r
video_on_v = 1\'b1;\r
$display("Pixel counter reset to zero");\r
end else\r
begin\r
if (enable_crtc)\r
begin\r
h_count <= (h_count==hor_scan_end) ? 10\'b0 : h_count + 10\'b1;\r
horiz_sync_i <= horiz_sync_i ? (h_count[9:3]!=st_hor_retr)\r
: (h_count[7:3]==end_hor_retr);\r
v_count <= (v_count==ver_scan_end && h_count==hor_scan_end) ? 10\'b0\r
: ((h_count==hor_scan_end) ? v_count + 10\'b1 : v_count);\r
vert_sync <= vert_sync ? (v_count!=ver_sync_beg)\r
: (v_count[3:0]==ver_sync_end);\r
\r
video_on_h_i <= (h_count==hor_scan_end) ? 1\'b1\r
: ((h_count==hor_disp_end) ? 1\'b0 : video_on_h_i);\r
video_on_v <= (v_count==10\'h0) ? 1\'b1\r
: ((v_count==ver_disp_end) ? 1\'b0 : video_on_v);\r
end\r
end \r
end \r
\r
always begin\r
// Initialize to a known state\r
rst = 1\'b1; // reset is active \r
enable_crtc = 1\'b0; // Make sure the crtc is not active\r
enable_sequencer = 1\'b0; // Make sure sequencer is not active\r
\r
waitclock; \r
\r
rst = 1\'b0;\r
\r
enable_crtc = 1\'b1; // Enable crtc\r
enable_sequencer = 1\'b1; // Enable sequencer \r
\r
waitclock;\r
\r
// CRTC configuration signals\r
\r
horiz_total = 7\'d639; // reg [6:0] horiz_total,\r
end_horiz = 7\'d750; // reg [6:0] end_horiz,\r
// st_hor_retr = 7\'d760; // reg [6:0] st_hor_retr,\r
st_hor_retr = 7\'d656; // reg [6:0] st_hor_retr,\r
// end_hor_retr = 5\'d10; // reg [4:0] end_hor_retr,\r
end_hor_retr = 5\'d752; // reg [4:0] end_hor_retr,\r
vert_total = 10\'d399; // reg [9:0] vert_total,\r
end_vert = 10\'d550; // reg [9:0] end_vert,\r
st_ver_retr = 10\'d560; // reg [9:0] st_ver_retr,\r
end_ver_retr = 4\'d10; // reg [3:0] end_ver_retr,\r
\r
//waitclock;\r
\r
// Total number of pixels to check\r
repeat (1000) begin\r
begin\r
if (color != fml_color) begin \r
$display("Attributes color = %x and fml_color = %x did not match at (h_count = %d and v_count = %d) at time index %t" , color, fml_color, h_count, v_count, $time); \r
end\r
//if (csr_gm_adr_o != fml_gm_adr_o) begin\r
// $display("Address csr_gm_adr_o = %x and fml_gm_adr_o = %x did not match at (h_count = %d and v_count = %d) at time index %t" , csr_gm_adr_o, fml_gm_adr_o, h_count, v_count, $time); \r
//end\r
if (video_on_h_gm != fml_video_on_h_gm) begin\r
$display("Video_on_h video_on_h_gm = %x and fml_video_on_h_gm = %x did not match at (h_count = %d and v_count = %d) at time index %t" , csr_gm_adr_o, fml_video_on_h_gm, h_count, v_count, $time);\r
end\r
if (horiz_sync_gm != fml_horiz_sync_gm) begin\r
$display("Horiz_sync horiz_sync_gm = %x and fml_horiz_sync_gm = %x did not match at (h_count = %d and v_count = %d) at time index %t" , horiz_sync_gm, fml_horiz_sync_gm, h_count, v_count, $time);\r
end\r
end\r
waitclock;\r
//nextpixel;\r
end \r
\r
$stop;\r
\r
end \r
\r
endmodule
|
/*
* 8 bit pwm DAC
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module sound_dac8 (
input clk,
input [7:0] dac_in,
output audio_out
);
reg [8:0] dac_register;
assign audio_out = dac_register[8];
always @(posedge clk) dac_register <= dac_register[7:0] + dac_in;
endmodule
|
/*
* Super Simple Priority Interrupt Controller
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module simple_pic (
input clk,
input rst,
input [7:0] intv,
input inta,
output intr,
output reg [2:0] iid
);
// Registers
reg [7:0] irr;
reg inta_r;
reg int3_r;
reg int4_r;
// Continuous assignments, note that only IRQs 0,1,3 & 4 are driven atm
assign intr = irr[4] | irr[3] | irr[1] | irr[0];
// Behaviour of inta_r
always @(posedge clk) inta_r <= inta;
// irr
always @(posedge clk)
irr[0] <= rst ? 1'b0 : (intv[0] | irr[0] & !(iid == 3'b000 && inta_r && !inta));
always @(posedge clk)
irr[1] <= rst ? 1'b0 : (intv[1] | irr[1] & !(iid == 3'b001 && inta_r && !inta));
always @(posedge clk)
irr[3] <= rst ? 1'b0 : ((intv[3] && !int3_r) | irr[3] & !(iid == 3'b011 && inta_r && !inta));
always @(posedge clk) int3_r <= rst ? 1'b0 : intv[3]; // int3_r
always @(posedge clk)
irr[4] <= rst ? 1'b0 : ((intv[4] && !int4_r) | irr[4] & !(iid == 3'b100 && inta_r && !inta));
always @(posedge clk) int4_r <= rst ? 1'b0 : intv[4]; // int4_r
always @(posedge clk) // iid
iid <= rst ? 3'b0 : (inta ? iid :
(irr[0] ? 3'b000 :
(irr[1] ? 3'b001 :
(irr[3] ? 3'b011 :
(irr[4] ? 3'b100 :
3'b000
)))));
endmodule
|
/*
* 8-bit rotate module for Zet
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_rxr8 (
input [7:0] x,
input ci,
input [3:0] y,
input e,
output reg [7:0] w,
output reg co
);
always @(x or ci or y or e)
case (y)
default: {co,w} <= {ci,x};
5'd01: {co,w} <= e ? {x[0], ci, x[7:1]} : {ci, x[0], x[7:1]};
5'd02: {co,w} <= e ? {x[1:0], ci, x[7:2]} : {ci, x[1:0], x[7:2]};
5'd03: {co,w} <= e ? {x[2:0], ci, x[7:3]} : {ci, x[2:0], x[7:3]};
5'd04: {co,w} <= e ? {x[3:0], ci, x[7:4]} : {ci, x[3:0], x[7:4]};
5'd05: {co,w} <= e ? {x[4:0], ci, x[7:5]} : {ci, x[4:0], x[7:5]};
5'd06: {co,w} <= e ? {x[5:0], ci, x[7:6]} : {ci, x[5:0], x[7:6]};
5'd07: {co,w} <= e ? {x[6:0], ci, x[7]} : {ci, x[6:0], x[7]};
5'd08: {co,w} <= {x,ci};
endcase
endmodule
|
/*
* Wishbone Compatible RS232 core
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module serial (
// Wishbone slave interface
input wb_clk_i, // Clock Input
input wb_rst_i, // Reset Input
input [15:0] wb_dat_i, // Command to send to mouse
output [15:0] wb_dat_o, // Received data
input wb_cyc_i, // Cycle
input wb_stb_i, // Strobe
input [ 1:0] wb_adr_i, // Wishbone address lines
input [ 1:0] wb_sel_i, // Wishbone Select lines
input wb_we_i, // Write enable
output reg wb_ack_o, // Normal bus termination
output wb_tgc_o, // Interrupt request
output rs232_tx, // RS232 output
input rs232_rx // RS232 input
);
// --------------------------------------------------------------------
// This section is a simple WB interface
// --------------------------------------------------------------------
reg [7:0] dat_o;
wire [7:0] dat_i;
wire [2:0] UART_Addr;
wire wb_ack_i;
wire wr_command;
wire rd_command;
// Unused output
wire rxd_endofpacket;
// --------------------------------------------------------------------
// Wires for Interrupt Enable Register (IER)
// --------------------------------------------------------------------
wire EDAI;
wire ETXH;
//wire ERLS = ier[2]; // Enable Receive Line Status Interrupt
wire EMSI;
wire [7:0] INTE;
// --------------------------------------------------------------------
// Wires for Interrupt Identification Register (IIR)
// --------------------------------------------------------------------
reg IPEN; // 0 if intereupt pending
reg IPEND; // Interupt pending
reg [1:0] INTID; // Interrupt ID Bits
wire [7:0] ISTAT;
// --------------------------------------------------------------------
// Wires for Line Status Register (LSR)
// --------------------------------------------------------------------
wire TSRE;
wire PE;
wire BI;
wire FE;
wire OR;
reg rx_rden; // Receive data enable
reg DR; // Data Ready
reg THRE; // Transmitter Holding Register Empty
wire [7:0] LSTAT;
// --------------------------------------------------------------------
// Wires for Modem Control Register (MCR)
// --------------------------------------------------------------------
wire DTR;
wire RTS;
wire OUT1;
wire OUT2;
wire LOOP;
wire [7:0] MCON;
// --------------------------------------------------------------------
// Wires for Modem Status Register (MSR)
// --------------------------------------------------------------------
wire RLSD;
wire RI;
wire DSR;
wire CTS;
wire DRLSD;
wire TERI;
wire DDSR;
wire DCTS;
wire [7:0] MSTAT;
// --------------------------------------------------------------------
// Wires for Line Control Register (LCRR)
// --------------------------------------------------------------------
wire [7:0] LCON;
wire dlab;
// --------------------------------------------------------------------
// 8250A Registers
// --------------------------------------------------------------------
wire [7:0] output_data; // Wired to receiver
reg [7:0] input_data; // Transmit register
reg [3:0] ier; // Interrupt enable register
reg [7:0] lcr; // Line Control register
reg [7:0] mcr; // Modem Control register
reg [7:0] dll; // Data latch register low
reg [7:0] dlh; // Data latch register high
// --------------------------------------------------------------------
// Instantiate the UART
// --------------------------------------------------------------------
//reg rx_read; // Signal to read next byte in the buffer
wire rx_drdy; // Indicates new data has come in
wire rx_idle; // Indicates Receiver is idle
wire rx_over; // Indicates buffer over run error
reg tx_send; // Signal to send data
wire to_error; // Indicates a transmit error occured
wire tx_done;
wire tx_busy; // Signal transmitter is busy
// --------------------------------------------------------------------
// Baud Clock Generator
// --------------------------------------------------------------------
wire [18:0] Baudiv;
wire Baud1Tick;
wire Baud8Tick;
reg [18:0] BaudAcc1;
reg [15:0] BaudAcc8;
wire [18:0] BaudInc;
always @(posedge wb_clk_i or posedge wb_rst_i) begin // Synchrounous
if (wb_rst_i) wb_ack_o <= 1'b0;
else wb_ack_o <= wb_ack_i & ~wb_ack_o; // one clock delay on acknowledge output
end
// --------------------------------------------------------------------
// This section is a simple 8250 Emulator that front ends the UART
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// Register addresses and defaults
// --------------------------------------------------------------------
`define UART_RG_TR 3'h0 // RW - Transmit / Receive register
`define UART_RG_IE 3'h1 // RW - Interrupt enable
`define UART_RG_II 3'h2 // R - Interrupt identification (no fifo on 8250)
`define UART_RG_LC 3'h3 // RW - Line Control
`define UART_RG_MC 3'h4 // W - Modem control
`define UART_RG_LS 3'h5 // R - Line status
`define UART_RG_MS 3'h6 // R - Modem status
`define UART_RG_SR 3'h7 // RW - Scratch register
`define UART_DL_LSB 8'h60 // Divisor latch least significant byte, hard coded to 9600 baud
`define UART_DL_MSB 8'h00 // Divisor latch most significant byte
`define UART_IE_DEF 8'h00 // Interupt Enable default
`define UART_LC_DEF 8'h03 // Line Control default
`define UART_MC_DEF 8'h00 // Line Control default
// --------------------------------------------------------------------
// UART Interrupt Behavior
// --------------------------------------------------------------------
always @(posedge wb_clk_i or posedge wb_rst_i) begin // Synchrounous
if(wb_rst_i) begin
IPEN <= 1'b1; // Interupt Enable default
IPEND <= 1'b0; // Interupt pending
INTID <= 2'b00; // Interupt ID
end
else begin
if(DR & EDAI) begin // If enabled
IPEN <= 1'b0; // Set latch (inverted)
IPEND <= 1'b1; // Indicates an Interupt is pending
INTID <= 2'b10; // Set Interupt ID
end
if(THRE & ETXH) begin // If enabled
IPEN <= 1'b0; // Set latch (inverted)
IPEND <= 1'b1; // Indicates an Interupt is pending
INTID <= 2'b01; // Set Interupt ID
end
if((CTS | DSR | RI |RLSD) && EMSI) begin // If enabled
IPEN <= 1'b0; // Set latch (inverted)
IPEND <= 1'b1; // Indicates an Interupt is pending
INTID <= 2'b00; // Interupt ID
end
if(rd_command) // If a read was requested
case(UART_Addr) // Determine which register was read
`UART_RG_TR: IPEN <= 1'b1; // Resets interupt flag
`UART_RG_II: IPEN <= 1'b1; // Resets interupt flag
`UART_RG_MS: IPEN <= 1'b1; // Resets interupt flag
default: ; // Do nothing if anything else
endcase // End of case
if(wr_command) // If a write was requested
case(UART_Addr) // Determine which register was writen to
`UART_RG_TR: IPEN <= 1'b1; // Resets interupt flag;
default: ; // Do nothing if anything else
endcase // End of case
if(IPEN & IPEND) begin
INTID <= 2'b00; // user has cleared the Interupt
IPEND <= 1'b0; // Interupt pending
end
end
end // Synchrounous always
// --------------------------------------------------------------------
// UART Line Status Behavior
// --------------------------------------------------------------------
always @(posedge wb_clk_i or posedge wb_rst_i) begin // Synchrounous
if(wb_rst_i) begin
// rx_read <= 1'b0; // Singal to get the data out of the buffer
rx_rden <= 1'b1; // Singal to get the data out of the buffer
DR <= 1'b0; // Indicates data is waiting to be read
THRE <= 1'b0; // Transmitter holding register is empty
end
else begin
if(rx_drdy) begin // If enabled
DR <= 1'b1; // Indicates data is waiting to be read
if(rx_rden) /*rx_read <= 1'b1*/; // If reading enabled, request another byte
else begin // of data out of the buffer, else..
//rx_read <= 1'b0; // on next clock, do not request anymore
rx_rden <= 1'b0; // block your fifo from reading
end // until ready
end
if(tx_done) begin // If enabled
THRE <= 1'b1; // Transmitter holding register is empty
end
if(IPEN && IPEND) begin // If the user has cleared the and there is not one pending
rx_rden <= 1'b1; // User has digested that byte, now enable reading some more
DR <= 1'b0; // interrupt, then clear
THRE <= 1'b0; // the flags in the Line status register
end
end
end
// --------------------------------------------------------------------
// UART Register behavior
// --------------------------------------------------------------------
always @(posedge wb_clk_i or posedge wb_rst_i) begin // Synchrounous
if(wb_rst_i) begin
dat_o <= 8'h00; // Default value
end
else
if(rd_command) begin
case(UART_Addr) // Determine which register was read
`UART_RG_TR: dat_o <= dlab ? dll : output_data;
`UART_RG_IE: dat_o <= dlab ? dlh : INTE;
`UART_RG_II: dat_o <= ISTAT; // Interupt ID
`UART_RG_LC: dat_o <= LCON; // Line control
`UART_RG_MC: dat_o <= MCON; // Modem Control Register
`UART_RG_LS: dat_o <= LSTAT; // Line status
`UART_RG_MS: dat_o <= MSTAT; // Modem Status
`UART_RG_SR: dat_o <= 8'h00; // No Scratch register
default: dat_o <= 8'h00; // Default
endcase // End of case
end
end // Synchrounous always
always @(posedge wb_clk_i or posedge wb_rst_i) begin // Synchrounous
if(wb_rst_i) begin
dll <= `UART_DL_LSB; // Set default to 9600 baud
dlh <= `UART_DL_MSB; // Set default to 9600 baud
ier <= 4'h01; // Interupt Enable default
lcr <= 8'h03; // Default value
mcr <= 8'h00; // Default value
end
else if(wr_command) begin // If a write was requested
case(UART_Addr) // Determine which register was writen to
`UART_RG_TR: if(dlab) dll <= dat_i; else input_data <= dat_i;
`UART_RG_IE: if(dlab) dlh <= dat_i; else ier <= dat_i[3:0];
`UART_RG_II: ; // Read only register
`UART_RG_LC: lcr <= dat_i; // Line Control
`UART_RG_MC: mcr <= dat_i; // Modem Control Register
`UART_RG_LS: ; // Read only register
`UART_RG_MS: ; // Read only register
`UART_RG_SR: ; // No scratch register
default: ; // Default
endcase // End of case
end
end // Synchrounous always
// --------------------------------------------------------------------
// Transmit behavior
// --------------------------------------------------------------------
always @(posedge wb_clk_i or posedge wb_rst_i) begin // Synchrounous
if(wb_rst_i) tx_send <= 1'b0; // Default value
else tx_send <= (wr_command && (UART_Addr == `UART_RG_TR) && !dlab);
end // Synchrounous always
serial_arx arx (
.clk (wb_clk_i),
.baud8tick (Baud8Tick),
.rxd (rs232_rx),
.rxd_data_ready (rx_drdy),
.rxd_data (output_data),
.rxd_endofpacket (rxd_endofpacket),
.rxd_idle (rx_idle)
);
serial_atx atx (
.clk (wb_clk_i),
.baud1tick (Baud1Tick),
.txd (rs232_tx),
.txd_start (tx_send),
.txd_data (input_data),
.txd_busy (tx_busy)
);
// --------------------------------------------------------------------
// 1.8432Mhz Baud Clock Generator:
// This module generates the standard 1.8432Mhz Baud Clock. Using this clock
// The Baud Rate Generator below can then derive all the standard
// Bauds. Make the accumulator 1 more bit for carry out than what is
// Needed. Example: Main Clock = 12.5Mhz = 12,500,000 Hence
// 1024/151 = 6.78, => 12,500,000 / 6.78 = 1,843,261.72 , .003% error, Good !
// so the accumulator should be 11 bits (log2(1024) +1
//
// --------------------------------------------------------------------
// Baud Rate Generator:
// Once we have our little 1.8432Mhz Baud Clock, deriving the bauds is
// simple simon. Just divide by 16 to get the 1x baud for transmitting
// and divide by 2 to get the 8x oversampling clock for receiving.
//
// Baud Clock = 1.8432Mhz
// Divisor = 16
//
// Baud Divsr %Error
// ------ ----- -----
// 50 2304 0.000%
// 75 1536 0.000%
// 110 1047 0.026%
// 150 768 0.000%
// 300 384 0.000%
// 600 192 0.000%
// 1200 96 0.000%
// 2400 48 0.000%
// 4800 24 0.000%
// 7200 16 0.000%
// 9600 12 0.000%
// 14400 8 0.000%
// 19200 6 0.000%
// 28800 4 0.000%
// 38400 3 0.000%
// 57600 2 0.000%
// 115200 1 0.000%
//
// --------------------------------------------------------------------
always @(posedge wb_clk_i)
BaudAcc1 <= {1'b0, BaudAcc1[17:0]} + BaudInc;
always @(posedge wb_clk_i)
BaudAcc8 <= {1'b0, BaudAcc8[14:0]} + BaudInc[15:0];
// Combinatorial logic
assign dat_i = wb_sel_i[0] ? wb_dat_i[7:0] : wb_dat_i[15:8]; // 8 to 16 bit WB
assign wb_dat_o = wb_sel_i[0] ? {8'h00, dat_o} : {dat_o, 8'h00}; // 8 to 16 bit WB
assign UART_Addr = {wb_adr_i, wb_sel_i[1]}; // Computer UART Address
assign wb_ack_i = wb_stb_i & wb_cyc_i; // Immediate ack
assign wr_command = wb_ack_i & wb_we_i; // WISHBONE write access, Singal to send
assign rd_command = wb_ack_i & ~wb_we_i; // WISHBONE write access, Singal to send
assign wb_tgc_o = ~IPEN; // If ==0 - new data has been received
assign EDAI = ier[0]; // Enable Data Available Interrupt
assign ETXH = ier[1]; // Enable Tx Holding Register Empty Interrupt
assign EMSI = ier[3]; // Enable Modem Status Interrupt
assign INTE = {4'b0000, ier};
assign ISTAT = { 5'b0000_0,INTID,IPEN};
assign TSRE = tx_done; // Tx Shift Register Empty
assign PE = 1'b0; // Parity Error
assign BI = 1'b0; // Break Interrupt, hard coded off
assign FE = to_error; // Framing Error, hard coded off
assign OR = rx_over; // Overrun Error, hard coded off
assign LSTAT = {1'b0,TSRE,THRE,BI,FE,PE,OR,DR};
assign DTR = mcr[0];
assign RTS = mcr[1];
assign OUT1 = mcr[2];
assign OUT2 = mcr[3];
assign LOOP = mcr[4];
assign MCON = {3'b000, mcr[4:0]};
assign RLSD = LOOP ? OUT2 : 1'b0; // Received Line Signal Detect
assign RI = LOOP ? OUT1 : 1'b1; // Ring Indicator
assign DSR = LOOP ? DTR : 1'b0; // Data Set Ready
assign CTS = LOOP ? RTS : 1'b0; // Clear To Send
assign DRLSD = 1'b0; // Delta Rx Line Signal Detect
assign TERI = 1'b0; // Trailing Edge Ring Indicator
assign DDSR = 1'b0; // Delta Data Set Ready
assign DCTS = 1'b0; // Delta Clear to Send
assign MSTAT = {RLSD,RI,DSR,CTS,DCTS,DDSR,TERI,DRLSD};
assign LCON = lcr; // Data Latch Address Bit
assign dlab = lcr[7]; // Data Latch Address Bit
assign tx_done = ~tx_busy; // Signal command finished sending
assign rx_over = 1'b0;
assign to_error = 1'b0;
assign Baudiv = {3'b000,dlh,dll};
assign Baud1Tick = BaudAcc1[18];
assign BaudInc = 19'd2416/Baudiv;
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
* adjusted to FML 8x16 by Charley Picker <[email protected]>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module fmlarb #(
\tparameter fml_depth = 26
) (
\tinput sys_clk,
\tinput sys_rst,
\t
\t/* Interface 0 has higher priority than the others */
\tinput [fml_depth-1:0] m0_adr,
\tinput m0_stb,
\tinput m0_we,
\toutput m0_ack,
\tinput [1:0] m0_sel,
\tinput [15:0] m0_di,
\toutput [15:0] m0_do,
\t
\tinput [fml_depth-1:0] m1_adr,
\tinput m1_stb,
\tinput m1_we,
\toutput m1_ack,
\tinput [1:0] m1_sel,
\tinput [15:0] m1_di,
\toutput [15:0] m1_do,
\t
\tinput [fml_depth-1:0] m2_adr,
\tinput m2_stb,
\tinput m2_we,
\toutput m2_ack,
\tinput [1:0] m2_sel,
\tinput [15:0] m2_di,
\toutput [15:0] m2_do,
\t
\tinput [fml_depth-1:0] m3_adr,
\tinput m3_stb,
\tinput m3_we,
\toutput m3_ack,
\tinput [1:0] m3_sel,
\tinput [15:0] m3_di,
\toutput [15:0] m3_do,
\tinput [fml_depth-1:0] m4_adr,
\tinput m4_stb,
\tinput m4_we,
\toutput m4_ack,
\tinput [1:0] m4_sel,
\tinput [15:0] m4_di,
\toutput [15:0] m4_do,
\tinput [fml_depth-1:0] m5_adr,
\tinput m5_stb,
\tinput m5_we,
\toutput m5_ack,
\tinput [1:0] m5_sel,
\tinput [15:0] m5_di,
\toutput [15:0] m5_do,
\t
\toutput reg [fml_depth-1:0] s_adr,
\toutput reg s_stb,
\toutput reg s_we,
\tinput s_ack,
\toutput reg [1:0] s_sel,
\tinput [15:0] s_di,
\toutput reg [15:0] s_do
);
assign m0_do = s_di;
assign m1_do = s_di;
assign m2_do = s_di;
assign m3_do = s_di;
assign m4_do = s_di;
assign m5_do = s_di;
reg [2:0] master;
reg [2:0] next_master;
always @(posedge sys_clk) begin
\tif(sys_rst)
\t\tmaster <= 3'd0;
\telse
\t\tmaster <= next_master;
end
/* Decide the next master */
always @(*) begin
\t/* By default keep our current master */
\tnext_master = master;
\t
\tcase(master)
\t\t3'd0: if(~m0_stb | s_ack) begin
\t\t\tif(m1_stb) next_master = 3'd1;
\t\t\telse if(m2_stb) next_master = 3'd2;
\t\t\telse if(m3_stb) next_master = 3'd3;
\t\t\telse if(m4_stb) next_master = 3'd4;
\t\t\telse if(m5_stb) next_master = 3'd5;
\t\tend
\t\t3'd1: if(~m1_stb | s_ack) begin
\t\t\tif(m0_stb) next_master = 3'd0;
\t\t\telse if(m3_stb) next_master = 3'd3;
\t\t\telse if(m4_stb) next_master = 3'd4;
\t\t\telse if(m5_stb) next_master = 3'd5;
\t\t\telse if(m2_stb) next_master = 3'd2;
\t\tend
\t\t3'd2: if(~m2_stb | s_ack) begin
\t\t\tif(m0_stb) next_master = 3'd0;
\t\t\telse if(m3_stb) next_master = 3'd3;
\t\t\telse if(m4_stb) next_master = 3'd4;
\t\t\telse if(m5_stb) next_master = 3'd5;
\t\t\telse if(m1_stb) next_master = 3'd1;
\t\tend
\t\t3'd3: if(~m3_stb | s_ack) begin
\t\t\tif(m0_stb) next_master = 3'd0;
\t\t\telse if(m4_stb) next_master = 3'd4;
\t\t\telse if(m5_stb) next_master = 3'd5;
\t\t\telse if(m1_stb) next_master = 3'd1;
\t\t\telse if(m2_stb) next_master = 3'd2;
\t\tend
\t\t3'd4: if(~m4_stb | s_ack) begin
\t\t\tif(m0_stb) next_master = 3'd0;
\t\t\telse if(m5_stb) next_master = 3'd5;
\t\t\telse if(m1_stb) next_master = 3'd1;
\t\t\telse if(m2_stb) next_master = 3'd2;
\t\t\telse if(m3_stb) next_master = 3'd3;
\t\tend
\t\tdefault: if(~m5_stb | s_ack) begin // 3'd5
\t\t\tif(m0_stb) next_master = 3'd0;
\t\t\telse if(m1_stb) next_master = 3'd1;
\t\t\telse if(m2_stb) next_master = 3'd2;
\t\t\telse if(m3_stb) next_master = 3'd3;
\t\t\telse if(m4_stb) next_master = 3'd4;
\t\tend
\tendcase
end
/* Generate ack signals */
assign m0_ack = (master == 3'd0) & s_ack;
assign m1_ack = (master == 3'd1) & s_ack;
assign m2_ack = (master == 3'd2) & s_ack;
assign m3_ack = (master == 3'd3) & s_ack;
assign m4_ack = (master == 3'd4) & s_ack;
assign m5_ack = (master == 3'd5) & s_ack;
/* Mux control signals */
always @(*) begin
\tcase(master)
\t\t3'd0: begin
\t\t\ts_adr = m0_adr;
\t\t\ts_stb = m0_stb;
\t\t\ts_we = m0_we;
\t\tend
\t\t3'd1: begin
\t\t\ts_adr = m1_adr;
\t\t\ts_stb = m1_stb;
\t\t\ts_we = m1_we;
\t\tend
\t\t3'd2: begin
\t\t\ts_adr = m2_adr;
\t\t\ts_stb = m2_stb;
\t\t\ts_we = m2_we;
\t\tend
\t\t3'd3: begin
\t\t\ts_adr = m3_adr;
\t\t\ts_stb = m3_stb;
\t\t\ts_we = m3_we;
\t\tend
\t\t3'd4: begin
\t\t\ts_adr = m4_adr;
\t\t\ts_stb = m4_stb;
\t\t\ts_we = m4_we;
\t\tend
\t\tdefault: begin // 3'd5
\t\t\ts_adr = m5_adr;
\t\t\ts_stb = m5_stb;
\t\t\ts_we = m5_we;
\t\tend
\tendcase
end
/* Mux data write signals */
wire write_burst_start = s_we & s_ack;
reg [2:0] wmaster;
reg [2:0] burst_counter;
always @(posedge sys_clk) begin
\tif(sys_rst) begin
\t\twmaster <= 3'd0;
\t\tburst_counter <= 3'd0;
\tend else begin
\t\tif(|burst_counter)
\t\t\tburst_counter <= burst_counter - 3'd1;
\t\tif(write_burst_start)
\t\t\tburst_counter <= 3'd6;
\t\tif(~write_burst_start & ~(|burst_counter))
\t\t\twmaster <= next_master;
\tend
end
always @(*) begin
\tcase(wmaster)
\t\t3'd0: begin
\t\t\ts_do = m0_di;
\t\t\ts_sel = m0_sel;
\t\tend
\t\t3'd1: begin
\t\t\ts_do = m1_di;
\t\t\ts_sel = m1_sel;
\t\tend
\t\t3'd2: begin
\t\t\ts_do = m2_di;
\t\t\ts_sel = m2_sel;
\t\tend
\t\t3'd3: begin
\t\t\ts_do = m3_di;
\t\t\ts_sel = m3_sel;
\t\tend
\t\t3'd4: begin
\t\t\ts_do = m4_di;
\t\t\ts_sel = m4_sel;
\t\tend
\t\tdefault: begin // 3'd5
\t\t\ts_do = m5_di;
\t\t\ts_sel = m5_sel;
\t\tend
\tendcase
end
endmodule
|
/*
* Decoder for x86 memory access registers
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_memory_regs (
input [2:0] rm,
input [1:0] mod,
input [2:0] sovr_pr,
output reg [3:0] base,
output reg [3:0] index,
output [1:0] seg
);
// Register declaration
reg [1:0] s;
// Continuous assignments
assign seg = sovr_pr[2] ? sovr_pr[1:0] : s;
// Behaviour
always @(rm or mod)
case (rm)
3'b000: begin base <= 4'b0011; index <= 4'b0110; s <= 2'b11; end
3'b001: begin base <= 4'b0011; index <= 4'b0111; s <= 2'b11; end
3'b010: begin base <= 4'b0101; index <= 4'b0110; s <= 2'b10; end
3'b011: begin base <= 4'b0101; index <= 4'b0111; s <= 2'b10; end
3'b100: begin base <= 4'b1100; index <= 4'b0110; s <= 2'b11; end
3'b101: begin base <= 4'b1100; index <= 4'b0111; s <= 2'b11; end
3'b110: begin base <= mod ? 4'b0101 : 4'b1100; index <= 4'b1100;
s <= mod ? 2'b10 : 2'b11; end
3'b111: begin base <= 4'b0011; index <= 4'b1100; s <= 2'b11; end
endcase
endmodule
|
/*
* Memory interface for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga_cpu_mem_iface (
// Wishbone common signals
input wb_clk_i,
input wb_rst_i,
// Wishbone slave interface
input [16:1] wbs_adr_i,
input [ 1:0] wbs_sel_i,
input wbs_we_i,
input [15:0] wbs_dat_i,
output [15:0] wbs_dat_o,
input wbs_stb_i,
output wbs_ack_o,
// Wishbone master to SRAM
output [17:1] wbm_adr_o,
output [ 1:0] wbm_sel_o,
output wbm_we_o,
output [15:0] wbm_dat_o,
input [15:0] wbm_dat_i,
output wbm_stb_o,
input wbm_ack_i,
// VGA configuration registers
input chain_four,
input memory_mapping1,
input [ 1:0] write_mode,
input [ 1:0] raster_op,
input read_mode,
input [ 7:0] bitmask,
input [ 3:0] set_reset,
input [ 3:0] enable_set_reset,
input [ 3:0] map_mask,
input [ 1:0] read_map_select,
input [ 3:0] color_compare,
input [ 3:0] color_dont_care
);
// Registers and nets
wire read_stb;
wire write_stb;
wire rd_wbs_ack_o;
wire [15:0] rd_wbs_dat_o;
wire wr_wbs_ack_o;
wire [17:1] rd_wbm_adr_o;
wire [17:1] wr_wbm_adr_o;
wire rd_wbm_stb_o;
wire wr_wbm_stb_o;
wire rd_wbm_ack_i;
wire [ 1:0] wr_wbm_sel_o;
wire [15:0] wr_wbm_dat_o;
wire wr_wbm_ack_i;
wire [15:0] wbs_dat_o_c;
wire wbs_stb_i_c;
wire wbs_ack_o_c;
wire [17:1] wbm_adr_o_c;
wire [ 1:0] wbm_sel_o_c;
wire wbm_we_o_c;
wire [15:0] wbm_dat_o_c;
wire wbm_stb_o_c;
wire wbm_ack_i_c;
wire [7:0] latch0, latch1, latch2, latch3;
// Module instances
vga_read_iface read_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wbs_adr_i),
.wbs_sel_i (wbs_sel_i),
.wbs_dat_o (rd_wbs_dat_o),
.wbs_stb_i (read_stb),
.wbs_ack_o (rd_wbs_ack_o),
.wbm_adr_o (rd_wbm_adr_o),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (rd_wbm_stb_o),
.wbm_ack_i (rd_wbm_ack_i),
.memory_mapping1 (memory_mapping1),
.read_mode (read_mode),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care),
.latch0 (latch0),
.latch1 (latch1),
.latch2 (latch2),
.latch3 (latch3)
);
vga_write_iface write_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wbs_adr_i),
.wbs_sel_i (wbs_sel_i),
.wbs_dat_i (wbs_dat_i),
.wbs_stb_i (write_stb),
.wbs_ack_o (wr_wbs_ack_o),
.wbm_adr_o (wr_wbm_adr_o),
.wbm_sel_o (wr_wbm_sel_o),
.wbm_dat_o (wr_wbm_dat_o),
.wbm_stb_o (wr_wbm_stb_o),
.wbm_ack_i (wr_wbm_ack_i),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.latch0 (latch0),
.latch1 (latch1),
.latch2 (latch2),
.latch3 (latch3)
);
vga_c4_iface c4_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wbs_adr_i),
.wbs_sel_i (wbs_sel_i),
.wbs_we_i (wbs_we_i),
.wbs_dat_i (wbs_dat_i),
.wbs_dat_o (wbs_dat_o_c),
.wbs_stb_i (wbs_stb_i_c),
.wbs_ack_o (wbs_ack_o_c),
.wbm_adr_o (wbm_adr_o_c),
.wbm_sel_o (wbm_sel_o_c),
.wbm_we_o (wbm_we_o_c),
.wbm_dat_o (wbm_dat_o_c),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (wbm_stb_o_c),
.wbm_ack_i (wbm_ack_i_c)
);
// Continuous assignments
assign read_stb = wbs_stb_i & !wbs_we_i & !chain_four;
assign write_stb = wbs_stb_i & wbs_we_i & !chain_four;
assign rd_wbm_ack_i = !wbs_we_i & wbm_ack_i & !chain_four;
assign wr_wbm_ack_i = wbs_we_i & wbm_ack_i & !chain_four;
assign wbs_ack_o = chain_four ? wbs_ack_o_c
: (wbs_we_i ? wr_wbs_ack_o : rd_wbs_ack_o);
assign wbs_dat_o = chain_four ? wbs_dat_o_c : rd_wbs_dat_o;
assign wbm_adr_o = chain_four ? wbm_adr_o_c
: (wbs_we_i ? wr_wbm_adr_o : rd_wbm_adr_o);
assign wbm_stb_o = chain_four ? wbm_stb_o_c
: (wbs_we_i ? wr_wbm_stb_o : rd_wbm_stb_o);
assign wbm_sel_o = chain_four ? wbm_sel_o_c : wr_wbm_sel_o;
assign wbm_dat_o = chain_four ? wbm_dat_o_c : wr_wbm_dat_o;
assign wbm_we_o = chain_four & wbm_we_o_c
| !chain_four & wbs_we_i;
assign wbs_stb_i_c = chain_four & wbs_stb_i;
assign wbm_ack_i_c = chain_four & wbm_ack_i;
endmodule
|
/*
* Altera Quartus II multiplier inference module
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_signmul17 (
input clk,
input signed [16:0] a,
input signed [16:0] b,
output reg signed [33:0] p
);
// Behaviour
always @(posedge clk) p <= a * b;
endmodule
|
/*
* Phase accumulator clock generator:
* Output Frequency Fo = Fc * N / 2^bits
* Output Jitter = 1/Fc
*
* Copyright (c) 2009,2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module clk_gen #(
parameter res = 20, // bits - bit resolution
parameter phase = 1 // N - phase value for the counter
)(
input clk_i, // Fc - input frequency
input rst_i,
output clk_o // Fo - output frequency
);
// Registers and nets
reg [res-1:0] cnt;
// Continuous assignments
assign clk_o = cnt[res-1];
// Behaviour
always @(posedge clk_i)
cnt <= rst_i ? {res{1'b0}} : (cnt + phase);
endmodule
|
/*
* 16-bit bitwise rotate module for Zet
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_rxr16 (
input [15:0] x,
input ci,
input [ 4:0] y,
input e,
output reg [15:0] w,
output reg co
);
always @(x or ci or y or e)
case (y)
default: {co,w} <= {ci,x};
5'd01: {co,w} <= e ? {x[0], ci, x[15:1]} : {ci, x[0], x[15:1]};
5'd02: {co,w} <= e ? {x[ 1:0], ci, x[15: 2]} : {ci, x[ 1:0], x[15: 2]};
5'd03: {co,w} <= e ? {x[ 2:0], ci, x[15: 3]} : {ci, x[ 2:0], x[15: 3]};
5'd04: {co,w} <= e ? {x[ 3:0], ci, x[15: 4]} : {ci, x[ 3:0], x[15: 4]};
5'd05: {co,w} <= e ? {x[ 4:0], ci, x[15: 5]} : {ci, x[ 4:0], x[15: 5]};
5'd06: {co,w} <= e ? {x[ 5:0], ci, x[15: 6]} : {ci, x[ 5:0], x[15: 6]};
5'd07: {co,w} <= e ? {x[ 6:0], ci, x[15: 7]} : {ci, x[ 6:0], x[15: 7]};
5'd08: {co,w} <= e ? {x[ 7:0], ci, x[15: 8]} : {ci, x[ 7:0], x[15: 8]};
5'd09: {co,w} <= e ? {x[ 8:0], ci, x[15: 9]} : {ci, x[ 8:0], x[15: 9]};
5'd10: {co,w} <= e ? {x[ 9:0], ci, x[15:10]} : {ci, x[ 9:0], x[15:10]};
5'd11: {co,w} <= e ? {x[10:0], ci, x[15:11]} : {ci, x[10:0], x[15:11]};
5'd12: {co,w} <= e ? {x[11:0], ci, x[15:12]} : {ci, x[11:0], x[15:12]};
5'd13: {co,w} <= e ? {x[12:0], ci, x[15:13]} : {ci, x[12:0], x[15:13]};
5'd14: {co,w} <= e ? {x[13:0], ci, x[15:14]} : {ci, x[13:0], x[15:14]};
5'd15: {co,w} <= e ? {x[14:0], ci, x[15]} : {ci, x[14:0], x[15]};
5'd16: {co,w} <= {x,ci};
endcase
endmodule
|
/*
* Linear mode graphics for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga_linear (
input clk,
input rst,
// CSR slave interface for reading
output [17:1] csr_adr_o,
input [15:0] csr_dat_i,
output csr_stb_o,
input [9:0] h_count,
input [9:0] v_count,
input horiz_sync_i,
input video_on_h_i,
output video_on_h_o,
output [7:0] color,
output horiz_sync_o
);
// Registers
reg [ 9:0] row_addr;
reg [ 6:0] col_addr;
reg [14:1] word_offset;
reg [ 1:0] plane_addr;
reg [ 1:0] plane_addr0;
reg [ 7:0] color_l;
reg [4:0] video_on_h;
reg [4:0] horiz_sync;
reg [5:0] pipe;
reg [15:0] word_color;
// Continous assignments
assign csr_adr_o = { word_offset, plane_addr, 1'b0 };
assign csr_stb_o = pipe[1];
assign color = pipe[4] ? csr_dat_i[7:0] : color_l;
assign video_on_h_o = video_on_h[4];
assign horiz_sync_o = horiz_sync[4];
// Behaviour
// Pipeline count
always @(posedge clk)
pipe <= rst ? 6'b0 : { pipe[4:0], ~h_count[0] };
// video_on_h
always @(posedge clk)
video_on_h <= rst ? 5'b0 : { video_on_h[3:0], video_on_h_i };
// horiz_sync
always @(posedge clk)
horiz_sync <= rst ? 5'b0 : { horiz_sync[3:0], horiz_sync_i };
// Address generation
always @(posedge clk)
if (rst)
begin
row_addr <= 10'h0;
col_addr <= 7'h0;
plane_addr0 <= 2'b00;
word_offset <= 14'h0;
plane_addr <= 2'b00;
end
else
begin
// Loading new row_addr and col_addr when h_count[3:0]==4'h0
// v_count * 5 * 32
row_addr <= { v_count[8:1], 2'b00 } + v_count[8:1];
col_addr <= h_count[9:3];
plane_addr0 <= h_count[2:1];
word_offset <= { row_addr + col_addr[6:4], col_addr[3:0] };
plane_addr <= plane_addr0;
end
// color_l
always @(posedge clk)
color_l <= rst ? 8'h0 : (pipe[4] ? csr_dat_i[7:0] : color_l);
endmodule
|
/*
* Wishbone switch and address decoder
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
* Copyright (C) 2008, 2009 Sebastien Bourdeauducq - http://lekernel.net
* Copyright (C) 2000 Johny Chi - [email protected]
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module wb_switch #(
parameter s0_addr_1 = 20'h00000, // Default Values
parameter s0_mask_1 = 20'h00000,
parameter s1_addr_1 = 20'h00000,
parameter s1_mask_1 = 20'h00000,
parameter s1_addr_2 = 20'h00000,
parameter s1_mask_2 = 20'h00000,
parameter s2_addr_1 = 20'h00000,
parameter s2_mask_1 = 20'h00000,
parameter s3_addr_1 = 20'h00000,
parameter s3_mask_1 = 20'h00000,
parameter s4_addr_1 = 20'h00000,
parameter s4_mask_1 = 20'h00000,
parameter s5_addr_1 = 20'h00000,
parameter s5_mask_1 = 20'h00000,
parameter s6_addr_1 = 20'h00000,
parameter s6_mask_1 = 20'h00000,
parameter s7_addr_1 = 20'h00000,
parameter s7_mask_1 = 20'h00000,
parameter s8_addr_1 = 20'h00000,
parameter s8_mask_1 = 20'h00000,
parameter s9_addr_1 = 20'h00000,
parameter s9_mask_1 = 20'h00000,
parameter sA_addr_1 = 20'h00000,
parameter sA_mask_1 = 20'h00000,
parameter sA_addr_2 = 20'h00000,
parameter sA_mask_2 = 20'h00000
)(
// Master interface
input [15:0] m_dat_i,
output [15:0] m_dat_o,
input [20:1] m_adr_i,
input [ 1:0] m_sel_i,
input m_we_i,
input m_cyc_i,
input m_stb_i,
output m_ack_o,
// Slave 0 interface
input [15:0] s0_dat_i,
output [15:0] s0_dat_o,
output [20:1] s0_adr_o,
output [ 1:0] s0_sel_o,
output s0_we_o,
output s0_cyc_o,
output s0_stb_o,
input s0_ack_i,
// Slave 1 interface
input [15:0] s1_dat_i,
output [15:0] s1_dat_o,
output [20:1] s1_adr_o,
output [ 1:0] s1_sel_o,
output s1_we_o,
output s1_cyc_o,
output s1_stb_o,
input s1_ack_i,
// Slave 2 interface
input [15:0] s2_dat_i,
output [15:0] s2_dat_o,
output [20:1] s2_adr_o,
output [ 1:0] s2_sel_o,
output s2_we_o,
output s2_cyc_o,
output s2_stb_o,
input s2_ack_i,
// Slave 3 interface
input [15:0] s3_dat_i,
output [15:0] s3_dat_o,
output [20:1] s3_adr_o,
output [ 1:0] s3_sel_o,
output s3_we_o,
output s3_cyc_o,
output s3_stb_o,
input s3_ack_i,
// Slave 4 interface
input [15:0] s4_dat_i,
output [15:0] s4_dat_o,
output [20:1] s4_adr_o,
output [ 1:0] s4_sel_o,
output s4_we_o,
output s4_cyc_o,
output s4_stb_o,
input s4_ack_i,
// Slave 5 interface
input [15:0] s5_dat_i,
output [15:0] s5_dat_o,
output [20:1] s5_adr_o,
output [ 1:0] s5_sel_o,
output s5_we_o,
output s5_cyc_o,
output s5_stb_o,
input s5_ack_i,
// Slave 6 interface
input [15:0] s6_dat_i,
output [15:0] s6_dat_o,
output [20:1] s6_adr_o,
output [ 1:0] s6_sel_o,
output s6_we_o,
output s6_cyc_o,
output s6_stb_o,
input s6_ack_i,
// Slave 7 interface
input [15:0] s7_dat_i,
output [15:0] s7_dat_o,
output [20:1] s7_adr_o,
output [ 1:0] s7_sel_o,
output s7_we_o,
output s7_cyc_o,
output s7_stb_o,
input s7_ack_i,
// Slave 8 interface
input [15:0] s8_dat_i,
output [15:0] s8_dat_o,
output [20:1] s8_adr_o,
output [ 1:0] s8_sel_o,
output s8_we_o,
output s8_cyc_o,
output s8_stb_o,
input s8_ack_i,
// Slave 9 interface
input [15:0] s9_dat_i,
output [15:0] s9_dat_o,
output [20:1] s9_adr_o,
output [ 1:0] s9_sel_o,
output s9_we_o,
output s9_cyc_o,
output s9_stb_o,
input s9_ack_i,
// Slave A interface - masked default
input [15:0] sA_dat_i,
output [15:0] sA_dat_o,
output [20:1] sA_adr_o,
output [ 1:0] sA_sel_o,
output sA_we_o,
output sA_cyc_o,
output sA_stb_o,
input sA_ack_i,
// Slave B interface - default
input [15:0] sB_dat_i,
output [15:0] sB_dat_o,
output [20:1] sB_adr_o,
output [ 1:0] sB_sel_o,
output sB_we_o,
output sB_cyc_o,
output sB_stb_o,
input sB_ack_i
);
`define mbusw_ls 20 + 2 + 16 + 1 + 1 + 1 // address + byte select + data + cyc + we + stb
wire [11:0] slave_sel;
wire [15:0] i_dat_s; // internal shared bus, slave data to master
wire i_bus_ack; // internal shared bus, ack signal
wire [`mbusw_ls -1:0] i_bus_m; // internal shared bus, master data and control to slave
assign m_dat_o = i_dat_s;
assign m_ack_o = i_bus_ack;
// Bus Acknowlegement
assign i_bus_ack = s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i | s6_ack_i |
s7_ack_i | s8_ack_i | s9_ack_i | sA_ack_i | sB_ack_i;
assign i_dat_s = ({16{slave_sel[ 0]}} & s0_dat_i)
|({16{slave_sel[ 1]}} & s1_dat_i)
|({16{slave_sel[ 2]}} & s2_dat_i)
|({16{slave_sel[ 3]}} & s3_dat_i)
|({16{slave_sel[ 4]}} & s4_dat_i)
|({16{slave_sel[ 5]}} & s5_dat_i)
|({16{slave_sel[ 6]}} & s6_dat_i)
|({16{slave_sel[ 7]}} & s7_dat_i)
|({16{slave_sel[ 8]}} & s8_dat_i)
|({16{slave_sel[ 9]}} & s9_dat_i)
|({16{slave_sel[10]}} & sA_dat_i)
|({16{slave_sel[11]}} & sB_dat_i)
;
// Bus Selection logic
assign slave_sel[ 0] = ((m_adr_i & s0_mask_1) == s0_addr_1);
assign slave_sel[ 1] = ((m_adr_i & s1_mask_1) == s1_addr_1) | ((m_adr_i & s1_mask_2) == s1_addr_2);
assign slave_sel[ 2] = ((m_adr_i & s2_mask_1) == s2_addr_1);
assign slave_sel[ 3] = ((m_adr_i & s3_mask_1) == s3_addr_1);
assign slave_sel[ 4] = ((m_adr_i & s4_mask_1) == s4_addr_1);
assign slave_sel[ 5] = ((m_adr_i & s5_mask_1) == s5_addr_1);
assign slave_sel[ 6] = ((m_adr_i & s6_mask_1) == s6_addr_1);
assign slave_sel[ 7] = ((m_adr_i & s7_mask_1) == s7_addr_1);
assign slave_sel[ 8] = ((m_adr_i & s8_mask_1) == s8_addr_1);
assign slave_sel[ 9] = ((m_adr_i & s9_mask_1) == s9_addr_1);
assign slave_sel[10] = (((m_adr_i & sA_mask_1) == sA_addr_1) | (( m_adr_i & sA_mask_2)== sA_addr_2)) & ~(|slave_sel[9:0]);
assign slave_sel[11] = ~(|slave_sel[10:0]);
assign i_bus_m = {m_adr_i, m_sel_i, m_dat_i, m_we_i, m_cyc_i, m_stb_i};
assign {s0_adr_o, s0_sel_o, s0_dat_o, s0_we_o, s0_cyc_o} = i_bus_m[`mbusw_ls -1:1]; // slave 0
assign s0_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[0]; // stb_o = cyc_i & stb_i & slave_sel
assign {s1_adr_o, s1_sel_o, s1_dat_o, s1_we_o, s1_cyc_o} = i_bus_m[`mbusw_ls -1:1]; // slave 1
assign s1_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[1];
assign {s2_adr_o, s2_sel_o, s2_dat_o, s2_we_o, s2_cyc_o} = i_bus_m[`mbusw_ls -1:1]; // slave 2
assign s2_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[2];
assign {s3_adr_o, s3_sel_o, s3_dat_o, s3_we_o, s3_cyc_o} = i_bus_m[`mbusw_ls -1:1]; // slave 3
assign s3_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[3];
assign {s4_adr_o, s4_sel_o, s4_dat_o, s4_we_o, s4_cyc_o} = i_bus_m[`mbusw_ls -1:1]; // slave 4
assign s4_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[4];
assign {s5_adr_o, s5_sel_o, s5_dat_o, s5_we_o, s5_cyc_o} = i_bus_m[`mbusw_ls -1:1]; // slave 5
assign s5_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[5];
assign {s6_adr_o, s6_sel_o, s6_dat_o, s6_we_o, s6_cyc_o} = i_bus_m[`mbusw_ls -1:1]; // slave 6
assign s6_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[6];
assign {s7_adr_o, s7_sel_o, s7_dat_o, s7_we_o, s7_cyc_o} = i_bus_m[`mbusw_ls -1:1]; // slave 7
assign s7_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[7];
assign {s8_adr_o, s8_sel_o, s8_dat_o, s8_we_o, s8_cyc_o} = i_bus_m[`mbusw_ls -1:1]; // slave 8
assign s8_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[8];
assign {s9_adr_o, s9_sel_o, s9_dat_o, s9_we_o, s9_cyc_o} = i_bus_m[`mbusw_ls -1:1]; // slave 9
assign s9_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[9];
assign {sA_adr_o, sA_sel_o, sA_dat_o, sA_we_o, sA_cyc_o} = i_bus_m[`mbusw_ls -1:1]; // slave A
assign sA_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[10];
assign {sB_adr_o, sB_sel_o, sB_dat_o, sB_we_o, sB_cyc_o} = i_bus_m[`mbusw_ls -1:1]; // slave B
assign sB_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[11];
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// \t\t\taltpll
//
// Simulation Library Files(s):
// \t\t\taltera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation\'s design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
\tinclk0,
\tc0,
\tc2,
\tlocked);
\tinput\t inclk0;
\toutput\t c0;
\toutput\t c2;
\toutput\t locked;
\twire sub_wire0;
\twire [5:0] sub_wire1;
\twire [0:0] sub_wire6 = 1\'h0;
\twire locked = sub_wire0;
\twire [2:2] sub_wire3 = sub_wire1[2:2];
\twire [0:0] sub_wire2 = sub_wire1[0:0];
\twire c0 = sub_wire2;
\twire c2 = sub_wire3;
\twire sub_wire4 = inclk0;
\twire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
\taltpll\taltpll_component (
\t\t\t\t.inclk (sub_wire5),
\t\t\t\t.locked (sub_wire0),
\t\t\t\t.clk (sub_wire1),
\t\t\t\t.activeclock (),
\t\t\t\t.areset (1\'b0),
\t\t\t\t.clkbad (),
\t\t\t\t.clkena ({6{1\'b1}}),
\t\t\t\t.clkloss (),
\t\t\t\t.clkswitch (1\'b0),
\t\t\t\t.configupdate (1\'b0),
\t\t\t\t.enable0 (),
\t\t\t\t.enable1 (),
\t\t\t\t.extclk (),
\t\t\t\t.extclkena ({4{1\'b1}}),
\t\t\t\t.fbin (1\'b1),
\t\t\t\t.fbmimicbidir (),
\t\t\t\t.fbout (),
\t\t\t\t.fref (),
\t\t\t\t.icdrclk (),
\t\t\t\t.pfdena (1\'b1),
\t\t\t\t.phasecounterselect ({4{1\'b1}}),
\t\t\t\t.phasedone (),
\t\t\t\t.phasestep (1\'b1),
\t\t\t\t.phaseupdown (1\'b1),
\t\t\t\t.pllena (1\'b1),
\t\t\t\t.scanaclr (1\'b0),
\t\t\t\t.scanclk (1\'b0),
\t\t\t\t.scanclkena (1\'b1),
\t\t\t\t.scandata (1\'b0),
\t\t\t\t.scandataout (),
\t\t\t\t.scandone (),
\t\t\t\t.scanread (1\'b0),
\t\t\t\t.scanwrite (1\'b0),
\t\t\t\t.sclkout0 (),
\t\t\t\t.sclkout1 (),
\t\t\t\t.vcooverrange (),
\t\t\t\t.vcounderrange ());
\tdefparam
\t\taltpll_component.clk0_divide_by = 1,
\t\taltpll_component.clk0_duty_cycle = 50,
\t\taltpll_component.clk0_multiply_by = 2,
\t\taltpll_component.clk0_phase_shift = "-2917",
\t\taltpll_component.clk2_divide_by = 4,
\t\taltpll_component.clk2_duty_cycle = 50,
\t\taltpll_component.clk2_multiply_by = 1,
\t\taltpll_component.clk2_phase_shift = "0",
\t\taltpll_component.compensate_clock = "CLK0",
\t\taltpll_component.gate_lock_counter = 1048575,
\t\taltpll_component.gate_lock_signal = "YES",
\t\taltpll_component.inclk0_input_frequency = 20000,
\t\taltpll_component.intended_device_family = "Cyclone II",
\t\taltpll_component.invalid_lock_multiplier = 5,
\t\taltpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
\t\taltpll_component.lpm_type = "altpll",
\t\taltpll_component.operation_mode = "NORMAL",
\t\taltpll_component.port_activeclock = "PORT_UNUSED",
\t\taltpll_component.port_areset = "PORT_UNUSED",
\t\taltpll_component.port_clkbad0 = "PORT_UNUSED",
\t\taltpll_component.port_clkbad1 = "PORT_UNUSED",
\t\taltpll_component.port_clkloss = "PORT_UNUSED",
\t\taltpll_component.port_clkswitch = "PORT_UNUSED",
\t\taltpll_component.port_configupdate = "PORT_UNUSED",
\t\taltpll_component.port_fbin = "PORT_UNUSED",
\t\taltpll_component.port_inclk0 = "PORT_USED",
\t\taltpll_component.port_inclk1 = "PORT_UNUSED",
\t\taltpll_component.port_locked = "PORT_USED",
\t\taltpll_component.port_pfdena = "PORT_UNUSED",
\t\taltpll_component.port_phasecounterselect = "PORT_UNUSED",
\t\taltpll_component.port_phasedone = "PORT_UNUSED",
\t\taltpll_component.port_phasestep = "PORT_UNUSED",
\t\taltpll_component.port_phaseupdown = "PORT_UNUSED",
\t\taltpll_component.port_pllena = "PORT_UNUSED",
\t\taltpll_component.port_scanaclr = "PORT_UNUSED",
\t\taltpll_component.port_scanclk = "PORT_UNUSED",
\t\taltpll_component.port_scanclkena = "PORT_UNUSED",
\t\taltpll_component.port_scandata = "PORT_UNUSED",
\t\taltpll_component.port_scandataout = "PORT_UNUSED",
\t\taltpll_component.port_scandone = "PORT_UNUSED",
\t\taltpll_component.port_scanread = "PORT_UNUSED",
\t\taltpll_component.port_scanwrite = "PORT_UNUSED",
\t\taltpll_component.port_clk0 = "PORT_USED",
\t\taltpll_component.port_clk1 = "PORT_UNUSED",
\t\taltpll_component.port_clk2 = "PORT_USED",
\t\taltpll_component.port_clk3 = "PORT_UNUSED",
\t\taltpll_component.port_clk4 = "PORT_UNUSED",
\t\taltpll_component.port_clk5 = "PORT_UNUSED",
\t\taltpll_component.port_clkena0 = "PORT_UNUSED",
\t\taltpll_component.port_clkena1 = "PORT_UNUSED",
\t\taltpll_component.port_clkena2 = "PORT_UNUSED",
\t\taltpll_component.port_clkena3 = "PORT_UNUSED",
\t\taltpll_component.port_clkena4 = "PORT_UNUSED",
\t\taltpll_component.port_clkena5 = "PORT_UNUSED",
\t\taltpll_component.port_extclk0 = "PORT_UNUSED",
\t\taltpll_component.port_extclk1 = "PORT_UNUSED",
\t\taltpll_component.port_extclk2 = "PORT_UNUSED",
\t\taltpll_component.port_extclk3 = "PORT_UNUSED",
\t\taltpll_component.valid_lock_multiplier = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "4"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.500000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "10000000.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-2.91666700"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-2917"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "4"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: GATE_LOCK_COUNTER NUMERIC "1048575"
// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "YES"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/*\r
* VGA top level file\r
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>\r
*\r
* VGA FML support\r
* Copyright (C) 2013 Charley Picker <[email protected]>\r
*\r
* This file is part of the Zet processor. This processor is free\r
* hardware; you can redistribute it and/or modify it under the terms of\r
* the GNU General Public License as published by the Free Software\r
* Foundation; either version 3, or (at your option) any later version.\r
*\r
* Zet is distrubuted in the hope that it will be useful, but WITHOUT\r
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public\r
* License for more details.\r
*\r
* You should have received a copy of the GNU General Public License\r
* along with Zet; see the file COPYING. If not, see\r
* <http://www.gnu.org/licenses/>.\r
*/\r
\r
module vga_fml #(\r
parameter fml_depth = 20 // 1MB Video Memory\r
) (\r
// Wishbone signals\r
input wb_clk_i, // 100 Mhz VDU clock\r
input wb_rst_i,\r
input [15:0] wb_dat_i,\r
output [15:0] wb_dat_o,\r
input [16:1] wb_adr_i,\r
input wb_we_i,\r
input wb_tga_i,\r
input [ 1:0] wb_sel_i,\r
input wb_stb_i,\r
input wb_cyc_i,\r
output wb_ack_o,\r
\r
// VGA pad signals\r
output [ 3:0] vga_red_o,\r
output [ 3:0] vga_green_o,\r
output [ 3:0] vga_blue_o,\r
output horiz_sync,\r
output vert_sync,\r
\r
// VGA CPU FML master interface\r
output [fml_depth-1:0] vga_cpu_fml_adr,\r
output vga_cpu_fml_stb,\r
output vga_cpu_fml_we,\r
input vga_cpu_fml_ack,\r
output [1:0] vga_cpu_fml_sel,\r
output [15:0] vga_cpu_fml_do,\r
input [15:0] vga_cpu_fml_di,\r
\r
// VGA LCD FML master interface\r
output [fml_depth-1:0] vga_lcd_fml_adr,\r
output vga_lcd_fml_stb,\r
output vga_lcd_fml_we,\r
input vga_lcd_fml_ack,\r
output [1:0] vga_lcd_fml_sel,\r
output [15:0] vga_lcd_fml_do,\r
input [15:0] vga_lcd_fml_di,\r
\r
output vga_clk\r
\r
);\r
\r
\r
// Registers and nets\r
\r
// Config wires\r
wire [15:0] conf_wb_dat_o;\r
wire conf_wb_ack_o;\r
\r
// Mem wires\r
wire [15:0] mem_wb_dat_o;\r
wire mem_wb_ack_o;\r
\r
// LCD wires\r
wire v_retrace;\r
wire vh_retrace;\r
wire w_vert_sync;\r
\r
// VGA LCD Direct Cache Bus\r
wire vga_lcd_dcb_stb;\r
wire [fml_depth-1:0] vga_lcd_dcb_adr;\r
wire [15:0] vga_lcd_dcb_dat;\r
wire vga_lcd_dcb_hit;\r
\r
// VGA configuration registers\r
wire shift_reg1;\r
wire graphics_alpha;\r
wire memory_mapping1;\r
wire [ 1:0] write_mode;\r
wire [ 1:0] raster_op;\r
wire read_mode;\r
wire [ 7:0] bitmask;\r
wire [ 3:0] set_reset;\r
wire [ 3:0] enable_set_reset;\r
wire [ 3:0] map_mask;\r
wire x_dotclockdiv2;\r
wire chain_four;\r
wire [ 1:0] read_map_select;\r
wire [ 3:0] color_compare;\r
wire [ 3:0] color_dont_care;\r
\r
// Wishbone master to SDRAM\r
wire [17:1] wbm_adr_o;\r
wire [ 1:0] wbm_sel_o;\r
wire wbm_we_o;\r
wire [15:0] wbm_dat_o;\r
wire [15:0] wbm_dat_i;\r
wire wbm_stb_o;\r
wire wbm_ack_i;\r
\r
wire stb;\r
\r
// CRT wires\r
wire [ 5:0] cur_start;\r
wire [ 5:0] cur_end;\r
wire [15:0] start_addr;\r
wire [ 4:0] vcursor;\r
wire [ 6:0] hcursor;\r
wire [ 6:0] horiz_total;\r
wire [ 6:0] end_horiz;\r
wire [ 6:0] st_hor_retr;\r
wire [ 4:0] end_hor_retr;\r
wire [ 9:0] vert_total;\r
wire [ 9:0] end_vert;\r
wire [ 9:0] st_ver_retr;\r
wire [ 3:0] end_ver_retr;\r
\r
// attribute_ctrl wires\r
wire [3:0] pal_addr;\r
wire pal_we;\r
wire [7:0] pal_read;\r
wire [7:0] pal_write;\r
\r
// dac_regs wires\r
wire dac_we;\r
wire [1:0] dac_read_data_cycle;\r
wire [7:0] dac_read_data_register;\r
wire [3:0] dac_read_data;\r
wire [1:0] dac_write_data_cycle;\r
wire [7:0] dac_write_data_register;\r
wire [3:0] dac_write_data;\r
\r
// Module instances\r
//\r
vga_config_iface config_iface (\r
.wb_clk_i (wb_clk_i),\r
.wb_rst_i (wb_rst_i),\r
.wb_dat_i (wb_dat_i),\r
.wb_dat_o (conf_wb_dat_o),\r
.wb_adr_i (wb_adr_i[4:1]),\r
.wb_we_i (wb_we_i),\r
.wb_sel_i (wb_sel_i),\r
.wb_stb_i (stb & wb_tga_i),\r
.wb_ack_o (conf_wb_ack_o),\r
\r
.shift_reg1 (shift_reg1),\r
.graphics_alpha (graphics_alpha),\r
.memory_mapping1 (memory_mapping1),\r
.write_mode (write_mode),\r
.raster_op (raster_op),\r
.read_mode (read_mode),\r
.bitmask (bitmask),\r
.set_reset (set_reset),\r
.enable_set_reset (enable_set_reset),\r
.map_mask (map_mask),\r
.x_dotclockdiv2 (x_dotclockdiv2),\r
.chain_four (chain_four),\r
.read_map_select (read_map_select),\r
.color_compare (color_compare),\r
.color_dont_care (color_dont_care),\r
\r
.pal_addr (pal_addr),\r
.pal_we (pal_we),\r
.pal_read (pal_read),\r
.pal_write (pal_write),\r
\r
.dac_we (dac_we),\r
.dac_read_data_cycle (dac_read_data_cycle),\r
.dac_read_data_register (dac_read_data_register),\r
.dac_read_data (dac_read_data),\r
.dac_write_data_cycle (dac_write_data_cycle),\r
.dac_write_data_register (dac_write_data_register),\r
.dac_write_data (dac_write_data),\r
\r
.cur_start (cur_start),\r
.cur_end (cur_end),\r
.start_addr (start_addr),\r
.vcursor (vcursor),\r
.hcursor (hcursor),\r
\r
.horiz_total (horiz_total),\r
.end_horiz (end_horiz),\r
.st_hor_retr (st_hor_retr),\r
.end_hor_retr (end_hor_retr),\r
.vert_total (vert_total),\r
.end_vert (end_vert),\r
.st_ver_retr (st_ver_retr),\r
.end_ver_retr (end_ver_retr),\r
\r
.v_retrace (v_retrace),\r
.vh_retrace (vh_retrace)\r
);\r
\r
vga_lcd_fml #(\r
.fml_depth (fml_depth) // 1MB Memeory address range\r
) lcd (\r
.clk (wb_clk_i),\r
.rst (wb_rst_i),\r
\r
.shift_reg1 (shift_reg1),\r
.graphics_alpha (graphics_alpha),\r
\r
.pal_addr (pal_addr),\r
.pal_we (pal_we),\r
.pal_read (pal_read),\r
.pal_write (pal_write),\r
\r
.dac_we (dac_we),\r
.dac_read_data_cycle (dac_read_data_cycle),\r
.dac_read_data_register (dac_read_data_register),\r
.dac_read_data (dac_read_data),\r
.dac_write_data_cycle (dac_write_data_cycle),\r
.dac_write_data_register (dac_write_data_register),\r
.dac_write_data (dac_write_data),\r
\r
// VGA LCD FML master interface\r
.fml_adr (vga_lcd_fml_adr),\r
.fml_stb (vga_lcd_fml_stb),\r
.fml_we (vga_lcd_fml_we),\r
.fml_ack (vga_lcd_fml_ack),\r
.fml_sel (vga_lcd_fml_sel),\r
.fml_do (vga_lcd_fml_do),\r
.fml_di (vga_lcd_fml_di),\r
\r
// VGA LCD Direct Cache Bus\r
.dcb_stb(vga_lcd_dcb_stb),\r
.dcb_adr(vga_lcd_dcb_adr),\r
.dcb_dat(vga_lcd_dcb_dat),\r
.dcb_hit(vga_lcd_dcb_hit),\r
\r
.vga_red_o (vga_red_o),\r
.vga_green_o (vga_green_o),\r
.vga_blue_o (vga_blue_o),\r
.horiz_sync (horiz_sync),\r
.vert_sync (w_vert_sync),\r
\r
.start_addr (start_addr),\r
\r
.cur_start (cur_start),\r
.cur_end (cur_end),\r
.vcursor (vcursor),\r
.hcursor (hcursor),\r
\r
.horiz_total (horiz_total),\r
.end_horiz (end_horiz),\r
.st_hor_retr (st_hor_retr),\r
.end_hor_retr (end_hor_retr),\r
.vert_total (vert_total),\r
.end_vert (end_vert),\r
.st_ver_retr (st_ver_retr),\r
.end_ver_retr (end_ver_retr),\r
\r
.x_dotclockdiv2 (x_dotclockdiv2),\r
\r
.v_retrace (v_retrace),\r
.vh_retrace (vh_retrace),\r
\r
.vga_clk(vga_clk)\r
);\r
\r
vga_cpu_mem_iface cpu_mem_iface (\r
.wb_clk_i (wb_clk_i),\r
.wb_rst_i (wb_rst_i),\r
\r
.wbs_adr_i (wb_adr_i),\r
.wbs_sel_i (wb_sel_i),\r
.wbs_we_i (wb_we_i),\r
.wbs_dat_i (wb_dat_i),\r
.wbs_dat_o (mem_wb_dat_o),\r
.wbs_stb_i (stb & !wb_tga_i),\r
.wbs_ack_o (mem_wb_ack_o),\r
\r
.wbm_adr_o (wbm_adr_o),\r
.wbm_sel_o (wbm_sel_o),\r
.wbm_we_o (wbm_we_o),\r
.wbm_dat_o (wbm_dat_o),\r
.wbm_dat_i (wbm_dat_i),\r
.wbm_stb_o (wbm_stb_o),\r
.wbm_ack_i (wbm_ack_i),\r
\r
.chain_four (chain_four),\r
.memory_mapping1 (memory_mapping1),\r
.write_mode (write_mode),\r
.raster_op (raster_op),\r
.read_mode (read_mode),\r
.bitmask (bitmask),\r
.set_reset (set_reset),\r
.enable_set_reset (enable_set_reset),\r
.map_mask (map_mask),\r
.read_map_select (read_map_select),\r
.color_compare (color_compare),\r
.color_dont_care (color_dont_care)\r
);\r
\r
fmlbrg #(\r
.fml_depth (fml_depth), // 1MB Memory address range\r
.cache_depth (5) // 32 byte cache\r
) vgafmlbrg (\r
.sys_clk (wb_clk_i),\r
.sys_rst (wb_rst_i),\r
\r
// Wishbone slave interface\r
.wb_adr_i ({ 2'b0, wbm_adr_o }),\r
.wb_cti_i (3'b0),\r
.wb_dat_i (wbm_dat_o),\r
.wb_dat_o (wbm_dat_i),\r
.wb_sel_i (wbm_sel_o),\r
.wb_cyc_i (wbm_stb_o),\r
.wb_stb_i (wbm_stb_o),\r
.wb_tga_i (1'b0),\r
.wb_we_i (wbm_we_o),\r
.wb_ack_o (wbm_ack_i), \r
\r
// VGA CPU FML master interface\r
.fml_adr (vga_cpu_fml_adr),\r
.fml_stb (vga_cpu_fml_stb),\r
.fml_we (vga_cpu_fml_we),\r
.fml_ack (vga_cpu_fml_ack),\r
.fml_sel (vga_cpu_fml_sel),\r
.fml_do (vga_cpu_fml_do),\r
.fml_di (vga_cpu_fml_di),\r
\r
// VGA LCD Direct Cache Bus\t \r
.dcb_stb (vga_lcd_dcb_stb),\r
.dcb_adr (vga_lcd_dcb_adr),\r
.dcb_dat (vga_lcd_dcb_dat),\r
.dcb_hit (vga_lcd_dcb_hit)\r
\r
);\r
\r
// Continous assignments\r
assign wb_dat_o = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o;\r
assign wb_ack_o = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o;\r
assign stb = wb_stb_i & wb_cyc_i;\r
assign vert_sync = ~graphics_alpha ^ w_vert_sync;\r
\r
endmodule\r
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
* adjusted to FML 8x16 by Zeus Gomez Marmolejo <[email protected]>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_banktimer(
\tinput sys_clk,
\tinput sdram_rst,
\t
\tinput tim_cas,
\tinput [1:0] tim_wr,
\t
\tinput read,
\tinput write,
\toutput reg precharge_safe
);
reg [3:0] counter;
always @(posedge sys_clk) begin
\tif(sdram_rst) begin
\t\tcounter <= 4\'d0;
\t\tprecharge_safe <= 1\'b1;
\tend else begin
\t\tif(read) begin
\t\t\t/* see p.26 of datasheet :
\t\t\t * "A Read burst may be followed by, or truncated with, a Precharge command
\t\t\t * to the same bank. The Precharge command should be issued x cycles after
\t\t\t * the Read command, where x equals the number of desired data element
\t\t\t * pairs"
\t\t\t */
\t\t\tcounter <= 4\'d8;
\t\t\tprecharge_safe <= 1\'b0;
\t\tend else if(write) begin
\t\t\tcounter <= {2\'b10, tim_wr};
\t\t\tprecharge_safe <= 1\'b0;
\t\tend else begin
\t\t\tif(counter == 4\'b1)
\t\t\t\tprecharge_safe <= 1\'b1;
\t\t\tif(~precharge_safe)
\t\t\t\tcounter <= counter - 4\'b1;
\t\tend
\tend
end
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
* adjusted to FML 8x16 by Zeus Gomez Marmolejo <[email protected]>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_ctlif #(
\tparameter csr_addr = 1'b0,
\tparameter sdram_addrdepth = 12
) (
\tinput sys_clk,
\tinput sys_rst,
\t
\tinput [ 2:0] csr_a,
\tinput csr_we,
\tinput [15:0] csr_di,
\toutput reg [15:0] csr_do,
\t
\toutput reg bypass,
\toutput reg sdram_rst,
\t
\toutput reg sdram_cke,
\toutput reg sdram_cs_n,
\toutput reg sdram_we_n,
\toutput reg sdram_cas_n,
\toutput reg sdram_ras_n,
\toutput reg [sdram_addrdepth-1:0] sdram_adr,
\toutput [ 1:0] sdram_ba,
\t
\t/* Clocks we must wait following a PRECHARGE command (usually tRP). */
\toutput reg [2:0] tim_rp,
\t/* Clocks we must wait following an ACTIVATE command (usually tRCD). */
\toutput reg [2:0] tim_rcd,
\t/* CAS latency, 0 = 2 */
\toutput reg tim_cas,
\t/* Auto-refresh period (usually tREFI). */
\toutput reg [10:0] tim_refi,
\t/* Clocks we must wait following an AUTO REFRESH command (usually tRFC). */
\toutput reg [3:0] tim_rfc,
\t/* Clocks we must wait following the last word written to the SDRAM (usually tWR). */
\toutput reg [1:0] tim_wr
);
localparam low_addr_bits16 = 16 - sdram_addrdepth;
localparam low_addr_bits12 = sdram_addrdepth - 12;
wire csr_selected = csr_a[2] == csr_addr;
// We assume sdram_ba will be always zero, so we can truncate the bus to 16 bits
assign sdram_ba = 2'b00;
always @(posedge sys_clk) begin
\tif(sys_rst) begin
\t\tcsr_do <= 16'd0;
\t
\t\tbypass <= 1'b1;
\t\tsdram_rst <= 1'b1;
\t\t
\t\tsdram_cke <= 1'b0;
\t\tsdram_adr <= {sdram_addrdepth{1'd0}};
\t\t
\t\ttim_rp <= 3'd2;
\t\ttim_rcd <= 3'd2;
\t\ttim_cas <= 1'b0;
\t\ttim_refi <= 11'd740;
\t\ttim_rfc <= 4'd8;
\t\ttim_wr <= 2'd2;
\tend else begin
\t\tsdram_cs_n <= 1'b1;
\t\tsdram_we_n <= 1'b1;
\t\tsdram_cas_n <= 1'b1;
\t\tsdram_ras_n <= 1'b1;
\t\t
\t\tcsr_do <= 16'd0;
\t\tif(csr_selected) begin
\t\t\tif(csr_we) begin
\t\t\t\tcase(csr_a[1:0])
\t\t\t\t\t2'b00: begin
\t\t\t\t\t\tbypass <= csr_di[0];
\t\t\t\t\t\tsdram_rst <= csr_di[1];
\t\t\t\t\t\tsdram_cke <= csr_di[2];
\t\t\t\t\tend
\t\t\t\t\t2'b01: begin
\t\t\t\t\t\tsdram_cs_n <= ~csr_di[0];
\t\t\t\t\t\tsdram_we_n <= ~csr_di[1];
\t\t\t\t\t\tsdram_cas_n <= ~csr_di[2];
\t\t\t\t\t\tsdram_ras_n <= ~csr_di[3];
\t\t\t\t\t\tsdram_adr <= { {low_addr_bits12{1'b0}}, csr_di[15:4]};
\t\t\t\t\tend
\t\t\t\t\t2'b10: begin
\t\t\t\t\t\ttim_rp <= csr_di[2:0];
\t\t\t\t\t\ttim_rcd <= csr_di[5:3];
\t\t\t\t\t\ttim_cas <= csr_di[6];
\t\t\t\t\t\ttim_rfc <= csr_di[10:7];
\t\t\t\t\t\ttim_wr <= csr_di[12:11];
\t\t\t\t\tend
2'b11: begin
\t\t\t\t\t\ttim_refi <= csr_di[10:0];
end
\t\t\t\tendcase
\t\t\tend
\t\t\tcase(csr_a[1:0])
\t\t\t\t2'b00: csr_do <= {sdram_cke, sdram_rst, bypass};
\t\t\t\t2'b01: csr_do <= {sdram_adr, {low_addr_bits16{1'b0}} };
\t\t\t\t2'b10: csr_do <= {tim_wr, tim_rfc, tim_cas, tim_rcd, tim_rp};
2'b11: csr_do <= {5'd0, tim_refi};
\t\t\tendcase
\t\tend
\tend
end
endmodule
|
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