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//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_gpio.v
//
// *Module Description:
// Digital I/O interface
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
module omsp_gpio (
// OUTPUTs
irq_port1, // Port 1 interrupt
irq_port2, // Port 2 interrupt
p1_dout, // Port 1 data output
p1_dout_en, // Port 1 data output enable
p1_sel, // Port 1 function select
p2_dout, // Port 2 data output
p2_dout_en, // Port 2 data output enable
p2_sel, // Port 2 function select
p3_dout, // Port 3 data output
p3_dout_en, // Port 3 data output enable
p3_sel, // Port 3 function select
p4_dout, // Port 4 data output
p4_dout_en, // Port 4 data output enable
p4_sel, // Port 4 function select
p5_dout, // Port 5 data output
p5_dout_en, // Port 5 data output enable
p5_sel, // Port 5 function select
p6_dout, // Port 6 data output
p6_dout_en, // Port 6 data output enable
p6_sel, // Port 6 function select
per_dout, // Peripheral data output
// INPUTs
mclk, // Main system clock
p1_din, // Port 1 data input
p2_din, // Port 2 data input
p3_din, // Port 3 data input
p4_din, // Port 4 data input
p5_din, // Port 5 data input
p6_din, // Port 6 data input
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_we, // Peripheral write enable (high active)
puc_rst // Main system reset
);
// PARAMETERs
//============
parameter P1_EN = 1\'b1; // Enable Port 1
parameter P2_EN = 1\'b1; // Enable Port 2
parameter P3_EN = 1\'b0; // Enable Port 3
parameter P4_EN = 1\'b0; // Enable Port 4
parameter P5_EN = 1\'b0; // Enable Port 5
parameter P6_EN = 1\'b0; // Enable Port 6
// OUTPUTs
//=========
output irq_port1; // Port 1 interrupt
output irq_port2; // Port 2 interrupt
output [7:0] p1_dout; // Port 1 data output
output [7:0] p1_dout_en; // Port 1 data output enable
output [7:0] p1_sel; // Port 1 function select
output [7:0] p2_dout; // Port 2 data output
output [7:0] p2_dout_en; // Port 2 data output enable
output [7:0] p2_sel; // Port 2 function select
output [7:0] p3_dout; // Port 3 data output
output [7:0] p3_dout_en; // Port 3 data output enable
output [7:0] p3_sel; // Port 3 function select
output [7:0] p4_dout; // Port 4 data output
output [7:0] p4_dout_en; // Port 4 data output enable
output [7:0] p4_sel; // Port 4 function select
output [7:0] p5_dout; // Port 5 data output
output [7:0] p5_dout_en; // Port 5 data output enable
output [7:0] p5_sel; // Port 5 function select
output [7:0] p6_dout; // Port 6 data output
output [7:0] p6_dout_en; // Port 6 data output enable
output [7:0] p6_sel; // Port 6 function select
output [15:0] per_dout; // Peripheral data output
// INPUTs
//=========
input mclk; // Main system clock
input [7:0] p1_din; // Port 1 data input
input [7:0] p2_din; // Port 2 data input
input [7:0] p3_din; // Port 3 data input
input [7:0] p4_din; // Port 4 data input
input [7:0] p5_din; // Port 5 data input
input [7:0] p6_din; // Port 6 data input
input [13:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input puc_rst; // Main system reset
//=============================================================================
// 1) PARAMETER DECLARATION
//=============================================================================
// Masks
parameter P1_EN_MSK = {8{P1_EN[0]}};
parameter P2_EN_MSK = {8{P2_EN[0]}};
parameter P3_EN_MSK = {8{P3_EN[0]}};
parameter P4_EN_MSK = {8{P4_EN[0]}};
parameter P5_EN_MSK = {8{P5_EN[0]}};
parameter P6_EN_MSK = {8{P6_EN[0]}};
// Register base address (must be aligned to decoder bit width)
parameter [14:0] BASE_ADDR = 15\'h0000;
// Decoder bit width (defines how many bits are considered for address decoding)
parameter DEC_WD = 6;
// Register addresses offset
parameter [DEC_WD-1:0] P1IN = \'h20, // Port 1
P1OUT = \'h21,
P1DIR = \'h22,
P1IFG = \'h23,
P1IES = \'h24,
P1IE = \'h25,
P1SEL = \'h26,
P2IN = \'h28, // Port 2
P2OUT = \'h29,
P2DIR = \'h2A,
P2IFG = \'h2B,
P2IES = \'h2C,
P2IE = \'h2D,
P2SEL = \'h2E,
P3IN = \'h18, // Port 3
P3OUT = \'h19,
P3DIR = \'h1A,
P3SEL = \'h1B,
P4IN = \'h1C, // Port 4
P4OUT = \'h1D,
P4DIR = \'h1E,
P4SEL = \'h1F,
P5IN = \'h30, // Port 5
P5OUT = \'h31,
P5DIR = \'h32,
P5SEL = \'h33,
P6IN = \'h34, // Port 6
P6OUT = \'h35,
P6DIR = \'h36,
P6SEL = \'h37;
// Register one-hot decoder utilities
parameter DEC_SZ = (1 << DEC_WD);
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1\'b0}}, 1\'b1};
// Register one-hot decoder
parameter [DEC_SZ-1:0] P1IN_D = (BASE_REG << P1IN), // Port 1
P1OUT_D = (BASE_REG << P1OUT),
P1DIR_D = (BASE_REG << P1DIR),
P1IFG_D = (BASE_REG << P1IFG),
P1IES_D = (BASE_REG << P1IES),
P1IE_D = (BASE_REG << P1IE),
P1SEL_D = (BASE_REG << P1SEL),
P2IN_D = (BASE_REG << P2IN), // Port 2
P2OUT_D = (BASE_REG << P2OUT),
P2DIR_D = (BASE_REG << P2DIR),
P2IFG_D = (BASE_REG << P2IFG),
P2IES_D = (BASE_REG << P2IES),
P2IE_D = (BASE_REG << P2IE),
P2SEL_D = (BASE_REG << P2SEL),
P3IN_D = (BASE_REG << P3IN), // Port 3
P3OUT_D = (BASE_REG << P3OUT),
P3DIR_D = (BASE_REG << P3DIR),
P3SEL_D = (BASE_REG << P3SEL),
P4IN_D = (BASE_REG << P4IN), // Port 4
P4OUT_D = (BASE_REG << P4OUT),
P4DIR_D = (BASE_REG << P4DIR),
P4SEL_D = (BASE_REG << P4SEL),
P5IN_D = (BASE_REG << P5IN), // Port 5
P5OUT_D = (BASE_REG << P5OUT),
P5DIR_D = (BASE_REG << P5DIR),
P5SEL_D = (BASE_REG << P5SEL),
P6IN_D = (BASE_REG << P6IN), // Port 6
P6OUT_D = (BASE_REG << P6OUT),
P6DIR_D = (BASE_REG << P6DIR),
P6SEL_D = (BASE_REG << P6SEL);
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Local register selection
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
// Register local address
wire [DEC_WD-1:0] reg_addr = {1\'b0, per_addr[DEC_WD-2:0]};
// Register address decode
wire [DEC_SZ-1:0] reg_dec = (P1IN_D & {DEC_SZ{(reg_addr==(P1IN >>1)) & P1_EN[0]}}) |
(P1OUT_D & {DEC_SZ{(reg_addr==(P1OUT >>1)) & P1_EN[0]}}) |
(P1DIR_D & {DEC_SZ{(reg_addr==(P1DIR >>1)) & P1_EN[0]}}) |
(P1IFG_D & {DEC_SZ{(reg_addr==(P1IFG >>1)) & P1_EN[0]}}) |
(P1IES_D & {DEC_SZ{(reg_addr==(P1IES >>1)) & P1_EN[0]}}) |
(P1IE_D & {DEC_SZ{(reg_addr==(P1IE >>1)) & P1_EN[0]}}) |
(P1SEL_D & {DEC_SZ{(reg_addr==(P1SEL >>1)) & P1_EN[0]}}) |
(P2IN_D & {DEC_SZ{(reg_addr==(P2IN >>1)) & P2_EN[0]}}) |
(P2OUT_D & {DEC_SZ{(reg_addr==(P2OUT >>1)) & P2_EN[0]}}) |
(P2DIR_D & {DEC_SZ{(reg_addr==(P2DIR >>1)) & P2_EN[0]}}) |
(P2IFG_D & {DEC_SZ{(reg_addr==(P2IFG >>1)) & P2_EN[0]}}) |
(P2IES_D & {DEC_SZ{(reg_addr==(P2IES >>1)) & P2_EN[0]}}) |
(P2IE_D & {DEC_SZ{(reg_addr==(P2IE >>1)) & P2_EN[0]}}) |
(P2SEL_D & {DEC_SZ{(reg_addr==(P2SEL >>1)) & P2_EN[0]}}) |
(P3IN_D & {DEC_SZ{(reg_addr==(P3IN >>1)) & P3_EN[0]}}) |
(P3OUT_D & {DEC_SZ{(reg_addr==(P3OUT >>1)) & P3_EN[0]}}) |
(P3DIR_D & {DEC_SZ{(reg_addr==(P3DIR >>1)) & P3_EN[0]}}) |
(P3SEL_D & {DEC_SZ{(reg_addr==(P3SEL >>1)) & P3_EN[0]}}) |
(P4IN_D & {DEC_SZ{(reg_addr==(P4IN >>1)) & P4_EN[0]}}) |
(P4OUT_D & {DEC_SZ{(reg_addr==(P4OUT >>1)) & P4_EN[0]}}) |
(P4DIR_D & {DEC_SZ{(reg_addr==(P4DIR >>1)) & P4_EN[0]}}) |
(P4SEL_D & {DEC_SZ{(reg_addr==(P4SEL >>1)) & P4_EN[0]}}) |
(P5IN_D & {DEC_SZ{(reg_addr==(P5IN >>1)) & P5_EN[0]}}) |
(P5OUT_D & {DEC_SZ{(reg_addr==(P5OUT >>1)) & P5_EN[0]}}) |
(P5DIR_D & {DEC_SZ{(reg_addr==(P5DIR >>1)) & P5_EN[0]}}) |
(P5SEL_D & {DEC_SZ{(reg_addr==(P5SEL >>1)) & P5_EN[0]}}) |
(P6IN_D & {DEC_SZ{(reg_addr==(P6IN >>1)) & P6_EN[0]}}) |
(P6OUT_D & {DEC_SZ{(reg_addr==(P6OUT >>1)) & P6_EN[0]}}) |
(P6DIR_D & {DEC_SZ{(reg_addr==(P6DIR >>1)) & P6_EN[0]}}) |
(P6SEL_D & {DEC_SZ{(reg_addr==(P6SEL >>1)) & P6_EN[0]}});
// Read/Write probes
wire reg_lo_write = per_we[0] & reg_sel;
wire reg_hi_write = per_we[1] & reg_sel;
wire reg_read = ~|per_we & reg_sel;
// Read/Write vectors
wire [DEC_SZ-1:0] reg_hi_wr = reg_dec & {DEC_SZ{reg_hi_write}};
wire [DEC_SZ-1:0] reg_lo_wr = reg_dec & {DEC_SZ{reg_lo_write}};
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
//============================================================================
// 3) REGISTERS
//============================================================================
// P1IN Register
//---------------
wire [7:0] p1in;
omsp_sync_cell sync_cell_p1in_0 (.data_out(p1in[0]), .data_in(p1_din[0] & P1_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p1in_1 (.data_out(p1in[1]), .data_in(p1_din[1] & P1_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p1in_2 (.data_out(p1in[2]), .data_in(p1_din[2] & P1_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p1in_3 (.data_out(p1in[3]), .data_in(p1_din[3] & P1_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p1in_4 (.data_out(p1in[4]), .data_in(p1_din[4] & P1_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p1in_5 (.data_out(p1in[5]), .data_in(p1_din[5] & P1_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p1in_6 (.data_out(p1in[6]), .data_in(p1_din[6] & P1_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p1in_7 (.data_out(p1in[7]), .data_in(p1_din[7] & P1_EN[0]), .clk(mclk), .rst(puc_rst));
// P1OUT Register
//----------------
reg [7:0] p1out;
wire p1out_wr = P1OUT[0] ? reg_hi_wr[P1OUT] : reg_lo_wr[P1OUT];
wire [7:0] p1out_nxt = P1OUT[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p1out <= 8\'h00;
else if (p1out_wr) p1out <= p1out_nxt & P1_EN_MSK;
assign p1_dout = p1out;
// P1DIR Register
//----------------
reg [7:0] p1dir;
wire p1dir_wr = P1DIR[0] ? reg_hi_wr[P1DIR] : reg_lo_wr[P1DIR];
wire [7:0] p1dir_nxt = P1DIR[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p1dir <= 8\'h00;
else if (p1dir_wr) p1dir <= p1dir_nxt & P1_EN_MSK;
assign p1_dout_en = p1dir;
// P1IFG Register
//----------------
reg [7:0] p1ifg;
wire p1ifg_wr = P1IFG[0] ? reg_hi_wr[P1IFG] : reg_lo_wr[P1IFG];
wire [7:0] p1ifg_nxt = P1IFG[0] ? per_din[15:8] : per_din[7:0];
wire [7:0] p1ifg_set;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p1ifg <= 8\'h00;
else if (p1ifg_wr) p1ifg <= (p1ifg_nxt | p1ifg_set) & P1_EN_MSK;
else p1ifg <= (p1ifg | p1ifg_set) & P1_EN_MSK;
// P1IES Register
//----------------
reg [7:0] p1ies;
wire p1ies_wr = P1IES[0] ? reg_hi_wr[P1IES] : reg_lo_wr[P1IES];
wire [7:0] p1ies_nxt = P1IES[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p1ies <= 8\'h00;
else if (p1ies_wr) p1ies <= p1ies_nxt & P1_EN_MSK;
// P1IE Register
//----------------
reg [7:0] p1ie;
wire p1ie_wr = P1IE[0] ? reg_hi_wr[P1IE] : reg_lo_wr[P1IE];
wire [7:0] p1ie_nxt = P1IE[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p1ie <= 8\'h00;
else if (p1ie_wr) p1ie <= p1ie_nxt & P1_EN_MSK;
// P1SEL Register
//----------------
reg [7:0] p1sel;
wire p1sel_wr = P1SEL[0] ? reg_hi_wr[P1SEL] : reg_lo_wr[P1SEL];
wire [7:0] p1sel_nxt = P1SEL[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p1sel <= 8\'h00;
else if (p1sel_wr) p1sel <= p1sel_nxt & P1_EN_MSK;
assign p1_sel = p1sel;
// P2IN Register
//---------------
wire [7:0] p2in;
omsp_sync_cell sync_cell_p2in_0 (.data_out(p2in[0]), .data_in(p2_din[0] & P2_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p2in_1 (.data_out(p2in[1]), .data_in(p2_din[1] & P2_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p2in_2 (.data_out(p2in[2]), .data_in(p2_din[2] & P2_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p2in_3 (.data_out(p2in[3]), .data_in(p2_din[3] & P2_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p2in_4 (.data_out(p2in[4]), .data_in(p2_din[4] & P2_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p2in_5 (.data_out(p2in[5]), .data_in(p2_din[5] & P2_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p2in_6 (.data_out(p2in[6]), .data_in(p2_din[6] & P2_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p2in_7 (.data_out(p2in[7]), .data_in(p2_din[7] & P2_EN[0]), .clk(mclk), .rst(puc_rst));
// P2OUT Register
//----------------
reg [7:0] p2out;
wire p2out_wr = P2OUT[0] ? reg_hi_wr[P2OUT] : reg_lo_wr[P2OUT];
wire [7:0] p2out_nxt = P2OUT[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p2out <= 8\'h00;
else if (p2out_wr) p2out <= p2out_nxt & P2_EN_MSK;
assign p2_dout = p2out;
// P2DIR Register
//----------------
reg [7:0] p2dir;
wire p2dir_wr = P2DIR[0] ? reg_hi_wr[P2DIR] : reg_lo_wr[P2DIR];
wire [7:0] p2dir_nxt = P2DIR[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p2dir <= 8\'h00;
else if (p2dir_wr) p2dir <= p2dir_nxt & P2_EN_MSK;
assign p2_dout_en = p2dir;
// P2IFG Register
//----------------
reg [7:0] p2ifg;
wire p2ifg_wr = P2IFG[0] ? reg_hi_wr[P2IFG] : reg_lo_wr[P2IFG];
wire [7:0] p2ifg_nxt = P2IFG[0] ? per_din[15:8] : per_din[7:0];
wire [7:0] p2ifg_set;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p2ifg <= 8\'h00;
else if (p2ifg_wr) p2ifg <= (p2ifg_nxt | p2ifg_set) & P2_EN_MSK;
else p2ifg <= (p2ifg | p2ifg_set) & P2_EN_MSK;
// P2IES Register
//----------------
reg [7:0] p2ies;
wire p2ies_wr = P2IES[0] ? reg_hi_wr[P2IES] : reg_lo_wr[P2IES];
wire [7:0] p2ies_nxt = P2IES[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p2ies <= 8\'h00;
else if (p2ies_wr) p2ies <= p2ies_nxt & P2_EN_MSK;
// P2IE Register
//----------------
reg [7:0] p2ie;
wire p2ie_wr = P2IE[0] ? reg_hi_wr[P2IE] : reg_lo_wr[P2IE];
wire [7:0] p2ie_nxt = P2IE[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p2ie <= 8\'h00;
else if (p2ie_wr) p2ie <= p2ie_nxt & P2_EN_MSK;
// P2SEL Register
//----------------
reg [7:0] p2sel;
wire p2sel_wr = P2SEL[0] ? reg_hi_wr[P2SEL] : reg_lo_wr[P2SEL];
wire [7:0] p2sel_nxt = P2SEL[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p2sel <= 8\'h00;
else if (p2sel_wr) p2sel <= p2sel_nxt & P2_EN_MSK;
assign p2_sel = p2sel;
// P3IN Register
//---------------
wire [7:0] p3in;
omsp_sync_cell sync_cell_p3in_0 (.data_out(p3in[0]), .data_in(p3_din[0] & P3_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p3in_1 (.data_out(p3in[1]), .data_in(p3_din[1] & P3_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p3in_2 (.data_out(p3in[2]), .data_in(p3_din[2] & P3_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p3in_3 (.data_out(p3in[3]), .data_in(p3_din[3] & P3_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p3in_4 (.data_out(p3in[4]), .data_in(p3_din[4] & P3_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p3in_5 (.data_out(p3in[5]), .data_in(p3_din[5] & P3_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p3in_6 (.data_out(p3in[6]), .data_in(p3_din[6] & P3_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p3in_7 (.data_out(p3in[7]), .data_in(p3_din[7] & P3_EN[0]), .clk(mclk), .rst(puc_rst));
// P3OUT Register
//----------------
reg [7:0] p3out;
wire p3out_wr = P3OUT[0] ? reg_hi_wr[P3OUT] : reg_lo_wr[P3OUT];
wire [7:0] p3out_nxt = P3OUT[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p3out <= 8\'h00;
else if (p3out_wr) p3out <= p3out_nxt & P3_EN_MSK;
assign p3_dout = p3out;
// P3DIR Register
//----------------
reg [7:0] p3dir;
wire p3dir_wr = P3DIR[0] ? reg_hi_wr[P3DIR] : reg_lo_wr[P3DIR];
wire [7:0] p3dir_nxt = P3DIR[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p3dir <= 8\'h00;
else if (p3dir_wr) p3dir <= p3dir_nxt & P3_EN_MSK;
assign p3_dout_en = p3dir;
// P3SEL Register
//----------------
reg [7:0] p3sel;
wire p3sel_wr = P3SEL[0] ? reg_hi_wr[P3SEL] : reg_lo_wr[P3SEL];
wire [7:0] p3sel_nxt = P3SEL[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p3sel <= 8\'h00;
else if (p3sel_wr) p3sel <= p3sel_nxt & P3_EN_MSK;
assign p3_sel = p3sel;
// P4IN Register
//---------------
wire [7:0] p4in;
omsp_sync_cell sync_cell_p4in_0 (.data_out(p4in[0]), .data_in(p4_din[0] & P4_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p4in_1 (.data_out(p4in[1]), .data_in(p4_din[1] & P4_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p4in_2 (.data_out(p4in[2]), .data_in(p4_din[2] & P4_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p4in_3 (.data_out(p4in[3]), .data_in(p4_din[3] & P4_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p4in_4 (.data_out(p4in[4]), .data_in(p4_din[4] & P4_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p4in_5 (.data_out(p4in[5]), .data_in(p4_din[5] & P4_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p4in_6 (.data_out(p4in[6]), .data_in(p4_din[6] & P4_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p4in_7 (.data_out(p4in[7]), .data_in(p4_din[7] & P4_EN[0]), .clk(mclk), .rst(puc_rst));
// P4OUT Register
//----------------
reg [7:0] p4out;
wire p4out_wr = P4OUT[0] ? reg_hi_wr[P4OUT] : reg_lo_wr[P4OUT];
wire [7:0] p4out_nxt = P4OUT[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p4out <= 8\'h00;
else if (p4out_wr) p4out <= p4out_nxt & P4_EN_MSK;
assign p4_dout = p4out;
// P4DIR Register
//----------------
reg [7:0] p4dir;
wire p4dir_wr = P4DIR[0] ? reg_hi_wr[P4DIR] : reg_lo_wr[P4DIR];
wire [7:0] p4dir_nxt = P4DIR[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p4dir <= 8\'h00;
else if (p4dir_wr) p4dir <= p4dir_nxt & P4_EN_MSK;
assign p4_dout_en = p4dir;
// P4SEL Register
//----------------
reg [7:0] p4sel;
wire p4sel_wr = P4SEL[0] ? reg_hi_wr[P4SEL] : reg_lo_wr[P4SEL];
wire [7:0] p4sel_nxt = P4SEL[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p4sel <= 8\'h00;
else if (p4sel_wr) p4sel <= p4sel_nxt & P4_EN_MSK;
assign p4_sel = p4sel;
// P5IN Register
//---------------
wire [7:0] p5in;
omsp_sync_cell sync_cell_p5in_0 (.data_out(p5in[0]), .data_in(p5_din[0] & P5_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p5in_1 (.data_out(p5in[1]), .data_in(p5_din[1] & P5_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p5in_2 (.data_out(p5in[2]), .data_in(p5_din[2] & P5_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p5in_3 (.data_out(p5in[3]), .data_in(p5_din[3] & P5_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p5in_4 (.data_out(p5in[4]), .data_in(p5_din[4] & P5_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p5in_5 (.data_out(p5in[5]), .data_in(p5_din[5] & P5_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p5in_6 (.data_out(p5in[6]), .data_in(p5_din[6] & P5_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p5in_7 (.data_out(p5in[7]), .data_in(p5_din[7] & P5_EN[0]), .clk(mclk), .rst(puc_rst));
// P5OUT Register
//----------------
reg [7:0] p5out;
wire p5out_wr = P5OUT[0] ? reg_hi_wr[P5OUT] : reg_lo_wr[P5OUT];
wire [7:0] p5out_nxt = P5OUT[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p5out <= 8\'h00;
else if (p5out_wr) p5out <= p5out_nxt & P5_EN_MSK;
assign p5_dout = p5out;
// P5DIR Register
//----------------
reg [7:0] p5dir;
wire p5dir_wr = P5DIR[0] ? reg_hi_wr[P5DIR] : reg_lo_wr[P5DIR];
wire [7:0] p5dir_nxt = P5DIR[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p5dir <= 8\'h00;
else if (p5dir_wr) p5dir <= p5dir_nxt & P5_EN_MSK;
assign p5_dout_en = p5dir;
// P5SEL Register
//----------------
reg [7:0] p5sel;
wire p5sel_wr = P5SEL[0] ? reg_hi_wr[P5SEL] : reg_lo_wr[P5SEL];
wire [7:0] p5sel_nxt = P5SEL[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p5sel <= 8\'h00;
else if (p5sel_wr) p5sel <= p5sel_nxt & P5_EN_MSK;
assign p5_sel = p5sel;
// P6IN Register
//---------------
wire [7:0] p6in;
omsp_sync_cell sync_cell_p6in_0 (.data_out(p6in[0]), .data_in(p6_din[0] & P6_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p6in_1 (.data_out(p6in[1]), .data_in(p6_din[1] & P6_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p6in_2 (.data_out(p6in[2]), .data_in(p6_din[2] & P6_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p6in_3 (.data_out(p6in[3]), .data_in(p6_din[3] & P6_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p6in_4 (.data_out(p6in[4]), .data_in(p6_din[4] & P6_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p6in_5 (.data_out(p6in[5]), .data_in(p6_din[5] & P6_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p6in_6 (.data_out(p6in[6]), .data_in(p6_din[6] & P6_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p6in_7 (.data_out(p6in[7]), .data_in(p6_din[7] & P6_EN[0]), .clk(mclk), .rst(puc_rst));
// P6OUT Register
//----------------
reg [7:0] p6out;
wire p6out_wr = P6OUT[0] ? reg_hi_wr[P6OUT] : reg_lo_wr[P6OUT];
wire [7:0] p6out_nxt = P6OUT[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p6out <= 8\'h00;
else if (p6out_wr) p6out <= p6out_nxt & P6_EN_MSK;
assign p6_dout = p6out;
// P6DIR Register
//----------------
reg [7:0] p6dir;
wire p6dir_wr = P6DIR[0] ? reg_hi_wr[P6DIR] : reg_lo_wr[P6DIR];
wire [7:0] p6dir_nxt = P6DIR[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p6dir <= 8\'h00;
else if (p6dir_wr) p6dir <= p6dir_nxt & P6_EN_MSK;
assign p6_dout_en = p6dir;
// P6SEL Register
//----------------
reg [7:0] p6sel;
wire p6sel_wr = P6SEL[0] ? reg_hi_wr[P6SEL] : reg_lo_wr[P6SEL];
wire [7:0] p6sel_nxt = P6SEL[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p6sel <= 8\'h00;
else if (p6sel_wr) p6sel <= p6sel_nxt & P6_EN_MSK;
assign p6_sel = p6sel;
//============================================================================
// 4) INTERRUPT GENERATION
//============================================================================
// Port 1 interrupt
//------------------
// Delay input
reg [7:0] p1in_dly;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p1in_dly <= 8\'h00;
else p1in_dly <= p1in & P1_EN_MSK;
// Edge detection
wire [7:0] p1in_re = p1in & ~p1in_dly;
wire [7:0] p1in_fe = ~p1in & p1in_dly;
// Set interrupt flag
assign p1ifg_set = {p1ies[7] ? p1in_fe[7] : p1in_re[7],
p1ies[6] ? p1in_fe[6] : p1in_re[6],
p1ies[5] ? p1in_fe[5] : p1in_re[5],
p1ies[4] ? p1in_fe[4] : p1in_re[4],
p1ies[3] ? p1in_fe[3] : p1in_re[3],
p1ies[2] ? p1in_fe[2] : p1in_re[2],
p1ies[1] ? p1in_fe[1] : p1in_re[1],
p1ies[0] ? p1in_fe[0] : p1in_re[0]} & P1_EN_MSK;
// Generate CPU interrupt
assign irq_port1 = |(p1ie & p1ifg) & P1_EN[0];
// Port 1 interrupt
//------------------
// Delay input
reg [7:0] p2in_dly;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p2in_dly <= 8\'h00;
else p2in_dly <= p2in & P2_EN_MSK;
// Edge detection
wire [7:0] p2in_re = p2in & ~p2in_dly;
wire [7:0] p2in_fe = ~p2in & p2in_dly;
// Set interrupt flag
assign p2ifg_set = {p2ies[7] ? p2in_fe[7] : p2in_re[7],
p2ies[6] ? p2in_fe[6] : p2in_re[6],
p2ies[5] ? p2in_fe[5] : p2in_re[5],
p2ies[4] ? p2in_fe[4] : p2in_re[4],
p2ies[3] ? p2in_fe[3] : p2in_re[3],
p2ies[2] ? p2in_fe[2] : p2in_re[2],
p2ies[1] ? p2in_fe[1] : p2in_re[1],
p2ies[0] ? p2in_fe[0] : p2in_re[0]} & P2_EN_MSK;
// Generate CPU interrupt
assign irq_port2 = |(p2ie & p2ifg) & P2_EN[0];
//============================================================================
// 5) DATA OUTPUT GENERATION
//============================================================================
// Data output mux
wire [15:0] p1in_rd = {8\'h00, (p1in & {8{reg_rd[P1IN]}})} << (8 & {4{P1IN[0]}});
wire [15:0] p1out_rd = {8\'h00, (p1out & {8{reg_rd[P1OUT]}})} << (8 & {4{P1OUT[0]}});
wire [15:0] p1dir_rd = {8\'h00, (p1dir & {8{reg_rd[P1DIR]}})} << (8 & {4{P1DIR[0]}});
wire [15:0] p1ifg_rd = {8\'h00, (p1ifg & {8{reg_rd[P1IFG]}})} << (8 & {4{P1IFG[0]}});
wire [15:0] p1ies_rd = {8\'h00, (p1ies & {8{reg_rd[P1IES]}})} << (8 & {4{P1IES[0]}});
wire [15:0] p1ie_rd = {8\'h00, (p1ie & {8{reg_rd[P1IE]}})} << (8 & {4{P1IE[0]}});
wire [15:0] p1sel_rd = {8\'h00, (p1sel & {8{reg_rd[P1SEL]}})} << (8 & {4{P1SEL[0]}});
wire [15:0] p2in_rd = {8\'h00, (p2in & {8{reg_rd[P2IN]}})} << (8 & {4{P2IN[0]}});
wire [15:0] p2out_rd = {8\'h00, (p2out & {8{reg_rd[P2OUT]}})} << (8 & {4{P2OUT[0]}});
wire [15:0] p2dir_rd = {8\'h00, (p2dir & {8{reg_rd[P2DIR]}})} << (8 & {4{P2DIR[0]}});
wire [15:0] p2ifg_rd = {8\'h00, (p2ifg & {8{reg_rd[P2IFG]}})} << (8 & {4{P2IFG[0]}});
wire [15:0] p2ies_rd = {8\'h00, (p2ies & {8{reg_rd[P2IES]}})} << (8 & {4{P2IES[0]}});
wire [15:0] p2ie_rd = {8\'h00, (p2ie & {8{reg_rd[P2IE]}})} << (8 & {4{P2IE[0]}});
wire [15:0] p2sel_rd = {8\'h00, (p2sel & {8{reg_rd[P2SEL]}})} << (8 & {4{P2SEL[0]}});
wire [15:0] p3in_rd = {8\'h00, (p3in & {8{reg_rd[P3IN]}})} << (8 & {4{P3IN[0]}});
wire [15:0] p3out_rd = {8\'h00, (p3out & {8{reg_rd[P3OUT]}})} << (8 & {4{P3OUT[0]}});
wire [15:0] p3dir_rd = {8\'h00, (p3dir & {8{reg_rd[P3DIR]}})} << (8 & {4{P3DIR[0]}});
wire [15:0] p3sel_rd = {8\'h00, (p3sel & {8{reg_rd[P3SEL]}})} << (8 & {4{P3SEL[0]}});
wire [15:0] p4in_rd = {8\'h00, (p4in & {8{reg_rd[P4IN]}})} << (8 & {4{P4IN[0]}});
wire [15:0] p4out_rd = {8\'h00, (p4out & {8{reg_rd[P4OUT]}})} << (8 & {4{P4OUT[0]}});
wire [15:0] p4dir_rd = {8\'h00, (p4dir & {8{reg_rd[P4DIR]}})} << (8 & {4{P4DIR[0]}});
wire [15:0] p4sel_rd = {8\'h00, (p4sel & {8{reg_rd[P4SEL]}})} << (8 & {4{P4SEL[0]}});
wire [15:0] p5in_rd = {8\'h00, (p5in & {8{reg_rd[P5IN]}})} << (8 & {4{P5IN[0]}});
wire [15:0] p5out_rd = {8\'h00, (p5out & {8{reg_rd[P5OUT]}})} << (8 & {4{P5OUT[0]}});
wire [15:0] p5dir_rd = {8\'h00, (p5dir & {8{reg_rd[P5DIR]}})} << (8 & {4{P5DIR[0]}});
wire [15:0] p5sel_rd = {8\'h00, (p5sel & {8{reg_rd[P5SEL]}})} << (8 & {4{P5SEL[0]}});
wire [15:0] p6in_rd = {8\'h00, (p6in & {8{reg_rd[P6IN]}})} << (8 & {4{P6IN[0]}});
wire [15:0] p6out_rd = {8\'h00, (p6out & {8{reg_rd[P6OUT]}})} << (8 & {4{P6OUT[0]}});
wire [15:0] p6dir_rd = {8\'h00, (p6dir & {8{reg_rd[P6DIR]}})} << (8 & {4{P6DIR[0]}});
wire [15:0] p6sel_rd = {8\'h00, (p6sel & {8{reg_rd[P6SEL]}})} << (8 & {4{P6SEL[0]}});
wire [15:0] per_dout = p1in_rd |
p1out_rd |
p1dir_rd |
p1ifg_rd |
p1ies_rd |
p1ie_rd |
p1sel_rd |
p2in_rd |
p2out_rd |
p2dir_rd |
p2ifg_rd |
p2ies_rd |
p2ie_rd |
p2sel_rd |
p3in_rd |
p3out_rd |
p3dir_rd |
p3sel_rd |
p4in_rd |
p4out_rd |
p4dir_rd |
p4sel_rd |
p5in_rd |
p5out_rd |
p5dir_rd |
p5sel_rd |
p6in_rd |
p6out_rd |
p6dir_rd |
p6sel_rd;
endmodule // omsp_gpio
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: template_periph_16b.v
//
// *Module Description:
// 16 bit peripheral template.
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
module template_periph_16b (
// OUTPUTs
per_dout, // Peripheral data output
// INPUTs
mclk, // Main system clock
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_we, // Peripheral write enable (high active)
puc_rst // Main system reset
);
// OUTPUTs
//=========
output [15:0] per_dout; // Peripheral data output
// INPUTs
//=========
input mclk; // Main system clock
input [13:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input puc_rst; // Main system reset
//=============================================================================
// 1) PARAMETER DECLARATION
//=============================================================================
// Register base address (must be aligned to decoder bit width)
parameter [14:0] BASE_ADDR = 15\'h0190;
// Decoder bit width (defines how many bits are considered for address decoding)
parameter DEC_WD = 3;
// Register addresses offset
parameter [DEC_WD-1:0] CNTRL1 = \'h0,
CNTRL2 = \'h2,
CNTRL3 = \'h4,
CNTRL4 = \'h6;
// Register one-hot decoder utilities
parameter DEC_SZ = (1 << DEC_WD);
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1\'b0}}, 1\'b1};
// Register one-hot decoder
parameter [DEC_SZ-1:0] CNTRL1_D = (BASE_REG << CNTRL1),
CNTRL2_D = (BASE_REG << CNTRL2),
CNTRL3_D = (BASE_REG << CNTRL3),
CNTRL4_D = (BASE_REG << CNTRL4);
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Local register selection
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
// Register local address
wire [DEC_WD-1:0] reg_addr = {per_addr[DEC_WD-2:0], 1\'b0};
// Register address decode
wire [DEC_SZ-1:0] reg_dec = (CNTRL1_D & {DEC_SZ{(reg_addr == CNTRL1 )}}) |
(CNTRL2_D & {DEC_SZ{(reg_addr == CNTRL2 )}}) |
(CNTRL3_D & {DEC_SZ{(reg_addr == CNTRL3 )}}) |
(CNTRL4_D & {DEC_SZ{(reg_addr == CNTRL4 )}});
// Read/Write probes
wire reg_write = |per_we & reg_sel;
wire reg_read = ~|per_we & reg_sel;
// Read/Write vectors
wire [DEC_SZ-1:0] reg_wr = reg_dec & {DEC_SZ{reg_write}};
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
//============================================================================
// 3) REGISTERS
//============================================================================
// CNTRL1 Register
//-----------------
reg [15:0] cntrl1;
wire cntrl1_wr = reg_wr[CNTRL1];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cntrl1 <= 16\'h0000;
else if (cntrl1_wr) cntrl1 <= per_din;
// CNTRL2 Register
//-----------------
reg [15:0] cntrl2;
wire cntrl2_wr = reg_wr[CNTRL2];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cntrl2 <= 16\'h0000;
else if (cntrl2_wr) cntrl2 <= per_din;
// CNTRL3 Register
//-----------------
reg [15:0] cntrl3;
wire cntrl3_wr = reg_wr[CNTRL3];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cntrl3 <= 16\'h0000;
else if (cntrl3_wr) cntrl3 <= per_din;
// CNTRL4 Register
//-----------------
reg [15:0] cntrl4;
wire cntrl4_wr = reg_wr[CNTRL4];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cntrl4 <= 16\'h0000;
else if (cntrl4_wr) cntrl4 <= per_din;
//============================================================================
// 4) DATA OUTPUT GENERATION
//============================================================================
// Data output mux
wire [15:0] cntrl1_rd = cntrl1 & {16{reg_rd[CNTRL1]}};
wire [15:0] cntrl2_rd = cntrl2 & {16{reg_rd[CNTRL2]}};
wire [15:0] cntrl3_rd = cntrl3 & {16{reg_rd[CNTRL3]}};
wire [15:0] cntrl4_rd = cntrl4 & {16{reg_rd[CNTRL4]}};
wire [15:0] per_dout = cntrl1_rd |
cntrl2_rd |
cntrl3_rd |
cntrl4_rd;
endmodule // template_periph_16b
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: tb_openMSP430.v
//
// *Module Description:
// openMSP430 testbench
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
`include "timescale.v"
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module tb_openMSP430;
//
// Wire & Register definition
//------------------------------
// Data Memory interface
wire [`DMEM_MSB:0] dmem_addr;
wire dmem_cen;
wire [15:0] dmem_din;
wire [1:0] dmem_wen;
wire [15:0] dmem_dout;
// Program Memory interface
wire [`PMEM_MSB:0] pmem_addr;
wire pmem_cen;
wire [15:0] pmem_din;
wire [1:0] pmem_wen;
wire [15:0] pmem_dout;
// Peripherals interface
wire [13:0] per_addr;
wire [15:0] per_din;
wire [15:0] per_dout;
wire [1:0] per_we;
wire per_en;
// Direct Memory Access interface
wire [15:0] dma_dout;
wire dma_ready;
wire dma_resp;
reg [15:1] dma_addr;
reg [15:0] dma_din;
reg dma_en;
reg dma_priority;
reg [1:0] dma_we;
reg dma_wkup;
// Digital I/O
wire irq_port1;
wire irq_port2;
wire [15:0] per_dout_dio;
wire [7:0] p1_dout;
wire [7:0] p1_dout_en;
wire [7:0] p1_sel;
wire [7:0] p2_dout;
wire [7:0] p2_dout_en;
wire [7:0] p2_sel;
wire [7:0] p3_dout;
wire [7:0] p3_dout_en;
wire [7:0] p3_sel;
wire [7:0] p4_dout;
wire [7:0] p4_dout_en;
wire [7:0] p4_sel;
wire [7:0] p5_dout;
wire [7:0] p5_dout_en;
wire [7:0] p5_sel;
wire [7:0] p6_dout;
wire [7:0] p6_dout_en;
wire [7:0] p6_sel;
reg [7:0] p1_din;
reg [7:0] p2_din;
reg [7:0] p3_din;
reg [7:0] p4_din;
reg [7:0] p5_din;
reg [7:0] p6_din;
// uart:
wire [15:0] per_dout_uart;
// Peripheral templates
wire [15:0] per_dout_temp_8b;
wire [15:0] per_dout_temp_16b;
// Timer A
wire irq_ta0;
wire irq_ta1;
wire [15:0] per_dout_timerA;
reg inclk;
reg taclk;
reg ta_cci0a;
reg ta_cci0b;
reg ta_cci1a;
reg ta_cci1b;
reg ta_cci2a;
reg ta_cci2b;
wire ta_out0;
wire ta_out0_en;
wire ta_out1;
wire ta_out1_en;
wire ta_out2;
wire ta_out2_en;
// Clock / Reset & Interrupts
reg dco_clk;
wire dco_enable;
wire dco_wkup;
reg dco_local_enable;
reg lfxt_clk;
wire lfxt_enable;
wire lfxt_wkup;
reg lfxt_local_enable;
wire mclk;
wire aclk;
wire aclk_en;
wire smclk;
wire smclk_en;
reg reset_n;
wire puc_rst;
reg nmi;
reg [`IRQ_NR-3:0] irq;
wire [`IRQ_NR-3:0] irq_acc;
wire [`IRQ_NR-3:0] irq_in;
reg cpu_en;
reg [13:0] wkup;
wire [13:0] wkup_in;
// Scan (ASIC version only)
reg scan_enable;
reg scan_mode;
// Debug interface: UART
reg dbg_en;
wire dbg_freeze;
wire dbg_uart_txd;
wire dbg_uart_rxd;
reg dbg_uart_rxd_sel;
reg dbg_uart_rxd_dly;
reg dbg_uart_rxd_pre;
reg dbg_uart_rxd_meta;
reg [15:0] dbg_uart_buf;
reg dbg_uart_rx_busy;
reg dbg_uart_tx_busy;
// Debug interface: I2C
wire dbg_scl;
wire dbg_sda;
wire dbg_scl_slave;
wire dbg_scl_master;
reg dbg_scl_master_sel;
reg dbg_scl_master_dly;
reg dbg_scl_master_pre;
reg dbg_scl_master_meta;
wire dbg_sda_slave_out;
wire dbg_sda_slave_in;
wire dbg_sda_master_out;
reg dbg_sda_master_out_sel;
reg dbg_sda_master_out_dly;
reg dbg_sda_master_out_pre;
reg dbg_sda_master_out_meta;
wire dbg_sda_master_in;
reg [15:0] dbg_i2c_buf;
reg [8*32-1:0] dbg_i2c_string;
// Core testbench debuging signals
wire [8*32-1:0] i_state;
wire [8*32-1:0] e_state;
wire [31:0] inst_cycle;
wire [8*32-1:0] inst_full;
wire [31:0] inst_number;
wire [15:0] inst_pc;
wire [8*32-1:0] inst_short;
// Testbench variables
integer tb_idx;
integer tmp_seed;
integer error;
reg stimulus_done;
//
// Include files
//------------------------------
// CPU & Memory registers
`include "registers.v"
// Debug interface tasks
`include "dbg_uart_tasks.v"
`include "dbg_i2c_tasks.v"
// Direct Memory Access interface tasks
`include "dma_tasks.v"
// Verilog stimulus
// `include "stimulus.v"
//
// Initialize Memory
//------------------------------
initial
begin
// Initialize data memory
for (tb_idx=0; tb_idx < `DMEM_SIZE/2; tb_idx=tb_idx+1)
dmem_0.mem[tb_idx] = 16\'h0000;
// Initialize program memory
`ifdef MEM_FILENAME
#10 $readmemh(`MEM_FILENAME, pmem_0.mem);
`else
#10 $readmemh("./pmem.mem", pmem_0.mem);
`endif
end
//
// Generate Clock & Reset
//------------------------------
initial
begin
dco_clk = 1\'b0;
dco_local_enable = 1\'b0;
forever
begin
#25; // 20 MHz
dco_local_enable = (dco_enable===1) ? dco_enable : (dco_wkup===1);
if (dco_local_enable | scan_mode)
dco_clk = ~dco_clk;
end
end
initial
begin
lfxt_clk = 1\'b0;
lfxt_local_enable = 1\'b0;
forever
begin
#763; // 655 kHz
lfxt_local_enable = (lfxt_enable===1) ? lfxt_enable : (lfxt_wkup===1);
if (lfxt_local_enable)
lfxt_clk = ~lfxt_clk;
end
end
initial
begin
reset_n = 1\'b1;
#93;
reset_n = 1\'b0;
#593;
reset_n = 1\'b1;
end
initial
begin
tmp_seed = `SEED;
tmp_seed = $urandom(tmp_seed);
error = 0;
stimulus_done = 1;
irq = {`IRQ_NR-2{1\'b0}};
nmi = 1\'b0;
wkup = 14\'h0000;
dma_addr = 15\'h0000;
dma_din = 16\'h0000;
dma_en = 1\'b0;
dma_priority = 1\'b0;
dma_we = 2\'b00;
dma_wkup = 1\'b0;
dma_tfx_cancel = 1\'b0;
cpu_en = 1\'b1;
dbg_en = 1\'b0;
dbg_uart_rxd_sel = 1\'b0;
dbg_uart_rxd_dly = 1\'b1;
dbg_uart_rxd_pre = 1\'b1;
dbg_uart_rxd_meta = 1\'b0;
dbg_uart_buf = 16\'h0000;
dbg_uart_rx_busy = 1\'b0;
dbg_uart_tx_busy = 1\'b0;
dbg_scl_master_sel = 1\'b0;
dbg_scl_master_dly = 1\'b1;
dbg_scl_master_pre = 1\'b1;
dbg_scl_master_meta = 1\'b0;
dbg_sda_master_out_sel = 1\'b0;
dbg_sda_master_out_dly = 1\'b1;
dbg_sda_master_out_pre = 1\'b1;
dbg_sda_master_out_meta = 1\'b0;
dbg_i2c_string = "";
p1_din = 8\'h00;
p2_din = 8\'h00;
p3_din = 8\'h00;
p4_din = 8\'h00;
p5_din = 8\'h00;
p6_din = 8\'h00;
inclk = 1\'b0;
taclk = 1\'b0;
ta_cci0a = 1\'b0;
ta_cci0b = 1\'b0;
ta_cci1a = 1\'b0;
ta_cci1b = 1\'b0;
ta_cci2a = 1\'b0;
ta_cci2b = 1\'b0;
scan_enable = 1\'b0;
scan_mode = 1\'b0;
end
//
// Program Memory
//----------------------------------
ram #(`PMEM_MSB, `PMEM_SIZE) pmem_0 (
// OUTPUTs
.ram_dout (pmem_dout), // Program Memory data output
// INPUTs
.ram_addr (pmem_addr), // Program Memory address
.ram_cen (pmem_cen), // Program Memory chip enable (low active)
.ram_clk (mclk), // Program Memory clock
.ram_din (pmem_din), // Program Memory data input
.ram_wen (pmem_wen) // Program Memory write enable (low active)
);
//
// Data Memory
//----------------------------------
ram #(`DMEM_MSB, `DMEM_SIZE) dmem_0 (
// OUTPUTs
.ram_dout (dmem_dout), // Data Memory data output
// INPUTs
.ram_addr (dmem_addr), // Data Memory address
.ram_cen (dmem_cen), // Data Memory chip enable (low active)
.ram_clk (mclk), // Data Memory clock
.ram_din (dmem_din), // Data Memory data input
.ram_wen (dmem_wen) // Data Memory write enable (low active)
);
//
// openMSP430 Instance
//----------------------------------
openMSP430 dut (
// OUTPUTs
.aclk (aclk), // ASIC ONLY: ACLK
.aclk_en (aclk_en), // FPGA ONLY: ACLK enable
.dbg_freeze (dbg_freeze), // Freeze peripherals
.dbg_i2c_sda_out (dbg_sda_slave_out), // Debug interface: I2C SDA OUT
.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
.dco_enable (dco_enable), // ASIC ONLY: Fast oscillator enable
.dco_wkup (dco_wkup), // ASIC ONLY: Fast oscillator wake-up (asynchronous)
.dmem_addr (dmem_addr), // Data Memory address
.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
.dmem_din (dmem_din), // Data Memory data input
.dmem_wen (dmem_wen), // Data Memory write byte enable (low active)
.irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)
.lfxt_enable (lfxt_enable), // ASIC ONLY: Low frequency oscillator enable
.lfxt_wkup (lfxt_wkup), // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
.mclk (mclk), // Main system clock
.dma_dout (dma_dout), // Direct Memory Access data output
.dma_ready (dma_ready), // Direct Memory Access is complete
.dma_resp (dma_resp), // Direct Memory Access response (0:Okay / 1:Error)
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write byte enable (high active)
.pmem_addr (pmem_addr), // Program Memory address
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
.pmem_din (pmem_din), // Program Memory data input (optional)
.pmem_wen (pmem_wen), // Program Memory write byte enable (low active) (optional)
.puc_rst (puc_rst), // Main system reset
.smclk (smclk), // ASIC ONLY: SMCLK
.smclk_en (smclk_en), // FPGA ONLY: SMCLK enable
// INPUTs
.cpu_en (cpu_en), // Enable CPU code execution (asynchronous)
.dbg_en (dbg_en), // Debug interface enable (asynchronous)
.dbg_i2c_addr (I2C_ADDR), // Debug interface: I2C Address
.dbg_i2c_broadcast (I2C_BROADCAST), // Debug interface: I2C Broadcast Address (for multicore systems)
.dbg_i2c_scl (dbg_scl_slave), // Debug interface: I2C SCL
.dbg_i2c_sda_in (dbg_sda_slave_in), // Debug interface: I2C SDA IN
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD (asynchronous)
.dco_clk (dco_clk), // Fast oscillator (fast clock)
.dmem_dout (dmem_dout), // Data Memory data output
.irq (irq_in), // Maskable interrupts
.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
.dma_addr (dma_addr), // Direct Memory Access address
.dma_din (dma_din), // Direct Memory Access data input
.dma_en (dma_en), // Direct Memory Access enable (high active)
.dma_priority (dma_priority), // Direct Memory Access priority (0:low / 1:high)
.dma_we (dma_we), // Direct Memory Access write byte enable (high active)
.dma_wkup (dma_wkup), // ASIC ONLY: DMA Sub-System Wake-up (asynchronous and non-glitchy)
.nmi (nmi), // Non-maskable interrupt (asynchronous)
.per_dout (per_dout), // Peripheral data output
.pmem_dout (pmem_dout), // Program Memory data output
.reset_n (reset_n), // Reset Pin (low active, asynchronous)
.scan_enable (scan_enable), // ASIC ONLY: Scan enable (active during scan shifting)
.scan_mode (scan_mode), // ASIC ONLY: Scan mode
.wkup (|wkup_in) // ASIC ONLY: System Wake-up (asynchronous)
);
//
// Digital I/O
//----------------------------------
`ifdef CVER
omsp_gpio #(1,
1,
1,
1,
1,
1) gpio_0 (
`else
omsp_gpio #(.P1_EN(1),
.P2_EN(1),
.P3_EN(1),
.P4_EN(1),
.P5_EN(1),
.P6_EN(1)) gpio_0 (
`endif
// OUTPUTs
.irq_port1 (irq_port1), // Port 1 interrupt
.irq_port2 (irq_port2), // Port 2 interrupt
.p1_dout (p1_dout), // Port 1 data output
.p1_dout_en (p1_dout_en), // Port 1 data output enable
.p1_sel (p1_sel), // Port 1 function select
.p2_dout (p2_dout), // Port 2 data output
.p2_dout_en (p2_dout_en), // Port 2 data output enable
.p2_sel (p2_sel), // Port 2 function select
.p3_dout (p3_dout), // Port 3 data output
.p3_dout_en (p3_dout_en), // Port 3 data output enable
.p3_sel (p3_sel), // Port 3 function select
.p4_dout (p4_dout), // Port 4 data output
.p4_dout_en (p4_dout_en), // Port 4 data output enable
.p4_sel (p4_sel), // Port 4 function select
.p5_dout (p5_dout), // Port 5 data output
.p5_dout_en (p5_dout_en), // Port 5 data output enable
.p5_sel (p5_sel), // Port 5 function select
.p6_dout (p6_dout), // Port 6 data output
.p6_dout_en (p6_dout_en), // Port 6 data output enable
.p6_sel (p6_sel), // Port 6 function select
.per_dout (per_dout_dio), // Peripheral data output
// INPUTs
.mclk (mclk), // Main system clock
.p1_din (p1_din), // Port 1 data input
.p2_din (p2_din), // Port 2 data input
.p3_din (p3_din), // Port 3 data input
.p4_din (p4_din), // Port 4 data input
.p5_din (p5_din), // Port 5 data input
.p6_din (p6_din), // Port 6 data input
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc_rst (puc_rst) // Main system reset
);
//
// Timers
//----------------------------------
omsp_timerA timerA_0 (
// OUTPUTs
.irq_ta0 (irq_ta0), // Timer A interrupt: TACCR0
.irq_ta1 (irq_ta1), // Timer A interrupt: TAIV, TACCR1, TACCR2
.per_dout (per_dout_timerA), // Peripheral data output
.ta_out0 (ta_out0), // Timer A output 0
.ta_out0_en (ta_out0_en), // Timer A output 0 enable
.ta_out1 (ta_out1), // Timer A output 1
.ta_out1_en (ta_out1_en), // Timer A output 1 enable
.ta_out2 (ta_out2), // Timer A output 2
.ta_out2_en (ta_out2_en), // Timer A output 2 enable
// INPUTs
.aclk_en (aclk_en), // ACLK enable (from CPU)
.dbg_freeze (dbg_freeze), // Freeze Timer A counter
.inclk (inclk), // INCLK external timer clock (SLOW)
.irq_ta0_acc (irq_acc[`IRQ_NR-7]), // Interrupt request TACCR0 accepted
.mclk (mclk), // Main system clock
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc_rst (puc_rst), // Main system reset
.smclk_en (smclk_en), // SMCLK enable (from CPU)
.ta_cci0a (ta_cci0a), // Timer A compare 0 input A
.ta_cci0b (ta_cci0b), // Timer A compare 0 input B
.ta_cci1a (ta_cci1a), // Timer A compare 1 input A
.ta_cci1b (ta_cci1b), // Timer A compare 1 input B
.ta_cci2a (ta_cci2a), // Timer A compare 2 input A
.ta_cci2b (ta_cci2b), // Timer A compare 2 input B
.taclk (taclk) // TACLK external timer clock (SLOW)
);
// -----------------------------------
// uart:
omsp_uart omsp_uart_0 (
// OUTPUTs
.per_dout (per_dout_uart), // Peripheral data output
// INPUTs
.mclk (mclk), // Main system clock
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc_rst (puc_rst) // Main system reset
);
// -----------------------------------
//
// Peripheral templates
//----------------------------------
template_periph_8b template_periph_8b_0 (
// OUTPUTs
.per_dout (per_dout_temp_8b), // Peripheral data output
// INPUTs
.mclk (mclk), // Main system clock
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc_rst (puc_rst) // Main system reset
);
`ifdef CVER
template_periph_16b #(15\'h0190) template_periph_16b_0 (
`else
template_periph_16b #(.BASE_ADDR((15\'d`PER_SIZE-15\'h0070) & 15\'h7ff8)) template_periph_16b_0 (
`endif
// OUTPUTs
.per_dout (per_dout_temp_16b), // Peripheral data output
// INPUTs
.mclk (mclk), // Main system clock
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc_rst (puc_rst) // Main system reset
);
//
// Combine peripheral data bus
//----------------------------------
assign per_dout = per_dout_dio |
per_dout_timerA |
per_dout_uart |
per_dout_temp_8b |
per_dout_temp_16b;
//
// Map peripheral interrupts & wakeups
//----------------------------------------
assign irq_in = irq | {1\'b0, // Vector 13 (0xFFFA)
1\'b0, // Vector 12 (0xFFF8)
1\'b0, // Vector 11 (0xFFF6)
1\'b0, // Vector 10 (0xFFF4) - Watchdog -
irq_ta0, // Vector 9 (0xFFF2)
irq_ta1, // Vector 8 (0xFFF0)
1\'b0, // Vector 7 (0xFFEE)
1\'b0, // Vector 6 (0xFFEC)
1\'b0, // Vector 5 (0xFFEA)
1\'b0, // Vector 4 (0xFFE8)
irq_port2, // Vector 3 (0xFFE6)
irq_port1, // Vector 2 (0xFFE4)
1\'b0, // Vector 1 (0xFFE2)
{`IRQ_NR-15{1\'b0}}}; // Vector 0 (0xFFE0)
assign wkup_in = wkup | {1\'b0, // Vector 13 (0xFFFA)
1\'b0, // Vector 12 (0xFFF8)
1\'b0, // Vector 11 (0xFFF6)
1\'b0, // Vector 10 (0xFFF4) - Watchdog -
1\'b0, // Vector 9 (0xFFF2)
1\'b0, // Vector 8 (0xFFF0)
1\'b0, // Vector 7 (0xFFEE)
1\'b0, // Vector 6 (0xFFEC)
1\'b0, // Vector 5 (0xFFEA)
1\'b0, // Vector 4 (0xFFE8)
1\'b0, // Vector 3 (0xFFE6)
1\'b0, // Vector 2 (0xFFE4)
1\'b0, // Vector 1 (0xFFE2)
1\'b0}; // Vector 0 (0xFFE0)
//
// I2C serial debug interface
//----------------------------------
// I2C Bus
//.........................
pullup dbg_scl_inst (dbg_scl);
pullup dbg_sda_inst (dbg_sda);
// I2C Slave (openMSP430)
//.........................
io_cell scl_slave_inst (
.pad (dbg_scl), // I/O pad
.data_in (dbg_scl_slave), // Input
.data_out_en (1\'b0), // Output enable
.data_out (1\'b0) // Output
);
io_cell sda_slave_inst (
.pad (dbg_sda), // I/O pad
.data_in (dbg_sda_slave_in), // Input
.data_out_en (!dbg_sda_slave_out), // Output enable
.data_out (1\'b0) // Output
);
// I2C Master (Debugger)
//.........................
io_cell scl_master_inst (
.pad (dbg_scl), // I/O pad
.data_in (), // Input
.data_out_en (!dbg_scl_master), // Output enable
.data_out (1\'b0) // Output
);
io_cell sda_master_inst (
.pad (dbg_sda), // I/O pad
.data_in (dbg_sda_master_in), // Input
.data_out_en (!dbg_sda_master_out), // Output enable
.data_out (1\'b0) // Output
);
//
// Debug utility signals
//----------------------------------------
msp_debug msp_debug_0 (
// OUTPUTs
.e_state (e_state), // Execution state
.i_state (i_state), // Instruction fetch state
.inst_cycle (inst_cycle), // Cycle number within current instruction
.inst_full (inst_full), // Currently executed instruction (full version)
.inst_number (inst_number), // Instruction number since last system reset
.inst_pc (inst_pc), // Instruction Program counter
.inst_short (inst_short), // Currently executed instruction (short version)
// INPUTs
.mclk (mclk), // Main system clock
.puc_rst (puc_rst) // Main system reset
);
//
// Generate Waveform
//----------------------------------------
initial
begin
`ifdef NODUMP
`else
`ifdef VPD_FILE
$vcdplusfile("tb_openMSP430.vpd");
$vcdpluson();
`else
`ifdef TRN_FILE
$recordfile ("tb_openMSP430.trn");
$recordvars;
`else
$dumpfile("tb_openMSP430.vcd");
$dumpvars(0, tb_openMSP430);
`endif
`endif
`endif
end
//
// End of simulation
//----------------------------------------
initial // Timeout
begin
`ifdef NO_TIMEOUT
`else
`ifdef VERY_LONG_TIMEOUT
#500000000;
`else
`ifdef LONG_TIMEOUT
#5000000;
`else
#500000;
`endif
`endif
$display(" ===============================================");
$display("| SIMULATION FAILED |");
$display("| (simulation Timeout) |");
$display(" ===============================================");
$display("");
tb_extra_report;
$finish;
`endif
end
initial // Normal end of test
begin
@(negedge stimulus_done);
wait(inst_pc==\'hffff);
$display(" ===============================================");
if ((dma_rd_error!=0) || (dma_wr_error!=0))
begin
$display("| SIMULATION FAILED |");
$display("| (some DMA transfer failed) |");
end
else if (error!=0)
begin
$display("| SIMULATION FAILED |");
$display("| (some verilog stimulus checks failed) |");
end
else if (~stimulus_done)
begin
$display("| SIMULATION FAILED |");
$display("| (the verilog stimulus didn\'t complete) |");
end
else
begin
$display("| SIMULATION PASSED |");
end
$display(" ===============================================");
$display("");
tb_extra_report;
$finish;
end
//
// Tasks Definition
//------------------------------
task tb_error;
input [65*8:0] error_string;
begin
$display("ERROR: %s %t", error_string, $time);
error = error+1;
end
endtask
task tb_extra_report;
begin
$display("DMA REPORT: Total Accesses: %-d Total RD: %-d Total WR: %-d", dma_cnt_rd+dma_cnt_wr, dma_cnt_rd, dma_cnt_wr);
$display(" Total Errors: %-d Error RD: %-d Error WR: %-d", dma_rd_error+dma_wr_error, dma_rd_error, dma_wr_error);
if (!((`PMEM_SIZE>=4092) && (`DMEM_SIZE>=1024)))
begin
\t $display("");
$display("Note: DMA if verification disabled (PMEM must be 4kB or bigger, DMEM must be 1kB or bigger)");
end
$display("");
$display("SIMULATION SEED: %d", `SEED);
$display("");
end
endtask
task tb_skip_finish;
input [65*8-1:0] skip_string;
begin
$display(" ===============================================");
$display("| SIMULATION SKIPPED |");
$display("%s", skip_string);
$display(" ===============================================");
$display("");
tb_extra_report;
$finish;
end
endtask
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: ram.v
//
// *Module Description:
// Scalable RAM model
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
module ram (
// OUTPUTs
ram_dout, // RAM data output
// INPUTs
ram_addr, // RAM address
ram_cen, // RAM chip enable (low active)
ram_clk, // RAM clock
ram_din, // RAM data input
ram_wen // RAM write enable (low active)
);
// PARAMETERs
//============
parameter ADDR_MSB = 6; // MSB of the address bus
parameter MEM_SIZE = 256; // Memory size in bytes
// OUTPUTs
//============
output [15:0] ram_dout; // RAM data output
// INPUTs
//============
input [ADDR_MSB:0] ram_addr; // RAM address
input ram_cen; // RAM chip enable (low active)
input ram_clk; // RAM clock
input [15:0] ram_din; // RAM data input
input [1:0] ram_wen; // RAM write enable (low active)
// RAM
//============
reg [15:0] mem [0:(MEM_SIZE/2)-1];
reg [ADDR_MSB:0] ram_addr_reg;
wire [15:0] mem_val = mem[ram_addr];
always @(posedge ram_clk)
if (~ram_cen & ram_addr<(MEM_SIZE/2))
begin
if (ram_wen==2'b00) mem[ram_addr] <= ram_din;
else if (ram_wen==2'b01) mem[ram_addr] <= {ram_din[15:8], mem_val[7:0]};
else if (ram_wen==2'b10) mem[ram_addr] <= {mem_val[15:8], ram_din[7:0]};
ram_addr_reg <= ram_addr;
end
assign ram_dout = mem[ram_addr_reg];
endmodule // ram
|
import "DPI-C" context function int initspi();
import "DPI-C" context function void writespi(input bit[7:0] in);
import "DPI-C" context function bit[7:0] readspi();
module simsd(input wire\t\tclk,
\t input wire\t\tcs,
\t input wire [31:0]\tbus_addr,
\t input wire [31:0]\tbus_wr_val,\t
\t input wire [3:0]\t\tbus_bytesel,
\t output reg\t\tbus_ack,
\t output reg [31:0]\tbus_data
);
reg [7:0] readval;
initial begin
\tbus_ack = 1\'b0;
\tbus_data = 32\'b0;
initspi();
end
always @(posedge clk) begin
bus_data <= 32\'b0;
if (cs && bus_bytesel[3:0] == 4\'b0001) begin
\t\tif (bus_addr[3:0] == 4\'b1000) begin
\t\t\twritespi(bus_wr_val[7:0]);
readval <= readspi();
\t\tend
end else if (cs) begin
\t\tif (bus_addr[3:0] == 4\'b1000) begin
\t\t\tbus_data <= {24\'b0, readval};
\t\tend
\t end
\tbus_ack <= cs;
end
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_dbg_i2c.v
//
// *Module Description:
// Debug I2C Slave communication interface
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module omsp_dbg_i2c (
// OUTPUTs
dbg_addr, // Debug register address
dbg_din, // Debug register data input
dbg_i2c_sda_out, // Debug interface: I2C SDA OUT
dbg_rd, // Debug register data read
dbg_wr, // Debug register data write
// INPUTs
dbg_clk, // Debug unit clock
dbg_dout, // Debug register data output
dbg_i2c_addr, // Debug interface: I2C ADDRESS
dbg_i2c_broadcast, // Debug interface: I2C Broadcast Address (for multicore systems)
dbg_i2c_scl, // Debug interface: I2C SCL
dbg_i2c_sda_in, // Debug interface: I2C SDA IN
dbg_rst, // Debug unit reset
mem_burst, // Burst on going
mem_burst_end, // End TX/RX burst
mem_burst_rd, // Start TX burst
mem_burst_wr, // Start RX burst
mem_bw // Burst byte width
);
// OUTPUTs
//=========
output [5:0] dbg_addr; // Debug register address
output [15:0] dbg_din; // Debug register data input
output dbg_i2c_sda_out; // Debug interface: I2C SDA OUT
output dbg_rd; // Debug register data read
output dbg_wr; // Debug register data write
// INPUTs
//=========
input dbg_clk; // Debug unit clock
input [15:0] dbg_dout; // Debug register data output
input [6:0] dbg_i2c_addr; // Debug interface: I2C ADDRESS
input [6:0] dbg_i2c_broadcast; // Debug interface: I2C Broadcast Address (for multicore systems)
input dbg_i2c_scl; // Debug interface: I2C SCL
input dbg_i2c_sda_in; // Debug interface: I2C SDA IN
input dbg_rst; // Debug unit reset
input mem_burst; // Burst on going
input mem_burst_end; // End TX/RX burst
input mem_burst_rd; // Start TX burst
input mem_burst_wr; // Start RX burst
input mem_bw; // Burst byte width
//=============================================================================
// 1) I2C RECEIVE LINE SYNCHRONIZTION & FILTERING
//=============================================================================
// Synchronize SCL/SDA inputs
//--------------------------------
wire scl_sync_n;
omsp_sync_cell sync_cell_i2c_scl (
.data_out (scl_sync_n),
.data_in (~dbg_i2c_scl),
.clk (dbg_clk),
.rst (dbg_rst)
);
wire scl_sync = ~scl_sync_n;
wire sda_in_sync_n;
omsp_sync_cell sync_cell_i2c_sda (
.data_out (sda_in_sync_n),
.data_in (~dbg_i2c_sda_in),
.clk (dbg_clk),
.rst (dbg_rst)
);
wire sda_in_sync = ~sda_in_sync_n;
// SCL/SDA input buffers
//--------------------------------
reg [1:0] scl_buf;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) scl_buf <= 2\'h3;
else scl_buf <= {scl_buf[0], scl_sync};
reg [1:0] sda_in_buf;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) sda_in_buf <= 2\'h3;
else sda_in_buf <= {sda_in_buf[0], sda_in_sync};
// SCL/SDA Majority decision
//------------------------------
wire scl = (scl_sync & scl_buf[0]) |
(scl_sync & scl_buf[1]) |
(scl_buf[0] & scl_buf[1]);
wire sda_in = (sda_in_sync & sda_in_buf[0]) |
(sda_in_sync & sda_in_buf[1]) |
(sda_in_buf[0] & sda_in_buf[1]);
// SCL/SDA Edge detection
//------------------------------
// SDA Edge detection
reg sda_in_dly;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) sda_in_dly <= 1\'b1;
else sda_in_dly <= sda_in;
wire sda_in_fe = sda_in_dly & ~sda_in;
wire sda_in_re = ~sda_in_dly & sda_in;
wire sda_in_edge = sda_in_dly ^ sda_in;
// SCL Edge detection
reg scl_dly;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) scl_dly <= 1\'b1;
else scl_dly <= scl;
wire scl_fe = scl_dly & ~scl;
wire scl_re = ~scl_dly & scl;
wire scl_edge = scl_dly ^ scl;
// Delayed SCL Rising-Edge for SDA data sampling
reg [1:0] scl_re_dly;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) scl_re_dly <= 2\'b00;
else scl_re_dly <= {scl_re_dly[0], scl_re};
wire scl_sample = scl_re_dly[1];
//=============================================================================
// 2) I2C START & STOP CONDITION DETECTION
//=============================================================================
//-----------------
// Start condition
//-----------------
wire start_detect = sda_in_fe & scl;
//-----------------
// Stop condition
//-----------------
wire stop_detect = sda_in_re & scl;
//-----------------
// I2C Slave Active
//-----------------
// The I2C logic will be activated whenever a start condition
// is detected and will be disactivated if the slave address
// doesn\'t match or if a stop condition is detected.
wire i2c_addr_not_valid;
reg i2c_active_seq;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) i2c_active_seq <= 1\'b0;
else if (start_detect) i2c_active_seq <= 1\'b1;
else if (stop_detect || i2c_addr_not_valid) i2c_active_seq <= 1\'b0;
wire i2c_active = i2c_active_seq & ~stop_detect;
wire i2c_init = ~i2c_active | start_detect;
//=============================================================================
// 3) I2C STATE MACHINE
//=============================================================================
// State register/wires
reg [2:0] i2c_state;
reg [2:0] i2c_state_nxt;
// Utility signals
reg [8:0] shift_buf;
wire shift_rx_done;
wire shift_tx_done;
reg dbg_rd;
// State machine definition
parameter RX_ADDR = 3\'h0;
parameter RX_ADDR_ACK = 3\'h1;
parameter RX_DATA = 3\'h2;
parameter RX_DATA_ACK = 3\'h3;
parameter TX_DATA = 3\'h4;
parameter TX_DATA_ACK = 3\'h5;
// State transition
always @(i2c_state or i2c_init or shift_rx_done or i2c_addr_not_valid or shift_tx_done or scl_fe or shift_buf or sda_in)
case (i2c_state)
RX_ADDR : i2c_state_nxt = i2c_init ? RX_ADDR :
~shift_rx_done ? RX_ADDR :
i2c_addr_not_valid ? RX_ADDR :
RX_ADDR_ACK;
RX_ADDR_ACK : i2c_state_nxt = i2c_init ? RX_ADDR :
~scl_fe ? RX_ADDR_ACK :
shift_buf[0] ? TX_DATA :
RX_DATA;
RX_DATA : i2c_state_nxt = i2c_init ? RX_ADDR :
~shift_rx_done ? RX_DATA :
RX_DATA_ACK;
RX_DATA_ACK : i2c_state_nxt = i2c_init ? RX_ADDR :
~scl_fe ? RX_DATA_ACK :
RX_DATA;
TX_DATA : i2c_state_nxt = i2c_init ? RX_ADDR :
~shift_tx_done ? TX_DATA :
TX_DATA_ACK;
TX_DATA_ACK : i2c_state_nxt = i2c_init ? RX_ADDR :
~scl_fe ? TX_DATA_ACK :
~sda_in ? TX_DATA :
RX_ADDR;
// pragma coverage off
default : i2c_state_nxt = RX_ADDR;
// pragma coverage on
endcase
// State machine
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) i2c_state <= RX_ADDR;
else i2c_state <= i2c_state_nxt;
//=============================================================================
// 4) I2C SHIFT REGISTER (FOR RECEIVING & TRANSMITING)
//=============================================================================
wire shift_rx_en = ((i2c_state==RX_ADDR) | (i2c_state ==RX_DATA) | (i2c_state ==RX_DATA_ACK));
wire shift_tx_en = (i2c_state ==TX_DATA) | (i2c_state ==TX_DATA_ACK);
wire shift_tx_en_pre = (i2c_state_nxt==TX_DATA) | (i2c_state_nxt==TX_DATA_ACK);
assign shift_rx_done = shift_rx_en & scl_fe & shift_buf[8];
assign shift_tx_done = shift_tx_en & scl_fe & (shift_buf==9\'h100);
wire shift_buf_rx_init = i2c_init | ((i2c_state==RX_ADDR_ACK) & scl_fe & ~shift_buf[0]) |
((i2c_state==RX_DATA_ACK) & scl_fe);
wire shift_buf_rx_en = shift_rx_en & scl_sample;
wire shift_buf_tx_init = ((i2c_state==RX_ADDR_ACK) & scl_re & shift_buf[0]) |
((i2c_state==TX_DATA_ACK) & scl_re);
wire shift_buf_tx_en = shift_tx_en_pre & scl_fe & (shift_buf!=9\'h100);
wire [7:0] shift_tx_val;
wire [8:0] shift_buf_nxt = shift_buf_rx_init ? 9\'h001 : // RX Init
shift_buf_tx_init ? {shift_tx_val, 1\'b1} : // TX Init
shift_buf_rx_en ? {shift_buf[7:0], sda_in} : // RX Shift
shift_buf_tx_en ? {shift_buf[7:0], 1\'b0} : // TX Shift
shift_buf[8:0]; // Hold
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) shift_buf <= 9\'h001;
else shift_buf <= shift_buf_nxt;
// Detect when the received I2C device address is not valid
assign i2c_addr_not_valid = (i2c_state == RX_ADDR) && shift_rx_done && (
`ifdef DBG_I2C_BROADCAST
(shift_buf[7:1] != dbg_i2c_broadcast[6:0]) &&
`endif
(shift_buf[7:1] != dbg_i2c_addr[6:0]));
`ifdef DBG_I2C_BROADCAST
`else
wire [6:0] UNUSED_dbg_i2c_broadcast = dbg_i2c_broadcast;
`endif
// Utility signals
wire shift_rx_data_done = shift_rx_done & (i2c_state==RX_DATA);
wire shift_tx_data_done = shift_tx_done;
//=============================================================================
// 5) I2C TRANSMIT BUFFER
//=============================================================================
reg dbg_i2c_sda_out;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_i2c_sda_out <= 1\'b1;
else if (scl_fe) dbg_i2c_sda_out <= ~((i2c_state_nxt==RX_ADDR_ACK) ||
(i2c_state_nxt==RX_DATA_ACK) ||
(shift_buf_tx_en & ~shift_buf[8]));
//=============================================================================
// 6) DEBUG INTERFACE STATE MACHINE
//=============================================================================
// State register/wires
reg [2:0] dbg_state;
reg [2:0] dbg_state_nxt;
// Utility signals
reg dbg_bw;
// State machine definition
parameter RX_CMD = 3\'h0;
parameter RX_BYTE_LO = 3\'h1;
parameter RX_BYTE_HI = 3\'h2;
parameter TX_BYTE_LO = 3\'h3;
parameter TX_BYTE_HI = 3\'h4;
// State transition
always @(dbg_state or shift_rx_data_done or shift_tx_data_done or shift_buf or dbg_bw or
mem_burst_wr or mem_burst_rd or mem_burst or mem_burst_end or mem_bw)
case (dbg_state)
RX_CMD : dbg_state_nxt = mem_burst_wr ? RX_BYTE_LO :
mem_burst_rd ? TX_BYTE_LO :
~shift_rx_data_done ? RX_CMD :
shift_buf[7] ? RX_BYTE_LO :
TX_BYTE_LO;
RX_BYTE_LO : dbg_state_nxt = (mem_burst & mem_burst_end) ? RX_CMD :
~shift_rx_data_done ? RX_BYTE_LO :
(mem_burst & ~mem_burst_end) ?
(mem_bw ? RX_BYTE_LO :
RX_BYTE_HI) :
dbg_bw ? RX_CMD :
RX_BYTE_HI;
RX_BYTE_HI : dbg_state_nxt = ~shift_rx_data_done ? RX_BYTE_HI :
(mem_burst & ~mem_burst_end) ? RX_BYTE_LO :
RX_CMD;
TX_BYTE_LO : dbg_state_nxt = ~shift_tx_data_done ? TX_BYTE_LO :
( mem_burst & mem_bw) ? TX_BYTE_LO :
( mem_burst & ~mem_bw) ? TX_BYTE_HI :
~dbg_bw ? TX_BYTE_HI :
RX_CMD;
TX_BYTE_HI : dbg_state_nxt = ~shift_tx_data_done ? TX_BYTE_HI :
mem_burst ? TX_BYTE_LO :
RX_CMD;
// pragma coverage off
default : dbg_state_nxt = RX_CMD;
// pragma coverage on
endcase
// State machine
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_state <= RX_CMD;
else dbg_state <= dbg_state_nxt;
// Utility signals
wire cmd_valid = (dbg_state==RX_CMD) & shift_rx_data_done;
wire rx_lo_valid = (dbg_state==RX_BYTE_LO) & shift_rx_data_done;
wire rx_hi_valid = (dbg_state==RX_BYTE_HI) & shift_rx_data_done;
//=============================================================================
// 7) REGISTER READ/WRITE ACCESS
//=============================================================================
parameter MEM_DATA = 6\'h06;
// Debug register address & bit width
reg [5:0] dbg_addr;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst)
begin
dbg_bw <= 1\'b0;
dbg_addr <= 6\'h00;
end
else if (cmd_valid)
begin
dbg_bw <= shift_buf[6];
dbg_addr <= shift_buf[5:0];
end
else if (mem_burst)
begin
dbg_bw <= mem_bw;
dbg_addr <= MEM_DATA;
end
// Debug register data input
reg [7:0] dbg_din_lo;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_din_lo <= 8\'h00;
else if (rx_lo_valid) dbg_din_lo <= shift_buf[7:0];
reg [7:0] dbg_din_hi;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_din_hi <= 8\'h00;
else if (rx_lo_valid) dbg_din_hi <= 8\'h00;
else if (rx_hi_valid) dbg_din_hi <= shift_buf[7:0];
assign dbg_din = {dbg_din_hi, dbg_din_lo};
// Debug register data write command
reg dbg_wr;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_wr <= 1\'b0;
else dbg_wr <= (mem_burst & mem_bw) ? rx_lo_valid :
(mem_burst & ~mem_bw) ? rx_hi_valid :
dbg_bw ? rx_lo_valid :
rx_hi_valid;
// Debug register data read command
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_rd <= 1\'b0;
else dbg_rd <= (mem_burst & mem_bw) ? (shift_tx_data_done & (dbg_state==TX_BYTE_LO)) :
(mem_burst & ~mem_bw) ? (shift_tx_data_done & (dbg_state==TX_BYTE_HI)) :
cmd_valid ? ~shift_buf[7] :
1\'b0;
// Debug register data read value
assign shift_tx_val = (dbg_state==TX_BYTE_HI) ? dbg_dout[15:8] :
dbg_dout[7:0];
endmodule
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_timerA.v
//
// *Module Description:
// Timer A top-level
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OMSP_TA_NO_INCLUDE
`else
`include "omsp_timerA_defines.v"
`endif
module omsp_timerA (
// OUTPUTs
irq_ta0, // Timer A interrupt: TACCR0
irq_ta1, // Timer A interrupt: TAIV, TACCR1, TACCR2
per_dout, // Peripheral data output
ta_out0, // Timer A output 0
ta_out0_en, // Timer A output 0 enable
ta_out1, // Timer A output 1
ta_out1_en, // Timer A output 1 enable
ta_out2, // Timer A output 2
ta_out2_en, // Timer A output 2 enable
// INPUTs
aclk_en, // ACLK enable (from CPU)
dbg_freeze, // Freeze Timer A counter
inclk, // INCLK external timer clock (SLOW)
irq_ta0_acc, // Interrupt request TACCR0 accepted
mclk, // Main system clock
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_we, // Peripheral write enable (high active)
puc_rst, // Main system reset
smclk_en, // SMCLK enable (from CPU)
ta_cci0a, // Timer A capture 0 input A
ta_cci0b, // Timer A capture 0 input B
ta_cci1a, // Timer A capture 1 input A
ta_cci1b, // Timer A capture 1 input B
ta_cci2a, // Timer A capture 2 input A
ta_cci2b, // Timer A capture 2 input B
taclk // TACLK external timer clock (SLOW)
);
// OUTPUTs
//=========
output irq_ta0; // Timer A interrupt: TACCR0
output irq_ta1; // Timer A interrupt: TAIV, TACCR1, TACCR2
output [15:0] per_dout; // Peripheral data output
output ta_out0; // Timer A output 0
output ta_out0_en; // Timer A output 0 enable
output ta_out1; // Timer A output 1
output ta_out1_en; // Timer A output 1 enable
output ta_out2; // Timer A output 2
output ta_out2_en; // Timer A output 2 enable
// INPUTs
//=========
input aclk_en; // ACLK enable (from CPU)
input dbg_freeze; // Freeze Timer A counter
input inclk; // INCLK external timer clock (SLOW)
input irq_ta0_acc; // Interrupt request TACCR0 accepted
input mclk; // Main system clock
input [13:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input puc_rst; // Main system reset
input smclk_en; // SMCLK enable (from CPU)
input ta_cci0a; // Timer A capture 0 input A
input ta_cci0b; // Timer A capture 0 input B
input ta_cci1a; // Timer A capture 1 input A
input ta_cci1b; // Timer A capture 1 input B
input ta_cci2a; // Timer A capture 2 input A
input ta_cci2b; // Timer A capture 2 input B
input taclk; // TACLK external timer clock (SLOW)
//=============================================================================
// 1) PARAMETER DECLARATION
//=============================================================================
// Register base address (must be aligned to decoder bit width)
parameter [14:0] BASE_ADDR = 15\'h0100;
// Decoder bit width (defines how many bits are considered for address decoding)
parameter DEC_WD = 7;
// Register addresses offset
parameter [DEC_WD-1:0] TACTL = \'h60,
TAR = \'h70,
TACCTL0 = \'h62,
TACCR0 = \'h72,
TACCTL1 = \'h64,
TACCR1 = \'h74,
TACCTL2 = \'h66,
TACCR2 = \'h76,
TAIV = \'h2E;
// Register one-hot decoder utilities
parameter DEC_SZ = (1 << DEC_WD);
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1\'b0}}, 1\'b1};
// Register one-hot decoder
parameter [DEC_SZ-1:0] TACTL_D = (BASE_REG << TACTL),
TAR_D = (BASE_REG << TAR),
TACCTL0_D = (BASE_REG << TACCTL0),
TACCR0_D = (BASE_REG << TACCR0),
TACCTL1_D = (BASE_REG << TACCTL1),
TACCR1_D = (BASE_REG << TACCR1),
TACCTL2_D = (BASE_REG << TACCTL2),
TACCR2_D = (BASE_REG << TACCR2),
TAIV_D = (BASE_REG << TAIV);
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Local register selection
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
// Register local address
wire [DEC_WD-1:0] reg_addr = {per_addr[DEC_WD-2:0], 1\'b0};
// Register address decode
wire [DEC_SZ-1:0] reg_dec = (TACTL_D & {DEC_SZ{(reg_addr == TACTL )}}) |
(TAR_D & {DEC_SZ{(reg_addr == TAR )}}) |
(TACCTL0_D & {DEC_SZ{(reg_addr == TACCTL0 )}}) |
(TACCR0_D & {DEC_SZ{(reg_addr == TACCR0 )}}) |
(TACCTL1_D & {DEC_SZ{(reg_addr == TACCTL1 )}}) |
(TACCR1_D & {DEC_SZ{(reg_addr == TACCR1 )}}) |
(TACCTL2_D & {DEC_SZ{(reg_addr == TACCTL2 )}}) |
(TACCR2_D & {DEC_SZ{(reg_addr == TACCR2 )}}) |
(TAIV_D & {DEC_SZ{(reg_addr == TAIV )}});
// Read/Write probes
wire reg_write = |per_we & reg_sel;
wire reg_read = ~|per_we & reg_sel;
// Read/Write vectors
wire [DEC_SZ-1:0] reg_wr = reg_dec & {512{reg_write}};
wire [DEC_SZ-1:0] reg_rd = reg_dec & {512{reg_read}};
//============================================================================
// 3) REGISTERS
//============================================================================
// TACTL Register
//-----------------
reg [9:0] tactl;
wire tactl_wr = reg_wr[TACTL];
wire taclr = tactl_wr & per_din[`TACLR];
wire taifg_set;
wire taifg_clr;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) tactl <= 10\'h000;
else if (tactl_wr) tactl <= ((per_din[9:0] & 10\'h3f3) | {9\'h000, taifg_set}) & {9\'h1ff, ~taifg_clr};
else tactl <= (tactl | {9\'h000, taifg_set}) & {9\'h1ff, ~taifg_clr};
// TAR Register
//-----------------
reg [15:0] tar;
wire tar_wr = reg_wr[TAR];
wire tar_clk;
wire tar_clr;
wire tar_inc;
wire tar_dec;
wire [15:0] tar_add = tar_inc ? 16\'h0001 :
tar_dec ? 16\'hffff : 16\'h0000;
wire [15:0] tar_nxt = tar_clr ? 16\'h0000 : (tar+tar_add);
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) tar <= 16\'h0000;
else if (tar_wr) tar <= per_din;
else if (taclr) tar <= 16\'h0000;
else if (tar_clk & ~dbg_freeze) tar <= tar_nxt;
// TACCTL0 Register
//------------------
reg [15:0] tacctl0;
wire tacctl0_wr = reg_wr[TACCTL0];
wire ccifg0_set;
wire cov0_set;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) tacctl0 <= 16\'h0000;
else if (tacctl0_wr) tacctl0 <= ((per_din & 16\'hf9f7) | {14\'h0000, cov0_set, ccifg0_set}) & {15\'h7fff, ~irq_ta0_acc};
else tacctl0 <= (tacctl0 | {14\'h0000, cov0_set, ccifg0_set}) & {15\'h7fff, ~irq_ta0_acc};
wire cci0;
wire cci0_s;
reg scci0;
wire [15:0] tacctl0_full = tacctl0 | {5\'h00, scci0, 6\'h00, cci0_s, 3\'h0};
// TACCR0 Register
//------------------
reg [15:0] taccr0;
wire taccr0_wr = reg_wr[TACCR0];
wire cci0_cap;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) taccr0 <= 16\'h0000;
else if (taccr0_wr) taccr0 <= per_din;
else if (cci0_cap) taccr0 <= tar;
// TACCTL1 Register
//------------------
reg [15:0] tacctl1;
wire tacctl1_wr = reg_wr[TACCTL1];
wire ccifg1_set;
wire ccifg1_clr;
wire cov1_set;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) tacctl1 <= 16\'h0000;
else if (tacctl1_wr) tacctl1 <= ((per_din & 16\'hf9f7) | {14\'h0000, cov1_set, ccifg1_set}) & {15\'h7fff, ~ccifg1_clr};
else tacctl1 <= (tacctl1 | {14\'h0000, cov1_set, ccifg1_set}) & {15\'h7fff, ~ccifg1_clr};
wire cci1;
wire cci1_s;
reg scci1;
wire [15:0] tacctl1_full = tacctl1 | {5\'h00, scci1, 6\'h00, cci1_s, 3\'h0};
// TACCR1 Register
//------------------
reg [15:0] taccr1;
wire taccr1_wr = reg_wr[TACCR1];
wire cci1_cap;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) taccr1 <= 16\'h0000;
else if (taccr1_wr) taccr1 <= per_din;
else if (cci1_cap) taccr1 <= tar;
// TACCTL2 Register
//------------------
reg [15:0] tacctl2;
wire tacctl2_wr = reg_wr[TACCTL2];
wire ccifg2_set;
wire ccifg2_clr;
wire cov2_set;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) tacctl2 <= 16\'h0000;
else if (tacctl2_wr) tacctl2 <= ((per_din & 16\'hf9f7) | {14\'h0000, cov2_set, ccifg2_set}) & {15\'h7fff, ~ccifg2_clr};
else tacctl2 <= (tacctl2 | {14\'h0000, cov2_set, ccifg2_set}) & {15\'h7fff, ~ccifg2_clr};
wire cci2;
wire cci2_s;
reg scci2;
wire [15:0] tacctl2_full = tacctl2 | {5\'h00, scci2, 6\'h00, cci2_s, 3\'h0};
// TACCR2 Register
//------------------
reg [15:0] taccr2;
wire taccr2_wr = reg_wr[TACCR2];
wire cci2_cap;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) taccr2 <= 16\'h0000;
else if (taccr2_wr) taccr2 <= per_din;
else if (cci2_cap) taccr2 <= tar;
// TAIV Register
//------------------
wire [3:0] taiv = (tacctl1[`TACCIFG] & tacctl1[`TACCIE]) ? 4\'h2 :
(tacctl2[`TACCIFG] & tacctl2[`TACCIE]) ? 4\'h4 :
(tactl[`TAIFG] & tactl[`TAIE]) ? 4\'hA :
4\'h0;
assign ccifg1_clr = (reg_rd[TAIV] | reg_wr[TAIV]) & (taiv==4\'h2);
assign ccifg2_clr = (reg_rd[TAIV] | reg_wr[TAIV]) & (taiv==4\'h4);
assign taifg_clr = (reg_rd[TAIV] | reg_wr[TAIV]) & (taiv==4\'hA);
//============================================================================
// 4) DATA OUTPUT GENERATION
//============================================================================
// Data output mux
wire [15:0] tactl_rd = {6\'h00, tactl} & {16{reg_rd[TACTL]}};
wire [15:0] tar_rd = tar & {16{reg_rd[TAR]}};
wire [15:0] tacctl0_rd = tacctl0_full & {16{reg_rd[TACCTL0]}};
wire [15:0] taccr0_rd = taccr0 & {16{reg_rd[TACCR0]}};
wire [15:0] tacctl1_rd = tacctl1_full & {16{reg_rd[TACCTL1]}};
wire [15:0] taccr1_rd = taccr1 & {16{reg_rd[TACCR1]}};
wire [15:0] tacctl2_rd = tacctl2_full & {16{reg_rd[TACCTL2]}};
wire [15:0] taccr2_rd = taccr2 & {16{reg_rd[TACCR2]}};
wire [15:0] taiv_rd = {12\'h000, taiv} & {16{reg_rd[TAIV]}};
wire [15:0] per_dout = tactl_rd |
tar_rd |
tacctl0_rd |
taccr0_rd |
tacctl1_rd |
taccr1_rd |
tacctl2_rd |
taccr2_rd |
taiv_rd;
//============================================================================
// 5) Timer A counter control
//============================================================================
// Clock input synchronization (TACLK & INCLK)
//-----------------------------------------------------------
wire taclk_s;
wire inclk_s;
omsp_sync_cell sync_cell_taclk (
.data_out (taclk_s),
.data_in (taclk),
.clk (mclk),
.rst (puc_rst)
);
omsp_sync_cell sync_cell_inclk (
.data_out (inclk_s),
.data_in (inclk),
.clk (mclk),
.rst (puc_rst)
);
// Clock edge detection (TACLK & INCLK)
//-----------------------------------------------------------
reg taclk_dly;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) taclk_dly <= 1\'b0;
else taclk_dly <= taclk_s;
wire taclk_en = taclk_s & ~taclk_dly;
reg inclk_dly;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) inclk_dly <= 1\'b0;
else inclk_dly <= inclk_s;
wire inclk_en = inclk_s & ~inclk_dly;
// Timer clock input mux
//-----------------------------------------------------------
wire sel_clk = (tactl[`TASSELx]==2\'b00) ? taclk_en :
(tactl[`TASSELx]==2\'b01) ? aclk_en :
(tactl[`TASSELx]==2\'b10) ? smclk_en : inclk_en;
// Generate update pluse for the counter (<=> divided clock)
//-----------------------------------------------------------
reg [2:0] clk_div;
assign tar_clk = sel_clk & ((tactl[`TAIDx]==2\'b00) ? 1\'b1 :
(tactl[`TAIDx]==2\'b01) ? clk_div[0] :
(tactl[`TAIDx]==2\'b10) ? &clk_div[1:0] :
&clk_div[2:0]);
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) clk_div <= 3\'h0;
else if (tar_clk | taclr) clk_div <= 3\'h0;
else if ((tactl[`TAMCx]!=2\'b00) & sel_clk) clk_div <= clk_div+3\'h1;
// Time counter control signals
//-----------------------------------------------------------
assign tar_clr = ((tactl[`TAMCx]==2\'b01) & (tar>=taccr0)) |
((tactl[`TAMCx]==2\'b11) & (taccr0==16\'h0000));
assign tar_inc = (tactl[`TAMCx]==2\'b01) | (tactl[`TAMCx]==2\'b10) |
((tactl[`TAMCx]==2\'b11) & ~tar_dec);
reg tar_dir;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) tar_dir <= 1\'b0;
else if (taclr) tar_dir <= 1\'b0;
else if (tactl[`TAMCx]==2\'b11)
begin
if (tar_clk & (tar==16\'h0001)) tar_dir <= 1\'b0;
else if (tar>=taccr0) tar_dir <= 1\'b1;
end
else tar_dir <= 1\'b0;
assign tar_dec = tar_dir | ((tactl[`TAMCx]==2\'b11) & (tar>=taccr0));
//============================================================================
// 6) Timer A comparator
//============================================================================
wire equ0 = (tar_nxt==taccr0) & (tar!=taccr0);
wire equ1 = (tar_nxt==taccr1) & (tar!=taccr1);
wire equ2 = (tar_nxt==taccr2) & (tar!=taccr2);
//============================================================================
// 7) Timer A capture logic
//============================================================================
// Input selection
//------------------
assign cci0 = (tacctl0[`TACCISx]==2\'b00) ? ta_cci0a :
(tacctl0[`TACCISx]==2\'b01) ? ta_cci0b :
(tacctl0[`TACCISx]==2\'b10) ? 1\'b0 : 1\'b1;
assign cci1 = (tacctl1[`TACCISx]==2\'b00) ? ta_cci1a :
(tacctl1[`TACCISx]==2\'b01) ? ta_cci1b :
(tacctl1[`TACCISx]==2\'b10) ? 1\'b0 : 1\'b1;
assign cci2 = (tacctl2[`TACCISx]==2\'b00) ? ta_cci2a :
(tacctl2[`TACCISx]==2\'b01) ? ta_cci2b :
(tacctl2[`TACCISx]==2\'b10) ? 1\'b0 : 1\'b1;
// CCIx synchronization
omsp_sync_cell sync_cell_cci0 (
.data_out (cci0_s),
.data_in (cci0),
.clk (mclk),
.rst (puc_rst)
);
omsp_sync_cell sync_cell_cci1 (
.data_out (cci1_s),
.data_in (cci1),
.clk (mclk),
.rst (puc_rst)
);
omsp_sync_cell sync_cell_cci2 (
.data_out (cci2_s),
.data_in (cci2),
.clk (mclk),
.rst (puc_rst)
);
// Register CCIx for edge detection
reg cci0_dly;
reg cci1_dly;
reg cci2_dly;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst)
begin
cci0_dly <= 1\'b0;
cci1_dly <= 1\'b0;
cci2_dly <= 1\'b0;
end
else
begin
cci0_dly <= cci0_s;
cci1_dly <= cci1_s;
cci2_dly <= cci2_s;
end
// Generate SCCIx
//------------------
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) scci0 <= 1\'b0;
else if (tar_clk & equ0) scci0 <= cci0_s;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) scci1 <= 1\'b0;
else if (tar_clk & equ1) scci1 <= cci1_s;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) scci2 <= 1\'b0;
else if (tar_clk & equ2) scci2 <= cci2_s;
// Capture mode
//------------------
wire cci0_evt = (tacctl0[`TACMx]==2\'b00) ? 1\'b0 :
(tacctl0[`TACMx]==2\'b01) ? ( cci0_s & ~cci0_dly) : // Rising edge
(tacctl0[`TACMx]==2\'b10) ? (~cci0_s & cci0_dly) : // Falling edge
( cci0_s ^ cci0_dly); // Both edges
wire cci1_evt = (tacctl1[`TACMx]==2\'b00) ? 1\'b0 :
(tacctl1[`TACMx]==2\'b01) ? ( cci1_s & ~cci1_dly) : // Rising edge
(tacctl1[`TACMx]==2\'b10) ? (~cci1_s & cci1_dly) : // Falling edge
( cci1_s ^ cci1_dly); // Both edges
wire cci2_evt = (tacctl2[`TACMx]==2\'b00) ? 1\'b0 :
(tacctl2[`TACMx]==2\'b01) ? ( cci2_s & ~cci2_dly) : // Rising edge
(tacctl2[`TACMx]==2\'b10) ? (~cci2_s & cci2_dly) : // Falling edge
( cci2_s ^ cci2_dly); // Both edges
// Event Synchronization
//-----------------------
reg cci0_evt_s;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cci0_evt_s <= 1\'b0;
else if (tar_clk) cci0_evt_s <= 1\'b0;
else if (cci0_evt) cci0_evt_s <= 1\'b1;
reg cci1_evt_s;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cci1_evt_s <= 1\'b0;
else if (tar_clk) cci1_evt_s <= 1\'b0;
else if (cci1_evt) cci1_evt_s <= 1\'b1;
reg cci2_evt_s;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cci2_evt_s <= 1\'b0;
else if (tar_clk) cci2_evt_s <= 1\'b0;
else if (cci2_evt) cci2_evt_s <= 1\'b1;
reg cci0_sync;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cci0_sync <= 1\'b0;
else cci0_sync <= (tar_clk & cci0_evt_s) | (tar_clk & cci0_evt & ~cci0_evt_s);
reg cci1_sync;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cci1_sync <= 1\'b0;
else cci1_sync <= (tar_clk & cci1_evt_s) | (tar_clk & cci1_evt & ~cci1_evt_s);
reg cci2_sync;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cci2_sync <= 1\'b0;
else cci2_sync <= (tar_clk & cci2_evt_s) | (tar_clk & cci2_evt & ~cci2_evt_s);
// Generate final capture command
//-----------------------------------
assign cci0_cap = tacctl0[`TASCS] ? cci0_sync : cci0_evt;
assign cci1_cap = tacctl1[`TASCS] ? cci1_sync : cci1_evt;
assign cci2_cap = tacctl2[`TASCS] ? cci2_sync : cci2_evt;
// Generate capture overflow flag
//-----------------------------------
reg cap0_taken;
wire cap0_taken_clr = reg_rd[TACCR0] | (tacctl0_wr & tacctl0[`TACOV] & ~per_din[`TACOV]);
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cap0_taken <= 1\'b0;
else if (cci0_cap) cap0_taken <= 1\'b1;
else if (cap0_taken_clr) cap0_taken <= 1\'b0;
reg cap1_taken;
wire cap1_taken_clr = reg_rd[TACCR1] | (tacctl1_wr & tacctl1[`TACOV] & ~per_din[`TACOV]);
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cap1_taken <= 1\'b0;
else if (cci1_cap) cap1_taken <= 1\'b1;
else if (cap1_taken_clr) cap1_taken <= 1\'b0;
reg cap2_taken;
wire cap2_taken_clr = reg_rd[TACCR2] | (tacctl2_wr & tacctl2[`TACOV] & ~per_din[`TACOV]);
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cap2_taken <= 1\'b0;
else if (cci2_cap) cap2_taken <= 1\'b1;
else if (cap2_taken_clr) cap2_taken <= 1\'b0;
assign cov0_set = cap0_taken & cci0_cap & ~reg_rd[TACCR0];
assign cov1_set = cap1_taken & cci1_cap & ~reg_rd[TACCR1];
assign cov2_set = cap2_taken & cci2_cap & ~reg_rd[TACCR2];
//============================================================================
// 8) Timer A output unit
//============================================================================
// Output unit 0
//-------------------
reg ta_out0;
wire ta_out0_mode0 = tacctl0[`TAOUT]; // Output
wire ta_out0_mode1 = equ0 ? 1\'b1 : ta_out0; // Set
wire ta_out0_mode2 = equ0 ? ~ta_out0 : // Toggle/Reset
equ0 ? 1\'b0 : ta_out0;
wire ta_out0_mode3 = equ0 ? 1\'b1 : // Set/Reset
equ0 ? 1\'b0 : ta_out0;
wire ta_out0_mode4 = equ0 ? ~ta_out0 : ta_out0; // Toggle
wire ta_out0_mode5 = equ0 ? 1\'b0 : ta_out0; // Reset
wire ta_out0_mode6 = equ0 ? ~ta_out0 : // Toggle/Set
equ0 ? 1\'b1 : ta_out0;
wire ta_out0_mode7 = equ0 ? 1\'b0 : // Reset/Set
equ0 ? 1\'b1 : ta_out0;
wire ta_out0_nxt = (tacctl0[`TAOUTMODx]==3\'b000) ? ta_out0_mode0 :
(tacctl0[`TAOUTMODx]==3\'b001) ? ta_out0_mode1 :
(tacctl0[`TAOUTMODx]==3\'b010) ? ta_out0_mode2 :
(tacctl0[`TAOUTMODx]==3\'b011) ? ta_out0_mode3 :
(tacctl0[`TAOUTMODx]==3\'b100) ? ta_out0_mode4 :
(tacctl0[`TAOUTMODx]==3\'b101) ? ta_out0_mode5 :
(tacctl0[`TAOUTMODx]==3\'b110) ? ta_out0_mode6 :
ta_out0_mode7;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) ta_out0 <= 1\'b0;
else if ((tacctl0[`TAOUTMODx]==3\'b001) & taclr) ta_out0 <= 1\'b0;
else if (tar_clk) ta_out0 <= ta_out0_nxt;
assign ta_out0_en = ~tacctl0[`TACAP];
// Output unit 1
//-------------------
reg ta_out1;
wire ta_out1_mode0 = tacctl1[`TAOUT]; // Output
wire ta_out1_mode1 = equ1 ? 1\'b1 : ta_out1; // Set
wire ta_out1_mode2 = equ1 ? ~ta_out1 : // Toggle/Reset
equ0 ? 1\'b0 : ta_out1;
wire ta_out1_mode3 = equ1 ? 1\'b1 : // Set/Reset
equ0 ? 1\'b0 : ta_out1;
wire ta_out1_mode4 = equ1 ? ~ta_out1 : ta_out1; // Toggle
wire ta_out1_mode5 = equ1 ? 1\'b0 : ta_out1; // Reset
wire ta_out1_mode6 = equ1 ? ~ta_out1 : // Toggle/Set
equ0 ? 1\'b1 : ta_out1;
wire ta_out1_mode7 = equ1 ? 1\'b0 : // Reset/Set
equ0 ? 1\'b1 : ta_out1;
wire ta_out1_nxt = (tacctl1[`TAOUTMODx]==3\'b000) ? ta_out1_mode0 :
(tacctl1[`TAOUTMODx]==3\'b001) ? ta_out1_mode1 :
(tacctl1[`TAOUTMODx]==3\'b010) ? ta_out1_mode2 :
(tacctl1[`TAOUTMODx]==3\'b011) ? ta_out1_mode3 :
(tacctl1[`TAOUTMODx]==3\'b100) ? ta_out1_mode4 :
(tacctl1[`TAOUTMODx]==3\'b101) ? ta_out1_mode5 :
(tacctl1[`TAOUTMODx]==3\'b110) ? ta_out1_mode6 :
ta_out1_mode7;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) ta_out1 <= 1\'b0;
else if ((tacctl1[`TAOUTMODx]==3\'b001) & taclr) ta_out1 <= 1\'b0;
else if (tar_clk) ta_out1 <= ta_out1_nxt;
assign ta_out1_en = ~tacctl1[`TACAP];
// Output unit 2
//-------------------
reg ta_out2;
wire ta_out2_mode0 = tacctl2[`TAOUT]; // Output
wire ta_out2_mode1 = equ2 ? 1\'b1 : ta_out2; // Set
wire ta_out2_mode2 = equ2 ? ~ta_out2 : // Toggle/Reset
equ0 ? 1\'b0 : ta_out2;
wire ta_out2_mode3 = equ2 ? 1\'b1 : // Set/Reset
equ0 ? 1\'b0 : ta_out2;
wire ta_out2_mode4 = equ2 ? ~ta_out2 : ta_out2; // Toggle
wire ta_out2_mode5 = equ2 ? 1\'b0 : ta_out2; // Reset
wire ta_out2_mode6 = equ2 ? ~ta_out2 : // Toggle/Set
equ0 ? 1\'b1 : ta_out2;
wire ta_out2_mode7 = equ2 ? 1\'b0 : // Reset/Set
equ0 ? 1\'b1 : ta_out2;
wire ta_out2_nxt = (tacctl2[`TAOUTMODx]==3\'b000) ? ta_out2_mode0 :
(tacctl2[`TAOUTMODx]==3\'b001) ? ta_out2_mode1 :
(tacctl2[`TAOUTMODx]==3\'b010) ? ta_out2_mode2 :
(tacctl2[`TAOUTMODx]==3\'b011) ? ta_out2_mode3 :
(tacctl2[`TAOUTMODx]==3\'b100) ? ta_out2_mode4 :
(tacctl2[`TAOUTMODx]==3\'b101) ? ta_out2_mode5 :
(tacctl2[`TAOUTMODx]==3\'b110) ? ta_out2_mode6 :
ta_out2_mode7;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) ta_out2 <= 1\'b0;
else if ((tacctl2[`TAOUTMODx]==3\'b001) & taclr) ta_out2 <= 1\'b0;
else if (tar_clk) ta_out2 <= ta_out2_nxt;
assign ta_out2_en = ~tacctl2[`TACAP];
//============================================================================
// 9) Timer A interrupt generation
//============================================================================
assign taifg_set = tar_clk & (((tactl[`TAMCx]==2\'b01) & (tar==taccr0)) |
((tactl[`TAMCx]==2\'b10) & (tar==16\'hffff)) |
((tactl[`TAMCx]==2\'b11) & (tar_nxt==16\'h0000) & tar_dec));
assign ccifg0_set = tacctl0[`TACAP] ? cci0_cap : (tar_clk & ((tactl[`TAMCx]!=2\'b00) & equ0));
assign ccifg1_set = tacctl1[`TACAP] ? cci1_cap : (tar_clk & ((tactl[`TAMCx]!=2\'b00) & equ1));
assign ccifg2_set = tacctl2[`TACAP] ? cci2_cap : (tar_clk & ((tactl[`TAMCx]!=2\'b00) & equ2));
wire irq_ta0 = (tacctl0[`TACCIFG] & tacctl0[`TACCIE]);
wire irq_ta1 = (tactl[`TAIFG] & tactl[`TAIE]) |
(tacctl1[`TACCIFG] & tacctl1[`TACCIE]) |
(tacctl2[`TACCIFG] & tacctl2[`TACCIE]);
endmodule // omsp_timerA
`ifdef OMSP_TA_NO_INCLUDE
`else
`include "omsp_timerA_undefines.v"
`endif
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_wakeup_cell.v
//
// *Module Description:
// Generic Wakeup cell
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module omsp_wakeup_cell (
// OUTPUTs
wkup_out, // Wakup signal (asynchronous)
// INPUTs
scan_clk, // Scan clock
scan_mode, // Scan mode
scan_rst, // Scan reset
wkup_clear, // Glitch free wakeup event clear
wkup_event // Glitch free asynchronous wakeup event
);
// OUTPUTs
//=========
output wkup_out; // Wakup signal (asynchronous)
// INPUTs
//=========
input scan_clk; // Scan clock
input scan_mode; // Scan mode
input scan_rst; // Scan reset
input wkup_clear; // Glitch free wakeup event clear
input wkup_event; // Glitch free asynchronous wakeup event
//=============================================================================
// 1) AND GATE
//=============================================================================
// Scan stuff for the ASIC mode
`ifdef ASIC
wire wkup_rst;
omsp_scan_mux scan_mux_rst (
.scan_mode (scan_mode),
.data_in_scan (scan_rst),
.data_in_func (wkup_clear),
.data_out (wkup_rst)
);
wire wkup_clk;
omsp_scan_mux scan_mux_clk (
.scan_mode (scan_mode),
.data_in_scan (scan_clk),
.data_in_func (wkup_event),
.data_out (wkup_clk)
);
`else
wire wkup_rst = wkup_clear;
wire wkup_clk = wkup_event;
`endif
// Wakeup capture
reg wkup_out;
always @(posedge wkup_clk or posedge wkup_rst)
if (wkup_rst) wkup_out <= 1\'b0;
else wkup_out <= 1\'b1;
endmodule // omsp_wakeup_cell
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: dbg_i2c_tasks.v
//
// *Module Description:
// openMSP430 debug interface I2C tasks
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 17 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// I2C COMMUNICATION CONFIGURATION
//----------------------------------------------------------------------------
// Data rate
parameter I2C_FREQ = 2000000;
integer I2C_PERIOD = 1000000000/I2C_FREQ;
// Address
parameter I2C_ADDR = 7\'h45;
parameter I2C_BROADCAST = 7\'h67;
//----------------------------------------------------------------------------
// Generate START / STOP conditions
//----------------------------------------------------------------------------
task dbg_i2c_start;
begin
dbg_i2c_string = "Start";
dbg_sda_master_out_pre = 1\'b0;
#(I2C_PERIOD/2);
dbg_scl_master_pre = 1\'b0;
#(I2C_PERIOD/4);
dbg_i2c_string = "";
end
endtask
task dbg_i2c_stop;
begin
dbg_i2c_string = "Stop";
dbg_sda_master_out_pre = 1\'b0;
#(I2C_PERIOD/4);
dbg_scl_master_pre = 1\'b1;
#(I2C_PERIOD/4);
dbg_sda_master_out_pre = 1\'b1;
#(I2C_PERIOD/2);
dbg_i2c_string = "";
end
endtask
//----------------------------------------------------------------------------
// Send a byte on the I2C bus
//----------------------------------------------------------------------------
task dbg_i2c_send;
input [7:0] txbuf;
reg [9:0] \ttxbuf_full;
integer \ttxcnt;
begin
#(1);
txbuf_full = txbuf;
for (txcnt = 0; txcnt < 8; txcnt = txcnt + 1)
\tbegin
\t $sformat(dbg_i2c_string, "TX_%-d", txcnt);
\t dbg_sda_master_out_pre = txbuf_full[7-txcnt];
\t #(I2C_PERIOD/4);
\t dbg_scl_master_pre = 1\'b1;
\t #(I2C_PERIOD/2);
\t dbg_scl_master_pre = 1\'b0;
\t #(I2C_PERIOD/4);
\tend
dbg_sda_master_out_pre = 1\'b1;
dbg_i2c_string = "";
end
endtask
//----------------------------------------------------------------------------
// Read ACK / NACK
//----------------------------------------------------------------------------
task dbg_i2c_ack_rd;
begin
dbg_i2c_string = "ACK (rd)";
#(I2C_PERIOD/4);
dbg_scl_master_pre = 1\'b1;
#(I2C_PERIOD/2);
dbg_scl_master_pre = 1\'b0;
#(I2C_PERIOD/4);
dbg_i2c_string = "";
end
endtask
//----------------------------------------------------------------------------
// Read a byte from the I2C bus
//----------------------------------------------------------------------------
task dbg_i2c_receive;
output [7:0] rxbuf;
reg [9:0] \trxbuf_full;
integer \trxcnt;
begin
#(1);
rxbuf_full = 0;
for (rxcnt = 0; rxcnt < 8; rxcnt = rxcnt + 1)
\tbegin
\t $sformat(dbg_i2c_string, "RX_%-d", rxcnt);
\t #(I2C_PERIOD/4);
\t dbg_scl_master_pre = 1\'b1;
\t #(I2C_PERIOD/4);
\t rxbuf_full[7-rxcnt] = dbg_sda;
\t #(I2C_PERIOD/4);
\t dbg_scl_master_pre = 1\'b0;
\t #(I2C_PERIOD/4);
\tend
dbg_i2c_string = "";
rxbuf = rxbuf_full;
end
endtask
//----------------------------------------------------------------------------
// Write ACK
//----------------------------------------------------------------------------
task dbg_i2c_ack_wr;
begin
dbg_i2c_string = "ACK (wr)";
dbg_sda_master_out_pre = 1\'b0;
#(I2C_PERIOD/4);
dbg_scl_master_pre = 1\'b1;
#(I2C_PERIOD/2);
dbg_scl_master_pre = 1\'b0;
#(I2C_PERIOD/4);
dbg_sda_master_out_pre = 1\'b1;
dbg_i2c_string = "";
end
endtask
//----------------------------------------------------------------------------
// Write NACK
//----------------------------------------------------------------------------
task dbg_i2c_nack_wr;
begin
dbg_i2c_string = "NACK (wr)";
dbg_sda_master_out_pre = 1\'b1;
#(I2C_PERIOD/4);
dbg_scl_master_pre = 1\'b1;
#(I2C_PERIOD/2);
dbg_scl_master_pre = 1\'b0;
#(I2C_PERIOD/4);
dbg_sda_master_out_pre = 1\'b1;
dbg_i2c_string = "";
end
endtask
//----------------------------------------------------------------------------
// Start Burst
//----------------------------------------------------------------------------
task dbg_i2c_burst_start;
input read;
begin
dbg_i2c_start; // START
dbg_i2c_send({I2C_ADDR, read}); // Device Address + Write access
dbg_i2c_ack_rd;
end
endtask
//----------------------------------------------------------------------------
// Read 16 bits
//----------------------------------------------------------------------------
task dbg_i2c_rx16;
input is_last;
reg [7:0] \trxbuf_lo;
reg [7:0] \trxbuf_hi;
begin
rxbuf_lo = 8\'h00;
rxbuf_hi = 8\'h00;
dbg_i2c_receive(rxbuf_lo); // Data (low)
dbg_i2c_ack_wr;
dbg_i2c_receive(rxbuf_hi); // Data (high)
if (is_last)
\tbegin
\t dbg_i2c_nack_wr;
\t dbg_i2c_stop; // STOP
\tend
else
\tbegin
\t dbg_i2c_ack_wr;
\tend
dbg_i2c_buf = {rxbuf_hi, rxbuf_lo};
end
endtask
//----------------------------------------------------------------------------
// Transmit 16 bits
//----------------------------------------------------------------------------
task dbg_i2c_tx16;
input [15:0] dbg_data;
input is_last;
begin
dbg_i2c_send(dbg_data[7:0]); // write LSB
dbg_i2c_ack_rd;
dbg_i2c_send(dbg_data[15:8]); // write MSB
dbg_i2c_ack_rd;
if (is_last)
\tdbg_i2c_stop; // STOP CONDITION
end
endtask
//----------------------------------------------------------------------------
// Read 8 bits
//----------------------------------------------------------------------------
task dbg_i2c_rx8;
input is_last;
reg [7:0] \trxbuf;
begin
rxbuf = 8\'h00;
dbg_i2c_receive(rxbuf); // Data (low)
if (is_last)
\tbegin
\t dbg_i2c_nack_wr;
\t dbg_i2c_stop; // STOP
\tend
else
\tbegin
\t dbg_i2c_ack_wr;
\tend
dbg_i2c_buf = {8\'h00, rxbuf};
end
endtask
//----------------------------------------------------------------------------
// Transmit 8 bits
//----------------------------------------------------------------------------
task dbg_i2c_tx8;
input [7:0] dbg_data;
input is_last;
begin
dbg_i2c_send(dbg_data); // write LSB
dbg_i2c_ack_rd;
if (is_last)
\tdbg_i2c_stop; // STOP CONDITION
end
endtask
//----------------------------------------------------------------------------
// Write to Debug register
//----------------------------------------------------------------------------
task dbg_i2c_wr;
input [7:0] dbg_reg;
input [15:0] dbg_data;
begin
dbg_i2c_start; // START
dbg_i2c_tx8({I2C_ADDR, 1\'b0}, 0); // Device Address + Write access
dbg_i2c_tx8(DBG_WR | dbg_reg, 0); // Command
if (~dbg_reg[6])
\tdbg_i2c_tx16(dbg_data, 1);
else
\tdbg_i2c_tx8 (dbg_data[7:0], 1);
\t
end
endtask
//----------------------------------------------------------------------------
// Read Debug register
//----------------------------------------------------------------------------
task dbg_i2c_rd;
input [7:0] dbg_reg;
reg [7:0] \trxbuf_lo;
reg [7:0] \trxbuf_hi;
begin
rxbuf_lo = 8\'h00;
rxbuf_hi = 8\'h00;
dbg_i2c_start; // START
dbg_i2c_tx8({I2C_ADDR, 1\'b0}, 0); // Device Address + Write access
dbg_i2c_tx8(DBG_RD | dbg_reg, 1); // Command
dbg_i2c_start; // START
dbg_i2c_tx8({I2C_ADDR, 1\'b1}, 0); // Device Address + Read access
if (~dbg_reg[6])
\tdbg_i2c_rx16(1);
else
\tdbg_i2c_rx8(1);
\t
end
endtask
//----------------------------------------------------------------------------
// Build random delay insertion on SCL_MASTER and SDA_MASTER_OUT in order to
// simulate synchronization mechanism
//----------------------------------------------------------------------------
always @(posedge mclk or posedge dbg_rst)
if (dbg_rst)
begin
dbg_sda_master_out_sel <= 1\'b0;
dbg_sda_master_out_dly <= 1\'b1;
dbg_scl_master_sel <= 1\'b0;
dbg_scl_master_dly <= 1\'b1;
end
else if (dbg_en)
begin
dbg_sda_master_out_sel <= dbg_sda_master_out_meta ? $random : 1\'b0;
dbg_sda_master_out_dly <= dbg_sda_master_out_pre;
dbg_scl_master_sel <= dbg_scl_master_meta ? $random : 1\'b0;
dbg_scl_master_dly <= dbg_scl_master_pre;
end
assign dbg_sda_master_out = dbg_sda_master_out_sel ? dbg_sda_master_out_dly : dbg_sda_master_out_pre;
assign dbg_scl_master = dbg_scl_master_sel ? dbg_scl_master_dly : dbg_scl_master_pre;
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_timerA_undefines.v
//
// *Module Description:
// omsp_timerA Verilog `undef file
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 23 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// SYSTEM CONFIGURATION
//----------------------------------------------------------------------------
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
// Timer A: TACTL Control Register
`ifdef TASSELx
`undef TASSELx
`endif
`ifdef TAIDx
`undef TAIDx
`endif
`ifdef TAMCx
`undef TAMCx
`endif
`ifdef TACLR
`undef TACLR
`endif
`ifdef TAIE
`undef TAIE
`endif
`ifdef TAIFG
`undef TAIFG
`endif
// Timer A: TACCTLx Capture/Compare Control Register
`ifdef TACMx
`undef TACMx
`endif
`ifdef TACCISx
`undef TACCISx
`endif
`ifdef TASCS
`undef TASCS
`endif
`ifdef TASCCI
`undef TASCCI
`endif
`ifdef TACAP
`undef TACAP
`endif
`ifdef TAOUTMODx
`undef TAOUTMODx
`endif
`ifdef TACCIE
`undef TACCIE
`endif
`ifdef TACCI
`undef TACCI
`endif
`ifdef TAOUT
`undef TAOUT
`endif
`ifdef TACOV
`undef TACOV
`endif
`ifdef TACCIFG
`undef TACCIFG
`endif
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: registers.v
//
// *Module Description:
// Direct connections to internal registers & memory.
//
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
// CPU registers
//======================
wire [15:0] r0 = dut.execution_unit_0.register_file_0.r0;
wire [15:0] r1 = dut.execution_unit_0.register_file_0.r1;
wire [15:0] r2 = dut.execution_unit_0.register_file_0.r2;
wire [15:0] r3 = dut.execution_unit_0.register_file_0.r3;
wire [15:0] r4 = dut.execution_unit_0.register_file_0.r4;
wire [15:0] r5 = dut.execution_unit_0.register_file_0.r5;
wire [15:0] r6 = dut.execution_unit_0.register_file_0.r6;
wire [15:0] r7 = dut.execution_unit_0.register_file_0.r7;
wire [15:0] r8 = dut.execution_unit_0.register_file_0.r8;
wire [15:0] r9 = dut.execution_unit_0.register_file_0.r9;
wire [15:0] r10 = dut.execution_unit_0.register_file_0.r10;
wire [15:0] r11 = dut.execution_unit_0.register_file_0.r11;
wire [15:0] r12 = dut.execution_unit_0.register_file_0.r12;
wire [15:0] r13 = dut.execution_unit_0.register_file_0.r13;
wire [15:0] r14 = dut.execution_unit_0.register_file_0.r14;
wire [15:0] r15 = dut.execution_unit_0.register_file_0.r15;
// RAM cells
//======================
wire [15:0] mem200 = dmem_0.mem[0];
wire [15:0] mem202 = dmem_0.mem[1];
wire [15:0] mem204 = dmem_0.mem[2];
wire [15:0] mem206 = dmem_0.mem[3];
wire [15:0] mem208 = dmem_0.mem[4];
wire [15:0] mem20A = dmem_0.mem[5];
wire [15:0] mem20C = dmem_0.mem[6];
wire [15:0] mem20E = dmem_0.mem[7];
wire [15:0] mem210 = dmem_0.mem[8];
wire [15:0] mem212 = dmem_0.mem[9];
wire [15:0] mem214 = dmem_0.mem[10];
wire [15:0] mem216 = dmem_0.mem[11];
wire [15:0] mem218 = dmem_0.mem[12];
wire [15:0] mem21A = dmem_0.mem[13];
wire [15:0] mem21C = dmem_0.mem[14];
wire [15:0] mem21E = dmem_0.mem[15];
wire [15:0] mem220 = dmem_0.mem[16];
wire [15:0] mem222 = dmem_0.mem[17];
wire [15:0] mem224 = dmem_0.mem[18];
wire [15:0] mem226 = dmem_0.mem[19];
wire [15:0] mem228 = dmem_0.mem[20];
wire [15:0] mem22A = dmem_0.mem[21];
wire [15:0] mem22C = dmem_0.mem[22];
wire [15:0] mem22E = dmem_0.mem[23];
wire [15:0] mem230 = dmem_0.mem[24];
wire [15:0] mem232 = dmem_0.mem[25];
wire [15:0] mem234 = dmem_0.mem[26];
wire [15:0] mem236 = dmem_0.mem[27];
wire [15:0] mem238 = dmem_0.mem[28];
wire [15:0] mem23A = dmem_0.mem[29];
wire [15:0] mem23C = dmem_0.mem[30];
wire [15:0] mem23E = dmem_0.mem[31];
wire [15:0] mem240 = dmem_0.mem[32];
wire [15:0] mem242 = dmem_0.mem[33];
wire [15:0] mem244 = dmem_0.mem[34];
wire [15:0] mem246 = dmem_0.mem[35];
wire [15:0] mem248 = dmem_0.mem[36];
wire [15:0] mem24A = dmem_0.mem[37];
wire [15:0] mem24C = dmem_0.mem[38];
wire [15:0] mem24E = dmem_0.mem[39];
wire [15:0] mem250 = dmem_0.mem[40];
wire [15:0] mem252 = dmem_0.mem[41];
wire [15:0] mem254 = dmem_0.mem[42];
wire [15:0] mem256 = dmem_0.mem[43];
wire [15:0] mem258 = dmem_0.mem[44];
wire [15:0] mem25A = dmem_0.mem[45];
wire [15:0] mem25C = dmem_0.mem[46];
wire [15:0] mem25E = dmem_0.mem[47];
wire [15:0] mem260 = dmem_0.mem[48];
wire [15:0] mem262 = dmem_0.mem[49];
wire [15:0] mem264 = dmem_0.mem[50];
wire [15:0] mem266 = dmem_0.mem[51];
wire [15:0] mem268 = dmem_0.mem[52];
wire [15:0] mem26A = dmem_0.mem[53];
wire [15:0] mem26C = dmem_0.mem[54];
wire [15:0] mem26E = dmem_0.mem[55];
wire [15:0] mem270 = dmem_0.mem[56];
wire [15:0] mem272 = dmem_0.mem[57];
wire [15:0] mem274 = dmem_0.mem[58];
wire [15:0] mem276 = dmem_0.mem[59];
wire [15:0] mem278 = dmem_0.mem[60];
wire [15:0] mem27A = dmem_0.mem[61];
wire [15:0] mem27C = dmem_0.mem[62];
wire [15:0] mem27E = dmem_0.mem[63];
// Interrupt vectors
//======================
wire [15:0] irq_vect_15 = pmem_0.mem[(`PMEM_SIZE>>1)-1]; // RESET Vector
wire [15:0] irq_vect_14 = pmem_0.mem[(`PMEM_SIZE>>1)-2]; // NMI
wire [15:0] irq_vect_13 = pmem_0.mem[(`PMEM_SIZE>>1)-3]; // IRQ 13
wire [15:0] irq_vect_12 = pmem_0.mem[(`PMEM_SIZE>>1)-4]; // IRQ 12
wire [15:0] irq_vect_11 = pmem_0.mem[(`PMEM_SIZE>>1)-5]; // IRQ 11
wire [15:0] irq_vect_10 = pmem_0.mem[(`PMEM_SIZE>>1)-6]; // IRQ 10
wire [15:0] irq_vect_09 = pmem_0.mem[(`PMEM_SIZE>>1)-7]; // IRQ 9
wire [15:0] irq_vect_08 = pmem_0.mem[(`PMEM_SIZE>>1)-8]; // IRQ 8
wire [15:0] irq_vect_07 = pmem_0.mem[(`PMEM_SIZE>>1)-9]; // IRQ 7
wire [15:0] irq_vect_06 = pmem_0.mem[(`PMEM_SIZE>>1)-10]; // IRQ 6
wire [15:0] irq_vect_05 = pmem_0.mem[(`PMEM_SIZE>>1)-11]; // IRQ 5
wire [15:0] irq_vect_04 = pmem_0.mem[(`PMEM_SIZE>>1)-12]; // IRQ 4
wire [15:0] irq_vect_03 = pmem_0.mem[(`PMEM_SIZE>>1)-13]; // IRQ 3
wire [15:0] irq_vect_02 = pmem_0.mem[(`PMEM_SIZE>>1)-14]; // IRQ 2
wire [15:0] irq_vect_01 = pmem_0.mem[(`PMEM_SIZE>>1)-15]; // IRQ 1
wire [15:0] irq_vect_00 = pmem_0.mem[(`PMEM_SIZE>>1)-16]; // IRQ 0
// Interrupt detection
wire nmi_detect = dut.frontend_0.nmi_pnd;
wire irq_detect = dut.frontend_0.irq_detect;
// Debug interface
wire dbg_clk = dut.clock_module_0.dbg_clk;
wire dbg_rst = dut.clock_module_0.dbg_rst;
// CPU ID
//======================
wire [2:0] dbg_cpu_version = `CPU_VERSION;
`ifdef ASIC
wire dbg_cpu_asic = 1'b1;
`else
wire dbg_cpu_asic = 1'b0;
`endif
wire [4:0] dbg_user_version = `USER_VERSION;
wire [6:0] dbg_per_space = (`PER_SIZE >> 9);
`ifdef MULTIPLIER
wire dbg_mpy_info = 1'b1;
`else
wire dbg_mpy_info = 1'b0;
`endif
wire [8:0] dbg_dmem_size = (`DMEM_SIZE >> 7);
wire [5:0] dbg_pmem_size = (`PMEM_SIZE >> 10);
wire [31:0] dbg_cpu_id = {dbg_pmem_size,
dbg_dmem_size,
dbg_mpy_info,
dbg_per_space,
dbg_user_version,
dbg_cpu_asic,
dbg_cpu_version};
|
//----------------------------------------------------------------------------
// Copyright (C) 2014 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: dma_tasks.v
//
// *Module Description:
// generic tasks for using the Direct Memory Access interface
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
//============================================================================
// DMA Write access
//============================================================================
integer dma_cnt_wr;
integer dma_cnt_rd;
integer dma_wr_error;
integer dma_rd_error;
reg dma_tfx_cancel;
//---------------------
// Generic write task
//---------------------
task dma_write;
input [15:0] addr; // Address
input [15:0] data; // Data
input resp; // Expected transfer response (0: Okay / 1: Error)
input size; // Access size (0: 8-bit / 1: 16-bit)
begin
dma_addr = addr[15:1];
dma_en = 1\'b1;
dma_we = size ? 2\'b11 :
addr[0] ? 2\'b10 : 2\'b01;
dma_din = data;
@(posedge mclk or posedge dma_tfx_cancel);
while(~dma_ready & ~dma_tfx_cancel) @(posedge mclk or posedge dma_tfx_cancel);
dma_en = 1\'b0;
dma_we = 2\'b00;
dma_addr = 15\'h0000;
dma_din = 16\'h0000;
if (~dma_tfx_cancel) dma_cnt_wr = dma_cnt_wr+1;
// Check transfer response
if (~dma_tfx_cancel & (dma_resp != resp))
\tbegin
\t $display("ERROR: DMA interface write response check -- address: 0x%h -- response: %h / expected: %h (%t ns)", addr, dma_resp, resp, $time);
\t dma_wr_error = dma_wr_error+1;
\tend
end
endtask
//---------------------
// Write 16b task
//---------------------
task dma_write_16b;
input [15:0] addr; // Address
input [15:0] data; // Data
input resp; // Expected transfer response (0: Okay / 1: Error)
begin
dma_write(addr, data, resp, 1\'b1);
end
endtask
//---------------------
// Write 8b task
//---------------------
task dma_write_8b;
input [15:0] addr; // Address
input [7:0] data; // Data
input resp; // Expected transfer response (0: Okay / 1: Error)
begin
if (addr[0]) dma_write(addr, {data, 8\'h00}, resp, 1\'b0);
else dma_write(addr, {8\'h00, data }, resp, 1\'b0);
end
endtask
//============================================================================
// DMA read access
//============================================================================
//---------------------
// Read check process
//---------------------
reg dma_read_check_active;
reg [15:0] dma_read_check_addr;
reg [15:0] dma_read_check_data;
reg [15:0] dma_read_check_mask;
initial
begin
dma_read_check_active = 1\'b0;
dma_read_check_addr = 16\'h0000;
dma_read_check_data = 16\'h0000;
dma_read_check_mask = 16\'h0000;
forever
begin
\t @(negedge (mclk & dma_read_check_active) or posedge dma_tfx_cancel);
\t if (~dma_tfx_cancel & (dma_read_check_data !== (dma_read_check_mask & dma_dout)) & ~puc_rst)
\t begin
\t $display("ERROR: DMA interface read check -- address: 0x%h -- read: 0x%h / expected: 0x%h (%t ns)", dma_read_check_addr, (dma_read_check_mask & dma_dout), dma_read_check_data, $time);
\t dma_rd_error = dma_rd_error+1;
\t end
\t dma_read_check_active = 1\'b0;
end
end
//---------------------
// Generic read task
//---------------------
task dma_read;
input [15:0] addr; // Address
input [15:0] data; // Data to check against
input resp; // Expected transfer response (0: Okay / 1: Error)
input check; // Enable/disable read value check
input size; // Access size (0: 8-bit / 1: 16-bit)
begin
// Perform read transfer
dma_addr = addr[15:1];
dma_en = 1\'b1;
dma_we = 2\'b00;
dma_din = 16\'h0000;
@(posedge mclk or posedge dma_tfx_cancel);
while(~dma_ready & ~dma_tfx_cancel) @(posedge mclk or posedge dma_tfx_cancel);
dma_en = 1\'b0;
dma_addr = 15\'h0000;
// Trigger read check
dma_read_check_active = check;
dma_read_check_addr = addr;
dma_read_check_data = data;
dma_read_check_mask = size ? 16\'hFFFF :
(addr[0] ? 16\'hFF00 : 16\'h00FF);
if (~dma_tfx_cancel) dma_cnt_rd = dma_cnt_rd+1;
// Check transfer response
if (~dma_tfx_cancel & (dma_resp != resp))
\tbegin
\t $display("ERROR: DMA interface read response check -- address: 0x%h -- response: %h / expected: %h (%t ns)", addr, dma_resp, resp, $time);
\t dma_rd_error = dma_rd_error+1;
\tend
end
endtask
//---------------------
// Read 16b task
//---------------------
task dma_read_16b;
input [15:0] addr; // Address
input [15:0] data; // Data to check against
input resp; // Expected transfer response (0: Okay / 1: Error)
begin
dma_read(addr, data, resp, 1\'b1, 1\'b1);
end
endtask
//---------------------
// Read 8b task
//---------------------
task dma_read_8b;
input [15:0] addr; // Address
input [7:0] data; // Data to check against
input resp; // Expected transfer response (0: Okay / 1: Error)
begin
if (addr[0]) dma_read(addr, {data, 8\'h00}, resp, 1\'b1, 1\'b0);
else dma_read(addr, {8\'h00, data }, resp, 1\'b1, 1\'b0);
end
endtask
//--------------------------------
// Read 16b value task (no check)
//--------------------------------
task dma_read_val_16b;
input [15:0] addr; // Address
input resp; // Expected transfer response (0: Okay / 1: Error)
begin
dma_read(addr, 16\'h0000, resp, 1\'b0, 1\'b1);
end
endtask
//============================================================================
// Ramdom DMA access process
//============================================================================
integer dma_rand_wait;
integer dma_rand_wait_disable;
reg dma_rand_rdwr;
reg dma_rand_if;
integer\t dma_rand_data;
reg [6:0] dma_rand_addr;
reg [15:0] dma_rand_addr_full;
integer dma_mem_ref_idx;
reg [15:0] dma_pmem_reference[0:127];
reg [15:0] dma_dmem_reference[0:127];
reg\t dma_verif_on;
reg\t dma_verif_verbose;
initial
begin
// Initialize
`ifdef NO_DMA_VERIF
dma_verif_on = 0;
`else
`ifdef DMA_IF_EN
dma_verif_on = 1;
`else
dma_verif_on = 0;
`endif
`endif
dma_rand_wait_disable = 0;
dma_verif_verbose = 0;
dma_cnt_wr = 0;
dma_cnt_rd = 0;
dma_wr_error = 0;
dma_rd_error = 0;
#20;
dma_rand_wait = $urandom;
for (dma_mem_ref_idx=0; dma_mem_ref_idx < 128; dma_mem_ref_idx=dma_mem_ref_idx+1)
begin
\t dma_pmem_reference[dma_mem_ref_idx] = $urandom;
\t dma_dmem_reference[dma_mem_ref_idx]\t\t = $urandom;
\t if (dma_verif_on && (`PMEM_SIZE>=4092) && (`DMEM_SIZE>=1024))
\t begin
\t pmem_0.mem[(`PMEM_SIZE-512)/2+dma_mem_ref_idx] = dma_pmem_reference[dma_mem_ref_idx];
\t dmem_0.mem[(`DMEM_SIZE-256)/2+dma_mem_ref_idx] = dma_dmem_reference[dma_mem_ref_idx];
\t end
end
// Wait for reset release
repeat(1) @(posedge dco_clk);
@(negedge puc_rst);
// Perform random read/write 16b memory accesses
if (dma_verif_on && (`PMEM_SIZE>=4092) && (`DMEM_SIZE>=1024))
begin
\t forever
\t begin
\t // Randomize 1 or 0 wait states between accesses
\t // (1/3 proba of getting 1 wait state)
\t dma_rand_wait = dma_rand_wait_disable ? 0 : ($urandom_range(2,0)==0);
\t repeat(dma_rand_wait) @(posedge mclk);
\t // Randomize read/write accesses
\t // (1/3 proba of getting a read access)
\t dma_rand_rdwr = ($urandom_range(2,0)==0);
\t // Randomize address to be accessed (between 128 addresses)
\t dma_rand_addr = $urandom;
\t // Randomize access through PMEM or DMEM memories
\t dma_rand_if = $urandom_range(1,0);
\t // Make sure the core is not in reset
\t while(puc_rst) @(posedge mclk);
\t
\t if (dma_rand_rdwr)
\t\t begin
\t\t if (dma_rand_if) // Read from Program Memory
\t\t begin
\t\t\t dma_rand_addr_full = 16\'hFE00+dma_rand_addr*2;
\t\t\t if (dma_verif_verbose) $display("READ DMA interface -- address: 0x%h -- expected data: 0x%h", dma_rand_addr_full, dma_pmem_reference[dma_rand_addr]);
\t\t\t dma_read_16b(dma_rand_addr_full, dma_pmem_reference[dma_rand_addr], 1\'b0);
\t\t end
\t\t else // Read from Data Memory
\t\t begin
\t\t\t dma_rand_addr_full = `PER_SIZE+`DMEM_SIZE-256+dma_rand_addr*2;
\t\t\t if (dma_verif_verbose) $display("READ DMA interface -- address: 0x%h -- expected data: 0x%h", dma_rand_addr_full, dma_dmem_reference[dma_rand_addr]);
\t\t\t dma_read_16b(dma_rand_addr_full, dma_dmem_reference[dma_rand_addr], 1\'b0);
\t\t end
\t\t end
\t else
\t\t begin
\t\t dma_rand_data = $urandom;
\t\t if (dma_rand_if) // Write to Program memory
\t\t begin
\t\t\t dma_rand_addr_full = 16\'hFE00+dma_rand_addr*2;
\t\t\t if (dma_verif_verbose) $display("WRITE DMA interface -- address: 0x%h -- data: 0x%h", dma_rand_addr_full, dma_rand_data[15:0]);
\t\t\t dma_write_16b(dma_rand_addr_full, dma_rand_data[15:0], 1\'b0);
\t\t\t dma_pmem_reference[dma_rand_addr] = dma_rand_data[15:0];
\t\t\t #1;
\t\t\t if (pmem_0.mem[(`PMEM_SIZE-512)/2+dma_rand_addr] !== dma_rand_data[15:0])
\t\t\t begin
\t\t\t $display("ERROR: DMA interface write -- address: 0x%h -- wrote: 0x%h / expected: 0x%h (%t ns)", dma_rand_addr_full, dma_rand_data[15:0], pmem_0.mem[(`PMEM_SIZE-512)/2+dma_rand_addr], $time);
\t\t\t dma_wr_error = dma_wr_error+1;
\t\t\t end
\t\t end
\t\t else // Write to Data Memory
\t\t begin
\t\t\t dma_rand_addr_full = `PER_SIZE+`DMEM_SIZE-256+dma_rand_addr*2;
\t\t\t if (dma_verif_verbose) $display("WRITE DMA interface -- address: 0x%h -- data: 0x%h", dma_rand_addr_full, dma_rand_data[15:0]);
\t\t\t dma_write_16b(dma_rand_addr_full, dma_rand_data[15:0], 1\'b0);
\t\t\t dma_dmem_reference[dma_rand_addr] = dma_rand_data[15:0];
\t\t\t #1;
\t\t\t if (dmem_0.mem[(`DMEM_SIZE-256)/2+dma_rand_addr] !== dma_rand_data[15:0])
\t\t\t begin
\t\t\t $display("ERROR: DMA interface write -- address: 0x%h -- wrote: 0x%h / expected: 0x%h (%t ns)", dma_rand_addr_full, dma_rand_data[15:0], dmem_0.mem[(`DMEM_SIZE-256)/2+dma_rand_addr], $time);
\t\t\t dma_wr_error = dma_wr_error+1;
\t\t\t end
\t\t end
\t\t end
\t end
end
end
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_execution_unit.v
//
// *Module Description:
// openMSP430 Execution unit
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module omsp_execution_unit (
// OUTPUTs
cpuoff, // Turns off the CPU
dbg_reg_din, // Debug unit CPU register data input
gie, // General interrupt enable
mab, // Memory address bus
mb_en, // Memory bus enable
mb_wr, // Memory bus write transfer
mdb_out, // Memory data bus output
oscoff, // Turns off LFXT1 clock input
pc_sw, // Program counter software value
pc_sw_wr, // Program counter software write
scg0, // System clock generator 1. Turns off the DCO
scg1, // System clock generator 1. Turns off the SMCLK
// INPUTs
dbg_halt_st, // Halt/Run status from CPU
dbg_mem_dout, // Debug unit data output
dbg_reg_wr, // Debug unit CPU register write
e_state, // Execution state
exec_done, // Execution completed
inst_ad, // Decoded Inst: destination addressing mode
inst_as, // Decoded Inst: source addressing mode
inst_alu, // ALU control signals
inst_bw, // Decoded Inst: byte width
inst_dest, // Decoded Inst: destination (one hot)
inst_dext, // Decoded Inst: destination extended instruction word
inst_irq_rst, // Decoded Inst: reset interrupt
inst_jmp, // Decoded Inst: Conditional jump
inst_mov, // Decoded Inst: mov instruction
inst_sext, // Decoded Inst: source extended instruction word
inst_so, // Decoded Inst: Single-operand arithmetic
inst_src, // Decoded Inst: source (one hot)
inst_type, // Decoded Instruction type
mclk, // Main system clock
mdb_in, // Memory data bus input
pc, // Program counter
pc_nxt, // Next PC value (for CALL & IRQ)
puc_rst, // Main system reset
scan_enable // Scan enable (active during scan shifting)
);
// OUTPUTs
//=========
output cpuoff; // Turns off the CPU
output [15:0] dbg_reg_din; // Debug unit CPU register data input
output gie; // General interrupt enable
output [15:0] mab; // Memory address bus
output mb_en; // Memory bus enable
output [1:0] mb_wr; // Memory bus write transfer
output [15:0] mdb_out; // Memory data bus output
output oscoff; // Turns off LFXT1 clock input
output [15:0] pc_sw; // Program counter software value
output pc_sw_wr; // Program counter software write
output scg0; // System clock generator 1. Turns off the DCO
output scg1; // System clock generator 1. Turns off the SMCLK
// INPUTs
//=========
input dbg_halt_st; // Halt/Run status from CPU
input [15:0] dbg_mem_dout; // Debug unit data output
input dbg_reg_wr; // Debug unit CPU register write
input [3:0] e_state; // Execution state
input exec_done; // Execution completed
input [7:0] inst_ad; // Decoded Inst: destination addressing mode
input [7:0] inst_as; // Decoded Inst: source addressing mode
input [11:0] inst_alu; // ALU control signals
input inst_bw; // Decoded Inst: byte width
input [15:0] inst_dest; // Decoded Inst: destination (one hot)
input [15:0] inst_dext; // Decoded Inst: destination extended instruction word
input inst_irq_rst; // Decoded Inst: reset interrupt
input [7:0] inst_jmp; // Decoded Inst: Conditional jump
input inst_mov; // Decoded Inst: mov instruction
input [15:0] inst_sext; // Decoded Inst: source extended instruction word
input [7:0] inst_so; // Decoded Inst: Single-operand arithmetic
input [15:0] inst_src; // Decoded Inst: source (one hot)
input [2:0] inst_type; // Decoded Instruction type
input mclk; // Main system clock
input [15:0] mdb_in; // Memory data bus input
input [15:0] pc; // Program counter
input [15:0] pc_nxt; // Next PC value (for CALL & IRQ)
input puc_rst; // Main system reset
input scan_enable; // Scan enable (active during scan shifting)
//=============================================================================
// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
//=============================================================================
wire [15:0] alu_out;
wire [15:0] alu_out_add;
wire [3:0] alu_stat;
wire [3:0] alu_stat_wr;
wire [15:0] op_dst;
wire [15:0] op_src;
wire [15:0] reg_dest;
wire [15:0] reg_src;
wire [15:0] mdb_in_bw;
wire [15:0] mdb_in_val;
wire [3:0] status;
//=============================================================================
// 2) REGISTER FILE
//=============================================================================
wire reg_dest_wr = ((e_state==`E_EXEC) & (
(inst_type[`INST_TO] & inst_ad[`DIR] & ~inst_alu[`EXEC_NO_WR]) |
(inst_type[`INST_SO] & inst_as[`DIR] & ~(inst_so[`PUSH] | inst_so[`CALL] | inst_so[`RETI])) |
inst_type[`INST_JMP])) | dbg_reg_wr;
wire reg_sp_wr = (((e_state==`E_IRQ_1) | (e_state==`E_IRQ_3)) & ~inst_irq_rst) |
((e_state==`E_DST_RD) & ((inst_so[`PUSH] | inst_so[`CALL]) & ~inst_as[`IDX] & ~((inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1]))) |
((e_state==`E_SRC_AD) & ((inst_so[`PUSH] | inst_so[`CALL]) & inst_as[`IDX])) |
((e_state==`E_SRC_RD) & ((inst_so[`PUSH] | inst_so[`CALL]) & ((inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1])));
wire reg_sr_wr = (e_state==`E_DST_RD) & inst_so[`RETI];
wire reg_sr_clr = (e_state==`E_IRQ_2);
wire reg_pc_call = ((e_state==`E_EXEC) & inst_so[`CALL]) |
((e_state==`E_DST_WR) & inst_so[`RETI]);
wire reg_incr = (exec_done & inst_as[`INDIR_I]) |
((e_state==`E_SRC_RD) & inst_so[`RETI]) |
((e_state==`E_EXEC) & inst_so[`RETI]);
assign dbg_reg_din = reg_dest;
omsp_register_file register_file_0 (
// OUTPUTs
.cpuoff (cpuoff), // Turns off the CPU
.gie (gie), // General interrupt enable
.oscoff (oscoff), // Turns off LFXT1 clock input
.pc_sw (pc_sw), // Program counter software value
.pc_sw_wr (pc_sw_wr), // Program counter software write
.reg_dest (reg_dest), // Selected register destination content
.reg_src (reg_src), // Selected register source content
.scg0 (scg0), // System clock generator 1. Turns off the DCO
.scg1 (scg1), // System clock generator 1. Turns off the SMCLK
.status (status), // R2 Status {V,N,Z,C}
// INPUTs
.alu_stat (alu_stat), // ALU Status {V,N,Z,C}
.alu_stat_wr (alu_stat_wr), // ALU Status write {V,N,Z,C}
.inst_bw (inst_bw), // Decoded Inst: byte width
.inst_dest (inst_dest), // Register destination selection
.inst_src (inst_src), // Register source selection
.mclk (mclk), // Main system clock
.pc (pc), // Program counter
.puc_rst (puc_rst), // Main system reset
.reg_dest_val (alu_out), // Selected register destination value
.reg_dest_wr (reg_dest_wr), // Write selected register destination
.reg_pc_call (reg_pc_call), // Trigger PC update for a CALL instruction
.reg_sp_val (alu_out_add), // Stack Pointer next value
.reg_sp_wr (reg_sp_wr), // Stack Pointer write
.reg_sr_clr (reg_sr_clr), // Status register clear for interrupts
.reg_sr_wr (reg_sr_wr), // Status Register update for RETI instruction
.reg_incr (reg_incr), // Increment source register
.scan_enable (scan_enable) // Scan enable (active during scan shifting)
);
//=============================================================================
// 3) SOURCE OPERAND MUXING
//=============================================================================
// inst_as[`DIR] : Register direct. -> Source is in register
// inst_as[`IDX] : Register indexed. -> Source is in memory, address is register+offset
// inst_as[`INDIR] : Register indirect.
// inst_as[`INDIR_I]: Register indirect autoincrement.
// inst_as[`SYMB] : Symbolic (operand is in memory at address PC+x).
// inst_as[`IMM] : Immediate (operand is next word in the instruction stream).
// inst_as[`ABS] : Absolute (operand is in memory at address x).
// inst_as[`CONST] : Constant.
wire src_reg_src_sel = (e_state==`E_IRQ_0) |
(e_state==`E_IRQ_2) |
((e_state==`E_SRC_RD) & ~inst_as[`ABS]) |
((e_state==`E_SRC_WR) & ~inst_as[`ABS]) |
((e_state==`E_EXEC) & inst_as[`DIR] & ~inst_type[`INST_JMP]);
wire src_reg_dest_sel = (e_state==`E_IRQ_1) |
(e_state==`E_IRQ_3) |
((e_state==`E_DST_RD) & (inst_so[`PUSH] | inst_so[`CALL])) |
((e_state==`E_SRC_AD) & (inst_so[`PUSH] | inst_so[`CALL]) & inst_as[`IDX]);
wire src_mdb_in_val_sel = ((e_state==`E_DST_RD) & inst_so[`RETI]) |
((e_state==`E_EXEC) & (inst_as[`INDIR] | inst_as[`INDIR_I] |
inst_as[`IDX] | inst_as[`SYMB] |
inst_as[`ABS]));
wire src_inst_dext_sel = ((e_state==`E_DST_RD) & ~(inst_so[`PUSH] | inst_so[`CALL])) |
((e_state==`E_DST_WR) & ~(inst_so[`PUSH] | inst_so[`CALL] |
inst_so[`RETI]));
wire src_inst_sext_sel = ((e_state==`E_EXEC) & (inst_type[`INST_JMP] | inst_as[`IMM] |
inst_as[`CONST] | inst_so[`RETI]));
assign op_src = src_reg_src_sel ? reg_src :
src_reg_dest_sel ? reg_dest :
src_mdb_in_val_sel ? mdb_in_val :
src_inst_dext_sel ? inst_dext :
src_inst_sext_sel ? inst_sext : 16\'h0000;
//=============================================================================
// 4) DESTINATION OPERAND MUXING
//=============================================================================
// inst_ad[`DIR] : Register direct.
// inst_ad[`IDX] : Register indexed.
// inst_ad[`SYMB] : Symbolic (operand is in memory at address PC+x).
// inst_ad[`ABS] : Absolute (operand is in memory at address x).
wire dst_inst_sext_sel = ((e_state==`E_SRC_RD) & (inst_as[`IDX] | inst_as[`SYMB] |
inst_as[`ABS])) |
((e_state==`E_SRC_WR) & (inst_as[`IDX] | inst_as[`SYMB] |
inst_as[`ABS]));
wire dst_mdb_in_bw_sel = ((e_state==`E_DST_WR) & inst_so[`RETI]) |
((e_state==`E_EXEC) & ~(inst_ad[`DIR] | inst_type[`INST_JMP] |
inst_type[`INST_SO]) & ~inst_so[`RETI]);
wire dst_fffe_sel = (e_state==`E_IRQ_0) |
(e_state==`E_IRQ_1) |
(e_state==`E_IRQ_3) |
((e_state==`E_DST_RD) & (inst_so[`PUSH] | inst_so[`CALL]) & ~inst_so[`RETI]) |
((e_state==`E_SRC_AD) & (inst_so[`PUSH] | inst_so[`CALL]) & inst_as[`IDX]) |
((e_state==`E_SRC_RD) & (inst_so[`PUSH] | inst_so[`CALL]) & (inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1]);
wire dst_reg_dest_sel = ((e_state==`E_DST_RD) & ~(inst_so[`PUSH] | inst_so[`CALL] | inst_ad[`ABS] | inst_so[`RETI])) |
((e_state==`E_DST_WR) & ~inst_ad[`ABS]) |
((e_state==`E_EXEC) & (inst_ad[`DIR] | inst_type[`INST_JMP] |
inst_type[`INST_SO]) & ~inst_so[`RETI]);
assign op_dst = dbg_halt_st ? dbg_mem_dout :
dst_inst_sext_sel ? inst_sext :
dst_mdb_in_bw_sel ? mdb_in_bw :
dst_reg_dest_sel ? reg_dest :
dst_fffe_sel ? 16\'hfffe : 16\'h0000;
//=============================================================================
// 5) ALU
//=============================================================================
wire exec_cycle = (e_state==`E_EXEC);
omsp_alu alu_0 (
// OUTPUTs
.alu_out (alu_out), // ALU output value
.alu_out_add (alu_out_add), // ALU adder output value
.alu_stat (alu_stat), // ALU Status {V,N,Z,C}
.alu_stat_wr (alu_stat_wr), // ALU Status write {V,N,Z,C}
// INPUTs
.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
.exec_cycle (exec_cycle), // Instruction execution cycle
.inst_alu (inst_alu), // ALU control signals
.inst_bw (inst_bw), // Decoded Inst: byte width
.inst_jmp (inst_jmp), // Decoded Inst: Conditional jump
.inst_so (inst_so), // Single-operand arithmetic
.op_dst (op_dst), // Destination operand
.op_src (op_src), // Source operand
.status (status) // R2 Status {V,N,Z,C}
);
//=============================================================================
// 6) MEMORY INTERFACE
//=============================================================================
// Detect memory read/write access
wire mb_rd_det = ((e_state==`E_SRC_RD) & ~inst_as[`IMM]) |
((e_state==`E_EXEC) & inst_so[`RETI]) |
((e_state==`E_DST_RD) & ~inst_type[`INST_SO]
& ~inst_mov);
wire mb_wr_det = ((e_state==`E_IRQ_1) & ~inst_irq_rst) |
((e_state==`E_IRQ_3) & ~inst_irq_rst) |
((e_state==`E_DST_WR) & ~inst_so[`RETI]) |
(e_state==`E_SRC_WR);
wire [1:0] mb_wr_msk = inst_alu[`EXEC_NO_WR] ? 2\'b00 :
~inst_bw ? 2\'b11 :
alu_out_add[0] ? 2\'b10 : 2\'b01;
assign mb_en = mb_rd_det | (mb_wr_det & ~inst_alu[`EXEC_NO_WR]);
assign mb_wr = ({2{mb_wr_det}}) & mb_wr_msk;
// Memory address bus
assign mab = alu_out_add[15:0];
// Memory data bus output
reg [15:0] mdb_out_nxt;
`ifdef CLOCK_GATING
wire mdb_out_nxt_en = (e_state==`E_DST_RD) |
(((e_state==`E_EXEC) & ~inst_so[`CALL]) |
(e_state==`E_IRQ_0) | (e_state==`E_IRQ_2));
wire mclk_mdb_out_nxt;
omsp_clock_gate clock_gate_mdb_out_nxt (.gclk(mclk_mdb_out_nxt),
.clk (mclk), .enable(mdb_out_nxt_en), .scan_enable(scan_enable));
`else
wire mclk_mdb_out_nxt = mclk;
`endif
always @(posedge mclk_mdb_out_nxt or posedge puc_rst)
if (puc_rst) mdb_out_nxt <= 16\'h0000;
else if (e_state==`E_DST_RD) mdb_out_nxt <= pc_nxt;
`ifdef CLOCK_GATING
else mdb_out_nxt <= alu_out;
`else
else if ((e_state==`E_EXEC & ~inst_so[`CALL]) |
(e_state==`E_IRQ_0) | (e_state==`E_IRQ_2)) mdb_out_nxt <= alu_out;
`endif
assign mdb_out = inst_bw ? {2{mdb_out_nxt[7:0]}} : mdb_out_nxt;
// Format memory data bus input depending on BW
reg mab_lsb;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) mab_lsb <= 1\'b0;
else if (mb_en) mab_lsb <= alu_out_add[0];
assign mdb_in_bw = ~inst_bw ? mdb_in :
mab_lsb ? {2{mdb_in[15:8]}} : mdb_in;
// Memory data bus input buffer (buffer after a source read)
reg mdb_in_buf_en;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) mdb_in_buf_en <= 1\'b0;
else mdb_in_buf_en <= (e_state==`E_SRC_RD);
reg mdb_in_buf_valid;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) mdb_in_buf_valid <= 1\'b0;
else if (e_state==`E_EXEC) mdb_in_buf_valid <= 1\'b0;
else if (mdb_in_buf_en) mdb_in_buf_valid <= 1\'b1;
reg [15:0] mdb_in_buf;
`ifdef CLOCK_GATING
wire mclk_mdb_in_buf;
omsp_clock_gate clock_gate_mdb_in_buf (.gclk(mclk_mdb_in_buf),
.clk (mclk), .enable(mdb_in_buf_en), .scan_enable(scan_enable));
`else
wire mclk_mdb_in_buf = mclk;
`endif
always @(posedge mclk_mdb_in_buf or posedge puc_rst)
if (puc_rst) mdb_in_buf <= 16\'h0000;
`ifdef CLOCK_GATING
else mdb_in_buf <= mdb_in_bw;
`else
else if (mdb_in_buf_en) mdb_in_buf <= mdb_in_bw;
`endif
assign mdb_in_val = mdb_in_buf_valid ? mdb_in_buf : mdb_in_bw;
// LINT cleanup
wire UNUSED_inst_ad_idx = inst_ad[`IDX];
wire UNUSED_inst_ad_indir = inst_ad[`INDIR];
wire UNUSED_inst_ad_indir_i = inst_ad[`INDIR_I];
wire UNUSED_inst_ad_symb = inst_ad[`SYMB];
wire UNUSED_inst_ad_imm = inst_ad[`IMM];
wire UNUSED_inst_ad_const = inst_ad[`CONST];
endmodule // omsp_execution_unit
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_frontend.v
//
// *Module Description:
// openMSP430 Instruction fetch and decode unit
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module omsp_frontend (
// OUTPUTs
cpu_halt_st, // Halt/Run status from CPU
decode_noirq, // Frontend decode instruction
e_state, // Execution state
exec_done, // Execution completed
inst_ad, // Decoded Inst: destination addressing mode
inst_as, // Decoded Inst: source addressing mode
inst_alu, // ALU control signals
inst_bw, // Decoded Inst: byte width
inst_dest, // Decoded Inst: destination (one hot)
inst_dext, // Decoded Inst: destination extended instruction word
inst_irq_rst, // Decoded Inst: Reset interrupt
inst_jmp, // Decoded Inst: Conditional jump
inst_mov, // Decoded Inst: mov instruction
inst_sext, // Decoded Inst: source extended instruction word
inst_so, // Decoded Inst: Single-operand arithmetic
inst_src, // Decoded Inst: source (one hot)
inst_type, // Decoded Instruction type
irq_acc, // Interrupt request accepted (one-hot signal)
mab, // Frontend Memory address bus
mb_en, // Frontend Memory bus enable
mclk_dma_enable, // DMA Sub-System Clock enable
mclk_dma_wkup, // DMA Sub-System Clock wake-up (asynchronous)
mclk_enable, // Main System Clock enable
mclk_wkup, // Main System Clock wake-up (asynchronous)
nmi_acc, // Non-Maskable interrupt request accepted
pc, // Program counter
pc_nxt, // Next PC value (for CALL & IRQ)
// INPUTs
cpu_en_s, // Enable CPU code execution (synchronous)
cpu_halt_cmd, // Halt CPU command
cpuoff, // Turns off the CPU
dbg_reg_sel, // Debug selected register for rd/wr access
dma_en, // Direct Memory Access enable (high active)
dma_wkup, // DMA Sub-System Wake-up (asynchronous and non-glitchy)
fe_pmem_wait, // Frontend wait for Instruction fetch
gie, // General interrupt enable
irq, // Maskable interrupts
mclk, // Main system clock
mdb_in, // Frontend Memory data bus input
nmi_pnd, // Non-maskable interrupt pending
nmi_wkup, // NMI Wakeup
pc_sw, // Program counter software value
pc_sw_wr, // Program counter software write
puc_rst, // Main system reset
scan_enable, // Scan enable (active during scan shifting)
wdt_irq, // Watchdog-timer interrupt
wdt_wkup, // Watchdog Wakeup
wkup // System Wake-up (asynchronous)
);
// OUTPUTs
//=========
output cpu_halt_st; // Halt/Run status from CPU
output decode_noirq; // Frontend decode instruction
output [3:0] e_state; // Execution state
output exec_done; // Execution completed
output [7:0] inst_ad; // Decoded Inst: destination addressing mode
output [7:0] inst_as; // Decoded Inst: source addressing mode
output [11:0] inst_alu; // ALU control signals
output inst_bw; // Decoded Inst: byte width
output [15:0] inst_dest; // Decoded Inst: destination (one hot)
output [15:0] inst_dext; // Decoded Inst: destination extended instruction word
output inst_irq_rst; // Decoded Inst: Reset interrupt
output [7:0] inst_jmp; // Decoded Inst: Conditional jump
output inst_mov; // Decoded Inst: mov instruction
output [15:0] inst_sext; // Decoded Inst: source extended instruction word
output [7:0] inst_so; // Decoded Inst: Single-operand arithmetic
output [15:0] inst_src; // Decoded Inst: source (one hot)
output [2:0] inst_type; // Decoded Instruction type
output [`IRQ_NR-3:0] irq_acc; // Interrupt request accepted (one-hot signal)
output [15:0] mab; // Frontend Memory address bus
output mb_en; // Frontend Memory bus enable
output mclk_dma_enable; // DMA Sub-System Clock enable
output mclk_dma_wkup; // DMA Sub-System Clock wake-up (asynchronous)
output mclk_enable; // Main System Clock enable
output mclk_wkup; // Main System Clock wake-up (asynchronous)
output nmi_acc; // Non-Maskable interrupt request accepted
output [15:0] pc; // Program counter
output [15:0] pc_nxt; // Next PC value (for CALL & IRQ)
// INPUTs
//=========
input cpu_en_s; // Enable CPU code execution (synchronous)
input cpu_halt_cmd; // Halt CPU command
input cpuoff; // Turns off the CPU
input [3:0] dbg_reg_sel; // Debug selected register for rd/wr access
input dma_en; // Direct Memory Access enable (high active)
input dma_wkup; // DMA Sub-System Wake-up (asynchronous and non-glitchy)
input fe_pmem_wait; // Frontend wait for Instruction fetch
input gie; // General interrupt enable
input [`IRQ_NR-3:0] irq; // Maskable interrupts
input mclk; // Main system clock
input [15:0] mdb_in; // Frontend Memory data bus input
input nmi_pnd; // Non-maskable interrupt pending
input nmi_wkup; // NMI Wakeup
input [15:0] pc_sw; // Program counter software value
input pc_sw_wr; // Program counter software write
input puc_rst; // Main system reset
input scan_enable; // Scan enable (active during scan shifting)
input wdt_irq; // Watchdog-timer interrupt
input wdt_wkup; // Watchdog Wakeup
input wkup; // System Wake-up (asynchronous)
//=============================================================================
// 1) UTILITY FUNCTIONS
//=============================================================================
// 64 bits one-hot decoder
function [63:0] one_hot64;
input [5:0] binary;
begin
one_hot64 = 64\'h0000_0000_0000_0000;
one_hot64[binary] = 1\'b1;
end
endfunction
// 16 bits one-hot decoder
function [15:0] one_hot16;
input [3:0] binary;
begin
one_hot16 = 16\'h0000;
one_hot16[binary] = 1\'b1;
end
endfunction
// 8 bits one-hot decoder
function [7:0] one_hot8;
input [2:0] binary;
begin
one_hot8 = 8\'h00;
one_hot8[binary] = 1\'b1;
end
endfunction
// Get IRQ number
function [5:0] get_irq_num;
input [62:0] irq_all;
integer ii;
begin
get_irq_num = 6\'h3f;
for (ii = 62; ii >= 0; ii = ii - 1)
if (&get_irq_num & irq_all[ii]) get_irq_num = ii[5:0];
end
endfunction
//=============================================================================
// 2) PARAMETER DEFINITIONS
//=============================================================================
//
// 2.1) Instruction State machine definitons
//-------------------------------------------
parameter I_IRQ_FETCH = `I_IRQ_FETCH;
parameter I_IRQ_DONE = `I_IRQ_DONE;
parameter I_DEC = `I_DEC; // New instruction ready for decode
parameter I_EXT1 = `I_EXT1; // 1st Extension word
parameter I_EXT2 = `I_EXT2; // 2nd Extension word
parameter I_IDLE = `I_IDLE; // CPU is in IDLE mode
//
// 2.2) Execution State machine definitons
//-------------------------------------------
parameter E_IRQ_0 = `E_IRQ_0;
parameter E_IRQ_1 = `E_IRQ_1;
parameter E_IRQ_2 = `E_IRQ_2;
parameter E_IRQ_3 = `E_IRQ_3;
parameter E_IRQ_4 = `E_IRQ_4;
parameter E_SRC_AD = `E_SRC_AD;
parameter E_SRC_RD = `E_SRC_RD;
parameter E_SRC_WR = `E_SRC_WR;
parameter E_DST_AD = `E_DST_AD;
parameter E_DST_RD = `E_DST_RD;
parameter E_DST_WR = `E_DST_WR;
parameter E_EXEC = `E_EXEC;
parameter E_JUMP = `E_JUMP;
parameter E_IDLE = `E_IDLE;
//=============================================================================
// 3) FRONTEND STATE MACHINE
//=============================================================================
// The wire "conv" is used as state bits to calculate the next response
reg [2:0] i_state;
reg [2:0] i_state_nxt;
reg [1:0] inst_sz;
wire [1:0] inst_sz_nxt;
wire irq_detect;
wire [2:0] inst_type_nxt;
wire is_const;
reg [15:0] sconst_nxt;
reg [3:0] e_state_nxt;
// CPU on/off through an external interface (debug or mstr) or cpu_en port
wire cpu_halt_req = cpu_halt_cmd | ~cpu_en_s;
// States Transitions
always @(i_state or inst_sz or inst_sz_nxt or pc_sw_wr or exec_done or
irq_detect or cpuoff or cpu_halt_req or e_state)
case(i_state)
I_IDLE : i_state_nxt = (irq_detect & ~cpu_halt_req) ? I_IRQ_FETCH :
(~cpuoff & ~cpu_halt_req) ? I_DEC : I_IDLE;
I_IRQ_FETCH: i_state_nxt = I_IRQ_DONE;
I_IRQ_DONE : i_state_nxt = I_DEC;
I_DEC : i_state_nxt = irq_detect ? I_IRQ_FETCH :
(cpuoff | cpu_halt_req) & exec_done ? I_IDLE :
cpu_halt_req & (e_state==E_IDLE) ? I_IDLE :
pc_sw_wr ? I_DEC :
~exec_done & ~(e_state==E_IDLE) ? I_DEC : // Wait in decode state
(inst_sz_nxt!=2\'b00) ? I_EXT1 : I_DEC; // until execution is completed
I_EXT1 : i_state_nxt = pc_sw_wr ? I_DEC :
(inst_sz!=2\'b01) ? I_EXT2 : I_DEC;
I_EXT2 : i_state_nxt = I_DEC;
// pragma coverage off
default : i_state_nxt = I_IRQ_FETCH;
// pragma coverage on
endcase
// State machine
always @(posedge mclk or posedge puc_rst)
if (puc_rst) i_state <= I_IRQ_FETCH;
else i_state <= i_state_nxt;
// Utility signals
wire decode_noirq = ((i_state==I_DEC) & (exec_done | (e_state==E_IDLE)));
wire decode = decode_noirq | irq_detect;
wire fetch = ~((i_state==I_DEC) & ~(exec_done | (e_state==E_IDLE))) & ~(e_state_nxt==E_IDLE);
// Halt/Run CPU status
reg cpu_halt_st;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) cpu_halt_st <= 1\'b0;
else cpu_halt_st <= cpu_halt_req & (i_state_nxt==I_IDLE);
//=============================================================================
// 4) INTERRUPT HANDLING & SYSTEM WAKEUP
//=============================================================================
//
// 4.1) INTERRUPT HANDLING
//-----------------------------------------
// Detect reset interrupt
reg inst_irq_rst;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) inst_irq_rst <= 1\'b1;
else if (exec_done) inst_irq_rst <= 1\'b0;
// Detect other interrupts
assign irq_detect = (nmi_pnd | ((|irq | wdt_irq) & gie)) & ~cpu_halt_req & ~cpu_halt_st & (exec_done | (i_state==I_IDLE));
`ifdef CLOCK_GATING
wire mclk_irq_num;
omsp_clock_gate clock_gate_irq_num (.gclk(mclk_irq_num),
.clk (mclk), .enable(irq_detect), .scan_enable(scan_enable));
`else
wire UNUSED_scan_enable = scan_enable;
wire mclk_irq_num = mclk;
`endif
// Combine all IRQs
`ifdef IRQ_16
wire [62:0] irq_all = {nmi_pnd, irq, 48\'h0000_0000_0000} |
`else
`ifdef IRQ_32
wire [62:0] irq_all = {nmi_pnd, irq, 32\'h0000_0000} |
`else
`ifdef IRQ_64
wire [62:0] irq_all = {nmi_pnd, irq} |
`endif
`endif
`endif
{1\'b0, 3\'h0, wdt_irq, {58{1\'b0}}};
// Select highest priority IRQ
reg [5:0] irq_num;
always @(posedge mclk_irq_num or posedge puc_rst)
if (puc_rst) irq_num <= 6\'h3f;
`ifdef CLOCK_GATING
else
`else
else if (irq_detect)
`endif
irq_num <= get_irq_num(irq_all);
// Generate selected IRQ vector address
wire [15:0] irq_addr = {9\'h1ff, irq_num, 1\'b0};
// Interrupt request accepted
wire [63:0] irq_acc_all = one_hot64(irq_num) & {64{(i_state==I_IRQ_FETCH)}};
wire [`IRQ_NR-3:0] irq_acc = irq_acc_all[61:64-`IRQ_NR];
wire nmi_acc = irq_acc_all[62];
//
// 4.2) SYSTEM WAKEUP
//-----------------------------------------
`ifdef CPUOFF_EN
// Generate the main system clock enable signal
// Keep the clock running if:
wire mclk_enable = inst_irq_rst ? cpu_en_s : // - the RESET interrupt is currently executing
// and if the CPU is enabled
// otherwise if:
~((cpuoff | ~cpu_en_s) & // - the CPUOFF flag, cpu_en command, instruction
(i_state==I_IDLE) & // and execution state machines are all two
(e_state==E_IDLE)); // not idle.
// Wakeup condition from maskable interrupts
wire mirq_wkup;
omsp_and_gate and_mirq_wkup (.y(mirq_wkup), .a(wkup | wdt_wkup), .b(gie));
// Combined asynchronous wakeup detection from nmi & irq (masked if the cpu is disabled)
omsp_and_gate and_mclk_wkup (.y(mclk_wkup), .a(nmi_wkup | mirq_wkup), .b(cpu_en_s));
// Wakeup condition from DMA interface
`ifdef DMA_IF_EN
wire mclk_dma_enable = dma_en & cpu_en_s;
omsp_and_gate and_mclk_dma_wkup (.y(mclk_dma_wkup), .a(dma_wkup), .b(cpu_en_s));
`else
assign mclk_dma_wkup = 1\'b0;
assign mclk_dma_enable = 1\'b0;
wire UNUSED_dma_en = dma_en;
wire UNUSED_dma_wkup = dma_wkup;
`endif
`else
// In the CPUOFF feature is disabled, the wake-up and enable signals are always 1
assign mclk_dma_wkup = 1\'b1;
assign mclk_dma_enable = 1\'b1;
assign mclk_wkup = 1\'b1;
assign mclk_enable = 1\'b1;
wire UNUSED_dma_en = dma_en;
wire UNUSED_wkup = wkup;
wire UNUSED_wdt_wkup = wdt_wkup;
wire UNUSED_nmi_wkup = nmi_wkup;
wire UNUSED_dma_wkup = dma_wkup;
`endif
//=============================================================================
// 5) FETCH INSTRUCTION
//=============================================================================
//
// 5.1) PROGRAM COUNTER & MEMORY INTERFACE
//-----------------------------------------
// Program counter
reg [15:0] pc;
// Compute next PC value
wire [15:0] pc_incr = pc + {14\'h0000, fetch, 1\'b0};
wire [15:0] pc_nxt = pc_sw_wr ? pc_sw :
(i_state==I_IRQ_FETCH) ? irq_addr :
(i_state==I_IRQ_DONE) ? mdb_in : pc_incr;
`ifdef CLOCK_GATING
wire pc_en = fetch |
pc_sw_wr |
(i_state==I_IRQ_FETCH) |
(i_state==I_IRQ_DONE);
wire mclk_pc;
omsp_clock_gate clock_gate_pc (.gclk(mclk_pc),
.clk (mclk), .enable(pc_en), .scan_enable(scan_enable));
`else
wire mclk_pc = mclk;
`endif
always @(posedge mclk_pc or posedge puc_rst)
if (puc_rst) pc <= 16\'h0000;
else pc <= pc_nxt;
// Check if Program-Memory has been busy in order to retry Program-Memory access
reg pmem_busy;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) pmem_busy <= 1\'b0;
else pmem_busy <= fe_pmem_wait;
// Memory interface
wire [15:0] mab = pc_nxt;
wire mb_en = fetch | pc_sw_wr | (i_state==I_IRQ_FETCH) | pmem_busy | (cpu_halt_st & ~cpu_halt_req);
//
// 5.2) INSTRUCTION REGISTER
//--------------------------------
// Instruction register
wire [15:0] ir = mdb_in;
// Detect if source extension word is required
wire is_sext = (inst_as[`IDX] | inst_as[`SYMB] | inst_as[`ABS] | inst_as[`IMM]);
// For the Symbolic addressing mode, add -2 to the extension word in order
// to make up for the PC address
wire [15:0] ext_incr = ((i_state==I_EXT1) & inst_as[`SYMB]) |
((i_state==I_EXT2) & inst_ad[`SYMB]) |
((i_state==I_EXT1) & ~inst_as[`SYMB] &
~(i_state_nxt==I_EXT2) & inst_ad[`SYMB]) ? 16\'hfffe : 16\'h0000;
wire [15:0] ext_nxt = ir + ext_incr;
// Store source extension word
reg [15:0] inst_sext;
`ifdef CLOCK_GATING
wire inst_sext_en = (decode & is_const) |
(decode & inst_type_nxt[`INST_JMP]) |
((i_state==I_EXT1) & is_sext);
wire mclk_inst_sext;
omsp_clock_gate clock_gate_inst_sext (.gclk(mclk_inst_sext),
.clk (mclk), .enable(inst_sext_en), .scan_enable(scan_enable));
`else
wire mclk_inst_sext = mclk;
`endif
always @(posedge mclk_inst_sext or posedge puc_rst)
if (puc_rst) inst_sext <= 16\'h0000;
else if (decode & is_const) inst_sext <= sconst_nxt;
else if (decode & inst_type_nxt[`INST_JMP]) inst_sext <= {{5{ir[9]}},ir[9:0],1\'b0};
`ifdef CLOCK_GATING
else inst_sext <= ext_nxt;
`else
else if ((i_state==I_EXT1) & is_sext) inst_sext <= ext_nxt;
`endif
// Source extension word is ready
wire inst_sext_rdy = (i_state==I_EXT1) & is_sext;
// Store destination extension word
reg [15:0] inst_dext;
`ifdef CLOCK_GATING
wire inst_dext_en = ((i_state==I_EXT1) & ~is_sext) |
(i_state==I_EXT2);
wire mclk_inst_dext;
omsp_clock_gate clock_gate_inst_dext (.gclk(mclk_inst_dext),
.clk (mclk), .enable(inst_dext_en), .scan_enable(scan_enable));
`else
wire mclk_inst_dext = mclk;
`endif
always @(posedge mclk_inst_dext or posedge puc_rst)
if (puc_rst) inst_dext <= 16\'h0000;
else if ((i_state==I_EXT1) & ~is_sext) inst_dext <= ext_nxt;
`ifdef CLOCK_GATING
else inst_dext <= ext_nxt;
`else
else if (i_state==I_EXT2) inst_dext <= ext_nxt;
`endif
// Destination extension word is ready
wire inst_dext_rdy = (((i_state==I_EXT1) & ~is_sext) | (i_state==I_EXT2));
//=============================================================================
// 6) DECODE INSTRUCTION
//=============================================================================
`ifdef CLOCK_GATING
wire mclk_decode;
omsp_clock_gate clock_gate_decode (.gclk(mclk_decode),
.clk (mclk), .enable(decode), .scan_enable(scan_enable));
`else
wire mclk_decode = mclk;
`endif
//
// 6.1) OPCODE: INSTRUCTION TYPE
//----------------------------------------
// Instructions type is encoded in a one hot fashion as following:
//
// 3\'b001: Single-operand arithmetic
// 3\'b010: Conditional jump
// 3\'b100: Two-operand arithmetic
reg [2:0] inst_type;
assign inst_type_nxt = {(ir[15:14]!=2\'b00),
(ir[15:13]==3\'b001),
(ir[15:13]==3\'b000)} & {3{~irq_detect}};
always @(posedge mclk_decode or posedge puc_rst)
if (puc_rst) inst_type <= 3\'b000;
`ifdef CLOCK_GATING
else inst_type <= inst_type_nxt;
`else
else if (decode) inst_type <= inst_type_nxt;
`endif
//
// 6.2) OPCODE: SINGLE-OPERAND ARITHMETIC
//----------------------------------------
// Instructions are encoded in a one hot fashion as following:
//
// 8\'b00000001: RRC
// 8\'b00000010: SWPB
// 8\'b00000100: RRA
// 8\'b00001000: SXT
// 8\'b00010000: PUSH
// 8\'b00100000: CALL
// 8\'b01000000: RETI
// 8\'b10000000: IRQ
reg [7:0] inst_so;
wire [7:0] inst_so_nxt = irq_detect ? 8\'h80 : (one_hot8(ir[9:7]) & {8{inst_type_nxt[`INST_SO]}});
always @(posedge mclk_decode or posedge puc_rst)
if (puc_rst) inst_so <= 8\'h00;
`ifdef CLOCK_GATING
else inst_so <= inst_so_nxt;
`else
else if (decode) inst_so <= inst_so_nxt;
`endif
//
// 6.3) OPCODE: CONDITIONAL JUMP
//--------------------------------
// Instructions are encoded in a one hot fashion as following:
//
// 8\'b00000001: JNE/JNZ
// 8\'b00000010: JEQ/JZ
// 8\'b00000100: JNC/JLO
// 8\'b00001000: JC/JHS
// 8\'b00010000: JN
// 8\'b00100000: JGE
// 8\'b01000000: JL
// 8\'b10000000: JMP
reg [2:0] inst_jmp_bin;
always @(posedge mclk_decode or posedge puc_rst)
if (puc_rst) inst_jmp_bin <= 3\'h0;
`ifdef CLOCK_GATING
else inst_jmp_bin <= ir[12:10];
`else
else if (decode) inst_jmp_bin <= ir[12:10];
`endif
wire [7:0] inst_jmp = one_hot8(inst_jmp_bin) & {8{inst_type[`INST_JMP]}};
//
// 6.4) OPCODE: TWO-OPERAND ARITHMETIC
//-------------------------------------
// Instructions are encoded in a one hot fashion as following:
//
// 12\'b000000000001: MOV
// 12\'b000000000010: ADD
// 12\'b000000000100: ADDC
// 12\'b000000001000: SUBC
// 12\'b000000010000: SUB
// 12\'b000000100000: CMP
// 12\'b000001000000: DADD
// 12\'b000010000000: BIT
// 12\'b000100000000: BIC
// 12\'b001000000000: BIS
// 12\'b010000000000: XOR
// 12\'b100000000000: AND
wire [15:0] inst_to_1hot = one_hot16(ir[15:12]) & {16{inst_type_nxt[`INST_TO]}};
wire [11:0] inst_to_nxt = inst_to_1hot[15:4];
reg inst_mov;
always @(posedge mclk_decode or posedge puc_rst)
if (puc_rst) inst_mov <= 1\'b0;
`ifdef CLOCK_GATING
else inst_mov <= inst_to_nxt[`MOV];
`else
else if (decode) inst_mov <= inst_to_nxt[`MOV];
`endif
//
// 6.5) SOURCE AND DESTINATION REGISTERS
//---------------------------------------
// Destination register
reg [3:0] inst_dest_bin;
always @(posedge mclk_decode or posedge puc_rst)
if (puc_rst) inst_dest_bin <= 4\'h0;
`ifdef CLOCK_GATING
else inst_dest_bin <= ir[3:0];
`else
else if (decode) inst_dest_bin <= ir[3:0];
`endif
wire [15:0] inst_dest = cpu_halt_st ? one_hot16(dbg_reg_sel) :
inst_type[`INST_JMP] ? 16\'h0001 :
inst_so[`IRQ] |
inst_so[`PUSH] |
inst_so[`CALL] ? 16\'h0002 :
one_hot16(inst_dest_bin);
// Source register
reg [3:0] inst_src_bin;
always @(posedge mclk_decode or posedge puc_rst)
if (puc_rst) inst_src_bin <= 4\'h0;
`ifdef CLOCK_GATING
else inst_src_bin <= ir[11:8];
`else
else if (decode) inst_src_bin <= ir[11:8];
`endif
wire [15:0] inst_src = inst_type[`INST_TO] ? one_hot16(inst_src_bin) :
inst_so[`RETI] ? 16\'h0002 :
inst_so[`IRQ] ? 16\'h0001 :
inst_type[`INST_SO] ? one_hot16(inst_dest_bin) : 16\'h0000;
//
// 6.6) SOURCE ADDRESSING MODES
//--------------------------------
// Source addressing modes are encoded in a one hot fashion as following:
//
// 13\'b0000000000001: Register direct.
// 13\'b0000000000010: Register indexed.
// 13\'b0000000000100: Register indirect.
// 13\'b0000000001000: Register indirect autoincrement.
// 13\'b0000000010000: Symbolic (operand is in memory at address PC+x).
// 13\'b0000000100000: Immediate (operand is next word in the instruction stream).
// 13\'b0000001000000: Absolute (operand is in memory at address x).
// 13\'b0000010000000: Constant 4.
// 13\'b0000100000000: Constant 8.
// 13\'b0001000000000: Constant 0.
// 13\'b0010000000000: Constant 1.
// 13\'b0100000000000: Constant 2.
// 13\'b1000000000000: Constant -1.
reg [12:0] inst_as_nxt;
wire [3:0] src_reg = inst_type_nxt[`INST_SO] ? ir[3:0] : ir[11:8];
always @(src_reg or ir or inst_type_nxt)
begin
if (inst_type_nxt[`INST_JMP])
inst_as_nxt = 13\'b0000000000001;
else if (src_reg==4\'h3) // Addressing mode using R3
case (ir[5:4])
2\'b11 : inst_as_nxt = 13\'b1000000000000;
2\'b10 : inst_as_nxt = 13\'b0100000000000;
2\'b01 : inst_as_nxt = 13\'b0010000000000;
default: inst_as_nxt = 13\'b0001000000000;
endcase
else if (src_reg==4\'h2) // Addressing mode using R2
case (ir[5:4])
2\'b11 : inst_as_nxt = 13\'b0000100000000;
2\'b10 : inst_as_nxt = 13\'b0000010000000;
2\'b01 : inst_as_nxt = 13\'b0000001000000;
default: inst_as_nxt = 13\'b0000000000001;
endcase
else if (src_reg==4\'h0) // Addressing mode using R0
case (ir[5:4])
2\'b11 : inst_as_nxt = 13\'b0000000100000;
2\'b10 : inst_as_nxt = 13\'b0000000000100;
2\'b01 : inst_as_nxt = 13\'b0000000010000;
default: inst_as_nxt = 13\'b0000000000001;
endcase
else // General Addressing mode
case (ir[5:4])
2\'b11 : inst_as_nxt = 13\'b0000000001000;
2\'b10 : inst_as_nxt = 13\'b0000000000100;
2\'b01 : inst_as_nxt = 13\'b0000000000010;
default: inst_as_nxt = 13\'b0000000000001;
endcase
end
assign is_const = |inst_as_nxt[12:7];
reg [7:0] inst_as;
always @(posedge mclk_decode or posedge puc_rst)
if (puc_rst) inst_as <= 8\'h00;
`ifdef CLOCK_GATING
else inst_as <= {is_const, inst_as_nxt[6:0]};
`else
else if (decode) inst_as <= {is_const, inst_as_nxt[6:0]};
`endif
// 13\'b0000010000000: Constant 4.
// 13\'b0000100000000: Constant 8.
// 13\'b0001000000000: Constant 0.
// 13\'b0010000000000: Constant 1.
// 13\'b0100000000000: Constant 2.
// 13\'b1000000000000: Constant -1.
always @(inst_as_nxt)
begin
if (inst_as_nxt[7]) sconst_nxt = 16\'h0004;
else if (inst_as_nxt[8]) sconst_nxt = 16\'h0008;
else if (inst_as_nxt[9]) sconst_nxt = 16\'h0000;
else if (inst_as_nxt[10]) sconst_nxt = 16\'h0001;
else if (inst_as_nxt[11]) sconst_nxt = 16\'h0002;
else if (inst_as_nxt[12]) sconst_nxt = 16\'hffff;
else sconst_nxt = 16\'h0000;
end
//
// 6.7) DESTINATION ADDRESSING MODES
//-----------------------------------
// Destination addressing modes are encoded in a one hot fashion as following:
//
// 8\'b00000001: Register direct.
// 8\'b00000010: Register indexed.
// 8\'b00010000: Symbolic (operand is in memory at address PC+x).
// 8\'b01000000: Absolute (operand is in memory at address x).
reg [7:0] inst_ad_nxt;
wire [3:0] dest_reg = ir[3:0];
always @(dest_reg or ir or inst_type_nxt)
begin
if (~inst_type_nxt[`INST_TO])
inst_ad_nxt = 8\'b00000000;
else if (dest_reg==4\'h2) // Addressing mode using R2
case (ir[7])
1\'b1 : inst_ad_nxt = 8\'b01000000;
default: inst_ad_nxt = 8\'b00000001;
endcase
else if (dest_reg==4\'h0) // Addressing mode using R0
case (ir[7])
1\'b1 : inst_ad_nxt = 8\'b00010000;
default: inst_ad_nxt = 8\'b00000001;
endcase
else // General Addressing mode
case (ir[7])
1\'b1 : inst_ad_nxt = 8\'b00000010;
default: inst_ad_nxt = 8\'b00000001;
endcase
end
reg [7:0] inst_ad;
always @(posedge mclk_decode or posedge puc_rst)
if (puc_rst) inst_ad <= 8\'h00;
`ifdef CLOCK_GATING
else inst_ad <= inst_ad_nxt;
`else
else if (decode) inst_ad <= inst_ad_nxt;
`endif
//
// 6.8) REMAINING INSTRUCTION DECODING
//-------------------------------------
// Operation size
reg inst_bw;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) inst_bw <= 1\'b0;
else if (decode) inst_bw <= ir[6] & ~inst_type_nxt[`INST_JMP] & ~irq_detect & ~cpu_halt_req;
// Extended instruction size
assign inst_sz_nxt = {1\'b0, (inst_as_nxt[`IDX] | inst_as_nxt[`SYMB] | inst_as_nxt[`ABS] | inst_as_nxt[`IMM])} +
{1\'b0, ((inst_ad_nxt[`IDX] | inst_ad_nxt[`SYMB] | inst_ad_nxt[`ABS]) & ~inst_type_nxt[`INST_SO])};
always @(posedge mclk_decode or posedge puc_rst)
if (puc_rst) inst_sz <= 2\'b00;
`ifdef CLOCK_GATING
else inst_sz <= inst_sz_nxt;
`else
else if (decode) inst_sz <= inst_sz_nxt;
`endif
//=============================================================================
// 7) EXECUTION-UNIT STATE MACHINE
//=============================================================================
// State machine registers
reg [3:0] e_state;
// State machine control signals
//--------------------------------
wire src_acalc_pre = inst_as_nxt[`IDX] | inst_as_nxt[`SYMB] | inst_as_nxt[`ABS];
wire src_rd_pre = inst_as_nxt[`INDIR] | inst_as_nxt[`INDIR_I] | inst_as_nxt[`IMM] | inst_so_nxt[`RETI];
wire dst_acalc_pre = inst_ad_nxt[`IDX] | inst_ad_nxt[`SYMB] | inst_ad_nxt[`ABS];
wire dst_acalc = inst_ad[`IDX] | inst_ad[`SYMB] | inst_ad[`ABS];
wire dst_rd_pre = inst_ad_nxt[`IDX] | inst_so_nxt[`PUSH] | inst_so_nxt[`CALL] | inst_so_nxt[`RETI];
wire dst_rd = inst_ad[`IDX] | inst_so[`PUSH] | inst_so[`CALL] | inst_so[`RETI];
wire inst_branch = (inst_ad_nxt[`DIR] & (ir[3:0]==4\'h0)) | inst_type_nxt[`INST_JMP] | inst_so_nxt[`RETI];
reg exec_jmp;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) exec_jmp <= 1\'b0;
else if (inst_branch & decode) exec_jmp <= 1\'b1;
else if (e_state==E_JUMP) exec_jmp <= 1\'b0;
reg exec_dst_wr;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) exec_dst_wr <= 1\'b0;
else if (e_state==E_DST_RD) exec_dst_wr <= 1\'b1;
else if (e_state==E_DST_WR) exec_dst_wr <= 1\'b0;
reg exec_src_wr;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) exec_src_wr <= 1\'b0;
else if (inst_type[`INST_SO] & (e_state==E_SRC_RD)) exec_src_wr <= 1\'b1;
else if ((e_state==E_SRC_WR) || (e_state==E_DST_WR)) exec_src_wr <= 1\'b0;
reg exec_dext_rdy;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) exec_dext_rdy <= 1\'b0;
else if (e_state==E_DST_RD) exec_dext_rdy <= 1\'b0;
else if (inst_dext_rdy) exec_dext_rdy <= 1\'b1;
// Execution first state
wire [3:0] e_first_state = ~cpu_halt_st & inst_so_nxt[`IRQ] ? E_IRQ_0 :
cpu_halt_req | (i_state==I_IDLE) ? E_IDLE :
cpuoff ? E_IDLE :
src_acalc_pre ? E_SRC_AD :
src_rd_pre ? E_SRC_RD :
dst_acalc_pre ? E_DST_AD :
dst_rd_pre ? E_DST_RD : E_EXEC;
// State machine
//--------------------------------
// States Transitions
always @(e_state or dst_acalc or dst_rd or inst_sext_rdy or
inst_dext_rdy or exec_dext_rdy or exec_jmp or exec_dst_wr or
e_first_state or exec_src_wr)
case(e_state)
E_IDLE : e_state_nxt = e_first_state;
E_IRQ_0 : e_state_nxt = E_IRQ_1;
E_IRQ_1 : e_state_nxt = E_IRQ_2;
E_IRQ_2 : e_state_nxt = E_IRQ_3;
E_IRQ_3 : e_state_nxt = E_IRQ_4;
E_IRQ_4 : e_state_nxt = E_EXEC;
E_SRC_AD : e_state_nxt = inst_sext_rdy ? E_SRC_RD : E_SRC_AD;
E_SRC_RD : e_state_nxt = dst_acalc ? E_DST_AD :
dst_rd ? E_DST_RD : E_EXEC;
E_DST_AD : e_state_nxt = (inst_dext_rdy |
exec_dext_rdy) ? E_DST_RD : E_DST_AD;
E_DST_RD : e_state_nxt = E_EXEC;
E_EXEC : e_state_nxt = exec_dst_wr ? E_DST_WR :
exec_jmp ? E_JUMP :
exec_src_wr ? E_SRC_WR : e_first_state;
E_JUMP : e_state_nxt = e_first_state;
E_DST_WR : e_state_nxt = exec_jmp ? E_JUMP : e_first_state;
E_SRC_WR : e_state_nxt = e_first_state;
// pragma coverage off
default : e_state_nxt = E_IRQ_0;
// pragma coverage on
endcase
// State machine
always @(posedge mclk or posedge puc_rst)
if (puc_rst) e_state <= E_IRQ_1;
else e_state <= e_state_nxt;
// Frontend State machine control signals
//----------------------------------------
wire exec_done = exec_jmp ? (e_state==E_JUMP) :
exec_dst_wr ? (e_state==E_DST_WR) :
exec_src_wr ? (e_state==E_SRC_WR) : (e_state==E_EXEC);
//=============================================================================
// 8) EXECUTION-UNIT STATE CONTROL
//=============================================================================
//
// 8.1) ALU CONTROL SIGNALS
//-------------------------------------
//
// 12\'b000000000001: Enable ALU source inverter
// 12\'b000000000010: Enable Incrementer
// 12\'b000000000100: Enable Incrementer on carry bit
// 12\'b000000001000: Select Adder
// 12\'b000000010000: Select AND
// 12\'b000000100000: Select OR
// 12\'b000001000000: Select XOR
// 12\'b000010000000: Select DADD
// 12\'b000100000000: Update N, Z & C (C=~Z)
// 12\'b001000000000: Update all status bits
// 12\'b010000000000: Update status bit for XOR instruction
// 12\'b100000000000: Don\'t write to destination
reg [11:0] inst_alu;
wire alu_src_inv = inst_to_nxt[`SUB] | inst_to_nxt[`SUBC] |
inst_to_nxt[`CMP] | inst_to_nxt[`BIC] ;
wire alu_inc = inst_to_nxt[`SUB] | inst_to_nxt[`CMP];
wire alu_inc_c = inst_to_nxt[`ADDC] | inst_to_nxt[`DADD] |
inst_to_nxt[`SUBC];
wire alu_add = inst_to_nxt[`ADD] | inst_to_nxt[`ADDC] |
inst_to_nxt[`SUB] | inst_to_nxt[`SUBC] |
inst_to_nxt[`CMP] | inst_type_nxt[`INST_JMP] |
inst_so_nxt[`RETI];
wire alu_and = inst_to_nxt[`AND] | inst_to_nxt[`BIC] |
inst_to_nxt[`BIT];
wire alu_or = inst_to_nxt[`BIS];
wire alu_xor = inst_to_nxt[`XOR];
wire alu_dadd = inst_to_nxt[`DADD];
wire alu_stat_7 = inst_to_nxt[`BIT] | inst_to_nxt[`AND] |
inst_so_nxt[`SXT];
wire alu_stat_f = inst_to_nxt[`ADD] | inst_to_nxt[`ADDC] |
inst_to_nxt[`SUB] | inst_to_nxt[`SUBC] |
inst_to_nxt[`CMP] | inst_to_nxt[`DADD] |
inst_to_nxt[`BIT] | inst_to_nxt[`XOR] |
inst_to_nxt[`AND] |
inst_so_nxt[`RRC] | inst_so_nxt[`RRA] |
inst_so_nxt[`SXT];
wire alu_shift = inst_so_nxt[`RRC] | inst_so_nxt[`RRA];
wire exec_no_wr = inst_to_nxt[`CMP] | inst_to_nxt[`BIT];
wire [11:0] inst_alu_nxt = {exec_no_wr,
alu_shift,
alu_stat_f,
alu_stat_7'b',
alu_dadd,
alu_xor,
alu_or,
alu_and,
alu_add,
alu_inc_c,
alu_inc,
alu_src_inv};
always @(posedge mclk_decode or posedge puc_rst)
if (puc_rst) inst_alu <= 12\'h000;
`ifdef CLOCK_GATING
else inst_alu <= inst_alu_nxt;
`else
else if (decode) inst_alu <= inst_alu_nxt;
`endif
endmodule // omsp_frontend
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_sync_cell.v
//
// *Module Description:
// Generic synchronizer for the openMSP430
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
module omsp_sync_cell (
// OUTPUTs
data_out, // Synchronized data output
// INPUTs
clk, // Receiving clock
data_in, // Asynchronous data input
rst // Receiving reset (active high)
);
// OUTPUTs
//=========
output data_out; // Synchronized data output
// INPUTs
//=========
input clk; // Receiving clock
input data_in; // Asynchronous data input
input rst; // Receiving reset (active high)
//=============================================================================
// 1) SYNCHRONIZER
//=============================================================================
reg [1:0] data_sync;
always @(posedge clk or posedge rst)
if (rst) data_sync <= 2\'b00;
else data_sync <= {data_sync[0], data_in};
assign data_out = data_sync[1];
endmodule // omsp_sync_cell
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_mem_backbone.v
//
// *Module Description:
// Memory interface backbone (decoder + arbiter)
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module omsp_mem_backbone (
// OUTPUTs
cpu_halt_cmd, // Halt CPU command
dbg_mem_din, // Debug unit Memory data input
dmem_addr, // Data Memory address
dmem_cen, // Data Memory chip enable (low active)
dmem_din, // Data Memory data input
dmem_wen, // Data Memory write enable (low active)
eu_mdb_in, // Execution Unit Memory data bus input
fe_mdb_in, // Frontend Memory data bus input
fe_pmem_wait, // Frontend wait for Instruction fetch
dma_dout, // Direct Memory Access data output
dma_ready, // Direct Memory Access is complete
dma_resp, // Direct Memory Access response (0:Okay / 1:Error)
per_addr, // Peripheral address
per_din, // Peripheral data input
per_we, // Peripheral write enable (high active)
per_en, // Peripheral enable (high active)
pmem_addr, // Program Memory address
pmem_cen, // Program Memory chip enable (low active)
pmem_din, // Program Memory data input (optional)
pmem_wen, // Program Memory write enable (low active) (optional)
// INPUTs
cpu_halt_st, // Halt/Run status from CPU
dbg_halt_cmd, // Debug interface Halt CPU command
dbg_mem_addr, // Debug address for rd/wr access
dbg_mem_dout, // Debug unit data output
dbg_mem_en, // Debug unit memory enable
dbg_mem_wr, // Debug unit memory write
dmem_dout, // Data Memory data output
eu_mab, // Execution Unit Memory address bus
eu_mb_en, // Execution Unit Memory bus enable
eu_mb_wr, // Execution Unit Memory bus write transfer
eu_mdb_out, // Execution Unit Memory data bus output
fe_mab, // Frontend Memory address bus
fe_mb_en, // Frontend Memory bus enable
mclk, // Main system clock
dma_addr, // Direct Memory Access address
dma_din, // Direct Memory Access data input
dma_en, // Direct Memory Access enable (high active)
dma_priority, // Direct Memory Access priority (0:low / 1:high)
dma_we, // Direct Memory Access write byte enable (high active)
per_dout, // Peripheral data output
pmem_dout, // Program Memory data output
puc_rst, // Main system reset
scan_enable // Scan enable (active during scan shifting)
);
// OUTPUTs
//=========
output cpu_halt_cmd; // Halt CPU command
output [15:0] dbg_mem_din; // Debug unit Memory data input
output [`DMEM_MSB:0] dmem_addr; // Data Memory address
output dmem_cen; // Data Memory chip enable (low active)
output [15:0] dmem_din; // Data Memory data input
output [1:0] dmem_wen; // Data Memory write enable (low active)
output [15:0] eu_mdb_in; // Execution Unit Memory data bus input
output [15:0] fe_mdb_in; // Frontend Memory data bus input
output fe_pmem_wait; // Frontend wait for Instruction fetch
output [15:0] dma_dout; // Direct Memory Access data output
output dma_ready; // Direct Memory Access is complete
output dma_resp; // Direct Memory Access response (0:Okay / 1:Error)
output [13:0] per_addr; // Peripheral address
output [15:0] per_din; // Peripheral data input
output [1:0] per_we; // Peripheral write enable (high active)
output per_en; // Peripheral enable (high active)
output [`PMEM_MSB:0] pmem_addr; // Program Memory address
output pmem_cen; // Program Memory chip enable (low active)
output [15:0] pmem_din; // Program Memory data input (optional)
output [1:0] pmem_wen; // Program Memory write enable (low active) (optional)
// INPUTs
//=========
input cpu_halt_st; // Halt/Run status from CPU
input dbg_halt_cmd; // Debug interface Halt CPU command
input [15:1] dbg_mem_addr; // Debug address for rd/wr access
input [15:0] dbg_mem_dout; // Debug unit data output
input dbg_mem_en; // Debug unit memory enable
input [1:0] dbg_mem_wr; // Debug unit memory write
input [15:0] dmem_dout; // Data Memory data output
input [14:0] eu_mab; // Execution Unit Memory address bus
input eu_mb_en; // Execution Unit Memory bus enable
input [1:0] eu_mb_wr; // Execution Unit Memory bus write transfer
input [15:0] eu_mdb_out; // Execution Unit Memory data bus output
input [14:0] fe_mab; // Frontend Memory address bus
input fe_mb_en; // Frontend Memory bus enable
input mclk; // Main system clock
input [15:1] dma_addr; // Direct Memory Access address
input [15:0] dma_din; // Direct Memory Access data input
input dma_en; // Direct Memory Access enable (high active)
input dma_priority; // Direct Memory Access priority (0:low / 1:high)
input [1:0] dma_we; // Direct Memory Access write byte enable (high active)
input [15:0] per_dout; // Peripheral data output
input [15:0] pmem_dout; // Program Memory data output
input puc_rst; // Main system reset
input scan_enable; // Scan enable (active during scan shifting)
wire ext_mem_en;
wire [15:0] ext_mem_din;
wire ext_dmem_sel;
wire ext_dmem_en;
wire ext_pmem_sel;
wire ext_pmem_en;
wire ext_per_sel;
wire ext_per_en;
//=============================================================================
// 1) DECODER
//=============================================================================
//------------------------------------------
// Arbiter between DMA and Debug interface
//------------------------------------------
`ifdef DMA_IF_EN
// Debug-interface always stops the CPU
// Master interface stops the CPU in priority mode
assign cpu_halt_cmd = dbg_halt_cmd | (dma_en & dma_priority);
// Return ERROR response if address lays outside the memory spaces (Peripheral, Data & Program memories)
assign dma_resp = ~dbg_mem_en & ~(ext_dmem_sel | ext_pmem_sel | ext_per_sel) & dma_en;
// Master interface access is ready when the memory access occures
assign dma_ready = ~dbg_mem_en & (ext_dmem_en | ext_pmem_en | ext_per_en | dma_resp);
// Use delayed version of \'dma_ready\' to mask the \'dma_dout\' data output
// when not accessed and reduce toggle rate (thus power consumption)
reg dma_ready_dly;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) dma_ready_dly <= 1\'b0;
else dma_ready_dly <= dma_ready;
// Mux between debug and master interface
assign ext_mem_en = dbg_mem_en | dma_en;
wire [1:0] ext_mem_wr = dbg_mem_en ? dbg_mem_wr : dma_we;
wire [15:1] ext_mem_addr = dbg_mem_en ? dbg_mem_addr : dma_addr;
wire [15:0] ext_mem_dout = dbg_mem_en ? dbg_mem_dout : dma_din;
// External interface read data
assign dbg_mem_din = ext_mem_din;
assign dma_dout = ext_mem_din & {16{dma_ready_dly}};
`else
// Debug-interface always stops the CPU
assign cpu_halt_cmd = dbg_halt_cmd;
// Master interface access is always ready with error response when excluded
assign dma_resp = 1\'b1;
assign dma_ready = 1\'b1;
// Debug interface only
assign ext_mem_en = dbg_mem_en;
wire [1:0] ext_mem_wr = dbg_mem_wr;
wire [15:1] ext_mem_addr = dbg_mem_addr;
wire [15:0] ext_mem_dout = dbg_mem_dout;
// External interface read data
assign dbg_mem_din = ext_mem_din;
assign dma_dout = 16\'h0000;
// LINT Cleanup
wire [15:1] UNUSED_dma_addr = dma_addr;
wire [15:0] UNUSED_dma_din = dma_din;
wire UNUSED_dma_en = dma_en;
wire UNUSED_dma_priority = dma_priority;
wire [1:0] UNUSED_dma_we = dma_we;
`endif
//------------------------------------------
// DATA-MEMORY Interface
//------------------------------------------
parameter DMEM_END = `DMEM_BASE+`DMEM_SIZE;
// Execution unit access
wire eu_dmem_sel = (eu_mab>=(`DMEM_BASE>>1)) &
(eu_mab< ( DMEM_END >>1));
wire eu_dmem_en = eu_mb_en & eu_dmem_sel;
wire [15:0] eu_dmem_addr = {1\'b0, eu_mab}-(`DMEM_BASE>>1);
// Front-end access
// -- not allowed to execute from data memory --
// External Master/Debug interface access
assign ext_dmem_sel = (ext_mem_addr[15:1]>=(`DMEM_BASE>>1)) &
(ext_mem_addr[15:1]< ( DMEM_END >>1));
assign ext_dmem_en = ext_mem_en & ext_dmem_sel & ~eu_dmem_en;
wire [15:0] ext_dmem_addr = {1\'b0, ext_mem_addr[15:1]}-(`DMEM_BASE>>1);
// Data-Memory Interface
wire dmem_cen = ~(ext_dmem_en | eu_dmem_en);
wire [1:0] dmem_wen = ext_dmem_en ? ~ext_mem_wr : ~eu_mb_wr;
wire [`DMEM_MSB:0] dmem_addr = ext_dmem_en ? ext_dmem_addr[`DMEM_MSB:0] : eu_dmem_addr[`DMEM_MSB:0];
wire [15:0] dmem_din = ext_dmem_en ? ext_mem_dout : eu_mdb_out;
//------------------------------------------
// PROGRAM-MEMORY Interface
//------------------------------------------
parameter PMEM_OFFSET = (16\'hFFFF-`PMEM_SIZE+1);
// Execution unit access (only read access are accepted)
wire eu_pmem_sel = (eu_mab>=(PMEM_OFFSET>>1));
wire eu_pmem_en = eu_mb_en & ~|eu_mb_wr & eu_pmem_sel;
wire [15:0] eu_pmem_addr = eu_mab-(PMEM_OFFSET>>1);
// Front-end access
wire fe_pmem_sel = (fe_mab>=(PMEM_OFFSET>>1));
wire fe_pmem_en = fe_mb_en & fe_pmem_sel;
wire [15:0] fe_pmem_addr = fe_mab-(PMEM_OFFSET>>1);
// External Master/Debug interface access
assign ext_pmem_sel = (ext_mem_addr[15:1]>=(PMEM_OFFSET>>1));
assign ext_pmem_en = ext_mem_en & ext_pmem_sel & ~eu_pmem_en & ~fe_pmem_en;
wire [15:0] ext_pmem_addr = {1\'b0, ext_mem_addr[15:1]}-(PMEM_OFFSET>>1);
// Program-Memory Interface (Execution unit has priority over the Front-end)
wire pmem_cen = ~(fe_pmem_en | eu_pmem_en | ext_pmem_en);
wire [1:0] pmem_wen = ext_pmem_en ? ~ext_mem_wr : 2\'b11;
wire [`PMEM_MSB:0] pmem_addr = ext_pmem_en ? ext_pmem_addr[`PMEM_MSB:0] :
eu_pmem_en ? eu_pmem_addr[`PMEM_MSB:0] : fe_pmem_addr[`PMEM_MSB:0];
wire [15:0] pmem_din = ext_mem_dout;
wire fe_pmem_wait = (fe_pmem_en & eu_pmem_en);
//------------------------------------------
// PERIPHERALS Interface
//------------------------------------------
// Execution unit access
wire eu_per_sel = (eu_mab<(`PER_SIZE>>1));
wire eu_per_en = eu_mb_en & eu_per_sel;
// Front-end access
// -- not allowed to execute from peripherals memory space --
// External Master/Debug interface access
assign ext_per_sel = (ext_mem_addr[15:1]<(`PER_SIZE>>1));
assign ext_per_en = ext_mem_en & ext_per_sel & ~eu_per_en;
// Peripheral Interface
wire per_en = ext_per_en | eu_per_en;
wire [1:0] per_we = ext_per_en ? ext_mem_wr : eu_mb_wr;
wire [`PER_MSB:0] per_addr_mux = ext_per_en ? ext_mem_addr[`PER_MSB+1:1] : eu_mab[`PER_MSB:0];
wire [14:0] per_addr_ful = {{15-`PER_AWIDTH{1\'b0}}, per_addr_mux};
wire [13:0] per_addr = per_addr_ful[13:0];
wire [15:0] per_din = ext_per_en ? ext_mem_dout : eu_mdb_out;
// Register peripheral data read path
reg [15:0] per_dout_val;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) per_dout_val <= 16\'h0000;
else per_dout_val <= per_dout;
//------------------------------------------
// Frontend data Mux
//------------------------------------------
// Whenever the frontend doesn\'t access the program memory, backup the data
// Detect whenever the data should be backuped and restored
reg fe_pmem_en_dly;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) fe_pmem_en_dly <= 1\'b0;
else fe_pmem_en_dly <= fe_pmem_en;
wire fe_pmem_save = (~fe_pmem_en & fe_pmem_en_dly) & ~cpu_halt_st;
wire fe_pmem_restore = ( fe_pmem_en & ~fe_pmem_en_dly) | cpu_halt_st;
`ifdef CLOCK_GATING
wire mclk_bckup_gated;
omsp_clock_gate clock_gate_bckup (.gclk(mclk_bckup_gated),
.clk (mclk), .enable(fe_pmem_save), .scan_enable(scan_enable));
`define MCLK_BCKUP mclk_bckup_gated
`else
wire UNUSED_scan_enable = scan_enable;
`define MCLK_BCKUP mclk // use macro to solve delta cycle issues with some mixed VHDL/Verilog simulators
`endif
reg [15:0] pmem_dout_bckup;
always @(posedge `MCLK_BCKUP or posedge puc_rst)
if (puc_rst) pmem_dout_bckup <= 16\'h0000;
`ifdef CLOCK_GATING
else pmem_dout_bckup <= pmem_dout;
`else
else if (fe_pmem_save) pmem_dout_bckup <= pmem_dout;
`endif
// Mux between the Program memory data and the backup
reg pmem_dout_bckup_sel;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) pmem_dout_bckup_sel <= 1\'b0;
else if (fe_pmem_save) pmem_dout_bckup_sel <= 1\'b1;
else if (fe_pmem_restore) pmem_dout_bckup_sel <= 1\'b0;
assign fe_mdb_in = pmem_dout_bckup_sel ? pmem_dout_bckup : pmem_dout;
//------------------------------------------
// Execution-Unit data Mux
//------------------------------------------
// Select between Peripherals, Program and Data memories
reg [1:0] eu_mdb_in_sel;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) eu_mdb_in_sel <= 2\'b00;
else eu_mdb_in_sel <= {eu_pmem_en, eu_per_en};
// Mux
assign eu_mdb_in = eu_mdb_in_sel[1] ? pmem_dout :
eu_mdb_in_sel[0] ? per_dout_val : dmem_dout;
//------------------------------------------
// External Master/Debug interface data Mux
//------------------------------------------
// Select between Peripherals, Program and Data memories
reg [1:0] ext_mem_din_sel;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) ext_mem_din_sel <= 2\'b00;
else ext_mem_din_sel <= {ext_pmem_en, ext_per_en};
// Mux
assign ext_mem_din = ext_mem_din_sel[1] ? pmem_dout :
ext_mem_din_sel[0] ? per_dout_val : dmem_dout;
endmodule // omsp_mem_backbone
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
// Generator : SpinalHDL v1.2.0 git head : cf3b44dbd881428e70669e5b623479c23b2d0ddd
// Date : 07/11/2018, 09:09:46
// Component : Murax
`define JtagState_defaultEncoding_type [3:0]
`define JtagState_defaultEncoding_RESET 4'b0000
`define JtagState_defaultEncoding_IDLE 4'b0001
`define JtagState_defaultEncoding_IR_SELECT 4'b0010
`define JtagState_defaultEncoding_IR_CAPTURE 4'b0011
`define JtagState_defaultEncoding_IR_SHIFT 4'b0100
`define JtagState_defaultEncoding_IR_EXIT1 4'b0101
`define JtagState_defaultEncoding_IR_PAUSE 4'b0110
`define JtagState_defaultEncoding_IR_EXIT2 4'b0111
`define JtagState_defaultEncoding_IR_UPDATE 4'b1000
`define JtagState_defaultEncoding_DR_SELECT 4'b1001
`define JtagState_defaultEncoding_DR_CAPTURE 4'b1010
`define JtagState_defaultEncoding_DR_SHIFT 4'b1011
`define JtagState_defaultEncoding_DR_EXIT1 4'b1100
`define JtagState_defaultEncoding_DR_PAUSE 4'b1101
`define JtagState_defaultEncoding_DR_EXIT2 4'b1110
`define JtagState_defaultEncoding_DR_UPDATE 4'b1111
`define Src1CtrlEnum_defaultEncoding_type [1:0]
`define Src1CtrlEnum_defaultEncoding_RS 2'b00
`define Src1CtrlEnum_defaultEncoding_IMU 2'b01
`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10
`define UartCtrlTxState_defaultEncoding_type [2:0]
`define UartCtrlTxState_defaultEncoding_IDLE 3'b000
`define UartCtrlTxState_defaultEncoding_START 3'b001
`define UartCtrlTxState_defaultEncoding_DATA 3'b010
`define UartCtrlTxState_defaultEncoding_PARITY 3'b011
`define UartCtrlTxState_defaultEncoding_STOP 3'b100
`define Src2CtrlEnum_defaultEncoding_type [1:0]
`define Src2CtrlEnum_defaultEncoding_RS 2'b00
`define Src2CtrlEnum_defaultEncoding_IMI 2'b01
`define Src2CtrlEnum_defaultEncoding_IMS 2'b10
`define Src2CtrlEnum_defaultEncoding_PC 2'b11
`define BranchCtrlEnum_defaultEncoding_type [1:0]
`define BranchCtrlEnum_defaultEncoding_INC 2'b00
`define BranchCtrlEnum_defaultEncoding_B 2'b01
`define BranchCtrlEnum_defaultEncoding_JAL 2'b10
`define BranchCtrlEnum_defaultEncoding_JALR 2'b11
`define ShiftCtrlEnum_defaultEncoding_type [1:0]
`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00
`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01
`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10
`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11
`define UartCtrlRxState_defaultEncoding_type [2:0]
`define UartCtrlRxState_defaultEncoding_IDLE 3'b000
`define UartCtrlRxState_defaultEncoding_START 3'b001
`define UartCtrlRxState_defaultEncoding_DATA 3'b010
`define UartCtrlRxState_defaultEncoding_PARITY 3'b011
`define UartCtrlRxState_defaultEncoding_STOP 3'b100
`define UartParityType_defaultEncoding_type [1:0]
`define UartParityType_defaultEncoding_NONE 2'b00
`define UartParityType_defaultEncoding_EVEN 2'b01
`define UartParityType_defaultEncoding_ODD 2'b10
`define UartStopType_defaultEncoding_type [0:0]
`define UartStopType_defaultEncoding_ONE 1'b0
`define UartStopType_defaultEncoding_TWO 1'b1
`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0]
`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00
`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01
`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10
`define AluBitwiseCtrlEnum_defaultEncoding_SRC1 2'b11
`define EnvCtrlEnum_defaultEncoding_type [2:0]
`define EnvCtrlEnum_defaultEncoding_NONE 3'b000
`define EnvCtrlEnum_defaultEncoding_EBREAK 3'b001
`define EnvCtrlEnum_defaultEncoding_MRET 3'b010
`define EnvCtrlEnum_defaultEncoding_WFI 3'b011
`define EnvCtrlEnum_defaultEncoding_ECALL 3'b100
`define AluCtrlEnum_defaultEncoding_type [1:0]
`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00
`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01
`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10
module BufferCC (
input io_initial,
input io_dataIn,
output io_dataOut,
input io_mainClk,
input resetCtrl_systemReset);
reg buffers_0;
reg buffers_1;
assign io_dataOut = buffers_1;
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
buffers_0 <= io_initial;
buffers_1 <= io_initial;
end else begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
end
endmodule
module BufferCC_1_ (
input io_dataIn,
output io_dataOut,
input io_mainClk,
input resetCtrl_mainClkReset);
reg buffers_0;
reg buffers_1;
assign io_dataOut = buffers_1;
always @ (posedge io_mainClk) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmodule
module UartCtrlTx (
input [2:0] io_configFrame_dataLength,
input `UartStopType_defaultEncoding_type io_configFrame_stop,
input `UartParityType_defaultEncoding_type io_configFrame_parity,
input io_samplingTick,
input io_write_valid,
output reg io_write_ready,
input [7:0] io_write_payload,
output io_txd,
input io_mainClk,
input resetCtrl_systemReset);
wire _zz_1_;
wire [0:0] _zz_2_;
wire [2:0] _zz_3_;
wire [0:0] _zz_4_;
wire [2:0] _zz_5_;
reg clockDivider_counter_willIncrement;
wire clockDivider_counter_willClear;
reg [2:0] clockDivider_counter_valueNext;
reg [2:0] clockDivider_counter_value;
wire clockDivider_counter_willOverflowIfInc;
wire clockDivider_willOverflow;
reg [2:0] tickCounter_value;
reg `UartCtrlTxState_defaultEncoding_type stateMachine_state;
reg stateMachine_parity;
reg stateMachine_txd;
reg stateMachine_txd_regNext;
assign _zz_1_ = (tickCounter_value == io_configFrame_dataLength);
assign _zz_2_ = clockDivider_counter_willIncrement;
assign _zz_3_ = {2'd0, _zz_2_};
assign _zz_4_ = ((io_configFrame_stop == `UartStopType_defaultEncoding_ONE) ? (1'b0) : (1'b1));
assign _zz_5_ = {2'd0, _zz_4_};
always @ (*) begin
clockDivider_counter_willIncrement = 1'b0;
if(io_samplingTick)begin
clockDivider_counter_willIncrement = 1'b1;
end
end
assign clockDivider_counter_willClear = 1'b0;
assign clockDivider_counter_willOverflowIfInc = (clockDivider_counter_value == (3'b100));
assign clockDivider_willOverflow = (clockDivider_counter_willOverflowIfInc && clockDivider_counter_willIncrement);
always @ (*) begin
if(clockDivider_willOverflow)begin
clockDivider_counter_valueNext = (3'b000);
end else begin
clockDivider_counter_valueNext = (clockDivider_counter_value + _zz_3_);
end
if(clockDivider_counter_willClear)begin
clockDivider_counter_valueNext = (3'b000);
end
end
always @ (*) begin
stateMachine_txd = 1'b1;
io_write_ready = 1'b0;
case(stateMachine_state)
`UartCtrlTxState_defaultEncoding_IDLE : begin
end
`UartCtrlTxState_defaultEncoding_START : begin
stateMachine_txd = 1'b0;
end
`UartCtrlTxState_defaultEncoding_DATA : begin
stateMachine_txd = io_write_payload[tickCounter_value];
if(clockDivider_willOverflow)begin
if(_zz_1_)begin
io_write_ready = 1'b1;
end
end
end
`UartCtrlTxState_defaultEncoding_PARITY : begin
stateMachine_txd = stateMachine_parity;
end
default : begin
end
endcase
end
assign io_txd = stateMachine_txd_regNext;
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
clockDivider_counter_value <= (3'b000);
stateMachine_state <= `UartCtrlTxState_defaultEncoding_IDLE;
stateMachine_txd_regNext <= 1'b1;
end else begin
clockDivider_counter_value <= clockDivider_counter_valueNext;
case(stateMachine_state)
`UartCtrlTxState_defaultEncoding_IDLE : begin
if((io_write_valid && clockDivider_willOverflow))begin
stateMachine_state <= `UartCtrlTxState_defaultEncoding_START;
end
end
`UartCtrlTxState_defaultEncoding_START : begin
if(clockDivider_willOverflow)begin
stateMachine_state <= `UartCtrlTxState_defaultEncoding_DATA;
end
end
`UartCtrlTxState_defaultEncoding_DATA : begin
if(clockDivider_willOverflow)begin
if(_zz_1_)begin
if((io_configFrame_parity == `UartParityType_defaultEncoding_NONE))begin
stateMachine_state <= `UartCtrlTxState_defaultEncoding_STOP;
end else begin
stateMachine_state <= `UartCtrlTxState_defaultEncoding_PARITY;
end
end
end
end
`UartCtrlTxState_defaultEncoding_PARITY : begin
if(clockDivider_willOverflow)begin
stateMachine_state <= `UartCtrlTxState_defaultEncoding_STOP;
end
end
default : begin
if(clockDivider_willOverflow)begin
if((tickCounter_value == _zz_5_))begin
stateMachine_state <= (io_write_valid ? `UartCtrlTxState_defaultEncoding_START : `UartCtrlTxState_defaultEncoding_IDLE);
end
end
end
endcase
stateMachine_txd_regNext <= stateMachine_txd;
end
end
always @ (posedge io_mainClk) begin
if(clockDivider_willOverflow)begin
tickCounter_value <= (tickCounter_value + (3'b001));
end
if(clockDivider_willOverflow)begin
stateMachine_parity <= (stateMachine_parity ^ stateMachine_txd);
end
case(stateMachine_state)
`UartCtrlTxState_defaultEncoding_IDLE : begin
end
`UartCtrlTxState_defaultEncoding_START : begin
if(clockDivider_willOverflow)begin
stateMachine_parity <= (io_configFrame_parity == `UartParityType_defaultEncoding_ODD);
tickCounter_value <= (3'b000);
end
end
`UartCtrlTxState_defaultEncoding_DATA : begin
if(clockDivider_willOverflow)begin
if(_zz_1_)begin
tickCounter_value <= (3'b000);
end
end
end
`UartCtrlTxState_defaultEncoding_PARITY : begin
if(clockDivider_willOverflow)begin
tickCounter_value <= (3'b000);
end
end
default : begin
end
endcase
end
endmodule
module UartCtrlRx (
input [2:0] io_configFrame_dataLength,
input `UartStopType_defaultEncoding_type io_configFrame_stop,
input `UartParityType_defaultEncoding_type io_configFrame_parity,
input io_samplingTick,
output io_read_valid,
output [7:0] io_read_payload,
input io_rxd,
input io_mainClk,
input resetCtrl_systemReset);
wire _zz_1_;
wire _zz_2_;
wire _zz_3_;
wire _zz_4_;
wire _zz_5_;
wire [0:0] _zz_6_;
wire [2:0] _zz_7_;
wire sampler_syncroniser;
wire sampler_samples_0;
reg sampler_samples_1;
reg sampler_samples_2;
reg sampler_value;
reg sampler_tick;
reg [2:0] bitTimer_counter;
reg bitTimer_tick;
reg [2:0] bitCounter_value;
reg `UartCtrlRxState_defaultEncoding_type stateMachine_state;
reg stateMachine_parity;
reg [7:0] stateMachine_shifter;
reg stateMachine_validReg;
assign _zz_3_ = (bitTimer_counter == (3'b000));
assign _zz_4_ = (sampler_tick && (! sampler_value));
assign _zz_5_ = (bitCounter_value == io_configFrame_dataLength);
assign _zz_6_ = ((io_configFrame_stop == `UartStopType_defaultEncoding_ONE) ? (1'b0) : (1'b1));
assign _zz_7_ = {2'd0, _zz_6_};
BufferCC bufferCC_3_ (
.io_initial(_zz_1_),
.io_dataIn(io_rxd),
.io_dataOut(_zz_2_),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
assign _zz_1_ = 1'b0;
assign sampler_syncroniser = _zz_2_;
assign sampler_samples_0 = sampler_syncroniser;
always @ (*) begin
bitTimer_tick = 1'b0;
if(sampler_tick)begin
if(_zz_3_)begin
bitTimer_tick = 1'b1;
end
end
end
assign io_read_valid = stateMachine_validReg;
assign io_read_payload = stateMachine_shifter;
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
sampler_samples_1 <= 1'b1;
sampler_samples_2 <= 1'b1;
sampler_value <= 1'b1;
sampler_tick <= 1'b0;
stateMachine_state <= `UartCtrlRxState_defaultEncoding_IDLE;
stateMachine_validReg <= 1'b0;
end else begin
if(io_samplingTick)begin
sampler_samples_1 <= sampler_samples_0;
end
if(io_samplingTick)begin
sampler_samples_2 <= sampler_samples_1;
end
sampler_value <= (((1'b0 || ((1'b1 && sampler_samples_0) && sampler_samples_1)) || ((1'b1 && sampler_samples_0) && sampler_samples_2)) || ((1'b1 && sampler_samples_1) && sampler_samples_2));
sampler_tick <= io_samplingTick;
stateMachine_validReg <= 1'b0;
case(stateMachine_state)
`UartCtrlRxState_defaultEncoding_IDLE : begin
if(_zz_4_)begin
stateMachine_state <= `UartCtrlRxState_defaultEncoding_START;
end
end
`UartCtrlRxState_defaultEncoding_START : begin
if(bitTimer_tick)begin
stateMachine_state <= `UartCtrlRxState_defaultEncoding_DATA;
if((sampler_value == 1'b1))begin
stateMachine_state <= `UartCtrlRxState_defaultEncoding_IDLE;
end
end
end
`UartCtrlRxState_defaultEncoding_DATA : begin
if(bitTimer_tick)begin
if(_zz_5_)begin
if((io_configFrame_parity == `UartParityType_defaultEncoding_NONE))begin
stateMachine_state <= `UartCtrlRxState_defaultEncoding_STOP;
stateMachine_validReg <= 1'b1;
end else begin
stateMachine_state <= `UartCtrlRxState_defaultEncoding_PARITY;
end
end
end
end
`UartCtrlRxState_defaultEncoding_PARITY : begin
if(bitTimer_tick)begin
if((stateMachine_parity == sampler_value))begin
stateMachine_state <= `UartCtrlRxState_defaultEncoding_STOP;
stateMachine_validReg <= 1'b1;
end else begin
stateMachine_state <= `UartCtrlRxState_defaultEncoding_IDLE;
end
end
end
default : begin
if(bitTimer_tick)begin
if((! sampler_value))begin
stateMachine_state <= `UartCtrlRxState_defaultEncoding_IDLE;
end else begin
if((bitCounter_value == _zz_7_))begin
stateMachine_state <= `UartCtrlRxState_defaultEncoding_IDLE;
end
end
end
end
endcase
end
end
always @ (posedge io_mainClk) begin
if(sampler_tick)begin
bitTimer_counter <= (bitTimer_counter - (3'b001));
if(_zz_3_)begin
bitTimer_counter <= (3'b100);
end
end
if(bitTimer_tick)begin
bitCounter_value <= (bitCounter_value + (3'b001));
end
if(bitTimer_tick)begin
stateMachine_parity <= (stateMachine_parity ^ sampler_value);
end
case(stateMachine_state)
`UartCtrlRxState_defaultEncoding_IDLE : begin
if(_zz_4_)begin
bitTimer_counter <= (3'b001);
end
end
`UartCtrlRxState_defaultEncoding_START : begin
if(bitTimer_tick)begin
bitCounter_value <= (3'b000);
stateMachine_parity <= (io_configFrame_parity == `UartParityType_defaultEncoding_ODD);
end
end
`UartCtrlRxState_defaultEncoding_DATA : begin
if(bitTimer_tick)begin
stateMachine_shifter[bitCounter_value] <= sampler_value;
if(_zz_5_)begin
bitCounter_value <= (3'b000);
end
end
end
`UartCtrlRxState_defaultEncoding_PARITY : begin
if(bitTimer_tick)begin
bitCounter_value <= (3'b000);
end
end
default : begin
end
endcase
end
endmodule
module StreamFifoLowLatency (
input io_push_valid,
output io_push_ready,
input io_push_payload_error,
input [31:0] io_push_payload_inst,
output reg io_pop_valid,
input io_pop_ready,
output reg io_pop_payload_error,
output reg [31:0] io_pop_payload_inst,
input io_flush,
output [0:0] io_occupancy,
input io_mainClk,
input resetCtrl_systemReset);
wire [0:0] _zz_5_;
reg _zz_1_;
reg pushPtr_willIncrement;
reg pushPtr_willClear;
wire pushPtr_willOverflowIfInc;
wire pushPtr_willOverflow;
reg popPtr_willIncrement;
reg popPtr_willClear;
wire popPtr_willOverflowIfInc;
wire popPtr_willOverflow;
wire ptrMatch;
reg risingOccupancy;
wire empty;
wire full;
wire pushing;
wire popping;
wire [32:0] _zz_2_;
wire [32:0] _zz_3_;
reg [32:0] _zz_4_;
assign _zz_5_ = _zz_2_[0 : 0];
always @ (*) begin
_zz_1_ = 1'b0;
pushPtr_willIncrement = 1'b0;
if(pushing)begin
_zz_1_ = 1'b1;
pushPtr_willIncrement = 1'b1;
end
end
always @ (*) begin
pushPtr_willClear = 1'b0;
popPtr_willClear = 1'b0;
if(io_flush)begin
pushPtr_willClear = 1'b1;
popPtr_willClear = 1'b1;
end
end
assign pushPtr_willOverflowIfInc = 1'b1;
assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement);
always @ (*) begin
popPtr_willIncrement = 1'b0;
if(popping)begin
popPtr_willIncrement = 1'b1;
end
end
assign popPtr_willOverflowIfInc = 1'b1;
assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement);
assign ptrMatch = 1'b1;
assign empty = (ptrMatch && (! risingOccupancy));
assign full = (ptrMatch && risingOccupancy);
assign pushing = (io_push_valid && io_push_ready);
assign popping = (io_pop_valid && io_pop_ready);
assign io_push_ready = (! full);
always @ (*) begin
if((! empty))begin
io_pop_valid = 1'b1;
io_pop_payload_error = _zz_5_[0];
io_pop_payload_inst = _zz_2_[32 : 1];
end else begin
io_pop_valid = io_push_valid;
io_pop_payload_error = io_push_payload_error;
io_pop_payload_inst = io_push_payload_inst;
end
end
assign _zz_2_ = _zz_3_;
assign io_occupancy = (risingOccupancy && ptrMatch);
assign _zz_3_ = _zz_4_;
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
risingOccupancy <= 1'b0;
end else begin
if((pushing != popping))begin
risingOccupancy <= pushing;
end
if(io_flush)begin
risingOccupancy <= 1'b0;
end
end
end
always @ (posedge io_mainClk) begin
if(_zz_1_)begin
_zz_4_ <= {io_push_payload_inst,io_push_payload_error};
end
end
endmodule
module FlowCCByToggle (
input io_input_valid,
input io_input_payload_last,
input [0:0] io_input_payload_fragment,
output io_output_valid,
output io_output_payload_last,
output [0:0] io_output_payload_fragment,
input io_jtag_tck,
input io_mainClk,
input resetCtrl_mainClkReset);
wire _zz_1_;
wire outHitSignal;
reg inputArea_target = 0;
reg inputArea_data_last;
reg [0:0] inputArea_data_fragment;
wire outputArea_target;
reg outputArea_hit;
wire outputArea_flow_valid;
wire outputArea_flow_payload_last;
wire [0:0] outputArea_flow_payload_fragment;
reg outputArea_flow_regNext_valid;
reg outputArea_flow_regNext_payload_last;
reg [0:0] outputArea_flow_regNext_payload_fragment;
BufferCC_1_ bufferCC_3_ (
.io_dataIn(inputArea_target),
.io_dataOut(_zz_1_),
.io_mainClk(io_mainClk),
.resetCtrl_mainClkReset(resetCtrl_mainClkReset)
);
assign outputArea_target = _zz_1_;
assign outputArea_flow_valid = (outputArea_target != outputArea_hit);
assign outputArea_flow_payload_last = inputArea_data_last;
assign outputArea_flow_payload_fragment = inputArea_data_fragment;
assign io_output_valid = outputArea_flow_regNext_valid;
assign io_output_payload_last = outputArea_flow_regNext_payload_last;
assign io_output_payload_fragment = outputArea_flow_regNext_payload_fragment;
always @ (posedge io_jtag_tck) begin
if(io_input_valid)begin
inputArea_target <= (! inputArea_target);
inputArea_data_last <= io_input_payload_last;
inputArea_data_fragment <= io_input_payload_fragment;
end
end
always @ (posedge io_mainClk) begin
outputArea_hit <= outputArea_target;
outputArea_flow_regNext_payload_last <= outputArea_flow_payload_last;
outputArea_flow_regNext_payload_fragment <= outputArea_flow_payload_fragment;
end
always @ (posedge io_mainClk or posedge resetCtrl_mainClkReset) begin
if (resetCtrl_mainClkReset) begin
outputArea_flow_regNext_valid <= 1'b0;
end else begin
outputArea_flow_regNext_valid <= outputArea_flow_valid;
end
end
endmodule
module UartCtrl (
input [2:0] io_config_frame_dataLength,
input `UartStopType_defaultEncoding_type io_config_frame_stop,
input `UartParityType_defaultEncoding_type io_config_frame_parity,
input [19:0] io_config_clockDivider,
input io_write_valid,
output io_write_ready,
input [7:0] io_write_payload,
output io_read_valid,
output [7:0] io_read_payload,
output io_uart_txd,
input io_uart_rxd,
input io_mainClk,
input resetCtrl_systemReset);
wire _zz_1_;
wire _zz_2_;
wire _zz_3_;
wire [7:0] _zz_4_;
reg [19:0] clockDivider_counter;
wire clockDivider_tick;
UartCtrlTx tx (
.io_configFrame_dataLength(io_config_frame_dataLength),
.io_configFrame_stop(io_config_frame_stop),
.io_configFrame_parity(io_config_frame_parity),
.io_samplingTick(clockDivider_tick),
.io_write_valid(io_write_valid),
.io_write_ready(_zz_1_),
.io_write_payload(io_write_payload),
.io_txd(_zz_2_),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
UartCtrlRx rx (
.io_configFrame_dataLength(io_config_frame_dataLength),
.io_configFrame_stop(io_config_frame_stop),
.io_configFrame_parity(io_config_frame_parity),
.io_samplingTick(clockDivider_tick),
.io_read_valid(_zz_3_),
.io_read_payload(_zz_4_),
.io_rxd(io_uart_rxd),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
assign clockDivider_tick = (clockDivider_counter == (20'b00000000000000000000));
assign io_write_ready = _zz_1_;
assign io_read_valid = _zz_3_;
assign io_read_payload = _zz_4_;
assign io_uart_txd = _zz_2_;
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
clockDivider_counter <= (20'b00000000000000000000);
end else begin
clockDivider_counter <= (clockDivider_counter - (20'b00000000000000000001));
if(clockDivider_tick)begin
clockDivider_counter <= io_config_clockDivider;
end
end
end
endmodule
module StreamFifo (
input io_push_valid,
output io_push_ready,
input [7:0] io_push_payload,
output io_pop_valid,
input io_pop_ready,
output [7:0] io_pop_payload,
input io_flush,
output [4:0] io_occupancy,
output [4:0] io_availability,
input io_mainClk,
input resetCtrl_systemReset);
reg [7:0] _zz_3_;
wire [0:0] _zz_4_;
wire [3:0] _zz_5_;
wire [0:0] _zz_6_;
wire [3:0] _zz_7_;
wire [3:0] _zz_8_;
wire _zz_9_;
reg _zz_1_;
reg pushPtr_willIncrement;
reg pushPtr_willClear;
reg [3:0] pushPtr_valueNext;
reg [3:0] pushPtr_value;
wire pushPtr_willOverflowIfInc;
wire pushPtr_willOverflow;
reg popPtr_willIncrement;
reg popPtr_willClear;
reg [3:0] popPtr_valueNext;
reg [3:0] popPtr_value;
wire popPtr_willOverflowIfInc;
wire popPtr_willOverflow;
wire ptrMatch;
reg risingOccupancy;
wire pushing;
wire popping;
wire empty;
wire full;
reg _zz_2_;
wire [3:0] ptrDif;
reg [7:0] ram [0:15];
assign _zz_4_ = pushPtr_willIncrement;
assign _zz_5_ = {3'd0, _zz_4_};
assign _zz_6_ = popPtr_willIncrement;
assign _zz_7_ = {3'd0, _zz_6_};
assign _zz_8_ = (popPtr_value - pushPtr_value);
assign _zz_9_ = 1'b1;
always @ (posedge io_mainClk) begin
if(_zz_1_) begin
ram[pushPtr_value] <= io_push_payload;
end
end
always @ (posedge io_mainClk) begin
if(_zz_9_) begin
_zz_3_ <= ram[popPtr_valueNext];
end
end
always @ (*) begin
_zz_1_ = 1'b0;
pushPtr_willIncrement = 1'b0;
if(pushing)begin
_zz_1_ = 1'b1;
pushPtr_willIncrement = 1'b1;
end
end
always @ (*) begin
pushPtr_willClear = 1'b0;
popPtr_willClear = 1'b0;
if(io_flush)begin
pushPtr_willClear = 1'b1;
popPtr_willClear = 1'b1;
end
end
assign pushPtr_willOverflowIfInc = (pushPtr_value == (4'b1111));
assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement);
always @ (*) begin
pushPtr_valueNext = (pushPtr_value + _zz_5_);
if(pushPtr_willClear)begin
pushPtr_valueNext = (4'b0000);
end
end
always @ (*) begin
popPtr_willIncrement = 1'b0;
if(popping)begin
popPtr_willIncrement = 1'b1;
end
end
assign popPtr_willOverflowIfInc = (popPtr_value == (4'b1111));
assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement);
always @ (*) begin
popPtr_valueNext = (popPtr_value + _zz_7_);
if(popPtr_willClear)begin
popPtr_valueNext = (4'b0000);
end
end
assign ptrMatch = (pushPtr_value == popPtr_value);
assign pushing = (io_push_valid && io_push_ready);
assign popping = (io_pop_valid && io_pop_ready);
assign empty = (ptrMatch && (! risingOccupancy));
assign full = (ptrMatch && risingOccupancy);
assign io_push_ready = (! full);
assign io_pop_valid = ((! empty) && (! (_zz_2_ && (! full))));
assign io_pop_payload = _zz_3_;
assign ptrDif = (pushPtr_value - popPtr_value);
assign io_occupancy = {(risingOccupancy && ptrMatch),ptrDif};
assign io_availability = {((! risingOccupancy) && ptrMatch),_zz_8_};
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
pushPtr_value <= (4'b0000);
popPtr_value <= (4'b0000);
risingOccupancy <= 1'b0;
_zz_2_ <= 1'b0;
end else begin
pushPtr_value <= pushPtr_valueNext;
popPtr_value <= popPtr_valueNext;
_zz_2_ <= (popPtr_valueNext == pushPtr_value);
if((pushing != popping))begin
risingOccupancy <= pushing;
end
if(io_flush)begin
risingOccupancy <= 1'b0;
end
end
end
endmodule
//StreamFifo_1_ remplaced by StreamFifo
module Prescaler (
input io_clear,
input [15:0] io_limit,
output io_overflow,
input io_mainClk,
input resetCtrl_systemReset);
reg [15:0] counter;
assign io_overflow = (counter == io_limit);
always @ (posedge io_mainClk) begin
counter <= (counter + (16'b0000000000000001));
if((io_clear || io_overflow))begin
counter <= (16'b0000000000000000);
end
end
endmodule
module Timer (
input io_tick,
input io_clear,
input [15:0] io_limit,
output io_full,
output [15:0] io_value,
input io_mainClk,
input resetCtrl_systemReset);
wire [0:0] _zz_1_;
wire [15:0] _zz_2_;
reg [15:0] counter;
wire limitHit;
reg inhibitFull;
assign _zz_1_ = (! limitHit);
assign _zz_2_ = {15'd0, _zz_1_};
assign limitHit = (counter == io_limit);
assign io_full = ((limitHit && io_tick) && (! inhibitFull));
assign io_value = counter;
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
inhibitFull <= 1'b0;
end else begin
if(io_tick)begin
inhibitFull <= limitHit;
end
if(io_clear)begin
inhibitFull <= 1'b0;
end
end
end
always @ (posedge io_mainClk) begin
if(io_tick)begin
counter <= (counter + _zz_2_);
end
if(io_clear)begin
counter <= (16'b0000000000000000);
end
end
endmodule
//Timer_1_ remplaced by Timer
module InterruptCtrl (
input [1:0] io_inputs,
input [1:0] io_clears,
input [1:0] io_masks,
output [1:0] io_pendings,
input io_mainClk,
input resetCtrl_systemReset);
reg [1:0] pendings;
assign io_pendings = (pendings & io_masks);
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
pendings <= (2'b00);
end else begin
pendings <= ((pendings & (~ io_clears)) | io_inputs);
end
end
endmodule
module BufferCC_2_ (
input io_dataIn,
output io_dataOut,
input io_mainClk);
reg buffers_0;
reg buffers_1;
assign io_dataOut = buffers_1;
always @ (posedge io_mainClk) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmodule
module MuraxMasterArbiter (
input io_iBus_cmd_valid,
output reg io_iBus_cmd_ready,
input [31:0] io_iBus_cmd_payload_pc,
output io_iBus_rsp_valid,
output io_iBus_rsp_payload_error,
output [31:0] io_iBus_rsp_payload_inst,
input io_dBus_cmd_valid,
output reg io_dBus_cmd_ready,
input io_dBus_cmd_payload_wr,
input [31:0] io_dBus_cmd_payload_address,
input [31:0] io_dBus_cmd_payload_data,
input [1:0] io_dBus_cmd_payload_size,
output io_dBus_rsp_ready,
output io_dBus_rsp_error,
output [31:0] io_dBus_rsp_data,
output reg io_masterBus_cmd_valid,
input io_masterBus_cmd_ready,
output io_masterBus_cmd_payload_wr,
output [31:0] io_masterBus_cmd_payload_address,
output [31:0] io_masterBus_cmd_payload_data,
output [3:0] io_masterBus_cmd_payload_mask,
input io_masterBus_rsp_valid,
input [31:0] io_masterBus_rsp_payload_data,
input io_mainClk,
input resetCtrl_systemReset);
reg [3:0] _zz_1_;
reg rspPending;
reg rspTarget;
always @ (*) begin
io_masterBus_cmd_valid = (io_iBus_cmd_valid || io_dBus_cmd_valid);
io_iBus_cmd_ready = (io_masterBus_cmd_ready && (! io_dBus_cmd_valid));
io_dBus_cmd_ready = io_masterBus_cmd_ready;
if((rspPending && (! io_masterBus_rsp_valid)))begin
io_iBus_cmd_ready = 1'b0;
io_dBus_cmd_ready = 1'b0;
io_masterBus_cmd_valid = 1'b0;
end
end
assign io_masterBus_cmd_payload_wr = (io_dBus_cmd_valid && io_dBus_cmd_payload_wr);
assign io_masterBus_cmd_payload_address = (io_dBus_cmd_valid ? io_dBus_cmd_payload_address : io_iBus_cmd_payload_pc);
assign io_masterBus_cmd_payload_data = io_dBus_cmd_payload_data;
always @ (*) begin
case(io_dBus_cmd_payload_size)
2'b00 : begin
_zz_1_ = (4'b0001);
end
2'b01 : begin
_zz_1_ = (4'b0011);
end
default : begin
_zz_1_ = (4'b1111);
end
endcase
end
assign io_masterBus_cmd_payload_mask = (_zz_1_ <<< io_dBus_cmd_payload_address[1 : 0]);
assign io_iBus_rsp_valid = (io_masterBus_rsp_valid && (! rspTarget));
assign io_iBus_rsp_payload_inst = io_masterBus_rsp_payload_data;
assign io_iBus_rsp_payload_error = 1'b0;
assign io_dBus_rsp_ready = (io_masterBus_rsp_valid && rspTarget);
assign io_dBus_rsp_data = io_masterBus_rsp_payload_data;
assign io_dBus_rsp_error = 1'b0;
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
rspPending <= 1'b0;
rspTarget <= 1'b0;
end else begin
if(io_masterBus_rsp_valid)begin
rspPending <= 1'b0;
end
if(((io_masterBus_cmd_valid && io_masterBus_cmd_ready) && (! io_masterBus_cmd_payload_wr)))begin
rspTarget <= io_dBus_cmd_valid;
rspPending <= 1'b1;
end
end
end
endmodule
module VexRiscv (
output iBus_cmd_valid,
input iBus_cmd_ready,
output [31:0] iBus_cmd_payload_pc,
input iBus_rsp_valid,
input iBus_rsp_payload_error,
input [31:0] iBus_rsp_payload_inst,
input timerInterrupt,
input externalInterrupt,
input debug_bus_cmd_valid,
output reg debug_bus_cmd_ready,
input debug_bus_cmd_payload_wr,
input [7:0] debug_bus_cmd_payload_address,
input [31:0] debug_bus_cmd_payload_data,
output reg [31:0] debug_bus_rsp_data,
output debug_resetOut,
output dBus_cmd_valid,
input dBus_cmd_ready,
output dBus_cmd_payload_wr,
output [31:0] dBus_cmd_payload_address,
output [31:0] dBus_cmd_payload_data,
output [1:0] dBus_cmd_payload_size,
input dBus_rsp_ready,
input dBus_rsp_error,
input [31:0] dBus_rsp_data,
input io_mainClk,
input resetCtrl_systemReset,
input resetCtrl_mainClkReset);
wire _zz_205_;
wire _zz_206_;
reg [31:0] _zz_207_;
reg [31:0] _zz_208_;
reg [31:0] _zz_209_;
reg [3:0] _zz_210_;
reg [31:0] _zz_211_;
wire _zz_212_;
wire _zz_213_;
wire _zz_214_;
wire [31:0] _zz_215_;
wire [0:0] _zz_216_;
wire _zz_217_;
wire _zz_218_;
wire _zz_219_;
wire _zz_220_;
wire _zz_221_;
wire _zz_222_;
wire _zz_223_;
wire _zz_224_;
wire _zz_225_;
wire [0:0] _zz_226_;
wire _zz_227_;
wire [4:0] _zz_228_;
wire [1:0] _zz_229_;
wire [1:0] _zz_230_;
wire [1:0] _zz_231_;
wire _zz_232_;
wire [1:0] _zz_233_;
wire [1:0] _zz_234_;
wire [1:0] _zz_235_;
wire [1:0] _zz_236_;
wire [2:0] _zz_237_;
wire [31:0] _zz_238_;
wire [31:0] _zz_239_;
wire [11:0] _zz_240_;
wire [11:0] _zz_241_;
wire [2:0] _zz_242_;
wire [31:0] _zz_243_;
wire [2:0] _zz_244_;
wire [0:0] _zz_245_;
wire [2:0] _zz_246_;
wire [0:0] _zz_247_;
wire [2:0] _zz_248_;
wire [0:0] _zz_249_;
wire [2:0] _zz_250_;
wire [1:0] _zz_251_;
wire [1:0] _zz_252_;
wire [2:0] _zz_253_;
wire [3:0] _zz_254_;
wire [4:0] _zz_255_;
wire [31:0] _zz_256_;
wire [0:0] _zz_257_;
wire [0:0] _zz_258_;
wire [0:0] _zz_259_;
wire [0:0] _zz_260_;
wire [0:0] _zz_261_;
wire [0:0] _zz_262_;
wire [0:0] _zz_263_;
wire [0:0] _zz_264_;
wire [0:0] _zz_265_;
wire [0:0] _zz_266_;
wire [0:0] _zz_267_;
wire [0:0] _zz_268_;
wire [0:0] _zz_269_;
wire [0:0] _zz_270_;
wire [0:0] _zz_271_;
wire [2:0] _zz_272_;
wire [11:0] _zz_273_;
wire [11:0] _zz_274_;
wire [31:0] _zz_275_;
wire [31:0] _zz_276_;
wire [31:0] _zz_277_;
wire [31:0] _zz_278_;
wire [1:0] _zz_279_;
wire [31:0] _zz_280_;
wire [1:0] _zz_281_;
wire [1:0] _zz_282_;
wire [31:0] _zz_283_;
wire [32:0] _zz_284_;
wire [51:0] _zz_285_;
wire [51:0] _zz_286_;
wire [51:0] _zz_287_;
wire [32:0] _zz_288_;
wire [51:0] _zz_289_;
wire [49:0] _zz_290_;
wire [51:0] _zz_291_;
wire [49:0] _zz_292_;
wire [51:0] _zz_293_;
wire [65:0] _zz_294_;
wire [65:0] _zz_295_;
wire [31:0] _zz_296_;
wire [31:0] _zz_297_;
wire [0:0] _zz_298_;
wire [5:0] _zz_299_;
wire [32:0] _zz_300_;
wire [32:0] _zz_301_;
wire [31:0] _zz_302_;
wire [31:0] _zz_303_;
wire [32:0] _zz_304_;
wire [32:0] _zz_305_;
wire [32:0] _zz_306_;
wire [0:0] _zz_307_;
wire [32:0] _zz_308_;
wire [0:0] _zz_309_;
wire [32:0] _zz_310_;
wire [0:0] _zz_311_;
wire [31:0] _zz_312_;
wire [19:0] _zz_313_;
wire [11:0] _zz_314_;
wire [11:0] _zz_315_;
wire [0:0] _zz_316_;
wire [0:0] _zz_317_;
wire [0:0] _zz_318_;
wire [0:0] _zz_319_;
wire [0:0] _zz_320_;
wire [0:0] _zz_321_;
wire [0:0] _zz_322_;
wire _zz_323_;
wire _zz_324_;
wire [0:0] _zz_325_;
wire _zz_326_;
wire _zz_327_;
wire [6:0] _zz_328_;
wire [4:0] _zz_329_;
wire _zz_330_;
wire [4:0] _zz_331_;
wire [31:0] _zz_332_;
wire [31:0] _zz_333_;
wire [31:0] _zz_334_;
wire _zz_335_;
wire [0:0] _zz_336_;
wire [0:0] _zz_337_;
wire _zz_338_;
wire [0:0] _zz_339_;
wire [21:0] _zz_340_;
wire [31:0] _zz_341_;
wire [31:0] _zz_342_;
wire [31:0] _zz_343_;
wire [31:0] _zz_344_;
wire _zz_345_;
wire [0:0] _zz_346_;
wire [0:0] _zz_347_;
wire [0:0] _zz_348_;
wire [0:0] _zz_349_;
wire _zz_350_;
wire [0:0] _zz_351_;
wire [17:0] _zz_352_;
wire [31:0] _zz_353_;
wire [31:0] _zz_354_;
wire [31:0] _zz_355_;
wire _zz_356_;
wire [0:0] _zz_357_;
wire [1:0] _zz_358_;
wire _zz_359_;
wire [1:0] _zz_360_;
wire [1:0] _zz_361_;
wire _zz_362_;
wire [0:0] _zz_363_;
wire [14:0] _zz_364_;
wire [31:0] _zz_365_;
wire [31:0] _zz_366_;
wire [31:0] _zz_367_;
wire [31:0] _zz_368_;
wire [31:0] _zz_369_;
wire [31:0] _zz_370_;
wire [31:0] _zz_371_;
wire _zz_372_;
wire [0:0] _zz_373_;
wire [0:0] _zz_374_;
wire [2:0] _zz_375_;
wire [2:0] _zz_376_;
wire _zz_377_;
wire [0:0] _zz_378_;
wire [11:0] _zz_379_;
wire [31:0] _zz_380_;
wire [31:0] _zz_381_;
wire _zz_382_;
wire [0:0] _zz_383_;
wire [0:0] _zz_384_;
wire [0:0] _zz_385_;
wire [0:0] _zz_386_;
wire [0:0] _zz_387_;
wire [0:0] _zz_388_;
wire _zz_389_;
wire [0:0] _zz_390_;
wire [8:0] _zz_391_;
wire [31:0] _zz_392_;
wire [31:0] _zz_393_;
wire _zz_394_;
wire _zz_395_;
wire [0:0] _zz_396_;
wire [0:0] _zz_397_;
wire _zz_398_;
wire [0:0] _zz_399_;
wire [5:0] _zz_400_;
wire [0:0] _zz_401_;
wire [1:0] _zz_402_;
wire [31:0] _zz_403_;
wire [31:0] _zz_404_;
wire _zz_405_;
wire [3:0] _zz_406_;
wire [3:0] _zz_407_;
wire _zz_408_;
wire [0:0] _zz_409_;
wire [1:0] _zz_410_;
wire [31:0] _zz_411_;
wire [31:0] _zz_412_;
wire [31:0] _zz_413_;
wire [31:0] _zz_414_;
wire [31:0] _zz_415_;
wire [0:0] _zz_416_;
wire [0:0] _zz_417_;
wire _zz_418_;
wire [0:0] _zz_419_;
wire [1:0] _zz_420_;
wire [4:0] _zz_421_;
wire [4:0] _zz_422_;
wire [2:0] _zz_423_;
wire [2:0] _zz_424_;
wire [31:0] _zz_425_;
wire [31:0] _zz_426_;
wire _zz_427_;
wire [0:0] _zz_428_;
wire [0:0] _zz_429_;
wire [31:0] _zz_430_;
wire [31:0] _zz_431_;
wire [31:0] _zz_432_;
wire [31:0] _zz_433_;
wire [31:0] _zz_434_;
wire [31:0] memory_MEMORY_READ_DATA;
wire [31:0] decode_RS1;
wire [33:0] memory_MUL_HH;
wire [33:0] execute_MUL_HH;
wire decode_BYPASSABLE_EXECUTE_STAGE;
wire [31:0] execute_BRANCH_CALC;
wire [31:0] decode_SRC1;
wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL;
wire `EnvCtrlEnum_defaultEncoding_type _zz_1_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_2_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_3_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_4_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_5_;
wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL;
wire `EnvCtrlEnum_defaultEncoding_type _zz_6_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_7_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_8_;
wire decode_CSR_WRITE_OPCODE;
wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL;
wire `AluCtrlEnum_defaultEncoding_type _zz_9_;
wire `AluCtrlEnum_defaultEncoding_type _zz_10_;
wire `AluCtrlEnum_defaultEncoding_type _zz_11_;
wire decode_CSR_READ_OPCODE;
wire decode_IS_RS2_SIGNED;
wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_12_;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_13_;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_14_;
wire [1:0] memory_MEMORY_ADDRESS_LOW;
wire [1:0] execute_MEMORY_ADDRESS_LOW;
wire [31:0] decode_RS2;
wire [31:0] writeBack_FORMAL_PC_NEXT;
wire [31:0] memory_FORMAL_PC_NEXT;
wire [31:0] execute_FORMAL_PC_NEXT;
wire [31:0] decode_FORMAL_PC_NEXT;
wire decode_IS_RS1_SIGNED;
wire decode_IS_DIV;
wire decode_IS_EBREAK;
wire [33:0] execute_MUL_LH;
wire [31:0] execute_MUL_LL;
wire execute_BYPASSABLE_MEMORY_STAGE;
wire decode_BYPASSABLE_MEMORY_STAGE;
wire memory_IS_MUL;
wire execute_IS_MUL;
wire decode_IS_MUL;
wire execute_BRANCH_DO;
wire [31:0] memory_PC;
wire [31:0] writeBack_REGFILE_WRITE_DATA;
wire [31:0] execute_REGFILE_WRITE_DATA;
wire [51:0] memory_MUL_LOW;
wire decode_MEMORY_ENABLE;
wire decode_SRC_LESS_UNSIGNED;
wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_15_;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_16_;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_17_;
wire decode_SRC_USE_SUB_LESS;
wire [31:0] decode_SRC2;
wire [33:0] execute_MUL_HL;
wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL;
wire `BranchCtrlEnum_defaultEncoding_type _zz_18_;
wire `BranchCtrlEnum_defaultEncoding_type _zz_19_;
wire `BranchCtrlEnum_defaultEncoding_type _zz_20_;
wire execute_IS_EBREAK;
wire [31:0] memory_BRANCH_CALC;
wire memory_BRANCH_DO;
wire [31:0] _zz_21_;
wire [31:0] execute_PC;
wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL;
wire `BranchCtrlEnum_defaultEncoding_type _zz_22_;
wire _zz_23_;
wire execute_IS_RS1_SIGNED;
wire [31:0] execute_RS1;
wire execute_IS_DIV;
wire execute_IS_RS2_SIGNED;
reg [31:0] _zz_24_;
wire memory_IS_DIV;
wire writeBack_IS_MUL;
wire [33:0] writeBack_MUL_HH;
wire [51:0] writeBack_MUL_LOW;
wire [33:0] memory_MUL_HL;
wire [33:0] memory_MUL_LH;
wire [31:0] memory_MUL_LL;
wire [51:0] _zz_25_;
wire [33:0] _zz_26_;
wire [33:0] _zz_27_;
wire [33:0] _zz_28_;
wire [31:0] _zz_29_;
wire decode_RS2_USE;
wire decode_RS1_USE;
wire execute_REGFILE_WRITE_VALID;
wire execute_BYPASSABLE_EXECUTE_STAGE;
wire memory_REGFILE_WRITE_VALID;
wire memory_BYPASSABLE_MEMORY_STAGE;
wire writeBack_REGFILE_WRITE_VALID;
wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_30_;
wire _zz_31_;
wire [31:0] _zz_32_;
wire [31:0] _zz_33_;
wire execute_SRC_LESS_UNSIGNED;
wire execute_SRC_USE_SUB_LESS;
wire [31:0] _zz_34_;
wire [31:0] _zz_35_;
wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL;
wire `Src2CtrlEnum_defaultEncoding_type _zz_36_;
wire [31:0] _zz_37_;
wire [31:0] _zz_38_;
wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL;
wire `Src1CtrlEnum_defaultEncoding_type _zz_39_;
wire [31:0] _zz_40_;
wire [31:0] execute_SRC_ADD_SUB;
wire execute_SRC_LESS;
wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL;
wire `AluCtrlEnum_defaultEncoding_type _zz_41_;
wire [31:0] _zz_42_;
wire [31:0] execute_SRC2;
wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_43_;
wire [31:0] _zz_44_;
wire _zz_45_;
reg _zz_46_;
wire [31:0] _zz_47_;
wire [31:0] _zz_48_;
wire [31:0] decode_INSTRUCTION_ANTICIPATED;
reg decode_REGFILE_WRITE_VALID;
wire `BranchCtrlEnum_defaultEncoding_type _zz_49_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_50_;
wire _zz_51_;
wire `AluCtrlEnum_defaultEncoding_type _zz_52_;
wire _zz_53_;
wire _zz_54_;
wire _zz_55_;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_56_;
wire _zz_57_;
wire `Src2CtrlEnum_defaultEncoding_type _zz_58_;
wire _zz_59_;
wire _zz_60_;
wire _zz_61_;
wire `Src1CtrlEnum_defaultEncoding_type _zz_62_;
wire _zz_63_;
wire _zz_64_;
wire _zz_65_;
wire _zz_66_;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_67_;
wire _zz_68_;
wire _zz_69_;
reg [31:0] _zz_70_;
wire execute_CSR_READ_OPCODE;
wire execute_CSR_WRITE_OPCODE;
wire [31:0] memory_REGFILE_WRITE_DATA;
wire [31:0] execute_SRC1;
wire execute_IS_CSR;
wire decode_IS_CSR;
wire _zz_71_;
wire _zz_72_;
wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL;
wire `EnvCtrlEnum_defaultEncoding_type _zz_73_;
wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL;
wire `EnvCtrlEnum_defaultEncoding_type _zz_74_;
reg [31:0] _zz_75_;
wire writeBack_MEMORY_ENABLE;
wire [1:0] writeBack_MEMORY_ADDRESS_LOW;
wire [31:0] writeBack_MEMORY_READ_DATA;
wire [31:0] memory_INSTRUCTION;
wire memory_MEMORY_ENABLE;
wire [31:0] _zz_76_;
wire [1:0] _zz_77_;
wire [31:0] execute_RS2;
wire [31:0] execute_SRC_ADD;
wire [31:0] execute_INSTRUCTION;
wire execute_ALIGNEMENT_FAULT;
wire execute_MEMORY_ENABLE;
reg [31:0] _zz_78_;
wire [31:0] _zz_79_;
wire _zz_80_;
wire [31:0] _zz_81_;
wire [31:0] _zz_82_;
wire [31:0] _zz_83_;
wire decode_IS_RVC;
wire [31:0] writeBack_PC /* verilator public */ ;
wire [31:0] writeBack_INSTRUCTION /* verilator public */ ;
wire [31:0] decode_PC /* verilator public */ ;
wire [31:0] decode_INSTRUCTION /* verilator public */ ;
reg decode_arbitration_haltItself /* verilator public */ ;
reg decode_arbitration_haltByOther;
reg decode_arbitration_removeIt;
reg decode_arbitration_flushAll /* verilator public */ ;
wire decode_arbitration_redoIt;
reg decode_arbitration_isValid /* verilator public */ ;
wire decode_arbitration_isStuck;
wire decode_arbitration_isStuckByOthers;
wire decode_arbitration_isFlushed;
wire decode_arbitration_isMoving;
wire decode_arbitration_isFiring;
reg execute_arbitration_haltItself;
reg execute_arbitration_haltByOther;
reg execute_arbitration_removeIt;
reg execute_arbitration_flushAll;
wire execute_arbitration_redoIt;
reg execute_arbitration_isValid;
wire execute_arbitration_isStuck;
wire execute_arbitration_isStuckByOthers;
wire execute_arbitration_isFlushed;
wire execute_arbitration_isMoving;
wire execute_arbitration_isFiring;
reg memory_arbitration_haltItself;
reg memory_arbitration_haltByOther;
reg memory_arbitration_removeIt;
reg memory_arbitration_flushAll;
wire memory_arbitration_redoIt;
reg memory_arbitration_isValid;
wire memory_arbitration_isStuck;
wire memory_arbitration_isStuckByOthers;
wire memory_arbitration_isFlushed;
wire memory_arbitration_isMoving;
wire memory_arbitration_isFiring;
wire writeBack_arbitration_haltItself;
wire writeBack_arbitration_haltByOther;
reg writeBack_arbitration_removeIt;
wire writeBack_arbitration_flushAll;
wire writeBack_arbitration_redoIt;
reg writeBack_arbitration_isValid /* verilator public */ ;
wire writeBack_arbitration_isStuck;
wire writeBack_arbitration_isStuckByOthers;
wire writeBack_arbitration_isFlushed;
wire writeBack_arbitration_isMoving;
wire writeBack_arbitration_isFiring /* verilator public */ ;
reg _zz_84_;
reg _zz_85_;
reg _zz_86_;
reg _zz_87_;
reg [31:0] _zz_88_;
reg _zz_89_;
reg [3:0] _zz_90_;
wire contextSwitching;
reg [1:0] _zz_91_;
wire _zz_92_;
reg _zz_93_;
reg _zz_94_;
wire _zz_95_;
wire [31:0] _zz_96_;
reg _zz_97_;
reg _zz_98_;
wire IBusSimplePlugin_jump_pcLoad_valid;
wire [31:0] IBusSimplePlugin_jump_pcLoad_payload;
wire [1:0] _zz_99_;
wire _zz_100_;
wire IBusSimplePlugin_fetchPc_preOutput_valid;
wire IBusSimplePlugin_fetchPc_preOutput_ready;
wire [31:0] IBusSimplePlugin_fetchPc_preOutput_payload;
wire _zz_101_;
wire IBusSimplePlugin_fetchPc_output_valid;
wire IBusSimplePlugin_fetchPc_output_ready;
wire [31:0] IBusSimplePlugin_fetchPc_output_payload;
reg [31:0] IBusSimplePlugin_fetchPc_pcReg /* verilator public */ ;
wire [31:0] IBusSimplePlugin_fetchPc_pcPlus4;
reg _zz_102_;
reg [31:0] IBusSimplePlugin_decodePc_pcReg /* verilator public */ ;
wire [31:0] IBusSimplePlugin_decodePc_pcPlus;
reg IBusSimplePlugin_decodePc_injectedDecode;
wire IBusSimplePlugin_iBusRsp_input_valid;
wire IBusSimplePlugin_iBusRsp_input_ready;
wire [31:0] IBusSimplePlugin_iBusRsp_input_payload;
wire IBusSimplePlugin_iBusRsp_inputPipeline_0_valid;
reg IBusSimplePlugin_iBusRsp_inputPipeline_0_ready;
wire [31:0] IBusSimplePlugin_iBusRsp_inputPipeline_0_payload;
wire _zz_103_;
reg _zz_104_;
reg [31:0] _zz_105_;
reg IBusSimplePlugin_iBusRsp_readyForError;
wire IBusSimplePlugin_iBusRsp_output_valid;
wire IBusSimplePlugin_iBusRsp_output_ready;
wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_pc;
wire IBusSimplePlugin_iBusRsp_output_payload_rsp_error;
wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_rsp_inst;
wire IBusSimplePlugin_iBusRsp_output_payload_isRvc;
wire IBusSimplePlugin_decompressor_inputBeforeStage_valid;
wire IBusSimplePlugin_decompressor_inputBeforeStage_ready;
wire [31:0] IBusSimplePlugin_decompressor_inputBeforeStage_payload_pc;
wire IBusSimplePlugin_decompressor_inputBeforeStage_payload_rsp_error;
wire [31:0] IBusSimplePlugin_decompressor_inputBeforeStage_payload_rsp_inst;
wire IBusSimplePlugin_decompressor_inputBeforeStage_payload_isRvc;
reg IBusSimplePlugin_decompressor_bufferValid;
reg [15:0] IBusSimplePlugin_decompressor_bufferData;
wire [31:0] IBusSimplePlugin_decompressor_raw;
wire IBusSimplePlugin_decompressor_isRvc;
wire [15:0] _zz_106_;
reg [31:0] IBusSimplePlugin_decompressor_decompressed;
wire [4:0] _zz_107_;
wire [4:0] _zz_108_;
wire [11:0] _zz_109_;
wire _zz_110_;
reg [11:0] _zz_111_;
wire _zz_112_;
reg [9:0] _zz_113_;
wire [20:0] _zz_114_;
wire _zz_115_;
reg [14:0] _zz_116_;
wire _zz_117_;
reg [2:0] _zz_118_;
wire _zz_119_;
reg [9:0] _zz_120_;
wire [20:0] _zz_121_;
wire _zz_122_;
reg [4:0] _zz_123_;
wire [12:0] _zz_124_;
wire [4:0] _zz_125_;
wire [4:0] _zz_126_;
wire [4:0] _zz_127_;
wire _zz_128_;
reg [2:0] _zz_129_;
reg [2:0] _zz_130_;
wire _zz_131_;
reg [6:0] _zz_132_;
wire IBusSimplePlugin_injector_decodeInput_valid;
wire IBusSimplePlugin_injector_decodeInput_ready;
wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_pc;
wire IBusSimplePlugin_injector_decodeInput_payload_rsp_error;
wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst;
wire IBusSimplePlugin_injector_decodeInput_payload_isRvc;
reg _zz_133_;
reg [31:0] _zz_134_;
reg _zz_135_;
reg [31:0] _zz_136_;
reg _zz_137_;
reg _zz_138_;
reg _zz_139_;
reg _zz_140_;
reg _zz_141_;
reg IBusSimplePlugin_injector_decodeRemoved;
reg [31:0] IBusSimplePlugin_injector_formal_rawInDecode;
reg [2:0] IBusSimplePlugin_pendingCmd;
wire [2:0] IBusSimplePlugin_pendingCmdNext;
wire _zz_142_;
reg [2:0] IBusSimplePlugin_rsp_discardCounter;
wire [31:0] IBusSimplePlugin_rsp_fetchRsp_pc;
reg IBusSimplePlugin_rsp_fetchRsp_rsp_error;
wire [31:0] IBusSimplePlugin_rsp_fetchRsp_rsp_inst;
wire IBusSimplePlugin_rsp_fetchRsp_isRvc;
wire IBusSimplePlugin_rsp_issueDetected;
wire _zz_143_;
wire _zz_144_;
wire IBusSimplePlugin_rsp_join_valid;
wire IBusSimplePlugin_rsp_join_ready;
wire [31:0] IBusSimplePlugin_rsp_join_payload_pc;
wire IBusSimplePlugin_rsp_join_payload_rsp_error;
wire [31:0] IBusSimplePlugin_rsp_join_payload_rsp_inst;
wire IBusSimplePlugin_rsp_join_payload_isRvc;
wire _zz_145_;
reg [31:0] _zz_146_;
reg [3:0] _zz_147_;
wire [3:0] execute_DBusSimplePlugin_formalMask;
reg [31:0] writeBack_DBusSimplePlugin_rspShifted;
wire _zz_148_;
reg [31:0] _zz_149_;
wire _zz_150_;
reg [31:0] _zz_151_;
reg [31:0] writeBack_DBusSimplePlugin_rspFormated;
reg [1:0] CsrPlugin_misa_base;
reg [25:0] CsrPlugin_misa_extensions;
reg [31:0] CsrPlugin_mtvec;
reg [31:0] CsrPlugin_mepc;
reg CsrPlugin_mstatus_MIE;
reg CsrPlugin_mstatus_MPIE;
reg [1:0] CsrPlugin_mstatus_MPP;
reg CsrPlugin_mip_MEIP;
reg CsrPlugin_mip_MTIP;
reg CsrPlugin_mip_MSIP;
reg CsrPlugin_mie_MEIE;
reg CsrPlugin_mie_MTIE;
reg CsrPlugin_mie_MSIE;
reg [31:0] CsrPlugin_mscratch;
reg CsrPlugin_mcause_interrupt;
reg [3:0] CsrPlugin_mcause_exceptionCode;
reg [31:0] CsrPlugin_mbadaddr;
reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000;
reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000;
wire CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack;
wire CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code;
reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
wire execute_exception_agregat_valid;
wire [3:0] execute_exception_agregat_payload_code;
wire [31:0] execute_exception_agregat_payload_badAddr;
wire [1:0] _zz_152_;
wire _zz_153_;
wire [0:0] _zz_154_;
wire CsrPlugin_interruptRequest;
wire CsrPlugin_interrupt;
wire CsrPlugin_exception;
reg CsrPlugin_writeBackWasWfi;
reg CsrPlugin_pipelineLiberator_done;
wire [3:0] CsrPlugin_interruptCode /* verilator public */ ;
wire CsrPlugin_interruptJump /* verilator public */ ;
reg CsrPlugin_exception_regNext;
reg execute_CsrPlugin_illegalAccess;
wire [31:0] execute_CsrPlugin_writeSrc;
reg [31:0] execute_CsrPlugin_readData;
reg execute_CsrPlugin_readDataRegValid;
reg [31:0] execute_CsrPlugin_writeData;
wire execute_CsrPlugin_writeInstruction;
wire execute_CsrPlugin_readInstruction;
wire execute_CsrPlugin_writeEnable;
wire execute_CsrPlugin_readEnable;
wire [11:0] execute_CsrPlugin_csrAddress;
wire [28:0] _zz_155_;
wire _zz_156_;
wire _zz_157_;
wire _zz_158_;
wire _zz_159_;
wire _zz_160_;
wire _zz_161_;
wire _zz_162_;
wire _zz_163_;
wire _zz_164_;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_165_;
wire `Src1CtrlEnum_defaultEncoding_type _zz_166_;
wire `Src2CtrlEnum_defaultEncoding_type _zz_167_;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_168_;
wire `AluCtrlEnum_defaultEncoding_type _zz_169_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_170_;
wire `BranchCtrlEnum_defaultEncoding_type _zz_171_;
wire [4:0] decode_RegFilePlugin_regFileReadAddress1;
wire [4:0] decode_RegFilePlugin_regFileReadAddress2;
wire [31:0] decode_RegFilePlugin_rs1Data;
wire [31:0] decode_RegFilePlugin_rs2Data;
reg writeBack_RegFilePlugin_regFileW"b"rite_valid /* verilator public */ ;
wire [4:0] writeBack_RegFilePlugin_regFileWrite_payload_address /* verilator public */ ;
wire [31:0] writeBack_RegFilePlugin_regFileWrite_payload_data /* verilator public */ ;
reg _zz_172_;
reg [31:0] execute_IntAluPlugin_bitwise;
reg [31:0] _zz_173_;
reg [31:0] _zz_174_;
wire _zz_175_;
reg [19:0] _zz_176_;
wire _zz_177_;
reg [19:0] _zz_178_;
reg [31:0] _zz_179_;
wire [31:0] execute_SrcPlugin_addSub;
wire execute_SrcPlugin_less;
reg execute_LightShifterPlugin_isActive;
wire execute_LightShifterPlugin_isShift;
reg [4:0] execute_LightShifterPlugin_amplitudeReg;
wire [4:0] execute_LightShifterPlugin_amplitude;
wire [31:0] execute_LightShifterPlugin_shiftInput;
wire execute_LightShifterPlugin_done;
reg [31:0] _zz_180_;
reg _zz_181_;
reg _zz_182_;
reg _zz_183_;
reg [4:0] _zz_184_;
reg execute_MulPlugin_aSigned;
reg execute_MulPlugin_bSigned;
wire [31:0] execute_MulPlugin_a;
wire [31:0] execute_MulPlugin_b;
wire [15:0] execute_MulPlugin_aULow;
wire [15:0] execute_MulPlugin_bULow;
wire [16:0] execute_MulPlugin_aSLow;
wire [16:0] execute_MulPlugin_bSLow;
wire [16:0] execute_MulPlugin_aHigh;
wire [16:0] execute_MulPlugin_bHigh;
wire [65:0] writeBack_MulPlugin_result;
reg [32:0] memory_DivPlugin_rs1;
reg [31:0] memory_DivPlugin_rs2;
reg [64:0] memory_DivPlugin_accumulator;
reg memory_DivPlugin_div_needRevert;
reg memory_DivPlugin_div_counter_willIncrement;
reg memory_DivPlugin_div_counter_willClear;
reg [5:0] memory_DivPlugin_div_counter_valueNext;
reg [5:0] memory_DivPlugin_div_counter_value;
wire memory_DivPlugin_div_willOverflowIfInc;
wire memory_DivPlugin_div_counter_willOverflow;
reg [31:0] memory_DivPlugin_div_result;
wire [31:0] _zz_185_;
wire [32:0] _zz_186_;
wire [32:0] _zz_187_;
wire [31:0] _zz_188_;
wire _zz_189_;
wire _zz_190_;
reg [32:0] _zz_191_;
wire execute_BranchPlugin_eq;
wire [2:0] _zz_192_;
reg _zz_193_;
reg _zz_194_;
wire [31:0] execute_BranchPlugin_branch_src1;
wire _zz_195_;
reg [10:0] _zz_196_;
wire _zz_197_;
reg [19:0] _zz_198_;
wire _zz_199_;
reg [18:0] _zz_200_;
reg [31:0] _zz_201_;
wire [31:0] execute_BranchPlugin_branch_src2;
wire [31:0] execute_BranchPlugin_branchAdder;
reg DebugPlugin_firstCycle;
reg DebugPlugin_secondCycle;
reg DebugPlugin_resetIt;
reg DebugPlugin_haltIt;
reg DebugPlugin_stepIt;
reg DebugPlugin_isPipActive;
reg DebugPlugin_isPipActive_regNext;
wire DebugPlugin_isPipBusy;
reg DebugPlugin_haltedByBreak;
reg [31:0] DebugPlugin_busReadDataReg;
reg _zz_202_;
reg _zz_203_;
reg DebugPlugin_resetIt_regNext;
reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL;
reg [33:0] execute_to_memory_MUL_HL;
reg decode_to_execute_IS_CSR;
reg [31:0] decode_to_execute_SRC2;
reg decode_to_execute_SRC_USE_SUB_LESS;
reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL;
reg decode_to_execute_SRC_LESS_UNSIGNED;
reg decode_to_execute_MEMORY_ENABLE;
reg execute_to_memory_MEMORY_ENABLE;
reg memory_to_writeBack_MEMORY_ENABLE;
reg [51:0] memory_to_writeBack_MUL_LOW;
reg [31:0] execute_to_memory_REGFILE_WRITE_DATA;
reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA;
reg [31:0] decode_to_execute_PC;
reg [31:0] execute_to_memory_PC;
reg [31:0] memory_to_writeBack_PC;
reg execute_to_memory_BRANCH_DO;
reg decode_to_execute_IS_MUL;
reg execute_to_memory_IS_MUL;
reg memory_to_writeBack_IS_MUL;
reg decode_to_execute_BYPASSABLE_MEMORY_STAGE;
reg execute_to_memory_BYPASSABLE_MEMORY_STAGE;
reg [31:0] execute_to_memory_MUL_LL;
reg [33:0] execute_to_memory_MUL_LH;
reg decode_to_execute_IS_EBREAK;
reg decode_to_execute_IS_DIV;
reg execute_to_memory_IS_DIV;
reg decode_to_execute_IS_RS1_SIGNED;
reg [31:0] decode_to_execute_FORMAL_PC_NEXT;
reg [31:0] execute_to_memory_FORMAL_PC_NEXT;
reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT;
reg [31:0] decode_to_execute_RS2;
reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW;
reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW;
reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL;
reg decode_to_execute_IS_RS2_SIGNED;
reg decode_to_execute_CSR_READ_OPCODE;
reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL;
reg decode_to_execute_CSR_WRITE_OPCODE;
reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL;
reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL;
reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL;
reg [31:0] decode_to_execute_SRC1;
reg [31:0] execute_to_memory_BRANCH_CALC;
reg decode_to_execute_REGFILE_WRITE_VALID;
reg execute_to_memory_REGFILE_WRITE_VALID;
reg memory_to_writeBack_REGFILE_WRITE_VALID;
reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
reg [33:0] execute_to_memory_MUL_HH;
reg [33:0] memory_to_writeBack_MUL_HH;
reg [31:0] decode_to_execute_INSTRUCTION;
reg [31:0] execute_to_memory_INSTRUCTION;
reg [31:0] memory_to_writeBack_INSTRUCTION;
reg [31:0] decode_to_execute_RS1;
reg [31:0] memory_to_writeBack_MEMORY_READ_DATA;
reg [2:0] _zz_204_;
reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ;
assign _zz_217_ = (memory_arbitration_isValid && memory_IS_DIV);
assign _zz_218_ = (! memory_DivPlugin_div_willOverflowIfInc);
assign _zz_219_ = (CsrPlugin_exception || CsrPlugin_interruptJump);
assign _zz_220_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_MRET));
assign _zz_221_ = (memory_arbitration_isValid || writeBack_arbitration_isValid);
assign _zz_222_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000)));
assign _zz_223_ = (! execute_arbitration_isStuckByOthers);
assign _zz_224_ = (DebugPlugin_stepIt && _zz_86_);
assign _zz_225_ = (! memory_arbitration_isStuck);
assign _zz_226_ = debug_bus_cmd_payload_address[2 : 2];
assign _zz_227_ = (IBusSimplePlugin_iBusRsp_output_valid && IBusSimplePlugin_iBusRsp_output_ready);
assign _zz_228_ = {_zz_106_[1 : 0],_zz_106_[15 : 13]};
assign _zz_229_ = _zz_106_[6 : 5];
assign _zz_230_ = _zz_106_[11 : 10];
assign _zz_231_ = writeBack_INSTRUCTION[13 : 12];
assign _zz_232_ = execute_INSTRUCTION[13];
assign _zz_233_ = execute_INSTRUCTION[13 : 12];
assign _zz_234_ = writeBack_INSTRUCTION[13 : 12];
assign _zz_235_ = (_zz_99_ & (~ _zz_236_));
assign _zz_236_ = (_zz_99_ - (2'b01));
assign _zz_237_ = (decode_IS_RVC ? (3'b010) : (3'b100));
assign _zz_238_ = {29'd0, _zz_237_};
assign _zz_239_ = {{_zz_116_,_zz_106_[6 : 2]},(12'b000000000000)};
assign _zz_240_ = {{{(4'b0000),_zz_106_[8 : 7]},_zz_106_[12 : 9]},(2'b00)};
assign _zz_241_ = {{{(4'b0000),_zz_106_[8 : 7]},_zz_106_[12 : 9]},(2'b00)};
assign _zz_242_ = (decode_IS_RVC ? (3'b010) : (3'b100));
assign _zz_243_ = {29'd0, _zz_242_};
assign _zz_244_ = (IBusSimplePlugin_pendingCmd + _zz_246_);
assign _zz_245_ = (iBus_cmd_valid && iBus_cmd_ready);
assign _zz_246_ = {2'd0, _zz_245_};
assign _zz_247_ = iBus_rsp_valid;
assign _zz_248_ = {2'd0, _zz_247_};
assign _zz_249_ = (iBus_rsp_valid && (IBusSimplePlugin_rsp_discardCounter != (3'b000)));
assign _zz_250_ = {2'd0, _zz_249_};
assign _zz_251_ = (_zz_152_ & (~ _zz_252_));
assign _zz_252_ = (_zz_152_ - (2'b01));
assign _zz_253_ = ((CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE) ? (3'b011) : (3'b111));
assign _zz_254_ = {1'd0, _zz_253_};
assign _zz_255_ = execute_INSTRUCTION[19 : 15];
assign _zz_256_ = {27'd0, _zz_255_};
assign _zz_257_ = _zz_155_[0 : 0];
assign _zz_258_ = _zz_155_[1 : 1];
assign _zz_259_ = _zz_155_[4 : 4];
assign _zz_260_ = _zz_155_[5 : 5];
assign _zz_261_ = _zz_155_[6 : 6];
assign _zz_262_ = _zz_155_[7 : 7];
assign _zz_263_ = _zz_155_[10 : 10];
assign _zz_264_ = _zz_155_[11 : 11];
assign _zz_265_ = _zz_155_[12 : 12];
assign _zz_266_ = _zz_155_[15 : 15];
assign _zz_267_ = _zz_155_[18 : 18];
assign _zz_268_ = _zz_155_[19 : 19];
assign _zz_269_ = _zz_155_[20 : 20];
assign _zz_270_ = _zz_155_[23 : 23];
assign _zz_271_ = execute_SRC_LESS;
assign _zz_272_ = (decode_IS_RVC ? (3'b010) : (3'b100));
assign _zz_273_ = decode_INSTRUCTION[31 : 20];
assign _zz_274_ = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]};
assign _zz_275_ = ($signed(_zz_276_) + $signed(_zz_280_));
assign _zz_276_ = ($signed(_zz_277_) + $signed(_zz_278_));
assign _zz_277_ = execute_SRC1;
assign _zz_278_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2);
assign _zz_279_ = (execute_SRC_USE_SUB_LESS ? _zz_281_ : _zz_282_);
assign _zz_280_ = {{30{_zz_279_[1]}}, _zz_279_};
assign _zz_281_ = (2'b01);
assign _zz_282_ = (2'b00);
assign _zz_283_ = (_zz_284_ >>> 1);
assign _zz_284_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput};
assign _zz_285_ = ($signed(_zz_286_) + $signed(_zz_291_));
assign _zz_286_ = ($signed(_zz_287_) + $signed(_zz_289_));
assign _zz_287_ = (52'b0000000000000000000000000000000000000000000000000000);
assign _zz_288_ = {1'b0,memory_MUL_LL};
assign _zz_289_ = {{19{_zz_288_[32]}}, _zz_288_};
assign _zz_290_ = ({16'd0,memory_MUL_LH} <<< 16);
assign _zz_291_ = {{2{_zz_290_[49]}}, _zz_290_};
assign _zz_292_ = ({16'd0,memory_MUL_HL} <<< 16);
assign _zz_293_ = {{2{_zz_292_[49]}}, _zz_292_};
assign _zz_294_ = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW};
assign _zz_295_ = ({32'd0,writeBack_MUL_HH} <<< 32);
assign _zz_296_ = writeBack_MUL_LOW[31 : 0];
assign _zz_297_ = writeBack_MulPlugin_result[63 : 32];
assign _zz_298_ = memory_DivPlugin_div_counter_willIncrement;
assign _zz_299_ = {5'd0, _zz_298_};
assign _zz_300_ = {1'd0, memory_DivPlugin_rs2};
assign _zz_301_ = {_zz_185_,(! _zz_187_[32])};
assign _zz_302_ = _zz_187_[31:0];
assign _zz_303_ = _zz_186_[31:0];
assign _zz_304_ = _zz_305_;
assign _zz_305_ = _zz_306_;
assign _zz_306_ = ({1'b0,(memory_DivPlugin_div_needRevert ? (~ _zz_188_) : _zz_188_)} + _zz_308_);
assign _zz_307_ = memory_DivPlugin_div_needRevert;
assign _zz_308_ = {32'd0, _zz_307_};
assign _zz_309_ = _zz_190_;
assign _zz_310_ = {32'd0, _zz_309_};
assign _zz_311_ = _zz_189_;
assign _zz_312_ = {31'd0, _zz_311_};
assign _zz_313_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz_314_ = execute_INSTRUCTION[31 : 20];
assign _zz_315_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz_316_ = execute_CsrPlugin_writeData[7 : 7];
assign _zz_317_ = execute_CsrPlugin_writeData[3 : 3];
assign _zz_318_ = execute_CsrPlugin_writeData[3 : 3];
assign _zz_319_ = execute_CsrPlugin_writeData[11 : 11];
assign _zz_320_ = execute_CsrPlugin_writeData[7 : 7];
assign _zz_321_ = execute_CsrPlugin_writeData[3 : 3];
assign _zz_322_ = execute_CsrPlugin_writeData[31 : 31];
assign _zz_323_ = 1'b1;
assign _zz_324_ = 1'b1;
assign _zz_325_ = _zz_100_;
assign _zz_326_ = (_zz_106_[11 : 10] == (2'b01));
assign _zz_327_ = ((_zz_106_[11 : 10] == (2'b11)) && (_zz_106_[6 : 5] == (2'b00)));
assign _zz_328_ = (7'b0000000);
assign _zz_329_ = _zz_106_[6 : 2];
assign _zz_330_ = _zz_106_[12];
assign _zz_331_ = _zz_106_[11 : 7];
assign _zz_332_ = (32'b00000000000000000000000001011000);
assign _zz_333_ = (decode_INSTRUCTION & (32'b00100000000100000011000001010000));
assign _zz_334_ = (32'b00000000000000000000000001010000);
assign _zz_335_ = ((decode_INSTRUCTION & (32'b00010000000000000011000001010000)) == (32'b00010000000000000000000001010000));
assign _zz_336_ = ((decode_INSTRUCTION & (32'b00110000000000000011000001010000)) == (32'b00010000000000000000000001010000));
assign _zz_337_ = (1'b0);
assign _zz_338_ = ({(_zz_341_ == _zz_342_),(_zz_343_ == _zz_344_)} != (2'b00));
assign _zz_339_ = ({_zz_345_,{_zz_346_,_zz_347_}} != (3'b000));
assign _zz_340_ = {(_zz_164_ != (1'b0)),{(_zz_348_ != _zz_349_),{_zz_350_,{_zz_351_,_zz_352_}}}};
assign _zz_341_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010000));
assign _zz_342_ = (32'b00000000000000000010000000000000);
assign _zz_343_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000000));
assign _zz_344_ = (32'b00000000000000000001000000000000);
assign _zz_345_ = ((decode_INSTRUCTION & (32'b00000000000000000100000000000100)) == (32'b00000000000000000100000000000000));
assign _zz_346_ = ((decode_INSTRUCTION & _zz_353_) == (32'b00000000000000000000000000100100));
assign _zz_347_ = ((decode_INSTRUCTION & _zz_354_) == (32'b00000000000000000001000000000000));
assign _zz_348_ = ((decode_INSTRUCTION & _zz_355_) == (32'b00000010000000000000000000110000));
assign _zz_349_ = (1'b0);
assign _zz_350_ = ({_zz_356_,{_zz_357_,_zz_358_}} != (4'b0000));
assign _zz_351_ = (_zz_359_ != (1'b0));
assign _zz_352_ = {(_zz_360_ != _zz_361_),{_zz_362_,{_zz_363_,_zz_364_}}};
assign _zz_353_ = (32'b00000000000000000000000001100100);
assign _zz_354_ = (32'b00000000000000000011000000000100);
assign _zz_355_ = (32'b00000010000000000100000001110100);
assign _zz_356_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000000000000));
assign _zz_357_ = ((decode_INSTRUCTION & _zz_365_) == (32'b00000000000000000000000000000000));
assign _zz_358_ = {_zz_164_,(_zz_366_ == _zz_367_)};
assign _zz_359_ = ((decode_INSTRUCTION & (32'b00000010000000000100000001100100)) == (32'b00000010000000000100000000100000));
assign _zz_360_ = {(_zz_368_ == _zz_369_),(_zz_370_ == _zz_371_)};
assign _zz_361_ = (2'b00);
assign _zz_362_ = ({_zz_372_,{_zz_373_,_zz_374_}} != (3'b000));
assign _zz_363_ = (_zz_162_ != (1'b0));
assign _zz_364_ = {(_zz_375_ != _zz_376_),{_zz_377_,{_zz_378_,_zz_379_}}};
assign _zz_365_ = (32'b00000000000000000000000000011000);
assign _zz_366_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000100));
assign _zz_367_ = (32'b00000000000000000001000000000000);
assign _zz_368_ = (decode_INSTRUCTION & (32'b00000000000000000111000000110100));
assign _zz_369_ = (32'b00000000000000000101000000010000);
assign _zz_370_ = (decode_INSTRUCTION & (32'b00000010000000000111000001100100));
assign _zz_371_ = (32'b00000000000000000101000000100000);
assign _zz_372_ = ((decode_INSTRUCTION & (32'b01000000000000000011000001010100)) == (32'b01000000000000000001000000010000));
assign _zz_373_ = ((decode_INSTRUCTION & _zz_380_) == (32'b00000000000000000001000000010000));
assign _zz_374_ = ((decode_INSTRUCTION & _zz_381_) == (32'b00000000000000000001000000010000));
assign _zz_375_ = {_zz_158_,{_zz_163_,_zz_382_}};
assign _zz_376_ = (3'b000);
assign _zz_377_ = ({_zz_158_,{_zz_383_,_zz_384_}} != (3'b000));
assign _zz_378_ = ({_zz_385_,_zz_386_} != (2'b00));
assign _zz_379_ = {(_zz_387_ != _zz_388_),{_zz_389_,{_zz_390_,_zz_391_}}};
assign _zz_380_ = (32'b00000000000000000111000000110100);
assign _zz_381_ = (32'b00000010000000000111000001010100);
assign _zz_382_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001110000)) == (32'b00000000000000000000000000100000));
assign _zz_383_ = _zz_160_;
assign _zz_384_ = _zz_163_;
assign _zz_385_ = ((decode_INSTRUCTION & _zz_392_) == (32'b00000000000000000000000000100000));
assign _zz_386_ = ((decode_INSTRUCTION & _zz_393_) == (32'b00000000000000000000000000100000));
assign _zz_387_ = _zz_162_;
assign _zz_388_ = (1'b0);
assign _zz_389_ = ({_zz_394_,_zz_395_} != (2'b00));
assign _zz_390_ = (_zz_161_ != (1'b0));
assign _zz_391_ = {(_zz_396_ != _zz_397_),{_zz_398_,{_zz_399_,_zz_400_}}};
assign _zz_392_ = (32'b00000000000000000000000000110100);
assign _zz_393_ = (32'b00000000000000000000000001100100);
assign _zz_394_ = ((decode_INSTRUCTION & (32'b00000000000000000001000001010000)) == (32'b00000000000000000001000001010000));
assign _zz_395_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001010000)) == (32'b00000000000000000010000001010000));
assign _zz_396_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000000000100));
assign _zz_397_ = (1'b0);
assign _zz_398_ = ({_zz_158_,{_zz_160_,{_zz_401_,_zz_402_}}} != (5'b00000));
assign _zz_399_ = ((_zz_403_ == _zz_404_) != (1'b0));
assign _zz_400_ = {(_zz_405_ != (1'b0)),{(_zz_406_ != _zz_407_),{_zz_408_,{_zz_409_,_zz_410_}}}};
assign _zz_401_ = ((decode_INSTRUCTION & _zz_411_) == (32'b00000000000000000001000000010000));
assign _zz_402_ = {(_zz_412_ == _zz_413_),(_zz_414_ == _zz_415_)};
assign _zz_403_ = (decode_INSTRUCTION & (32'b00010000000100000011000001010000));
assign _zz_404_ = (32'b00000000000100000000000001010000);
assign _zz_405_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000000000));
assign _zz_406_ = {_zz_159_,{_zz_158_,{_zz_416_,_zz_417_}}};
assign _zz_407_ = (4'b0000);
assign _zz_408_ = ({_zz_418_,_zz_158_} != (2'b00));
assign _zz_409_ = ({_zz_419_,_zz_420_} != (3'b000));
assign _zz_410_ = {(_zz_421_ != _zz_422_),(_zz_423_ != _zz_424_)};
assign _zz_411_ = (32'b00000000000000000001000000010000);
assign _zz_412_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010000));
assign _zz_413_ = (32'b00000000000000000010000000010000);
assign _zz_414_ = (decode_INSTRUCTION & (32'b00000000000000000000000001010000));
assign _zz_415_ = (32'b00000000000000000000000000010000);
assign _zz_416_ = _zz_157_;
assign _zz_417_ = _zz_156_;
assign _zz_418_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000000000)) == (32'b00000000000000000001000000000000));
assign _zz_419_ = _zz_158_;
assign _zz_420_ = {((decode_INSTRUCTION & _zz_425_) == (32'b00000000000000000001000000000000)),((decode_INSTRUCTION & _zz_426_) == (32'b00000000000000000010000000000000))};
assign _zz_421_ = {_zz_159_,{_zz_158_,{_zz_427_,{_zz_428_,_zz_429_}}}};
assign _zz_422_ = (5'b00000);
assign _zz_423_ = {((decode_INSTRUCTION & _zz_430_) == (32'b01000000000000000000000000110000)),{(_zz_431_ == _zz_432_),(_zz_433_ == _zz_434_)}};
assign _zz_424_ = (3'b000);
assign _zz_425_ = (32'b00000000000000000011000000000000);
assign _zz_426_ = (32'b00000000000000000011000000000000);
assign _zz_427_ = ((decode_INSTRUCTION & (32'b00000000000000000100000000100000)) == (32'b00000000000000000100000000100000));
assign _zz_428_ = _zz_157_;
assign _zz_429_ = _zz_156_;
assign _zz_430_ = (32'b01000000000000000000000000110000);
assign _zz_431_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010100));
assign _zz_432_ = (32'b00000000000000000010000000010000);
assign _zz_433_ = (decode_INSTRUCTION & (32'b00000000000000000000000001010100));
assign _zz_434_ = (32'b00000000000000000000000001000000);
always @ (posedge io_mainClk) begin
if(_zz_46_) begin
RegFilePlugin_regFile[writeBack_RegFilePlugin_regFileWrite_payload_address] <= writeBack_RegFilePlugin_regFileWrite_payload_data;
end
end
always @ (posedge io_mainClk) begin
if(_zz_323_) begin
_zz_207_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1];
end
end
always @ (posedge io_mainClk) begin
if(_zz_324_) begin
_zz_208_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2];
end
end
StreamFifoLowLatency IBusSimplePlugin_rsp_rspBuffer (
.io_push_valid(_zz_205_),
.io_push_ready(_zz_212_),
.io_push_payload_error(iBus_rsp_payload_error),
.io_push_payload_inst(iBus_rsp_payload_inst),
.io_pop_valid(_zz_213_),
.io_pop_ready(_zz_144_),
.io_pop_payload_error(_zz_214_),
.io_pop_payload_inst(_zz_215_),
.io_flush(_zz_206_),
.io_occupancy(_zz_216_),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
always @(*) begin
case(_zz_325_)
1'b0 : begin
_zz_209_ = _zz_88_;
end
default : begin
_zz_209_ = _zz_96_;
end
endcase
end
always @(*) begin
case(_zz_154_)
1'b0 : begin
_zz_210_ = _zz_90_;
_zz_211_ = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
end
default : begin
_zz_210_ = (4'b0010);
_zz_211_ = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
end
endcase
end
assign memory_MEMORY_READ_DATA = _zz_76_;
assign decode_RS1 = _zz_48_;
assign memory_MUL_HH = execute_to_memory_MUL_HH;
assign execute_MUL_HH = _zz_26_;
assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_66_;
assign execute_BRANCH_CALC = _zz_21_;
assign decode_SRC1 = _zz_40_;
assign memory_ENV_CTRL = _zz_1_;
assign _zz_2_ = _zz_3_;
assign _zz_4_ = _zz_5_;
assign decode_ENV_CTRL = _zz_6_;
assign _zz_7_ = _zz_8_;
assign decode_CSR_WRITE_OPCODE = _zz_72_;
assign decode_ALU_CTRL = _zz_9_;
assign _zz_10_ = _zz_11_;
assign decode_CSR_READ_OPCODE = _zz_71_;
assign decode_IS_RS2_SIGNED = _zz_57_;
assign decode_ALU_BITWISE_CTRL = _zz_12_;
assign _zz_13_ = _zz_14_;
assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW;
assign execute_MEMORY_ADDRESS_LOW = _zz_77_;
assign decode_RS2 = _zz_47_;
assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT;
assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT;
assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT;
assign decode_FORMAL_PC_NEXT = _zz_79_;
assign decode_IS_RS1_SIGNED = _zz_60_;
assign decode_IS_DIV = _zz_55_;
assign decode_IS_EBREAK = _zz_64_;
assign execute_MUL_LH = _zz_28_;
assign execute_MUL_LL = _zz_29_;
assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE;
assign decode_BYPASSABLE_MEMORY_STAGE = _zz_68_;
assign memory_IS_MUL = execute_to_memory_IS_MUL;
assign execute_IS_MUL = decode_to_execute_IS_MUL;
assign decode_IS_MUL = _zz_53_;
assign execute_BRANCH_DO = _zz_23_;
assign memory_PC = execute_to_memory_PC;
assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA;
assign execute_REGFILE_WRITE_DATA = _zz_42_;
assign memory_MUL_LOW = _zz_25_;
assign decode_MEMORY_ENABLE = _zz_65_;
assign decode_SRC_LESS_UNSIGNED = _zz_51_;
assign decode_SHIFT_CTRL = _zz_15_;
assign _zz_16_ = _zz_17_;
assign decode_SRC_USE_SUB_LESS = _zz_69_;
assign decode_SRC2 = _zz_37_;
assign execute_MUL_HL = _zz_27_;
assign decode_BRANCH_CTRL = _zz_18_;
assign _zz_19_ = _zz_20_;
assign execute_IS_EBREAK = decode_to_execute_IS_EBREAK;
assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC;
assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO;
assign execute_PC = decode_to_execute_PC;
assign execute_BRANCH_CTRL = _zz_22_;
assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED;
assign execute_RS1 = decode_to_execute_RS1;
assign execute_IS_DIV = decode_to_execute_IS_DIV;
assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED;
always @ (*) begin
_zz_24_ = memory_REGFILE_WRITE_DATA;
memory_arbitration_haltItself = 1'b0;
if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_INSTRUCTION[5])) && (! dBus_rsp_ready)))begin
memory_arbitration_haltItself = 1'b1;
end
memory_DivPlugin_div_counter_willIncrement = 1'b0;
if(_zz_217_)begin
if(_zz_218_)begin
memory_arbitration_haltItself = 1'b1;
memory_DivPlugin_div_counter_willIncrement = 1'b1;
end
_zz_24_ = memory_DivPlugin_div_result;
end
end
assign memory_IS_DIV = execute_to_memory_IS_DIV;
assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL;
assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH;
assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW;
assign memory_MUL_HL = execute_to_memory_MUL_HL;
assign memory_MUL_LH = execute_to_memory_MUL_LH;
assign memory_MUL_LL = execute_to_memory_MUL_LL;
assign decode_RS2_USE = _zz_59_;
assign decode_RS1_USE = _zz_54_;
assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID;
assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID;
assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE;
assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID;
assign execute_SHIFT_CTRL = _zz_30_;
assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED;
assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS;
assign _zz_34_ = decode_PC;
assign _zz_35_ = decode_RS2;
assign decode_SRC2_CTRL = _zz_36_;
assign _zz_38_ = decode_RS1;
assign decode_SRC1_CTRL = _zz_39_;
assign execute_SRC_ADD_SUB = _zz_33_;
assign execute_SRC_LESS = _zz_31_;
assign execute_ALU_CTRL = _zz_41_;
assign execute_SRC2 = decode_to_execute_SRC2;
assign execute_ALU_BITWISE_CTRL = _zz_43_;
assign _zz_44_ = writeBack_INSTRUCTION;
assign _zz_45_ = writeBack_REGFILE_WRITE_VALID;
always @ (*) begin
_zz_46_ = 1'b0;
if(writeBack_RegFilePlugin_regFileWrite_valid)begin
_zz_46_ = 1'b1;
end
end
assign decode_INSTRUCTION_ANTICIPATED = _zz_83_;
always @ (*) begin
decode_REGFILE_WRITE_VALID = _zz_63_;
if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin
decode_REGFILE_WRITE_VALID = 1'b0;
end
end
always @ (*) begin
_zz_70_ = execute_REGFILE_WRITE_DATA;
decode_arbitration_flushAll = 1'b0;
execute_arbitration_haltItself = 1'b0;
memory_arbitration_flushAll = 1'b0;
_zz_84_ = 1'b0;
_zz_85_ = 1'b0;
_zz_87_ = 1'b0;
_zz_88_ = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
if((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_ALIGNEMENT_FAULT)))begin
execute_arbitration_haltItself = 1'b1;
end
if(_zz_219_)begin
_zz_87_ = 1'b1;
_zz_88_ = CsrPlugin_mtvec;
memory_arbitration_flushAll = 1'b1;
end
if(_zz_220_)begin
if(_zz_221_)begin
execute_arbitration_haltItself = 1'b1;
end else begin
_zz_87_ = 1'b1;
_zz_88_ = CsrPlugin_mepc;
decode_arbitration_flushAll = 1'b1;
end
end
if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)))begin
if((! CsrPlugin_interrupt))begin
execute_arbitration_haltItself = 1'b1;
end
end
if((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_readDataRegValid)))begin
execute_arbitration_haltItself = 1'b1;
end
if((execute_arbitration_isValid && execute_IS_CSR))begin
_zz_70_ = execute_CsrPlugin_readData;
end
if(_zz_222_)begin
_zz_70_ = _zz_180_;
if(_zz_223_)begin
if(! execute_LightShifterPlugin_done) begin
execute_arbitration_haltItself = 1'b1;
end
end
end
if(execute_IS_EBREAK)begin
if(execute_arbitration_isValid)begin
_zz_85_ = 1'b1;
_zz_84_ = 1'b1;
decode_arbitration_flushAll = 1'b1;
end
end
if(DebugPlugin_haltIt)begin
_zz_84_ = 1'b1;
end
if(_zz_224_)begin
_zz_84_ = 1'b1;
end
end
assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE;
assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE;
assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA;
assign execute_SRC1 = decode_to_execute_SRC1;
assign execute_IS_CSR = decode_to_execute_IS_CSR;
assign decode_IS_CSR = _zz_61_;
assign execute_ENV_CTRL = _zz_73_;
assign writeBack_ENV_CTRL = _zz_74_;
always @ (*) begin
_zz_75_ = writeBack_REGFILE_WRITE_DATA;
if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin
_zz_75_ = writeBack_DBusSimplePlugin_rspFormated;
end
if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin
case(_zz_234_)
2'b00 : begin
_zz_75_ = _zz_296_;
end
default : begin
_zz_75_ = _zz_297_;
end
endcase
end
end
assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE;
assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW;
assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA;
assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION;
assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE;
assign execute_RS2 = decode_to_execute_RS2;
assign execute_SRC_ADD = _zz_32_;
assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION;
assign execute_ALIGNEMENT_FAULT = 1'b0;
assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE;
always @ (*) begin
_zz_78_ = memory_FORMAL_PC_NEXT;
if(_zz_95_)begin
_zz_78_ = _zz_96_;
end
end
assign decode_IS_RVC = _zz_80_;
assign writeBack_PC = memory_to_writeBack_PC;
assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION;
assign decode_PC = _zz_82_;
assign decode_INSTRUCTION = _zz_81_;
always @ (*) begin
decode_arbitration_haltItself = 1'b0;
decode_arbitration_isValid = (IBusSimplePlugin_injector_decodeInput_valid && (! IBusSimplePlugin_injector_decodeRemoved));
if(((decode_arbitration_isValid && decode_IS_CSR) && (execute_arbitration_isValid || memory_arbitration_isValid)))begin
decode_arbitration_haltItself = 1'b1;
end
if((decode_arbitration_isValid && (_zz_181_ || _zz_182_)))begin
decode_arbitration_haltItself = 1'b1;
end
_zz_98_ = 1'b0;
case(_zz_204_)
3'b000 : begin
end
3'b001 : begin
end
3'b010 : begin
decode_arbitration_isValid = 1'b1;
decode_arbitration_haltItself = 1'b1;
end
3'b011 : begin
decode_arbitration_isValid = 1'b1;
end
3'b100 : begin
_zz_98_ = 1'b1;
end
default : begin
end
endcase
end
always @ (*) begin
decode_arbitration_haltByOther = 1'b0;
if(CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute)begin
decode_arbitration_haltByOther = 1'b1;
end
if((CsrPlugin_interrupt && decode_arbitration_isValid))begin
decode_arbitration_haltByOther = 1'b1;
end
end
always @ (*) begin
decode_arbitration_removeIt = 1'b0;
if(_zz_203_)begin
decode_arbitration_removeIt = 1'b1;
end
if(decode_arbitration_isFlushed)begin
decode_arbitration_removeIt = 1'b1;
end
end
assign decode_arbitration_redoIt = 1'b0;
always @ (*) begin
execute_arbitration_haltByOther = 1'b0;
if(CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory)begin
execute_arbitration_haltByOther = 1'b1;
end
end
always @ (*) begin
execute_arbitration_removeIt = 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
if(execute_exception_agregat_valid)begin
execute_arbitration_removeIt = 1'b1;
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1;
end
if(execute_arbitration_isFlushed)begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0;
end
if(execute_arbitration_isFlushed)begin
execute_arbitration_removeIt = 1'b1;
end
end
always @ (*) begin
execute_arbitration_flushAll = 1'b0;
if(_zz_95_)begin
execute_arbitration_flushAll = 1'b1;
end
end
assign execute_arbitration_redoIt = 1'b0;
always @ (*) begin
memory_arbitration_haltByOther = 1'b0;
if(CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack)begin
memory_arbitration_haltByOther = 1'b1;
end
end
always @ (*) begin
memory_arbitration_removeIt = 1'b0;
if(memory_arbitration_isFlushed)begin
memory_arbitration_removeIt = 1'b1;
end
end
assign memory_arbitration_redoIt = 1'b0;
assign writeBack_arbitration_haltItself = 1'b0;
assign writeBack_arbitration_haltByOther = 1'b0;
always @ (*) begin
writeBack_arbitration_removeIt = 1'b0;
if(writeBack_arbitration_isFlushed)begin
writeBack_arbitration_removeIt = 1'b1;
end
end
assign writeBack_arbitration_flushAll = 1'b0;
assign writeBack_arbitration_redoIt = 1'b0;
always @ (*) begin
_zz_86_ = 1'b0;
if(IBusSimplePlugin_iBusRsp_inputPipeline_0_valid)begin
_zz_86_ = 1'b1;
end
if((IBusSimplePlugin_decompressor_bufferValid && (IBusSimplePlugin_decompressor_bufferData[1 : 0] != (2'b11))))begin
_zz_86_ = 1'b1;
end
if(IBusSimplePlugin_injector_decodeInput_valid)begin
_zz_86_ = 1'b1;
end
end
always @ (*) begin
_zz_89_ = 1'b0;
_zz_90_ = (4'bxxxx);
if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)))begin
_zz_89_ = 1'b1;
_zz_90_ = (4'b1011);
end
end
always @ (*) begin
_zz_93_ = 1'b1;
if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin
_zz_93_ = 1'b0;
end
end
always @ (*) begin
_zz_94_ = 1'b1;
if(DebugPlugin_haltIt)begin
_zz_94_ = 1'b0;
end
end
assign IBusSimplePlugin_jump_pcLoad_valid = (_zz_87_ || _zz_95_);
assign _zz_99_ = {_zz_95_,_zz_87_};
assign _zz_100_ = _zz_235_[1];
assign IBusSimplePlugin_jump_pcLoad_payload = _zz_209_;
assign _zz_101_ = (! _zz_84_);
assign IBusSimplePlugin_fetchPc_output_valid = (IBusSimplePlugin_fetchPc_preOutput_valid && _zz_101_);
assign IBusSimplePlugin_fetchPc_preOutput_ready = (IBusSimplePlugin_fetchPc_output_ready && _zz_101_);
assign IBusSimplePlugin_fetchPc_output_payload = IBusSimplePlugin_fetchPc_preOutput_payload;
assign IBusSimplePlugin_fetchPc_pcPlus4 = (IBusSimplePlugin_fetchPc_pcReg + (32'b00000000000000000000000000000100));
assign IBusSimplePlugin_fetchPc_preOutput_valid = _zz_102_;
assign IBusSimplePlugin_fetchPc_preOutput_payload = IBusSimplePlugin_fetchPc_pcReg;
assign IBusSimplePlugin_decodePc_pcPlus = (IBusSimplePlugin_decodePc_pcReg + _zz_238_);
always @ (*) begin
IBusSimplePlugin_decodePc_injectedDecode = 1'b0;
if((_zz_204_ != (3'b000)))begin
IBusSimplePlugin_decodePc_injectedDecode = 1'b1;
end
end
assign IBusSimplePlugin_iBusRsp_input_ready = ((1'b0 && (! _zz_103_)) || IBusSimplePlugin_iBusRsp_inputPipeline_0_ready);
assign _zz_103_ = _zz_104_;
assign IBusSimplePlugin_iBusRsp_inputPipeline_0_valid = _zz_103_;
assign IBusSimplePlugin_iBusRsp_inputPipeline_0_payload = _zz_105_;
always @ (*) begin
IBusSimplePlugin_iBusRsp_readyForError = 1'b1;
if((IBusSimplePlugin_decompressor_bufferValid && IBusSimplePlugin_decompressor_isRvc))begin
IBusSimplePlugin_iBusRsp_readyForError = 1'b0;
end
if(IBusSimplePlugin_injector_decodeInput_valid)begin
IBusSimplePlugin_iBusRsp_readyForError = 1'b0;
end
end
assign IBusSimplePlugin_decompressor_raw = (IBusSimplePlugin_decompressor_bufferValid ? {IBusSimplePlugin_iBusRsp_output_payload_rsp_inst[15 : 0],IBusSimplePlugin_decompressor_bufferData} : {IBusSimplePlugin_iBusRsp_output_payload_rsp_inst[31 : 16],(IBusSimplePlugin_iBusRsp_output_payload_pc[1] ? IBusSimplePlugin_iBusRsp_output_payload_rsp_inst[31 : 16] : IBusSimplePlugin_iBusRsp_output_payload_rsp_inst[15 : 0])});
assign IBusSimplePlugin_decompressor_isRvc = (IBusSimplePlugin_decompressor_raw[1 : 0] != (2'b11));
assign _zz_106_ = IBusSimplePlugin_decompressor_raw[15 : 0];
always @ (*) begin
IBusSimplePlugin_decompressor_decompressed = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
case(_zz_228_)
5'b00000 : begin
IBusSimplePlugin_decompressor_decompressed = {{{{{{{{{(2'b00),_zz_106_[10 : 7]},_zz_106_[12 : 11]},_zz_106_[5]},_zz_106_[6]},(2'b00)},(5'b00010)},(3'b000)},_zz_108_},(7'b0010011)};
end
5'b00010 : begin
IBusSimplePlugin_decompressor_decompressed = {{{{_zz_109_,_zz_107_},(3'b010)},_zz_108_},(7'b0000011)};
end
5'b00110 : begin
IBusSimplePlugin_decompressor_decompressed = {{{{{_zz_109_[11 : 5],_zz_108_},_zz_107_},(3'b010)},_zz_109_[4 : 0]},(7'b0100011)};
end
5'b01000 : begin
IBusSimplePlugin_decompressor_decompressed = {{{{_zz_111_,_zz_106_[11 : 7]},(3'b000)},_zz_106_[11 : 7]},(7'b0010011)};
end
5'b01001 : begin
IBusSimplePlugin_decompressor_decompressed = {{{{{_zz_114_[20],_zz_114_[10 : 1]},_zz_114_[11]},_zz_114_[19 : 12]},_zz_126_},(7'b1101111)};
end
5'b01010 : begin
IBusSimplePlugin_decompressor_decompressed = {{{{_zz_111_,(5'b00000)},(3'b000)},_zz_106_[11 : 7]},(7'b0010011)};
end
5'b01011 : begin
IBusSimplePlugin_decompressor_decompressed = ((_zz_106_[11 : 7] == (5'b00010)) ? {{{{{{{{{_zz_118_,_zz_106_[4 : 3]},_zz_106_[5]},_zz_106_[2]},_zz_106_[6]},(4'b0000)},_zz_106_[11 : 7]},(3'b000)},_zz_106_[11 : 7]},(7'b0010011)} : {{_zz_239_[31 : 12],_zz_106_[11 : 7]},(7'b0110111)});
end
5'b01100 : begin
IBusSimplePlugin_decompressor_decompressed = {{{{{((_zz_106_[11 : 10] == (2'b10)) ? _zz_132_ : {{(1'b0),(_zz_326_ || _zz_327_)},(5'b00000)}),(((! _zz_106_[11]) || _zz_128_) ? _zz_106_[6 : 2] : _zz_108_)},_zz_107_},_zz_130_},_zz_107_},(_zz_128_ ? (7'b0010011) : (7'b0110011))};
end
5'b01101 : begin
IBusSimplePlugin_decompressor_decompressed = {{{{{_zz_121_[20],_zz_121_[10 : 1]},_zz_121_[11]},_zz_121_[19 : 12]},_zz_125_},(7'b1101111)};
end
5'b01110 : begin
IBusSimplePlugin_decompressor_decompressed = {{{{{{{_zz_124_[12],_zz_124_[10 : 5]},_zz_125_},_zz_107_},(3'b000)},_zz_124_[4 : 1]},_zz_124_[11]},(7'b1100011)};
end
5'b01111 : begin
IBusSimplePlugin_decompressor_decompressed = {{{{{{{_zz_124_[12],_zz_124_[10 : 5]},_zz_125_},_zz_107_},(3'b001)},_zz_124_[4 : 1]},_zz_124_[11]},(7'b1100011)};
end
5'b10000 : begin
IBusSimplePlugin_decompressor_decompressed = {{{{{(7'b0000000),_zz_106_[6 : 2]},_zz_106_[11 : 7]},(3'b001)},_zz_106_[11 : 7]},(7'b0010011)};
end
5'b10010 : begin
IBusSimplePlugin_decompressor_decompressed = {{{{{{{{(4'b0000),_zz_106_[3 : 2]},_zz_106_[12]},_zz_106_[6 : 4]},(2'b00)},_zz_127_},(3'b010)},_zz_106_[11 : 7]},(7'b0000011)};
end
5'b10100 : begin
IBusSimplePlugin_decompressor_decompressed = ((_zz_106_[12 : 2] == (11'b10000000000)) ? (32'b00000000000100000000000001110011) : ((_zz_106_[6 : 2] == (5'b00000)) ? {{{{(12'b000000000000),_zz_106_[11 : 7]},(3'b000)},(_zz_106_[12] ? _zz_126_ : _zz_125_)},(7'b1100111)} : {{{{{_zz_328_,_zz_329_},(_zz_330_ ? _zz_331_ : _zz_125_)},(3'b000)},_zz_106_[11 : 7]},(7'b0110011)}));
end
5'b10110 : begin
IBusSimplePlugin_decompressor_decompressed = {{{{{_zz_240_[11 : 5],_zz_106_[6 : 2]},_zz_127_},(3'b010)},_zz_241_[4 : 0]},(7'b0100011)};
end
default : begin
end
endcase
end
assign _zz_107_ = {(2'b01),_zz_106_[9 : 7]};
assign _zz_108_ = {(2'b01),_zz_106_[4 : 2]};
assign _zz_109_ = {{{{(5'b00000),_zz_106_[5]},_zz_106_[12 : 10]},_zz_106_[6]},(2'b00)};
assign _zz_110_ = _zz_106_[12];
always @ (*) begin
_zz_111_[11] = _zz_110_;
_zz_111_[10] = _zz_110_;
_zz_111_[9] = _zz_110_;
_zz_111_[8] = _zz_110_;
_zz_111_[7] = _zz_110_;
_zz_111_[6] = _zz_110_;
_zz_111_[5] = _zz_110_;
_zz_111_[4 : 0] = _zz_106_[6 : 2];
end
assign _zz_112_ = _zz_106_[12];
always @ (*) begin
_zz_113_[9] = _zz_112_;
_zz_113_[8] = _zz_112_;
_zz_113_[7] = _zz_112_;
_zz_113_[6] = _zz_112_;
_zz_113_[5] = _zz_112_;
_zz_113_[4] = _zz_112_;
_zz_113_[3] = _zz_112_;
_zz_113_[2] = _zz_112_;
_zz_113_[1] = _zz_112_;
_zz_113_[0] = _zz_112_;
end
assign _zz_114_ = {{{{{{{{_zz_113_,_zz_106_[8]},_zz_106_[10 : 9]},_zz_106_[6]},_zz_106_[7]},_zz_106_[2]},_zz_106_[11]},_zz_106_[5 : 3]},(1'b0)};
assign _zz_115_ = _zz_106_[12];
always @ (*) begin
_zz_116_[14] = _zz_115_;
_zz_116_[13] = _zz_115_;
_zz_116_[12] = _zz_115_;
_zz_116_[11] = _zz_115_;
_zz_116_[10] = _zz_115_;
_zz_116_[9] = _zz_115_;
_zz_116_[8] = _zz_115_;
_zz_116_[7] = _zz_115_;
_zz_116_[6] = _zz_115_;
_zz_116_[5] = _zz_115_;
_zz_116_[4] = _zz_115_;
_zz_116_[3] = _zz_115_;
_zz_116_[2] = _zz_115_;
_zz_116_[1] = _zz_115_;
_zz_116_[0] = _zz_115_;
end
assign _zz_117_ = _zz_106_[12];
always @ (*) begin
_zz_118_[2] = _zz_117_;
_zz_118_[1] = _zz_117_;
_zz_118_[0] = _zz_117_;
end
assign _zz_119_ = _zz_106_[12];
always @ (*) begin
_zz_120_[9] = _zz_119_;
_zz_120_[8] = _zz_119_;
_zz_120_[7] = _zz_119_;
_zz_120_[6] = _zz_119_;
_zz_120_[5] = _zz_119_;
_zz_120_[4] = _zz_119_;
_zz_120_[3] = _zz_119_;
_zz_120_[2] = _zz_119_;
_zz_120_[1] = _zz_119_;
_zz_120_[0] = _zz_119_;
end
assign _zz_121_ = {{{{{{{{_zz_120_,_zz_106_[8]},_zz_106_[10 : 9]},_zz_106_[6]},_zz_106_[7]},_zz_106_[2]},_zz_106_[11]},_zz_106_[5 : 3]},(1'b0)};
assign _zz_122_ = _zz_106_[12];
always @ (*) begin
_zz_123_[4] = _zz_122_;
_zz_123_[3] = _zz_122_;
_zz_123_[2] = _zz_122_;
_zz_123_[1] = _zz_122_;
_zz_123_[0] = _zz_122_;
end
assign _zz_124_ = {{{{{_zz_123_,_zz_106_[6 : 5]},_zz_106_[2]},_zz_106_[11 : 10]},_zz_106_[4 : 3]},(1'b0)};
assign _zz_125_ = (5'b00000);
assign _zz_126_ = (5'b00001);
assign _zz_127_ = (5'b00010);
assign _zz_128_ = (_zz_106_[11 : 10] != (2'b11));
always @ (*) begin
case(_zz_229_)
2'b00 : begin
_zz_129_ = (3'b000);
end
2'b01 : begin
_zz_129_ = (3'b100);
end
2'b10 : begin
_zz_129_ = (3'b110);
end
default : begin
_zz_129_ = (3'b111);
end
endcase
end
always @ (*) begin
case(_zz_230_)
2'b00 : begin
_zz_130_ = (3'b101);
end
2'b01 : begin
_zz_130_ = (3'b101);
end
2'b10 : begin
_zz_130_ = (3'b111);
end
default : begin
_zz_130_ = _zz_129_;
end
endcase
end
assign _zz_131_ = _zz_106_[12];
always @ (*) begin
_zz_132_[6] = _zz_131_;
_zz_132_[5] = _zz_131_;
_zz_132_[4] = _zz_131_;
_zz_132_[3] = _zz_131_;
_zz_132_[2] = _zz_131_;
_zz_132_[1] = _zz_131_;
_zz_132_[0] = _zz_131_;
end
assign IBusSimplePlugin_decompressor_inputBeforeStage_valid = (IBusSimplePlugin_decompressor_isRvc ? (IBusSimplePlugin_decompressor_bufferValid || IBusSimplePlugin_iBusRsp_output_valid) : (IBusSimplePlugin_iBusRsp_output_valid && (IBusSimplePlugin_decompressor_bufferValid || (! IBusSimplePlugin_iBusRsp_output_payload_pc[1]))));
assign IBusSimplePlugin_decompressor_inputBeforeStage_payload_pc = IBusSimplePlugin_iBusRsp_output_payload_pc;
assign IBusSimplePlugin_decompressor_inputBeforeStage_payload_isRvc = IBusSimplePlugin_decompressor_isRvc;
assign IBusSimplePlugin_decompressor_inputBeforeStage_payload_rsp_inst = (IBusSimplePlugin_decompressor_isRvc ? IBusSimplePlugin_decompressor_decompressed : IBusSimplePlugin_decompressor_raw);
assign IBusSimplePlugin_iBusRsp_output_ready = ((! IBusSimplePlugin_decompressor_inputBeforeStage_valid) || (! (((! IBusSimplePlugin_decompressor_inputBeforeStage_ready) || ((IBusSimplePlugin_decompressor_isRvc && (! IBusSimplePlugin_iBusRsp_output_payload_pc[1])) && (IBusSimplePlugin_iBusRsp_output_payload_rsp_inst[17 : 16] != (2'b11)))) || (((! IBusSimplePlugin_decompressor_isRvc) && IBusSimplePlugin_decompressor_bufferValid) && (IBusSimplePlugin_iBusRsp_output_payload_rsp_inst[17 : 16] != (2'b11))))));
assign IBusSimplePlugin_decompressor_inputBeforeStage_ready = ((1'b0 && (! IBusSimplePlugin_injector_decodeInput_valid)) || IBusSimplePlugin_injector_decodeInput_ready);
assign IBusSimplePlugin_injector_decodeInput_valid = _zz_133_;
assign IBusSimplePlugin_injector_decodeInput_payload_pc = _zz_134_;
assign IBusSimplePlugin_injector_decodeInput_payload_rsp_error = _zz_135_;
assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_136_;
assign IBusSimplePlugin_injector_decodeInput_payload_isRvc = _zz_137_;
assign _zz_83_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_decompressor_inputBeforeStage_payload_rsp_inst);
assign IBusSimplePlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck);
assign _zz_82_ = IBusSimplePlugin_decodePc_pcReg;
assign _zz_81_ = IBusSimplePlugin_injector_decodeInput_payload_rsp_inst;
assign _zz_80_ = IBusSimplePlugin_injector_decodeInput_payload_isRvc;
assign _zz_79_ = (decode_PC + _zz_243_);
assign IBusSimplePlugin_pendingCmdNext = (_zz_244_ - _zz_248_);
assign _zz_142_ = (iBus_cmd_valid && iBus_cmd_ready);
assign IBusSimplePlugin_fetchPc_output_ready = (IBusSimplePlugin_iBusRsp_input_ready && _zz_142_);
assign IBusSimplePlugin_iBusRsp_input_valid = (IBusSimplePlugin_fetchPc_output_valid && _zz_142_);
assign IBusSimplePlugin_iBusRsp_input_payload = IBusSimplePlugin_fetchPc_output_payload;
assign iBus_cmd_valid = ((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_iBusRsp_input_ready) && (IBusSimplePlugin_pendingCmd != (3'b111)));
assign iBus_cmd_payload_pc = {IBusSimplePlugin_fetchPc_output_payload[31 : 2],(2'b00)};
assign _zz_205_ = (iBus_rsp_valid && (! (IBusSimplePlugin_rsp_discardCounter != (3'b000))));
assign _zz_206_ = (IBusSimplePlugin_jump_pcLoad_valid || _zz_85_);
assign IBusSimplePlugin_rsp_fetchRsp_pc = IBusSimplePlugin_iBusRsp_inputPipeline_0_payload;
always @ (*) begin
IBusSimplePlugin_rsp_fetchRsp_rsp_error = _zz_214_;
if((! _zz_213_))begin
IBusSimplePlugin_rsp_fetchRsp_rsp_error = 1'b0;
end
end
assign IBusSimplePlugin_rsp_fetchRsp_rsp_inst = _zz_215_;
assign IBusSimplePlugin_rsp_issueDetected = 1'b0;
assign _zz_144_ = (_zz_143_ && IBusSimplePlugin_rsp_join_ready);
assign _zz_143_ = (IBusSimplePlugin_iBusRsp_inputPipeline_0_valid && _zz_213_);
always @ (*) begin
IBusSimplePlugin_iBusRsp_inputPipeline_0_ready = _zz_144_;
if((! IBusSimplePlugin_iBusRsp_inputPipeline_0_valid))begin
IBusSimplePlugin_iBusRsp_inputPipeline_0_ready = 1'b1;
end
end
assign IBusSimplePlugin_rsp_join_valid = _zz_143_;
assign IBusSimplePlugin_rsp_join_payload_pc = IBusSimplePlugin_rsp_fetchRsp_pc;
assign IBusSimplePlugin_rsp_join_payload_rsp_error = IBusSimplePlugin_rsp_fetchRsp_rsp_error;
assign IBusSimplePlugin_rsp_join_payload_rsp_inst = IBusSimplePlugin_rsp_fetchRsp_rsp_inst;
assign IBusSimplePlugin_rsp_join_payload_isRvc = IBusSimplePlugin_rsp_fetchRsp_isRvc;
assign _zz_145_ = (! IBusSimplePlugin_rsp_issueDetected);
assign IBusSimplePlugin_rsp_join_ready = (IBusSimplePlugin_iBusRsp_output_ready && _zz_145_);
assign IBusSimplePlugin_iBusRsp_output_valid = (IBusSimplePlugin_rsp_join_valid && _zz_145_);
assign IBusSimplePlugin_iBusRsp_output_payload_pc = IBusSimplePlugin_rsp_join_payload_pc;
assign IBusSimplePlugin_iBusRsp_output_payload_rsp_error = IBusSimplePlugin_rsp_join_payload_rsp_error;
assign IBusSimplePlugin_iBusRsp_output_payload_rsp_inst = IBusSimplePlugin_rsp_join_payload_rsp_inst;
assign IBusSimplePlugin_iBusRsp_output_payload_isRvc = IBusSimplePlugin_rsp_join_payload_isRvc;
assign dBus_cmd_valid = ((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_removeIt)) && (! execute_ALIGNEMENT_FAULT));
assign dBus_cmd_payload_wr = execute_INSTRUCTION[5];
assign dBus_cmd_payload_address = execute_SRC_ADD;
assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12];
always @ (*) begin
case(dBus_cmd_payload_size)
2'b00 : begin
_zz_146_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]};
end
2'b01 : begin
_zz_146_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]};
end
default : begin
_zz_146_ = execute_RS2[31 : 0];
end
endcase
end
assign dBus_cmd_payload_data = _zz_146_;
assign _zz_77_ = dBus_cmd_payload_address[1 : 0];
always @ (*) begin
case(dBus_cmd_payload_size)
2'b00 : begin
_zz_147_ = (4'b0001);
end
2'b01 : begin
_zz_147_ = (4'b0011);
end
default : begin
_zz_147_ = (4'b1111);
end
endcase
end
assign execute_DBusSimplePlugin_formalMask = (_zz_147_ <<< dBus_cmd_payload_address[1 : 0]);
assign _zz_76_ = dBus_rsp_data;
always @ (*) begin
writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA;
case(writeBack_MEMORY_ADDRESS_LOW)
2'b01 : begin
writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8];
end
2'b10 : begin
writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16];
end
2'b11 : begin
writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24];
end
default : begin
end
endcase
end
assign _zz_148_ = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14]));
always @ (*) begin
_zz_149_[31] = _zz_148_;
_zz_149_[30] = _zz_148_;
_zz_149_[29] = _zz_148_;
_zz_149_[28] = _zz_148_;
_zz_149_[27] = _zz_148_;
_zz_149_[26] = _zz_148_;
_zz_149_[25] = _zz_148_;
_zz_149_[24] = _zz_148_;
_zz_149_[23] = _zz_148_;
_zz_149_[22] = _zz_148_;
_zz_149_[21] = _zz_148_;
_zz_149_[20] = _zz_148_;
_zz_149_[19] = _zz_148_;
_zz_149_[18] = _zz_148_;
_zz_149_[17] = _zz_148_;
_zz_149_[16] = _zz_148_;
_zz_149_[15] = _zz_148_;
_zz_149_[14] = _zz_148_;
_zz_149_[13] = _zz_148_;
_zz_149_[12] = _zz_148_;
_zz_149_[11] = _zz_148_;
_zz_149_[10] = _zz_148_;
_zz_149_[9] = _zz_148_;
_zz_149_[8] = _zz_148_;
_zz_149_[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0];
end
assign _zz_150_ = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14]));
always @ (*) begin
_zz_151_[31] = _zz_150_;
_zz_151_[30] = _zz_150_;
_zz_151_[29] = _zz_150_;
_zz_151_[28] = _zz_150_;
_zz_151_[27] = _zz_150_;
_zz_151_[26] = _zz_150_;
_zz_151_[25] = _zz_150_;
_zz_151_[24] = _zz_150_;
_zz_151_[23] = _zz_150_;
_zz_151_[22] = _zz_150_;
_zz_151_[21] = _zz_150_;
_zz_151_[20] = _zz_150_;
_zz_151_[19] = _zz_150_;
_zz_151_[18] = _zz_150_;
_zz_151_[17] = _zz_150_;
_zz_151_[16] = _zz_150_;
_zz_151_[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0];
end
always @ (*) begin
case(_zz_231_)
2'b00 : begin
writeBack_DBusSimplePlugin_rspFormated = _zz_149_;
end
2'b01 : begin
writeBack_DBusSimplePlugin_rspFormated = _zz_151_;
end
default : begin
writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted;
end
endcase
end
assign CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode = 1'b0;
assign execute_exception_agregat_valid = (_zz_89_ || _zz_92_);
assign _zz_152_ = {_zz_92_,_zz_89_};
assign _zz_153_ = _zz_251_[1];
assign _zz_154_ = _zz_153_;
assign execute_exception_agregat_payload_code = _zz_210_;
assign execute_exception_agregat_payload_badAddr = _zz_211_;
assign CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
always @ (*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
if(memory_arbitration_isFlushed)begin
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0;
end
end
always @ (*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
if(writeBack_arbitration_isFlushed)begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0;
end
end
assign CsrPlugin_interruptRequest = ((((CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE) || (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE)) || (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE)) && CsrPlugin_mstatus_MIE);
assign CsrPlugin_interrupt = (CsrPlugin_interruptRequest && _zz_93_);
assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && _zz_94_);
always @ (*) begin
CsrPlugin_pipelineLiberator_done = ((! ((execute_arbitration_isValid || memory_arbitration_isValid) || writeBack_arbitration_isValid)) && _zz_141_);
if(((CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute || CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory) || CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack))begin
CsrPlugin_pipelineLiberator_done = 1'b0;
end
end
assign CsrPlugin_interruptCode = ((CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE) ? (4'b1011) : _zz_254_);
assign CsrPlugin_interruptJump = (CsrPlugin_interrupt && CsrPlugin_pipelineLiberator_done);
assign contextSwitching = _zz_87_;
assign _zz_72_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000)))));
assign _zz_71_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000));
always @ (*) begin
execute_CsrPlugin_illegalAccess = (execute_arbitration_isValid && execute_IS_CSR);
execute_CsrPlugin_readData = (32'b00000000000000000000000000000000);
case("b'execute_CsrPlugin_csrAddress)
12\'b001100000000 : begin
execute_CsrPlugin_illegalAccess = 1\'b0;
execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP;
execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE;
execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE;
end
12\'b111100010001 : begin
if(execute_CSR_READ_OPCODE)begin
execute_CsrPlugin_illegalAccess = 1\'b0;
end
execute_CsrPlugin_readData[3 : 0] = (4\'b1011);
end
12\'b111100010100 : begin
if(execute_CSR_READ_OPCODE)begin
execute_CsrPlugin_illegalAccess = 1\'b0;
end
end
12\'b001101000001 : begin
execute_CsrPlugin_illegalAccess = 1\'b0;
execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc;
end
12\'b101100000000 : begin
execute_CsrPlugin_illegalAccess = 1\'b0;
execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mcycle[31 : 0];
end
12\'b101110000000 : begin
execute_CsrPlugin_illegalAccess = 1\'b0;
execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mcycle[63 : 32];
end
12\'b001101000100 : begin
execute_CsrPlugin_illegalAccess = 1\'b0;
execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP;
execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP;
execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP;
end
12\'b001100000101 : begin
execute_CsrPlugin_illegalAccess = 1\'b0;
execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtvec;
end
12\'b101100000010 : begin
execute_CsrPlugin_illegalAccess = 1\'b0;
execute_CsrPlugin_readData[31 : 0] = CsrPlugin_minstret[31 : 0];
end
12\'b111100010011 : begin
if(execute_CSR_READ_OPCODE)begin
execute_CsrPlugin_illegalAccess = 1\'b0;
end
execute_CsrPlugin_readData[5 : 0] = (6\'b100001);
end
12\'b001101000011 : begin
execute_CsrPlugin_illegalAccess = 1\'b0;
execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mbadaddr;
end
12\'b110000000000 : begin
if(execute_CSR_READ_OPCODE)begin
execute_CsrPlugin_illegalAccess = 1\'b0;
end
execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mcycle[31 : 0];
end
12\'b001100000001 : begin
execute_CsrPlugin_illegalAccess = 1\'b0;
execute_CsrPlugin_readData[31 : 30] = CsrPlugin_misa_base;
execute_CsrPlugin_readData[25 : 0] = CsrPlugin_misa_extensions;
end
12\'b001101000000 : begin
execute_CsrPlugin_illegalAccess = 1\'b0;
execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mscratch;
end
12\'b111100010010 : begin
if(execute_CSR_READ_OPCODE)begin
execute_CsrPlugin_illegalAccess = 1\'b0;
end
execute_CsrPlugin_readData[4 : 0] = (5\'b10110);
end
12\'b001100000100 : begin
execute_CsrPlugin_illegalAccess = 1\'b0;
execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE;
execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE;
execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE;
end
12\'b101110000010 : begin
execute_CsrPlugin_illegalAccess = 1\'b0;
execute_CsrPlugin_readData[31 : 0] = CsrPlugin_minstret[63 : 32];
end
12\'b001101000010 : begin
execute_CsrPlugin_illegalAccess = 1\'b0;
execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt;
execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode;
end
default : begin
end
endcase
if((_zz_91_ < execute_CsrPlugin_csrAddress[9 : 8]))begin
execute_CsrPlugin_illegalAccess = 1\'b1;
end
end
assign _zz_92_ = (execute_CsrPlugin_illegalAccess || ((execute_arbitration_isValid && (_zz_91_ == (2\'b00))) && ((execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_EBREAK) || (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_MRET))));
assign execute_CsrPlugin_writeSrc = (execute_INSTRUCTION[14] ? _zz_256_ : execute_SRC1);
always @ (*) begin
case(_zz_232_)
1\'b0 : begin
execute_CsrPlugin_writeData = execute_CsrPlugin_writeSrc;
end
default : begin
execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (memory_REGFILE_WRITE_DATA & (~ execute_CsrPlugin_writeSrc)) : (memory_REGFILE_WRITE_DATA | execute_CsrPlugin_writeSrc));
end
endcase
end
assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE);
assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE);
assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && execute_CsrPlugin_readDataRegValid);
assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_readDataRegValid));
assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20];
assign _zz_156_ = ((decode_INSTRUCTION & (32\'b00000010000000000000000000100000)) == (32\'b00000000000000000000000000100000));
assign _zz_157_ = ((decode_INSTRUCTION & (32\'b00000000000000000000000000110000)) == (32\'b00000000000000000000000000010000));
assign _zz_158_ = ((decode_INSTRUCTION & (32\'b00000000000000000000000000000100)) == (32\'b00000000000000000000000000000100));
assign _zz_159_ = ((decode_INSTRUCTION & (32\'b00000000000000000000000001000000)) == (32\'b00000000000000000000000001000000));
assign _zz_160_ = ((decode_INSTRUCTION & (32\'b00000000000000000000000000100000)) == (32\'b00000000000000000000000000000000));
assign _zz_161_ = ((decode_INSTRUCTION & (32\'b00000000000000000000000000010100)) == (32\'b00000000000000000000000000000100));
assign _zz_162_ = ((decode_INSTRUCTION & (32\'b00000000000000000001000000000000)) == (32\'b00000000000000000000000000000000));
assign _zz_163_ = ((decode_INSTRUCTION & (32\'b00000000000000000000000001010000)) == (32\'b00000000000000000000000001010000));
assign _zz_164_ = ((decode_INSTRUCTION & (32\'b00000000000000000110000000000100)) == (32\'b00000000000000000010000000000000));
assign _zz_155_ = {(_zz_161_ != (1\'b0)),{(((decode_INSTRUCTION & _zz_332_) == (32\'b00000000000000000000000001000000)) != (1\'b0)),{((_zz_333_ == _zz_334_) != (1\'b0)),{(_zz_335_ != (1\'b0)),{(_zz_336_ != _zz_337_),{_zz_338_,{_zz_339_,_zz_340_}}}}}}};
assign _zz_69_ = _zz_257_[0];
assign _zz_68_ = _zz_258_[0];
assign _zz_165_ = _zz_155_[3 : 2];
assign _zz_67_ = _zz_165_;
assign _zz_66_ = _zz_259_[0];
assign _zz_65_ = _zz_260_[0];
assign _zz_64_ = _zz_261_[0];
assign _zz_63_ = _zz_262_[0];
assign _zz_166_ = _zz_155_[9 : 8];
assign _zz_62_ = _zz_166_;
assign _zz_61_ = _zz_263_[0];
assign _zz_60_ = _zz_264_[0];
assign _zz_59_ = _zz_265_[0];
assign _zz_167_ = _zz_155_[14 : 13];
assign _zz_58_ = _zz_167_;
assign _zz_57_ = _zz_266_[0];
assign _zz_168_ = _zz_155_[17 : 16];
assign _zz_56_ = _zz_168_;
assign _zz_55_ = _zz_267_[0];
assign _zz_54_ = _zz_268_[0];
assign _zz_53_ = _zz_269_[0];
assign _zz_169_ = _zz_155_[22 : 21];
assign _zz_52_ = _zz_169_;
assign _zz_51_ = _zz_270_[0];
assign _zz_170_ = _zz_155_[26 : 24];
assign _zz_50_ = _zz_170_;
assign _zz_171_ = _zz_155_[28 : 27];
assign _zz_49_ = _zz_171_;
assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15];
assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20];
assign decode_RegFilePlugin_rs1Data = _zz_207_;
assign decode_RegFilePlugin_rs2Data = _zz_208_;
assign _zz_48_ = decode_RegFilePlugin_rs1Data;
assign _zz_47_ = decode_RegFilePlugin_rs2Data;
always @ (*) begin
writeBack_RegFilePlugin_regFileWrite_valid = (_zz_45_ && writeBack_arbitration_isFiring);
if(_zz_172_)begin
writeBack_RegFilePlugin_regFileWrite_valid = 1\'b1;
end
end
assign writeBack_RegFilePlugin_regFileWrite_payload_address = _zz_44_[11 : 7];
assign writeBack_RegFilePlugin_regFileWrite_payload_data = _zz_75_;
always @ (*) begin
case(execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2);
end
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2);
end
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2);
end
default : begin
execute_IntAluPlugin_bitwise = execute_SRC1;
end
endcase
end
always @ (*) begin
case(execute_ALU_CTRL)
`AluCtrlEnum_defaultEncoding_BITWISE : begin
_zz_173_ = execute_IntAluPlugin_bitwise;
end
`AluCtrlEnum_defaultEncoding_SLT_SLTU : begin
_zz_173_ = {31\'d0, _zz_271_};
end
default : begin
_zz_173_ = execute_SRC_ADD_SUB;
end
endcase
end
assign _zz_42_ = _zz_173_;
always @ (*) begin
case(decode_SRC1_CTRL)
`Src1CtrlEnum_defaultEncoding_RS : begin
_zz_174_ = _zz_38_;
end
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin
_zz_174_ = {29\'d0, _zz_272_};
end
default : begin
_zz_174_ = {decode_INSTRUCTION[31 : 12],(12\'b000000000000)};
end
endcase
end
assign _zz_40_ = _zz_174_;
assign _zz_175_ = _zz_273_[11];
always @ (*) begin
_zz_176_[19] = _zz_175_;
_zz_176_[18] = _zz_175_;
_zz_176_[17] = _zz_175_;
_zz_176_[16] = _zz_175_;
_zz_176_[15] = _zz_175_;
_zz_176_[14] = _zz_175_;
_zz_176_[13] = _zz_175_;
_zz_176_[12] = _zz_175_;
_zz_176_[11] = _zz_175_;
_zz_176_[10] = _zz_175_;
_zz_176_[9] = _zz_175_;
_zz_176_[8] = _zz_175_;
_zz_176_[7] = _zz_175_;
_zz_176_[6] = _zz_175_;
_zz_176_[5] = _zz_175_;
_zz_176_[4] = _zz_175_;
_zz_176_[3] = _zz_175_;
_zz_176_[2] = _zz_175_;
_zz_176_[1] = _zz_175_;
_zz_176_[0] = _zz_175_;
end
assign _zz_177_ = _zz_274_[11];
always @ (*) begin
_zz_178_[19] = _zz_177_;
_zz_178_[18] = _zz_177_;
_zz_178_[17] = _zz_177_;
_zz_178_[16] = _zz_177_;
_zz_178_[15] = _zz_177_;
_zz_178_[14] = _zz_177_;
_zz_178_[13] = _zz_177_;
_zz_178_[12] = _zz_177_;
_zz_178_[11] = _zz_177_;
_zz_178_[10] = _zz_177_;
_zz_178_[9] = _zz_177_;
_zz_178_[8] = _zz_177_;
_zz_178_[7] = _zz_177_;
_zz_178_[6] = _zz_177_;
_zz_178_[5] = _zz_177_;
_zz_178_[4] = _zz_177_;
_zz_178_[3] = _zz_177_;
_zz_178_[2] = _zz_177_;
_zz_178_[1] = _zz_177_;
_zz_178_[0] = _zz_177_;
end
always @ (*) begin
case(decode_SRC2_CTRL)
`Src2CtrlEnum_defaultEncoding_RS : begin
_zz_179_ = _zz_35_;
end
`Src2CtrlEnum_defaultEncoding_IMI : begin
_zz_179_ = {_zz_176_,decode_INSTRUCTION[31 : 20]};
end
`Src2CtrlEnum_defaultEncoding_IMS : begin
_zz_179_ = {_zz_178_,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}};
end
default : begin
_zz_179_ = _zz_34_;
end
endcase
end
assign _zz_37_ = _zz_179_;
assign execute_SrcPlugin_addSub = _zz_275_;
assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31]));
assign _zz_33_ = execute_SrcPlugin_addSub;
assign _zz_32_ = execute_SrcPlugin_addSub;
assign _zz_31_ = execute_SrcPlugin_less;
assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1);
assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]);
assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1);
assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == (4\'b0000));
always @ (*) begin
case(execute_SHIFT_CTRL)
`ShiftCtrlEnum_defaultEncoding_SLL_1 : begin
_zz_180_ = (execute_LightShifterPlugin_shiftInput <<< 1);
end
default : begin
_zz_180_ = _zz_283_;
end
endcase
end
always @ (*) begin
_zz_181_ = 1\'b0;
_zz_182_ = 1\'b0;
if(_zz_183_)begin
if((_zz_184_ == decode_INSTRUCTION[19 : 15]))begin
_zz_181_ = 1\'b1;
end
if((_zz_184_ == decode_INSTRUCTION[24 : 20]))begin
_zz_182_ = 1\'b1;
end
end
if((writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID))begin
if((1\'b1 || (! 1\'b1)))begin
if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin
_zz_181_ = 1\'b1;
end
if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin
_zz_182_ = 1\'b1;
end
end
end
if((memory_arbitration_isValid && memory_REGFILE_WRITE_VALID))begin
if((1\'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)))begin
if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin
_zz_181_ = 1\'b1;
end
if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin
_zz_182_ = 1\'b1;
end
end
end
if((execute_arbitration_isValid && execute_REGFILE_WRITE_VALID))begin
if((1\'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)))begin
if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin
_zz_181_ = 1\'b1;
end
if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin
_zz_182_ = 1\'b1;
end
end
end
if((! decode_RS1_USE))begin
_zz_181_ = 1\'b0;
end
if((! decode_RS2_USE))begin
_zz_182_ = 1\'b0;
end
end
assign execute_MulPlugin_a = execute_SRC1;
assign execute_MulPlugin_b = execute_SRC2;
always @ (*) begin
case(_zz_233_)
2\'b01 : begin
execute_MulPlugin_aSigned = 1\'b1;
execute_MulPlugin_bSigned = 1\'b1;
end
2\'b10 : begin
execute_MulPlugin_aSigned = 1\'b1;
execute_MulPlugin_bSigned = 1\'b0;
end
default : begin
execute_MulPlugin_aSigned = 1\'b0;
execute_MulPlugin_bSigned = 1\'b0;
end
endcase
end
assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0];
assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0];
assign execute_MulPlugin_aSLow = {1\'b0,execute_MulPlugin_a[15 : 0]};
assign execute_MulPlugin_bSLow = {1\'b0,execute_MulPlugin_b[15 : 0]};
assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]};
assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]};
assign _zz_29_ = (execute_MulPlugin_aULow * execute_MulPlugin_bULow);
assign _zz_28_ = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh));
assign _zz_27_ = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow));
assign _zz_26_ = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh));
assign _zz_25_ = ($signed(_zz_285_) + $signed(_zz_293_));
assign writeBack_MulPlugin_result = ($signed(_zz_294_) + $signed(_zz_295_));
always @ (*) begin
memory_DivPlugin_div_counter_willClear = 1\'b0;
if(_zz_225_)begin
memory_DivPlugin_div_counter_willClear = 1\'b1;
end
end
assign memory_DivPlugin_div_willOverflowIfInc = (memory_DivPlugin_div_counter_value == (6\'b100001));
assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement);
always @ (*) begin
if(memory_DivPlugin_div_counter_willOverflow)begin
memory_DivPlugin_div_counter_valueNext = (6\'b000000);
end else begin
memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_299_);
end
if(memory_DivPlugin_div_counter_willClear)begin
memory_DivPlugin_div_counter_valueNext = (6\'b000000);
end
end
assign _zz_185_ = memory_DivPlugin_rs1[31 : 0];
assign _zz_186_ = {memory_DivPlugin_accumulator[31 : 0],_zz_185_[31]};
assign _zz_187_ = (_zz_186_ - _zz_300_);
assign _zz_188_ = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]);
assign _zz_189_ = (execute_RS2[31] && execute_IS_RS2_SIGNED);
assign _zz_190_ = (1\'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED));
always @ (*) begin
_zz_191_[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]);
_zz_191_[31 : 0] = execute_RS1;
end
assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2);
assign _zz_192_ = execute_INSTRUCTION[14 : 12];
always @ (*) begin
if((_zz_192_ == (3\'b000))) begin
_zz_193_ = execute_BranchPlugin_eq;
end else if((_zz_192_ == (3\'b001))) begin
_zz_193_ = (! execute_BranchPlugin_eq);
end else if((((_zz_192_ & (3\'b101)) == (3\'b101)))) begin
_zz_193_ = (! execute_SRC_LESS);
end else begin
_zz_193_ = execute_SRC_LESS;
end
end
always @ (*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_defaultEncoding_INC : begin
_zz_194_ = 1\'b0;
end
`BranchCtrlEnum_defaultEncoding_JAL : begin
_zz_194_ = 1\'b1;
end
`BranchCtrlEnum_defaultEncoding_JALR : begin
_zz_194_ = 1\'b1;
end
default : begin
_zz_194_ = _zz_193_;
end
endcase
end
assign _zz_23_ = _zz_194_;
assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC);
assign _zz_195_ = _zz_313_[19];
always @ (*) begin
_zz_196_[10] = _zz_195_;
_zz_196_[9] = _zz_195_;
_zz_196_[8] = _zz_195_;
_zz_196_[7] = _zz_195_;
_zz_196_[6] = _zz_195_;
_zz_196_[5] = _zz_195_;
_zz_196_[4] = _zz_195_;
_zz_196_[3] = _zz_195_;
_zz_196_[2] = _zz_195_;
_zz_196_[1] = _zz_195_;
_zz_196_[0] = _zz_195_;
end
assign _zz_197_ = _zz_314_[11];
always @ (*) begin
_zz_198_[19] = _zz_197_;
_zz_198_[18] = _zz_197_;
_zz_198_[17] = _zz_197_;
_zz_198_[16] = _zz_197_;
_zz_198_[15] = _zz_197_;
_zz_198_[14] = _zz_197_;
_zz_198_[13] = _zz_197_;
_zz_198_[12] = _zz_197_;
_zz_198_[11] = _zz_197_;
_zz_198_[10] = _zz_197_;
_zz_198_[9] = _zz_197_;
_zz_198_[8] = _zz_197_;
_zz_198_[7] = _zz_197_;
_zz_198_[6] = _zz_197_;
_zz_198_[5] = _zz_197_;
_zz_198_[4] = _zz_197_;
_zz_198_[3] = _zz_197_;
_zz_198_[2] = _zz_197_;
_zz_198_[1] = _zz_197_;
_zz_198_[0] = _zz_197_;
end
assign _zz_199_ = _zz_315_[11];
always @ (*) begin
_zz_200_[18] = _zz_199_;
_zz_200_[17] = _zz_199_;
_zz_200_[16] = _zz_199_;
_zz_200_[15] = _zz_199_;
_zz_200_[14] = _zz_199_;
_zz_200_[13] = _zz_199_;
_zz_200_[12] = _zz_199_;
_zz_200_[11] = _zz_199_;
_zz_200_[10] = _zz_199_;
_zz_200_[9] = _zz_199_;
_zz_200_[8] = _zz_199_;
_zz_200_[7] = _zz_199_;
_zz_200_[6] = _zz_199_;
_zz_200_[5] = _zz_199_;
_zz_200_[4] = _zz_199_;
_zz_200_[3] = _zz_199_;
_zz_200_[2] = _zz_199_;
_zz_200_[1] = _zz_199_;
_zz_200_[0] = _zz_199_;
end
always @ (*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_defaultEncoding_JAL : begin
_zz_201_ = {{_zz_196_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1\'b0};
end
`BranchCtrlEnum_defaultEncoding_JALR : begin
_zz_201_ = {_zz_198_,execute_INSTRUCTION[31 : 20]};
end
default : begin
_zz_201_ = {{_zz_200_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1\'b0};
end
endcase
end
assign execute_BranchPlugin_branch_src2 = _zz_201_;
assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2);
assign _zz_21_ = {execute_BranchPlugin_branchAdder[31 : 1],((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? 1\'b0 : execute_BranchPlugin_branchAdder[0])};
assign _zz_95_ = (memory_arbitration_isFiring && memory_BRANCH_DO);
assign _zz_96_ = memory_BRANCH_CALC;
assign DebugPlugin_isPipBusy = (DebugPlugin_isPipActive || DebugPlugin_isPipActive_regNext);
always @ (*) begin
debug_bus_cmd_ready = 1\'b1;
_zz_97_ = 1\'b0;
if(debug_bus_cmd_valid)begin
case(_zz_226_)
1\'b0 : begin
end
default : begin
if(debug_bus_cmd_payload_wr)begin
_zz_97_ = 1\'b1;
debug_bus_cmd_ready = _zz_98_;
end
end
endcase
end
end
always @ (*) begin
debug_bus_rsp_data = DebugPlugin_busReadDataReg;
if((! _zz_202_))begin
debug_bus_rsp_data[0] = DebugPlugin_resetIt;
debug_bus_rsp_data[1] = DebugPlugin_haltIt;
debug_bus_rsp_data[2] = DebugPlugin_isPipBusy;
debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak;
debug_bus_rsp_data[4] = DebugPlugin_stepIt;
end
end
assign debug_resetOut = DebugPlugin_resetIt_regNext;
assign _zz_20_ = decode_BRANCH_CTRL;
assign _zz_18_ = _zz_49_;
assign _zz_22_ = decode_to_execute_BRANCH_CTRL;
assign _zz_17_ = decode_SHIFT_CTRL;
assign _zz_15_ = _zz_56_;
assign _zz_30_ = decode_to_execute_SHIFT_CTRL;
assign _zz_36_ = _zz_58_;
assign _zz_14_ = decode_ALU_BITWISE_CTRL;
assign _zz_12_ = _zz_67_;
assign _zz_43_ = decode_to_execute_ALU_BITWISE_CTRL;
assign _zz_39_ = _zz_62_;
assign _zz_11_ = decode_ALU_CTRL;
assign _zz_9_ = _zz_52_;
assign _zz_41_ = decode_to_execute_ALU_CTRL;
assign _zz_8_ = decode_ENV_CTRL;
assign _zz_5_ = execute_ENV_CTRL;
assign _zz_3_ = memory_ENV_CTRL;
assign _zz_6_ = _zz_50_;
assign _zz_73_ = decode_to_execute_ENV_CTRL;
assign _zz_1_ = execute_to_memory_ENV_CTRL;
assign _zz_74_ = memory_to_writeBack_ENV_CTRL;
assign decode_arbitration_isFlushed = (((decode_arbitration_flushAll || execute_arbitration_flushAll) || memory_arbitration_flushAll) || writeBack_arbitration_flushAll);
assign execute_arbitration_isFlushed = ((execute_arbitration_flushAll || memory_arbitration_flushAll) || writeBack_arbitration_flushAll);
assign memory_arbitration_isFlushed = (memory_arbitration_flushAll || writeBack_arbitration_flushAll);
assign writeBack_arbitration_isFlushed = writeBack_arbitration_flushAll;
assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1\'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers);
assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt));
assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1\'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers);
assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt));
assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1\'b0 || writeBack_arbitration_isStuck));
assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers);
assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));
assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt));
assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1\'b0);
assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers);
assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt));
assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt));
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
_zz_91_ <= (2\'b11);
IBusSimplePlugin_fetchPc_pcReg <= (32\'b10000000000000000000000000000000);
_zz_102_ <= 1\'b0;
IBusSimplePlugin_decodePc_pcReg <= (32\'b10000000000000000000000000000000);
_zz_104_ <= 1\'b0;
IBusSimplePlugin_decompressor_bufferValid <= 1\'b0;
_zz_133_ <= 1\'b0;
_zz_138_ <= 1\'b0;
_zz_139_ <= 1\'b0;
_zz_140_ <= 1\'b0;
_zz_141_ <= 1\'b0;
IBusSimplePlugin_injector_decodeRemoved <= 1\'b0;
IBusSimplePlugin_pendingCmd <= (3\'b000);
IBusSimplePlugin_rsp_discardCounter <= (3\'b000);
CsrPlugin_misa_base <= (2\'b01);
CsrPlugin_misa_extensions <= (26\'b00000000000000000001000010);
CsrPlugin_mtvec <= (32\'b10000000000000000000000000100000);
CsrPlugin_mstatus_MIE <= 1\'b0;
CsrPlugin_mstatus_MPIE <= 1\'b0;
CsrPlugin_mstatus_MPP <= (2\'b11);
CsrPlugin_mip_MEIP <= 1\'b0;
CsrPlugin_mip_MTIP <= 1\'b0;
CsrPlugin_mip_MSIP <= 1\'b0;
CsrPlugin_mie_MEIE <= 1\'b0;
CsrPlugin_mie_MTIE <= 1\'b0;
CsrPlugin_mie_MSIE <= 1\'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1\'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1\'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1\'b0;
CsrPlugin_writeBackWasWfi <= 1\'b0;
_zz_172_ <= 1\'b1;
execute_LightShifterPlugin_isActive <= 1\'b0;
_zz_183_ <= 1\'b0;
memory_DivPlugin_div_counter_value <= (6\'b000000);
execute_arbitration_isValid <= 1\'b0;
memory_arbitration_isValid <= 1\'b0;
writeBack_arbitration_isValid <= 1\'b0;
_zz_204_ <= (3\'b000);
memory_to_writeBack_REGFILE_WRITE_DATA <= (32\'b00000000000000000000000000000000);
memory_to_writeBack_INSTRUCTION <= (32\'b00000000000000000000000000000000);
end else begin
if((IBusSimplePlugin_fetchPc_preOutput_valid && IBusSimplePlugin_fetchPc_preOutput_ready))begin
IBusSimplePlugin_fetchPc_pcReg <= IBusSimplePlugin_fetchPc_pcPlus4;
end
if((IBusSimplePlugin_fetchPc_preOutput_valid && IBusSimplePlugin_fetchPc_preOutput_ready))begin
IBusSimplePlugin_fetchPc_pcReg[1 : 0] <= (2\'b00);
end
_zz_102_ <= 1\'b1;
if(IBusSimplePlugin_jump_pcLoad_valid)begin
IBusSimplePlugin_fetchPc_pcReg <= IBusSimplePlugin_jump_pcLoad_payload;
end
if((decode_arbitration_isFiring && (! IBusSimplePlugin_decodePc_injectedDecode)))begin
IBusSimplePlugin_decodePc_pcReg <= IBusSimplePlugin_decodePc_pcPlus;
end
if(IBusSimplePlugin_jump_pcLoad_valid)begin
IBusSimplePlugin_decodePc_pcReg <= IBusSimplePlugin_jump_pcLoad_payload;
end
if(IBusSimplePlugin_iBusRsp_input_ready)begin
_zz_104_ <= IBusSimplePlugin_iBusRsp_input_valid;
end
if((IBusSimplePlugin_jump_pcLoad_valid || _zz_85_))begin
_zz_104_ <= 1\'b0;
end
if((IBusSimplePlugin_decompressor_inputBeforeStage_valid && IBusSimplePlugin_decompressor_inputBeforeStage_ready))begin
IBusSimplePlugin_decompressor_bufferValid <= 1\'b0;
end
if(_zz_227_)begin
IBusSimplePlugin_decompressor_bufferValid <= ((! (((! IBusSimplePlugin_decompressor_isRvc) && (! IBusSimplePlugin_iBusRsp_output_payload_pc[1])) && (! IBusSimplePlugin_decompressor_bufferValid))) && (! ((IBusSimplePlugin_decompressor_isRvc && IBusSimplePlugin_iBusRsp_output_payload_pc[1]) && IBusSimplePlugin_decompressor_inputBeforeStage_ready)));
end
if((IBusSimplePlugin_jump_pcLoad_valid || _zz_85_))begin
IBusSimplePlugin_decompressor_bufferValid <= 1\'b0;
end
if(IBusSimplePlugin_decompressor_inputBeforeStage_ready)begin
_zz_133_ <= IBusSimplePlugin_decompressor_inputBeforeStage_valid;
end
if((IBusSimplePlugin_jump_pcLoad_valid || _zz_85_))begin
_zz_133_ <= 1\'b0;
end
if((! 1\'b0))begin
_zz_138_ <= 1\'b1;
end
if((IBusSimplePlugin_jump_pcLoad_valid || _zz_85_))begin
_zz_138_ <= 1\'b0;
end
if((! execute_arbitration_isStuck))begin
_zz_139_ <= _zz_138_;
end
if((IBusSimplePlugin_jump_pcLoad_valid || _zz_85_))begin
_zz_139_ <= 1\'b0;
end
if((! memory_arbitration_isStuck))begin
_zz_140_ <= _zz_139_;
end
if((IBusSimplePlugin_jump_pcLoad_valid || _zz_85_))begin
_zz_140_ <= 1\'b0;
end
if((! writeBack_arbitration_isStuck))begin
_zz_141_ <= _zz_140_;
end
if((IBusSimplePlugin_jump_pcLoad_valid || _zz_85_))begin
_zz_141_ <= 1\'b0;
end
if(decode_arbitration_removeIt)begin
IBusSimplePlugin_injector_decodeRemoved <= 1\'b1;
end
if((IBusSimplePlugin_jump_pcLoad_valid || _zz_85_))begin
IBusSimplePlugin_injector_decodeRemoved <= 1\'b0;
end
IBusSimplePlugin_pendingCmd <= IBusSimplePlugin_pendingCmdNext;
IBusSimplePlugin_rsp_discardCounter <= (IBusSimplePlugin_rsp_discardCounter - _zz_250_);
if((IBusSimplePlugin_jump_pcLoad_valid || _zz_85_))begin
IBusSimplePlugin_rsp_discardCounter <= IBusSimplePlugin_pendingCmdNext;
end
CsrPlugin_mip_MEIP <= externalInterrupt;
CsrPlugin_mip_MTIP <= timerInterrupt;
if((! execute_arbitration_isStuck))begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1\'b0;
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
end
if((! memory_arbitration_isStuck))begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
end
if((! writeBack_arbitration_isStuck))begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack;
end
CsrPlugin_writeBackWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI));
if(_zz_219_)begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1\'b0;
CsrPlugin_mstatus_MIE <= 1\'b0;
CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE;
CsrPlugin_mstatus_MPP <= _zz_91_;
end
if(_zz_220_)begin
if(! _zz_221_) begin
CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE;
_zz_91_ <= CsrPlugin_mstatus_MPP;
end
end
_zz_172_ <= 1\'b0;
if(_zz_222_)begin
if(_zz_223_)begin
execute_LightShifterPlugin_isActive <= 1\'b1;
if(execute_LightShifterPlugin_done)begin
execute_LightShifterPlugin_isActive <= 1\'b0;
end
end
end
if(execute_arbitration_removeIt)begin
execute_LightShifterPlugin_isActive <= 1\'b0;
end
_zz_183_ <= (_zz_45_ && writeBack_arbitration_isFiring);
memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext;
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_24_;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION;
end
if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin
execute_arbitration_isValid <= 1\'b0;
end
if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin
execute_arbitration_isValid <= decode_arbitration_isValid;
end
if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin
memory_arbitration_isValid <= 1\'b0;
end
if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin
memory_arbitration_isValid <= execute_arbitration_isValid;
end
if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin
writeBack_arbitration_isValid <= 1\'b0;
end
if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin
writeBack_arbitration_isValid <= memory_arbitration_isValid;
end
case(_zz_204_)
3\'b000 : begin
if(_zz_97_)begin
_zz_204_ <= (3\'b001);
end
end
3\'b001 : begin
_zz_204_ <= (3\'b010);
end
3\'b010 : begin
_zz_204_ <= (3\'b011);
end
3\'b011 : begin
if((! decode_arbitration_isStuck))begin
_zz_204_ <= (3\'b100);
end
end
3\'b100 : begin
_zz_204_ <= (3\'b000);
end
default : begin
end
endcase
case(execute_CsrPlugin_csrAddress)
12\'b001100000000 : begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11];
CsrPlugin_mstatus_MPIE <= _zz_316_[0];
CsrPlugin_mstatus_MIE <= _zz_317_[0];
end
end
12\'b111100010001 : begin
end
12\'b111100010100 : begin
end
12\'b001101000001 : begin
end
12\'b101100000000 : begin
end
12\'b101110000000 : begin
end
12\'b001101000100 : begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_mip_MSIP <= _zz_318_[0];
end
end
12\'b001100000101 : begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_mtvec <= execute_CsrPlugin_writeData[31 : 0];
end
end
12\'b101100000010 : begin
end
12\'b111100010011 : begin
end
12\'b001101000011 : begin
end
12\'b110000000000 : begin
end
12\'b001100000001 : begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_misa_base <= execute_CsrPlugin_writeData[31 : 30];
CsrPlugin_misa_extensions <= execute_CsrPlugin_writeData[25 : 0];
end
end
12\'b001101000000 : begin
end
12\'b111100010010 : begin
end
12\'b001100000100 : begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_mie_MEIE <= _zz_319_[0];
CsrPlugin_mie_MTIE <= _zz_320_[0];
CsrPlugin_mie_MSIE <= _zz_321_[0];
end
end
12\'b101110000010 : begin
end
12\'b001101000010 : begin
end
default : begin
end
endcase
end
end
always @ (posedge io_mainClk) begin
if(IBusSimplePlugin_iBusRsp_input_ready)begin
_zz_105_ <= IBusSimplePlugin_iBusRsp_input_payload;
end
if(_zz_227_)begin
IBusSimplePlugin_decompressor_bufferData <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst[31 : 16];
end
if(IBusSimplePlugin_decompressor_inputBeforeStage_ready)begin
_zz_134_ <= IBusSimplePlugin_decompressor_inputBeforeStage_payload_pc;
_zz_135_ <= IBusSimplePlugin_decompressor_inputBeforeStage_payload_rsp_error;
_zz_136_ <= IBusSimplePlugin_decompressor_inputBeforeStage_payload_rsp_inst;
_zz_137_ <= IBusSimplePlugin_decompressor_inputBeforeStage_payload_isRvc;
end
if(IBusSimplePlugin_injector_decodeInput_ready)begin
IBusSimplePlugin_injector_formal_rawInDecode <= IBusSimplePlugin_decompressor_raw;
end
`ifndef SYNTHESIS
if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin
$display("ERROR DBusSimplePlugin doesn\'t allow memory stage stall when read happend");
end
`endif
`ifndef SYNTHESIS
if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_INSTRUCTION[5])) && writeBack_arbitration_isStuck))) begin
$display("ERROR DBusSimplePlugin doesn\'t allow writeback stage stall when read happend");
end
`endif
CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64\'b0000000000000000000000000000000000000000000000000000000000000001));
if(writeBack_arbitration_isFiring)begin
CsrPlugin_minstret <= (CsrPlugin_minstret + (64\'b0000000000000000000000000000000000000000000000000000000000000001));
end
if(execute_exception_agregat_valid)begin
if((! ((1\'b0 || CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory) || CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack)))begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= execute_exception_agregat_payload_code;
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= execute_exception_agregat_payload_badAddr;
end
end
if(_zz_219_)begin
CsrPlugin_mepc <= writeBack_PC;
CsrPlugin_mcause_interrupt <= CsrPlugin_interruptJump;
CsrPlugin_mcause_exceptionCode <= CsrPlugin_interruptCode;
end
CsrPlugin_exception_regNext <= CsrPlugin_exception;
if(CsrPlugin_exception_regNext)begin
CsrPlugin_mbadaddr <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
CsrPlugin_mcause_exceptionCode <= CsrPlugin_exceptionPortCtrl_exceptionContext_code;
end
if(execute_arbitration_isValid)begin
execute_CsrPlugin_readDataRegValid <= 1\'b1;
end
if((! execute_arbitration_isStuck))begin
execute_CsrPlugin_readDataRegValid <= 1\'b0;
end
if(_zz_222_)begin
if(_zz_223_)begin
execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - (5\'b00001));
end
end
_zz_184_ <= _zz_44_[11 : 7];
if(_zz_217_)begin
if(_zz_218_)begin
memory_DivPlugin_rs1[31 : 0] <= _zz_301_[31:0];
memory_DivPlugin_accumulator[31 : 0] <= ((! _zz_187_[32]) ? _zz_302_ : _zz_303_);
if((memory_DivPlugin_div_counter_value == (6\'b100000)))begin
memory_DivPlugin_div_result <= _zz_304_[31:0];
end
end
end
if(_zz_225_)begin
memory_DivPlugin_accumulator <= (65\'b00000000000000000000000000000000000000000000000000000000000000000);
memory_DivPlugin_rs1 <= ((_zz_190_ ? (~ _zz_191_) : _zz_191_) + _zz_310_);
memory_DivPlugin_rs2 <= ((_zz_189_ ? (~ execute_RS2) : execute_RS2) + _zz_312_);
memory_DivPlugin_div_needRevert <= (_zz_190_ ^ (_zz_189_ && (! execute_INSTRUCTION[13])));
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_BRANCH_CTRL <= _zz_19_;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_MUL_HL <= execute_MUL_HL;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_IS_CSR <= decode_IS_CSR;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_SRC2 <= decode_SRC2;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_SHIFT_CTRL <= _zz_16_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_MUL_LOW <= memory_MUL_LOW;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_REGFILE_WRITE_DATA <= _zz_70_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_PC <= _zz_34_;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_PC <= execute_PC;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_PC <= memory_PC;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_BRANCH_DO <= execute_BRANCH_DO;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_IS_MUL <= decode_IS_MUL;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_IS_MUL <= execute_IS_MUL;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_IS_MUL <= memory_IS_MUL;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_MUL_LL <= execute_MUL_LL;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_MUL_LH <= execute_MUL_LH;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_IS_EBREAK <= decode_IS_EBREAK;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_IS_DIV <= decode_IS_DIV;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_IS_DIV <= execute_IS_DIV;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_FORMAL_PC_NEXT <= _zz_78_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_RS2 <= _zz_35_;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_ALU_BITWISE_CTRL <= _zz_13_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_ALU_CTRL <= _zz_10_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_ENV_CTRL <= _zz_7_;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_ENV_CTRL <= _zz_4_;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_ENV_CTRL <= _zz_2_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_SRC1 <= decode_SRC1;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_MUL_HH <= execute_MUL_HH;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_MUL_HH <= memory_MUL_HH;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_INSTRUCTION <= decode_INSTRUCTION;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_INSTRUCTION <= execute_INSTRUCTION;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_RS1 <= _zz_38_;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA;
end
if((((! IBusSimplePlugin_iBusRsp_output_ready) && (IBusSimplePlugin_decompressor_inputBeforeStage_valid && IBusSimplePlugin_decompressor_inputBeforeStage_ready)) && (! (IBusSimplePlugin_jump_pcLoad_valid || _zz_85_))))begin
_zz_105_[1] <= 1\'b1;
end
if((_zz_204_ != (3\'b000)))begin
_zz_136_ <= debug_bus_cmd_payload_data;
end
case(execute_CsrPlugin_csrAddress)
12\'b001100000000 : begin
end
12\'b111100010001 : begin
end
12\'b111100010100 : begin
end
12\'b001101000001 : begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0];
end
end
12\'b101100000000 : begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_mcycle[31 : 0] <= execute_CsrPlugin_writeData[31 : 0];
end
end
12\'b101110000000 : begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_mcycle[63 : 32] <= execute_CsrPlugin_writeData[31 : 0];
end
end
12\'b001101000100 : begin
end
12\'b001100000101 : begin
end
12\'b101100000010 : begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_minstret[31 : 0] <= execute_CsrPlugin_writeData[31 : 0];
end
end
12\'b111100010011 : begin
end
12\'b001101000011 : begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_mbadaddr <= execute_CsrPlugin_writeData[31 : 0];
end
end
12\'b110000000000 : begin
end
12\'b001100000001 : begin
end
12\'b001101000000 : begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0];
end
end
12\'b111100010010 : begin
end
12\'b001100000100 : begin
end
12\'b101110000010 : begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0];
end
end
12\'b001101000010 : begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_mcause_interrupt <= _zz_322_[0];
CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0];
end
end
default : begin
end
endcase
end
always @ (posedge io_mainClk) begin
DebugPlugin_firstCycle <= 1\'b0;
if(debug_bus_cmd_ready)begin
DebugPlugin_firstCycle <= 1\'b1;
end
DebugPlugin_secondCycle <= DebugPlugin_firstCycle;
DebugPlugin_isPipActive <= (((decode_arbitration_isValid || execute_arbitration_isValid) || memory_arbitration_isValid) || writeBack_arbitration_isValid);
DebugPlugin_isPipActive_regNext <= DebugPlugin_isPipActive;
if(writeBack_arbitration_isValid)begin
DebugPlugin_busReadDataReg <= _zz_75_;
end
_zz_202_ <= debug_bus_cmd_payload_address[2];
DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt;
end
always @ (posedge io_mainClk or posedge resetCtrl_mainClkReset) begin
if (resetCtrl_mainClkReset) begin
DebugPlugin_resetIt <= 1\'b0;
DebugPlugin_haltIt <= 1\'b0;
DebugPlugin_stepIt <= 1\'b0;
DebugPlugin_haltedByBreak <= 1\'b0;
_zz_203_ <= 1\'b0;
end else begin
if(debug_bus_cmd_valid)begin
case(_zz_226_)
1\'b0 : begin
if(debug_bus_cmd_payload_wr)begin
DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4];
if(debug_bus_cmd_payload_data[16])begin
DebugPlugin_resetIt <= 1\'b1;
end
if(debug_bus_cmd_payload_data[24])begin
DebugPlugin_resetIt <= 1\'b0;
end
if(debug_bus_cmd_payload_data[17])begin
DebugPlugin_haltIt <= 1\'b1;
end
if(debug_bus_cmd_payload_data[25])begin
DebugPlugin_haltIt <= 1\'b0;
end
if(debug_bus_cmd_payload_data[25])begin
DebugPlugin_haltedByBreak <= 1\'b0;
end
end
end
default : begin
end
endcase
end
if(execute_IS_EBREAK)begin
if(execute_arbitration_isFiring)begin
DebugPlugin_haltIt <= 1\'b1;
DebugPlugin_haltedByBreak <= 1\'b1;
end
end
if(_zz_224_)begin
if(decode_arbitration_isValid)begin
DebugPlugin_haltIt <= 1\'b1;
end
end
if((DebugPlugin_stepIt && ({writeBack_arbitration_redoIt,{memory_arbitration_redoIt,{execute_arbitration_redoIt,decode_arbitration_redoIt}}} != (4\'b0000))))begin
DebugPlugin_haltIt <= 1\'b0;
end
_zz_203_ <= (DebugPlugin_stepIt && decode_arbitration_isFiring);
end
end
endmodule
module JtagBridge (
input io_jtag_tms,
input io_jtag_tdi,
output reg io_jtag_tdo,
input io_jtag_tck,
output io_remote_cmd_valid,
input io_remote_cmd_ready,
output io_remote_cmd_payload_last,
output [0:0] io_remote_cmd_payload_fragment,
input io_remote_rsp_valid,
output io_remote_rsp_ready,
input io_remote_rsp_payload_error,
input [31:0] io_remote_rsp_payload_data,
input io_mainClk,
input resetCtrl_mainClkReset);
wire _zz_2_;
wire _zz_3_;
wire [0:0] _zz_4_;
wire _zz_5_;
wire _zz_6_;
wire [3:0] _zz_7_;
wire [3:0] _zz_8_;
wire [3:0] _zz_9_;
wire system_cmd_valid;
wire system_cmd_payload_last;
wire [0:0] system_cmd_payload_fragment;
reg system_rsp_valid;
reg system_rsp_payload_error;
reg [31:0] system_rsp_payload_data;
wire `JtagState_defaultEncoding_type jtag_tap_fsm_stateNext;
reg `JtagState_defaultEncoding_type jtag_tap_fsm_state = `JtagState_defaultEncoding_RESET;
reg `JtagState_defaultEncoding_type _zz_1_;
reg [3:0] jtag_tap_instruction;
reg [3:0] jtag_tap_instructionShift;
reg jtag_tap_bypass;
wire [0:0] jtag_idcodeArea_instructionId;
wire jtag_idcodeArea_instructionHit;
reg [31:0] jtag_idcodeArea_shifter;
wire [1:0] jtag_writeArea_instructionId;
wire jtag_writeArea_instructionHit;
reg jtag_writeArea_source_valid;
wire jtag_writeArea_source_payload_last;
wire [0:0] jtag_writeArea_source_payload_fragment;
wire [1:0] jtag_readArea_instructionId;
wire jtag_readArea_instructionHit;
reg [33:0] jtag_readArea_shifter;
assign _zz_5_ = (jtag_tap_fsm_state == `JtagState_defaultEncoding_DR_SHIFT);
assign _zz_6_ = (jtag_tap_fsm_state == `JtagState_defaultEncoding_DR_SHIFT);
assign _zz_7_ = {3\'d0, jtag_idcodeArea_instructionId};
assign _zz_8_ = {2\'d0, jtag_writeArea_instructionId};
assign _zz_9_ = {2\'d0, jtag_readArea_instructionId};
FlowCCByToggle flowCCByToggle_1_ (
.io_input_valid(jtag_writeArea_source_valid),
.io_input_payload_last(jtag_writeArea_source_payload_last),
.io_input_payload_fragment(jtag_writeArea_source_payload_fragment),
.io_output_valid(_zz_2_),
.io_output_payload_last(_zz_3_),
.io_output_payload_fragment(_zz_4_),
.io_jtag_tck(io_jtag_tck),
.io_mainClk(io_mainClk),
.resetCtrl_mainClkReset(resetCtrl_mainClkReset)
);
assign io_remote_cmd_valid = system_cmd_valid;
assign io_remote_cmd_payload_last = system_cmd_payload_last;
assign io_remote_cmd_payload_fragment = system_cmd_payload_fragment;
assign io_remote_rsp_ready = 1\'b1;
always @ (*) begin
case(jtag_tap_fsm_state)
`JtagState_defaultEncoding_IDLE : begin
_zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_DR_SELECT : `JtagState_defaultEncoding_IDLE);
end
`JtagState_defaultEncoding_IR_SELECT : begin
_zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_RESET : `JtagState_defaultEncoding_IR_CAPTURE);
end
`JtagState_defaultEncoding_IR_CAPTURE : begin
_zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_IR_EXIT1 : `JtagState_defaultEncoding_IR_SHIFT);
end
`JtagState_defaultEncoding_IR_SHIFT : begin
_zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_IR_EXIT1 : `JtagState_defaultEncoding_IR_SHIFT);
end
`JtagState_defaultEncoding_IR_EXIT1 : begin
_zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_IR_UPDATE : `JtagState_defaultEncoding_IR_PAUSE);
end
`JtagState_defaultEncoding_IR_PAUSE : begin
_zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_IR_EXIT2 : `JtagState_defaultEncoding_IR_PAUSE);
end
`JtagState_defaultEncoding_IR_EXIT2 : begin
_zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_IR_UPDATE : `JtagState_defaultEncoding_IR_SHIFT);
end
`JtagState_defaultEncoding_IR_UPDATE : begin
_zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_DR_SELECT : `JtagState_defaultEncoding_IDLE);
end
`JtagState_defaultEncoding_DR_SELECT : begin
_zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_IR_SELECT : `JtagState_defaultEncoding_DR_CAPTURE);
end
`JtagState_defaultEncoding_DR_CAPTURE : begin
_zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_DR_EXIT1 : `JtagState_defaultEncoding_DR_SHIFT);
end
`JtagState_defaultEncoding_DR_SHIFT : begin
_zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_DR_EXIT1 : `JtagState_defaultEncoding_DR_SHIFT);
end
`JtagState_defaultEncoding_DR_EXIT1 : begin
_zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_DR_UPDATE : `JtagState_defaultEncoding_DR_PAUSE);
end
`JtagState_defaultEncoding_DR_PAUSE : begin
_zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_DR_EXIT2 : `JtagState_defaultEncoding_DR_PAUSE);
end
`JtagState_defaultEncoding_DR_EXIT2 : begin
_zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_DR_UPDATE : `JtagState_defaultEncoding_DR_SHIFT);
end
`JtagState_defaultEncoding_DR_UPDATE : begin
_zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_DR_SELECT : `JtagState_defaultEncoding_IDLE);
end
default : begin
_zz_1_ = (io_jtag_tms ? `JtagState_defaultEncoding_RESET : `JtagState_defaultEncoding_IDLE);
end
endcase
end
assign jtag_tap_fsm_stateNext = _zz_1_;
always @ (*) begin
io_jtag_tdo = jtag_tap_bypass;
case(jtag_tap_fsm_state)
`JtagState_defaultEncoding_IR_CAPTURE : begin
end
`JtagState_defaultEncoding_IR_SHIFT : begin
io_jtag_tdo = jtag_tap_instructionShift[0];
end
`JtagState_defaultEncoding_IR_UPDATE : begin
end
`JtagState_defaultEncoding_DR_SHIFT : begin
end
default : begin
end
endcase
if(jtag_idcodeArea_instructionHit)begin
if(_zz_5_)begin
io_jtag_tdo = jtag_idcodeArea_shifter[0];
end
end
if(jtag_readArea_instructionHit)begin
if(_zz_6_)begin
io_jtag_tdo = jtag_readArea_shifter[0];
end
end
end
assign jtag_idcodeArea_instructionId = (1\'b1);
assign jtag_idcodeArea_instructionHit = (jtag_tap_instruction == _zz_7_);
assign jtag_writeArea_instructionId = (2\'b10);
assign jtag_writeArea_instructionHit = (jtag_tap_instruction == _zz_8_);
always @ (*) begin
jtag_writeArea_source_valid = 1\'b0;
if(jtag_writeArea_instructionHit)begin
if((jtag_tap_fsm_state == `JtagState_defaultEncoding_DR_SHIFT))begin
jtag_writeArea_source_valid = 1\'b1;
end
end
end
assign jtag_writeArea_source_payload_last = io_jtag_tms;
assign jtag_writeArea_source_payload_fragment[0] = io_jtag_tdi;
assign system_cmd_valid = _zz_2_;
assign system_cmd_payload_last = _zz_3_;
assign system_cmd_payload_fragment = _zz_4_;
assign jtag_readArea_instructionId = (2\'b11);
assign jtag_readArea_instructionHit = (jtag_tap_instruction == _zz_9_);
always @ (posedge io_mainClk) begin
if(io_remote_cmd_valid)begin
system_rsp_valid <= 1\'b0;
end
if((io_remote_rsp_valid && io_remote_rsp_ready))begin
system_rsp_valid <= 1\'b1;
system_rsp_payload_error <= io_remote_rsp_payload_error;
system_rsp_payload_data <= io_remote_rsp_payload_data;
end
end
always @ (posedge io_jtag_tck) begin
jtag_tap_fsm_state <= jtag_tap_fsm_stateNext;
case(jtag_tap_fsm_state)
`JtagState_defaultEncoding_IR_CAPTURE : begin
jtag_tap_instructionShift <= jtag_tap_instruction;
end
`JtagState_defaultEncoding_IR_SHIFT : begin
jtag_tap_instructionShift <= ({io_jtag_tdi,jtag_tap_instructionShift} >>> 1);
end
`JtagState_defaultEncoding_IR_UPDATE : begin
jtag_tap_instruction <= jtag_tap_instructionShift;
end
`JtagState_defaultEncoding_DR_SHIFT : begin
jtag_tap_bypass <= io_jtag_tdi;
end
default : begin
end
endcase
if(jtag_idcodeArea_instructionHit)begin
if(_zz_5_)begin
jtag_idcodeArea_shifter <= ({io_jtag_tdi,jtag_idcodeArea_shifter} >>> 1);
end
end
if((jtag_tap_fsm_state == `JtagState_defaultEncoding_RESET))begin
jtag_idcodeArea_shifter <= (32\'b00010000000000000001111111111111);
jtag_tap_instruction <= {3\'d0, jtag_idcodeArea_instructionId};
end
if(jtag_readArea_instructionHit)begin
if((jtag_tap_fsm_state == `JtagState_defaultEncoding_DR_CAPTURE))begin
jtag_readArea_shifter <= {{system_rsp_payload_data,system_rsp_payload_error},system_rsp_valid};
end
if(_zz_6_)begin
jtag_readArea_shifter <= ({io_jtag_tdi,jtag_readArea_shifter} >>> 1);
end
end
end
endmodule
module SystemDebugger (
input io_remote_cmd_valid,
output io_remote_cmd_ready,
input io_remote_cmd_payload_last,
input [0:0] io_remote_cmd_payload_fragment,
output io_remote_rsp_valid,
input io_remote_rsp_ready,
output io_remote_rsp_payload_error,
output [31:0] io_remote_rsp_payload_data,
output io_mem_cmd_valid,
input io_mem_cmd_ready,
output [31:0] io_mem_cmd_payload_address,
output [31:0] io_mem_cmd_payload_data,
output io_mem_cmd_payload_wr,
output [1:0] io_mem_cmd_payload_size,
input io_mem_rsp_valid,
input [31:0] io_mem_rsp_payload,
input io_mainClk,
input resetCtrl_mainClkReset);
wire _zz_2_;
wire [0:0] _zz_3_;
reg [66:0] dispatcher_dataShifter;
reg dispatcher_dataLoaded;
reg [7:0] dispatcher_headerShifter;
wire [7:0] dispatcher_header;
reg dispatcher_headerLoaded;
reg [2:0] dispatcher_counter;
wire [66:0] _zz_1_;
assign _zz_2_ = (dispatcher_headerLoaded == 1\'b0);
assign _zz_3_ = _zz_1_[64 : 64];
assign dispatcher_header = dispatcher_headerShifter[7 : 0];
assign io_remote_cmd_ready = (! dispatcher_dataLoaded);
assign _zz_1_ = dispatcher_dataShifter[66 : 0];
assign io_mem_cmd_payload_address = _zz_1_[31 : 0];
assign io_mem_cmd_payload_data = _zz_1_[63 : 32];
assign io_mem_cmd_payload_wr = _zz_3_[0];
assign io_mem_cmd_payload_size = _zz_1_[66 : 65];
assign io_mem_cmd_valid = (dispatcher_dataLoaded && (dispatcher_header == (8\'b00000000)));
assign io_remote_rsp_valid = io_mem_rsp_valid;
assign io_remote_rsp_payload_error = 1\'b0;
assign io_remote_rsp_payload_data = io_mem_rsp_payload;
always @ (posedge io_mainClk or posedge resetCtrl_mainClkReset) begin
if (resetCtrl_mainClkReset) begin
dispatcher_dataLoaded <= 1\'b0;
dispatcher_headerLoaded <= 1\'b0;
dispatcher_counter <= (3\'b000);
end else begin
if(io_remote_cmd_valid)begin
if(_zz_2_)begin
dispatcher_counter <= (dispatcher_counter + (3\'b001));
if((dispatcher_counter == (3\'b111)))begin
dispatcher_headerLoaded <= 1\'b1;
end
end
if(io_remote_cmd_payload_last)begin
dispatcher_headerLoaded <= 1\'b1;
dispatcher_dataLoaded <= 1\'b1;
dispatcher_counter <= (3\'b000);
end
end
if((io_mem_cmd_valid && io_mem_cmd_ready))begin
dispatcher_headerLoaded <= 1\'b0;
dispatcher_dataLoaded <= 1\'b0;
end
end
end
always @ (posedge io_mainClk) begin
if(io_remote_cmd_valid)begin
if(_zz_2_)begin
dispatcher_headerShifter <= ({io_remote_cmd_payload_fragment,dispatcher_headerShifter} >>> 1);
end else begin
dispatcher_dataShifter <= ({io_remote_cmd_payload_fragment,dispatcher_dataShifter} >>> 1);
end
end
end
endmodule
module MuraxSimpleBusRam (
input io_bus_cmd_valid,
output io_bus_cmd_ready,
input io_bus_cmd_payload_wr,
input [31:0] io_bus_cmd_payload_address,
input [31:0] io_bus_cmd_payload_data,
input [3:0] io_bus_cmd_payload_mask,
output io_bus_rsp_valid,
output [31:0] io_bus_rsp_0_data,
input io_mainClk,
input resetCtrl_systemReset);
reg [31:0] _zz_4_;
wire [15:0] _zz_5_;
reg _zz_1_;
wire [29:0] _zz_2_;
wire [31:0] _zz_3_;
reg [7:0] ram_symbol0 [0:49151];
reg [7:0] ram_symbol1 [0:49151];
reg [7:0] ram_symbol2'b' [0:49151];
reg [7:0] ram_symbol3 [0:49151];
reg [7:0] _zz_6_;
reg [7:0] _zz_7_;
reg [7:0] _zz_8_;
reg [7:0] _zz_9_;
assign _zz_5_ = _zz_2_[15:0];
initial begin
$readmemb("Murax.v_toplevel_system_ram_ram_symbol0.bin",ram_symbol0);
$readmemb("Murax.v_toplevel_system_ram_ram_symbol1.bin",ram_symbol1);
$readmemb("Murax.v_toplevel_system_ram_ram_symbol2.bin",ram_symbol2);
$readmemb("Murax.v_toplevel_system_ram_ram_symbol3.bin",ram_symbol3);
end
always @ (*) begin
_zz_4_ = {_zz_9_, _zz_8_, _zz_7_, _zz_6_};
end
always @ (posedge io_mainClk) begin
if(io_bus_cmd_payload_mask[0] && io_bus_cmd_valid && io_bus_cmd_payload_wr ) begin
ram_symbol0[_zz_5_] <= _zz_3_[7 : 0];
end
if(io_bus_cmd_payload_mask[1] && io_bus_cmd_valid && io_bus_cmd_payload_wr ) begin
ram_symbol1[_zz_5_] <= _zz_3_[15 : 8];
end
if(io_bus_cmd_payload_mask[2] && io_bus_cmd_valid && io_bus_cmd_payload_wr ) begin
ram_symbol2[_zz_5_] <= _zz_3_[23 : 16];
end
if(io_bus_cmd_payload_mask[3] && io_bus_cmd_valid && io_bus_cmd_payload_wr ) begin
ram_symbol3[_zz_5_] <= _zz_3_[31 : 24];
end
if(io_bus_cmd_valid) begin
_zz_6_ <= ram_symbol0[_zz_5_];
_zz_7_ <= ram_symbol1[_zz_5_];
_zz_8_ <= ram_symbol2[_zz_5_];
_zz_9_ <= ram_symbol3[_zz_5_];
end
end
assign io_bus_rsp_valid = _zz_1_;
assign _zz_2_ = (io_bus_cmd_payload_address >>> 2);
assign _zz_3_ = io_bus_cmd_payload_data;
assign io_bus_rsp_0_data = _zz_4_;
assign io_bus_cmd_ready = 1\'b1;
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
_zz_1_ <= 1\'b0;
end else begin
_zz_1_ <= ((io_bus_cmd_valid && io_bus_cmd_ready) && (! io_bus_cmd_payload_wr));
end
end
endmodule
module MuraxSimpleBusToApbBridge (
input io_simpleBus_cmd_valid,
output io_simpleBus_cmd_ready,
input io_simpleBus_cmd_payload_wr,
input [31:0] io_simpleBus_cmd_payload_address,
input [31:0] io_simpleBus_cmd_payload_data,
input [3:0] io_simpleBus_cmd_payload_mask,
output io_simpleBus_rsp_valid,
output [31:0] io_simpleBus_rsp_1_data,
output [19:0] io_apb_PADDR,
output [0:0] io_apb_PSEL,
output io_apb_PENABLE,
input io_apb_PREADY,
output io_apb_PWRITE,
output [31:0] io_apb_PWDATA,
input [31:0] io_apb_PRDATA,
input io_apb_PSLVERROR,
input io_mainClk,
input resetCtrl_systemReset);
wire _zz_8_;
wire _zz_9_;
wire simpleBusStage_cmd_valid;
reg simpleBusStage_cmd_ready;
wire simpleBusStage_cmd_payload_wr;
wire [31:0] simpleBusStage_cmd_payload_address;
wire [31:0] simpleBusStage_cmd_payload_data;
wire [3:0] simpleBusStage_cmd_payload_mask;
reg simpleBusStage_rsp_valid;
wire [31:0] simpleBusStage_rsp_payload_data;
wire _zz_1_;
reg _zz_2_;
reg _zz_3_;
reg _zz_4_;
reg [31:0] _zz_5_;
reg [31:0] _zz_6_;
reg [3:0] _zz_7_;
reg simpleBusStage_rsp_regNext_valid;
reg [31:0] simpleBusStage_rsp_regNext_payload_data;
reg state;
assign _zz_8_ = (! state);
assign _zz_9_ = (! _zz_2_);
assign io_simpleBus_cmd_ready = _zz_3_;
assign simpleBusStage_cmd_valid = _zz_2_;
assign _zz_1_ = simpleBusStage_cmd_ready;
assign simpleBusStage_cmd_payload_wr = _zz_4_;
assign simpleBusStage_cmd_payload_address = _zz_5_;
assign simpleBusStage_cmd_payload_data = _zz_6_;
assign simpleBusStage_cmd_payload_mask = _zz_7_;
assign io_simpleBus_rsp_valid = simpleBusStage_rsp_regNext_valid;
assign io_simpleBus_rsp_1_data = simpleBusStage_rsp_regNext_payload_data;
always @ (*) begin
simpleBusStage_cmd_ready = 1\'b0;
simpleBusStage_rsp_valid = 1\'b0;
if(! _zz_8_) begin
if(io_apb_PREADY)begin
simpleBusStage_rsp_valid = (! simpleBusStage_cmd_payload_wr);
simpleBusStage_cmd_ready = 1\'b1;
end
end
end
assign io_apb_PSEL[0] = simpleBusStage_cmd_valid;
assign io_apb_PENABLE = state;
assign io_apb_PWRITE = simpleBusStage_cmd_payload_wr;
assign io_apb_PADDR = simpleBusStage_cmd_payload_address[19:0];
assign io_apb_PWDATA = simpleBusStage_cmd_payload_data;
assign simpleBusStage_rsp_payload_data = io_apb_PRDATA;
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
_zz_2_ <= 1\'b0;
_zz_3_ <= 1\'b1;
simpleBusStage_rsp_regNext_valid <= 1\'b0;
state <= 1\'b0;
end else begin
if(_zz_9_)begin
_zz_2_ <= io_simpleBus_cmd_valid;
_zz_3_ <= (! io_simpleBus_cmd_valid);
end else begin
_zz_2_ <= (! _zz_1_);
_zz_3_ <= _zz_1_;
end
simpleBusStage_rsp_regNext_valid <= simpleBusStage_rsp_valid;
if(_zz_8_)begin
state <= simpleBusStage_cmd_valid;
end else begin
if(io_apb_PREADY)begin
state <= 1\'b0;
end
end
end
end
always @ (posedge io_mainClk) begin
if(_zz_9_)begin
_zz_4_ <= io_simpleBus_cmd_payload_wr;
_zz_5_ <= io_simpleBus_cmd_payload_address;
_zz_6_ <= io_simpleBus_cmd_payload_data;
_zz_7_ <= io_simpleBus_cmd_payload_mask;
end
simpleBusStage_rsp_regNext_payload_data <= simpleBusStage_rsp_payload_data;
end
endmodule
module Apb3Gpio (
input [3:0] io_apb_PADDR,
input [0:0] io_apb_PSEL,
input io_apb_PENABLE,
output io_apb_PREADY,
input io_apb_PWRITE,
input [31:0] io_apb_PWDATA,
output reg [31:0] io_apb_PRDATA,
output io_apb_PSLVERROR,
input [31:0] io_gpio_read,
output [31:0] io_gpio_write,
output [31:0] io_gpio_writeEnable,
input io_mainClk,
input resetCtrl_systemReset);
wire ctrl_askWrite;
wire ctrl_askRead;
wire ctrl_doWrite;
wire ctrl_doRead;
reg [31:0] _zz_1_;
reg [31:0] _zz_2_;
assign io_apb_PREADY = 1\'b1;
always @ (*) begin
io_apb_PRDATA = (32\'b00000000000000000000000000000000);
case(io_apb_PADDR)
4\'b0000 : begin
io_apb_PRDATA[31 : 0] = io_gpio_read;
end
4\'b0100 : begin
io_apb_PRDATA[31 : 0] = _zz_1_;
end
4\'b1000 : begin
io_apb_PRDATA[31 : 0] = _zz_2_;
end
default : begin
end
endcase
end
assign io_apb_PSLVERROR = 1\'b0;
assign ctrl_askWrite = ((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PWRITE);
assign ctrl_askRead = ((io_apb_PSEL[0] && io_apb_PENABLE) && (! io_apb_PWRITE));
assign ctrl_doWrite = (((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PREADY) && io_apb_PWRITE);
assign ctrl_doRead = (((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PREADY) && (! io_apb_PWRITE));
assign io_gpio_write = _zz_1_;
assign io_gpio_writeEnable = _zz_2_;
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
_zz_2_ <= (32\'b00000000000000000000000000000000);
end else begin
case(io_apb_PADDR)
4\'b0000 : begin
end
4\'b0100 : begin
end
4\'b1000 : begin
if(ctrl_doWrite)begin
_zz_2_ <= io_apb_PWDATA[31 : 0];
end
end
default : begin
end
endcase
end
end
always @ (posedge io_mainClk) begin
case(io_apb_PADDR)
4\'b0000 : begin
end
4\'b0100 : begin
if(ctrl_doWrite)begin
_zz_1_ <= io_apb_PWDATA[31 : 0];
end
end
4\'b1000 : begin
end
default : begin
end
endcase
end
endmodule
module Apb3UartCtrl (
input [3:0] io_apb_PADDR,
input [0:0] io_apb_PSEL,
input io_apb_PENABLE,
output io_apb_PREADY,
input io_apb_PWRITE,
input [31:0] io_apb_PWDATA,
output reg [31:0] io_apb_PRDATA,
output io_uart_txd,
input io_uart_rxd,
output io_interrupt,
input io_mainClk,
input resetCtrl_systemReset);
wire _zz_3_;
reg _zz_4_;
wire _zz_5_;
wire _zz_6_;
wire _zz_7_;
wire [7:0] _zz_8_;
wire _zz_9_;
wire _zz_10_;
wire _zz_11_;
wire [7:0] _zz_12_;
wire [4:0] _zz_13_;
wire [4:0] _zz_14_;
wire _zz_15_;
wire _zz_16_;
wire [7:0] _zz_17_;
wire [4:0] _zz_18_;
wire [4:0] _zz_19_;
wire [0:0] _zz_20_;
wire [0:0] _zz_21_;
wire [4:0] _zz_22_;
wire busCtrl_askWrite;
wire busCtrl_askRead;
wire busCtrl_doWrite;
wire busCtrl_doRead;
wire [2:0] bridge_uartConfigReg_frame_dataLength;
wire `UartStopType_defaultEncoding_type bridge_uartConfigReg_frame_stop;
wire `UartParityType_defaultEncoding_type bridge_uartConfigReg_frame_parity;
reg [19:0] bridge_uartConfigReg_clockDivider;
reg _zz_1_;
wire bridge_write_streamUnbuffered_valid;
wire bridge_write_streamUnbuffered_ready;
wire [7:0] bridge_write_streamUnbuffered_payload;
reg bridge_interruptCtrl_writeIntEnable;
reg bridge_interruptCtrl_readIntEnable;
wire bridge_interruptCtrl_readInt;
wire bridge_interruptCtrl_writeInt;
wire bridge_interruptCtrl_interrupt;
wire [7:0] _zz_2_;
function [19:0] zz_bridge_uartConfigReg_clockDivider(input dummy);
begin
zz_bridge_uartConfigReg_clockDivider = (20\'b00000000000000000000);
zz_bridge_uartConfigReg_clockDivider = (20\'b00000000000001010101);
end
endfunction
wire [19:0] _zz_23_;
assign _zz_20_ = io_apb_PWDATA[0 : 0];
assign _zz_21_ = io_apb_PWDATA[1 : 1];
assign _zz_22_ = ((5\'b10000) - _zz_13_);
UartCtrl uartCtrl_1_ (
.io_config_frame_dataLength(bridge_uartConfigReg_frame_dataLength),
.io_config_frame_stop(bridge_uartConfigReg_frame_stop),
.io_config_frame_parity(bridge_uartConfigReg_frame_parity),
.io_config_clockDivider(bridge_uartConfigReg_clockDivider),
.io_write_valid(_zz_11_),
.io_write_ready(_zz_6_),
.io_write_payload(_zz_12_),
.io_read_valid(_zz_7_),
.io_read_payload(_zz_8_),
.io_uart_txd(_zz_9_),
.io_uart_rxd(io_uart_rxd),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
StreamFifo streamFifo_2_ (
.io_push_valid(bridge_write_streamUnbuffered_valid),
.io_push_ready(_zz_10_),
.io_push_payload(bridge_write_streamUnbuffered_payload),
.io_pop_valid(_zz_11_),
.io_pop_ready(_zz_6_),
.io_pop_payload(_zz_12_),
.io_flush(_zz_3_),
.io_occupancy(_zz_13_),
.io_availability(_zz_14_),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
StreamFifo streamFifo_3_ (
.io_push_valid(_zz_7_),
.io_push_ready(_zz_15_),
.io_push_payload(_zz_8_),
.io_pop_valid(_zz_16_),
.io_pop_ready(_zz_4_),
.io_pop_payload(_zz_17_),
.io_flush(_zz_5_),
.io_occupancy(_zz_18_),
.io_availability(_zz_19_),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
assign io_uart_txd = _zz_9_;
assign io_apb_PREADY = 1\'b1;
always @ (*) begin
io_apb_PRDATA = (32\'b00000000000000000000000000000000);
_zz_1_ = 1\'b0;
_zz_4_ = 1\'b0;
case(io_apb_PADDR)
4\'b0000 : begin
if(busCtrl_doWrite)begin
_zz_1_ = 1\'b1;
end
if(busCtrl_doRead)begin
_zz_4_ = 1\'b1;
end
io_apb_PRDATA[16 : 16] = _zz_16_;
io_apb_PRDATA[7 : 0] = _zz_17_;
end
4\'b0100 : begin
io_apb_PRDATA[20 : 16] = _zz_22_;
io_apb_PRDATA[28 : 24] = _zz_18_;
io_apb_PRDATA[0 : 0] = bridge_interruptCtrl_writeIntEnable;
io_apb_PRDATA[1 : 1] = bridge_interruptCtrl_readIntEnable;
io_apb_PRDATA[8 : 8] = bridge_interruptCtrl_writeInt;
io_apb_PRDATA[9 : 9] = bridge_interruptCtrl_readInt;
end
default : begin
end
endcase
end
assign busCtrl_askWrite = ((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PWRITE);
assign busCtrl_askRead = ((io_apb_PSEL[0] && io_apb_PENABLE) && (! io_apb_PWRITE));
assign busCtrl_doWrite = (((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PREADY) && io_apb_PWRITE);
assign busCtrl_doRead = (((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PREADY) && (! io_apb_PWRITE));
assign _zz_23_ = zz_bridge_uartConfigReg_clockDivider(1\'b0);
always @ (*) bridge_uartConfigReg_clockDivider = _zz_23_;
assign bridge_uartConfigReg_frame_dataLength = (3\'b111);
assign bridge_uartConfigReg_frame_parity = `UartParityType_defaultEncoding_NONE;
assign bridge_uartConfigReg_frame_stop = `UartStopType_defaultEncoding_ONE;
assign bridge_write_streamUnbuffered_valid = _zz_1_;
assign bridge_write_streamUnbuffered_payload = _zz_2_;
assign bridge_write_streamUnbuffered_ready = _zz_10_;
assign bridge_interruptCtrl_readInt = (bridge_interruptCtrl_readIntEnable && _zz_16_);
assign bridge_interruptCtrl_writeInt = (bridge_interruptCtrl_writeIntEnable && (! _zz_11_));
assign bridge_interruptCtrl_interrupt = (bridge_interruptCtrl_readInt || bridge_interruptCtrl_writeInt);
assign io_interrupt = bridge_interruptCtrl_interrupt;
assign _zz_2_ = io_apb_PWDATA[7 : 0];
assign _zz_3_ = 1\'b0;
assign _zz_5_ = 1\'b0;
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
bridge_interruptCtrl_writeIntEnable <= 1\'b0;
bridge_interruptCtrl_readIntEnable <= 1\'b0;
end else begin
case(io_apb_PADDR)
4\'b0000 : begin
end
4\'b0100 : begin
if(busCtrl_doWrite)begin
bridge_interruptCtrl_writeIntEnable <= _zz_20_[0];
bridge_interruptCtrl_readIntEnable <= _zz_21_[0];
end
end
default : begin
end
endcase
end
end
endmodule
module MuraxApb3Timer (
input [7:0] io_apb_PADDR,
input [0:0] io_apb_PSEL,
input io_apb_PENABLE,
output io_apb_PREADY,
input io_apb_PWRITE,
input [31:0] io_apb_PWDATA,
output reg [31:0] io_apb_PRDATA,
output io_apb_PSLVERROR,
output io_interrupt,
input io_mainClk,
input resetCtrl_systemReset);
wire _zz_10_;
wire _zz_11_;
wire _zz_12_;
wire _zz_13_;
reg [1:0] _zz_14_;
reg [1:0] _zz_15_;
wire _zz_16_;
wire _zz_17_;
wire [15:0] _zz_18_;
wire _zz_19_;
wire [15:0] _zz_20_;
wire [1:0] _zz_21_;
wire busCtrl_askWrite;
wire busCtrl_askRead;
wire busCtrl_doWrite;
wire busCtrl_doRead;
reg [15:0] _zz_1_;
reg _zz_2_;
reg [1:0] timerABridge_ticksEnable;
reg [0:0] timerABridge_clearsEnable;
reg timerABridge_busClearing;
reg [15:0] _zz_3_;
reg _zz_4_;
reg _zz_5_;
reg [1:0] timerBBridge_ticksEnable;
reg [0:0] timerBBridge_clearsEnable;
reg timerBBridge_busClearing;
reg [15:0] _zz_6_;
reg _zz_7_;
reg _zz_8_;
reg [1:0] _zz_9_;
Prescaler prescaler_1_ (
.io_clear(_zz_2_),
.io_limit(_zz_1_),
.io_overflow(_zz_16_),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
Timer timerA (
.io_tick(_zz_10_),
.io_clear(_zz_11_),
.io_limit(_zz_3_),
.io_full(_zz_17_),
.io_value(_zz_18_),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
Timer timerB (
.io_tick(_zz_12_),
.io_clear(_zz_13_),
.io_limit(_zz_6_),
.io_full(_zz_19_),
.io_value(_zz_20_),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
InterruptCtrl interruptCtrl_1_ (
.io_inputs(_zz_14_),
.io_clears(_zz_15_),
.io_masks(_zz_9_),
.io_pendings(_zz_21_),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
assign io_apb_PREADY = 1\'b1;
always @ (*) begin
io_apb_PRDATA = (32\'b00000000000000000000000000000000);
_zz_2_ = 1\'b0;
_zz_4_ = 1\'b0;
_zz_5_ = 1\'b0;
_zz_7_ = 1\'b0;
_zz_8_ = 1\'b0;
_zz_15_ = (2\'b00);
case(io_apb_PADDR)
8\'b00000000 : begin
if(busCtrl_doWrite)begin
_zz_2_ = 1\'b1;
end
io_apb_PRDATA[15 : 0] = _zz_1_;
end
8\'b01000000 : begin
io_apb_PRDATA[1 : 0] = timerABridge_ticksEnable;
io_apb_PRDATA[16 : 16] = timerABridge_clearsEnable;
end
8\'b01000100 : begin
if(busCtrl_doWrite)begin
_zz_4_ = 1\'b1;
end
io_apb_PRDATA[15 : 0] = _zz_3_;
end
8\'b01001000 : begin
if(busCtrl_doWrite)begin
_zz_5_ = 1\'b1;
end
io_apb_PRDATA[15 : 0] = _zz_18_;
end
8\'b01010000 : begin
io_apb_PRDATA[1 : 0] = timerBBridge_ticksEnable;
io_apb_PRDATA[16 : 16] = timerBBridge_clearsEnable;
end
8\'b01010100 : begin
if(busCtrl_doWrite)begin
_zz_7_ = 1\'b1;
end
io_apb_PRDATA[15 : 0] = _zz_6_;
end
8\'b01011000 : begin
if(busCtrl_doWrite)begin
_zz_8_ = 1\'b1;
end
io_apb_PRDATA[15 : 0] = _zz_20_;
end
8\'b00010000 : begin
if(busCtrl_doWrite)begin
_zz_15_ = io_apb_PWDATA[1 : 0];
end
io_apb_PRDATA[1 : 0] = _zz_21_;
end
8\'b00010100 : begin
io_apb_PRDATA[1 : 0] = _zz_9_;
end
default : begin
end
endcase
end
assign io_apb_PSLVERROR = 1\'b0;
assign busCtrl_askWrite = ((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PWRITE);
assign busCtrl_askRead = ((io_apb_PSEL[0] && io_apb_PENABLE) && (! io_apb_PWRITE));
assign busCtrl_doWrite = (((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PREADY) && io_apb_PWRITE);
assign busCtrl_doRead = (((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PREADY) && (! io_apb_PWRITE));
always @ (*) begin
timerABridge_busClearing = 1\'b0;
if(_zz_4_)begin
timerABridge_busClearing = 1\'b1;
end
if(_zz_5_)begin
timerABridge_busClearing = 1\'b1;
end
end
assign _zz_11_ = (((timerABridge_clearsEnable & _zz_17_) != (1\'b0)) || timerABridge_busClearing);
assign _zz_10_ = ((timerABridge_ticksEnable & {_zz_16_,1\'b1}) != (2\'b00));
always @ (*) begin
timerBBridge_busClearing = 1\'b0;
if(_zz_7_)begin
timerBBridge_busClearing = 1\'b1;
end
if(_zz_8_)begin
timerBBridge_busClearing = 1\'b1;
end
end
assign _zz_13_ = (((timerBBridge_clearsEnable & _zz_19_) != (1\'b0)) || timerBBridge_busClearing);
assign _zz_12_ = ((timerBBridge_ticksEnable & {_zz_16_,1\'b1}) != (2\'b00));
always @ (*) begin
_zz_14_[0] = _zz_17_;
_zz_14_[1] = _zz_19_;
end
assign io_interrupt = (_zz_21_ != (2\'b00));
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
timerABridge_ticksEnable <= (2\'b00);
timerABridge_clearsEnable <= (1\'b0);
timerBBridge_ticksEnable <= (2\'b00);
timerBBridge_clearsEnable <= (1\'b0);
_zz_9_ <= (2\'b00);
end else begin
case(io_apb_PADDR)
8\'b00000000 : begin
end
8\'b01000000 : begin
if(busCtrl_doWrite)begin
timerABridge_ticksEnable <= io_apb_PWDATA[1 : 0];
timerABridge_clearsEnable <= io_apb_PWDATA[16 : 16];
end
end
8\'b01000100 : begin
end
8\'b01001000 : begin
end
8\'b01010000 : begin
if(busCtrl_doWrite)begin
timerBBridge_ticksEnable <= io_apb_PWDATA[1 : 0];
timerBBridge_clearsEnable <= io_apb_PWDATA[16 : 16];
end
end
8\'b01010100 : begin
end
8\'b01011000 : begin
end
8\'b00010000 : begin
end
8\'b00010100 : begin
if(busCtrl_doWrite)begin
_zz_9_ <= io_apb_PWDATA[1 : 0];
end
end
default : begin
end
endcase
end
end
always @ (posedge io_mainClk) begin
case(io_apb_PADDR)
8\'b00000000 : begin
if(busCtrl_doWrite)begin
_zz_1_ <= io_apb_PWDATA[15 : 0];
end
end
8\'b01000000 : begin
end
8\'b01000100 : begin
if(busCtrl_doWrite)begin
_zz_3_ <= io_apb_PWDATA[15 : 0];
end
end
8\'b01001000 : begin
end
8\'b01010000 : begin
end
8\'b01010100 : begin
if(busCtrl_doWrite)begin
_zz_6_ <= io_apb_PWDATA[15 : 0];
end
end
8\'b01011000 : begin
end
8\'b00010000 : begin
end
8\'b00010100 : begin
end
default : begin
end
endcase
end
endmodule
module Apb3Decoder (
input [19:0] io_input_PADDR,
input [0:0] io_input_PSEL,
input io_input_PENABLE,
output reg io_input_PREADY,
input io_input_PWRITE,
input [31:0] io_input_PWDATA,
output [31:0] io_input_PRDATA,
output reg io_input_PSLVERROR,
output [19:0] io_output_PADDR,
output reg [2:0] io_output_PSEL,
output io_output_PENABLE,
input io_output_PREADY,
output io_output_PWRITE,
output [31:0] io_output_PWDATA,
input [31:0] io_output_PRDATA,
input io_output_PSLVERROR);
wire [19:0] _zz_1_;
wire [19:0] _zz_2_;
wire [19:0] _zz_3_;
assign _zz_1_ = (20\'b11111111000000000000);
assign _zz_2_ = (20\'b11111111000000000000);
assign _zz_3_ = (20\'b11111111000000000000);
assign io_output_PADDR = io_input_PADDR;
assign io_output_PENABLE = io_input_PENABLE;
assign io_output_PWRITE = io_input_PWRITE;
assign io_output_PWDATA = io_input_PWDATA;
always @ (*) begin
io_output_PSEL[0] = (((io_input_PADDR & _zz_1_) == (20\'b00000000000000000000)) && io_input_PSEL[0]);
io_output_PSEL[1] = (((io_input_PADDR & _zz_2_) == (20\'b00010000000000000000)) && io_input_PSEL[0]);
io_output_PSEL[2] = (((io_input_PADDR & _zz_3_) == (20\'b00100000000000000000)) && io_input_PSEL[0]);
end
always @ (*) begin
io_input_PREADY = io_output_PREADY;
io_input_PSLVERROR = io_output_PSLVERROR;
if((io_input_PSEL[0] && (io_output_PSEL == (3\'b000))))begin
io_input_PREADY = 1\'b1;
io_input_PSLVERROR = 1\'b1;
end
end
assign io_input_PRDATA = io_output_PRDATA;
endmodule
module Apb3Router (
input [19:0] io_input_PADDR,
input [2:0] io_input_PSEL,
input io_input_PENABLE,
output io_input_PREADY,
input io_input_PWRITE,
input [31:0] io_input_PWDATA,
output [31:0] io_input_PRDATA,
output io_input_PSLVERROR,
output [19:0] io_outputs_0_PADDR,
output [0:0] io_outputs_0_PSEL,
output io_outputs_0_PENABLE,
input io_outputs_0_PREADY,
output io_outputs_0_PWRITE,
output [31:0] io_outputs_0_PWDATA,
input [31:0] io_outputs_0_PRDATA,
input io_outputs_0_PSLVERROR,
output [19:0] io_outputs_1_PADDR,
output [0:0] io_outputs_1_PSEL,
output io_outputs_1_PENABLE,
input io_outputs_1_PREADY,
output io_outputs_1_PWRITE,
output [31:0] io_outputs_1_PWDATA,
input [31:0] io_outputs_1_PRDATA,
input io_outputs_1_PSLVERROR,
output [19:0] io_outputs_2_PADDR,
output [0:0] io_outputs_2_PSEL,
output io_outputs_2_PENABLE,
input io_outputs_2_PREADY,
output io_outputs_2_PWRITE,
output [31:0] io_outputs_2_PWDATA,
input [31:0] io_outputs_2_PRDATA,
input io_outputs_2_PSLVERROR,
input io_mainClk,
input resetCtrl_systemReset);
reg _zz_3_;
reg [31:0] _zz_4_;
reg _zz_5_;
wire _zz_1_;
wire _zz_2_;
reg [1:0] selIndex;
always @(*) begin
case(selIndex)
2\'b00 : begin
_zz_3_ = io_outputs_0_PREADY;
_zz_4_ = io_outputs_0_PRDATA;
_zz_5_ = io_outputs_0_PSLVERROR;
end
2\'b01 : begin
_zz_3_ = io_outputs_1_PREADY;
_zz_4_ = io_outputs_1_PRDATA;
_zz_5_ = io_outputs_1_PSLVERROR;
end
default : begin
_zz_3_ = io_outputs_2_PREADY;
_zz_4_ = io_outputs_2_PRDATA;
_zz_5_ = io_outputs_2_PSLVERROR;
end
endcase
end
assign io_outputs_0_PADDR = io_input_PADDR;
assign io_outputs_0_PENABLE = io_input_PENABLE;
assign io_outputs_0_PSEL[0] = io_input_PSEL[0];
assign io_outputs_0_PWRITE = io_input_PWRITE;
assign io_outputs_0_PWDATA = io_input_PWDATA;
assign io_outputs_1_PADDR = io_input_PADDR;
assign io_outputs_1_PENABLE = io_input_PENABLE;
assign io_outputs_1_PSEL[0] = io_input_PSEL[1];
assign io_outputs_1_PWRITE = io_input_PWRITE;
assign io_outputs_1_PWDATA = io_input_PWDATA;
assign io_outputs_2_PADDR = io_input_PADDR;
assign io_outputs_2_PENABLE = io_input_PENABLE;
assign io_outputs_2_PSEL[0] = io_input_PSEL[2];
assign io_outputs_2_PWRITE = io_input_PWRITE;
assign io_outputs_2_PWDATA = io_input_PWDATA;
assign _zz_1_ = io_input_PSEL[1];
assign _zz_2_ = io_input_PSEL[2];
assign io_input_PREADY = _zz_3_;
assign io_input_PRDATA = _zz_4_;
assign io_input_PSLVERROR = _zz_5_;
always @ (posedge io_mainClk) begin
selIndex <= {_zz_2_,_zz_1_};
end
endmodule
module Murax (
input io_asyncReset,
input io_mainClk,
input io_jtag_tms,
input io_jtag_tdi,
output io_jtag_tdo,
input io_jtag_tck,
input [31:0] io_gpioA_read,
output [31:0] io_gpioA_write,
output [31:0] io_gpioA_writeEnable,
output io_uart_txd,
input io_uart_rxd);
wire [7:0] _zz_10_;
reg _zz_11_;
reg _zz_12_;
wire [3:0] _zz_13_;
wire [3:0] _zz_14_;
wire [7:0] _zz_15_;
wire _zz_16_;
reg [31:0] _zz_17_;
wire _zz_18_;
wire _zz_19_;
wire _zz_20_;
wire _zz_21_;
wire [31:0] _zz_22_;
wire _zz_23_;
wire _zz_24_;
wire _zz_25_;
wire [31:0] _zz_26_;
wire _zz_27_;
wire _zz_28_;
wire [31:0] _zz_29_;
wire [31:0] _zz_30_;
wire [3:0] _zz_31_;
wire _zz_32_;
wire [31:0] _zz_33_;
wire _zz_34_;
wire [31:0] _zz_35_;
wire _zz_36_;
wire _zz_37_;
wire _zz_38_;
wire [31:0] _zz_39_;
wire [31:0] _zz_40_;
wire [1:0] _zz_41_;
wire _zz_42_;
wire _zz_43_;
wire _zz_44_;
wire [0:0] _zz_45_;
wire _zz_46_;
wire _zz_47_;
wire _zz_48_;
wire _zz_49_;
wire [31:0] _zz_50_;
wire _zz_51_;
wire [31:0] _zz_52_;
wire [31:0] _zz_53_;
wire _zz_54_;
wire [1:0] _zz_55_;
wire _zz_56_;
wire _zz_57_;
wire [31:0] _zz_58_;
wire _zz_59_;
wire _zz_60_;
wire [31:0] _zz_61_;
wire [19:0] _zz_62_;
wire [0:0] _zz_63_;
wire _zz_64_;
wire _zz_65_;
wire [31:0] _zz_66_;
wire _zz_67_;
wire [31:0] _zz_68_;
wire _zz_69_;
wire [31:0] _zz_70_;
wire [31:0] _zz_71_;
wire _zz_72_;
wire [31:0] _zz_73_;
wire _zz_74_;
wire _zz_75_;
wire _zz_76_;
wire [31:0] _zz_77_;
wire _zz_78_;
wire _zz_79_;
wire _zz_80_;
wire [31:0] _zz_81_;
wire _zz_82_;
wire [19:0] _zz_83_;
wire [2:0] _zz_84_;
wire _zz_85_;
wire _zz_86_;
wire [31:0] _zz_87_;
wire _zz_88_;
wire [31:0] _zz_89_;
wire _zz_90_;
wire [19:0] _zz_91_;
wire [0:0] _zz_92_;
wire _zz_93_;
wire _zz_94_;
wire [31:0] _zz_95_;
wire [19:0] _zz_96_;
wire [0:0] _zz_97_;
wire _zz_98_;
wire _zz_99_;
wire [31:0] _zz_100_;
wire [19:0] _zz_101_;
wire [0:0] _zz_102_;
wire _zz_103_;
wire _zz_104_;
wire [31:0] _zz_105_;
wire _zz_106_;
wire _zz_107_;
wire [31:0] _zz_108_;
reg resetCtrl_mainClkResetUnbuffered;
reg [5:0] resetCtrl_systemClkResetCounter = (6\'b000000);
wire [5:0] _zz_1_;
reg resetCtrl_mainClkReset;
reg resetCtrl_systemReset;
reg system_timerInterrupt;
reg system_externalInterrupt;
wire _zz_2_;
reg _zz_3_;
reg _zz_4_;
reg _zz_5_;
reg [31:0] _zz_6_;
reg [31:0] _zz_7_;
reg [1:0] _zz_8_;
reg debug_resetOut_regNext;
reg _zz_9_;
wire system_mainBusDecoder_logic_masterPipelined_cmd_valid;
reg system_mainBusDecoder_logic_masterPipelined_cmd_ready;
wire system_mainBusDecoder_logic_masterPipelined_cmd_payload_wr;
wire [31:0] system_mainBusDecoder_logic_masterPipelined_cmd_payload_address;
wire [31:0] system_mainBusDecoder_logic_masterPipelined_cmd_payload_data;
wire [3:0] system_mainBusDecoder_logic_masterPipelined_cmd_payload_mask;
wire system_mainBusDecoder_logic_masterPipelined_rsp_valid;
wire [31:0] system_mainBusDecoder_logic_masterPipelined_rsp_payload_data;
wire system_mainBusDecoder_logic_hits_0;
wire system_mainBusDecoder_logic_hits_1;
wire system_mainBusDecoder_logic_noHit;
reg system_mainBusDecoder_logic_rspPending;
reg system_mainBusDecoder_logic_rspNoHit;
reg [0:0] system_mainBusDecoder_logic_rspSourceId;
assign _zz_106_ = (resetCtrl_systemClkResetCounter != _zz_1_);
assign _zz_107_ = (! _zz_3_);
assign _zz_108_ = (32\'b11111111111100000000000000000000);
BufferCC_2_ bufferCC_3_ (
.io_dataIn(io_asyncReset),
.io_dataOut(_zz_18_),
.io_mainClk(io_mainClk)
);
MuraxMasterArbiter system_mainBusArbiter (
.io_iBus_cmd_valid(_zz_32_),
.io_iBus_cmd_ready(_zz_19_),
.io_iBus_cmd_payload_pc(_zz_33_),
.io_iBus_rsp_valid(_zz_20_),
.io_iBus_rsp_payload_error(_zz_21_),
.io_iBus_rsp_payload_inst(_zz_22_),
.io_dBus_cmd_valid(_zz_3_),
.io_dBus_cmd_ready(_zz_23_),
.io_dBus_cmd_payload_wr(_zz_5_),
.io_dBus_cmd_payload_address(_zz_6_),
.io_dBus_cmd_payload_data(_zz_7_),
.io_dBus_cmd_payload_size(_zz_8_),
.io_dBus_rsp_ready(_zz_24_),
.io_dBus_rsp_error(_zz_25_),
.io_dBus_rsp_data(_zz_26_),
.io_masterBus_cmd_valid(_zz_27_),
.io_masterBus_cmd_ready(system_mainBusDecoder_logic_masterPipelined_cmd_ready),
.io_masterBus_cmd_payload_wr(_zz_28_),
.io_masterBus_cmd_payload_address(_zz_29_),
.io_masterBus_cmd_payload_data(_zz_30_),
.io_masterBus_cmd_payload_mask(_zz_31_),
.io_masterBus_rsp_valid(system_mainBusDecoder_logic_masterPipelined_rsp_valid),
.io_masterBus_rsp_payload_data(system_mainBusDecoder_logic_masterPipelined_rsp_payload_data),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
VexRiscv system_cpu (
.iBus_cmd_valid(_zz_32_),
.iBus_cmd_ready(_zz_19_),
.iBus_cmd_payload_pc(_zz_33_),
.iBus_rsp_valid(_zz_20_),
.iBus_rsp_payload_error(_zz_21_),
.iBus_rsp_payload_inst(_zz_22_),
.timerInterrupt(system_timerInterrupt),
.externalInterrupt(system_externalInterrupt),
.debug_bus_cmd_valid(_zz_51_),
.debug_bus_cmd_ready(_zz_34_),
.debug_bus_cmd_payload_wr(_zz_54_),
.debug_bus_cmd_payload_address(_zz_10_),
.debug_bus_cmd_payload_data(_zz_53_),
.debug_bus_rsp_data(_zz_35_),
.debug_resetOut(_zz_36_),
.dBus_cmd_valid(_zz_37_),
.dBus_cmd_ready(_zz_4_),
.dBus_cmd_payload_wr(_zz_38_),
.dBus_cmd_payload_address(_zz_39_),
.dBus_cmd_payload_data(_zz_40_),
.dBus_cmd_payload_size(_zz_41_),
.dBus_rsp_ready(_zz_24_),
.dBus_rsp_error(_zz_25_),
.dBus_rsp_data(_zz_26_),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset),
.resetCtrl_mainClkReset(resetCtrl_mainClkReset)
);
JtagBridge jtagBridge_1_ (
.io_jtag_tms(io_jtag_tms),
.io_jtag_tdi(io_jtag_tdi),
.io_jtag_tdo(_zz_42_),
.io_jtag_tck(io_jtag_tck),
.io_remote_cmd_valid(_zz_43_),
.io_remote_cmd_ready(_zz_47_),
.io_remote_cmd_payload_last(_zz_44_),
.io_remote_cmd_payload_fragment(_zz_45_),
.io_remote_rsp_valid(_zz_48_),
.io_remote_rsp_ready(_zz_46_),
.io_remote_rsp_payload_error(_zz_49_),
.io_remote_rsp_payload_data(_zz_50_),
.io_mainClk(io_mainClk),
.resetCtrl_mainClkReset(resetCtrl_mainClkReset)
);
SystemDebugger systemDebugger_1_ (
.io_remote_cmd_valid(_zz_43_),
.io_remote_cmd_ready(_zz_47_),
.io_remote_cmd_payload_last(_zz_44_),
.io_remote_cmd_payload_fragment(_zz_45_),
.io_remote_rsp_valid(_zz_48_),
.io_remote_rsp_ready(_zz_46_),
.io_remote_rsp_payload_error(_zz_49_),
.io_remote_rsp_payload_data(_zz_50_),
.io_mem_cmd_valid(_zz_51_),
.io_mem_cmd_ready(_zz_34_),
.io_mem_cmd_payload_address(_zz_52_),
.io_mem_cmd_payload_data(_zz_53_),
.io_mem_cmd_payload_wr(_zz_54_),
.io_mem_cmd_payload_size(_zz_55_),
.io_mem_rsp_valid(_zz_9_),
.io_mem_rsp_payload(_zz_35_),
.io_mainClk(io_mainClk),
.resetCtrl_mainClkReset(resetCtrl_mainClkReset)
);
MuraxSimpleBusRam system_ram (
.io_bus_cmd_valid(_zz_11_),
.io_bus_cmd_ready(_zz_56_),
.io_bus_cmd_payload_wr(system_mainBusDecoder_logic_masterPipelined_cmd_payload_wr),
.io_bus_cmd_payload_address(system_mainBusDecoder_logic_masterPipelined_cmd_payload_address),
.io_bus_cmd_payload_data(system_mainBusDecoder_logic_masterPipelined_cmd_payload_data),
.io_bus_cmd_payload_mask(system_mainBusDecoder_logic_masterPipelined_cmd_payload_mask),
.io_bus_rsp_valid(_zz_57_),
.io_bus_rsp_0_data(_zz_58_),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
MuraxSimpleBusToApbBridge system_apbBridge (
.io_simpleBus_cmd_valid(_zz_12_),
.io_simpleBus_cmd_ready(_zz_59_),
.io_simpleBus_cmd_payload_wr(system_mainBusDecoder_logic_masterPipelined_cmd_payload_wr),
.io_simpleBus_cmd_payload_address(system_mainBusDecoder_logic_masterPipelined_cmd_payload_address),
.io_simpleBus_cmd_payload_data(system_mainBusDecoder_logic_masterPipelined_cmd_payload_data),
.io_simpleBus_cmd_payload_mask(system_mainBusDecoder_logic_masterPipelined_cmd_payload_mask),
.io_simpleBus_rsp_valid(_zz_60_),
.io_simpleBus_rsp_1_data(_zz_61_),
.io_apb_PADDR(_zz_62_),
.io_apb_PSEL(_zz_63_),
.io_apb_PENABLE(_zz_64_),
.io_apb_PREADY(_zz_80_),
.io_apb_PWRITE(_zz_65_),
.io_apb_PWDATA(_zz_66_),
.io_apb_PRDATA(_zz_81_),
.io_apb_PSLVERROR(_zz_82_),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
Apb3Gpio system_gpioACtrl (
.io_apb_PADDR(_zz_13_),
.io_apb_PSEL(_zz_92_),
.io_apb_PENABLE(_zz_93_),
.io_apb_PREADY(_zz_67_),
.io_apb_PWRITE(_zz_94_),
.io_apb_PWDATA(_zz_95_),
.io_apb_PRDATA(_zz_68_),
.io_apb_PSLVERROR(_zz_69_),
.io_gpio_read(io_gpioA_read),
.io_gpio_write(_zz_70_),
.io_gpio_writeEnable(_zz_71_),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
Apb3UartCtrl system_uartCtrl (
.io_apb_PADDR(_zz_14_),
.io_apb_PSEL(_zz_97_),
.io_apb_PENABLE(_zz_98_),
.io_apb_PREADY(_zz_72_),
.io_apb_PWRITE(_zz_99_),
.io_apb_PWDATA(_zz_100_),
.io_apb_PRDATA(_zz_73_),
.io_uart_txd(_zz_74_),
.io_uart_rxd(io_uart_rxd),
.io_interrupt(_zz_75_),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
MuraxApb3Timer system_timer (
.io_apb_PADDR(_zz_15_),
.io_apb_PSEL(_zz_102_),
.io_apb_PENABLE(_zz_103_),
.io_apb_PREADY(_zz_76_),
.io_apb_PWRITE(_zz_104_),
.io_apb_PWDATA(_zz_105_),
.io_apb_PRDATA(_zz_77_),
.io_apb_PSLVERROR(_zz_78_),
.io_interrupt(_zz_79_),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
Apb3Decoder io_apb_decoder (
.io_input_PADDR(_zz_62_),
.io_input_PSEL(_zz_63_),
.io_input_PENABLE(_zz_64_),
.io_input_PREADY(_zz_80_),
.io_input_PWRITE(_zz_65_),
.io_input_PWDATA(_zz_66_),
.io_input_PRDATA(_zz_81_),
.io_input_PSLVERROR(_zz_82_),
.io_output_PADDR(_zz_83_),
.io_output_PSEL(_zz_84_),
.io_output_PENABLE(_zz_85_),
.io_output_PREADY(_zz_88_),
.io_output_PWRITE(_zz_86_),
.io_output_PWDATA(_zz_87_),
.io_output_PRDATA(_zz_89_),
.io_output_PSLVERROR(_zz_90_)
);
Apb3Router apb3Router_1_ (
.io_input_PADDR(_zz_83_),
.io_input_PSEL(_zz_84_),
.io_input_PENABLE(_zz_85_),
.io_input_PREADY(_zz_88_),
.io_input_PWRITE(_zz_86_),
.io_input_PWDATA(_zz_87_),
.io_input_PRDATA(_zz_89_),
.io_input_PSLVERROR(_zz_90_),
.io_outputs_0_PADDR(_zz_91_),
.io_outputs_0_PSEL(_zz_92_),
.io_outputs_0_PENABLE(_zz_93_),
.io_outputs_0_PREADY(_zz_67_),
.io_outputs_0_PWRITE(_zz_94_),
.io_outputs_0_PWDATA(_zz_95_),
.io_outputs_0_PRDATA(_zz_68_),
.io_outputs_0_PSLVERROR(_zz_69_),
.io_outputs_1_PADDR(_zz_96_),
.io_outputs_1_PSEL(_zz_97_),
.io_outputs_1_PENABLE(_zz_98_),
.io_outputs_1_PREADY(_zz_72_),
.io_outputs_1_PWRITE(_zz_99_),
.io_outputs_1_PWDATA(_zz_100_),
.io_outputs_1_PRDATA(_zz_73_),
.io_outputs_1_PSLVERROR(_zz_16_),
.io_outputs_2_PADDR(_zz_101_),
.io_outputs_2_PSEL(_zz_102_),
.io_outputs_2_PENABLE(_zz_103_),
.io_outputs_2_PREADY(_zz_76_),
.io_outputs_2_PWRITE(_zz_104_),
.io_outputs_2_PWDATA(_zz_105_),
.io_outputs_2_PRDATA(_zz_77_),
.io_outputs_2_PSLVERROR(_zz_78_),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
always @(*) begin
case(system_mainBusDecoder_logic_rspSourceId)
1\'b0 : begin
_zz_17_ = _zz_58_;
end
default : begin
_zz_17_ = _zz_61_;
end
endcase
end
always @ (*) begin
resetCtrl_mainClkResetUnbuffered = 1\'b0;
if(_zz_106_)begin
resetCtrl_mainClkResetUnbuffered = 1\'b1;
end
end
assign _zz_1_[5 : 0] = (6\'b111111);
always @ (*) begin
system_timerInterrupt = 1\'b0;
if(_zz_79_)begin
system_timerInterrupt = 1\'b1;
end
end
always @ (*) begin
system_externalInterrupt = 1\'b0;
if(_zz_75_)begin
system_externalInterrupt = 1\'b1;
end
end
assign _zz_2_ = _zz_23_;
assign _zz_10_ = _zz_52_[7:0];
assign io_jtag_tdo = _zz_42_;
assign io_gpioA_write = _zz_70_;
assign io_gpioA_writeEnable = _zz_71_;
assign io_uart_txd = _zz_74_;
assign _zz_13_ = _zz_91_[3:0];
assign _zz_14_ = _zz_96_[3:0];
assign _zz_16_ = 1\'b0;
assign _zz_15_ = _zz_101_[7:0];
assign system_mainBusDecoder_logic_masterPipelined_cmd_valid = _zz_27_;
assign system_mainBusDecoder_logic_masterPipelined_cmd_payload_wr = _zz_28_;
assign system_mainBusDecoder_logic_masterPipelined_cmd_payload_address = _zz_29_;
assign system_mainBusDecoder_logic_masterPipelined_cmd_payload_data = _zz_30_;
assign system_mainBusDecoder_logic_masterPipelined_cmd_payload_mask = _zz_31_;
assign system_mainBusDecoder_logic_hits_0 = (((32\'b10000000000000000000000000000000) <= system_mainBusDecoder_logic_masterPipelined_cmd_payload_address) && (system_mainBusDecoder_logic_masterPipelined_cmd_payload_address < (32\'b10000000000000110000000000000000)));
always @ (*) begin
_zz_11_ = (system_mainBusDecoder_logic_masterPipelined_cmd_valid && system_mainBusDecoder_logic_hits_0);
_zz_12_ = (system_mainBusDecoder_logic_masterPipelined_cmd_valid && system_mainBusDecoder_logic_hits_1);
system_mainBusDecoder_logic_masterPipelined_cmd_ready = (((system_mainBusDecoder_logic_hits_0 && _zz_56_) || (system_mainBusDecoder_logic_hits_1 && _zz_59_)) || system_mainBusDecoder_logic_noHit);
if((system_mainBusDecoder_logic_rspPending && (! system_mainBusDecoder_logic_masterPipelined_rsp_valid)))begin
system_mainBusDecoder_logic_masterPipelined_cmd_ready = 1\'b0;
_zz_11_ = 1\'b0;
_zz_12_ = 1\'b0;
end
end
assign system_mainBusDecoder_logic_hits_1 = ((system_mainBusDecoder_logic_masterPipelined_cmd_payload_address & _zz_108_) == (32\'b11110000000000000000000000000000));
assign system_mainBusDecoder_logic_noHit = (! (system_mainBusDecoder_logic_hits_0 || system_mainBusDecoder_logic_hits_1));
assign system_mainBusDecoder_logic_masterPipelined_rsp_valid = ((_zz_57_ || _zz_60_) || (system_mainBusDecoder_logic_rspPending && system_mainBusDecoder_logic_rspNoHit));
assign system_mainBusDecoder_logic_masterPipelined_rsp_payload_data = _zz_17_;
always @ (posedge io_mainClk) begin
if(_zz_106_)begin
resetCtrl_systemClkResetCounter <= (resetCtrl_systemClkResetCounter + (6\'b000001));
end
if(_zz_18_)begin
resetCtrl_systemClkResetCounter <= (6\'b000000);
end
end
always @ (posedge io_mainClk) begin
resetCtrl_mainClkReset <= resetCtrl_mainClkResetUnbuffered;
resetCtrl_systemReset <= resetCtrl_mainClkResetUnbuffered;
if(debug_resetOut_regNext)begin
resetCtrl_systemReset <= 1\'b1;
end
end
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
_zz_3_ <= 1\'b0;
_zz_4_ <= 1\'b1;
system_mainBusDecoder_logic_rspPending <= 1\'b0;
system_mainBusDecoder_logic_rspNoHit <= 1\'b0;
end else begin
if(_zz_107_)begin
_zz_3_ <= _zz_37_;
_zz_4_ <= (! _zz_37_);
end else begin
_zz_3_ <= (! _zz_2_);
_zz_4_ <= _zz_2_;
end
if(system_mainBusDecoder_logic_masterPipelined_rsp_valid)begin
system_mainBusDecoder_logic_rspPending <= 1\'b0;
end
if(((system_mainBusDecoder_logic_masterPipelined_cmd_valid && system_mainBusDecoder_logic_masterPipelined_cmd_ready) && (! system_mainBusDecoder_logic_masterPipelined_cmd_payload_wr)))begin
system_mainBusDecoder_logic_rspPending <= 1\'b1;
end
system_mainBusDecoder_logic_rspNoHit <= 1\'b0;
if(system_mainBusDecoder_logic_noHit)begin
system_mainBusDecoder_logic_rspNoHit <= 1\'b1;
end
end
end
always @ (posedge io_mainClk) begin
if(_zz_107_)begin
_zz_5_ <= _zz_38_;
_zz_6_ <= _zz_39_;
_zz_7_ <= _zz_40_;
_zz_8_ <= _zz_41_;
end
if((system_mainBusDecoder_logic_masterPipelined_cmd_valid && system_mainBusDecoder_logic_masterPipelined_cmd_ready))begin
system_mainBusDecoder_logic_rspSourceId <= system_mainBusDecoder_logic_hits_1;
end
end
always @ (posedge io_mainClk) begin
debug_resetOut_regNext <= _zz_36_;
end
always @ (posedge io_mainClk or posedge resetCtrl_mainClkReset) begin
if (resetCtrl_mainClkReset) begin
_zz_9_ <= 1\'b0;
end else begin
_zz_9_ <= (_zz_51_ && _zz_34_);
end
end
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: openMSP430_defines.v
//
// *Module Description:
// openMSP430 Configuration file
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
`define OMSP_NO_INCLUDE
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
`define VERY_LONG_TIMEOUT
//============================================================================
//============================================================================
// BASIC SYSTEM CONFIGURATION
//============================================================================
//============================================================================
//
// Note: the sum of program, data and peripheral memory spaces must not
// exceed 64 kB
//
// Program Memory Size:
// Uncomment the required memory size
//-------------------------------------------------------
//`define PMEM_SIZE_CUSTOM
//`define PMEM_SIZE_59_KB
//`define PMEM_SIZE_55_KB
//`define PMEM_SIZE_54_KB
//`define PMEM_SIZE_51_KB
//`define PMEM_SIZE_48_KB
//`define PMEM_SIZE_41_KB
//`define PMEM_SIZE_32_KB
//`define PMEM_SIZE_24_KB
//`define PMEM_SIZE_16_KB
//`define PMEM_SIZE_12_KB
//`define PMEM_SIZE_8_KB
`define PMEM_SIZE_4_KB
//`define PMEM_SIZE_2_KB
//`define PMEM_SIZE_1_KB
// Data Memory Size:
// Uncomment the required memory size
//-------------------------------------------------------
//`define DMEM_SIZE_CUSTOM
//`define DMEM_SIZE_32_KB
//`define DMEM_SIZE_24_KB
//`define DMEM_SIZE_16_KB
//`define DMEM_SIZE_10_KB
//`define DMEM_SIZE_8_KB
//`define DMEM_SIZE_5_KB
//`define DMEM_SIZE_4_KB
//`define DMEM_SIZE_2p5_KB
`define DMEM_SIZE_2_KB
//`define DMEM_SIZE_1_KB
//`define DMEM_SIZE_512_B
//`define DMEM_SIZE_256_B
//`define DMEM_SIZE_128_B
// Include/Exclude Hardware Multiplier
`define MULTIPLIER
// Include/Exclude Serial Debug interface
`define DBG_EN
//============================================================================
//============================================================================
// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
//============================================================================
//============================================================================
//-------------------------------------------------------
// Custom user version number
//-------------------------------------------------------
// This 5 bit field can be freely used in order to allow
// custom identification of the system through the debug
// interface.
// (see CPU_ID.USER_VERSION field in the documentation)
//-------------------------------------------------------
`define USER_VERSION 5\'b00000
//-------------------------------------------------------
// Include/Exclude Watchdog timer
//-------------------------------------------------------
// When excluded, the following functionality will be
// lost:
// - Watchog (both interval and watchdog modes)
// - NMI interrupt edge selection
// - Possibility to generate a software PUC reset
//-------------------------------------------------------
//`define WATCHDOG
//-------------------------------------------------------
// Include/Exclude DMA interface support
//-------------------------------------------------------
//`define DMA_IF_EN
//-------------------------------------------------------
// Include/Exclude Non-Maskable-Interrupt support
//-------------------------------------------------------
`define NMI
//-------------------------------------------------------
// Number of available IRQs
//-------------------------------------------------------
// Indicates the number of interrupt vectors supported
// (16, 32 or 64).
//-------------------------------------------------------
`define IRQ_16
//`define IRQ_32
//`define IRQ_64
//-------------------------------------------------------
// Input synchronizers
//-------------------------------------------------------
// In some cases, the asynchronous input ports might
// already be synchronized externally.
// If an extensive CDC design review showed that this
// is really the case, the individual synchronizers
// can be disabled with the following defines.
//
// Notes:
// - all three signals are all sampled in the MCLK domain
//
// - the dbg_en signal reset the debug interface
// when 0. Therefore make sure it is glitch free.
//
//-------------------------------------------------------
`define SYNC_NMI
//`define SYNC_CPU_EN
//`define SYNC_DBG_EN
//-------------------------------------------------------
// Peripheral Memory Space:
//-------------------------------------------------------
// The original MSP430 architecture map the peripherals
// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
// The following defines allow you to expand this space
// up to 32 kB (i.e. from 0x0000 to 0x7fff).
// As a consequence, the data memory mapping will be
// shifted up and a custom linker script will therefore
// be required by the GCC compiler.
//-------------------------------------------------------
//`define PER_SIZE_CUSTOM
//`define PER_SIZE_32_KB
//`define PER_SIZE_16_KB
//`define PER_SIZE_8_KB
//`define PER_SIZE_4_KB
//`define PER_SIZE_2_KB
//`define PER_SIZE_1_KB
`define PER_SIZE_512_B
//-------------------------------------------------------
// Defines the debugger CPU_CTL.RST_BRK_EN reset value
// (CPU break on PUC reset)
//-------------------------------------------------------
// When defined, the CPU will automatically break after
// a PUC occurrence by default. This is typically useful
// when the program memory can only be initialized through
// the serial debug interface.
//-------------------------------------------------------
`define DBG_RST_BRK_EN
//============================================================================
//============================================================================
// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
//============================================================================
//============================================================================
//
// IMPORTANT NOTE: Please update following configuration options ONLY if
// you have a good reason to do so... and if you know what
// you are doing :-P
//
//============================================================================
//-------------------------------------------------------
// Select serial debug interface protocol
//-------------------------------------------------------
// DBG_UART -> Enable UART (8N1) debug interface
// DBG_I2C -> Enable I2C debug interface
//-------------------------------------------------------
`define DBG_UART
//`define DBG_I2C
//-------------------------------------------------------
// Enable the I2C broadcast address
//-------------------------------------------------------
// For multicore systems, a common I2C broadcast address
// can be given to all oMSP cores in order to
// synchronously RESET, START, STOP, or STEP all CPUs
// at once with a single I2C command.
// If you have a single openMSP430 in your system,
// this option can stay commented-out.
//-------------------------------------------------------
//`define DBG_I2C_BROADCAST
//-------------------------------------------------------
// Number of hardware breakpoint/watchpoint units
// (each unit contains two hardware addresses available
// for breakpoints or watchpoints):
// - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
// - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
// - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
// - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
//-------------------------------------------------------
// Please keep in mind that hardware breakpoints only
// make sense whenever the program memory is not an SRAM
// (i.e. Flash/OTP/ROM/...) or when you are interested
// in data breakpoints.
//-------------------------------------------------------
//`define DBG_HWBRK_0
//`define DBG_HWBRK_1
//`define DBG_HWBRK_2
//`define DBG_HWBRK_3
//-------------------------------------------------------
// Enable/Disable the hardware breakpoint RANGE mode
//-------------------------------------------------------
// When enabled this feature allows the hardware breakpoint
// units to stop the cpu whenever an instruction or data
// access lays within an address range.
// Note that this feature is not supported by GDB.
//-------------------------------------------------------
//`define DBG_HWBRK_RANGE
//-------------------------------------------------------
// Custom Program/Data and Peripheral Memory Spaces
//-------------------------------------------------------
// The following values are valid only if the
// corresponding *_SIZE_CUSTOM defines are uncommented:
//
// - *_SIZE : size of the section in bytes.
// - *_AWIDTH : address port width, this value must allow
// to address all WORDS of the section
// (i.e. the *_SIZE divided by 2)
//-------------------------------------------------------
// Custom Program memory (enabled with PMEM_SIZE_CUSTOM)
`define PMEM_CUSTOM_AWIDTH 10
`define PMEM_CUSTOM_SIZE 2048
// Custom Data memory (enabled with DMEM_SIZE_CUSTOM)
`define DMEM_CUSTOM_AWIDTH 6
`define DMEM_CUSTOM_SIZE 128
// Custom Peripheral memory (enabled with PER_SIZE_CUSTOM)
`define PER_CUSTOM_AWIDTH 8
`define PER_CUSTOM_SIZE 512
//-------------------------------------------------------
// ASIC version
//-------------------------------------------------------
// When uncommented, this define will enable the
// ASIC system configuration section (see below) and
// will activate scan support for production test.
//
// WARNING: if you target an FPGA, leave this define
// commented.
//-------------------------------------------------------
//`define ASIC
//============================================================================
//============================================================================
// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS/PROFESSIONALS ONLY !!!! )
//============================================================================
//============================================================================
`ifdef ASIC
//===============================================================
// FINE GRAINED CLOCK GATING
//===============================================================
//-------------------------------------------------------
// When uncommented, this define will enable the fine
// grained clock gating of all registers in the core.
//-------------------------------------------------------
`define CLOCK_GATING
//===============================================================
// ASIC CLOCKING
//===============================================================
//-------------------------------------------------------
// When uncommented, this define will enable the ASIC
// architectural clock gating as well as the advanced low
// power modes support (most common).
// Comment this out in order to get FPGA-like clocking.
//-------------------------------------------------------
`define ASIC_CLOCKING
`ifdef ASIC_CLOCKING
//===============================================================
// LFXT CLOCK DOMAIN
//===============================================================
//-------------------------------------------------------
// When uncommented, this define will enable the lfxt_clk
// clock domain.
// When commented out, the whole chip is clocked with dco_clk.
//-------------------------------------------------------
`define LFXT_DOMAIN
//===============================================================
// CLOCK MUXES
//===============================================================
//-------------------------------------------------------
// MCLK: Clock Mux
//-------------------------------------------------------
// When uncommented, this define will enable the
// MCLK clock MUX allowing the selection between
// DCO_CLK and LFXT_CLK with the BCSCTL2.SELMx register.
// When commented, DCO_CLK is selected.
//-------------------------------------------------------
`define MCLK_MUX
//-------------------------------------------------------
// SMCLK: Clock Mux
//-------------------------------------------------------
// When uncommented, this define will enable the
// SMCLK clock MUX allowing the selection between
// DCO_CLK and LFXT_CLK with the BCSCTL2.SELS register.
// When commented, DCO_CLK is selected.
//-------------------------------------------------------
`define SMCLK_MUX
//-------------------------------------------------------
// WATCHDOG: Clock Mux
//-------------------------------------------------------
// When uncommented, this define will enable the
// Watchdog clock MUX allowing the selection between
// ACLK and SMCLK with the WDTCTL.WDTSSEL register.
// When commented out, ACLK is selected if the
// WATCHDOG_NOMUX_ACLK define is uncommented, SMCLK is
// selected otherwise.
//-------------------------------------------------------
`define WATCHDOG_MUX
//`define WATCHDOG_NOMUX_ACLK
//===============================================================
// CLOCK DIVIDERS
//===============================================================
//-------------------------------------------------------
// MCLK: Clock divider
//-------------------------------------------------------
// When uncommented, this define will enable the
// MCLK clock divider (/1/2/4/8)
//-------------------------------------------------------
`define MCLK_DIVIDER
//-------------------------------------------------------
// SMCLK: Clock divider (/1/2/4/8)
//-------------------------------------------------------
// When uncommented, this define will enable the
// SMCLK clock divider
//-------------------------------------------------------
`define SMCLK_DIVIDER
//-------------------------------------------------------
// ACLK: Clock divider (/1/2/4/8)
//-------------------------------------------------------
// When uncommented, this define will enable the
// ACLK clock divider
//-------------------------------------------------------
`define ACLK_DIVIDER
//===============================================================
// LOW POWER MODES
//===============================================================
//-------------------------------------------------------
// LOW POWER MODE: CPUOFF
//-------------------------------------------------------
// When uncommented, this define will include the
// clock gate allowing to switch off MCLK in
// all low power modes: LPM0, LPM1, LPM2, LPM3, LPM4
//-------------------------------------------------------
`define CPUOFF_EN
//-------------------------------------------------------
// LOW POWER MODE: SCG0
//-------------------------------------------------------
// When uncommented, this define will enable the
// DCO_ENABLE/WKUP port control (always 1 when commented).
// This allows to switch off the DCO oscillator in the
// following low power modes: LPM1, LPM3, LPM4
//-------------------------------------------------------
`define SCG0_EN
//-------------------------------------------------------
// LOW POWER MODE: SCG1
//-------------------------------------------------------
// When uncommented, this define will include the
// clock gate allowing to switch off SMCLK in
// the following low power modes: LPM2, LPM3, LPM4
//-------------------------------------------------------
`define SCG1_EN
//-------------------------------------------------------
// LOW POWER MODE: OSCOFF
//-------------------------------------------------------
// When uncommented, this define will include the
// LFXT_CLK clock gate and enable the LFXT_ENABLE/WKUP
// port control (always 1 when commented).
// This allows to switch off the low frequency oscillator
// in the following low power modes: LPM4
//-------------------------------------------------------
`define OSCOFF_EN
//-------------------------------------------------------
// SCAN REPAIR NEG-EDGE CLOCKED FLIP-FLOPS
//-------------------------------------------------------
// When uncommented, a scan mux will be infered to
// replace all inverted clocks with regular ones when
// in scan mode.
//
// Note: standard scan insertion tool can usually deal
// with mixed rising/falling edge FF... so there
// is usually no need to uncomment this.
//-------------------------------------------------------
//`define SCAN_REPAIR_INV_CLOCKS
`endif
`endif
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//
// PROGRAM, DATA & PERIPHERAL MEMORY CONFIGURATION
//==================================================
// Program Memory Size
`ifdef PMEM_SIZE_59_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 60416
`endif
`ifdef PMEM_SIZE_55_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 56320
`endif
`ifdef PMEM_SIZE_54_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 55296
`endif
`ifdef PMEM_SIZE_51_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 52224
`endif
`ifdef PMEM_SIZE_48_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 49152
`endif
`ifdef PMEM_SIZE_41_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 41984
`endif
`ifdef PMEM_SIZE_32_KB
`define PMEM_AWIDTH 14
`define PMEM_SIZE 32768
`endif
`ifdef PMEM_SIZE_24_KB
`define PMEM_AWIDTH 14
`define PMEM_SIZE 24576
`endif
`ifdef PMEM_SIZE_16_KB
`define PMEM_AWIDTH 13
`define PMEM_SIZE 16384
`endif
`ifdef PMEM_SIZE_12_KB
`define PMEM_AWIDTH 13
`define PMEM_SIZE 12288
`endif
`ifdef PMEM_SIZE_8_KB
`define PMEM_AWIDTH 12
`define PMEM_SIZE 8192
`endif
`ifdef PMEM_SIZE_4_KB
`define PMEM_AWIDTH 11
`define PMEM_SIZE 4096
`endif
`ifdef PMEM_SIZE_2_KB
`define PMEM_AWIDTH 10
`define PMEM_SIZE 2048
`endif
`ifdef PMEM_SIZE_1_KB
`define PMEM_AWIDTH 9
`define PMEM_SIZE 1024
`endif
`ifdef PMEM_SIZE_CUSTOM
`define PMEM_AWIDTH `PMEM_CUSTOM_AWIDTH
`define PMEM_SIZE `PMEM_CUSTOM_SIZE
`endif
// Data Memory Size
`ifdef DMEM_SIZE_32_KB
`define DMEM_AWIDTH 14
`define DMEM_SIZE 32768
`endif
`ifdef DMEM_SIZE_24_KB
`define DMEM_AWIDTH 14
`define DMEM_SIZE 24576
`endif
`ifdef DMEM_SIZE_16_KB
`define DMEM_AWIDTH 13
`define DMEM_SIZE 16384
`endif
`ifdef DMEM_SIZE_10_KB
`define DMEM_AWIDTH 13
`define DMEM_SIZE 10240
`endif
`ifdef DMEM_SIZE_8_KB
`define DMEM_AWIDTH 12
`define DMEM_SIZE 8192
`endif
`ifdef DMEM_SIZE_5_KB
`define DMEM_AWIDTH 12
`define DMEM_SIZE 5120
`endif
`ifdef DMEM_SIZE_4_KB
`define DMEM_AWIDTH 11
`define DMEM_SIZE 4096
`endif
`ifdef DMEM_SIZE_2p5_KB
`define DMEM_AWIDTH 11
`define DMEM_SIZE 2560
`endif
`ifdef DMEM_SIZE_2_KB
`define DMEM_AWIDTH 10
`define DMEM_SIZE 2048
`endif
`ifdef DMEM_SIZE_1_KB
`define DMEM_AWIDTH 9
`define DMEM_SIZE 1024
`endif
`ifdef DMEM_SIZE_512_B
`define DMEM_AWIDTH 8
`define DMEM_SIZE 512
`endif
`ifdef DMEM_SIZE_256_B
`define DMEM_AWIDTH 7
`define DMEM_SIZE 256
`endif
`ifdef DMEM_SIZE_128_B
`define DMEM_AWIDTH 6
`define DMEM_SIZE 128
`endif
`ifdef DMEM_SIZE_CUSTOM
`define DMEM_AWIDTH `DMEM_CUSTOM_AWIDTH
`define DMEM_SIZE `DMEM_CUSTOM_SIZE
`endif
// Peripheral Memory Size
`ifdef PER_SIZE_32_KB
`define PER_AWIDTH 14
`define PER_SIZE 32768
`endif
`ifdef PER_SIZE_16_KB
`define PER_AWIDTH 13
`define PER_SIZE 16384
`endif
`ifdef PER_SIZE_8_KB
`define PER_AWIDTH 12
`define PER_SIZE 8192
`endif
`ifdef PER_SIZE_4_KB
`define PER_AWIDTH 11
`define PER_SIZE 4096
`endif
`ifdef PER_SIZE_2_KB
`define PER_AWIDTH 10
`define PER_SIZE 2048
`endif
`ifdef PER_SIZE_1_KB
`define PER_AWIDTH 9
`define PER_SIZE 1024
`endif
`ifdef PER_SIZE_512_B
`define PER_AWIDTH 8
`define PER_SIZE 512
`endif
`ifdef PER_SIZE_CUSTOM
`define PER_AWIDTH `PER_CUSTOM_AWIDTH
`define PER_SIZE `PER_CUSTOM_SIZE
`endif
// Data Memory Base Adresses
`define DMEM_BASE `PER_SIZE
// Program & Data Memory most significant address bit (for 16 bit words)
`define PMEM_MSB `PMEM_AWIDTH-1
`define DMEM_MSB `DMEM_AWIDTH-1
`define PER_MSB `PER_AWIDTH-1
// Number of available IRQs
`ifdef IRQ_16
`define IRQ_NR 16
`endif
`ifdef IRQ_32
`define IRQ_NR 32
`define IRQ_NR_GE_32
`endif
`ifdef IRQ_64
`define IRQ_NR 64
`define IRQ_NR_GE_32
`endif
//
// STATES, REGISTER FIELDS, ...
//======================================
// Instructions type
`define INST_SO 0
`define INST_JMP 1
`define INST_TO 2
// Single-operand arithmetic
`define RRC 0
`define SWPB 1
`define RRA 2
`define SXT 3
`define PUSH 4
`define CALL 5
`define RETI 6
`define IRQ 7
// Conditional jump
`define JNE 0
`define JEQ 1
`define JNC 2
`define JC 3
`define JN 4
`define JGE 5
`define JL 6
`define JMP 7
// Two-operand arithmetic
`define MOV 0
`define ADD 1
`define ADDC 2
`define SUBC 3
`define SUB 4
`define CMP 5
`define DADD 6
`define BIT 7
`define BIC 8
`define BIS 9
`define XOR 10
`define AND 11
// Addressing modes
`define DIR 0
`define IDX 1
`define INDIR 2
`define INDIR_I 3
`define SYMB 4
`define IMM 5
`define ABS 6
`define CONST 7
// Instruction state machine
`define I_IRQ_FETCH 3\'h0
`define I_IRQ_DONE 3\'h1
`define I_DEC 3\'h2
`define I_EXT1 3\'h3
`define I_EXT2 3\'h4
`define I_IDLE 3\'h5
// Execution state machine
// (swapped E_IRQ_0 and E_IRQ_2 values to suppress glitch generation warning from lint tool)
`define E_IRQ_0 4\'h2
`define E_IRQ_1 4\'h1
`define E_IRQ_2 4\'h0
`define E_IRQ_3 4\'h3
`define E_IRQ_4 4\'h4
`define E_SRC_AD 4\'h5
`define E_SRC_RD 4\'h6
`define E_SRC_WR 4\'h7
`define E_DST_AD 4\'h8
`define E_DST_RD 4\'h9
`define E_DST_WR 4\'hA
`define E_EXEC 4\'hB
`define E_JUMP 4\'hC
`define E_IDLE 4\'hD
// ALU control signals
`define ALU_SRC_INV 0
`define ALU_INC 1
`define ALU_INC_C 2
`define ALU_ADD 3
`define ALU_AND 4
`define ALU_OR 5
`define ALU_XOR 6
`define ALU_DADD 7
`define ALU_STAT_7 8
`define ALU_STAT_F 9
`define ALU_SHIFT 10
`define EXEC_NO_WR 11
// Debug interface
`define DBG_UART_WR 18
`define DBG_UART_BW 17
`define DBG_UART_ADDR 16:11
// Debug interface CPU_CTL register
`define HALT 0
`define RUN 1
`define ISTEP 2
`define SW_BRK_EN 3
`define FRZ_BRK_EN 4
`define RST_BRK_EN 5
`define CPU_RST 6
// Debug interface CPU_STAT register
`define HALT_RUN 0
`define PUC_PND 1
`define SWBRK_PND 3
`define HWBRK0_PND 4
`define HWBRK1_PND 5
// Debug interface BRKx_CTL register
`define BRK_MODE_RD 0
`define BRK_MODE_WR 1
`define BRK_MODE 1:0
`define BRK_EN 2
`define BRK_I_EN 3
`define BRK_RANGE 4
// Basic clock module: BCSCTL1 Control Register
`define DIVAx 5:4
`define DMA_CPUOFF 0
`define DMA_OSCOFF 1
`define DMA_SCG0 2
`define DMA_SCG1 3
// Basic clock module: BCSCTL2 Control Register
`define SELMx 7
`define DIVMx 5:4
`define SELS 3
`define DIVSx 2:1
// MCLK Clock gate
`ifdef CPUOFF_EN
`define MCLK_CGATE
`else
`ifdef MCLK_DIVIDER
`define MCLK_CGATE
`endif
`endif
// SMCLK Clock gate
`ifdef SCG1_EN
`define SMCLK_CGATE
`else
`ifdef SMCLK_DIVIDER
`define SMCLK_CGATE
`endif
`endif
//
// DEBUG INTERFACE EXTRA CONFIGURATION
//======================================
// Debug interface: CPU version
// 1 - FPGA support only (Pre-BSD licence era)
// 2 - Add ASIC support
// 3 - Add DMA interface support
`define CPU_VERSION 3\'h3
// Debug interface: Software breakpoint opcode
`define DBG_SWBRK_OP 16\'h4343
// Debug UART interface auto data synchronization
// If the following define is commented out, then
// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
// defined.
`define DBG_UART_AUTO_SYNC
// Debug UART interface data rate
// In order to properly setup the UART debug interface, you
// need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
// the chosen BAUD rate from the UART interface.
//
//`define DBG_UART_BAUD 9600
//`define DBG_UART_BAUD 19200
//`define DBG_UART_BAUD 38400
//`define DBG_UART_BAUD 57600
//`define DBG_UART_BAUD 115200
//`define DBG_UART_BAUD 230400
//`define DBG_UART_BAUD 460800
//`define DBG_UART_BAUD 576000
//`define DBG_UART_BAUD 921600
`define DBG_UART_BAUD 2000000
`define DBG_DCO_FREQ 20000000
`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
// Debug interface input synchronizer
`define SYNC_DBG_UART_RXD
// Enable/Disable the hardware breakpoint RANGE mode
`ifdef DBG_HWBRK_RANGE
`define HWBRK_RANGE 1\'b1
`else
`define HWBRK_RANGE 1\'b0
`endif
// Counter width for the debug interface UART
`define DBG_UART_XFER_CNT_W 16
// Check configuration
`ifdef DBG_EN
`ifdef DBG_UART
`ifdef DBG_I2C
CONFIGURATION ERROR: I2C AND UART DEBUG INTERFACE ARE BOTH ENABLED
`endif
`else
`ifdef DBG_I2C
`else
CONFIGURATION ERROR: I2C OR UART DEBUG INTERFACE SHOULD BE ENABLED
`endif
`endif
`endif
//
// MULTIPLIER CONFIGURATION
//======================================
// If uncommented, the following define selects
// the 16x16 multiplier (1 cycle) instead of the
// default 16x8 multplier (2 cycles)
//`define MPY_16x16
//======================================
// CONFIGURATION CHECKS
//======================================
`ifdef IRQ_16
`ifdef IRQ_32
CONFIGURATION ERROR: ONLY ONE OF THE IRQ NUMBER OPTION CAN BE SELECTED
`endif
`ifdef IRQ_64
CONFIGURATION ERROR: ONLY ONE OF THE IRQ NUMBER OPTION CAN BE SELECTED
`endif
`endif
`ifdef IRQ_32
`ifdef IRQ_64
CONFIGURATION ERROR: ONLY ONE OF THE IRQ NUMBER OPTION CAN BE SELECTED
`endif
`endif
`ifdef LFXT_DOMAIN
`else
`ifdef MCLK_MUX
CONFIGURATION ERROR: THE MCLK_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
`endif
`ifdef SMCLK_MUX
CONFIGURATION ERROR: THE SMCLK_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
`endif
`ifdef WATCHDOG_MUX
CONFIGURATION ERROR: THE WATCHDOG_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
`else
`ifdef WATCHDOG_NOMUX_ACLK
CONFIGURATION ERROR: THE WATCHDOG_NOMUX_ACLK CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
`endif
`endif
`ifdef OSCOFF_EN
CONFIGURATION ERROR: THE OSCOFF LOW POWER MODE CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
`endif
`endif
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: msp_debug.v
//
// *Module Description:
// MSP430 core debug utility signals
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module msp_debug (
// OUTPUTs
e_state, // Execution state
i_state, // Instruction fetch state
inst_cycle, // Cycle number within current instruction
inst_full, // Currently executed instruction (full version)
inst_number, // Instruction number since last system reset
inst_pc, // Instruction Program counter
inst_short, // Currently executed instruction (short version)
// INPUTs
mclk, // Main system clock
puc_rst // Main system reset
);
// OUTPUTs
//============
output [8*32-1:0] e_state; // Execution state
output [8*32-1:0] i_state; // Instruction fetch state
output [31:0] inst_cycle; // Cycle number within current instruction
output [8*32-1:0] inst_full; // Currently executed instruction (full version)
output [31:0] inst_number; // Instruction number since last system reset
output [15:0] inst_pc; // Instruction Program counter
output [8*32-1:0] inst_short; // Currently executed instruction (short version)
// INPUTs
//============
input mclk; // Main system clock
input puc_rst; // Main system reset
//=============================================================================
// 1) ASCII FORMATING FUNCTIONS
//=============================================================================
// This function simply concatenates two strings together, ignorning the NULL
// at the end of string2.
// The specified number of space will be inserted between string1 and string2
function [64*8-1:0] myFormat;
input [32*8-1:0] string1;
input [32*8-1:0] string2;
input [3:0] space;
integer i,j;
begin
myFormat = 0;
`ifdef VXL\t\t\t// no +:
`else
j = 0;
for ( i=0; i < 32; i=i+1) // Copy string2
begin
\t myFormat[8*i +: 8] = string2[8*i +: 8];
\t if ((string2[8*i +: 8] == 0) && (j == 0)) j=i;
end
for ( i=0; i < space; i=i+1) // Add spaces
myFormat[8*(j+i) +: 8] = " ";
j=j+space;
for ( i=0; i < 32; i=i+1) // Copy string1
myFormat[8*(j+i) +: 8] = string1[8*i +: 8];
`endif
end
endfunction
//=============================================================================
// 2) CONNECTIONS TO MSP430 CORE INTERNALS
//=============================================================================
wire [2:0] i_state_bin = tb_openMSP430.dut.frontend_0.i_state;
wire [3:0] e_state_bin = tb_openMSP430.dut.frontend_0.e_state;
wire decode = tb_openMSP430.dut.frontend_0.decode;
wire [15:0] ir = tb_openMSP430.dut.frontend_0.ir;
wire irq_detect = tb_openMSP430.dut.frontend_0.irq_detect;
wire [3:0] irq_num = tb_openMSP430.dut.frontend_0.irq_num;
wire [15:0] pc = tb_openMSP430.dut.frontend_0.pc;
//=============================================================================
// 3) GENERATE DEBUG SIGNALS
//=============================================================================
// Instruction fetch state
//=========================
reg [8*32-1:0] i_state;
always @(i_state_bin)
case(i_state_bin)
3\'h0 : i_state = "IRQ_FETCH";
3\'h1 : i_state = "IRQ_DONE";
3\'h2 : i_state = "DEC";
3\'h3 : i_state = "EXT1";
3\'h4 : i_state = "EXT2";
3\'h5 : i_state = "IDLE";
default : i_state = "XXXXX";
endcase
// Execution state
//=========================
reg [8*32-1:0] e_state;
always @(e_state_bin)
case(e_state_bin)
4\'h2 : e_state = "IRQ_0";
4\'h1 : e_state = "IRQ_1";
4\'h0 : e_state = "IRQ_2";
4\'h3 : e_state = "IRQ_3";
4\'h4 : e_state = "IRQ_4";
4\'h5 : e_state = "SRC_AD";
4\'h6 : e_state = "SRC_RD";
4\'h7 : e_state = "SRC_WR";
4\'h8 : e_state = "DST_AD";
4\'h9 : e_state = "DST_RD";
4\'hA : e_state = "DST_WR";
4\'hB : e_state = "EXEC";
4\'hC : e_state = "JUMP";
4\'hD : e_state = "IDLE";
default : e_state = "xxxx";
endcase
// Count instruction number & cycles
//====================================
reg [31:0] inst_number;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) inst_number <= 0;
else if (decode) inst_number <= inst_number+1;
reg [31:0] inst_cycle;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) inst_cycle <= 0;
else if (decode) inst_cycle <= 0;
else inst_cycle <= inst_cycle+1;
// Decode instruction
//====================================
// Buffer opcode
reg [15:0] opcode;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) opcode <= 0;
else if (decode) opcode <= ir;
// Interrupts
reg irq;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) irq <= 1\'b1;
else if (decode) irq <= irq_detect;
// Instruction type
reg [8*32-1:0] inst_type;
always @(opcode or irq)
if (irq)
inst_type = "IRQ";
else
case(opcode[15:13])
3\'b000 : inst_type = "SIG-OP";
3\'b001 : inst_type = "JUMP";
default : inst_type = "TWO-OP";
endcase
// Instructions name
reg [8*32-1:0] inst_name;
always @(opcode or inst_type or irq_num)
if (inst_type=="IRQ")
case(irq_num[3:0])
4\'b0000 : inst_name = "IRQ 0";
4\'b0001 : inst_name = "IRQ 1";
4\'b0010 : inst_name = "IRQ 2";
4\'b0011 : inst_name = "IRQ 3";
4\'b0100 : inst_name = "IRQ 4";
4\'b0101 : inst_name = "IRQ 5";
4\'b0110 : inst_name = "IRQ 6";
4\'b0111 : inst_name = "IRQ 7";
4\'b1000 : inst_name = "IRQ 8";
4\'b1001 : inst_name = "IRQ 9";
4\'b1010 : inst_name = "IRQ 10";
4\'b1011 : inst_name = "IRQ 11";
4\'b1100 : inst_name = "IRQ 12";
4\'b1101 : inst_name = "IRQ 13";
4\'b1110 : inst_name = "NMI";
default : inst_name = "RESET";
endcase
else if (inst_type=="SIG-OP")
case(opcode[15:7])
9\'b000100_000 : inst_name = "RRC";
9\'b000100_001 : inst_name = "SWPB";
9\'b000100_010 : inst_name = "RRA";
9\'b000100_011 : inst_name = "SXT";
9\'b000100_100 : inst_name = "PUSH";
9\'b000100_101 : inst_name = "CALL";
9\'b000100_110 : inst_name = "RETI";
default : inst_name = "xxxx";
endcase
else if (inst_type=="JUMP")
case(opcode[15:10])
6\'b001_000 : inst_name = "JNE";
6\'b001_001 : inst_name = "JEQ";
6\'b001_010 : inst_name = "JNC";
6\'b001_011 : inst_name = "JC";
6\'b001_100 : inst_name = "JN";
6\'b001_101 : inst_name = "JGE";
6\'b001_110 : inst_name = "JL";
6\'b001_111 : inst_name = "JMP";
default : inst_name = "xxxx";
endcase
else if (inst_type=="TWO-OP")
case(opcode[15:12])
4\'b0100 : inst_name = "MOV";
4\'b0101 : inst_name = "ADD";
4\'b0110 : inst_name = "ADDC";
4\'b0111 : inst_name = "SUBC";
4\'b1000 : inst_name = "SUB";
4\'b1001 : inst_name = "CMP";
4\'b1010 : inst_name = "DADD";
4\'b1011 : inst_name = "BIT";
4\'b1100 : inst_name = "BIC";
4\'b1101 : inst_name = "BIS";
4\'b1110 : inst_name = "XOR";
4\'b1111 : inst_name = "AND";
default : inst_name = "xxxx";
endcase
// Instructions byte/word mode
reg [8*32-1:0] inst_bw;
always @(opcode or inst_type)
if (inst_type=="IRQ")
inst_bw = "";
else if (inst_type=="SIG-OP")
inst_bw = opcode[6] ? ".B" : "";
else if (inst_type=="JUMP")
inst_bw = "";
else if (inst_type=="TWO-OP")
inst_bw = opcode[6] ? ".B" : "";
// Source register
reg [8*32-1:0] inst_src;
wire [3:0] src_reg = (inst_type=="SIG-OP") ? opcode[3:0] : opcode[11:8];
always @(src_reg or inst_type)
if (inst_type=="IRQ")
inst_src = "";
else if (inst_type=="JUMP")
inst_src = "";
else if ((inst_type=="SIG-OP") || (inst_type=="TWO-OP"))
case(src_reg)
4\'b0000 : inst_src = "r0";
4\'b0001 : inst_src = "r1";
4\'b0010 : inst_src = "r2";
4\'b0011 : inst_src = "r3";
4\'b0100 : inst_src = "r4";
4\'b0101 : inst_src = "r5";
4\'b0110 : inst_src = "r6";
4\'b0111 : inst_src = "r7";
4\'b1000 : inst_src = "r8";
4\'b1001 : inst_src = "r9";
4\'b1010 : inst_src = "r10";
4\'b1011 : inst_src = "r11";
4\'b1100 : inst_src = "r12";
4\'b1101 : inst_src = "r13";
4\'b1110 : inst_src = "r14";
default : inst_src = "r15";
endcase
// Destination register
reg [8*32-1:0] inst_dst;
always @(opcode or inst_type)
if (inst_type=="IRQ")
inst_dst = "";
else if (inst_type=="SIG-OP")
inst_dst = "";
else if (inst_type=="JUMP")
inst_dst = "";
else if (inst_type=="TWO-OP")
case(opcode[3:0])
4\'b0000 : inst_dst = "r0";
4\'b0001 : inst_dst = "r1";
4\'b0010 : inst_dst = "r2";
4\'b0011 : inst_dst = "r3";
4\'b0100 : inst_dst = "r4";
4\'b0101 : inst_dst = "r5";
4\'b0110 : inst_dst = "r6";
4\'b0111 : inst_dst = "r7";
4\'b1000 : inst_dst = "r8";
4\'b1001 : inst_dst = "r9";
4\'b1010 : inst_dst = "r10";
4\'b1011 : inst_dst = "r11";
4\'b1100 : inst_dst = "r12";
4\'b1101 : inst_dst = "r13";
4\'b1110 : inst_dst = "r14";
default : inst_dst = "r15";
endcase
// Source Addressing mode
reg [8*32-1:0] inst_as;
always @(inst_type or src_reg or opcode or inst_src)
begin
if (inst_type=="IRQ")
inst_as = "";
else if (inst_type=="JUMP")
inst_as = "";
else if (src_reg==4\'h3) // Addressing mode using R3
case (opcode[5:4])
2\'b11 : inst_as = "#-1";
2\'b10 : inst_as = "#2";
2\'b01 : inst_as = "#1";
default: inst_as = "#0";
endcase
else if (src_reg==4\'h2) // Addressing mode using R2
case (opcode[5:4])
2\'b11 : inst_as = "#8";
2\'b10 : inst_as = "#4";
2\'b01 : inst_as = "&EDE";
default: inst_as = inst_src;
endcase
else if (src_reg==4\'h0) // Addressing mode using R0
case (opcode[5:4])
2\'b11 : inst_as = "#N";
2\'b10 : inst_as = myFormat("@", inst_src, 0);
2\'b01 : inst_as = "EDE";
default: inst_as = inst_src;
endcase
else // General Addressing mode
case (opcode[5:4])
2\'b11 : begin
\t inst_as = myFormat("@", inst_src, 0);
\t inst_as = myFormat(inst_as, "+", 0);
end
2\'b10 : inst_as = myFormat("@", inst_src, 0);
2\'b01 : begin
\t inst_as = myFormat("x(", inst_src, 0);
\t inst_as = myFormat(inst_as, ")", 0);
end
default: inst_as = inst_src;
endcase
end
// Destination Addressing mode
reg [8*32-1:0] inst_ad;
always @(opcode or inst_type or inst_dst)
begin
if (inst_type!="TWO-OP")
inst_ad = "";
else if (opcode[3:0]==4\'h2) // Addressing mode using R2
case (opcode[7])
\t 1\'b1 : inst_ad = "&EDE";
\t default: inst_ad = inst_dst;
endcase
else if (opcode[3:0]==4\'h0) // Addressing mode using R0
case (opcode[7])
\t 2\'b1 : inst_ad = "EDE";
\t default: inst_ad = inst_dst;
endcase
else // General Addressing mode
case (opcode[7])
\t 2\'b1 : begin
\t inst_ad = myFormat("x(", inst_dst, 0);
\t inst_ad = myFormat(inst_ad, ")", 0);
end
\t default: inst_ad = inst_dst;
endcase
end
// Currently executed instruction
//================================
wire [8*32-1:0] inst_short = inst_name;
reg [8*32-1:0] inst_full;
always @(inst_type or inst_name or inst_bw or inst_as or inst_ad)
begin
inst_full = myFormat(inst_name, inst_bw, 0);
inst_full = myFormat(inst_full, inst_as, 1);
if (inst_type=="TWO-OP")
inst_full = myFormat(inst_full, ",", 0);
inst_full = myFormat(inst_full, inst_ad, 1);
if (opcode==16\'h4303)
inst_full = "NOP";
if (opcode==`DBG_SWBRK_OP)
inst_full = "SBREAK";
\t\t
end
// Instruction program counter
//================================
reg [15:0] inst_pc;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) inst_pc <= 16\'h0000;
else if (decode) inst_pc <= pc;
endmodule // msp_debug
|
`timescale 1 ns / 1 ps
//`define DEBUG
module system_tb;
integer i;\t
\treg clk = 1;
\talways #5 clk = ~clk;
\treg resetn = 0;
\tinitial begin
\t\tif ($test$plusargs("vcd")) begin
\t\t\t$dumpfile("system.vcd");
\t\t $dumpvars(0, system_tb);
for (i = 0; i < 32; i = i + 1) begin
\t\t $dumpvars(0,system_tb.uut.picorv32_core.cpuregs[i]);
\t\t\tend \t\t
\t\tend
\t\trepeat (100) @(posedge clk);
\t\tresetn <= 1;
\tend
\twire trap;
\twire [7:0] out_byte;
\twire out_byte_en;
\tsystem uut (
\t\t.clk (clk ),
\t\t.resetn (resetn ),
\t\t.trap (trap ),
.out_byte (out_byte ),
\t\t.out_byte_en(out_byte_en)
\t);
\talways @(posedge clk) begin
if (resetn && out_byte_en) begin
\t\t\t$write("%c", out_byte);
\t\t\t$fflush;
\t\tend
\t\tif (resetn && trap) begin
\t\t\t$finish;
\t\tend
\tend
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_clock_module.v
//
// *Module Description:
// Basic clock module implementation.
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module omsp_clock_module (
// OUTPUTs
aclk, // ACLK
aclk_en, // ACLK enable
cpu_en_s, // Enable CPU code execution (synchronous)
cpu_mclk, // Main system CPU only clock
dma_mclk, // Main system DMA and/or CPU clock
dbg_clk, // Debug unit clock
dbg_en_s, // Debug interface enable (synchronous)
dbg_rst, // Debug unit reset
dco_enable, // Fast oscillator enable
dco_wkup, // Fast oscillator wake-up (asynchronous)
lfxt_enable, // Low frequency oscillator enable
lfxt_wkup, // Low frequency oscillator wake-up (asynchronous)
per_dout, // Peripheral data output
por, // Power-on reset
puc_pnd_set, // PUC pending set for the serial debug interface
puc_rst, // Main system reset
smclk, // SMCLK
smclk_en, // SMCLK enable
// INPUTs
cpu_en, // Enable CPU code execution (asynchronous)
cpuoff, // Turns off the CPU
dbg_cpu_reset, // Reset CPU from debug interface
dbg_en, // Debug interface enable (asynchronous)
dco_clk, // Fast oscillator (fast clock)
lfxt_clk, // Low frequency oscillator (typ 32kHz)
mclk_dma_enable, // DMA Sub-System Clock enable
mclk_dma_wkup, // DMA Sub-System Clock wake-up (asynchronous)
mclk_enable, // Main System Clock enable
mclk_wkup, // Main System Clock wake-up (asynchronous)
oscoff, // Turns off LFXT1 clock input
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_we, // Peripheral write enable (high active)
reset_n, // Reset Pin (low active, asynchronous)
scan_enable, // Scan enable (active during scan shifting)
scan_mode, // Scan mode
scg0, // System clock generator 1. Turns off the DCO
scg1, // System clock generator 1. Turns off the SMCLK
wdt_reset // Watchdog-timer reset
);
// OUTPUTs
//=========
output aclk; // ACLK
output aclk_en; // ACLK enable
output cpu_en_s; // Enable CPU code execution (synchronous)
output cpu_mclk; // Main system CPU only clock
output dma_mclk; // Main system DMA and/or CPU clock
output dbg_clk; // Debug unit clock
output dbg_en_s; // Debug unit enable (synchronous)
output dbg_rst; // Debug unit reset
output dco_enable; // Fast oscillator enable
output dco_wkup; // Fast oscillator wake-up (asynchronous)
output lfxt_enable; // Low frequency oscillator enable
output lfxt_wkup; // Low frequency oscillator wake-up (asynchronous)
output [15:0] per_dout; // Peripheral data output
output por; // Power-on reset
output puc_pnd_set; // PUC pending set for the serial debug interface
output puc_rst; // Main system reset
output smclk; // SMCLK
output smclk_en; // SMCLK enable
// INPUTs
//=========
input cpu_en; // Enable CPU code execution (asynchronous)
input cpuoff; // Turns off the CPU
input dbg_cpu_reset; // Reset CPU from debug interface
input dbg_en; // Debug interface enable (asynchronous)
input dco_clk; // Fast oscillator (fast clock)
input lfxt_clk; // Low frequency oscillator (typ 32kHz)
input mclk_dma_enable; // DMA Sub-System Clock enable
input mclk_dma_wkup; // DMA Sub-System Clock wake-up (asynchronous)
input mclk_enable; // Main System Clock enable
input mclk_wkup; // Main System Clock wake-up (asynchronous)
input oscoff; // Turns off LFXT1 clock input
input [13:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input reset_n; // Reset Pin (low active, asynchronous)
input scan_enable; // Scan enable (active during scan shifting)
input scan_mode; // Scan mode
input scg0; // System clock generator 1. Turns off the DCO
input scg1; // System clock generator 1. Turns off the SMCLK
input wdt_reset; // Watchdog-timer reset
//=============================================================================
// 1) WIRES & PARAMETER DECLARATION
//=============================================================================
// Register base address (must be aligned to decoder bit width)
parameter [14:0] BASE_ADDR = 15\'h0050;
// Decoder bit width (defines how many bits are considered for address decoding)
parameter DEC_WD = 4;
// Register addresses offset
parameter [DEC_WD-1:0] BCSCTL1 = \'h7,
BCSCTL2 = \'h8;
// Register one-hot decoder utilities
parameter DEC_SZ = (1 << DEC_WD);
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1\'b0}}, 1\'b1};
// Register one-hot decoder
parameter [DEC_SZ-1:0] BCSCTL1_D = (BASE_REG << BCSCTL1),
BCSCTL2_D = (BASE_REG << BCSCTL2);
// Local wire declarations
wire nodiv_mclk;
wire nodiv_smclk;
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Local register selection
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
// Register local address
wire [DEC_WD-1:0] reg_addr = {1\'b0, per_addr[DEC_WD-2:0]};
// Register address decode
wire [DEC_SZ-1:0] reg_dec = (BCSCTL1_D & {DEC_SZ{(reg_addr==(BCSCTL1 >>1))}}) |
(BCSCTL2_D & {DEC_SZ{(reg_addr==(BCSCTL2 >>1))}});
// Read/Write probes
wire reg_lo_write = per_we[0] & reg_sel;
wire reg_hi_write = per_we[1] & reg_sel;
wire reg_read = ~|per_we & reg_sel;
// Read/Write vectors
wire [DEC_SZ-1:0] reg_hi_wr = reg_dec & {DEC_SZ{reg_hi_write}};
wire [DEC_SZ-1:0] reg_lo_wr = reg_dec & {DEC_SZ{reg_lo_write}};
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
//============================================================================
// 3) REGISTERS
//============================================================================
// BCSCTL1 Register
//--------------
reg [7:0] bcsctl1;
wire bcsctl1_wr = BCSCTL1[0] ? reg_hi_wr[BCSCTL1] : reg_lo_wr[BCSCTL1];
wire [7:0] bcsctl1_nxt = BCSCTL1[0] ? per_din[15:8] : per_din[7:0];
`ifdef ASIC_CLOCKING
`ifdef ACLK_DIVIDER
wire [7:0] divax_mask = 8\'h30;
`else
wire [7:0] divax_mask = 8\'h00;
`endif
`ifdef DMA_IF_EN
`ifdef CPUOFF_EN
wire [7:0] dma_cpuoff_mask = 8\'h01;
`else
wire [7:0] dma_cpuoff_mask = 8\'h00;
`endif
`ifdef OSCOFF_EN
wire [7:0] dma_oscoff_mask = 8\'h02;
`else
wire [7:0] dma_oscoff_mask = 8\'h00;
`endif
`ifdef SCG0_EN
wire [7:0] dma_scg0_mask = 8\'h04;
`else
wire [7:0] dma_scg0_mask = 8\'h00;
`endif
`ifdef SCG1_EN
wire [7:0] dma_scg1_mask = 8\'h08;
`else
wire [7:0] dma_scg1_mask = 8\'h00;
`endif
`else
wire [7:0] dma_cpuoff_mask = 8\'h00;
wire [7:0] dma_scg0_mask = 8\'h00;
wire [7:0] dma_scg1_mask = 8\'h00;
wire [7:0] dma_oscoff_mask = 8\'h00;
`endif
`else
wire [7:0] divax_mask = 8\'h30;
wire [7:0] dma_cpuoff_mask = 8\'h00;
wire [7:0] dma_scg0_mask = 8\'h00;
`ifdef DMA_IF_EN
wire [7:0] dma_oscoff_mask = 8\'h02;
wire [7:0] dma_scg1_mask = 8\'h08;
`else
wire [7:0] dma_oscoff_mask = 8\'h00;
wire [7:0] dma_scg1_mask = 8\'h00;
`endif
`endif
always @ (posedge dma_mclk or posedge puc_rst)
if (puc_rst) bcsctl1 <= 8\'h00;
else if (bcsctl1_wr) bcsctl1 <= bcsctl1_nxt & (divax_mask |
dma_cpuoff_mask | dma_oscoff_mask |
dma_scg0_mask | dma_scg1_mask ); // Mask unused bits
// BCSCTL2 Register
//--------------
reg [7:0] bcsctl2;
wire bcsctl2_wr = BCSCTL2[0] ? reg_hi_wr[BCSCTL2] : reg_lo_wr[BCSCTL2];
wire [7:0] bcsctl2_nxt = BCSCTL2[0] ? per_din[15:8] : per_din[7:0];
`ifdef MCLK_MUX
wire [7:0] selmx_mask = 8\'h80;
`else
wire [7:0] selmx_mask = 8\'h00;
`endif
`ifdef MCLK_DIVIDER
wire [7:0] divmx_mask = 8\'h30;
`else
wire [7:0] divmx_mask = 8\'h00;
`endif
`ifdef ASIC_CLOCKING
`ifdef SMCLK_MUX
wire [7:0] sels_mask = 8\'h08;
`else
wire [7:0] sels_mask = 8\'h00;
`endif
`ifdef SMCLK_DIVIDER
wire [7:0] divsx_mask = 8\'h06;
`else
wire [7:0] divsx_mask = 8\'h00;
`endif
`else
wire [7:0] sels_mask = 8\'h08;
wire [7:0] divsx_mask = 8\'h06;
`endif
always @ (posedge dma_mclk or posedge puc_rst)
if (puc_rst) bcsctl2 <= 8\'h00;
else if (bcsctl2_wr) bcsctl2 <= bcsctl2_nxt & ( sels_mask | divsx_mask |
selmx_mask | divmx_mask); // Mask unused bits
//============================================================================
// 4) DATA OUTPUT GENERATION
//============================================================================
// Data output mux
wire [15:0] bcsctl1_rd = {8\'h00, (bcsctl1 & {8{reg_rd[BCSCTL1]}})} << (8 & {4{BCSCTL1[0]}});
wire [15:0] bcsctl2_rd = {8\'h00, (bcsctl2 & {8{reg_rd[BCSCTL2]}})} << (8 & {4{BCSCTL2[0]}});
wire [15:0] per_dout = bcsctl1_rd |
bcsctl2_rd;
//=============================================================================
// 5) DCO_CLK / LFXT_CLK INTERFACES (WAKEUP, ENABLE, ...)
//=============================================================================
`ifdef ASIC_CLOCKING
wire cpuoff_and_mclk_enable;
wire cpuoff_and_mclk_dma_enable;
wire cpuoff_and_mclk_dma_wkup;
`ifdef CPUOFF_EN
omsp_and_gate and_cpuoff_mclk_en (.y(cpuoff_and_mclk_enable), .a(cpuoff), .b(mclk_enable));
`ifdef DMA_IF_EN
omsp_and_gate and_cpuoff_mclk_dma_en (.y(cpuoff_and_mclk_dma_enable), .a(bcsctl1[`DMA_CPUOFF]), .b(mclk_dma_enable));
omsp_and_gate and_cpuoff_mclk_dma_wkup (.y(cpuoff_and_mclk_dma_wkup), .a(bcsctl1[`DMA_CPUOFF]), .b(mclk_dma_wkup));
`else
assign cpuoff_and_mclk_dma_enable = 1\'b0;
assign cpuoff_and_mclk_dma_wkup = 1\'b0;
`endif
`else
assign cpuoff_and_mclk_enable = 1\'b0;
assign cpuoff_and_mclk_dma_enable = 1\'b0;
assign cpuoff_and_mclk_dma_wkup = 1\'b0;
wire UNUSED_cpuoff = cpuoff;
`endif
wire scg0_and_mclk_dma_enable;
wire scg0_and_mclk_dma_wkup;
`ifdef DMA_IF_EN
`ifdef SCG0_EN
omsp_and_gate and_scg0_mclk_dma_en (.y(scg0_and_mclk_dma_enable), .a(bcsctl1[`DMA_SCG0]), .b(mclk_dma_enable));
omsp_and_gate and_scg0_mclk_dma_wkup (.y(scg0_and_mclk_dma_wkup), .a(bcsctl1[`DMA_SCG0]), .b(mclk_dma_wkup));
`else
assign scg0_and_mclk_dma_enable = 1\'b0;
assign scg0_and_mclk_dma_wkup = 1\'b0;
wire UNUSED_scg0_mclk_dma_wkup = mclk_dma_wkup;
`endif
`else
assign scg0_and_mclk_dma_enable = 1\'b0;
assign scg0_and_mclk_dma_wkup = 1\'b0;
`endif
wire scg1_and_mclk_dma_enable;
wire scg1_and_mclk_dma_wkup;
`ifdef DMA_IF_EN
`ifdef SCG1_EN
omsp_and_gate and_scg1_mclk_dma_en (.y(scg1_and_mclk_dma_enable), .a(bcsctl1[`DMA_SCG1]), .b(mclk_dma_enable));
omsp_and_gate and_scg1_mclk_dma_wkup (.y(scg1_and_mclk_dma_wkup), .a(bcsctl1[`DMA_SCG1]), .b(mclk_dma_wkup));
`else
assign scg1_and_mclk_dma_enable = 1\'b0;
assign scg1_and_mclk_dma_wkup = 1\'b0;
wire UNUSED_scg1_mclk_dma_wkup = mclk_dma_wkup;
`endif
`else
assign scg1_and_mclk_dma_enable = 1\'b0;
assign scg1_and_mclk_dma_wkup = 1\'b0;
`endif
wire oscoff_and_mclk_dma_enable;
wire oscoff_and_mclk_dma_wkup;
`ifdef DMA_IF_EN
`ifdef OSCOFF_EN
omsp_and_gate and_oscoff_mclk_dma_en (.y(oscoff_and_mclk_dma_enable), .a(bcsctl1[`DMA_OSCOFF]), .b(mclk_dma_enable));
omsp_and_gate and_oscoff_mclk_dma_wkup (.y(oscoff_and_mclk_dma_wkup), .a(bcsctl1[`DMA_OSCOFF]), .b(mclk_dma_wkup));
`else
assign oscoff_and_mclk_dma_enable = 1\'b0;
assign oscoff_and_mclk_dma_wkup = 1\'b0;
wire UNUSED_oscoff_mclk_dma_wkup = mclk_dma_wkup;
`endif
`else
assign oscoff_and_mclk_dma_enable = 1\'b0;
assign oscoff_and_mclk_dma_wkup = 1\'b0;
wire UNUSED_mclk_dma_wkup = mclk_dma_wkup;
`endif
`else
wire UNUSED_cpuoff = cpuoff;
wire UNUSED_mclk_enable = mclk_enable;
wire UNUSED_mclk_dma_wkup = mclk_dma_wkup;
`endif
//-----------------------------------------------------------
// 5.1) HIGH SPEED SYSTEM CLOCK GENERATOR (DCO_CLK)
//-----------------------------------------------------------
// Note1: switching off the DCO osillator is only
// supported in ASIC mode with SCG0 low power mode
//
// Note2: unlike the original MSP430 specification,
// we allow to switch off the DCO even
// if it is selected by MCLK or SMCLK.
wire por_a;
wire dco_wkup;
wire cpu_en_wkup;
`ifdef SCG0_EN
// The DCO oscillator is synchronously disabled if:
// - the cpu pin is disabled (in that case, wait for mclk_enable==0)
// - the debug interface is disabled
// - SCG0 is set (in that case, wait for the mclk_enable==0 if selected by SELMx)
//
// Note that we make extensive use of the AND gate module in order
// to prevent glitch propagation on the wakeup logic cone.
wire cpu_enabled_with_dco;
wire dco_not_enabled_by_dbg;
wire dco_disable_by_scg0;
wire dco_disable_by_cpu_en;
wire dco_enable_nxt;
omsp_and_gate and_dco_dis1 (.y(cpu_enabled_with_dco), .a(~bcsctl2[`SELMx]), .b(cpuoff_and_mclk_enable));
omsp_and_gate and_dco_dis2 (.y(dco_not_enabled_by_dbg), .a(~dbg_en_s), .b(~(cpu_enabled_with_dco | scg0_and_mclk_dma_enable)));
omsp_and_gate and_dco_dis3 (.y(dco_disable_by_scg0), .a(scg0), .b(dco_not_enabled_by_dbg));
omsp_and_gate and_dco_dis4 (.y(dco_disable_by_cpu_en), .a(~cpu_en_s), .b(~mclk_enable));
omsp_and_gate and_dco_dis5 (.y(dco_enable_nxt), .a(~dco_disable_by_scg0), .b(~dco_disable_by_cpu_en));
// Register to prevent glitch propagation
reg dco_disable;
wire dco_wkup_set_scan_observe;
always @(posedge nodiv_mclk or posedge por)
if (por) dco_disable <= 1\'b1;
else dco_disable <= ~dco_enable_nxt | dco_wkup_set_scan_observe;
// Optional scan repair
wire dco_clk_n;
`ifdef SCAN_REPAIR_INV_CLOCKS
omsp_scan_mux scan_mux_repair_dco_clk_n (
.scan_mode (scan_mode),
.data_in_scan ( dco_clk),
.data_in_func (~dco_clk),
.data_out ( dco_clk_n)
);
`else
assign dco_clk_n = ~dco_clk;
`endif
// Note that a synchronizer is required if the MCLK mux is included
`ifdef MCLK_MUX
omsp_sync_cell sync_cell_dco_disable (
.data_out (dco_enable),
.data_in (~dco_disable),
.clk (dco_clk_n),
.rst (por)
);
`else
// Optional scan repair
wire nodiv_mclk_n;
`ifdef SCAN_REPAIR_INV_CLOCKS
omsp_scan_mux scan_mux_repair_nodiv_mclk_n (
.scan_mode (scan_mode),
.data_in_scan ( nodiv_mclk),
.data_in_func (~nodiv_mclk),
.data_out ( nodiv_mclk_n)
);
`else
assign nodiv_mclk_n = ~nodiv_mclk;
`endif
// Re-time DCO enable with MCLK falling edge
reg dco_enable;
always @(posedge nodiv_mclk_n or posedge por)
if (por) dco_enable <= 1\'b0;
else dco_enable <= ~dco_disable;
`endif
// The DCO oscillator will get an asynchronous wakeup if:
// - the MCLK generates a wakeup (only if the MCLK mux selects dco_clk)
// - if the DCO wants to be synchronously enabled (i.e dco_enable_nxt=1)
wire dco_mclk_wkup;
wire dco_en_wkup;
omsp_and_gate and_dco_mclk_wkup (.y(dco_mclk_wkup), .a(mclk_wkup), .b(~bcsctl2[`SELMx]));
omsp_and_gate and_dco_en_wkup (.y(dco_en_wkup), .a(~dco_enable), .b(dco_enable_nxt));
wire dco_wkup_set = dco_mclk_wkup | scg0_and_mclk_dma_wkup | dco_en_wkup | cpu_en_wkup;
// Scan MUX for the asynchronous SET
wire dco_wkup_set_scan;
omsp_scan_mux scan_mux_dco_wkup (
.scan_mode (scan_mode),
.data_in_scan (por_a),
.data_in_func (dco_wkup_set | por),
.data_out (dco_wkup_set_scan)
);
// Scan MUX to increase coverage
omsp_scan_mux scan_mux_dco_wkup_observe (
.scan_mode (scan_mode),
.data_in_scan (dco_wkup_set),
.data_in_func (1\'b0),
.data_out (dco_wkup_set_scan_observe)
);
// The wakeup is asynchronously set, synchronously released
wire dco_wkup_n;
omsp_sync_cell sync_cell_dco_wkup (
.data_out (dco_wkup_n),
.data_in (1\'b1),
.clk (dco_clk_n),
.rst (dco_wkup_set_scan)
);
omsp_and_gate and_dco_wkup (.y(dco_wkup), .a(~dco_wkup_n), .b(cpu_en));
`else
assign dco_enable = 1\'b1;
assign dco_wkup = 1\'b1;
wire UNUSED_scg0 = scg0;
wire UNUSED_cpu_en_wkup1 = cpu_en_wkup;
`endif
//-----------------------------------------------------------
// 5.2) LOW FREQUENCY CRYSTAL CLOCK GENERATOR (LFXT_CLK)
//-----------------------------------------------------------
// ASIC MODE
//------------------------------------------------
// Note: unlike the original MSP430 specification,
// we allow to switch off the LFXT even
// if it is selected by MCLK or SMCLK.
`ifdef ASIC_CLOCKING
`ifdef OSCOFF_EN
// The LFXT is synchronously disabled if:
// - the cpu pin is disabled (in that case, wait for mclk_enable==0)
// - the debug interface is disabled
// - OSCOFF is set (in that case, wait for the mclk_enable==0 if selected by SELMx)
wire cpu_enabled_with_lfxt;
wire lfxt_not_enabled_by_dbg;
wire lfxt_disable_by_oscoff;
wire lfxt_disable_by_cpu_en;
wire lfxt_enable_nxt;
omsp_and_gate and_lfxt_dis1 (.y(cpu_enabled_with_lfxt), .a(bcsctl2[`SELMx]), .b(cpuoff_and_mclk_enable));
omsp_and_gate and_lfxt_dis2 (.y(lfxt_not_enabled_by_dbg), .a(~dbg_en_s), .b(~(cpu_enabled_with_lfxt | oscoff_and_mclk_dma_enable)));
omsp_and_gate and_lfxt_dis3 (.y(lfxt_disable_by_oscoff), .a(oscoff), .b(lfxt_not_enabled_by_dbg));
omsp_and_gate and_lfxt_dis4 (.y(lfxt_disable_by_cpu_en), .a(~cpu_en_s), .b(~mclk_enable));
omsp_and_gate and_lfxt_dis5 (.y(lfxt_enable_nxt), .a(~lfxt_disable_by_oscoff), .b(~lfxt_disable_by_cpu_en));
// Register to prevent glitch propagation
reg lfxt_disable;
wire lfxt_wkup_set_scan_observe;
always @(posedge nodiv_mclk or posedge por)
if (por) lfxt_disable <= 1\'b1;
else lfxt_disable <= ~lfxt_enable_nxt | lfxt_wkup_set_scan_observe;
// Optional scan repair
wire lfxt_clk_n;
`ifdef SCAN_REPAIR_INV_CLOCKS
omsp_scan_mux scan_mux_repair_lfxt_clk_n (
.scan_mode (scan_mode),
.data_in_scan ( lfxt_clk),
.data_in_func (~lfxt_clk),
.data_out ( lfxt_clk_n)
);
`else
assign lfxt_clk_n = ~lfxt_clk;
`endif
// Synchronize the OSCOFF control signal to the LFXT clock domain
omsp_sync_cell sync_cell_lfxt_disable (
.data_out (lfxt_enable),
.data_in (~lfxt_disable),
.clk (lfxt_clk_n),
.rst (por)
);
// The LFXT will get an asynchronous wakeup if:
// - the MCLK generates a wakeup (only if the MCLK mux selects lfxt_clk)
// - if the LFXT wants to be synchronously enabled (i.e lfxt_enable_nxt=1)
wire lfxt_mclk_wkup;
wire lfxt_en_wkup;
omsp_and_gate and_lfxt_mclk_wkup (.y(lfxt_mclk_wkup), .a(mclk_wkup), .b(bcsctl2[`SELMx]));
omsp_and_gate and_lfxt_en_wkup (.y(lfxt_en_wkup), .a(~lfxt_enable), .b(lfxt_enable_nxt));
wire lfxt_wkup_set = lfxt_mclk_wkup | oscoff_and_mclk_dma_wkup | lfxt_en_wkup | cpu_en_wkup;
// Scan MUX for the asynchronous SET
wire lfxt_wkup_set_scan;
omsp_scan_mux scan_mux_lfxt_wkup (
.scan_mode (scan_mode),
.data_in_scan (por_a),
.data_in_func (lfxt_wkup_set | por),
.data_out (lfxt_wkup_set_scan)
);
// Scan MUX to increase coverage
omsp_scan_mux scan_mux_lfxt_wkup_observe (
.scan_mode (scan_mode),
.data_in_scan (lfxt_wkup_set),
.data_in_func (1\'b0),
.data_out (lfxt_wkup_set_scan_observe)
);
// The wakeup is asynchronously set, synchronously released
wire lfxt_wkup_n;
omsp_sync_cell sync_cell_lfxt_wkup (
.data_out (lfxt_wkup_n),
.data_in (1\'b1),
.clk (lfxt_clk_n),
.rst (lfxt_wkup_set_scan)
);
omsp_and_gate and_lfxt_wkup (.y(lfxt_wkup), .a(~lfxt_wkup_n), .b(cpu_en));
`else
assign lfxt_enable = 1\'b1;
assign lfxt_wkup = 1\'b0;
wire UNUSED_oscoff = oscoff;
wire UNUSED_cpuoff_and_mclk_enable = cpuoff_and_mclk_enable;
wire UNUSED_cpu_en_wkup2 = cpu_en_wkup;
`endif
// FPGA MODE
//---------------------------------------
// Synchronize LFXT_CLK & edge detection
`else
wire lfxt_clk_s;
omsp_sync_cell sync_cell_lfxt_clk (
.data_out (lfxt_clk_s),
.data_in (lfxt_clk),
.clk (nodiv_mclk),
.rst (por)
);
reg lfxt_clk_dly;
always @ (posedge nodiv_mclk or posedge por)
if (por) lfxt_clk_dly <= 1\'b0;
else lfxt_clk_dly <= lfxt_clk_s;
wire lfxt_clk_en = (lfxt_clk_s & ~lfxt_clk_dly) & (~oscoff | (mclk_dma_enable & bcsctl1[`DMA_OSCOFF]));
assign lfxt_enable = 1\'b1;
assign lfxt_wkup = 1\'b0;
`endif
//=============================================================================
// 6) CLOCK GENERATION
//=============================================================================
//-----------------------------------------------------------
// 6.1) GLOBAL CPU ENABLE
//----------------------------------------------------------
// ACLK and SMCLK are directly switched-off
// with the cpu_en pin (after synchronization).
// MCLK will be switched off once the CPU reaches
// its IDLE state (through the mclk_enable signal)
// Synchronize CPU_EN signal to the MCLK domain
//----------------------------------------------
`ifdef SYNC_CPU_EN
omsp_sync_cell sync_cell_cpu_en (
.data_out (cpu_en_s),
.data_in (cpu_en),
.clk (nodiv_mclk),
.rst (por)
);
omsp_and_gate and_cpu_en_wkup (.y(cpu_en_wkup), .a(cpu_en), .b(~cpu_en_s));
`else
assign cpu_en_s = cpu_en;
assign cpu_en_wkup = 1\'b0;
`endif
// Synchronize CPU_EN signal to the ACLK domain
//----------------------------------------------
`ifdef LFXT_DOMAIN
wire cpu_en_aux_s;
omsp_sync_cell sync_cell_cpu_aux_en (
.data_out (cpu_en_aux_s),
.data_in (cpu_en),
.clk (lfxt_clk),
.rst (por)
);
`else
wire cpu_en_aux_s = cpu_en_s;
`endif
// Synchronize CPU_EN signal to the SMCLK domain
//----------------------------------------------
// Note: the synchronizer is only required if there is a SMCLK_MUX
`ifdef ASIC_CLOCKING
`ifdef SMCLK_MUX
wire cpu_en_sm_s;
omsp_sync_cell sync_cell_cpu_sm_en (
.data_out (cpu_en_sm_s),
.data_in (cpu_en),
.clk (nodiv_smclk),
.rst (por)
);
`else
wire cpu_en_sm_s = cpu_en_s;
`endif
`endif
//-----------------------------------------------------------
// 6.2) MCLK GENERATION
//-----------------------------------------------------------
// Clock MUX
//----------------------------
`ifdef MCLK_MUX
omsp_clock_mux clock_mux_mclk (
.clk_out (nodiv_mclk),
.clk_in0 (dco_clk),
.clk_in1 (lfxt_clk),
.reset (por),
.scan_mode (scan_mode),
.select_in (bcsctl2[`SELMx])
);
`else
assign nodiv_mclk = dco_clk;
`endif
// Wakeup synchronizer
//----------------------------
wire cpuoff_and_mclk_dma_wkup_s;
wire mclk_wkup_s;
`ifdef CPUOFF_EN
`ifdef DMA_IF_EN
omsp_sync_cell sync_cell_mclk_dma_wkup (
.data_out (cpuoff_and_mclk_dma_wkup_s),
.data_in (cpuoff_and_mclk_dma_wkup),
.clk (nodiv_mclk),
.rst (puc_rst)
);
`else
assign cpuoff_and_mclk_dma_wkup_s = 1\'b0;
`endif
omsp_sync_cell sync_cell_mclk_wkup (
.data_out (mclk_wkup_s),
.data_in (mclk_wkup),
.clk (nodiv_mclk),
.rst (puc_rst)
);
`else
assign cpuoff_and_mclk_dma_wkup_s = 1\'b0;
assign mclk_wkup_s = 1\'b0;
wire UNUSED_mclk_wkup = mclk_wkup;
`endif
// Clock Divider
//----------------------------
// No need for extra synchronizer as bcsctl2
// comes from the same clock domain.
`ifdef CPUOFF_EN
wire mclk_active = mclk_enable | mclk_wkup_s | (dbg_en_s & cpu_en_s);
wire mclk_dma_active = cpuoff_and_mclk_dma_enable | cpuoff_and_mclk_dma_wkup_s | mclk_active;
`else
wire mclk_active = 1\'b1;
wire mclk_dma_active = 1\'b1;
`endif
`ifdef MCLK_DIVIDER
reg [2:0] mclk_div;
always @ (posedge nodiv_mclk or posedge puc_rst)
if (puc_rst) mclk_div <= 3\'h0;
else if ((bcsctl2[`DIVMx]!=2\'b00)) mclk_div <= mclk_div+3\'h1;
wire mclk_div_sel = (bcsctl2[`DIVMx]==2\'b00) ? 1\'b1 :
(bcsctl2[`DIVMx]==2\'b01) ? mclk_div[0] :
(bcsctl2[`DIVMx]==2\'b10) ? &mclk_div[1:0] :
&mclk_div[2:0] ;
wire mclk_div_en = mclk_active & mclk_div_sel;
wire mclk_dma_div_en = mclk_dma_active & mclk_div_sel;
`else
wire mclk_div_en = mclk_active;
wire mclk_dma_div_en = mclk_dma_active;
`endif
// Generate main system clock
//----------------------------
`ifdef MCLK_CGATE
omsp_clock_gate clock_gate_mclk (
.gclk (cpu_mclk),
.clk (nodiv_mclk),
.enable (mclk_div_en),
.scan_enable (scan_enable)
);
`ifdef DMA_IF_EN
omsp_clock_gate clock_gate_dma_mclk (
.gclk (dma_mclk),
.clk (nodiv_mclk),
.enable (mclk_dma_div_en),
.scan_enable (scan_enable)
);
`else
assign dma_mclk = cpu_mclk;
`endif
`else
assign cpu_mclk = nodiv_mclk;
assign dma_mclk = nodiv_mclk;
`endif
//-----------------------------------------------------------
// 6.3) ACLK GENERATION
//-----------------------------------------------------------
// ASIC MODE
//----------------------------
`ifdef ASIC_CLOCKING
`ifdef ACLK_DIVIDER
`ifdef LFXT_DOMAIN
wire nodiv_aclk = lfxt_clk;
// Synchronizers
//------------------------------------------------------
// Local Reset synchronizer
wire puc_lfxt_noscan_n;
wire puc_lfxt_rst;
omsp_sync_cell sync_cell_puc_lfxt (
.data_out (puc_lfxt_noscan_n),
.data_in (1\'b1),
.clk (nodiv_aclk),
.rst (puc_rst)
);
omsp_scan_mux scan_mux_puc_lfxt (
.scan_mode (scan_mode),
.data_in_scan (por_a),
.data_in_func (~puc_lfxt_noscan_n),
.data_out (puc_lfxt_rst)
);
// If the OSCOFF mode is enabled synchronize OSCOFF signal
wire oscoff_s;
`ifdef OSCOFF_EN
omsp_sync_cell sync_cell_oscoff (
.data_out (oscoff_s),
.data_in (oscoff),
.clk (nodiv_aclk),
.rst (puc_lfxt_rst)
);
`else
assign oscoff_s = 1\'b0;
`endif
// Local synchronizer for the bcsctl1.DIVAx configuration
// (note that we can live with a full bus synchronizer as
// it won\'t hurt if we get a wrong DIVAx value for a single clock cycle)
reg [1:0] divax_s;
reg [1:0] divax_ss;
always @ (posedge nodiv_aclk or posedge puc_lfxt_rst)
if (puc_lfxt_rst)
begin
divax_s <= 2\'h0;
divax_ss <= 2\'h0;
end
else
begin
divax_s <= bcsctl1[`DIVAx];
divax_ss <= divax_s;
end
`else
wire puc_lfxt_rst = puc_rst;
wire nodiv_aclk = dco_clk;
wire [1:0] divax_ss = bcsctl1[`DIVAx];
wire oscoff_s = oscoff;
`endif
// Wakeup synchronizer
//----------------------------
wire oscoff_and_mclk_dma_enable_s;
`ifdef OSCOFF_EN
`ifdef DMA_IF_EN
omsp_sync_cell sync_cell_aclk_dma_wkup (
.data_out (oscoff_and_mclk_dma_enable_s),
.data_in (oscoff_and_mclk_dma_wkup | oscoff_and_mclk_dma_enable),
.clk (nodiv_aclk),
.rst (puc_lfxt_rst)
);
`else
assign oscoff_and_mclk_dma_enable_s = 1\'b0;
`endif
`else
assign oscoff_and_mclk_dma_enable_s = 1\'b0;
`endif
// Clock Divider
//----------------------------
wire aclk_active = cpu_en_aux_s & (~oscoff_s | oscoff_and_mclk_dma_enable_s);
reg [2:0] aclk_div;
always @ (posedge nodiv_aclk or posedge puc_lfxt_rst)
if (puc_lfxt_rst) aclk_div <= 3\'h0;
else if ((divax_ss!=2\'b00)) aclk_div <= aclk_div+3\'h1;
wire aclk_div_sel = ((divax_ss==2\'b00) ? 1\'b1 :
(divax_ss==2\'b01) ? aclk_div[0] :
(divax_ss==2\'b10) ? &aclk_div[1:0] :
&aclk_div[2:0]);
wire aclk_div_en = aclk_active & aclk_div_sel;
// Clock gate
omsp_clock_gate clock_gate_aclk (
.gclk (aclk),
.clk (nodiv_aclk),
.enable (aclk_div_en),
.scan_enable (scan_enable)
);
`else
`ifdef LFXT_DOMAIN
assign aclk = lfxt_clk;
`else
assign aclk = dco_clk;
`endif
wire UNUSED_cpu_en_aux_s = cpu_en_aux_s;
`endif
`ifdef LFXT_DOMAIN
`else
wire UNUSED_lfxt_clk = lfxt_clk;
`endif
assign aclk_en = 1\'b1;
// FPGA MODE
//----------------------------
`else
reg aclk_en;
reg [2:0] aclk_div;
wire aclk_en_nxt = lfxt_clk_en & ((bcsctl1[`DIVAx]==2\'b00) ? 1\'b1 :
(bcsctl1[`DIVAx]==2\'b01) ? aclk_div[0] :
(bcsctl1[`DIVAx]==2\'b10) ? &aclk_div[1:0] :
&aclk_div[2:0]);
always @ (posedge nodiv_mclk or posedge puc_rst)
if (puc_rst) aclk_div <= 3\'h0;
else if ((bcsctl1[`DIVAx]!=2\'b00) & lfxt_clk_en) aclk_div <= aclk_div+3\'h1;
always @ (posedge nodiv_mclk or posedge puc_rst)
if (puc_rst) aclk_en <= 1\'b0;
else aclk_en <= aclk_en_nxt & cpu_en_s;
assign aclk = nodiv_mclk;
wire UNUSED_scan_enable = scan_enable;
wire UNUSED_scan_mode = scan_mode;
`endif
//-----------------------------------------------------------
// 6.4) SMCLK GENERATION
//-----------------------------------------------------------
// Clock MUX
//----------------------------
`ifdef SMCLK_MUX
omsp_clock_mux clock_mux_smclk (
.clk_out (nodiv_smclk),
.clk_in0 (dco_clk),
.clk_in1 (lfxt_clk),
.reset (por),
.scan_mode (scan_mode),
.select_in (bcsctl2[`SELS])
);
`else
assign nodiv_smclk = dco_clk;
`endif
// ASIC MODE
//----------------------------
`ifdef ASIC_CLOCKING
`ifdef SMCLK_MUX
// SMCLK_MUX Synchronizers
//------------------------------------------------------
// When the SMCLK MUX is enabled, the reset and DIVSx
// and SCG1 signals must be synchronized, otherwise not.
// Local Reset synchronizer
wire puc_sm_noscan_n;
wire puc_sm_rst;
omsp_sync_cell sync_cell_puc_sm (
.data_out (puc_sm_noscan_n),
.data_in (1\'b1),
.clk (nodiv_smclk),
.rst (puc_rst)
);
omsp_scan_mux scan_mux_puc_sm (
.scan_mode (scan_mode),
.data_in_scan (por_a),
.data_in_func (~puc_sm_noscan_n),
.data_out (puc_sm_rst)
);
// SCG1 synchronizer
wire scg1_s;
`ifdef SCG1_EN
omsp_sync_cell sync_cell_scg1 (
.data_out (scg1_s),
.data_in (scg1),
.clk (nodiv_smclk),
.rst (puc_sm_rst)
);
`else
assign scg1_s = 1\'b0;
wire UNUSED_scg1 = scg1;
wire UNUSED_puc_sm_rst = puc_sm_rst;
`endif
`ifdef SMCLK_DIVIDER
// Local synchronizer for the bcsctl2.DIVSx configuration
// (note that we can live with a full bus synchronizer as
// it won\'t hurt if we get a wrong DIVSx value for a single clock cycle)
reg [1:0] divsx_s;
reg [1:0] divsx_ss;
always @ (posedge nodiv_smclk or posedge puc_sm_rst)
if (puc_sm_rst)
begin
divsx_s <= 2\'h0;
divsx_ss <= 2\'h0;
end
else
begin
divsx_s <= bcsctl2[`DIVSx];
divsx_ss <= divsx_s;
end
`endif
`else
wire puc_sm_rst = puc_rst;
wire [1:0] divsx_ss = bcsctl2[`DIVSx];
wire scg1_s = scg1;
`endif
// Wakeup synchronizer
//----------------------------
wire scg1_and_mclk_dma_enable_s;
`ifdef SCG1_EN
`ifdef DMA_IF_EN
`ifdef SMCLK_MUX
omsp_sync_cell sync_cell_smclk_dma_wkup (
.data_out (scg1_and_mclk_dma_enable_s),
.data_in (scg1_and_mclk_dma_wkup | scg1_and_mclk_dma_enable),
.clk (nodiv_smclk),
.rst (puc_sm_rst)
);
`else
wire scg1_and_mclk_dma_wkup_s;
omsp_sync_cell sync_cell_smclk_dma_wkup (
.data_out (scg1_and_mclk_dma_wkup_s),
.data_in (scg1_and_mclk_dma_wkup),
.clk (nodiv_smclk),
.rst (puc_sm_rst)
);
assign scg1_and_mclk_dma_enable_s = scg1_and_mclk_dma_wkup_s | scg1_and_mclk_dma_enable;
`endif
`else
assign scg1_and_mclk_dma_enable_s = 1\'b0;
`endif
`else
assign scg1_and_mclk_dma_enable_s = 1\'b0;
`endif
// Clock Divider
//----------------------------
`ifdef SCG1_EN
wire smclk_active = cpu_en_sm_s & (~scg1_s | scg1_and_mclk_dma_enable_s);
`else
wire smclk_active = cpu_en_sm_s;
`endif
`ifdef SMCLK_DIVIDER
reg [2:0] smclk_div;
always @ (posedge nodiv_smclk or posedge puc_sm_rst)
if (puc_sm_rst) smclk_div <= 3\'h0;
else if ((divsx_ss!=2\'b00)) smclk_div <= smclk_div+3\'h1;
wire smclk_div_sel = ((divsx_ss==2\'b00) ? 1\'b1 :
(divsx_ss==2\'b01) ? smclk_div[0] :
(divsx_ss==2\'b10) ? &smclk_div[1:0] :
&smclk_div[2:0]);
wire smclk_div_en = smclk_active & smclk_div_sel;
`else
wire smclk_div_en = smclk_active;
`endif
// Generate sub-system clock
//----------------------------
`ifdef SMCLK_CGATE
omsp_clock_gate clock_gate_smclk (
.gclk (smclk),
.clk (nodiv_smclk),
.enable (smclk_div_en),
.scan_enable (scan_enable)
);
`else
assign smclk = nodiv_smclk;
`endif
assign smclk_en = 1\'b1;
// FPGA MODE
//----------------------------
`else
reg smclk_en;
reg [2:0] smclk_div;
wire smclk_in = (scg1 & ~(mclk_dma_enable & bcsctl1[`DMA_SCG1])) ? 1\'b0 :
bcsctl2[`SELS] ? lfxt_clk_en : 1\'b1;
wire smclk_en_nxt = smclk_in & ((bcsctl2[`DIVSx]==2\'b00) ? 1\'b1 :
(bcsctl2[`DIVSx]==2\'b01) ? smclk_div[0] :
(bcsctl2[`DIVSx]==2\'b10) ? &smclk_div[1:0] :
&smclk_div[2:0]);
always @ (posedge nodiv_mclk or posedge puc_rst)
if (puc_rst) smclk_en <= 1\'b0;
else smclk_en <= smclk_en_nxt & cpu_en_s;
always @ (posedge nodiv_mclk or posedge puc_rst)
if (puc_rst) smclk_div <= 3\'h0;
else if ((bcsctl2[`DIVSx]!=2\'b00) & smclk_in) smclk_div <= smclk_div+3\'h1;
wire smclk = nodiv_mclk;
`endif
//-----------------------------------------------------------
// 6.5) DEBUG INTERFACE CLOCK GENERATION (DBG_CLK)
//-----------------------------------------------------------
// Synchronize DBG_EN signal to MCLK domain
//------------------------------------------
`ifdef DBG_EN
`ifdef SYNC_DBG_EN
wire dbg_en_n_s;
omsp_sync_cell sync_cell_dbg_en (
.data_out (dbg_en_n_s),
.data_in (~dbg_en),
.clk (cpu_mclk),
.rst (por)
);
assign dbg_en_s = ~dbg_en_n_s;
wire dbg_rst_nxt = dbg_en_n_s;
`else
assign dbg_en_s = dbg_en;
wire dbg_rst_nxt = ~dbg_en;
`endif
`else
assign dbg_en_s = 1\'b0;
wire dbg_rst_nxt = 1\'b0;
wire UNUSED_dbg_en = dbg_en;
`endif
// Serial Debug Interface Clock gate
//------------------------------------------------
`ifdef DBG_EN
`ifdef ASIC_CLOCKING
omsp_clock_gate clock_gate_dbg_clk (
.gclk (dbg_clk),
.clk (cpu_mclk),
.enable ('b'dbg_en_s),
.scan_enable (scan_enable)
);
`else
assign dbg_clk = dco_clk;
`endif
`else
assign dbg_clk = 1\'b0;
`endif
//=============================================================================
// 7) RESET GENERATION
//=============================================================================
//
// Whenever the reset pin (reset_n) is deasserted, the internal resets of the
// openMSP430 will be released in the following order:
// 1- POR
// 2- DBG_RST (if the sdi interface is enabled, i.e. dbg_en=1)
// 3- PUC
//
// Note: releasing the DBG_RST before PUC is particularly important in order
// to allow the sdi interface to halt the cpu immediately after a PUC.
//
// Generate synchronized POR to MCLK domain
//------------------------------------------
// Asynchronous reset source
assign por_a = !reset_n;
wire por_noscan;
// Reset Synchronizer
omsp_sync_reset sync_reset_por (
.rst_s (por_noscan),
.clk (nodiv_mclk),
.rst_a (por_a)
);
// Scan Reset Mux
`ifdef ASIC
omsp_scan_mux scan_mux_por (
.scan_mode (scan_mode),
.data_in_scan (por_a),
.data_in_func (por_noscan),
.data_out (por)
);
`else
assign por = por_noscan;
`endif
// Generate synchronized reset for the SDI
//------------------------------------------
`ifdef DBG_EN
// Reset Generation
reg dbg_rst_noscan;
always @ (posedge cpu_mclk or posedge por)
if (por) dbg_rst_noscan <= 1\'b1;
else dbg_rst_noscan <= dbg_rst_nxt;
// Scan Reset Mux
`ifdef ASIC
omsp_scan_mux scan_mux_dbg_rst (
.scan_mode (scan_mode),
.data_in_scan (por_a),
.data_in_func (dbg_rst_noscan),
.data_out (dbg_rst)
);
`else
assign dbg_rst = dbg_rst_noscan;
`endif
`else
wire dbg_rst_noscan = 1\'b1;
assign dbg_rst = 1\'b1;
`endif
// Generate main system reset (PUC_RST)
//--------------------------------------
wire puc_noscan_n;
wire puc_a_scan;
// Asynchronous PUC reset
wire puc_a = por | wdt_reset;
// Synchronous PUC reset
wire puc_s = dbg_cpu_reset | // With the debug interface command
(dbg_en_s & dbg_rst_noscan & ~puc_noscan_n); // Sequencing making sure PUC is released
// after DBG_RST if the debug interface is
// enabled at power-on-reset time
// Scan Reset Mux
`ifdef ASIC
omsp_scan_mux scan_mux_puc_rst_a (
.scan_mode (scan_mode),
.data_in_scan (por_a),
.data_in_func (puc_a),
.data_out (puc_a_scan)
);
`else
assign puc_a_scan = puc_a;
`endif
// Reset Synchronizer
// (required because of the asynchronous watchdog reset)
omsp_sync_cell sync_cell_puc (
.data_out (puc_noscan_n),
.data_in (~puc_s),
.clk (cpu_mclk),
.rst (puc_a_scan)
);
// Scan Reset Mux
`ifdef ASIC
omsp_scan_mux scan_mux_puc_rst (
.scan_mode (scan_mode),
.data_in_scan (por_a),
.data_in_func (~puc_noscan_n),
.data_out (puc_rst)
);
`else
assign puc_rst = ~puc_noscan_n;
`endif
// PUC pending set the serial debug interface
assign puc_pnd_set = ~puc_noscan_n;
endmodule // omsp_clock_module
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: openMSP430.v
//
// *Module Description:
// openMSP430 Top level file
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module openMSP430 (
// OUTPUTs
aclk, // ASIC ONLY: ACLK
aclk_en, // FPGA ONLY: ACLK enable
dbg_freeze, // Freeze peripherals
dbg_i2c_sda_out, // Debug interface: I2C SDA OUT
dbg_uart_txd, // Debug interface: UART TXD
dco_enable, // ASIC ONLY: Fast oscillator enable
dco_wkup, // ASIC ONLY: Fast oscillator wake-up (asynchronous)
dmem_addr, // Data Memory address
dmem_cen, // Data Memory chip enable (low active)
dmem_din, // Data Memory data input
dmem_wen, // Data Memory write byte enable (low active)
irq_acc, // Interrupt request accepted (one-hot signal)
lfxt_enable, // ASIC ONLY: Low frequency oscillator enable
lfxt_wkup, // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
mclk, // Main system clock
dma_dout, // Direct Memory Access data output
dma_ready, // Direct Memory Access is complete
dma_resp, // Direct Memory Access response (0:Okay / 1:Error)
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_we, // Peripheral write byte enable (high active)
pmem_addr, // Program Memory address
pmem_cen, // Program Memory chip enable (low active)
pmem_din, // Program Memory data input (optional)
pmem_wen, // Program Memory write byte enable (low active) (optional)
puc_rst, // Main system reset
smclk, // ASIC ONLY: SMCLK
smclk_en, // FPGA ONLY: SMCLK enable
// INPUTs
cpu_en, // Enable CPU code execution (asynchronous and non-glitchy)
dbg_en, // Debug interface enable (asynchronous and non-glitchy)
dbg_i2c_addr, // Debug interface: I2C Address
dbg_i2c_broadcast, // Debug interface: I2C Broadcast Address (for multicore systems)
dbg_i2c_scl, // Debug interface: I2C SCL
dbg_i2c_sda_in, // Debug interface: I2C SDA IN
dbg_uart_rxd, // Debug interface: UART RXD (asynchronous)
dco_clk, // Fast oscillator (fast clock)
dmem_dout, // Data Memory data output
irq, // Maskable interrupts
lfxt_clk, // Low frequency oscillator (typ 32kHz)
dma_addr, // Direct Memory Access address
dma_din, // Direct Memory Access data input
dma_en, // Direct Memory Access enable (high active)
dma_priority, // Direct Memory Access priority (0:low / 1:high)
dma_we, // Direct Memory Access write byte enable (high active)
dma_wkup, // ASIC ONLY: DMA Sub-System Wake-up (asynchronous and non-glitchy)
nmi, // Non-maskable interrupt (asynchronous)
per_dout, // Peripheral data output
pmem_dout, // Program Memory data output
reset_n, // Reset Pin (low active, asynchronous and non-glitchy)
scan_enable, // ASIC ONLY: Scan enable (active during scan shifting)
scan_mode, // ASIC ONLY: Scan mode
wkup // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
);
// PARAMETERs
//============
parameter INST_NR = 8\'h00; // Current oMSP instance number (for multicore systems)
parameter TOTAL_NR = 8\'h00; // Total number of oMSP instances-1 (for multicore systems)
// OUTPUTs
//============
output aclk; // ASIC ONLY: ACLK
output aclk_en; // FPGA ONLY: ACLK enable
output dbg_freeze; // Freeze peripherals
output dbg_i2c_sda_out; // Debug interface: I2C SDA OUT
output dbg_uart_txd; // Debug interface: UART TXD
output dco_enable; // ASIC ONLY: Fast oscillator enable
output dco_wkup; // ASIC ONLY: Fast oscillator wake-up (asynchronous)
output [`DMEM_MSB:0] dmem_addr; // Data Memory address
output dmem_cen; // Data Memory chip enable (low active)
output [15:0] dmem_din; // Data Memory data input
output [1:0] dmem_wen; // Data Memory write byte enable (low active)
output [`IRQ_NR-3:0] irq_acc; // Interrupt request accepted (one-hot signal)
output lfxt_enable; // ASIC ONLY: Low frequency oscillator enable
output lfxt_wkup; // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
output mclk; // Main system clock
output [15:0] dma_dout; // Direct Memory Access data output
output dma_ready; // Direct Memory Access is complete
output dma_resp; // Direct Memory Access response (0:Okay / 1:Error)
output [13:0] per_addr; // Peripheral address
output [15:0] per_din; // Peripheral data input
output per_en; // Peripheral enable (high active)
output [1:0] per_we; // Peripheral write byte enable (high active)
output [`PMEM_MSB:0] pmem_addr; // Program Memory address
output pmem_cen; // Program Memory chip enable (low active)
output [15:0] pmem_din; // Program Memory data input (optional)
output [1:0] pmem_wen; // Program Memory write enable (low active) (optional)
output puc_rst; // Main system reset
output smclk; // ASIC ONLY: SMCLK
output smclk_en; // FPGA ONLY: SMCLK enable
// INPUTs
//============
input cpu_en; // Enable CPU code execution (asynchronous and non-glitchy)
input dbg_en; // Debug interface enable (asynchronous and non-glitchy)
input [6:0] dbg_i2c_addr; // Debug interface: I2C Address
input [6:0] dbg_i2c_broadcast; // Debug interface: I2C Broadcast Address (for multicore systems)
input dbg_i2c_scl; // Debug interface: I2C SCL
input dbg_i2c_sda_in; // Debug interface: I2C SDA IN
input dbg_uart_rxd; // Debug interface: UART RXD (asynchronous)
input dco_clk; // Fast oscillator (fast clock)
input [15:0] dmem_dout; // Data Memory data output
input [`IRQ_NR-3:0] irq; // Maskable interrupts (14, 30 or 62)
input lfxt_clk; // Low frequency oscillator (typ 32kHz)
input [15:1] dma_addr; // Direct Memory Access address
input [15:0] dma_din; // Direct Memory Access data input
input dma_en; // Direct Memory Access enable (high active)
input dma_priority; // Direct Memory Access priority (0:low / 1:high)
input [1:0] dma_we; // Direct Memory Access write byte enable (high active)
input dma_wkup; // ASIC ONLY: DMA Wake-up (asynchronous and non-glitchy)
input nmi; // Non-maskable interrupt (asynchronous and non-glitchy)
input [15:0] per_dout; // Peripheral data output
input [15:0] pmem_dout; // Program Memory data output
input reset_n; // Reset Pin (active low, asynchronous and non-glitchy)
input scan_enable; // ASIC ONLY: Scan enable (active during scan shifting)
input scan_mode; // ASIC ONLY: Scan mode
input wkup; // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
//=============================================================================
// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
//=============================================================================
wire [7:0] inst_ad;
wire [7:0] inst_as;
wire [11:0] inst_alu;
wire inst_bw;
wire inst_irq_rst;
wire inst_mov;
wire [15:0] inst_dest;
wire [15:0] inst_dext;
wire [15:0] inst_sext;
wire [7:0] inst_so;
wire [15:0] inst_src;
wire [2:0] inst_type;
wire [7:0] inst_jmp;
wire [3:0] e_state;
wire exec_done;
wire decode_noirq;
wire cpu_en_s;
wire cpuoff;
wire oscoff;
wire scg0;
wire scg1;
wire por;
wire gie;
wire cpu_mclk;
wire dma_mclk;
wire mclk_dma_enable;
wire mclk_dma_wkup;
wire mclk_enable;
wire mclk_wkup;
wire [31:0] cpu_id;
wire [7:0] cpu_nr_inst = INST_NR;
wire [7:0] cpu_nr_total = TOTAL_NR;
wire [15:0] eu_mab;
wire [15:0] eu_mdb_in;
wire [15:0] eu_mdb_out;
wire [1:0] eu_mb_wr;
wire eu_mb_en;
wire [15:0] fe_mab;
wire [15:0] fe_mdb_in;
wire fe_mb_en;
wire fe_pmem_wait;
wire pc_sw_wr;
wire [15:0] pc_sw;
wire [15:0] pc;
wire [15:0] pc_nxt;
wire nmi_acc;
wire nmi_pnd;
wire nmi_wkup;
wire wdtie;
wire wdtnmies;
wire wdtifg;
wire wdt_irq;
wire wdt_wkup;
wire wdt_reset;
wire wdtifg_sw_clr;
wire wdtifg_sw_set;
wire dbg_clk;
wire dbg_rst;
wire dbg_en_s;
wire dbg_halt_cmd;
wire dbg_mem_en;
wire dbg_reg_wr;
wire dbg_cpu_reset;
wire [15:0] dbg_mem_addr;
wire [15:0] dbg_mem_dout;
wire [15:0] dbg_mem_din;
wire [15:0] dbg_reg_din;
wire [1:0] dbg_mem_wr;
wire cpu_halt_st;
wire cpu_halt_cmd;
wire puc_pnd_set;
wire [15:0] per_dout_or;
wire [15:0] per_dout_sfr;
wire [15:0] per_dout_wdog;
wire [15:0] per_dout_mpy;
wire [15:0] per_dout_clk;
//=============================================================================
// 2) GLOBAL CLOCK & RESET MANAGEMENT
//=============================================================================
omsp_clock_module clock_module_0 (
// OUTPUTs
.aclk (aclk), // ACLK
.aclk_en (aclk_en), // ACLK enablex
.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
.cpu_mclk (cpu_mclk), // Main system CPU only clock
.dma_mclk (dma_mclk), // Main system DMA and/or CPU clock
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_en_s (dbg_en_s), // Debug interface enable (synchronous)
.dbg_rst (dbg_rst), // Debug unit reset
.dco_enable (dco_enable), // Fast oscillator enable
.dco_wkup (dco_wkup), // Fast oscillator wake-up (asynchronous)
.lfxt_enable (lfxt_enable), // Low frequency oscillator enable
.lfxt_wkup (lfxt_wkup), // Low frequency oscillator wake-up (asynchronous)
.per_dout (per_dout_clk), // Peripheral data output
.por (por), // Power-on reset
.puc_pnd_set (puc_pnd_set), // PUC pending set for the serial debug interface
.puc_rst (puc_rst), // Main system reset
.smclk (smclk), // SMCLK
.smclk_en (smclk_en), // SMCLK enable
// INPUTs
.cpu_en (cpu_en), // Enable CPU code execution (asynchronous)
.cpuoff (cpuoff), // Turns off the CPU
.dbg_cpu_reset (dbg_cpu_reset), // Reset CPU from debug interface
.dbg_en (dbg_en), // Debug interface enable (asynchronous)
.dco_clk (dco_clk), // Fast oscillator (fast clock)
.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
.mclk_dma_enable (mclk_dma_enable), // DMA Sub-System Clock enable
.mclk_dma_wkup (mclk_dma_wkup), // DMA Sub-System Clock wake-up (asynchronous)
.mclk_enable (mclk_enable), // Main System Clock enable
.mclk_wkup (mclk_wkup), // Main System Clock wake-up (asynchronous)
.oscoff (oscoff), // Turns off LFXT1 clock input
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.reset_n (reset_n), // Reset Pin (low active, asynchronous)
.scan_enable (scan_enable), // Scan enable (active during scan shifting)
.scan_mode (scan_mode), // Scan mode
.scg0 (scg0), // System clock generator 1. Turns off the DCO
.scg1 (scg1), // System clock generator 1. Turns off the SMCLK
.wdt_reset (wdt_reset) // Watchdog-timer reset
);
assign mclk = dma_mclk;
//=============================================================================
// 3) FRONTEND (<=> FETCH & DECODE)
//=============================================================================
omsp_frontend frontend_0 (
// OUTPUTs
.cpu_halt_st (cpu_halt_st), // Halt/Run status from CPU
.decode_noirq (decode_noirq), // Frontend decode instruction
.e_state (e_state), // Execution state
.exec_done (exec_done), // Execution completed
.inst_ad (inst_ad), // Decoded Inst: destination addressing mode
.inst_as (inst_as), // Decoded Inst: source addressing mode
.inst_alu (inst_alu), // ALU control signals
.inst_bw (inst_bw), // Decoded Inst: byte width
.inst_dest (inst_dest), // Decoded Inst: destination (one hot)
.inst_dext (inst_dext), // Decoded Inst: destination extended instruction word
.inst_irq_rst (inst_irq_rst), // Decoded Inst: Reset interrupt
.inst_jmp (inst_jmp), // Decoded Inst: Conditional jump
.inst_mov (inst_mov), // Decoded Inst: mov instruction
.inst_sext (inst_sext), // Decoded Inst: source extended instruction word
.inst_so (inst_so), // Decoded Inst: Single-operand arithmetic
.inst_src (inst_src), // Decoded Inst: source (one hot)
.inst_type (inst_type), // Decoded Instruction type
.irq_acc (irq_acc), // Interrupt request accepted
.mab (fe_mab), // Frontend Memory address bus
.mb_en (fe_mb_en), // Frontend Memory bus enable
.mclk_dma_enable (mclk_dma_enable), // DMA Sub-System Clock enable
.mclk_dma_wkup (mclk_dma_wkup), // DMA Sub-System Clock wake-up (asynchronous)
.mclk_enable (mclk_enable), // Main System Clock enable
.mclk_wkup (mclk_wkup), // Main System Clock wake-up (asynchronous)
.nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted
.pc (pc), // Program counter
.pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ)
// INPUTs
.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
.cpu_halt_cmd (cpu_halt_cmd), // Halt CPU command
.cpuoff (cpuoff), // Turns off the CPU
.dbg_reg_sel (dbg_mem_addr[3:0]), // Debug selected register for rd/wr access
.dma_en (dma_en), // Direct Memory Access enable (high active)
.dma_wkup (dma_wkup), // DMA Sub-System Wake-up (asynchronous and non-glitchy)
.fe_pmem_wait (fe_pmem_wait), // Frontend wait for Instruction fetch
.gie (gie), // General interrupt enable
.irq (irq), // Maskable interrupts
.mclk (cpu_mclk), // Main system clock
.mdb_in (fe_mdb_in), // Frontend Memory data bus input
.nmi_pnd (nmi_pnd), // Non-maskable interrupt pending
.nmi_wkup (nmi_wkup), // NMI Wakeup
.pc_sw (pc_sw), // Program counter software value
.pc_sw_wr (pc_sw_wr), // Program counter software write
.puc_rst (puc_rst), // Main system reset
.scan_enable (scan_enable), // Scan enable (active during scan shifting)
.wdt_irq (wdt_irq), // Watchdog-timer interrupt
.wdt_wkup (wdt_wkup), // Watchdog Wakeup
.wkup (wkup) // System Wake-up (asynchronous)
);
//=============================================================================
// 4) EXECUTION UNIT
//=============================================================================
omsp_execution_unit execution_unit_0 (
// OUTPUTs
.cpuoff (cpuoff), // Turns off the CPU
.dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input
.mab (eu_mab), // Memory address bus
.mb_en (eu_mb_en), // Memory bus enable
.mb_wr (eu_mb_wr), // Memory bus write transfer
.mdb_out (eu_mdb_out), // Memory data bus output
.oscoff (oscoff), // Turns off LFXT1 clock input
.pc_sw (pc_sw), // Program counter software value
.pc_sw_wr (pc_sw_wr), // Program counter software write
.scg0 (scg0), // System clock generator 1. Turns off the DCO
.scg1 (scg1), // System clock generator 1. Turns off the SMCLK
// INPUTs
.dbg_halt_st (cpu_halt_st), // Halt/Run status from CPU
.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
.dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write
.e_state (e_state), // Execution state
.exec_done (exec_done), // Execution completed
.gie (gie), // General interrupt enable
.inst_ad (inst_ad), // Decoded Inst: destination addressing mode
.inst_as (inst_as), // Decoded Inst: source addressing mode
.inst_alu (inst_alu), // ALU control signals
.inst_bw (inst_bw), // Decoded Inst: byte width
.inst_dest (inst_dest), // Decoded Inst: destination (one hot)
.inst_dext (inst_dext), // Decoded Inst: destination extended instruction word
.inst_irq_rst (inst_irq_rst), // Decoded Inst: reset interrupt
.inst_jmp (inst_jmp), // Decoded Inst: Conditional jump
.inst_mov (inst_mov), // Decoded Inst: mov instruction
.inst_sext (inst_sext), // Decoded Inst: source extended instruction word
.inst_so (inst_so), // Decoded Inst: Single-operand arithmetic
.inst_src (inst_src), // Decoded Inst: source (one hot)
.inst_type (inst_type), // Decoded Instruction type
.mclk (cpu_mclk), // Main system clock
.mdb_in (eu_mdb_in), // Memory data bus input
.pc (pc), // Program counter
.pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ)
.puc_rst (puc_rst), // Main system reset
.scan_enable (scan_enable) // Scan enable (active during scan shifting)
);
//=============================================================================
// 5) MEMORY BACKBONE
//=============================================================================
omsp_mem_backbone mem_backbone_0 (
// OUTPUTs
.cpu_halt_cmd (cpu_halt_cmd), // Halt CPU command
.dbg_mem_din (dbg_mem_din), // Debug unit Memory data input
.dmem_addr (dmem_addr), // Data Memory address
.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
.dmem_din (dmem_din), // Data Memory data input
.dmem_wen (dmem_wen), // Data Memory write enable (low active)
.eu_mdb_in (eu_mdb_in), // Execution Unit Memory data bus input
.fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input
.fe_pmem_wait (fe_pmem_wait), // Frontend wait for Instruction fetch
.dma_dout (dma_dout), // Direct Memory Access data output
.dma_ready (dma_ready), // Direct Memory Access is complete
.dma_resp (dma_resp), // Direct Memory Access response (0:Okay / 1:Error)
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_we (per_we), // Peripheral write enable (high active)
.per_en (per_en), // Peripheral enable (high active)
.pmem_addr (pmem_addr), // Program Memory address
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
.pmem_din (pmem_din), // Program Memory data input (optional)
.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
// INPUTs
.cpu_halt_st (cpu_halt_st), // Halt/Run status from CPU
.dbg_halt_cmd (dbg_halt_cmd), // Debug interface Halt CPU command
.dbg_mem_addr (dbg_mem_addr[15:1]), // Debug address for rd/wr access
.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
.dbg_mem_en (dbg_mem_en), // Debug unit memory enable
.dbg_mem_wr (dbg_mem_wr), // Debug unit memory write
.dmem_dout (dmem_dout), // Data Memory data output
.eu_mab (eu_mab[15:1]), // Execution Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution Unit Memory bus write transfer
.eu_mdb_out (eu_mdb_out), // Execution Unit Memory data bus output
.fe_mab (fe_mab[15:1]), // Frontend Memory address bus
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
.mclk (dma_mclk), // Main system clock
.dma_addr (dma_addr), // Direct Memory Access address
.dma_din (dma_din), // Direct Memory Access data input
.dma_en (dma_en), // Direct Memory Access enable (high active)
.dma_priority (dma_priority), // Direct Memory Access priority (0:low / 1:high)
.dma_we (dma_we), // Direct Memory Access write byte enable (high active)
.per_dout (per_dout_or), // Peripheral data output
.pmem_dout (pmem_dout), // Program Memory data output
.puc_rst (puc_rst), // Main system reset
.scan_enable (scan_enable) // Scan enable (active during scan shifting)
);
wire UNUSED_fe_mab_0 = fe_mab[0];
//=============================================================================
// 6) SPECIAL FUNCTION REGISTERS
//=============================================================================
omsp_sfr sfr_0 (
// OUTPUTs
.cpu_id (cpu_id), // CPU ID
.nmi_pnd (nmi_pnd), // NMI Pending
.nmi_wkup (nmi_wkup), // NMI Wakeup
.per_dout (per_dout_sfr), // Peripheral data output
.wdtie (wdtie), // Watchdog-timer interrupt enable
.wdtifg_sw_clr (wdtifg_sw_clr), // Watchdog-timer interrupt flag software clear
.wdtifg_sw_set (wdtifg_sw_set), // Watchdog-timer interrupt flag software set
// INPUTs
.cpu_nr_inst (cpu_nr_inst), // Current oMSP instance number
.cpu_nr_total (cpu_nr_total), // Total number of oMSP instances-1
.mclk (dma_mclk), // Main system clock
.nmi (nmi), // Non-maskable interrupt (asynchronous)
.nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc_rst (puc_rst), // Main system reset
.scan_mode (scan_mode), // Scan mode
.wdtifg (wdtifg), // Watchdog-timer interrupt flag
.wdtnmies (wdtnmies) // Watchdog-timer NMI edge selection
);
//=============================================================================
// 7) WATCHDOG TIMER
//=============================================================================
`ifdef WATCHDOG
omsp_watchdog watchdog_0 (
// OUTPUTs
.per_dout (per_dout_wdog), // Peripheral data output
.wdt_irq (wdt_irq), // Watchdog-timer interrupt
.wdt_reset (wdt_reset), // Watchdog-timer reset
.wdt_wkup (wdt_wkup), // Watchdog Wakeup
.wdtifg (wdtifg), // Watchdog-timer interrupt flag
.wdtnmies (wdtnmies), // Watchdog-timer NMI edge selection
// INPUTs
.aclk (aclk), // ACLK
.aclk_en (aclk_en), // ACLK enable
.dbg_freeze (dbg_freeze), // Freeze Watchdog counter
.mclk (dma_mclk), // Main system clock
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.por (por), // Power-on reset
.puc_rst (puc_rst), // Main system reset
.scan_enable (scan_enable), // Scan enable (active during scan shifting)
.scan_mode (scan_mode), // Scan mode
.smclk (smclk), // SMCLK
.smclk_en (smclk_en), // SMCLK enable
.wdtie (wdtie), // Watchdog-timer interrupt enable
.wdtifg_irq_clr (irq_acc[`IRQ_NR-6]), // Clear Watchdog-timer interrupt flag
.wdtifg_sw_clr (wdtifg_sw_clr), // Watchdog-timer interrupt flag software clear
.wdtifg_sw_set (wdtifg_sw_set) // Watchdog-timer interrupt flag software set
);
`else
assign per_dout_wdog = 16\'h0000;
assign wdt_irq = 1\'b0;
assign wdt_reset = 1\'b0;
assign wdt_wkup = 1\'b0;
assign wdtifg = 1\'b0;
assign wdtnmies = 1\'b0;
wire UNUSED_por = por;
wire UNUSED_wdtie = wdtie;
wire UNUSED_wdtifg_sw_clr = wdtifg_sw_clr;
wire UNUSED_wdtifg_sw_set = wdtifg_sw_set;
`endif
//=============================================================================
// 8) HARDWARE MULTIPLIER
//=============================================================================
`ifdef MULTIPLIER
omsp_multiplier multiplier_0 (
// OUTPUTs
.per_dout (per_dout_mpy), // Peripheral data output
// INPUTs
.mclk (dma_mclk), // Main system clock
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc_rst (puc_rst), // Main system reset
.scan_enable (scan_enable) // Scan enable (active during scan shifting)
);
`else
assign per_dout_mpy = 16\'h0000;
`endif
//=============================================================================
// 9) PERIPHERALS\' OUTPUT BUS
//=============================================================================
assign per_dout_or = per_dout |
per_dout_clk |
per_dout_sfr |
per_dout_wdog |
per_dout_mpy;
//=============================================================================
// 10) DEBUG INTERFACE
//=============================================================================
`ifdef DBG_EN
omsp_dbg dbg_0 (
// OUTPUTs
.dbg_cpu_reset (dbg_cpu_reset), // Reset CPU from debug interface
.dbg_freeze (dbg_freeze), // Freeze peripherals
.dbg_halt_cmd (dbg_halt_cmd), // Halt CPU command
.dbg_i2c_sda_out (dbg_i2c_sda_out), // Debug interface: I2C SDA OUT
.dbg_mem_addr (dbg_mem_addr), // Debug address for rd/wr access
.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
.dbg_mem_en (dbg_mem_en), // Debug unit memory enable
.dbg_mem_wr (dbg_mem_wr), // Debug unit memory write
.dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write
.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
// INPUTs
.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
.cpu_id (cpu_id), // CPU ID
.cpu_nr_inst (cpu_nr_inst), // Current oMSP instance number
.cpu_nr_total (cpu_nr_total), // Total number of oMSP instances-1
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_en_s (dbg_en_s), // Debug interface enable (synchronous)
.dbg_halt_st (cpu_halt_st), // Halt/Run status from CPU
.dbg_i2c_addr (dbg_i2c_addr), // Debug interface: I2C Address
.dbg_i2c_broadcast (dbg_i2c_broadcast), // Debug interface: I2C Broadcast Address (for multicore systems)
.dbg_i2c_scl (dbg_i2c_scl), // Debug interface: I2C SCL
.dbg_i2c_sda_in (dbg_i2c_sda_in), // Debug interface: I2C SDA IN
.dbg_mem_din (dbg_mem_din), // Debug unit Memory data input
.dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input
.dbg_rst (dbg_rst), // Debug unit reset
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD (asynchronous)
.decode_noirq (decode_noirq), // Frontend decode instruction
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
.fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input
.pc (pc), // Program counter
.puc_pnd_set (puc_pnd_set) // PUC pending set for the serial debug interface
);
`else
assign dbg_cpu_reset = 1\'b0;
assign dbg_freeze = ~cpu_en_s;
assign dbg_halt_cmd = 1\'b0;
assign dbg_i2c_sda_out = 1\'b1;
assign dbg_mem_addr = 16\'h0000;
assign dbg_mem_dout = 16\'h0000;
assign dbg_mem_en = 1\'b0;
assign dbg_mem_wr = 2\'b00;
assign dbg_reg_wr = 1\'b0;
assign dbg_uart_txd = 1\'b1;
wire UNUSED_decode_noirq = decode_noirq;
wire [31:0] UNUSED_cpu_id = cpu_id;
wire UNUSED_eu_mab_0 = eu_mab[0];
wire UNUSED_dbg_clk = dbg_clk;
wire UNUSED_dbg_rst = dbg_rst;
wire UNUSED_dbg_en_s = dbg_en_s;
wire [15:0] UNUSED_dbg_mem_din = dbg_mem_din;
wire [15:0] UNUSED_dbg_reg_din = dbg_reg_din;
wire UNUSED_puc_pnd_set = puc_pnd_set;
wire [6:0] UNUSED_dbg_i2c_addr = dbg_i2c_addr;
wire [6:0] UNUSED_dbg_i2c_broadcast = dbg_i2c_broadcast;
wire UNUSED_dbg_i2c_scl = dbg_i2c_scl;
wire UNUSED_dbg_i2c_sda_in = dbg_i2c_sda_in;
wire UNUSED_dbg_uart_rxd = dbg_uart_rxd;
`endif
endmodule // openMSP430
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_register_file.v
//
// *Module Description:
// openMSP430 Register files
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module omsp_register_file (
// OUTPUTs
cpuoff, // Turns off the CPU
gie, // General interrupt enable
oscoff, // Turns off LFXT1 clock input
pc_sw, // Program counter software value
pc_sw_wr, // Program counter software write
reg_dest, // Selected register destination content
reg_src, // Selected register source content
scg0, // System clock generator 1. Turns off the DCO
scg1, // System clock generator 1. Turns off the SMCLK
status, // R2 Status {V,N,Z,C}
// INPUTs
alu_stat, // ALU Status {V,N,Z,C}
alu_stat_wr, // ALU Status write {V,N,Z,C}
inst_bw, // Decoded Inst: byte width
inst_dest, // Register destination selection
inst_src, // Register source selection
mclk, // Main system clock
pc, // Program counter
puc_rst, // Main system reset
reg_dest_val, // Selected register destination value
reg_dest_wr, // Write selected register destination
reg_pc_call, // Trigger PC update for a CALL instruction
reg_sp_val, // Stack Pointer next value
reg_sp_wr, // Stack Pointer write
reg_sr_wr, // Status register update for RETI instruction
reg_sr_clr, // Status register clear for interrupts
reg_incr, // Increment source register
scan_enable // Scan enable (active during scan shifting)
);
// OUTPUTs
//=========
output cpuoff; // Turns off the CPU
output gie; // General interrupt enable
output oscoff; // Turns off LFXT1 clock input
output [15:0] pc_sw; // Program counter software value
output pc_sw_wr; // Program counter software write
output [15:0] reg_dest; // Selected register destination content
output [15:0] reg_src; // Selected register source content
output scg0; // System clock generator 1. Turns off the DCO
output scg1; // System clock generator 1. Turns off the SMCLK
output [3:0] status; // R2 Status {V,N,Z,C}
// INPUTs
//=========
input [3:0] alu_stat; // ALU Status {V,N,Z,C}
input [3:0] alu_stat_wr; // ALU Status write {V,N,Z,C}
input inst_bw; // Decoded Inst: byte width
input [15:0] inst_dest; // Register destination selection
input [15:0] inst_src; // Register source selection
input mclk; // Main system clock
input [15:0] pc; // Program counter
input puc_rst; // Main system reset
input [15:0] reg_dest_val; // Selected register destination value
input reg_dest_wr; // Write selected register destination
input reg_pc_call; // Trigger PC update for a CALL instruction
input [15:0] reg_sp_val; // Stack Pointer next value
input reg_sp_wr; // Stack Pointer write
input reg_sr_wr; // Status register update for RETI instruction
input reg_sr_clr; // Status register clear for interrupts
input reg_incr; // Increment source register
input scan_enable; // Scan enable (active during scan shifting)
//=============================================================================
// 1) AUTOINCREMENT UNIT
//=============================================================================
wire [15:0] inst_src_in;
wire [15:0] incr_op = (inst_bw & ~inst_src_in[1]) ? 16\'h0001 : 16\'h0002;
wire [15:0] reg_incr_val = reg_src+incr_op;
wire [15:0] reg_dest_val_in = inst_bw ? {8\'h00,reg_dest_val[7:0]} : reg_dest_val;
//=============================================================================
// 2) SPECIAL REGISTERS (R1/R2/R3)
//=============================================================================
// Source input selection mask (for interrupt support)
//-----------------------------------------------------
assign inst_src_in = reg_sr_clr ? 16\'h0004 : inst_src;
// R0: Program counter
//---------------------
wire [15:0] r0 = pc;
wire [15:0] pc_sw = reg_dest_val_in;
wire pc_sw_wr = (inst_dest[0] & reg_dest_wr) | reg_pc_call;
// R1: Stack pointer
//-------------------
reg [15:0] r1;
wire r1_wr = inst_dest[1] & reg_dest_wr;
wire r1_inc = inst_src_in[1] & reg_incr;
`ifdef CLOCK_GATING
wire r1_en = r1_wr | reg_sp_wr | r1_inc;
wire mclk_r1;
omsp_clock_gate clock_gate_r1 (.gclk(mclk_r1),
.clk (mclk), .enable(r1_en), .scan_enable(scan_enable));
`else
wire UNUSED_scan_enable = scan_enable;
wire mclk_r1 = mclk;
`endif
always @(posedge mclk_r1 or posedge puc_rst)
if (puc_rst) r1 <= 16\'h0000;
else if (r1_wr) r1 <= reg_dest_val_in & 16\'hfffe;
else if (reg_sp_wr) r1 <= reg_sp_val & 16\'hfffe;
`ifdef CLOCK_GATING
else r1 <= reg_incr_val & 16\'hfffe;
`else
else if (r1_inc) r1 <= reg_incr_val & 16\'hfffe;
`endif
wire UNUSED_reg_sp_val_0 = reg_sp_val[0];
// R2: Status register
//---------------------
reg [15:0] r2;
wire r2_wr = (inst_dest[2] & reg_dest_wr) | reg_sr_wr;
`ifdef CLOCK_GATING // -- WITH CLOCK GATING --
wire r2_c = alu_stat_wr[0] ? alu_stat[0] : reg_dest_val_in[0]; // C
wire r2_z = alu_stat_wr[1] ? alu_stat[1] : reg_dest_val_in[1]; // Z
wire r2_n = alu_stat_wr[2] ? alu_stat[2] : reg_dest_val_in[2]; // N
wire [7:3] r2_nxt = r2_wr ? reg_dest_val_in[7:3] : r2[7:3];
wire r2_v = alu_stat_wr[3] ? alu_stat[3] : reg_dest_val_in[8]; // V
wire r2_en = |alu_stat_wr | r2_wr | reg_sr_clr;
wire mclk_r2;
omsp_clock_gate clock_gate_r2 (.gclk(mclk_r2),
.clk (mclk), .enable(r2_en), .scan_enable(scan_enable));
`else // -- WITHOUT CLOCK GATING --
wire r2_c = alu_stat_wr[0] ? alu_stat[0] :
r2_wr ? reg_dest_val_in[0] : r2[0]; // C
wire r2_z = alu_stat_wr[1] ? alu_stat[1] :
r2_wr ? reg_dest_val_in[1] : r2[1]; // Z
wire r2_n = alu_stat_wr[2] ? alu_stat[2] :
r2_wr ? reg_dest_val_in[2] : r2[2]; // N
wire [7:3] r2_nxt = r2_wr ? reg_dest_val_in[7:3] : r2[7:3];
wire r2_v = alu_stat_wr[3] ? alu_stat[3] :
r2_wr ? reg_dest_val_in[8] : r2[8]; // V
wire mclk_r2 = mclk;
`endif
`ifdef ASIC_CLOCKING
`ifdef CPUOFF_EN
wire [15:0] cpuoff_mask = 16\'h0010;
`else
wire [15:0] cpuoff_mask = 16\'h0000;
`endif
`ifdef OSCOFF_EN
wire [15:0] oscoff_mask = 16\'h0020;
`else
wire [15:0] oscoff_mask = 16\'h0000;
`endif
`ifdef SCG0_EN
wire [15:0] scg0_mask = 16\'h0040;
`else
wire [15:0] scg0_mask = 16\'h0000;
`endif
`ifdef SCG1_EN
wire [15:0] scg1_mask = 16\'h0080;
`else
wire [15:0] scg1_mask = 16\'h0000;
`endif
`else
wire [15:0] cpuoff_mask = 16\'h0010; // For the FPGA version: - the CPUOFF mode is emulated
wire [15:0] oscoff_mask = 16\'h0020; // - the SCG1 mode is emulated
wire [15:0] scg0_mask = 16\'h0000; // - the SCG0 is not supported
wire [15:0] scg1_mask = 16\'h0080; // - the SCG1 mode is emulated
`endif
wire [15:0] r2_mask = cpuoff_mask | oscoff_mask | scg0_mask | scg1_mask | 16\'h010f;
always @(posedge mclk_r2 or posedge puc_rst)
if (puc_rst) r2 <= 16\'h0000;
else if (reg_sr_clr) r2 <= 16\'h0000;
else r2 <= {7\'h00, r2_v, r2_nxt, r2_n, r2_z, r2_c} & r2_mask;
assign status = {r2[8], r2[2:0]};
assign gie = r2[3];
assign cpuoff = r2[4] | (r2_nxt[4] & r2_wr & cpuoff_mask[4]);
assign oscoff = r2[5];
assign scg0 = r2[6];
assign scg1 = r2[7];
// R3: Constant generator
//-------------------------------------------------------------
// Note: the auto-increment feature is not implemented for R3
// because the @R3+ addressing mode is used for constant
// generation (#-1).
reg [15:0] r3;
wire r3_wr = inst_dest[3] & reg_dest_wr;
`ifdef CLOCK_GATING
wire r3_en = r3_wr;
wire mclk_r3;
omsp_clock_gate clock_gate_r3 (.gclk(mclk_r3),
.clk (mclk), .enable(r3_en), .scan_enable(scan_enable));
`else
wire mclk_r3 = mclk;
`endif
always @(posedge mclk_r3 or posedge puc_rst)
if (puc_rst) r3 <= 16\'h0000;
`ifdef CLOCK_GATING
else r3 <= reg_dest_val_in;
`else
else if (r3_wr) r3 <= reg_dest_val_in;
`endif
//=============================================================================
// 4) GENERAL PURPOSE REGISTERS (R4...R15)
//=============================================================================
// R4
//------------
reg [15:0] r4;
wire r4_wr = inst_dest[4] & reg_dest_wr;
wire r4_inc = inst_src_in[4] & reg_incr;
`ifdef CLOCK_GATING
wire r4_en = r4_wr | r4_inc;
wire mclk_r4;
omsp_clock_gate clock_gate_r4 (.gclk(mclk_r4),
.clk (mclk), .enable(r4_en), .scan_enable(scan_enable));
`else
wire mclk_r4 = mclk;
`endif
always @(posedge mclk_r4 or posedge puc_rst)
if (puc_rst) r4 <= 16\'h0000;
else if (r4_wr) r4 <= reg_dest_val_in;
`ifdef CLOCK_GATING
else r4 <= reg_incr_val;
`else
else if (r4_inc) r4 <= reg_incr_val;
`endif
// R5
//------------
reg [15:0] r5;
wire r5_wr = inst_dest[5] & reg_dest_wr;
wire r5_inc = inst_src_in[5] & reg_incr;
`ifdef CLOCK_GATING
wire r5_en = r5_wr | r5_inc;
wire mclk_r5;
omsp_clock_gate clock_gate_r5 (.gclk(mclk_r5),
.clk (mclk), .enable(r5_en), .scan_enable(scan_enable));
`else
wire mclk_r5 = mclk;
`endif
always @(posedge mclk_r5 or posedge puc_rst)
if (puc_rst) r5 <= 16\'h0000;
else if (r5_wr) r5 <= reg_dest_val_in;
`ifdef CLOCK_GATING
else r5 <= reg_incr_val;
`else
else if (r5_inc) r5 <= reg_incr_val;
`endif
// R6
//------------
reg [15:0] r6;
wire r6_wr = inst_dest[6] & reg_dest_wr;
wire r6_inc = inst_src_in[6] & reg_incr;
`ifdef CLOCK_GATING
wire r6_en = r6_wr | r6_inc;
wire mclk_r6;
omsp_clock_gate clock_gate_r6 (.gclk(mclk_r6),
.clk (mclk), .enable(r6_en), .scan_enable(scan_enable));
`else
wire mclk_r6 = mclk;
`endif
always @(posedge mclk_r6 or posedge puc_rst)
if (puc_rst) r6 <= 16\'h0000;
else if (r6_wr) r6 <= reg_dest_val_in;
`ifdef CLOCK_GATING
else r6 <= reg_incr_val;
`else
else if (r6_inc) r6 <= reg_incr_val;
`endif
// R7
//------------
reg [15:0] r7;
wire r7_wr = inst_dest[7] & reg_dest_wr;
wire r7_inc = inst_src_in[7] & reg_incr;
`ifdef CLOCK_GATING
wire r7_en = r7_wr | r7_inc;
wire mclk_r7;
omsp_clock_gate clock_gate_r7 (.gclk(mclk_r7),
.clk (mclk), .enable(r7_en), .scan_enable(scan_enable));
`else
wire mclk_r7 = mclk;
`endif
always @(posedge mclk_r7 or posedge puc_rst)
if (puc_rst) r7 <= 16\'h0000;
else if (r7_wr) r7 <= reg_dest_val_in;
`ifdef CLOCK_GATING
else r7 <= reg_incr_val;
`else
else if (r7_inc) r7 <= reg_incr_val;
`endif
// R8
//------------
reg [15:0] r8;
wire r8_wr = inst_dest[8] & reg_dest_wr;
wire r8_inc = inst_src_in[8] & reg_incr;
`ifdef CLOCK_GATING
wire r8_en = r8_wr | r8_inc;
wire mclk_r8;
omsp_clock_gate clock_gate_r8 (.gclk(mclk_r8),
.clk (mclk), .enable(r8_en), .scan_enable(scan_enable));
`else
wire mclk_r8 = mclk;
`endif
always @(posedge mclk_r8 or posedge puc_rst)
if (puc_rst) r8 <= 16\'h0000;
else if (r8_wr) r8 <= reg_dest_val_in;
`ifdef CLOCK_GATING
else r8 <= reg_incr_val;
`else
else if (r8_inc) r8 <= reg_incr_val;
`endif
// R9
//------------
reg [15:0] r9;
wire r9_wr = inst_dest[9] & reg_dest_wr;
wire r9_inc = inst_src_in[9] & reg_incr;
`ifdef CLOCK_GATING
wire r9_en = r9_wr | r9_inc;
wire mclk_r9;
omsp_clock_gate clock_gate_r9 (.gclk(mclk_r9),
.clk (mclk), .enable(r9_en), .scan_enable(scan_enable));
`else
wire mclk_r9 = mclk;
`endif
always @(posedge mclk_r9 or posedge puc_rst)
if (puc_rst) r9 <= 16\'h0000;
else if (r9_wr) r9 <= reg_dest_val_in;
`ifdef CLOCK_GATING
else r9 <= reg_incr_val;
`else
else if (r9_inc) r9 <= reg_incr_val;
`endif
// R10
//------------
reg [15:0] r10;
wire r10_wr = inst_dest[10] & reg_dest_wr;
wire r10_inc = inst_src_in[10] & reg_incr;
`ifdef CLOCK_GATING
wire r10_en = r10_wr | r10_inc;
wire mclk_r10;
omsp_clock_gate clock_gate_r10 (.gclk(mclk_r10),
.clk (mclk), .enable(r10_en), .scan_enable(scan_enable));
`else
wire mclk_r10 = mclk;
`endif
always @(posedge mclk_r10 or posedge puc_rst)
if (puc_rst) r10 <= 16\'h0000;
else if (r10_wr) r10 <= reg_dest_val_in;
`ifdef CLOCK_GATING
else r10 <= reg_incr_val;
`else
else if (r10_inc) r10 <= reg_incr_val;
`endif
// R11
//------------
reg [15:0] r11;
wire r11_wr = inst_dest[11] & reg_dest_wr;
wire r11_inc = inst_src_in[11] & reg_incr;
`ifdef CLOCK_GATING
wire r11_en = r11_wr | r11_inc;
wire mclk_r11;
omsp_clock_gate clock_gate_r11 (.gclk(mclk_r11),
.clk (mclk), .enable(r11_en), .scan_enable(scan_enable));
`else
wire mclk_r11 = mclk;
`endif
always @(posedge mclk_r11 or posedge puc_rst)
if (puc_rst) r11 <= 16\'h0000;
else if (r11_wr) r11 <= reg_dest_val_in;
`ifdef CLOCK_GATING
else r11 <= reg_incr_val;
`else
else if (r11_inc) r11 <= reg_incr_val;
`endif
// R12
//------------
reg [15:0] r12;
wire r12_wr = inst_dest[12] & reg_dest_wr;
wire r12_inc = inst_src_in[12] & reg_incr;
`ifdef CLOCK_GATING
wire r12_en = r12_wr | r12_inc;
wire mclk_r12;
omsp_clock_gate clock_gate_r12 (.gclk(mclk_r12),
.clk (mclk), .enable(r12_en), .scan_enable(scan_enable));
`else
wire mclk_r12 = mclk;
`endif
always @(posedge mclk_r12 or posedge puc_rst)
if (puc_rst) r12 <= 16\'h0000;
else if (r12_wr) r12 <= reg_dest_val_in;
`ifdef CLOCK_GATING
else r12 <= reg_incr_val;
`else
else if (r12_inc) r12 <= reg_incr_val;
`endif
// R13
//------------
reg [15:0] r13;
wire r13_wr = inst_dest[13] & reg_dest_wr;
wire r13_inc = inst_src_in[13] & reg_incr;
`ifdef CLOCK_GATING
wire r13_en = r13_wr | r13_inc;
wire mclk_r13;
omsp_clock_gate clock_gate_r13 (.gclk(mclk_r13),
.clk (mclk), .enable(r13_en), .scan_enable(scan_enable));
`else
wire mclk_r13 = mclk;
`endif
always @(posedge mclk_r13 or posedge puc_rst)
if (puc_rst) r13 <= 16\'h0000;
else if (r13_wr) r13 <= reg_dest_val_in;
`ifdef CLOCK_GATING
else r13 <= reg_incr_val;
`else
else if (r13_inc) r13 <= reg_incr_val;
`endif
// R14
//------------
reg [15:0] r14;
wire r14_wr = inst_dest[14] & reg_dest_wr;
wire r14_inc = inst_src_in[14] & reg_incr;
`ifdef CLOCK_GATING
wire r14_en = r14_wr | r14_inc;
wire mclk_r14;
omsp_clock_gate clock_gate_r14 (.gclk(mclk_r14),
.clk (mclk), .enable(r14_en), .scan_enable(scan_enable));
`else
wire mclk_r14 = mclk;
`endif
always @(posedge mclk_r14 or posedge puc_rst)
if (puc_rst) r14 <= 16\'h0000;
else if (r14_wr) r14 <= reg_dest_val_in;
`ifdef CLOCK_GATING
else r14 <= reg_incr_val;
`else
else if (r14_inc) r14 <= reg_incr_val;
`endif
// R15
//------------
reg [15:0] r15;
wire r15_wr = inst_dest[15] & reg_dest_wr;
wire r15_inc = inst_src_in[15] & reg_incr;
`ifdef CLOCK_GATING
wire r15_en = r15_wr | r15_inc;
wire mclk_r15;
omsp_clock_gate clock_gate_r15 (.gclk(mclk_r15),
.clk (mclk), .enable(r15_en), .scan_enable(scan_enable));
`else
wire mclk_r15 = mclk;
`endif
always @(posedge mclk_r15 or posedge puc_rst)
if (puc_rst) r15 <= 16\'h0000;
else if (r15_wr) r15 <= reg_dest_val_in;
`ifdef CLOCK_GATING
else r15 <= reg_incr_val;
`else
else if (r15_inc) r15 <= reg_incr_val;
`endif
//=============================================================================
// 5) READ MUX
//=============================================================================
assign reg_src = (r0 & {16{inst_src_in[0]}}) |
(r1 & {16{inst_src_in[1]}}) |
(r2 & {16{inst_src_in[2]}}) |
(r3 & {16{inst_src_in[3]}}) |
(r4 & {16{inst_src_in[4]}}) |
(r5 & {16{inst_src_in[5]}}) |
(r6 & {16{inst_src_in[6]}}) |
(r7 & {16{inst_src_in[7]}}) |
(r8 & {16{inst_src_in[8]}}) |
(r9 & {16{inst_src_in[9]}}) |
(r10 & {16{inst_src_in[10]}}) |
(r11 & {16{inst_src_in[11]}}) |
(r12 & {16{inst_src_in[12]}}) |
(r13 & {16{inst_src_in[13]}}) |
(r14 & {16{inst_src_in[14]}}) |
(r15 & {16{inst_src_in[15]}});
assign reg_dest = (r0 & {16{inst_dest[0]}}) |
(r1 & {16{inst_dest[1]}}) |
(r2 & {16{inst_dest[2]}}) |
(r3 & {16{inst_dest[3]}}) |
(r4 & {16{inst_dest[4]}}) |
(r5 & {16{inst_dest[5]}}) |
(r6 & {16{inst_dest[6]}}) |
(r7 & {16{inst_dest[7]}}) |
(r8 & {16{inst_dest[8]}}) |
(r9 & {16{inst_dest[9]}}) |
(r10 & {16{inst_dest[10]}}) |
(r11 & {16{inst_dest[11]}}) |
(r12 & {16{inst_dest[12]}}) |
(r13 & {16{inst_dest[13]}}) |
(r14 & {16{inst_dest[14]}}) |
(r15 & {16{inst_dest[15]}});
endmodule // omsp_register_file
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_timerA_defines.v
//
// *Module Description:
// omsp_timerA Configuration file
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
//`define OMSP_TA_NO_INCLUDE
`ifdef OMSP_TA_NO_INCLUDE
`else
`include "omsp_timerA_undefines.v"
`endif
//----------------------------------------------------------------------------
// TIMER A CONFIGURATION
//----------------------------------------------------------------------------
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
// Timer A: TACTL Control Register
`define TASSELx 9:8
`define TAIDx 7:6
`define TAMCx 5:4
`define TACLR 2
`define TAIE 1
`define TAIFG 0
// Timer A: TACCTLx Capture/Compare Control Register
`define TACMx 15:14
`define TACCISx 13:12
`define TASCS 11
`define TASCCI 10
`define TACAP 8
`define TAOUTMODx 7:5
`define TACCIE 4
`define TACCI 3
`define TAOUT 2
`define TACOV 1
`define TACCIFG 0
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_dbg.v
//
// *Module Description:
// Debug interface
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module omsp_dbg (
// OUTPUTs
dbg_cpu_reset, // Reset CPU from debug interface
dbg_freeze, // Freeze peripherals
dbg_halt_cmd, // Halt CPU command
dbg_i2c_sda_out, // Debug interface: I2C SDA OUT
dbg_mem_addr, // Debug address for rd/wr access
dbg_mem_dout, // Debug unit data output
dbg_mem_en, // Debug unit memory enable
dbg_mem_wr, // Debug unit memory write
dbg_reg_wr, // Debug unit CPU register write
dbg_uart_txd, // Debug interface: UART TXD
// INPUTs
cpu_en_s, // Enable CPU code execution (synchronous)
cpu_id, // CPU ID
cpu_nr_inst, // Current oMSP instance number
cpu_nr_total, // Total number of oMSP instances-1
dbg_clk, // Debug unit clock
dbg_en_s, // Debug interface enable (synchronous)
dbg_halt_st, // Halt/Run status from CPU
dbg_i2c_addr, // Debug interface: I2C Address
dbg_i2c_broadcast, // Debug interface: I2C Broadcast Address (for multicore systems)
dbg_i2c_scl, // Debug interface: I2C SCL
dbg_i2c_sda_in, // Debug interface: I2C SDA IN
dbg_mem_din, // Debug unit Memory data input
dbg_reg_din, // Debug unit CPU register data input
dbg_rst, // Debug unit reset
dbg_uart_rxd, // Debug interface: UART RXD (asynchronous)
decode_noirq, // Frontend decode instruction
eu_mab, // Execution-Unit Memory address bus
eu_mb_en, // Execution-Unit Memory bus enable
eu_mb_wr, // Execution-Unit Memory bus write transfer
fe_mdb_in, // Frontend Memory data bus input
pc, // Program counter
puc_pnd_set // PUC pending set for the serial debug interface
);
// OUTPUTs
//=========
output dbg_cpu_reset; // Reset CPU from debug interface
output dbg_freeze; // Freeze peripherals
output dbg_halt_cmd; // Halt CPU command
output dbg_i2c_sda_out; // Debug interface: I2C SDA OUT
output [15:0] dbg_mem_addr; // Debug address for rd/wr access
output [15:0] dbg_mem_dout; // Debug unit data output
output dbg_mem_en; // Debug unit memory enable
output [1:0] dbg_mem_wr; // Debug unit memory write
output dbg_reg_wr; // Debug unit CPU register write
output dbg_uart_txd; // Debug interface: UART TXD
// INPUTs
//=========
input cpu_en_s; // Enable CPU code execution (synchronous)
input [31:0] cpu_id; // CPU ID
input [7:0] cpu_nr_inst; // Current oMSP instance number
input [7:0] cpu_nr_total; // Total number of oMSP instances-1
input dbg_clk; // Debug unit clock
input dbg_en_s; // Debug interface enable (synchronous)
input dbg_halt_st; // Halt/Run status from CPU
input [6:0] dbg_i2c_addr; // Debug interface: I2C Address
input [6:0] dbg_i2c_broadcast; // Debug interface: I2C Broadcast Address (for multicore systems)
input dbg_i2c_scl; // Debug interface: I2C SCL
input dbg_i2c_sda_in; // Debug interface: I2C SDA IN
input [15:0] dbg_mem_din; // Debug unit Memory data input
input [15:0] dbg_reg_din; // Debug unit CPU register data input
input dbg_rst; // Debug unit reset
input dbg_uart_rxd; // Debug interface: UART RXD (asynchronous)
input decode_noirq; // Frontend decode instruction
input [15:0] eu_mab; // Execution-Unit Memory address bus
input eu_mb_en; // Execution-Unit Memory bus enable
input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer
input [15:0] fe_mdb_in; // Frontend Memory data bus input
input [15:0] pc; // Program counter
input puc_pnd_set; // PUC pending set for the serial debug interface
//=============================================================================
// 1) WIRE & PARAMETER DECLARATION
//=============================================================================
// Diverse wires and registers
wire [5:0] dbg_addr;
wire [15:0] dbg_din;
wire dbg_wr;
reg mem_burst;
wire dbg_reg_rd;
wire dbg_mem_rd;
reg dbg_mem_rd_dly;
wire dbg_swbrk;
wire dbg_rd;
reg dbg_rd_rdy;
wire mem_burst_rd;
wire mem_burst_wr;
wire brk0_halt;
wire brk0_pnd;
wire [15:0] brk0_dout;
wire brk1_halt;
wire brk1_pnd;
wire [15:0] brk1_dout;
wire brk2_halt;
wire brk2_pnd;
wire [15:0] brk2_dout;
wire brk3_halt;
wire brk3_pnd;
wire [15:0] brk3_dout;
// Number of registers
parameter NR_REG = 25;
// Register addresses
parameter CPU_ID_LO = 6\'h00;
parameter CPU_ID_HI = 6\'h01;
parameter CPU_CTL = 6\'h02;
parameter CPU_STAT = 6\'h03;
parameter MEM_CTL = 6\'h04;
parameter MEM_ADDR = 6\'h05;
parameter MEM_DATA = 6\'h06;
parameter MEM_CNT = 6\'h07;
`ifdef DBG_HWBRK_0
parameter BRK0_CTL = 6\'h08;
parameter BRK0_STAT = 6\'h09;
parameter BRK0_ADDR0 = 6\'h0A;
parameter BRK0_ADDR1 = 6\'h0B;
`endif
`ifdef DBG_HWBRK_1
parameter BRK1_CTL = 6\'h0C;
parameter BRK1_STAT = 6\'h0D;
parameter BRK1_ADDR0 = 6\'h0E;
parameter BRK1_ADDR1 = 6\'h0F;
`endif
`ifdef DBG_HWBRK_2
parameter BRK2_CTL = 6\'h10;
parameter BRK2_STAT = 6\'h11;
parameter BRK2_ADDR0 = 6\'h12;
parameter BRK2_ADDR1 = 6\'h13;
`endif
`ifdef DBG_HWBRK_3
parameter BRK3_CTL = 6\'h14;
parameter BRK3_STAT = 6\'h15;
parameter BRK3_ADDR0 = 6\'h16;
parameter BRK3_ADDR1 = 6\'h17;
`endif
parameter CPU_NR = 6\'h18;
// Register one-hot decoder
parameter BASE_D = {{NR_REG-1{1\'b0}}, 1\'b1};
parameter CPU_ID_LO_D = (BASE_D << CPU_ID_LO);
parameter CPU_ID_HI_D = (BASE_D << CPU_ID_HI);
parameter CPU_CTL_D = (BASE_D << CPU_CTL);
parameter CPU_STAT_D = (BASE_D << CPU_STAT);
parameter MEM_CTL_D = (BASE_D << MEM_CTL);
parameter MEM_ADDR_D = (BASE_D << MEM_ADDR);
parameter MEM_DATA_D = (BASE_D << MEM_DATA);
parameter MEM_CNT_D = (BASE_D << MEM_CNT);
`ifdef DBG_HWBRK_0
parameter BRK0_CTL_D = (BASE_D << BRK0_CTL);
parameter BRK0_STAT_D = (BASE_D << BRK0_STAT);
parameter BRK0_ADDR0_D = (BASE_D << BRK0_ADDR0);
parameter BRK0_ADDR1_D = (BASE_D << BRK0_ADDR1);
`endif
`ifdef DBG_HWBRK_1
parameter BRK1_CTL_D = (BASE_D << BRK1_CTL);
parameter BRK1_STAT_D = (BASE_D << BRK1_STAT);
parameter BRK1_ADDR0_D = (BASE_D << BRK1_ADDR0);
parameter BRK1_ADDR1_D = (BASE_D << BRK1_ADDR1);
`endif
`ifdef DBG_HWBRK_2
parameter BRK2_CTL_D = (BASE_D << BRK2_CTL);
parameter BRK2_STAT_D = (BASE_D << BRK2_STAT);
parameter BRK2_ADDR0_D = (BASE_D << BRK2_ADDR0);
parameter BRK2_ADDR1_D = (BASE_D << BRK2_ADDR1);
`endif
`ifdef DBG_HWBRK_3
parameter BRK3_CTL_D = (BASE_D << BRK3_CTL);
parameter BRK3_STAT_D = (BASE_D << BRK3_STAT);
parameter BRK3_ADDR0_D = (BASE_D << BRK3_ADDR0);
parameter BRK3_ADDR1_D = (BASE_D << BRK3_ADDR1);
`endif
parameter CPU_NR_D = (BASE_D << CPU_NR);
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Select Data register during a burst
wire [5:0] dbg_addr_in = mem_burst ? MEM_DATA : dbg_addr;
// Register address decode
reg [NR_REG-1:0] reg_dec;
always @(dbg_addr_in)
case (dbg_addr_in)
CPU_ID_LO : reg_dec = CPU_ID_LO_D;
CPU_ID_HI : reg_dec = CPU_ID_HI_D;
CPU_CTL : reg_dec = CPU_CTL_D;
CPU_STAT : reg_dec = CPU_STAT_D;
MEM_CTL : reg_dec = MEM_CTL_D;
MEM_ADDR : reg_dec = MEM_ADDR_D;
MEM_DATA : reg_dec = MEM_DATA_D;
MEM_CNT : reg_dec = MEM_CNT_D;
`ifdef DBG_HWBRK_0
BRK0_CTL : reg_dec = BRK0_CTL_D;
BRK0_STAT : reg_dec = BRK0_STAT_D;
BRK0_ADDR0: reg_dec = BRK0_ADDR0_D;
BRK0_ADDR1: reg_dec = BRK0_ADDR1_D;
`endif
`ifdef DBG_HWBRK_1
BRK1_CTL : reg_dec = BRK1_CTL_D;
BRK1_STAT : reg_dec = BRK1_STAT_D;
BRK1_ADDR0: reg_dec = BRK1_ADDR0_D;
BRK1_ADDR1: reg_dec = BRK1_ADDR1_D;
`endif
`ifdef DBG_HWBRK_2
BRK2_CTL : reg_dec = BRK2_CTL_D;
BRK2_STAT : reg_dec = BRK2_STAT_D;
BRK2_ADDR0: reg_dec = BRK2_ADDR0_D;
BRK2_ADDR1: reg_dec = BRK2_ADDR1_D;
`endif
`ifdef DBG_HWBRK_3
BRK3_CTL : reg_dec = BRK3_CTL_D;
BRK3_STAT : reg_dec = BRK3_STAT_D;
BRK3_ADDR0: reg_dec = BRK3_ADDR0_D;
BRK3_ADDR1: reg_dec = BRK3_ADDR1_D;
`endif
CPU_NR : reg_dec = CPU_NR_D;
// pragma coverage off
default: reg_dec = {NR_REG{1\'b0}};
// pragma coverage on
endcase
// Read/Write probes
wire reg_write = dbg_wr;
wire reg_read = 1\'b1;
// Read/Write vectors
wire [NR_REG-1:0] reg_wr = reg_dec & {NR_REG{reg_write}};
wire [NR_REG-1:0] reg_rd = reg_dec & {NR_REG{reg_read}};
//=============================================================================
// 3) REGISTER: CORE INTERFACE
//=============================================================================
// CPU_ID Register
//-----------------
// -------------------------------------------------------------------
// CPU_ID_LO: | 15 14 13 12 11 10 9 | 8 7 6 5 4 | 3 | 2 1 0 |
// |----------------------------+-----------------+------+-------------|
// | PER_SPACE | USER_VERSION | ASIC | CPU_VERSION |
// --------------------------------------------------------------------
// CPU_ID_HI: | 15 14 13 12 11 10 | 9 8 7 6 5 4 3 2 1 | 0 |
// |----------------------------+-------------------------------+------|
// | PMEM_SIZE | DMEM_SIZE | MPY |
// -------------------------------------------------------------------
// This register is assigned in the SFR module
// CPU_NR Register
//-----------------
// -------------------------------------------------------------------
// | 15 14 13 12 11 10 9 8 | 7 6 5 4 3 2 1 0 |
// |---------------------------------+---------------------------------|
// | CPU_TOTAL_NR | CPU_INST_NR |
// -------------------------------------------------------------------
wire [15:0] cpu_nr = {cpu_nr_total, cpu_nr_inst};
// CPU_CTL Register
//-----------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// Reserved CPU_RST RST_BRK_EN FRZ_BRK_EN SW_BRK_EN ISTEP RUN HALT
//-----------------------------------------------------------------------------
reg [6:3] cpu_ctl;
wire cpu_ctl_wr = reg_wr[CPU_CTL];
always @ (posedge dbg_clk or posedge dbg_rst)
`ifdef DBG_RST_BRK_EN
if (dbg_rst) cpu_ctl <= 4\'h6;
`else
if (dbg_rst) cpu_ctl <= 4\'h2;
`endif
else if (cpu_ctl_wr) cpu_ctl <= dbg_din[6:3];
wire [7:0] cpu_ctl_full = {1\'b0, cpu_ctl, 3\'b000};
wire halt_cpu = cpu_ctl_wr & dbg_din[`HALT] & ~dbg_halt_st;
wire run_cpu = cpu_ctl_wr & dbg_din[`RUN] & dbg_halt_st;
wire istep = cpu_ctl_wr & dbg_din[`ISTEP] & dbg_halt_st;
// CPU_STAT Register
//------------------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// HWBRK3_PND HWBRK2_PND HWBRK1_PND HWBRK0_PND SWBRK_PND PUC_PND Res. HALT_RUN
//------------------------------------------------------------------------------------
reg [3:2] cpu_stat;
wire cpu_stat_wr = reg_wr[CPU_STAT];
wire [3:2] cpu_stat_set = {dbg_swbrk, puc_pnd_set};
wire [3:2] cpu_stat_clr = ~dbg_din[3:2];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) cpu_stat <= 2\'b00;
else if (cpu_stat_wr) cpu_stat <= ((cpu_stat & cpu_stat_clr) | cpu_stat_set);
else cpu_stat <= (cpu_stat | cpu_stat_set);
wire [7:0] cpu_stat_full = {brk3_pnd, brk2_pnd, brk1_pnd, brk0_pnd,
cpu_stat, 1\'b0, dbg_halt_st};
//=============================================================================
// 4) REGISTER: MEMORY INTERFACE
//=============================================================================
// MEM_CTL Register
//-----------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// Reserved B/W MEM/REG RD/WR START
//
// START : - 0 : Do nothing.
// - 1 : Initiate memory transfer.
//
// RD/WR : - 0 : Read access.
// - 1 : Write access.
//
// MEM/REG: - 0 : Memory access.
// - 1 : CPU Register access.
//
// B/W : - 0 : 16 bit access.
// - 1 : 8 bit access (not valid for CPU Registers).
//
//-----------------------------------------------------------------------------
reg [3:1] mem_ctl;
wire mem_ctl_wr = reg_wr[MEM_CTL];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_ctl <= 3\'h0;
else if (mem_ctl_wr) mem_ctl <= dbg_din[3:1];
wire [7:0] mem_ctl_full = {4\'b0000, mem_ctl, 1\'b0};
reg mem_start;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_start <= 1\'b0;
else mem_start <= mem_ctl_wr & dbg_din[0];
wire mem_bw = mem_ctl[3];
// MEM_DATA Register
//------------------
reg [15:0] mem_data;
reg [15:0] mem_addr;
wire mem_access;
wire mem_data_wr = reg_wr[MEM_DATA];
wire [15:0] dbg_mem_din_bw = ~mem_bw ? dbg_mem_din :
mem_addr[0] ? {8\'h00, dbg_mem_din[15:8]} :
{8\'h00, dbg_mem_din[7:0]};
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_data <= 16\'h0000;
else if (mem_data_wr) mem_data <= dbg_din;
else if (dbg_reg_rd) mem_data <= dbg_reg_din;
else if (dbg_mem_rd_dly) mem_data <= dbg_mem_din_bw;
// MEM_ADDR Register
//------------------
reg [15:0] mem_cnt;
wire mem_addr_wr = reg_wr[MEM_ADDR];
wire dbg_mem_acc = (|dbg_mem_wr | (dbg_rd_rdy & ~mem_ctl[2]));
wire dbg_reg_acc = ( dbg_reg_wr | (dbg_rd_rdy & mem_ctl[2]));
wire [15:0] mem_addr_inc = (mem_cnt==16\'h0000) ? 16\'h0000 :
(mem_burst & dbg_mem_acc & ~mem_bw) ? 16\'h0002 :
(mem_burst & (dbg_mem_acc | dbg_reg_acc)) ? 16\'h0001 : 16\'h0000;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_addr <= 16\'h0000;
else if (mem_addr_wr) mem_addr <= dbg_din;
else mem_addr <= mem_addr + mem_addr_inc;
// MEM_CNT Register
//------------------
wire mem_cnt_wr = reg_wr[MEM_CNT];
wire [15:0] mem_cnt_dec = (mem_cnt==16\'h0000) ? 16\'h0000 :
(mem_burst & (dbg_mem_acc | dbg_reg_acc)) ? 16\'hffff : 16\'h0000;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_cnt <= 16\'h0000;
else if (mem_cnt_wr) mem_cnt <= dbg_din;
else mem_cnt <= mem_cnt + mem_cnt_dec;
//=============================================================================
// 5) BREAKPOINTS / WATCHPOINTS
//=============================================================================
`ifdef DBG_HWBRK_0
// Hardware Breakpoint/Watchpoint Register read select
wire [3:0] brk0_reg_rd = {reg_rd[BRK0_ADDR1],
reg_rd[BRK0_ADDR0],
reg_rd[BRK0_STAT],
reg_rd[BRK0_CTL]};
// Hardware Breakpoint/Watchpoint Register write select
wire [3:0] brk0_reg_wr = {reg_wr[BRK0_ADDR1],
reg_wr[BRK0_ADDR0],
reg_wr[BRK0_STAT],
reg_wr[BRK0_CTL]};
omsp_dbg_hwbrk dbg_hwbr_0 (
// OUTPUTs
.brk_halt (brk0_halt), // Hardware breakpoint command
.brk_pnd (brk0_pnd), // Hardware break/watch-point pending
.brk_dout (brk0_dout), // Hardware break/watch-point register data input
// INPUTs
.brk_reg_rd (brk0_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk0_reg_wr), // Hardware break/watch-point register write select
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_din (dbg_din), // Debug register data input
.dbg_rst (dbg_rst), // Debug unit reset
.decode_noirq (decode_noirq), // Frontend decode instruction
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
.pc (pc) // Program counter
);
`else
assign brk0_halt = 1\'b0;
assign brk0_pnd = 1\'b0;
assign brk0_dout = 16\'h0000;
wire [15:0] UNUSED_eu_mab = eu_mab;
wire UNUSED_eu_mb_en = eu_mb_en;
wire [1:0] UNUSED_eu_mb_wr = eu_mb_wr;
wire [15:0] UNUSED_pc = pc;
`endif
`ifdef DBG_HWBRK_1
// Hardware Breakpoint/Watchpoint Register read select
wire [3:0] brk1_reg_rd = {reg_rd[BRK1_ADDR1],
reg_rd[BRK1_ADDR0],
reg_rd[BRK1_STAT],
reg_rd[BRK1_CTL]};
// Hardware Breakpoint/Watchpoint Register write select
wire [3:0] brk1_reg_wr = {reg_wr[BRK1_ADDR1],
reg_wr[BRK1_ADDR0],
reg_wr[BRK1_STAT],
reg_wr[BRK1_CTL]};
omsp_dbg_hwbrk dbg_hwbr_1 (
// OUTPUTs
.brk_halt (brk1_halt), // Hardware breakpoint command
.brk_pnd (brk1_pnd), // Hardware break/watch-point pending
.brk_dout (brk1_dout), // Hardware break/watch-point register data input
// INPUTs
.brk_reg_rd (brk1_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk1_reg_wr), // Hardware break/watch-point register write select
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_din (dbg_din), // Debug register data input
.dbg_rst (dbg_rst), // Debug unit reset
.decode_noirq (decode_noirq), // Frontend decode instruction
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
.pc (pc) // Program counter
);
`else
assign brk1_halt = 1\'b0;
assign brk1_pnd = 1\'b0;
assign brk1_dout = 16\'h0000;
`endif
`ifdef DBG_HWBRK_2
// Hardware Breakpoint/Watchpoint Register read select
wire [3:0] brk2_reg_rd = {reg_rd[BRK2_ADDR1],
reg_rd[BRK2_ADDR0],
reg_rd[BRK2_STAT],
reg_rd[BRK2_CTL]};
// Hardware Breakpoint/Watchpoint Register write select
wire [3:0] brk2_reg_wr = {reg_wr[BRK2_ADDR1],
reg_wr[BRK2_ADDR0],
reg_wr[BRK2_STAT],
reg_wr[BRK2_CTL]};
omsp_dbg_hwbrk dbg_hwbr_2 (
// OUTPUTs
.brk_halt (brk2_halt), // Hardware breakpoint command
.brk_pnd (brk2_pnd), // Hardware break/watch-point pending
.brk_dout (brk2_dout), // Hardware break/watch-point register data input
// INPUTs
.brk_reg_rd (brk2_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk2_reg_wr), // Hardware break/watch-point register write select
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_din (dbg_din), // Debug register data input
.dbg_rst (dbg_rst), // Debug unit reset
.decode_noirq (decode_noirq), // Frontend decode instruction
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
.pc (pc) // Program counter
);
`else
assign brk2_halt = 1\'b0;
assign brk2_pnd = 1\'b0;
assign brk2_dout = 16\'h0000;
`endif
`ifdef DBG_HWBRK_3
// Hardware Breakpoint/Watchpoint Register read select
wire [3:0] brk3_reg_rd = {reg_rd[BRK3_ADDR1],
reg_rd[BRK3_ADDR0],
reg_rd[BRK3_STAT],
reg_rd[BRK3_CTL]};
// Hardware Breakpoint/Watchpoint Register write select
wire [3:0] brk3_reg_wr = {reg_wr[BRK3_ADDR1],
reg_wr[BRK3_ADDR0],
reg_wr[BRK3_STAT],
reg_wr[BRK3_CTL]};
omsp_dbg_hwbrk dbg_hwbr_3 (
// OUTPUTs
.brk_halt (brk3_halt), // Hardware breakpoint command
.brk_pnd (brk3_pnd), // Hardware break/watch-point pending
.brk_dout (brk3_dout), // Hardware break/watch-point register data input
// INPUTs
.brk_reg_rd (brk3_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk3_reg_wr), // Hardware break/watch-point register write select
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_din (dbg_din), // Debug register data input
.dbg_rst (dbg_rst), // Debug unit reset
.decode_noirq (decode_noirq), // Frontend decode instruction
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
.pc (pc) // Program counter
);
`else
assign brk3_halt = 1\'b0;
assign brk3_pnd = 1\'b0;
assign brk3_dout = 16\'h0000;
`endif
//============================================================================
// 6) DATA OUTPUT GENERATION
//============================================================================
wire [15:0] cpu_id_lo_rd = cpu_id[15:0] & {16{reg_rd[CPU_ID_LO]}};
wire [15:0] cpu_id_hi_rd = cpu_id[31:16] & {16{reg_rd[CPU_ID_HI]}};
wire [15:0] cpu_ctl_rd = {8\'h00, cpu_ctl_full} & {16{reg_rd[CPU_CTL]}};
wire [15:0] cpu_stat_rd = {8\'h00, cpu_stat_full} & {16{reg_rd[CPU_STAT]}};
wire [15:0] mem_ctl_rd = {8\'h00, mem_ctl_full} & {16{reg_rd[MEM_CTL]}};
wire [15:0] mem_data_rd = mem_data & {16{reg_rd[MEM_DATA]}};
wire [15:0] mem_addr_rd = mem_addr & {16{reg_rd[MEM_ADDR]}};
wire [15:0] mem_cnt_rd = mem_cnt & {16{reg_rd[MEM_CNT]}};
wire [15:0] cpu_nr_rd = cpu_nr & {16{reg_rd[CPU_NR]}};
wire [15:0] dbg_dout = cpu_id_lo_rd |
cpu_id_hi_rd |
cpu_ctl_rd |
cpu_stat_rd |
mem_ctl_rd |
mem_data_rd |
mem_addr_rd |
mem_cnt_rd |
brk0_dout |
brk1_dout |
brk2_dout |
brk3_dout |
cpu_nr_rd;
// Tell UART/I2C interface that the data is ready to be read
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_rd_rdy <= 1\'b0;
else if (mem_burst | mem_burst_rd) dbg_rd_rdy <= (dbg_reg_rd | dbg_mem_rd_dly);
else dbg_rd_rdy <= dbg_rd;
//============================================================================
// 7) CPU CONTROL
//============================================================================
// Reset CPU
//--------------------------
wire dbg_cpu_reset = cpu_ctl[`CPU_RST];
// Break after reset
//--------------------------
wire halt_rst = cpu_ctl[`RST_BRK_EN] & dbg_en_s & puc_pnd_set;
// Freeze peripherals
//--------------------------
wire dbg_freeze = dbg_halt_st & (cpu_ctl[`FRZ_BRK_EN] | ~cpu_en_s);
// Software break
//--------------------------
assign dbg_swbrk = (fe_mdb_in==`DBG_SWBRK_OP) & decode_noirq & cpu_ctl[`SW_BRK_EN];
// Single step
//--------------------------
reg [1:0] inc_step;
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) inc_step <= 2\'b00;
else if (istep) inc_step <= 2\'b11;
else inc_step <= {inc_step[0], 1\'b0};
// Run / Halt
//--------------------------
reg halt_flag;
wire mem_halt_cpu;
wire mem_run_cpu;
wire halt_flag_clr = run_cpu | mem_run_cpu;
wire halt_flag_set = halt_cpu | halt_rst | dbg_swbrk | mem_halt_cpu |
brk0_halt | brk1_halt | brk2_halt | brk3_halt;
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) halt_flag <= 1\'b0;
else if (halt_flag_clr) halt_flag <= 1\'b0;
else if (halt_flag_set) halt_flag <= 1\'b1;
wire dbg_halt_cmd = (halt_flag | halt_flag_set) & ~inc_step[1];
//============================================================================
// 8) MEMORY CONTROL
//============================================================================
// Control Memory bursts
//------------------------------
wire mem_burst_start = (mem_start & |mem_cnt);
wire mem_burst_end = ((dbg_wr | dbg_rd_rdy) & ~|mem_cnt);
// Detect when burst is on going
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_burst <= 1\'b0;
else if (mem_burst_start) mem_burst <= 1\'b1;
else if (mem_burst_end) mem_burst <= 1\'b0;
// Control signals for UART/I2C interface
assign mem_burst_rd = (mem_burst_start & ~mem_ctl[1]);
assign mem_burst_wr = (mem_burst_start & mem_ctl[1]);
// Trigger CPU Register or memory access during a burst
reg mem_startb;
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_startb <= 1\'b0;
else mem_startb <= (mem_burst & (dbg_wr | dbg_rd)) | mem_burst_rd;
// Combine single and burst memory start of sequence
wire mem_seq_start = ((mem_start & ~|mem_cnt) | mem_startb);
// Memory access state machine
//------------------------------
reg [1:0] mem_state;
reg [1:0] mem_state_nxt;
// State machine definition
parameter M_IDLE = 2\'h0;
parameter M_SET_BRK = 2\'h1;
parameter M_ACCESS_BRK = 2\'h2;
parameter M_ACCESS = 2\'h3;
// State transition
always @(mem_state or mem_seq_start or dbg_halt_st)
case (mem_state)
M_IDLE : mem_state_nxt = ~mem_seq_start ? M_IDLE :
dbg_halt_st ? M_ACCESS : M_SET_BRK;
M_SET_BRK : mem_state_nxt = dbg_halt_st ? M_ACCESS_BRK : M_SET_BRK;
M_ACCESS_BRK : mem_state_nxt = M_IDLE;
M_ACCESS : mem_state_nxt = M_IDLE;
// pragma coverage off
default : mem_state_nxt = M_IDLE;
// pragma coverage on
endcase
// State machine
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_state <= M_IDLE;
else mem_state <= mem_state_nxt;
// Utility signals
assign mem_halt_cpu = (mem_state==M_IDLE) & (mem_state_nxt==M_SET_BRK);
assign mem_run_cpu = (mem_state==M_ACCESS_BRK) & (mem_state_nxt==M_IDLE);
assign mem_access = (mem_state==M_ACCESS) | (mem_state==M_ACCESS_BRK);
// Interface to CPU Registers and Memory bacbkone
//------------------------------------------------
assign dbg_mem_addr = mem_addr;
assign dbg_mem_dout = ~mem_bw ? mem_data :
mem_addr[0] ? {mem_data[7:0], 8\'h00} :
{8\'h00, mem_data[7:0]};
assign dbg_reg_wr = mem_access & mem_ctl[1] & mem_ctl[2];
assign dbg_reg_rd = mem_access & ~mem_ctl[1] & mem_ctl[2];
assign dbg_mem_en = mem_access & ~mem_ctl[2];
assign dbg_mem_rd = dbg_mem_en & ~mem_ctl[1];
wire [1:0] dbg_mem_wr_msk = ~mem_bw ? 2\'b11 :
mem_addr[0] ? 2\'b10 : 2\'b01;
assign dbg_mem_wr = {2{dbg_mem_en & mem_ctl[1]}} & dbg_mem_wr_msk;
// It takes one additional cycle to read from Memory as from registers
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_mem_rd_dly <= 1\'b0;
else dbg_mem_rd_dly <= dbg_mem_rd;
//=============================================================================
// 9) UART COMMUNICATION
//=============================================================================
`ifdef DBG_UART
omsp_dbg_uart dbg_uart_0 (
// OUTPUTs
.dbg_addr (dbg_addr), // Debug register address
.dbg_din (dbg_din), // Debug register data input
.dbg_rd (dbg_rd), // Debug register data read
.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
.dbg_wr (dbg_wr), // Debug register data write
// INPUTs
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_dout (dbg_dout), // Debug register data output
.dbg_rd_rdy (dbg_rd_rdy), // Debug register data is ready for read
.dbg_rst (dbg_rst), // Debug unit reset
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD
.mem_burst (mem_burst), // Burst on going
.mem_burst_end (mem_burst_end), // End TX/RX burst
.mem_burst_rd (mem_burst_rd), // Start TX burst
.mem_burst_wr (mem_burst_wr), // Start RX burst
.mem_bw (mem_bw) // Burst byte width
);
`else
assign dbg_uart_txd = 1\'b1;
wire UNUSED_dbg_uart_rxd = dbg_uart_rxd;
`ifdef DBG_I2C
`else
assign dbg_addr = 6\'h00;
assign dbg_din = 16\'h0000;
assign dbg_rd = 1\'b0;
assign dbg_wr = 1\'b0;
`endif
`endif
//=============================================================================
// 10) I2C COMMUNICATION
//=============================================================================
`ifdef DBG_I2C
omsp_dbg_i2c dbg_i2c_0 (
// OUTPUTs
.dbg_addr (dbg_addr), // Debug register address
.dbg_din (dbg_din), // Debug register data input
.dbg_i2c_sda_out (dbg_i2c_sda_out), // Debug interface: I2C SDA OUT
.dbg_rd (dbg_rd), // Debug register data read
.dbg_wr (dbg_wr), // Debug register data write
// INPUTs
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_dout (dbg_dout), // Debug register data output
.dbg_i2c_addr (dbg_i2c_addr), // Debug interface: I2C Address
.dbg_i2c_broadcast (dbg_i2c_broadcast), // Debug interface: I2C Broadcast Address (for multicore systems)
.dbg_i2c_scl (dbg_i2c_scl), // Debug interface: I2C SCL
.dbg_i2c_sda_in (dbg_i2c_sda_in), // Debug interface: I2C SDA IN
.dbg_rst (dbg_rst), // Debug unit reset
.mem_burst (mem_burst), // Burst on going
.mem_burst_end (mem_burst_end), // End TX/RX burst
.mem_burst_rd (mem_burst_rd), // Start TX burst
.mem_burst_wr (mem_burst_wr), // Start RX burst
.mem_bw (mem_bw) // Burst byte width
);
`else
assign dbg_i2c_sda_out = 1\'b1;
wire [6:0] UNUSED_dbg_i2c_addr = dbg_i2c_addr;
wire [6:0] UNUSED_dbg_i2c_broadcast = dbg_i2c_broadcast;
wire UNUSED_dbg_i2c_scl = dbg_i2c_scl;
wire UNUSED_dbg_i2c_sda_in = dbg_i2c_sda_in;
wire UNUSED_dbg_rd_rdy = dbg_rd_rdy;
`endif
endmodule // omsp_dbg
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
import "DPI-C" context function int init_socket();
import "DPI-C" context function void close_socket();
import "DPI-C" context function void senduart(input bit[7:0] in);
import "DPI-C" context function bit[8:0] recuart();
module simuart(input wire\t\tclk,
\t input wire\t\tcs,
\t input wire [31:0]\tbus_addr,
\t input wire [31:0]\tbus_wr_val,\t
\t input wire [3:0]\t\tbus_bytesel,
\t output reg\t\tbus_ack,
\t output reg [31:0]\tbus_data,
output reg inter,
input wire intack
);
reg [8:0] uart_buf;
reg ff;
reg ffold;
initial begin
\tbus_ack = 1\'b0;
\tbus_data = 32\'b0;
inter = 1\'b0;
init_socket();
end
final begin
close_socket();
end
always @(posedge clk) begin
\tbus_data <= 32\'b0;
ff <= 1\'b0;
ffold <= 1\'b0;
\tif (~uart_buf[8] && ~cs)
\t uart_buf <= recuart();
ff<=ffold;
if (uart_buf[8] && (uart_buf[7:0]==8\'h3)) begin
if(intack==1\'b0) begin
inter <=1\'b1;
end else begin
uart_buf[8]<=1\'b0;
end
end else begin
if (cs && bus_bytesel[3:0] == 4\'b0001) begin
\t\tif (bus_addr[3:0] == 4\'b0000) begin
\t\t\tsenduart(bus_wr_val[7:0]);
\t\tend
if (bus_addr[3:0] == 4\'b1000) begin
\t\t\tinter<=1\'b0;
\t\tend
if (bus_addr[3:0] == 4\'b1100) begin
\t\t\tinter<=1\'b1;
\t\tend
\t end else if (cs) begin
\t\tif (bus_addr[3:0] == 4\'b0000) begin
\t\t\tbus_data <= {24\'b0, uart_buf[7:0]};
ff <= 1\'b1;
if (ff && ~ffold) uart_buf[8] <= 1\'b0;
end else if (bus_addr[3:0] == 4\'b0100) begin
\t\t\t/* Status register read. */
\t\t\tbus_data <= (uart_buf[8] ? 32\'b10 : 32\'b0);
\t\tend
\t end
end
\tbus_ack <= cs;
end
endmodule
|
module simuart(input wire\t\tclk,
\t input wire\t\tcs,
\t input wire [31:0]\tbus_addr,
\t input wire [31:0]\tbus_wr_val,\t
\t input wire [3:0]\t\tbus_bytesel,
\t output reg\t\tbus_ack,
\t output reg [31:0]\tbus_data,
output reg inter,
input wire intack
);
task write_data;
begin
\t$uart_put(bus_wr_val[7:0]);
end
endtask
task read_data;
begin
\t$uart_get(uart_buf);
end
endtask
reg [8:0]\tuart_buf = 9'b0;
wire uart_rdy\t= uart_buf[8];
wire [31:0] status_reg = (uart_rdy ? 32'b10 : 32'b0);
reg ff;
reg ffold;
initial begin
\tbus_ack = 1'b0;
\tbus_data = 32'b0;
inter = 1'b0;
end
always @(posedge clk) begin
\tbus_data <= 32'b0;
ff <= 1'b0;
ffold <= 1'b0;
\tif (~uart_rdy && ~cs)
\t\tread_data();
ff<=ffold;
if (uart_rdy && (uart_buf[7:0]==8'h3)) begin
if(intack==1'b0) begin
inter <=1'b1;
end else begin
uart_buf[8]<=1'b0;
end
end else begin
if (cs && bus_bytesel[3:0] == 4'b0001) begin
\t\tif (bus_addr[3:0] == 4'b0000) begin
\t\t\twrite_data();
\t\tend
if (bus_addr[3:0] == 4'b1000) begin
\t\t\tinter<=1'b0;
\t\tend
\t end else if (cs) begin
\t\tif (bus_addr[3:0] == 4'b0000) begin
\t\t\tbus_data <= {24'b0, uart_buf[7:0]};
ff <= 1'b1;
if (ff && ~ffold) uart_buf[8] <= 1'b0;
end else if (bus_addr[3:0] == 4'b0100) begin
\t\t\t/* Status register read. */
\t\t\tbus_data <= status_reg;
\t\tend
\t end
end
\tbus_ack <= cs;
end
endmodule
|
`timescale 1 ns / 1 ps
module system (
\tinput clk,
\tinput resetn,
\toutput trap,
output reg [7:0] out_byte,
\toutput reg out_byte_en
);
\t// 0x2000 32bit words = 0x8000 Byte = 32kByte memory
parameter MEMW_SIZE = 16\'h8000;
integer tb_idx;
\twire mem_valid;
\twire mem_instr;
\treg mem_ready;
\treg mem_ready_last;
\twire [31:0] mem_addr;
\twire [31:0] mem_wdata;
\twire [3:0] mem_wstrb;
\treg [31:0] mem_rdata;
wire uart_cs;
\twire [3:0] uart_wstrb;
wire [31:0] uart_rdata;
wire [31:0] irqs;
wire [31:0] eois;
\tpicorv32 picorv32_core (
\t\t.clk (clk ),
\t\t.resetn (resetn ),
\t\t.trap (trap ),
\t\t.mem_valid (mem_valid ),
\t\t.mem_instr (mem_instr ),
\t\t.mem_ready (mem_ready ),
\t\t.mem_addr (mem_addr ),
\t\t.mem_wdata (mem_wdata ),
\t\t.mem_wstrb (mem_wstrb ),
\t\t.mem_rdata (mem_rdata ),
.irq(irqs),
.eoi(eois)
\t);
`ifndef MEM_FILENAME
simuart uart(
\t\t.clk(clk),
\t\t.cs(uart_cs),
\t\t.bus_addr(mem_addr),
\t\t.bus_wr_val(mem_wdata),
\t\t.bus_bytesel(uart_wstrb),
\t\t.bus_ack(),
\t\t.bus_data(uart_rdata),
.inter(irqs[0]),
.intack(eois[0])
);
`else
assign uart_rdata = 32\'b0;
assign irqs = 32\'b0;
`endif
assign irqs[31:1] = 31\'b0;
assign uart_cs = mem_addr[31:4] == 28\'h1000000 && mem_valid;
assign uart_wstrb = mem_wstrb & mem_ready;
\treg [31:0] memory [0:MEMW_SIZE-1];
\tinitial begin
for (tb_idx=0; tb_idx < MEMW_SIZE; tb_idx=tb_idx+1)
memory[tb_idx] = 32\'b0;
`ifdef MEM_FILENAME
$readmemh(`MEM_FILENAME, memory);
`else
$readmemh("../firmware.hex", memory);
`endif
end
\treg [31:0] m_read_data;
\treg m_read_en;
\talways @(posedge clk) begin
\t\t\tm_read_en <= 0;
\t\t\tmem_ready <= mem_valid && !mem_ready_last && !mem_ready && m_read_en;
\t\t\tmem_ready_last <= mem_ready;
out_byte_en <= 0;
\t\t\t
\t\t\t(* parallel_case *)
\t\t\tcase (1)
\t\t\t\tmem_valid && !mem_ready && !mem_wstrb && (mem_addr >> 2) < MEMW_SIZE: begin
\t\t\t\t\tm_read_en <= 1;
\t\t\t\t m_read_data <= memory[mem_addr >> 2];
\t\t\t\t mem_rdata <= m_read_data;
\t\t\t\tend
\t\t\t\tmem_valid && !mem_ready && |mem_wstrb && (mem_addr >> 2) < MEMW_SIZE: begin
\t\t\t\t\tif (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
\t\t\t\t\tif (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
\t\t\t\t\tif (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
\t\t\t\t\tif (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
\t\t\t\t\tmem_ready <= 1;
\t\t\t\tend
\t\t\t\t
\t\t\t mem_valid && !mem_ready && !mem_wstrb && uart_cs: begin
\t\t\t\t\tm_read_en <= 1;
mem_rdata <= uart_rdata;
//mem_rdata <= m_read_data;
\t\t\t\tend
mem_valid && !mem_ready && |mem_wstrb && mem_addr == 32\'h2000_0000: begin
\t\t\t\t\tout_byte_en <= 1;
\t\t\t\t\tout_byte <= mem_wdata;
\t\t\t\t\tmem_ready <= 1;
\t\t\t\tend
\t\t\t\tmem_valid && !mem_ready && |mem_wstrb : begin
\t\t\t\t\tmem_ready <= 1;
\t\t\t\tend
\t\t\tendcase
if (resetn && out_byte_en) begin
\t\t\t $write("%c", out_byte);
\t\t end
\t\tend
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_sync_reset.v
//
// *Module Description:
// Generic reset synchronizer for the openMSP430
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
module omsp_sync_reset (
// OUTPUTs
rst_s, // Synchronized reset
// INPUTs
clk, // Receiving clock
rst_a // Asynchronous reset
);
// OUTPUTs
//=========
output rst_s; // Synchronized reset
// INPUTs
//=========
input clk; // Receiving clock
input rst_a; // Asynchronous reset
//=============================================================================
// 1) SYNCHRONIZER
//=============================================================================
reg [1:0] data_sync;
always @(posedge clk or posedge rst_a)
if (rst_a) data_sync <= 2\'b11;
else data_sync <= {data_sync[0], 1\'b0};
assign rst_s = data_sync[1];
endmodule // omsp_sync_reset
|
module rs232 (
\tinput clk,
\tinput resetn,
\tinput [ 3:0] ctrl_wr,
\tinput ctrl_rd,
\tinput [15:0] ctrl_addr,
\tinput [31:0] ctrl_wdat,
\toutput reg [31:0] ctrl_rdat,
\toutput reg ctrl_done,
input rxd,
\toutput reg txd
);
\tparameter integer BAUD_RATE = 115200;
\tparameter integer CLOCK_FREQ_HZ = 50000000;
\tlocalparam integer HALF_PERIOD = CLOCK_FREQ_HZ / (2 * BAUD_RATE);
\treg [7:0] send_din;
\twire [7:0] send_dout;
\treg send_shift_in;
\treg send_shift_out;
\twire [7:0] send_used_slots;
\twire [7:0] send_free_slots;
\treg [7:0] recv_din;
\twire [7:0] recv_dout;
\treg recv_shift_in;
\treg recv_shift_out;
\twire [7:0] recv_used_slots;
\twire [7:0] recv_free_slots;
\t
\treg [$clog2(3*HALF_PERIOD):0] rx_cnt;
\treg [3:0] rx_state;
\treg rxd_q;
\talways @(posedge clk) begin
\t\trxd_q <= rxd;
\t\trecv_shift_in <= 0;
\t\tif (!resetn) begin
\t\t\trx_state <= 0;
\t\t\trx_cnt <= 0;
\t\tend else
\t\tif (rx_cnt) begin
\t\t\trx_cnt <= rx_cnt - |1;
\t\tend else
\t\tif (rx_state == 0) begin
\t\t\tif (rxd_q && !rxd) begin
\t\t\t\trx_state <= rx_state + |1;
\t\t\t\trx_cnt <= 3*HALF_PERIOD;
\t\t\tend
\t\tend else begin
\t\t\trecv_din <= {rxd, recv_din[7:1]};
\t\t\trx_state <= rx_state + |1;
\t\t\trx_cnt <= 2*HALF_PERIOD;
\t\t\tif (rx_state == 8) begin
\t\t\t\trecv_shift_in <= 1;
\t\t\t\trx_state <= 0;
\t\t\tend
\t\tend
\tend
\treg [$clog2(2*HALF_PERIOD):0] tx_cnt;
\treg [3:0] tx_state;
\treg [7:0] tx_byte;
\talways @(posedge clk) begin
\t\tsend_shift_out <= 0;
\t\tif (!resetn) begin
\t\t\ttxd <= 1;
\t\t\ttx_state <= 0;
\t\t\ttx_cnt <= 0;
\t\tend else
\t\tif (tx_cnt) begin
\t\t\ttx_cnt <= tx_cnt - |1;
\t\tend else
\t\tif (tx_state == 0) begin
\t\t\tif (|send_used_slots) begin
\t\t\t\ttxd <= 0;
\t\t\t\tsend_shift_out <= 1;
\t\t\t\ttx_byte <= send_dout;
\t\t\t\ttx_cnt <= 2*HALF_PERIOD;
\t\t\t\ttx_state <= 1;
\t\t\tend
\t\tend else begin
\t\t\ttxd <= tx_byte[0];
\t\t\ttx_byte <= tx_byte[7:1];
\t\t\ttx_cnt <= 2*HALF_PERIOD;
\t\t\ttx_state <= tx_state + |1;
\t\t\tif (tx_state == 9) begin
\t\t\t\ttxd <= 1;
\t\t\t\ttx_state <= 0;
\t\t\tend
\t\tend
\tend
\ticosoc_mod_rs232_fifo send_fifo (
\t\t.clk (clk ),
\t\t.resetn (resetn ),
\t\t.din (send_din ),
\t\t.dout (send_dout ),
\t\t.shift_in (send_shift_in ),
\t\t.shift_out (send_shift_out ),
\t\t.used_slots(send_used_slots),
\t\t.free_slots(send_free_slots)
\t);
\ticosoc_mod_rs232_fifo recv_fifo (
\t\t.clk (clk ),
\t\t.resetn (resetn ),
\t\t.din (recv_din ),
\t\t.dout (recv_dout ),
\t\t.shift_in (recv_shift_in ),
\t\t.shift_out (recv_shift_out ),
\t\t.used_slots(recv_used_slots),
\t\t.free_slots(recv_free_slots)
\t);
\talways @(posedge clk) begin
\t\tctrl_rdat <= 'bx;
\t\tctrl_done <= 0;
\t\trecv_shift_out <= 0;
\t\tsend_shift_in <= 0;
\t\tsend_din <= 'bx;
\t\t// Register file:
\t\t// 0x00 shift data to/from send/recv fifos
\t\t// 0x04 number of unread bytes in recv fifo (read-only)
\t\t// 0x08 number of free bytes in send fifo (read-only)
\t\tif (resetn && !ctrl_done) begin
\t\t\tif (|ctrl_wr) begin
\t\t\t\tif (ctrl_addr == 0) begin
\t\t\t\t\tsend_shift_in <= 1;
\t\t\t\t\tsend_din <= ctrl_wdat;
\t\t\t\tend
\t\t\t\tctrl_done <= 1;
\t\t\tend
\t\t\tif (ctrl_rd) begin
\t\t\t\tif (ctrl_addr == 0) begin
\t\t\t\t\trecv_shift_out <= 1;
\t\t\t\t\tctrl_rdat <= recv_dout;
\t\t\t\tend
\t\t\t\tif (ctrl_addr == 4) ctrl_rdat <= recv_used_slots;
\t\t\t\tif (ctrl_addr == 8) ctrl_rdat <= send_free_slots;
\t\t\t\tctrl_done <= 1;
\t\t\tend
\t\tend
\tend
endmodule
module icosoc_mod_rs232_fifo (
\tinput clk,
\tinput resetn,
\tinput [7:0] din,
\toutput [7:0] dout,
\tinput shift_in,
\tinput shift_out,
\toutput reg [7:0] used_slots,
\toutput reg [7:0] free_slots
);
\treg [7:0] memory [0:255];
\treg [7:0] wptr, rptr;
\treg [7:0] memory_dout;
\treg [7:0] pass_dout;
\treg use_pass_dout;
\tassign dout = use_pass_dout ? pass_dout : memory_dout;
\twire do_shift_in = shift_in && |free_slots;
\twire do_shift_out = shift_out && |used_slots;
\talways @(posedge clk) begin
\t\tif (!resetn) begin
\t\t\twptr <= 0;
\t\t\trptr <= 0;
\t\t\tused_slots <= 0;
\t\t\tfree_slots <= 255;
\t\tend else begin
\t\t\tmemory[wptr] <= din;
\t\t\twptr <= wptr + do_shift_in;
\t\t\tmemory_dout <= memory[rptr + do_shift_out];
\t\t\trptr <= rptr + do_shift_out;
\t\t\tuse_pass_dout <= wptr == rptr;
\t\t\tpass_dout <= din;
\t\t\tif (do_shift_in && !do_shift_out) begin
\t\t\t\tused_slots <= used_slots + 1;
\t\t\t\tfree_slots <= free_slots - 1;
\t\t\tend
\t\t\tif (!do_shift_in && do_shift_out) begin
\t\t\t\tused_slots <= used_slots - 1;
\t\t\t\tfree_slots <= free_slots + 1;
\t\t\tend
\t\tend
\tend
endmodule
|
import "DPI-C" context function int init_socket();
import "DPI-C" context function void close_socket();
import "DPI-C" context function void senduart(input bit[7:0] in);
import "DPI-C" context function bit[8:0] recuart();
module simuart(input wire\t\tclk,
\t input wire\t\tcs,
\t input wire [31:0]\tbus_addr,
\t input wire [31:0]\tbus_wr_val,\t
\t input wire [3:0]\t\tbus_bytesel,
\t output reg\t\tbus_ack,
\t output reg [31:0]\tbus_data,
output reg inter,
input wire intack
);
reg [8:0] uart_buf;
reg ff;
reg ffold;
initial begin
\tbus_ack = 1\'b0;
\tbus_data = 32\'b0;
inter = 1\'b0;
`ifdef DBGUART
init_socket();
`endif
end
final begin
`ifdef DBGUART
close_socket();
`endif
end
always @(posedge clk) begin
\tbus_data <= 32\'b0;
ff <= 1\'b0;
ffold <= 1\'b0;
\tif (~uart_buf[8] && ~cs)
\t uart_buf <= recuart();
ff<=ffold;
if (uart_buf[8] && (uart_buf[7:0]==8\'h3)) begin
if(intack==1\'b0) begin
inter <=1\'b1;
end else begin
uart_buf[8]<=1\'b0;
end
end else begin
if (cs && bus_bytesel[3:0] == 4\'b0001) begin
\t\tif (bus_addr[3:0] == 4\'b0000) begin
\t\t\tsenduart(bus_wr_val[7:0]);
\t\tend
if (bus_addr[3:0] == 4\'b1000) begin
\t\t\tinter<=1\'b0;
\t\tend
if (bus_addr[3:0] == 4\'b1100) begin
\t\t\tinter<=1\'b1;
\t\tend
\t end else if (cs) begin
\t\tif (bus_addr[3:0] == 4\'b0000) begin
\t\t\tbus_data <= {24\'b0, uart_buf[7:0]};
ff <= 1\'b1;
if (ff && ~ffold) uart_buf[8] <= 1\'b0;
end else if (bus_addr[3:0] == 4\'b0100) begin
\t\t\t/* Status register read. */
\t\t\tbus_data <= (uart_buf[8] ? 32\'b10 : 32\'b0);
\t\tend
\t end
end
\tbus_ack <= cs;
end
endmodule
|
`timescale 1ns / 100ps
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_dbg_hwbrk.v
//
// *Module Description:
// Hardware Breakpoint / Watchpoint module
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module omsp_dbg_hwbrk (
// OUTPUTs
brk_halt, // Hardware breakpoint command
brk_pnd, // Hardware break/watch-point pending
brk_dout, // Hardware break/watch-point register data input
// INPUTs
brk_reg_rd, // Hardware break/watch-point register read select
brk_reg_wr, // Hardware break/watch-point register write select
dbg_clk, // Debug unit clock
dbg_din, // Debug register data input
dbg_rst, // Debug unit reset
decode_noirq, // Frontend decode instruction
eu_mab, // Execution-Unit Memory address bus
eu_mb_en, // Execution-Unit Memory bus enable
eu_mb_wr, // Execution-Unit Memory bus write transfer
pc // Program counter
);
// OUTPUTs
//=========
output brk_halt; // Hardware breakpoint command
output brk_pnd; // Hardware break/watch-point pending
output [15:0] brk_dout; // Hardware break/watch-point register data input
// INPUTs
//=========
input [3:0] brk_reg_rd; // Hardware break/watch-point register read select
input [3:0] brk_reg_wr; // Hardware break/watch-point register write select
input dbg_clk; // Debug unit clock
input [15:0] dbg_din; // Debug register data input
input dbg_rst; // Debug unit reset
input decode_noirq; // Frontend decode instruction
input [15:0] eu_mab; // Execution-Unit Memory address bus
input eu_mb_en; // Execution-Unit Memory bus enable
input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer
input [15:0] pc; // Program counter
//=============================================================================
// 1) WIRE & PARAMETER DECLARATION
//=============================================================================
wire range_wr_set;
wire range_rd_set;
wire addr1_wr_set;
wire addr1_rd_set;
wire addr0_wr_set;
wire addr0_rd_set;
parameter BRK_CTL = 0,
BRK_STAT = 1,
BRK_ADDR0 = 2,
BRK_ADDR1 = 3;
//=============================================================================
// 2) CONFIGURATION REGISTERS
//=============================================================================
// BRK_CTL Register
//-----------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// Reserved RANGE_MODE INST_EN BREAK_EN ACCESS_MODE
//
// ACCESS_MODE: - 00 : Disabled
// - 01 : Detect read access
// - 10 : Detect write access
// - 11 : Detect read/write access
// NOTE: \'10\' & \'11\' modes are not supported on the instruction flow
//
// BREAK_EN: - 0 : Watchmode enable
// - 1 : Break enable
//
// INST_EN: - 0 : Checks are done on the execution unit (data flow)
// - 1 : Checks are done on the frontend (instruction flow)
//
// RANGE_MODE: - 0 : Address match on BRK_ADDR0 or BRK_ADDR1
// - 1 : Address match on BRK_ADDR0->BRK_ADDR1 range
//
//-----------------------------------------------------------------------------
reg [4:0] brk_ctl;
wire brk_ctl_wr = brk_reg_wr[BRK_CTL];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) brk_ctl <= 5\'h00;
else if (brk_ctl_wr) brk_ctl <= {`HWBRK_RANGE & dbg_din[4], dbg_din[3:0]};
wire [7:0] brk_ctl_full = {3\'b000, brk_ctl};
// BRK_STAT Register
//-----------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// Reserved RANGE_WR RANGE_RD ADDR1_WR ADDR1_RD ADDR0_WR ADDR0_RD
//-----------------------------------------------------------------------------
reg [5:0] brk_stat;
wire brk_stat_wr = brk_reg_wr[BRK_STAT];
wire [5:0] brk_stat_set = {range_wr_set & `HWBRK_RANGE,
range_rd_set & `HWBRK_RANGE,
\t\t\t addr1_wr_set, addr1_rd_set,
\t\t\t addr0_wr_set, addr0_rd_set};
wire [5:0] brk_stat_clr = ~dbg_din[5:0];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) brk_stat <= 6\'h00;
else if (brk_stat_wr) brk_stat <= ((brk_stat & brk_stat_clr) | brk_stat_set);
else brk_stat <= (brk_stat | brk_stat_set);
wire [7:0] brk_stat_full = {2\'b00, brk_stat};
wire brk_pnd = |brk_stat;
// BRK_ADDR0 Register
//-----------------------------------------------------------------------------
reg [15:0] brk_addr0;
wire brk_addr0_wr = brk_reg_wr[BRK_ADDR0];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) brk_addr0 <= 16\'h0000;
else if (brk_addr0_wr) brk_addr0 <= dbg_din;
// BRK_ADDR1/DATA0 Register
//-----------------------------------------------------------------------------
reg [15:0] brk_addr1;
wire brk_addr1_wr = brk_reg_wr[BRK_ADDR1];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) brk_addr1 <= 16\'h0000;
else if (brk_addr1_wr) brk_addr1 <= dbg_din;
//============================================================================
// 3) DATA OUTPUT GENERATION
//============================================================================
wire [15:0] brk_ctl_rd = {8\'h00, brk_ctl_full} & {16{brk_reg_rd[BRK_CTL]}};
wire [15:0] brk_stat_rd = {8\'h00, brk_stat_full} & {16{brk_reg_rd[BRK_STAT]}};
wire [15:0] brk_addr0_rd = brk_addr0 & {16{brk_reg_rd[BRK_ADDR0]}};
wire [15:0] brk_addr1_rd = brk_addr1 & {16{brk_reg_rd[BRK_ADDR1]}};
wire [15:0] brk_dout = brk_ctl_rd |
brk_stat_rd |
brk_addr0_rd |
brk_addr1_rd;
//============================================================================
// 4) BREAKPOINT / WATCHPOINT GENERATION
//============================================================================
// Comparators
//---------------------------
// Note: here the comparison logic is instanciated several times in order
// to improve the timings, at the cost of a bit more area.
wire equ_d_addr0 = eu_mb_en & (eu_mab==brk_addr0) & ~brk_ctl[`BRK_RANGE];
wire equ_d_addr1 = eu_mb_en & (eu_mab==brk_addr1) & ~brk_ctl[`BRK_RANGE];
wire equ_d_range = eu_mb_en & ((eu_mab>=brk_addr0) & (eu_mab<=brk_addr1)) &
brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
wire equ_i_addr0 = decode_noirq & (pc==brk_addr0) & ~brk_ctl[`BRK_RANGE];
wire equ_i_addr1 = decode_noirq & (pc==brk_addr1) & ~brk_ctl[`BRK_RANGE];
wire equ_i_range = decode_noirq & ((pc>=brk_addr0) & (pc<=brk_addr1)) &
brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
// Detect accesses
//---------------------------
// Detect Instruction read access
wire i_addr0_rd = equ_i_addr0 & brk_ctl[`BRK_I_EN];
wire i_addr1_rd = equ_i_addr1 & brk_ctl[`BRK_I_EN];
wire i_range_rd = equ_i_range & brk_ctl[`BRK_I_EN];
// Detect Execution-Unit write access
wire d_addr0_wr = equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
wire d_addr1_wr = equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
wire d_range_wr = equ_d_range & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
// Detect DATA read access
wire d_addr0_rd = equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr;
wire d_addr1_rd = equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr;
wire d_range_rd = equ_d_range & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr;
// Set flags
assign addr0_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr0_rd | i_addr0_rd);
assign addr0_wr_set = brk_ctl[`BRK_MODE_WR] & d_addr0_wr;
assign addr1_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr1_rd | i_addr1_rd);
assign addr1_wr_set = brk_ctl[`BRK_MODE_WR] & d_addr1_wr;
assign range_rd_set = brk_ctl[`BRK_MODE_RD] & (d_range_rd | i_range_rd);
assign range_wr_set = brk_ctl[`BRK_MODE_WR] & d_range_wr;
// Break CPU
assign brk_halt = brk_ctl[`BRK_EN] & |brk_stat_set;
endmodule // omsp_dbg_hwbrk
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: dbg_uart_tasks.v
//
// *Module Description:
// openMSP430 debug interface UART tasks
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
// Register B/W and addresses
parameter CPU_ID_LO = (8'h00 | 8'h00);
parameter CPU_ID_HI = (8'h00 | 8'h01);
parameter CPU_CTL = (8'h40 | 8'h02);
parameter CPU_STAT = (8'h40 | 8'h03);
parameter MEM_CTL = (8'h40 | 8'h04);
parameter MEM_ADDR = (8'h00 | 8'h05);
parameter MEM_DATA = (8'h00 | 8'h06);
parameter MEM_CNT = (8'h00 | 8'h07);
parameter BRK0_CTL = (8'h40 | 8'h08);
parameter BRK0_STAT = (8'h40 | 8'h09);
parameter BRK0_ADDR0 = (8'h00 | 8'h0A);
parameter BRK0_ADDR1 = (8'h00 | 8'h0B);
parameter BRK1_CTL = (8'h40 | 8'h0C);
parameter BRK1_STAT = (8'h40 | 8'h0D);
parameter BRK1_ADDR0 = (8'h00 | 8'h0E);
parameter BRK1_ADDR1 = (8'h00 | 8'h0F);
parameter BRK2_CTL = (8'h40 | 8'h10);
parameter BRK2_STAT = (8'h40 | 8'h11);
parameter BRK2_ADDR0 = (8'h00 | 8'h12);
parameter BRK2_ADDR1 = (8'h00 | 8'h13);
parameter BRK3_CTL = (8'h40 | 8'h14);
parameter BRK3_STAT = (8'h40 | 8'h15);
parameter BRK3_ADDR0 = (8'h00 | 8'h16);
parameter BRK3_ADDR1 = (8'h00 | 8'h17);
parameter CPU_NR = (8'h00 | 8'h18);
// Read / Write commands
parameter DBG_WR = 8'h80;
parameter DBG_RD = 8'h00;
// Synchronization value
parameter DBG_SYNC = 8'h80;
//----------------------------------------------------------------------------
// UART COMMUNICATION DATA RATE CONFIGURATION
//----------------------------------------------------------------------------
// If the auto synchronization mode is set, then the communication speed
// is configured by the testbench.
// If not, the values from the openMSP430.inc file are taken over.
`ifdef DBG_UART_AUTO_SYNC
parameter UART_BAUD = 4000000;
integer UART_PERIOD = 1000000000/UART_BAUD;
`else
integer UART_PERIOD = `DBG_UART_CNT;
`endif
//----------------------------------------------------------------------------
// Receive UART frame from CPU Debug interface (8N1)
//----------------------------------------------------------------------------
task dbg_uart_rx;
output [7:0] dbg_rxbuf;
reg [7:0] \tdbg_rxbuf;
reg [7:0] \trxbuf;
integer \trxcnt;
begin
#(1);
dbg_uart_rx_busy = 1'b1;
@(negedge dbg_uart_txd);
dbg_rxbuf = 0;
rxbuf = 0;
#(3*UART_PERIOD/2);
for (rxcnt = 0; rxcnt < 8; rxcnt = rxcnt + 1)
\tbegin
\t rxbuf = {dbg_uart_txd, rxbuf[7:1]};
\t #(UART_PERIOD);
\tend
dbg_rxbuf = rxbuf;
dbg_uart_rx_busy = 1'b0;
end
endtask
task dbg_uart_rx16;
reg [7:0] rxbuf_lo;
reg [7:0] rxbuf_hi;
begin
rxbuf_lo = 8'h00;
rxbuf_hi = 8'h00;
dbg_uart_rx(rxbuf_lo);
dbg_uart_rx(rxbuf_hi);
dbg_uart_buf = {rxbuf_hi, rxbuf_lo};
end
endtask
task dbg_uart_rx8;
reg [7:0] rxbuf;
begin
rxbuf = 8'h00;
dbg_uart_rx(rxbuf);
dbg_uart_buf = {8'h00, rxbuf};
end
endtask
//----------------------------------------------------------------------------
// Transmit UART frame to CPU Debug interface (8N1)
//----------------------------------------------------------------------------
task dbg_uart_tx;
input [7:0] txbuf;
reg [9:0] \ttxbuf_full;
integer \ttxcnt;
begin
#(1);
dbg_uart_tx_busy = 1'b1;
dbg_uart_rxd_pre = 1'b1;
txbuf_full = {1'b1, txbuf, 1'b0};
for (txcnt = 0; txcnt < 10; txcnt = txcnt + 1)
\tbegin
\t #(UART_PERIOD);
\t dbg_uart_rxd_pre = txbuf_full[txcnt];
\tend
dbg_uart_tx_busy = 1'b0;
end
endtask
task dbg_uart_tx16;
input [15:0] txbuf;
begin
dbg_uart_tx(txbuf[7:0]);
dbg_uart_tx(txbuf[15:8]);
end
endtask
always @(posedge mclk or posedge dbg_rst)
if (dbg_rst)
begin
dbg_uart_rxd_sel <= 1'b0;
dbg_uart_rxd_dly <= 1'b1;
end
else if (dbg_en)
begin
dbg_uart_rxd_sel <= dbg_uart_rxd_meta ? $random : 1'b0;
dbg_uart_rxd_dly <= dbg_uart_rxd_pre;
end
assign dbg_uart_rxd = dbg_uart_rxd_sel ? dbg_uart_rxd_dly : dbg_uart_rxd_pre;
//----------------------------------------------------------------------------
// Write to Debug register
//----------------------------------------------------------------------------
task dbg_uart_wr;
input [7:0] dbg_reg;
input [15:0] dbg_data;
begin
dbg_uart_tx(DBG_WR | dbg_reg);
dbg_uart_tx(dbg_data[7:0]);
if (~dbg_reg[6])
\tdbg_uart_tx(dbg_data[15:8]);
end
endtask
//----------------------------------------------------------------------------
// Read Debug register
//----------------------------------------------------------------------------
task dbg_uart_rd;
input [7:0] dbg_reg;
reg [7:0] \trxbuf_lo;
reg [7:0] \trxbuf_hi;
begin
rxbuf_lo = 8'h00;
rxbuf_hi = 8'h00;
dbg_uart_tx(DBG_RD | dbg_reg);
dbg_uart_rx(rxbuf_lo);
if (~dbg_reg[6])
\tdbg_uart_rx(rxbuf_hi);
dbg_uart_buf = {rxbuf_hi, rxbuf_lo};
end
endtask
//----------------------------------------------------------------------------
// Send synchronization frame
//----------------------------------------------------------------------------
task dbg_uart_sync;
begin
dbg_uart_tx(DBG_SYNC);
repeat(10) @(posedge mclk);
end
endtask
|
`timescale 1 ns / 1 ps
//`define DEBUG
module system_tb;
integer i;\t
\treg clk = 1;
\talways #5 clk = ~clk;
\treg resetn = 0;
\tinitial begin
\t\tif ($test$plusargs("vcd")) begin
\t\t\t$dumpfile("system.vcd");
\t\t $dumpvars(0, system_tb);
for (i = 0; i < 32; i = i + 1) begin
\t\t $dumpvars(0,system_tb.uut.picorv32_core.cpuregs[i]);
\t\t\tend \t\t
\t\tend
\t\trepeat (100) @(posedge clk);
\t\tresetn <= 1;
\tend
\twire trap;
\twire [7:0] out_byte;
\twire out_byte_en;
\tsystem uut (
\t\t.clk (clk ),
\t\t.resetn (resetn ),
\t\t.trap (trap ),
.out_byte (out_byte ),
\t\t.out_byte_en(out_byte_en)
\t);
\talways @(posedge clk) begin
\t\tif (resetn && trap) begin
\t\t\t$finish;
\t\tend
\tend
endmodule
|
module spi #(
\tparameter integer CLOCK_FREQ_HZ = 0,
\tparameter integer CS_LENGTH = 32
) (
\tinput clk,
\tinput resetn,
\tinput ctrl_wr,
\tinput ctrl_rd,
\tinput [ 7:0] ctrl_addr,
\tinput [31:0] ctrl_wdat,
\toutput reg [31:0] ctrl_rdat,
\toutput reg ctrl_done,
\toutput [CS_LENGTH-1:0] cs,
output mosi,
input miso,
output sclk
);
\twire spi_miso;
\treg spi_mosi, spi_sclk;
\treg [CS_LENGTH-1:0] spi_cs;
\treg mode_cpol;
\treg mode_cpha;
\treg [7:0] prescale_cnt;
\treg [7:0] prescale_cfg;
\treg [7:0] spi_data;
\treg [4:0] spi_state;
assign sclk = spi_sclk ^ ~mode_cpol;
assign cs = spi_cs;
assign spi_miso = miso;
\t\t assign mosi = spi_mosi;
\talways @(posedge clk) begin
\t\tctrl_rdat <= 'bx;
\t\tctrl_done <= 0;
\t\tif (!resetn) begin
\t\t\tspi_mosi <= 0;
\t\t\tspi_sclk <= 1;
\t\t\tspi_cs <= ~0;
\t\t\tmode_cpol <= 1;
\t\t\tmode_cpha <= 1;
\t\t\tprescale_cnt <= 0;
\t\t\tprescale_cfg <= 4;
\t\t\tspi_state <= 0;
\t\tend else
\t\tif (!ctrl_done) begin
\t\t\tif (ctrl_wr) begin
\t\t\t\tctrl_done <= 1;
\t\t\t\tif (ctrl_addr == 'h00) prescale_cfg <= ctrl_wdat;
\t\t\t\tif (ctrl_addr == 'h04) begin
\t\t\t\t\tspi_cs <= ctrl_wdat;
\t\t\t\t\tctrl_done <= prescale_cnt == prescale_cfg;
\t\t\t\t\tprescale_cnt <= prescale_cnt == prescale_cfg ? 0 : prescale_cnt + 1;
\t\t\t\tend
\t\t\t\tif (ctrl_addr == 'h08) begin
\t\t\t\t\tif (!prescale_cnt) begin
\t\t\t\t\t\tif (spi_state == 0) begin
\t\t\t\t\t\t\tspi_data <= ctrl_wdat;
\t\t\t\t\t\t\tspi_mosi <= ctrl_wdat[7];
\t\t\t\t\t\tend else begin
\t\t\t\t\t\t\tif (spi_state[0])
\t\t\t\t\t\t\t\tspi_data <= {spi_data, spi_miso};
\t\t\t\t\t\t\telse if (spi_state < 16)
\t\t\t\t\t\t\t\tspi_mosi <= spi_data[7];
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\t\tspi_sclk <= spi_state[0] ^ ~mode_cpha;
\t\t\t\t\tctrl_done <= spi_state == (mode_cpha ? 15 : 16) && prescale_cnt == prescale_cfg;
\t\t\t\t\tspi_state <= prescale_cnt == prescale_cfg ? (spi_state[4] ? 0 : spi_state + 1) : spi_state;
\t\t\t\t\tif (mode_cpha) spi_state[4] <= 0;
\t\t\t\t\tprescale_cnt <= prescale_cnt == prescale_cfg ? 0 : prescale_cnt + 1;
\t\t\t\tend
\t\t\t\tif (ctrl_addr == 'h0c) begin
\t\t\t\t\t{mode_cpol, mode_cpha} <= ctrl_wdat;
\t\t\t\t\tctrl_done <= prescale_cnt == prescale_cfg;
\t\t\t\t\tprescale_cnt <= prescale_cnt == prescale_cfg ? 0 : prescale_cnt + 1;
\t\t\t\tend
\t\t\tend
\t\t\tif (ctrl_rd) begin
\t\t\t\tctrl_done <= 1;
\t\t\t\tif (ctrl_addr == 'h00) ctrl_rdat <= prescale_cfg;
\t\t\t\tif (ctrl_addr == 'h04) ctrl_rdat <= spi_cs;
\t\t\t\tif (ctrl_addr == 'h08) ctrl_rdat <= spi_data;
\t\t\t\tif (ctrl_addr == 'h0c) ctrl_rdat <= {mode_cpol, mode_cpha};
\t\t\tend
\t\tend
\tend
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_sfr.v
//
// *Module Description:
// Processor Special function register
// Non-Maskable Interrupt generation
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module omsp_sfr (
// OUTPUTs
cpu_id, // CPU ID
nmi_pnd, // NMI Pending
nmi_wkup, // NMI Wakeup
per_dout, // Peripheral data output
wdtie, // Watchdog-timer interrupt enable
wdtifg_sw_clr, // Watchdog-timer interrupt flag software clear
wdtifg_sw_set, // Watchdog-timer interrupt flag software set
// INPUTs
cpu_nr_inst, // Current oMSP instance number
cpu_nr_total, // Total number of oMSP instances-1
mclk, // Main system clock
nmi, // Non-maskable interrupt (asynchronous)
nmi_acc, // Non-Maskable interrupt request accepted
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_we, // Peripheral write enable (high active)
puc_rst, // Main system reset
scan_mode, // Scan mode
wdtifg, // Watchdog-timer interrupt flag
wdtnmies // Watchdog-timer NMI edge selection
);
// OUTPUTs
//=========
output [31:0] cpu_id; // CPU ID
output nmi_pnd; // NMI Pending
output nmi_wkup; // NMI Wakeup
output [15:0] per_dout; // Peripheral data output
output wdtie; // Watchdog-timer interrupt enable
output wdtifg_sw_clr;// Watchdog-timer interrupt flag software clear
output wdtifg_sw_set;// Watchdog-timer interrupt flag software set
// INPUTs
//=========
input [7:0] cpu_nr_inst; // Current oMSP instance number
input [7:0] cpu_nr_total; // Total number of oMSP instances-1
input mclk; // Main system clock
input nmi; // Non-maskable interrupt (asynchronous)
input nmi_acc; // Non-Maskable interrupt request accepted
input [13:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input puc_rst; // Main system reset
input scan_mode; // Scan mode
input wdtifg; // Watchdog-timer interrupt flag
input wdtnmies; // Watchdog-timer NMI edge selection
//=============================================================================
// 1) PARAMETER DECLARATION
//=============================================================================
// Register base address (must be aligned to decoder bit width)
parameter [14:0] BASE_ADDR = 15\'h0000;
// Decoder bit width (defines how many bits are considered for address decoding)
parameter DEC_WD = 4;
// Register addresses offset
parameter [DEC_WD-1:0] IE1 = \'h0,
IFG1 = \'h2,
CPU_ID_LO = \'h4,
CPU_ID_HI = \'h6,
CPU_NR = \'h8;
// Register one-hot decoder utilities
parameter DEC_SZ = (1 << DEC_WD);
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1\'b0}}, 1\'b1};
// Register one-hot decoder
parameter [DEC_SZ-1:0] IE1_D = (BASE_REG << IE1),
IFG1_D = (BASE_REG << IFG1),
CPU_ID_LO_D = (BASE_REG << CPU_ID_LO),
CPU_ID_HI_D = (BASE_REG << CPU_ID_HI),
CPU_NR_D = (BASE_REG << CPU_NR);
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Local register selection
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
// Register local address
wire [DEC_WD-1:0] reg_addr = {1\'b0, per_addr[DEC_WD-2:0]};
// Register address decode
wire [DEC_SZ-1:0] reg_dec = (IE1_D & {DEC_SZ{(reg_addr==(IE1 >>1))}}) |
(IFG1_D & {DEC_SZ{(reg_addr==(IFG1 >>1))}}) |
(CPU_ID_LO_D & {DEC_SZ{(reg_addr==(CPU_ID_LO >>1))}}) |
(CPU_ID_HI_D & {DEC_SZ{(reg_addr==(CPU_ID_HI >>1))}}) |
(CPU_NR_D & {DEC_SZ{(reg_addr==(CPU_NR >>1))}});
// Read/Write probes
wire reg_lo_write = per_we[0] & reg_sel;
wire reg_hi_write = per_we[1] & reg_sel;
wire reg_read = ~|per_we & reg_sel;
// Read/Write vectors
wire [DEC_SZ-1:0] reg_hi_wr = reg_dec & {DEC_SZ{reg_hi_write}};
wire [DEC_SZ-1:0] reg_lo_wr = reg_dec & {DEC_SZ{reg_lo_write}};
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
//============================================================================
// 3) REGISTERS
//============================================================================
// IE1 Register
//--------------
wire [7:0] ie1;
wire ie1_wr = IE1[0] ? reg_hi_wr[IE1] : reg_lo_wr[IE1];
wire [7:0] ie1_nxt = IE1[0] ? per_din[15:8] : per_din[7:0];
`ifdef NMI
reg nmie;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) nmie <= 1\'b0;
else if (nmi_acc) nmie <= 1\'b0;
else if (ie1_wr) nmie <= ie1_nxt[4];
`else
wire nmie = 1\'b0;
`endif
`ifdef WATCHDOG
reg wdtie;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) wdtie <= 1\'b0;
else if (ie1_wr) wdtie <= ie1_nxt[0];
`else
wire wdtie = 1\'b0;
`endif
assign ie1 = {3\'b000, nmie, 3\'b000, wdtie};
// IFG1 Register
//---------------
wire [7:0] ifg1;
wire ifg1_wr = IFG1[0] ? reg_hi_wr[IFG1] : reg_lo_wr[IFG1];
wire [7:0] ifg1_nxt = IFG1[0] ? per_din[15:8] : per_din[7:0];
`ifdef NMI
reg nmiifg;
wire nmi_edge;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) nmiifg <= 1\'b0;
else if (nmi_edge) nmiifg <= 1\'b1;
else if (ifg1_wr) nmiifg <= ifg1_nxt[4];
`else
wire nmiifg = 1\'b0;
`endif
`ifdef WATCHDOG
assign wdtifg_sw_clr = ifg1_wr & ~ifg1_nxt[0];
assign wdtifg_sw_set = ifg1_wr & ifg1_nxt[0];
`else
assign wdtifg_sw_clr = 1\'b0;
assign wdtifg_sw_set = 1\'b0;
`endif
assign ifg1 = {3\'b000, nmiifg, 3\'b000, wdtifg};
// CPU_ID Register (READ ONLY)
//-----------------------------
// -------------------------------------------------------------------
// CPU_ID_LO: | 15 14 13 12 11 10 9 | 8 7 6 5 4 | 3 | 2 1 0 |
// |----------------------------+-----------------+------+-------------|
// | PER_SPACE | USER_VERSION | ASIC | CPU_VERSION |
// --------------------------------------------------------------------
// CPU_ID_HI: | 15 14 13 12 11 10 | 9 8 7 6 5 4 3 2 1 | 0 |
// |----------------------------+-------------------------------+------|
// | PMEM_SIZE | DMEM_SIZE | MPY |
// -------------------------------------------------------------------
wire [2:0] cpu_version = `CPU_VERSION;
`ifdef ASIC
wire cpu_asic = 1\'b1;
`else
wire cpu_asic = 1\'b0;
`endif
wire [4:0] user_version = `USER_VERSION;
wire [6:0] per_space = (`PER_SIZE >> 9); // cpu_id_per * 512 = peripheral space size
`ifdef MULTIPLIER
wire mpy_info = 1\'b1;
`else
wire mpy_info = 1\'b0;
`endif
wire [8:0] dmem_size = (`DMEM_SIZE >> 7); // cpu_id_dmem * 128 = data memory size
wire [5:0] pmem_size = (`PMEM_SIZE >> 10); // cpu_id_pmem * 1024 = program memory size
assign cpu_id = {pmem_size,
dmem_size,
mpy_info,
per_space,
user_version,
cpu_asic,
cpu_version};
// CPU_NR Register (READ ONLY)
//-----------------------------
// -------------------------------------------------------------------
// | 15 14 13 12 11 10 9 8 | 7 6 5 4 3 2 1 0 |
// |---------------------------------+---------------------------------|
// | CPU_TOTAL_NR | CPU_INST_NR |
// -------------------------------------------------------------------
wire [15:0] cpu_nr = {cpu_nr_total, cpu_nr_inst};
//============================================================================
// 4) DATA OUTPUT GENERATION
//============================================================================
// Data output mux
wire [15:0] ie1_rd = {8\'h00, (ie1 & {8{reg_rd[IE1]}})} << (8 & {4{IE1[0]}});
wire [15:0] ifg1_rd = {8\'h00, (ifg1 & {8{reg_rd[IFG1]}})} << (8 & {4{IFG1[0]}});
wire [15:0] cpu_id_lo_rd = cpu_id[15:0] & {16{reg_rd[CPU_ID_LO]}};
wire [15:0] cpu_id_hi_rd = cpu_id[31:16] & {16{reg_rd[CPU_ID_HI]}};
wire [15:0] cpu_nr_rd = cpu_nr & {16{reg_rd[CPU_NR]}};
wire [15:0] per_dout = ie1_rd |
ifg1_rd |
cpu_id_lo_rd |
cpu_id_hi_rd |
cpu_nr_rd;
//=============================================================================
// 5) NMI GENERATION
//=============================================================================
// NOTE THAT THE NMI INPUT IS ASSUMED TO BE NON-GLITCHY
`ifdef NMI
//-----------------------------------
// Edge selection
//-----------------------------------
wire nmi_pol = nmi ^ wdtnmies;
//-----------------------------------
// Pulse capture and synchronization
//-----------------------------------
`ifdef SYNC_NMI
`ifdef ASIC_CLOCKING
// Glitch free reset for the event capture
reg nmi_capture_rst;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) nmi_capture_rst <= 1\'b1;
else nmi_capture_rst <= ifg1_wr & ~ifg1_nxt[4];
// NMI event capture
wire nmi_capture;
omsp_wakeup_cell wakeup_cell_nmi (
.wkup_out (nmi_capture), // Wakup signal (asynchronous)
.scan_clk (mclk), // Scan clock
.scan_mode (scan_mode), // Scan mode
.scan_rst (puc_rst), // Scan reset
.wkup_clear (nmi_capture_rst), // Glitch free wakeup event clear
.wkup_event (nmi_pol) // Glitch free asynchronous wakeup event
);
`else
wire UNUSED_scan_mode = scan_mode;
wire nmi_capture = nmi_pol;
`endif
// Synchronization
wire nmi_s;
omsp_sync_cell sync_cell_nmi (
.data_out (nmi_s),
.data_in (nmi_capture),
.clk (mclk),
.rst (puc_rst)
);
`else
wire UNUSED_scan_mode = scan_mode;
wire nmi_capture = nmi_pol;
wire nmi_s = nmi_pol;
`endif
//-----------------------------------
// NMI Pending flag
//-----------------------------------
// Delay
reg nmi_dly;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) nmi_dly <= 1\'b0;
else nmi_dly <= nmi_s;
// Edge detection
assign nmi_edge = ~nmi_dly & nmi_s;
// NMI pending
wire nmi_pnd = nmiifg & nmie;
// NMI wakeup
`ifdef ASIC_CLOCKING
wire nmi_wkup;
omsp_and_gate and_nmi_wkup (.y(nmi_wkup), .a(nmi_capture ^ nmi_dly), .b(nmie));
`else
wire nmi_wkup = 1\'b0;
`endif
`else
wire nmi_pnd = 1\'b0;
wire nmi_wkup = 1\'b0;
wire UNUSED_scan_mode = scan_mode;
wire UNUSED_nmi = nmi;
wire UNUSED_nmi_acc = nmi_acc;
wire UNUSED_wdtnmies = wdtnmies;
`endif
// LINT cleanup
wire [7:0] UNUSED_per_din_15_8 = per_din[15:8];
endmodule // omsp_sfr
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_scan_mux.v
//
// *Module Description:
// Generic mux for scan mode
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
module omsp_scan_mux (
// OUTPUTs
data_out, // Scan mux data output
// INPUTs
data_in_scan, // Selected data input for scan mode
data_in_func, // Selected data input for functional mode
scan_mode // Scan mode
);
// OUTPUTs
//=========
output data_out; // Scan mux data output
// INPUTs
//=========
input data_in_scan; // Selected data input for scan mode
input data_in_func; // Selected data input for functional mode
input scan_mode; // Scan mode
//=============================================================================
// 1) SCAN MUX
//=============================================================================
assign data_out = scan_mode ? data_in_scan : data_in_func;
endmodule // omsp_scan_mux
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_clock_gate.v
//
// *Module Description:
// Generic clock gate cell for the openMSP430
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
module omsp_clock_gate (
// OUTPUTs
gclk, // Gated clock
// INPUTs
clk, // Clock
enable, // Clock enable
scan_enable // Scan enable (active during scan shifting)
);
// OUTPUTs
//=========
output gclk; // Gated clock
// INPUTs
//=========
input clk; // Clock
input enable; // Clock enable
input scan_enable; // Scan enable (active during scan shifting)
//=============================================================================
// CLOCK GATE: LATCH + AND
//=============================================================================
// Enable clock gate during scan shift
// (the gate itself is checked with the scan capture cycle)
wire enable_in = (enable | scan_enable);
// LATCH the enable signal
reg enable_latch;
always @(clk or enable_in)
if (~clk)
enable_latch <= enable_in;
// AND gate
assign gclk = (clk & enable_latch);
endmodule // omsp_clock_gate
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_uart.v
//
// *Module Description:
// uart peripheral
//
// *Author(s):
// - Windel Bouwman
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
module omsp_uart (
// OUTPUTs
per_dout, // Peripheral data output
// INPUTs
mclk, // Main system clock
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_we, // Peripheral write enable (high active)
puc_rst // Main system reset
);
// OUTPUTs
//=========
output [15:0] per_dout; // Peripheral data output
// INPUTs
//=========
input mclk; // Main system clock
input [13:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input puc_rst; // Main system reset
//=============================================================================
// 1) PARAMETER DECLARATION
//=============================================================================
// Register base address (must be aligned to decoder bit width)
parameter [14:0] BASE_ADDR = 15\'h0060;
// Decoder bit width (defines how many bits are considered for address decoding)
parameter DEC_WD = 3;
// Register addresses offset
parameter [DEC_WD-1:0] CNTRL1 = \'h0,
CNTRL2 = \'h1,
CNTRL3 = \'h2,
TXBUF = \'h7;
// Register one-hot decoder utilities
parameter DEC_SZ = (1 << DEC_WD);
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1\'b0}}, 1\'b1};
// Register one-hot decoder
parameter [DEC_SZ-1:0] CNTRL1_D = (BASE_REG << CNTRL1),
CNTRL2_D = (BASE_REG << CNTRL2),
CNTRL3_D = (BASE_REG << CNTRL3),
TXBUF_D = (BASE_REG << TXBUF );
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Local register selection
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
// Register local address
wire [DEC_WD-1:0] reg_addr = {1\'b0, per_addr[DEC_WD-2:0]};
// Register address decode
wire [DEC_SZ-1:0] reg_dec = (CNTRL1_D & {DEC_SZ{(reg_addr==(CNTRL1 >>1))}}) |
(CNTRL2_D & {DEC_SZ{(reg_addr==(CNTRL2 >>1))}}) |
(CNTRL3_D & {DEC_SZ{(reg_addr==(CNTRL3 >>1))}}) |
(TXBUF_D & {DEC_SZ{(reg_addr==(TXBUF >>1))}});
// Read/Write probes
wire reg_lo_write = per_we[0] & reg_sel;
wire reg_hi_write = per_we[1] & reg_sel;
wire reg_read = ~|per_we & reg_sel;
// Read/Write vectors
wire [DEC_SZ-1:0] reg_hi_wr = reg_dec & {DEC_SZ{reg_hi_write}};
wire [DEC_SZ-1:0] reg_lo_wr = reg_dec & {DEC_SZ{reg_lo_write}};
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
//============================================================================
// 3) REGISTERS
//============================================================================
// CNTRL1 Register
//-----------------
reg [7:0] cntrl1;
wire cntrl1_wr = CNTRL1[0] ? reg_hi_wr[CNTRL1] : reg_lo_wr[CNTRL1];
wire [7:0] cntrl1_nxt = CNTRL1[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cntrl1 <= 8\'h00;
else if (cntrl1_wr) cntrl1 <= cntrl1_nxt;
// CNTRL2 Register
//-----------------
reg [7:0] cntrl2;
wire cntrl2_wr = CNTRL2[0] ? reg_hi_wr[CNTRL2] : reg_lo_wr[CNTRL2];
wire [7:0] cntrl2_nxt = CNTRL2[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cntrl2 <= 8\'h00;
else if (cntrl2_wr) cntrl2 <= cntrl2_nxt;
// CNTRL3 Register
//-----------------
reg [7:0] cntrl3;
wire cntrl3_wr = CNTRL3[0] ? reg_hi_wr[CNTRL3] : reg_lo_wr[CNTRL3];
wire [7:0] cntrl3_nxt = CNTRL3[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cntrl3 <= 8\'h00;
else if (cntrl3_wr) cntrl3 <= cntrl3_nxt;
// TXBUF Register
//-----------------
reg [7:0] cntrl4;
wire cntrl4_wr = TXBUF[0] ? reg_hi_wr[TXBUF] : reg_lo_wr[TXBUF];
wire [7:0] cntrl4_nxt = TXBUF[0] ? per_din[15:8] : per_din[7:0];
integer fileHandle;
initial begin
fileHandle = $fopen("output.txt", "w");
end
always @ (posedge mclk or posedge puc_rst)
if (puc_rst)
cntrl4 <= 8\'h00;
else if (cntrl4_wr)
begin
cntrl4 <= cntrl4_nxt;
if (cntrl4_nxt == 4)
begin
$display("EOT: %b", cntrl4_nxt);
$fclose(fileHandle);
$finish;
end
else
begin
$display("Write serial: %b, %c", cntrl4_nxt, cntrl4_nxt);
$fwrite(fileHandle, "%c", cntrl4_nxt);
end
end
//============================================================================
// 4) DATA OUTPUT GENERATION
//============================================================================
// Data output mux
wire [15:0] cntrl1_rd = {8\'h00, (cntrl1 & {8{reg_rd[CNTRL1]}})} << (8 & {4{CNTRL1[0]}});
wire [15:0] cntrl2_rd = {8\'h00, (cntrl2 & {8{reg_rd[CNTRL2]}})} << (8 & {4{CNTRL2[0]}});
wire [15:0] cntrl3_rd = {8\'h00, (cntrl3 & {8{reg_rd[CNTRL3]}})} << (8 & {4{CNTRL3[0]}});
wire [15:0] cntrl4_rd = {8\'h00, (cntrl4 & {8{reg_rd[TXBUF]}})} << (8 & {4{TXBUF[0]}});
wire [15:0] per_dout = cntrl1_rd |
cntrl2_rd |
cntrl3_rd |
cntrl4_rd;
endmodule
|
/*
* PicoRV32 -- A Small RISC-V (RV32I) Processor Core
*
* Copyright (C) 2015 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
`timescale 1 ns / 1 ps
// `default_nettype none
// `define DEBUGNETS
`define DEBUGREGS
// `define DEBUGASM
//`define DEBUG
`ifdef DEBUG
`define debug(debug_command) debug_command
`else
`define debug(debug_command)
`endif
`ifdef FORMAL
`define FORMAL_KEEP (* keep *)
`define assert(assert_expr) assert(assert_expr)
`else
`ifdef DEBUGNETS
`define FORMAL_KEEP (* keep *)
`else
`define FORMAL_KEEP
`endif
`define assert(assert_expr) empty_statement
`endif
// uncomment this for register file in extra module
// `define PICORV32_REGS picorv32_regs
// this macro can be used to check if the verilog files in your
// design are read in the correct order.
`define PICORV32_V
/***************************************************************
* picorv32
***************************************************************/
module picorv32 #(
\tparameter [ 0:0] ENABLE_COUNTERS = 1,
\tparameter [ 0:0] ENABLE_COUNTERS64 = 1,
\tparameter [ 0:0] ENABLE_REGS_16_31 = 1,
\tparameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
\tparameter [ 0:0] LATCHED_MEM_RDATA = 0,
\tparameter [ 0:0] TWO_STAGE_SHIFT = 1,
\tparameter [ 0:0] BARREL_SHIFTER = 0,
\tparameter [ 0:0] TWO_CYCLE_COMPARE = 0,
\tparameter [ 0:0] TWO_CYCLE_ALU = 0,
\tparameter [ 0:0] COMPRESSED_ISA = 1,
\tparameter [ 0:0] CATCH_MISALIGN = 1,
\tparameter [ 0:0] CATCH_ILLINSN = 1,
\tparameter [ 0:0] ENABLE_PCPI = 0,
\tparameter [ 0:0] ENABLE_MUL = 1,
\tparameter [ 0:0] ENABLE_FAST_MUL = 0,
\tparameter [ 0:0] ENABLE_DIV = 1,
\tparameter [ 0:0] ENABLE_IRQ = 1,
\tparameter [ 0:0] ENABLE_IRQ_QREGS = 1,
\tparameter [ 0:0] ENABLE_IRQ_TIMER = 1,
\tparameter [ 0:0] ENABLE_TRACE = 0,
\tparameter [ 0:0] REGS_INIT_ZERO = 0,
\tparameter [31:0] MASKED_IRQ = 32\'h 0000_0000,
\tparameter [31:0] LATCHED_IRQ = 32\'h ffff_fffe,
\tparameter [31:0] PROGADDR_RESET = 32\'h 0000_0000,
\tparameter [31:0] PROGADDR_IRQ = 32\'h 0000_0010,
\tparameter [31:0] STACKADDR = 32\'h ffff_ffff
) (
\tinput clk, resetn,
\toutput reg trap,
\toutput reg mem_valid,
\toutput reg mem_instr,
\tinput mem_ready,
\toutput reg [31:0] mem_addr,
\toutput reg [31:0] mem_wdata,
\toutput reg [ 3:0] mem_wstrb,
\tinput [31:0] mem_rdata,
\t// Look-Ahead Interface
\toutput mem_la_read,
\toutput mem_la_write,
\toutput [31:0] mem_la_addr,
\toutput reg [31:0] mem_la_wdata,
\toutput reg [ 3:0] mem_la_wstrb,
\t// Pico Co-Processor Interface (PCPI)
\toutput reg pcpi_valid,
\toutput reg [31:0] pcpi_insn,
\toutput [31:0] pcpi_rs1,
\toutput [31:0] pcpi_rs2,
\tinput pcpi_wr,
\tinput [31:0] pcpi_rd,
\tinput pcpi_wait,
\tinput pcpi_ready,
\t// IRQ Interface
\tinput [31:0] irq,
\toutput reg [31:0] eoi,
`ifdef RISCV_FORMAL
\toutput reg rvfi_valid,
\toutput reg [63:0] rvfi_order,
\toutput reg [31:0] rvfi_insn,
\toutput reg rvfi_trap,
\toutput reg rvfi_halt,
\toutput reg rvfi_intr,
\toutput reg [ 4:0] rvfi_rs1_addr,
\toutput reg [ 4:0] rvfi_rs2_addr,
\toutput reg [31:0] rvfi_rs1_rdata,
\toutput reg [31:0] rvfi_rs2_rdata,
\toutput reg [ 4:0] rvfi_rd_addr,
\toutput reg [31:0] rvfi_rd_wdata,
\toutput reg [31:0] rvfi_pc_rdata,
\toutput reg [31:0] rvfi_pc_wdata,
\toutput reg [31:0] rvfi_mem_addr,
\toutput reg [ 3:0] rvfi_mem_rmask,
\toutput reg [ 3:0] rvfi_mem_wmask,
\toutput reg [31:0] rvfi_mem_rdata,
\toutput reg [31:0] rvfi_mem_wdata,
`endif
\t// Trace Interface
\toutput reg trace_valid,
\toutput reg [35:0] trace_data
);
\tlocalparam integer irq_timer = 0;
\tlocalparam integer irq_ebreak = 1;
\tlocalparam integer irq_buserror = 2;
\tlocalparam integer irqregs_offset = ENABLE_REGS_16_31 ? 32 : 16;
\tlocalparam integer regfile_size = (ENABLE_REGS_16_31 ? 32 : 16) + 4*ENABLE_IRQ*ENABLE_IRQ_QREGS;
\tlocalparam integer regindex_bits = (ENABLE_REGS_16_31 ? 5 : 4) + ENABLE_IRQ*ENABLE_IRQ_QREGS;
\tlocalparam WITH_PCPI = ENABLE_PCPI || ENABLE_MUL || ENABLE_FAST_MUL || ENABLE_DIV;
\tlocalparam [35:0] TRACE_BRANCH = {4\'b 0001, 32\'b 0};
\tlocalparam [35:0] TRACE_ADDR = {4\'b 0010, 32\'b 0};
\tlocalparam [35:0] TRACE_IRQ = {4\'b 1000, 32\'b 0};
\treg [63:0] count_cycle, count_instr;
\treg [31:0] reg_pc, reg_next_pc, reg_op1, reg_op2, reg_out;
\treg [4:0] reg_sh;
\treg [31:0] next_insn_opcode;
\treg [31:0] dbg_insn_opcode;
\treg [31:0] dbg_insn_addr;
\twire dbg_mem_valid = mem_valid;
\twire dbg_mem_instr = mem_instr;
\twire dbg_mem_ready = mem_ready;
\twire [31:0] dbg_mem_addr = mem_addr;
\twire [31:0] dbg_mem_wdata = mem_wdata;
\twire [ 3:0] dbg_mem_wstrb = mem_wstrb;
\twire [31:0] dbg_mem_rdata = mem_rdata;
\tassign pcpi_rs1 = reg_op1;
\tassign pcpi_rs2 = reg_op2;
\twire [31:0] next_pc;
\treg irq_delay;
\treg irq_active;
\treg [31:0] irq_mask;
\treg [31:0] irq_pending;
\treg [31:0] timer;
`ifndef PICORV32_REGS
\treg [31:0] cpuregs [0:regfile_size-1];
\tinteger i;
\tinitial begin
\t\tif (REGS_INIT_ZERO) begin
\t\t\tfor (i = 0; i < regfile_size; i = i+1)
\t\t\t\tcpuregs[i] = 0;
\t\tend
\tend
`endif
\ttask empty_statement;
\t\t// This task is used by the `assert directive in non-formal mode to
\t\t// avoid empty statement (which are unsupported by plain Verilog syntax).
\t\tbegin end
\tendtask
`ifdef DEBUGREGS
\twire [31:0] dbg_reg_x0 = 0;
\twire [31:0] dbg_reg_x1 = cpuregs[1];
\twire [31:0] dbg_reg_x2 = cpuregs[2];
\twire [31:0] dbg_reg_x3 = cpuregs[3];
\twire [31:0] dbg_reg_x4 = cpuregs[4];
\twire [31:0] dbg_reg_x5 = cpuregs[5];
\twire [31:0] dbg_reg_x6 = cpuregs[6];
\twire [31:0] dbg_reg_x7 = cpuregs[7];
\twire [31:0] dbg_reg_x8 = cpuregs[8];
\twire [31:0] dbg_reg_x9 = cpuregs[9];
\twire [31:0] dbg_reg_x10 = cpuregs[10];
\twire [31:0] dbg_reg_x11 = cpuregs[11];
\twire [31:0] dbg_reg_x12 = cpuregs[12];
\twire [31:0] dbg_reg_x13 = cpuregs[13];
\twire [31:0] dbg_reg_x14 = cpuregs[14];
\twire [31:0] dbg_reg_x15 = cpuregs[15];
\twire [31:0] dbg_reg_x16 = cpuregs[16];
\twire [31:0] dbg_reg_x17 = cpuregs[17];
\twire [31:0] dbg_reg_x18 = cpuregs[18];
\twire [31:0] dbg_reg_x19 = cpuregs[19];
\twire [31:0] dbg_reg_x20 = cpuregs[20];
\twire [31:0] dbg_reg_x21 = cpuregs[21];
\twire [31:0] dbg_reg_x22 = cpuregs[22];
\twire [31:0] dbg_reg_x23 = cpuregs[23];
\twire [31:0] dbg_reg_x24 = cpuregs[24];
\twire [31:0] dbg_reg_x25 = cpuregs[25];
\twire [31:0] dbg_reg_x26 = cpuregs[26];
\twire [31:0] dbg_reg_x27 = cpuregs[27];
\twire [31:0] dbg_reg_x28 = cpuregs[28];
\twire [31:0] dbg_reg_x29 = cpuregs[29];
\twire [31:0] dbg_reg_x30 = cpuregs[30];
\twire [31:0] dbg_reg_x31 = cpuregs[31];
`endif
\t// Internal PCPI Cores
\twire pcpi_mul_wr;
\twire [31:0] pcpi_mul_rd;
\twire pcpi_mul_wait;
\twire pcpi_mul_ready;
\twire pcpi_div_wr;
\twire [31:0] pcpi_div_rd;
\twire pcpi_div_wait;
\twire pcpi_div_ready;
\treg pcpi_int_wr;
\treg [31:0] pcpi_int_rd;
\treg pcpi_int_wait;
\treg pcpi_int_ready;
\tgenerate if (ENABLE_FAST_MUL) begin
\t\tpicorv32_pcpi_fast_mul pcpi_mul (
\t\t\t.clk (clk ),
\t\t\t.resetn (resetn ),
\t\t\t.pcpi_valid(pcpi_valid ),
\t\t\t.pcpi_insn (pcpi_insn ),
\t\t\t.pcpi_rs1 (pcpi_rs1 ),
\t\t\t.pcpi_rs2 (pcpi_rs2 ),
\t\t\t.pcpi_wr (pcpi_mul_wr ),
\t\t\t.pcpi_rd (pcpi_mul_rd ),
\t\t\t.pcpi_wait (pcpi_mul_wait ),
\t\t\t.pcpi_ready(pcpi_mul_ready )
\t\t);
\tend else if (ENABLE_MUL) begin
\t\tpicorv32_pcpi_mul pcpi_mul (
\t\t\t.clk (clk ),
\t\t\t.resetn (resetn ),
\t\t\t.pcpi_valid(pcpi_valid ),
\t\t\t.pcpi_insn (pcpi_insn ),
\t\t\t.pcpi_rs1 (pcpi_rs1 ),
\t\t\t.pcpi_rs2 (pcpi_rs2 ),
\t\t\t.pcpi_wr (pcpi_mul_wr ),
\t\t\t.pcpi_rd (pcpi_mul_rd ),
\t\t\t.pcpi_wait (pcpi_mul_wait ),
\t\t\t.pcpi_ready(pcpi_mul_ready )
\t\t);
\tend else begin
\t\tassign pcpi_mul_wr = 0;
\t\tassign pcpi_mul_rd = 32\'bx;
\t\tassign pcpi_mul_wait = 0;
\t\tassign pcpi_mul_ready = 0;
\tend endgenerate
\tgenerate if (ENABLE_DIV) begin
\t\tpicorv32_pcpi_div pcpi_div (
\t\t\t.clk (clk ),
\t\t\t.resetn (resetn ),
\t\t\t.pcpi_valid(pcpi_valid ),
\t\t\t.pcpi_insn (pcpi_insn ),
\t\t\t.pcpi_rs1 (pcpi_rs1 ),
\t\t\t.pcpi_rs2 (pcpi_rs2 ),
\t\t\t.pcpi_wr (pcpi_div_wr ),
\t\t\t.pcpi_rd (pcpi_div_rd ),
\t\t\t.pcpi_wait (pcpi_div_wait ),
\t\t\t.pcpi_ready(pcpi_div_ready )
\t\t);
\tend else begin
\t\tassign pcpi_div_wr = 0;
\t\tassign pcpi_div_rd = 32\'bx;
\t\tassign pcpi_div_wait = 0;
\t\tassign pcpi_div_ready = 0;
\tend endgenerate
\talways @* begin
\t\tpcpi_int_wr = 0;
\t\tpcpi_int_rd = 32\'bx;
\t\tpcpi_int_wait = |{ENABLE_PCPI && pcpi_wait, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_wait, ENABLE_DIV && pcpi_div_wait};
\t\tpcpi_int_ready = |{ENABLE_PCPI && pcpi_ready, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready, ENABLE_DIV && pcpi_div_ready};
\t\t(* parallel_case *)
\t\tcase (1\'b1)
\t\t\tENABLE_PCPI && pcpi_ready: begin
\t\t\t\tpcpi_int_wr = ENABLE_PCPI ? pcpi_wr : 0;
\t\t\t\tpcpi_int_rd = ENABLE_PCPI ? pcpi_rd : 0;
\t\t\tend
\t\t\t(ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready: begin
\t\t\t\tpcpi_int_wr = pcpi_mul_wr;
\t\t\t\tpcpi_int_rd = pcpi_mul_rd;
\t\t\tend
\t\t\tENABLE_DIV && pcpi_div_ready: begin
\t\t\t\tpcpi_int_wr = pcpi_div_wr;
\t\t\t\tpcpi_int_rd = pcpi_div_rd;
\t\t\tend
\t\tendcase
\tend
\t// Memory Interface
\treg [1:0] mem_state;
\treg [1:0] mem_wordsize;
\treg [31:0] mem_rdata_word;
\treg [31:0] mem_rdata_q;
\treg mem_do_prefetch;
\treg mem_do_rinst;
\treg mem_do_rdata;
\treg mem_do_wdata;
\twire mem_xfer;
\treg mem_la_secondword, mem_la_firstword_reg, last_mem_valid;
\twire mem_la_firstword = COMPRESSED_ISA && (mem_do_prefetch || mem_do_rinst) && next_pc[1] && !mem_la_secondword;
\twire mem_la_firstword_xfer = COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg);
\treg prefetched_high_word;
\treg clear_prefetched_high_word;
\treg [15:0] mem_16bit_buffer;
\twire [31:0] mem_rdata_latched_noshuffle;
\twire [31:0] mem_rdata_latched;
\twire mem_la_use_prefetched_high_word = COMPRESSED_ISA && mem_la_firstword && prefetched_high_word && !clear_prefetched_high_word;
\tassign mem_xfer = (mem_valid && mem_ready) || (mem_la_use_prefetched_high_word && mem_do_rinst);
\twire mem_busy = |{mem_do_prefetch, mem_do_rinst, mem_do_rdata, mem_do_wdata};
\twire mem_done = resetn && ((mem_xfer && |mem_state && (mem_do_rinst || mem_do_rdata || mem_do_wdata)) || (&mem_state && mem_do_rinst)) &&
\t\t\t(!mem_la_firstword || (~&mem_rdata_latched[1:0] && mem_xfer));
\tassign mem_la_write = resetn && !mem_state && mem_do_wdata;
\tassign mem_la_read = resetn && ((!mem_la_use_prefetched_high_word && !mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata)) ||
\t\t\t(COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg) && !mem_la_secondword && &mem_rdata_latched[1:0]));
\tassign mem_la_addr = (mem_do_prefetch || mem_do_rinst) ? {next_pc[31:2] + mem_la_firstword_xfer, 2\'b00} : {reg_op1[31:2], 2\'b00};
\tassign mem_rdata_latched_noshuffle = (mem_xfer || LATCHED_MEM_RDATA) ? mem_rdata : mem_rdata_q;
\tassign mem_rdata_latched = COMPRESSED_ISA && mem_la_use_prefetched_high_word ? {16\'bx, mem_16bit_buffer} :
\t\t\tCOMPRESSED_ISA && mem_la_secondword ? {mem_rdata_latched_noshuffle[15:0], mem_16bit_buffer} :
\t\t\tCOMPRESSED_ISA && mem_la_firstword ? {16\'bx, mem_rdata_latched_noshuffle[31:16]} : mem_rdata_latched_noshuffle;
\talways @(posedge clk) begin
\t\tif (!resetn) begin
\t\t\tmem_la_firstword_reg <= 0;
\t\t\tlast_mem_valid <= 0;
\t\tend else begin
\t\t\tif (!last_mem_valid)
\t\t\t\tmem_la_firstword_reg <= mem_la_firstword;
\t\t\tlast_mem_valid <= mem_valid && !mem_ready;
\t\tend
\tend
\talways @* begin
\t\t(* full_case *)
\t\tcase (mem_wordsize)
\t\t\t0: begin
\t\t\t\tmem_la_wdata = reg_op2;
\t\t\t\tmem_la_wstrb = 4\'b1111;
\t\t\t\tmem_rdata_word = mem_rdata;
\t\t\tend
\t\t\t1: begin
\t\t\t\tmem_la_wdata = {2{reg_op2[15:0]}};
\t\t\t\tmem_la_wstrb = reg_op1[1] ? 4\'b1100 : 4\'b0011;
\t\t\t\tcase (reg_op1[1])
\t\t\t\t\t1\'b0: mem_rdata_word = {16\'b0, mem_rdata[15: 0]};
\t\t\t\t\t1\'b1: mem_rdata_word = {16\'b0, mem_rdata[31:16]};
\t\t\t\tendcase
\t\t\tend
\t\t\t2: begin
\t\t\t\tmem_la_wdata = {4{reg_op2[7:0]}};
\t\t\t\tmem_la_wstrb = 4\'b0001 << reg_op1[1:0];
\t\t\t\tcase (reg_op1[1:0])
\t\t\t\t\t2\'b00: mem_rdata_word = {24\'b0, mem_rdata[ 7: 0]};
\t\t\t\t\t2\'b01: mem_rdata_word = {24\'b0, mem_rdata[15: 8]};
\t\t\t\t\t2\'b10: mem_rdata_word = {24\'b0, mem_rdata[23:16]};
\t\t\t\t\t2\'b11: mem_rdata_word = {24\'b0, mem_rdata[31:24]};
\t\t\t\tendcase
\t\t\tend
\t\tendcase
\tend
\talways @(posedge clk) begin
\t\tif (mem_xfer) begin
\t\t\tmem_rdata_q <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
\t\t\tnext_insn_opcode <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
\t\tend
\t\tif (COMPRESSED_ISA && mem_done && (mem_do_prefetch || mem_do_rinst)) begin
\t\t\tcase (mem_rdata_latched[1:0])
\t\t\t\t2\'b00: begin // Quadrant 0
\t\t\t\t\tcase (mem_rdata_latched[15:13])
\t\t\t\t\t\t3\'b000: begin // C.ADDI4SPN
\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b000;
\t\t\t\t\t\t\tmem_rdata_q[31:20] <= {2\'b0, mem_rdata_latched[10:7], mem_rdata_latched[12:11], mem_rdata_latched[5], mem_rdata_latched[6], 2\'b00};
\t\t\t\t\t\tend
\t\t\t\t\t\t3\'b010: begin // C.LW
\t\t\t\t\t\t\tmem_rdata_q[31:20] <= {5\'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2\'b00};
\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b 010;
\t\t\t\t\t\tend
\t\t\t\t\t\t3\'b 110: begin // C.SW
\t\t\t\t\t\t\t{mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {5\'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2\'b00};
\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b 010;
\t\t\t\t\t\tend
\t\t\t\t\tendcase
\t\t\t\tend
\t\t\t\t2\'b01: begin // Quadrant 1
\t\t\t\t\tcase (mem_rdata_latched[15:13])
\t\t\t\t\t\t3\'b 000: begin // C.ADDI
\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b000;
\t\t\t\t\t\t\tmem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
\t\t\t\t\t\tend
\t\t\t\t\t\t3\'b 010: begin // C.LI
\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b000;
\t\t\t\t\t\t\tmem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
\t\t\t\t\t\tend
\t\t\t\t\t\t3\'b 011: begin
\t\t\t\t\t\t\tif (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP
\t\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b000;
\t\t\t\t\t\t\t\tmem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[4:3],
\t\t\t\t\t\t\t\t\t\tmem_rdata_latched[5], mem_rdata_latched[2], mem_rdata_latched[6], 4\'b 0000});
\t\t\t\t\t\t\tend else begin // C.LUI
\t\t\t\t\t\t\t\tmem_rdata_q[31:12] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\t\t3\'b100: begin
\t\t\t\t\t\t\tif (mem_rdata_latched[11:10] == 2\'b00) begin // C.SRLI
\t\t\t\t\t\t\t\tmem_rdata_q[31:25] <= 7\'b0000000;
\t\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b 101;
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tif (mem_rdata_latched[11:10] == 2\'b01) begin // C.SRAI
\t\t\t\t\t\t\t\tmem_rdata_q[31:25] <= 7\'b0100000;
\t\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b 101;
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tif (mem_rdata_latched[11:10] == 2\'b10) begin // C.ANDI
\t\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b111;
\t\t\t\t\t\t\t\tmem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tif (mem_rdata_latched[12:10] == 3\'b011) begin // C.SUB, C.XOR, C.OR, C.AND
\t\t\t\t\t\t\t\tif (mem_rdata_latched[6:5] == 2\'b00) mem_rdata_q[14:12] <= 3\'b000;
\t\t\t\t\t\t\t\tif (mem_rdata_latched[6:5] == 2\'b01) mem_rdata_q[14:12] <= 3\'b100;
\t\t\t\t\t\t\t\tif (mem_rdata_latched[6:5] == 2\'b10) mem_rdata_q[14:12] <= 3\'b110;
\t\t\t\t\t\t\t\tif (mem_rdata_latched[6:5] == 2\'b11) mem_rdata_q[14:12] <= 3\'b111;
\t\t\t\t\t\t\t\tmem_rdata_q[31:25] <= mem_rdata_latched[6:5] == 2\'b00 ? 7\'b0100000 : 7\'b0000000;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\t\t3\'b 110: begin // C.BEQZ
\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b000;
\t\t\t\t\t\t\t{ mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
\t\t\t\t\t\t\t\t\t$signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
\t\t\t\t\t\t\t\t\t\t\tmem_rdata_latched[11:10], mem_rdata_latched[4:3]});
\t\t\t\t\t\tend
\t\t\t\t\t\t3\'b 111: begin // C.BNEZ
\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b001;
\t\t\t\t\t\t\t{ mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
\t\t\t\t\t\t\t\t\t$signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
\t\t\t\t\t\t\t\t\t\t\tmem_rdata_latched[11:10], mem_rdata_latched[4:3]});
\t\t\t\t\t\tend
\t\t\t\t\tendcase
\t\t\t\tend
\t\t\t\t2\'b10: begin // Quadrant 2
\t\t\t\t\tcase (mem_rdata_latched[15:13])
\t\t\t\t\t\t3\'b000: begin // C.SLLI
\t\t\t\t\t\t\tmem_rdata_q[31:25] <= 7\'b0000000;
\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b 001;
\t\t\t\t\t\tend
\t\t\t\t\t\t3\'b010: begin // C.LWSP
\t\t\t\t\t\t\tmem_rdata_q[31:20] <= {4\'b0, mem_rdata_latched[3:2], mem_rdata_latched[12], mem_rdata_latched[6:4], 2\'b00};
\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b 010;
\t\t\t\t\t\tend
\t\t\t\t\t\t3\'b100: begin
\t\t\t\t\t\t\tif (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] == 0) begin // C.JR
\t\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b000;
\t\t\t\t\t\t\t\tmem_rdata_q[31:20] <= 12\'b0;
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tif (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV
\t\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b000;
\t\t\t\t\t\t\t\tmem_rdata_q[31:25] <= 7\'b0000000;
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tif (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR
\t\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b000;
\t\t\t\t\t\t\t\tmem_rdata_q[31:20] <= 12\'b0;
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tif (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD
\t\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b000;
\t\t\t\t\t\t\t\tmem_rdata_q[31:25] <= 7\'b0000000;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\t\t3\'b110: begin // C.SWSP
\t\t\t\t\t\t\t{mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {4\'b0, mem_rdata_latched[8:7], mem_rdata_latched[12:9], 2\'b00};
\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b 010;
\t\t\t\t\t\tend
\t\t\t\t\tendcase
\t\t\t\tend
\t\t\tendcase
\t\tend
\tend
\talways @(posedge clk) begin
\t\tif (resetn && !trap) begin
\t\t\tif (mem_do_prefetch || mem_do_rinst || mem_do_rdata)
\t\t\t\t`assert(!mem_do_wdata);
\t\t\tif (mem_do_prefetch || mem_do_rinst)
\t\t\t\t`assert(!mem_do_rdata);
\t\t\tif (mem_do_rdata)
\t\t\t\t`assert(!mem_do_prefetch && !mem_do_rinst);
\t\t\tif (mem_do_wdata)
\t\t\t\t`assert(!(mem_do_prefetch || mem_do_rinst || mem_do_rdata));
\t\t\tif (mem_state == 2 || mem_state == 3)
\t\t\t\t`assert(mem_valid || mem_do_prefetch);
\t\tend
\tend
\talways @(posedge clk) begin
\t\tif (!resetn || trap) begin
\t\t\tif (!resetn)
\t\t\t\tmem_state <= 0;
\t\t\tif (!resetn || mem_ready)
\t\t\t\tmem_valid <= 0;
\t\t\tmem_la_secondword <= 0;
\t\t\tprefetched_high_word <= 0;
\t\tend else begin
\t\t\tif (mem_la_read || mem_la_write) begin
\t\t\t\tmem_addr <= mem_la_addr;
\t\t\t\tmem_wstrb <= mem_la_wstrb & {4{mem_la_write}};
\t\t\tend
\t\t\tif (mem_la_write) begin
\t\t\t\tmem_wdata <= mem_la_wdata;
\t\t\tend
\t\t\tcase (mem_state)
\t\t\t\t0: begin
\t\t\t\t\tif (mem_do_prefetch || mem_do_rinst || mem_do_rdata) begin
\t\t\t\t\t\tmem_valid <= !mem_la_use_prefetched_high_word;
\t\t\t\t\t\tmem_instr <= mem_do_prefetch || mem_do_rinst;
\t\t\t\t\t\tmem_wstrb <= 0;
\t\t\t\t\t\tmem_state <= 1;
\t\t\t\t\tend
\t\t\t\t\tif (mem_do_wdata) begin
\t\t\t\t\t\tmem_valid <= 1;
\t\t\t\t\t\tmem_instr <= 0;
\t\t\t\t\t\tmem_state <= 2;
\t\t\t\t\tend
\t\t\t\tend
\t\t\t\t1: begin
\t\t\t\t\t`assert(mem_wstrb == 0);
\t\t\t\t\t`assert(mem_do_prefetch || mem_do_rinst || mem_do_rdata);
\t\t\t\t\t`assert(mem_valid == !mem_la_use_prefetched_high_word);
\t\t\t\t\t`assert(mem_instr == (mem_do_prefetch || mem_do_rinst));
\t\t\t\t\tif (mem_xfer) begin
\t\t\t\t\t\tif (COMPRESSED_ISA && mem_la_read) begin
\t\t\t\t\t\t\tmem_valid <= 1;
\t\t\t\t\t\t\tmem_la_secondword <= 1;
\t\t\t\t\t\t\tif (!mem_la_use_prefetched_high_word)
\t\t\t\t\t\t\t\tmem_16bit_buffer <= mem_rdata[31:16];
\t\t\t\t\t\tend else begin
\t\t\t\t\t\t\tmem_valid <= 0;
\t\t\t\t\t\t\tmem_la_secondword <= 0;
\t\t\t\t\t\t\tif (COMPRESSED_ISA && !mem_do_rdata) begin
\t\t\t\t\t\t\t\tif (~&mem_rdata[1:0] || mem_la_secondword) begin
\t\t\t\t\t\t\t\t\tmem_16bit_buffer <= mem_rdata[31:16];
\t\t\t\t\t\t\t\t\tprefetched_high_word <= 1;
\t\t\t\t\t\t\t\tend else begin
\t\t\t\t\t\t\t\t\tprefetched_high_word <= 0;
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tmem_state <= mem_do_rinst || mem_do_rdata ? 0 : 3;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tend
\t\t\t\t2: begin
\t\t\t\t\t`assert(mem_wstrb != 0);
\t\t\t\t\t`assert(mem_do_wdata);
\t\t\t\t\tif (mem_xfer) begin
\t\t\t\t\t\tmem_valid <= 0;
\t\t\t\t\t\tmem_state <= 0;
\t\t\t\t\tend
\t\t\t\tend
\t\t\t\t3: begin
\t\t\t\t\t`assert(mem_wstrb == 0);
\t\t\t\t\t`assert(mem_do_prefetch);
\t\t\t\t\tif (mem_do_rinst) begin
\t\t\t\t\t\tmem_state <= 0;
\t\t\t\t\tend
\t\t\t\tend
\t\t\tendcase
\t\tend
\t\tif (clear_prefetched_high_word)
\t\t\tprefetched_high_word <= 0;
\tend
\t// Instruction Decoder
\treg instr_lui, instr_auipc, instr_jal, instr_jalr;
\treg instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu;
\treg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw;
\treg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai;
\treg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and;
\treg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak;
\treg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer;
reg instr_delint;
reg [31:0] delintreg;
\twire instr_trap;
\treg [regindex_bits-1:0] decoded_rd, decoded_rs1, decoded_rs2;
\treg [31:0] decoded_imm, decoded_imm_uj;
\treg decoder_trigger;
\treg decoder_trigger_q;
\treg decoder_pseudo_trigger;
\treg decoder_pseudo_trigger_q;
\treg compressed_instr;
\treg is_lui_auipc_jal;
\treg is_lb_lh_lw_lbu_lhu;
\treg is_slli_srli_srai;
\treg is_jalr_addi_slti_sltiu_xori_ori_andi;
\treg is_sb_sh_sw;
\treg is_sll_srl_sra;
\treg is_lui_auipc_jal_jalr_addi_add_sub;
\treg is_slti_blt_slt;
\treg is_sltiu_bltu_sltu;
\treg is_beq_bne_blt_bge_bltu_bgeu;
\treg is_lbu_lhu_lw;
\treg is_alu_reg_imm;
\treg is_alu_reg_reg;
\treg is_compare;
\tassign instr_trap = (CATCH_ILLINSN || WITH_PCPI) && !{instr_lui, instr_auipc, instr_jal, instr_jalr,
\t\t\tinstr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu,
\t\t\tinstr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw,
\t\t\tinstr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai,
\t\t\tinstr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and,
\t\t\tinstr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh,
\t\t\tinstr_getq, instr_setq, instr_delint, instr_retirq, instr_maskirq, instr_waitirq, instr_timer};
\t
\twire is_rdcycle_rdcycleh_rdinstr_rdinstrh;
\tassign is_rdcycle_rdcycleh_rdinstr_rdinstrh = |{instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh};
\treg [63:0] new_ascii_instr;
\t`FORMAL_KEEP reg [63:0] dbg_ascii_instr;
\t`FORMAL_KEEP reg [31:0] dbg_insn_imm;
\t`FORMAL_KEEP reg [4:0] dbg_insn_rs1;
\t`FORMAL_KEEP reg [4:0] dbg_insn_rs2;
\t`FORMAL_KEEP reg [4:0] dbg_insn_rd;
\t`FORMAL_KEEP reg [31:0] dbg_rs1val;
\t`FORMAL_KEEP reg [31:0] dbg_rs2val;
\t`FORMAL_KEEP reg dbg_rs1val_valid;
\t`FORMAL_KEEP reg dbg_rs2val_valid;
\talways @* begin
\t\tnew_ascii_instr = "";
\t\tif (instr_lui) new_ascii_instr = "lui";
\t\tif (instr_auipc) new_ascii_instr = "auipc";
\t\tif (instr_jal) new_ascii_instr = "jal";
\t\tif (instr_jalr) new_ascii_instr = "jalr";
\t\tif (instr_beq) new_ascii_instr = "beq";
\t\tif (instr_bne) new_ascii_instr = "bne";
\t\tif (instr_blt) new_ascii_instr = "blt";
\t\tif (instr_bge) new_ascii_instr = "bge";
\t\tif (instr_bltu) new_ascii_instr = "bltu";
\t\tif (instr_bgeu) new_ascii_instr = "bgeu";
\t\tif (instr_lb) new_ascii_instr = "lb";
\t\tif (instr_lh) new_ascii_instr = "lh";
\t\tif (instr_lw) new_ascii_instr = "lw";
\t\tif (instr_lbu) new_ascii_instr = "lbu";
\t\tif (instr_lhu) new_ascii_instr = "lhu";
\t\tif (instr_sb) new_ascii_instr = "sb";
\t\tif (instr_sh) new_ascii_instr = "sh";
\t\tif (instr_sw) new_ascii_instr = "sw";
\t\tif (instr_addi) new_ascii_instr = "addi";
\t\tif (instr_slti) new_ascii_instr = "slti";
\t\tif (instr_sltiu) new_ascii_instr = "sltiu";
\t\tif (instr_xori) new_ascii_instr = "xori";
\t\tif (instr_ori) new_ascii_instr = "ori";
\t\tif (instr_andi) new_ascii_instr = "andi";
\t\tif (instr_slli) new_ascii_instr = "slli";
\t\tif (instr_srli) new_ascii_instr = "srli";
\t\tif (instr_srai) new_ascii_instr = "srai";
\t\tif (instr_add) new_ascii_instr = "add";
\t\tif (instr_sub) new_ascii_instr = "sub";
\t\tif (instr_sll) new_ascii_instr = "sll";
\t\tif (instr_slt) new_ascii_instr = "slt";
\t\tif (instr_sltu) new_ascii_instr = "sltu";
\t\tif (instr_xor) new_ascii_instr = "xor";
\t\tif (instr_srl) new_ascii_instr = "srl";
\t\tif (instr_sra) new_ascii_instr = "sra";
\t\tif (instr_or) new_ascii_instr = "or";
\t\tif (instr_and) new_ascii_instr = "and";
\t\tif (instr_rdcycle) new_ascii_instr = "rdcycle";
\t\tif (instr_rdcycleh) new_ascii_instr = "rdcycleh";
\t\tif (instr_rdinstr) new_ascii_instr = "rdinstr";
\t\tif (instr_rdinstrh) new_ascii_instr = "rdinstrh";
\t\tif (instr_getq) new_ascii_instr = "getq";
\t\tif (instr_setq) new_ascii_instr = "setq";
if (instr_delint) new_ascii_instr = "delint";
\t\tif (instr_retirq) new_ascii_instr = "retirq";
\t\tif (instr_maskirq) new_ascii_instr = "maskirq";
\t\tif (instr_waitirq) new_ascii_instr = "waitirq";
\t\tif (instr_timer) new_ascii_instr = "timer";
\tend
\treg [63:0] q_ascii_instr;
\treg [31:0] q_insn_imm;
\treg [31:0] q_insn_opcode;
\treg [4:0] q_insn_rs1;
\treg [4:0] q_insn_rs2;
\treg [4:0] q_insn_rd;
\treg dbg_next;
\twire launch_next_insn;
\treg dbg_valid_insn;
\treg [63:0] cached_ascii_instr;
\treg [31:0] cached_insn_imm;
\treg [31:0] cached_insn_opcode;
\treg [4:0] cached_insn_rs1;
\treg [4:0] cached_insn_rs2;
\treg [4:0] cached_insn_rd;
\talways @(posedge clk) begin
\t\tq_ascii_instr <= dbg_ascii_instr;
\t\tq_insn_imm <= dbg_insn_imm;
\t\tq_insn_opcode <= dbg_insn_opcode;
\t\tq_insn_rs1 <= dbg_insn_rs1;
\t\tq_insn_rs2 <= dbg_insn_rs2;
\t\tq_insn_rd <= dbg_insn_rd;
\t\tdbg_next <= launch_next_insn;
\t\tif (!resetn || trap)
\t\t\tdbg_valid_insn <= 0;
\t\telse if (launch_next_insn)
\t\t\tdbg_valid_insn <= 1;
\t\tif (decoder_trigger_q) begin
\t\t\tcached_ascii_instr <= new_ascii_instr;
\t\t\tcached_insn_imm <= decoded_imm;
\t\t\tif (&next_insn_opcode[1:0])
\t\t\t\tcached_insn_opcode <= next_insn_opcode;
\t\t\telse
\t\t\t\tcached_insn_opcode <= {16\'b0, next_insn_opcode[15:0]};
\t\t\tcached_insn_rs1 <= decoded_rs1;
\t\t\tcached_insn_rs2 <= decoded_rs2;
\t\t\tcached_insn_rd <= decoded_rd;
\t\tend
\t\tif (launch_next_insn) begin
\t\t\tdbg_insn_addr <= next_pc;
\t\tend
\tend
\talways @* begin
\t\tdbg_ascii_instr = q_ascii_instr;
\t\tdbg_insn_imm = q_insn_imm;
\t\tdbg_insn_opcode = q_insn_opcode;
\t\tdbg_insn_rs1 = q_insn_rs1;
\t\tdbg_insn_rs2 = q_insn_rs2;
\t\tdbg_insn_rd = q_insn_rd;
\t\tif (dbg_next) begin
\t\t\tif (decoder_pseudo_trigger_q) begin
\t\t\t\tdbg_ascii_instr = cached_ascii_instr;
\t\t\t\tdbg_insn_imm = cached_insn_imm;
\t\t\t\tdbg_insn_opcode = cached_insn_opcode;
\t\t\t\tdbg_insn_rs1 = cached_insn_rs1;
\t\t\t\tdbg_insn_rs2 = cached_insn_rs2;
\t\t\t\tdbg_insn_rd = cached_insn_rd;
\t\t\tend else begin
\t\t\t\tdbg_ascii_instr = new_ascii_instr;
\t\t\t\tif (&next_insn_opcode[1:0])
\t\t\t\t\tdbg_insn_opcode = next_insn_opcode;
\t\t\t\telse
\t\t\t\t\tdbg_insn_opcode = {16\'b0, next_insn_opcode[15:0]};
\t\t\t\tdbg_insn_imm = decoded_imm;
\t\t\t\tdbg_insn_rs1 = decoded_rs1;
\t\t\t\tdbg_insn_rs2 = decoded_rs2;
\t\t\t\tdbg_insn_rd = decoded_rd;
\t\t\tend
\t\tend
\tend
`ifdef DEBUGASM
\talways @(posedge clk) begin
\t\tif (dbg_next) begin
\t\t\t$display("debugasm %x %x %s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "*");
\t\tend
\tend
`endif
`ifdef DEBUG
\talways @(posedge clk) begin
\t\tif (dbg_next) begin
\t\t\tif (&dbg_insn_opcode[1:0])
\t\t\t\t$display("DECODE: 0x%08x 0x%08x %s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
\t\t\telse
\t\t\t\t$display("DECODE: 0x%08x 0x%04x %s", dbg_insn_addr, dbg_insn_opcode[15:0], dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
\t\tend
\tend
`endif
\talways @(posedge clk) begin
\t\tis_lui_auipc_jal <= |{instr_lui, instr_auipc, instr_jal};
\t\tis_lui_auipc_jal_jalr_addi_add_sub <= |{instr_lui, instr_auipc, instr_jal, instr_jalr, instr_addi, instr_add, instr_sub};
\t\tis_slti_blt_slt <= |{instr_slti, instr_blt, instr_slt};
\t\tis_sltiu_bltu_sltu <= |{instr_sltiu, instr_bltu, instr_sltu};
\t\tis_lbu_lhu_lw <= |{instr_lbu, instr_lhu, instr_lw};
\t\tis_compare <= |{is_beq_bne_blt_bge_bltu_bgeu, instr_slti, instr_slt, instr_sltiu, instr_sltu};
\t\tif (mem_do_rinst && mem_done) begin
\t\t\tinstr_lui <= mem_rdata_latched[6:0] == 7\'b0110111;
\t\t\tinstr_auipc <= mem_rdata_latched[6:0] == 7\'b0010111;
\t\t\tinstr_jal <= mem_rdata_latched[6:0] == 7\'b1101111;
\t\t\tinstr_jalr <= mem_rdata_latched[6:0] == 7\'b1100111 && mem_rdata_latched[14:12] == 3\'b000;
\t\t\tinstr_retirq <= mem_rdata_latched[6:0] == 7\'b0001011 && mem_rdata_latched[31:25] == 7\'b0000010 && ENABLE_IRQ;
\t\t\tinstr_waitirq <= mem_rdata_latched[6:0] == 7\'b0001011 && mem_rdata_latched[31:25] == 7\'b0000100 && ENABLE_IRQ;
\t\t\tis_beq_bne_blt_bge_bltu_bgeu <= mem_rdata_latched[6:0] == 7\'b1100011;
\t\t\tis_lb_lh_lw_lbu_lhu <= mem_rdata_latched[6:0] == 7\'b0000011;
\t\t\tis_sb_sh_sw <= mem_rdata_latched[6:0] == 7\'b0100011;
\t\t\tis_alu_reg_imm <= mem_rdata_latched[6:0] == 7\'b0010011;
\t\t\tis_alu_reg_reg <= mem_rdata_latched[6:0] == 7\'b0110011;
\t\t\t{ decoded_imm_uj[31:20], decoded_imm_uj[10:1], decoded_imm_uj[11], decoded_imm_uj[19:12], decoded_imm_uj[0] } <= $signed({mem_rdata_latched[31:12], 1\'b0});
\t\t\tdecoded_rd <= mem_rdata_latched[11:7];
\t\t\tdecoded_rs1 <= mem_rdata_latched[19:15];
\t\t\tdecoded_rs2 <= mem_rdata_latched[24:20];
\t\t\tif (mem_rdata_latched[6:0] == 7\'b0001011 && mem_rdata_latched[31:25] == 7\'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS)
\t\t\t\tdecoded_rs1[regindex_bits-1] <= 1; // instr_getq
\t\t\tif (mem_rdata_latched[6:0] == 7\'b0001011 && mem_rdata_latched[31:25] == 7\'b0000010 && ENABLE_IRQ)
\t\t\t\tdecoded_rs1 <= ENABLE_IRQ_QREGS ? irqregs_offset : 3; // instr_retirq
\t\t\tcompressed_instr <= 0;
\t\t\tif (COMPRESSED_ISA && mem_rdata_latched[1:0] != 2\'b11) begin
\t\t\t\tcompressed_instr <= 1;
\t\t\t\tdecoded_rd <= 0;
\t\t\t\tdecoded_rs1 <= 0;
\t\t\t\tdecoded_rs2 <= 0;
\t\t\t\t{ decoded_imm_uj[31:11], decoded_imm_uj[4], decoded_imm_uj[9:8], decoded_imm_uj[10], decoded_imm_uj[6],
\t\t\t\t decoded_imm_uj[7], decoded_imm_uj[3:1], decoded_imm_uj[5], decoded_imm_uj[0] } <= $signed({mem_rdata_latched[12:2], 1\'b0});
\t\t\t\tcase (mem_rdata_latched[1:0])
\t\t\t\t\t2\'b00: begin // Quadrant 0
\t\t\t\t\t\tcase (mem_rdata_latched[15:13])
\t\t\t\t\t\t\t3\'b000: begin // C.ADDI4SPN
\t\t\t\t\t\t\t\tis_alu_reg_imm <= |mem_rdata_latched[12:5];
\t\t\t\t\t\t\t\tdecoded_rs1 <= 2;
\t\t\t\t\t\t\t\tdecoded_rd <= 8 + mem_rdata_latched[4:2];
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t3\'b010: begin // C.LW
\t\t\t\t\t\t\t\tis_lb_lh_lw_lbu_lhu <= 1;
\t\t\t\t\t\t\t\tdecoded_rs1 <= 8 + mem_rdata_latched[9:7];
\t\t\t\t\t\t\t\tdecoded_rd <= 8 + mem_rdata_latched[4:2];
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t3\'b110: begin // C.SW
\t\t\t\t\t\t\t\tis_sb_sh_sw <= 1;
\t\t\t\t\t\t\t\tdecoded_rs1 <= 8 + mem_rdata_latched[9:7];
\t\t\t\t\t\t\t\tdecoded_rs2 <= 8 + mem_rdata_latched[4:2];
\t\t\t\t\t\t\tend
\t\t\t\t\t\tendcase
\t\t\t\t\tend
\t\t\t\t\t2\'b01: begin // Quadrant 1
\t\t\t\t\t\tcase (mem_rdata_latched[15:13])
\t\t\t\t\t\t\t3\'b000: begin // C.NOP / C.ADDI
\t\t\t\t\t\t\t\tis_alu_reg_imm <= 1;
\t\t\t\t\t\t\t\tdecoded_rd <= mem_rdata_latched[11:7];
\t\t\t\t\t\t\t\tdecoded_rs1 <= mem_rdata_latched[11:7];
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t3\'b001: begin // C.JAL
\t\t\t\t\t\t\t\tinstr_jal <= 1;
\t\t\t\t\t\t\t\tdecoded_rd <= 1;
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t3\'b 010: begin // C.LI
\t\t\t\t\t\t\t\tis_alu_reg_imm <= 1;
\t\t\t\t\t\t\t\tdecoded_rd <= mem_rdata_latched[11:7];
\t\t\t\t\t\t\t\tdecoded_rs1 <= 0;
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t3\'b 011: begin
\t\t\t\t\t\t\t\tif (mem_rdata_latched[12] || mem_rdata_latched[6:2]) begin
\t\t\t\t\t\t\t\t\tif (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP
\t\t\t\t\t\t\t\t\t\tis_alu_reg_imm <= 1;
\t\t\t\t\t\t\t\t\t\tdecoded_rd <= mem_rdata_latched[11:7];
\t\t\t\t\t\t\t\t\t\tdecoded_rs1 <= mem_rdata_latched[11:7];
\t\t\t\t\t\t\t\t\tend else begin // C.LUI
\t\t\t\t\t\t\t\t\t\tinstr_lui <= 1;
\t\t\t\t\t\t\t\t\t\tdecoded_rd <= mem_rdata_latched[11:7];
\t\t\t\t\t\t\t\t\t\tdecoded_rs1 <= 0;
\t\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t3\'b100: begin
\t\t\t\t\t\t\t\tif (!mem_rdata_latched[11] && !mem_rdata_latched[12]) begin // C.SRLI, C.SRAI
\t\t\t\t\t\t\t\t\tis_alu_reg_imm <= 1;
\t\t\t\t\t\t\t\t\tdecoded_rd <= 8 + mem_rdata_latched[9:7];
\t\t\t\t\t\t\t\t\tdecoded_rs1 <= 8 + mem_rdata_latched[9:7];
\t\t\t\t\t\t\t\t\tdecoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\tif (mem_rdata_latched[11:10] == 2\'b10) begin // C.ANDI
\t\t\t\t\t\t\t\t\tis_alu_reg_imm <= 1;
\t\t\t\t\t\t\t\t\tdecoded_rd <= 8 + mem_rdata_latched[9:7];
\t\t\t\t\t\t\t\t\tdecoded_rs1 <= 8 + mem_rdata_latched[9:7];
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\tif (mem_rdata_latched[12:10] == 3\'b011) begin // C.SUB, C.XOR, C.OR, C.AND
\t\t\t\t\t\t\t\t\tis_alu_reg_reg <= 1;
\t\t\t\t\t\t\t\t\tdecoded_rd <= 8 + mem_rdata_latched[9:7];
\t\t\t\t\t\t\t\t\tdecoded_rs1 <= 8 + mem_rdata_latched[9:7];
\t\t\t\t\t\t\t\t\tdecoded_rs2 <= 8 + mem_rdata_latched[4:2];
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t3\'b101: begin // C.J
\t\t\t\t\t\t\t\tinstr_jal <= 1;
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t3\'b110: begin // C.BEQZ
\t\t\t\t\t\t\t\tis_beq_bne_blt_bge_bltu_bgeu <= 1;
\t\t\t\t\t\t\t\tdecoded_rs1 <= 8 + mem_rdata_latched[9:7];
\t\t\t\t\t\t\t\tdecoded_rs2 <= 0;
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t3\'b111: begin // C.BNEZ
\t\t\t\t\t\t\t\tis_beq_bne_blt_bge_bltu_bgeu <= 1;
\t\t\t\t\t\t\t\tdecoded_rs1 <= 8 + mem_rdata_latched[9:7];
\t\t\t\t\t\t\t\tdecoded_rs2 <= 0;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tendcase
\t\t\t\t\tend
\t\t\t\t\t2\'b10: begin // Quadrant 2
\t\t\t\t\t\tcase (mem_rdata_latched[15:13])
\t\t\t\t\t\t\t3\'b000: begin // C.SLLI
\t\t\t\t\t\t\t\tif (!mem_rdata_latched[12]) begin
\t\t\t\t\t\t\t\t\tis_alu_reg_imm <= 1;
\t\t\t\t\t\t\t\t\tdecoded_rd <= mem_rdata_latched[11:7];
\t\t\t\t\t\t\t\t\tdecoded_rs1 <= mem_rdata_latched[11:7];
\t\t\t\t\t\t\t\t\tdecoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t3\'b010: begin // C.LWSP
\t\t\t\t\t\t\t\tif (mem_rdata_latched[11:7]) begin
\t\t\t\t\t\t\t\t\tis_lb_lh_lw_lbu_lhu <= 1;
\t\t\t\t\t\t\t\t\tdecoded_rd <= mem_rdata_latched[11:7];
\t\t\t\t\t\t\t\t\tdecoded_rs1 <= 2;
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t3\'b100: begin
\t\t\t\t\t\t\t\tif (mem_rdata_latched[12] == 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JR
\t\t\t\t\t\t\t\t\tinstr_jalr <= 1;
\t\t\t\t\t\t\t\t\tdecoded_rd <= 0;
\t\t\t\t\t\t\t\t\tdecoded_rs1 <= mem_rdata_latched[11:7];
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\tif (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV
\t\t\t\t\t\t\t\t\tis_alu_reg_reg <= 1;
\t\t\t\t\t\t\t\t\tdecoded_rd <= mem_rdata_latched[11:7];
\t\t\t\t\t\t\t\t\tdecoded_rs1 <= 0;
\t\t\t\t\t\t\t\t\tdecoded_rs2 <= mem_rdata_latched[6:2];
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\tif (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR
\t\t\t\t\t\t\t\t\tinstr_jalr <= 1;
\t\t\t\t\t\t\t\t\tdecoded_rd <= 1;
\t\t\t\t\t\t\t\t\tdecoded_rs1 <= mem_rdata_latched[11:7];
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\tif (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD
\t\t\t\t\t\t\t\t\tis_alu_reg_reg <= 1;
\t\t\t\t\t\t\t\t\tdecoded_rd <= mem_rdata_latched[11:7];
\t\t\t\t\t\t\t\t\tdecoded_rs1 <= mem_rdata_latched[11:7];
\t\t\t\t\t\t\t\t\tdecoded_rs2 <= mem_rdata_latched[6:2];
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t3\'b110: begin // C.SWSP
\t\t\t\t\t\t\t\tis_sb_sh_sw <= 1;
\t\t\t\t\t\t\t\tdecoded_rs1 <= 2;
\t\t\t\t\t\t\t\tdecoded_rs2 <= mem_rdata_latched[6:2];
\t\t\t\t\t\t\tend
\t\t\t\t\t\tendcase
\t\t\t\t\tend
\t\t\t\tendcase
\t\t\tend
\t\tend
\t\tif (decoder_trigger && !decoder_pseudo_trigger) begin
\t\t\tpcpi_insn <= WITH_PCPI ? mem_rdata_q : \'bx;
\t\t\tinstr_beq <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3\'b000;
\t\t\tinstr_bne <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3\'b001;
\t\t\tinstr_blt <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3\'b100;
\t\t\tinstr_bge <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3\'b101;
\t\t\tinstr_bltu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3\'b110;
\t\t\tinstr_bgeu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3\'b111;
\t\t\tinstr_lb <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3\'b000;
\t\t\tinstr_lh <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3\'b001;
\t\t\tinstr_lw <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3\'b010;
\t\t\tinstr_lbu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3\'b100;
\t\t\tinstr_lhu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3\'b101;
\t\t\tinstr_sb <= is_sb_sh_sw && mem_rdata_q[14:12] == 3\'b000;
\t\t\tinstr_sh <= is_sb_sh_sw && mem_rdata_q[14:12] == 3\'b001;
\t\t\tinstr_sw <= is_sb_sh_sw && mem_rdata_q[14:12] == 3\'b010;
\t\t\tinstr_addi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3\'b000;
\t\t\tinstr_slti <= is_alu_reg_imm && mem_rdata_q[14:12] == 3\'b010;
\t\t\tinstr_sltiu <= is_alu_reg_imm && mem_rdata_q[14:12] == 3\'b011;
\t\t\tinstr_xori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3\'b100;
\t\t\tinstr_ori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3\'b110;
\t\t\tinstr_andi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3\'b111;
\t\t\tinstr_slli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3\'b001 && mem_rdata_q[31:25] == 7\'b0000000;
\t\t\tinstr_srli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3\'b101 && mem_rdata_q[31:25] == 7\'b0000000;
\t\t\tinstr_srai <= is_alu_reg_imm && mem_rdata_q[14:12] == 3\'b101 && mem_rdata_q[31:25] == 7\'b0100000;
\t\t\tinstr_add <= is_alu_reg_reg && mem_rdata_q[14:12] == 3\'b000 && mem_rdata_q[31:25] == 7\'b0000000;
\t\t\tinstr_sub <= is_alu_reg_reg && mem_rdata_q[14:12] == 3\'b000 && mem_rdata_q[31:25] == 7\'b0100000;
\t\t\tinstr_sll <= is_alu_reg_reg && mem_rdata_q[14:12] == 3\'b001 && mem_rdata_q[31:25] == 7\'b0000000;
\t\t\tinstr_slt <= is_alu_reg_reg && mem_rdata_q[14:12] == 3\'b010 && mem_rdata_q[31:25] == 7\'b0000000;
\t\t\tinstr_sltu <= is_alu_reg_reg && mem_rdata_q[14:12] == 3\'b011 && mem_rdata_q[31:25] == 7\'b0000000;
\t\t\tinstr_xor <= is_alu_reg_reg && mem_rdata_q[14:12] == 3\'b100 && mem_rdata_q[31:25] == 7\'b0000000;
\t\t\tinstr_srl <= is_alu_reg_reg && mem_rdata_q[14:12] == 3\'b101 && mem_rdata_q[31:25] == 7\'b0000000;
\t\t\tinstr_sra <= is_alu_reg_reg && mem_rdata_q[14:12] == 3\'b101 && mem_rdata_q[31:25] == 7\'b0100000;
\t\t\tinstr_or <= is_alu_reg_reg && mem_rdata_q[14:12] == 3\'b110 && mem_rdata_q[31:25] == 7\'b0000000;
\t\t\tinstr_and <= is_alu_reg_reg && mem_rdata_q[14:12] == 3\'b111 && mem_rdata_q[31:25] == 7\'b0000000;
\t\t\tinstr_rdcycle <= ((mem_rdata_q[6:0] == 7\'b1110011 && mem_rdata_q[31:12] == \'b11000000000000000010) ||
\t\t\t (mem_rdata_q[6:0] == 7\'b1110011 && mem_rdata_q[31:12] == \'b11000000000100000010)) && ENABLE_COUNTERS;
\t\t\tinstr_rdcycleh <= ((mem_rdata_q[6:0] == 7\'b1110011 && mem_rdata_q[31:12] == \'b11001000000000000010) ||
\t\t\t (mem_rdata_q[6:0] == 7\'b1110011 && mem_rdata_q[31:12] == \'b11001000000100000010)) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
\t\t\tinstr_rdinstr <= (mem_rdata_q[6:0] == 7\'b1110011 && mem_rdata_q[31:12] == \'b11000000001000000010) && ENABLE_COUNTERS;
\t\t\tinstr_rdinstrh <= (mem_rdata_q[6:0] == 7\'b1110011 && mem_rdata_q[31:12] == \'b11001000001000000010) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
\t\t\tinstr_ecall_ebreak <= ((mem_rdata_q[6:0] == 7\'b1110011 && !mem_rdata_q[31:21] && !mem_rdata_q[19:7]) ||
\t\t\t\t\t(COMPRESSED_ISA && mem_rdata_q[15:0] == 16\'h9002));
\t\t\tinstr_getq <= mem_rdata_q[6:0] == 7\'b0001011 && mem_rdata_q[31:25] == 7\'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
\t\t\tinstr_setq <= mem_rdata_q[6:0] == 7\'b0001011 && mem_rdata_q[31:25] == 7\'b0000001 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
instr_delint <= mem_rdata_q[6:0] == 7\'b0001011 && mem_rdata_q[31:25] == 7\'b0000110 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
\t\t\tinstr_maskirq <= mem_rdata_q[6:0] == 7\'b0001011 && mem_rdata_q[31:25] == 7\'b0000011 && ENABLE_IRQ;
\t\t\tinstr_timer <= mem_rdata_q[6:0] == 7\'b0001011 && mem_rdata_q[31:25] == 7\'b0000101 && ENABLE_IRQ && ENABLE_IRQ_TIMER;
\t\t\tis_slli_srli_srai <= is_alu_reg_imm && |{
\t\t\t\tmem_rdata_q[14:12] == 3\'b001 && mem_rdata_q[31:25] == 7\'b0000000,
\t\t\t\tmem_rdata_q[14:12] == 3\'b101 && mem_rdata_q[31:25] == 7\'b0000000,
\t\t\t\tmem_rdata_q[14:12] == 3\'b101 && mem_rdata_q[31:25] == 7\'b0100000
\t\t\t};
\t\t\tis_jalr_addi_slti_sltiu_xori_ori_andi <= instr_jalr || is_alu_reg_imm && |{
\t\t\t\tmem_rdata_q[14:12] == 3\'b000,
\t\t\t\tmem_rdata_q[14:12] == 3\'b010,
\t\t\t\tmem_rdata_q[14:12] == 3\'b011,
\t\t\t\tmem_rdata_q[14:12] == 3\'b100,
\t\t\t\tmem_rdata_q[14:12] == 3\'b110,
\t\t\t\tmem_rdata_q[14:12] == 3\'b111
\t\t\t};
\t\t\tis_sll_srl_sra <= is_alu_reg_reg && |{
\t\t\t\tmem_rdata_q[14:12] == 3\'b001 && mem_rdata_q[31:25] == 7\'b0000000,
\t\t\t\tmem_rdata_q[14:12] == 3\'b101 && mem_rdata_q[31:25] == 7\'b0000000,
\t\t\t\tmem_rdata_q[14:12] == 3\'b101 && mem_rdata_q[31:25] == 7\'b0100000
\t\t\t};
\t\t\tis_lui_auipc_jal_jalr_addi_add_sub <= 0;
\t\t\tis_compare <= 0;
\t\t\t(* parallel_case *)
\t\t\tcase (1\'b1)
\t\t\t\tinstr_jal:
\t\t\t\t\tdecoded_imm <= decoded_imm_uj;
\t\t\t\t|{instr_lui, instr_auipc}:
\t\t\t\t\tdecoded_imm <= mem_rdata_q[31:12] << 12;
\t\t\t\t|{instr_jalr, is_lb_lh_lw_lbu_lhu, is_alu_reg_imm}:
\t\t\t\t\tdecoded_imm <= $signed(mem_rdata_q[31:20]);
\t\t\t\tis_beq_bne_blt_bge_bltu_bgeu:
\t\t\t\t\tdecoded_imm <= $signed({mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8], 1\'b0});
\t\t\t\tis_sb_sh_sw:
\t\t\t\t\tdecoded_imm <= $signed({mem_rdata_q[31:25], mem_rdata_q[11:7]});
\t\t\t\tdefault:
\t\t\t\t\tdecoded_imm <= 1\'bx;
\t\t\tendcase
\t\tend
\t\tif (!resetn) begin
\t\t\tis_beq_bne_blt_bge_bltu_bgeu <= 0;
\t\t\tis_compare <= 0;
\t\t\tinstr_beq <= 0;
\t\t\tinstr_bne <= 0;
\t\t\tinstr_blt <= 0;
\t\t\tinstr_bge <= 0;
\t\t\tinstr_bltu <= 0;
\t\t\tinstr_bgeu <= 0;
\t\t\tinstr_addi <= 0;
\t\t\tinstr_slti <= 0;
\t\t\tinstr_sltiu <= 0;
\t\t\tinstr_xori <= 0;
\t\t\tinstr_ori <= 0;
\t\t\tinstr_andi <= 0;
\t\t\tinstr_add <= 0;
\t\t\tinstr_sub <= 0;
\t\t\tinstr_sll <= 0;
\t\t\tinstr_slt <= 0;
\t\t\tinstr_sltu <= 0;
\t\t\tinstr_xor <= 0;
\t\t\tinstr_srl <= 0;
\t\t\tinstr_sra <= 0;
\t\t\tinstr_or <= 0;
\t\t\tinstr_and <= 0;
\t\tend
\tend
\t// Main State Machine
\tlocalparam cpu_state_trap = 8\'b10000000;
\tlocalparam cpu_state_fetch = 8\'b01000000;
\tlocalparam cpu_state_ld_rs1 = 8\'b00100000;
\tlocalparam cpu_state_ld_rs2 = 8\'b00010000;
\tlocalparam cpu_state_exec = 8\'b00001000;
\tlocalparam cpu_state_shift = 8\'b00000100;
\tlocalparam cpu_state_stmem = 8\'b00000010;
\tlocalparam cpu_state_ldmem = 8\'b00000001;
\treg [7:0] cpu_state;
\treg [1:0] irq_state;
\t`FORMAL_KEEP reg [127:0] dbg_ascii_state;
\talways @* begin
\t\tdbg_ascii_state = "";
\t\tif (cpu_state == cpu_state_trap) dbg_ascii_state = "trap";
\t\tif (cpu_state == cpu_state_fetch) dbg_ascii_state = "fetch";
\t\tif (cpu_state == cpu_state_ld_rs1) dbg_ascii_state = "ld_rs1";
\t\tif (cpu_state == cpu_state_ld_rs2) dbg_ascii_state = "ld_rs2";
\t\tif (cpu_state == cpu_state_exec) dbg_ascii_state = "exec";
\t\tif (cpu_state == cpu_state_shift) dbg_ascii_state = "shift";
\t\tif (cpu_state == cpu_state_stmem) dbg_ascii_state = "stmem";
\t\tif (cpu_state == cpu_state_ldmem) dbg_ascii_state = "ldmem";
\tend
\treg set_mem_do_rinst;
\treg set_mem_do_rdata;
\treg set_mem_do_wdata;
\treg latched_store;
\treg latched_stalu;
\treg latched_branch;
\treg latched_compr;
\treg latched_trace;
\treg latched_is_lu;
\treg latched_is_lh;
\treg latched_is_lb;
\treg [regindex_bits-1:0] latched_rd;
\treg [31:0] current_pc;
\tassign next_pc = latched_store && latched_branch ? reg_out & ~1 : reg_next_pc;
\treg [3:0] pcpi_timeout_counter;
\treg pcpi_timeout;
\treg [31:0] next_irq_pending;
\treg do_waitirq;
\treg [31:0] alu_out, alu_out_q;
\treg alu_out_0, alu_out_0_q;
\treg alu_wait, alu_wait_2;
\treg [31:0] alu_add_sub;
\treg [31:0] alu_shl, alu_shr;
\treg alu_eq, alu_ltu, alu_lts;
\tgenerate if (TWO_CYCLE_ALU) begin
\t\talways @(posedge clk) begin
\t\t\talu_add_sub <= instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
\t\t\talu_eq <= reg_op1 == reg_op2;
\t\t\talu_lts <= $signed(reg_op1) < $signed(reg_op2);
\t\t\talu_ltu <= reg_op1 < reg_op2;
\t\t\talu_shl <= reg_op1 << reg_op2[4:0];
\t\t\talu_shr <= $signed({instr_sra || instr_srai ? reg_op1[31] : 1\'b0, reg_op1}) >>> reg_op2[4:0];
\t\tend
\tend else begin
\t\talways @* begin
\t\t\talu_add_sub = instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
\t\t\talu_eq = reg_op1 == reg_op2;
\t\t\talu_lts = $signed(reg_op1) < $signed(reg_op2);
\t\t\talu_ltu = reg_op1 < reg_op2;
\t\t\talu_shl = reg_op1 << reg_op2[4:0];
\t\t\talu_shr = $signed({instr_sra || instr_srai ? reg_op1[31] : 1\'b0, reg_op1}) >>> reg_op2[4:0];
\t\tend
\tend endgenerate
\talways @* begin
\t\talu_out_0 = \'bx;
\t\t(* parallel_case, full_case *)
\t\tcase (1\'b1)
\t\t\tinstr_beq:
\t\t\t\talu_out_0 = alu_eq;
\t\t\tinstr_bne:
\t\t\t\talu_out_0 = !alu_eq;
\t\t\tinstr_bge:
\t\t\t\talu_out_0 = !alu_lts;
\t\t\tinstr_bgeu:
\t\t\t\talu_out_0 = !alu_ltu;
\t\t\tis_slti_blt_slt && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
\t\t\t\talu_out_0 = alu_lts;
\t\t\tis_sltiu_bltu_sltu && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
\t\t\t\talu_out_0 = alu_ltu;
\t\tendcase
\t\talu_out = \'bx;
\t\t(* parallel_case, full_case *)
\t\tcase (1\'b1)
\t\t\tis_lui_auipc_jal_jalr_addi_add_sub:
\t\t\t\talu_out = alu_add_sub;
\t\t\tis_compare:
\t\t\t\talu_out = alu_out_0;
\t\t\tinstr_xori || instr_xor:
\t\t\t\talu_out = reg_op1 ^ reg_op2;
\t\t\tinstr_ori || instr_or:
\t\t\t\talu_out = reg_op1 | reg_op2;
\t\t\tinstr_andi || instr_and:
\t\t\t\talu_out = reg_op1 & reg_op2;
\t\t\tBARREL_SHI'b'FTER && (instr_sll || instr_slli):
\t\t\t\talu_out = alu_shl;
\t\t\tBARREL_SHIFTER && (instr_srl || instr_srli || instr_sra || instr_srai):
\t\t\t\talu_out = alu_shr;
\t\tendcase
`ifdef RISCV_FORMAL_BLACKBOX_ALU
\t\talu_out_0 = $anyseq;
\t\talu_out = $anyseq;
`endif
\tend
\treg clear_prefetched_high_word_q;
\talways @(posedge clk) clear_prefetched_high_word_q <= clear_prefetched_high_word;
\talways @* begin
\t\tclear_prefetched_high_word = clear_prefetched_high_word_q;
\t\tif (!prefetched_high_word)
\t\t\tclear_prefetched_high_word = 0;
\t\tif (latched_branch || irq_state || !resetn)
\t\t\tclear_prefetched_high_word = COMPRESSED_ISA;
\tend
\treg cpuregs_write;
\treg [31:0] cpuregs_wrdata;
\treg [31:0] cpuregs_rs1;
\treg [31:0] cpuregs_rs2;
\treg [regindex_bits-1:0] decoded_rs;
\talways @* begin
\t\tcpuregs_write = 0;
\t\tcpuregs_wrdata = \'bx;
\t\tif (cpu_state == cpu_state_fetch) begin
\t\t\t(* parallel_case *)
\t\t\tcase (1\'b1)
\t\t\t\tlatched_branch: begin
\t\t\t\t\tcpuregs_wrdata = reg_pc + (latched_compr ? 2 : 4);
\t\t\t\t\tcpuregs_write = 1;
\t\t\t\tend
\t\t\t\tlatched_store && !latched_branch: begin
\t\t\t\t\tcpuregs_wrdata = latched_stalu ? alu_out_q : reg_out;
\t\t\t\t\tcpuregs_write = 1;
\t\t\t\tend
\t\t\t\tENABLE_IRQ && irq_state[0]: begin
\t\t\t\t\tcpuregs_wrdata = reg_next_pc | latched_compr;
\t\t\t\t\tcpuregs_write = 1;
\t\t\t\tend
\t\t\t\tENABLE_IRQ && irq_state[1]: begin
\t\t\t\t\tcpuregs_wrdata = irq_pending & ~irq_mask;
\t\t\t\t\tcpuregs_write = 1;
\t\t\t\tend
\t\t\tendcase
\t\tend
\tend
`ifndef PICORV32_REGS
\talways @(posedge clk) begin
\t\tif (resetn && cpuregs_write && latched_rd)
\t\t\tcpuregs[latched_rd] <= cpuregs_wrdata;
\tend
\talways @* begin
\t\tdecoded_rs = \'bx;
\t\tif (ENABLE_REGS_DUALPORT) begin
`ifndef RISCV_FORMAL_BLACKBOX_REGS
\t\t\tcpuregs_rs1 = decoded_rs1 ? cpuregs[decoded_rs1] : 0;
\t\t\tcpuregs_rs2 = decoded_rs2 ? cpuregs[decoded_rs2] : 0;
`else
\t\t\tcpuregs_rs1 = decoded_rs1 ? $anyseq : 0;
\t\t\tcpuregs_rs2 = decoded_rs2 ? $anyseq : 0;
`endif
\t\tend else begin
\t\t\tdecoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
`ifndef RISCV_FORMAL_BLACKBOX_REGS
\t\t\tcpuregs_rs1 = decoded_rs ? cpuregs[decoded_rs] : 0;
`else
\t\t\tcpuregs_rs1 = decoded_rs ? $anyseq : 0;
`endif
\t\t\tcpuregs_rs2 = cpuregs_rs1;
\t\tend
\tend
`else
\twire[31:0] cpuregs_rdata1;
\twire[31:0] cpuregs_rdata2;
\twire [5:0] cpuregs_waddr = latched_rd;
\twire [5:0] cpuregs_raddr1 = ENABLE_REGS_DUALPORT ? decoded_rs1 : decoded_rs;
\twire [5:0] cpuregs_raddr2 = ENABLE_REGS_DUALPORT ? decoded_rs2 : 0;
\t`PICORV32_REGS cpuregs (
\t\t.clk(clk),
\t\t.wen(resetn && cpuregs_write && latched_rd),
\t\t.waddr(cpuregs_waddr),
\t\t.raddr1(cpuregs_raddr1),
\t\t.raddr2(cpuregs_raddr2),
\t\t.wdata(cpuregs_wrdata),
\t\t.rdata1(cpuregs_rdata1),
\t\t.rdata2(cpuregs_rdata2)
\t);
\talways @* begin
\t\tdecoded_rs = \'bx;
\t\tif (ENABLE_REGS_DUALPORT) begin
\t\t\tcpuregs_rs1 = decoded_rs1 ? cpuregs_rdata1 : 0;
\t\t\tcpuregs_rs2 = decoded_rs2 ? cpuregs_rdata2 : 0;
\t\tend else begin
\t\t\tdecoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
\t\t\tcpuregs_rs1 = decoded_rs ? cpuregs_rdata1 : 0;
\t\t\tcpuregs_rs2 = cpuregs_rs1;
\t\tend
\tend
`endif
\tassign launch_next_insn = cpu_state == cpu_state_fetch && decoder_trigger && (!ENABLE_IRQ || irq_delay || irq_active || !(irq_pending & ~irq_mask));
\talways @(posedge clk) begin
\t\ttrap <= 0;
\t\treg_sh <= \'bx;
\t\treg_out <= \'bx;
\t\tset_mem_do_rinst = 0;
\t\tset_mem_do_rdata = 0;
\t\tset_mem_do_wdata = 0;
\t\talu_out_0_q <= alu_out_0;
\t\talu_out_q <= alu_out;
\t\talu_wait <= 0;
\t\talu_wait_2 <= 0;
\t\tif (launch_next_insn) begin
\t\t\tdbg_rs1val <= \'bx;
\t\t\tdbg_rs2val <= \'bx;
\t\t\tdbg_rs1val_valid <= 0;
\t\t\tdbg_rs2val_valid <= 0;
\t\tend
\t\tif (WITH_PCPI && CATCH_ILLINSN) begin
\t\t\tif (resetn && pcpi_valid && !pcpi_int_wait) begin
\t\t\t\tif (pcpi_timeout_counter)
\t\t\t\t\tpcpi_timeout_counter <= pcpi_timeout_counter - 1;
\t\t\tend else
\t\t\t\tpcpi_timeout_counter <= ~0;
\t\t\tpcpi_timeout <= !pcpi_timeout_counter;
\t\tend
\t\tif (ENABLE_COUNTERS) begin
\t\t\tcount_cycle <= resetn ? count_cycle + 1 : 0;
\t\t\tif (!ENABLE_COUNTERS64) count_cycle[63:32] <= 0;
\t\tend else begin
\t\t\tcount_cycle <= \'bx;
\t\t\tcount_instr <= \'bx;
\t\tend
\t\tnext_irq_pending = ENABLE_IRQ ? irq_pending & LATCHED_IRQ : \'bx;
\t\tif (ENABLE_IRQ && ENABLE_IRQ_TIMER && timer) begin
\t\t\tif (timer - 1 == 0)
\t\t\t\tnext_irq_pending[irq_timer] = 1;
\t\t\ttimer <= timer - 1;
\t\tend
\t\tif (ENABLE_IRQ) begin
\t\t\tnext_irq_pending = next_irq_pending | irq;
\t\tend
\t\tdecoder_trigger <= mem_do_rinst && mem_done;
\t\tdecoder_trigger_q <= decoder_trigger;
\t\tdecoder_pseudo_trigger <= 0;
\t\tdecoder_pseudo_trigger_q <= decoder_pseudo_trigger;
\t\tdo_waitirq <= 0;
\t\ttrace_valid <= 0;
\t\tif (!ENABLE_TRACE)
\t\t\ttrace_data <= \'bx;
\t\tif (!resetn) begin
\t\t\treg_pc <= PROGADDR_RESET;
\t\t\treg_next_pc <= PROGADDR_RESET;
\t\t\tif (ENABLE_COUNTERS)
\t\t\t\tcount_instr <= 0;
\t\t\tlatched_store <= 0;
\t\t\tlatched_stalu <= 0;
\t\t\tlatched_branch <= 0;
\t\t\tlatched_trace <= 0;
\t\t\tlatched_is_lu <= 0;
\t\t\tlatched_is_lh <= 0;
\t\t\tlatched_is_lb <= 0;
\t\t\tpcpi_valid <= 0;
\t\t\tpcpi_timeout <= 0;
\t\t\tirq_active <= 0;
\t\t\tirq_delay <= 0;
\t\t\tirq_mask <= ~0;
\t\t\tnext_irq_pending = 0;
\t\t\tirq_state <= 0;
\t\t\teoi <= 0;
\t\t\ttimer <= 0;
\t\t\tif (~STACKADDR) begin
\t\t\t\tlatched_store <= 1;
\t\t\t\tlatched_rd <= 2;
\t\t\t\treg_out <= STACKADDR;
\t\t\tend
\t\t\tcpu_state <= cpu_state_fetch;
\t\tend else
\t\t(* parallel_case, full_case *)
\t\tcase (cpu_state)
\t\t\tcpu_state_trap: begin
\t\t\t\ttrap <= 1;
\t\t\tend
\t\t\tcpu_state_fetch: begin
\t\t\t\tmem_do_rinst <= !decoder_trigger && !do_waitirq;
\t\t\t\tmem_wordsize <= 0;
\t\t\t\tcurrent_pc = reg_next_pc;
\t\t\t\t(* parallel_case *)
\t\t\t\tcase (1\'b1)
\t\t\t\t\tlatched_branch: begin
\t\t\t\t\t\tcurrent_pc = latched_store ? (latched_stalu ? alu_out_q : reg_out) & ~1 : reg_next_pc;
\t\t\t\t\t\t`debug($display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + (latched_compr ? 2 : 4), current_pc);)
\t\t\t\t\tend
\t\t\t\t\tlatched_store && !latched_branch: begin
\t\t\t\t\t\t`debug($display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out);)
\t\t\t\t\tend
\t\t\t\t\tENABLE_IRQ && irq_state[0]: begin
\t\t\t\t\t\tcurrent_pc = PROGADDR_IRQ;
\t\t\t\t\t\tirq_active <= 1;
\t\t\t\t\t\tmem_do_rinst <= 1;
\t\t\t\t\tend
\t\t\t\t\tENABLE_IRQ && irq_state[1]: begin
\t\t\t\t\t\teoi <= irq_pending & ~irq_mask;
\t\t\t\t\t\tnext_irq_pending = next_irq_pending & irq_mask;
\t\t\t\t\tend
\t\t\t\tendcase
\t\t\t\tif (ENABLE_TRACE && latched_trace) begin
\t\t\t\t\tlatched_trace <= 0;
\t\t\t\t\ttrace_valid <= 1;
\t\t\t\t\tif (latched_branch)
\t\t\t\t\t\ttrace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_BRANCH | (current_pc & 32\'hfffffffe);
\t\t\t\t\telse
\t\t\t\t\t\ttrace_data <= (irq_active ? TRACE_IRQ : 0) | (latched_stalu ? alu_out_q : reg_out);
\t\t\t\tend
\t\t\t\treg_pc <= current_pc;
\t\t\t\treg_next_pc <= current_pc;
\t\t\t\tlatched_store <= 0;
\t\t\t\tlatched_stalu <= 0;
\t\t\t\tlatched_branch <= 0;
\t\t\t\tlatched_is_lu <= 0;
\t\t\t\tlatched_is_lh <= 0;
\t\t\t\tlatched_is_lb <= 0;
\t\t\t\tlatched_rd <= decoded_rd;
\t\t\t\tlatched_compr <= compressed_instr;
\t\t\t\tif (!delintreg && ENABLE_IRQ && ((decoder_trigger && !irq_active && !irq_delay && |(irq_pending & ~irq_mask)) || irq_state)) begin
\t\t\t\t\tirq_state <=
\t\t\t\t\t\tirq_state == 2\'b00 ? 2\'b01 :
\t\t\t\t\t\tirq_state == 2\'b01 ? 2\'b10 : 2\'b00;
\t\t\t\t\tlatched_compr <= latched_compr;
\t\t\t\t\tif (ENABLE_IRQ_QREGS)
\t\t\t\t\t\tlatched_rd <= irqregs_offset | irq_state[0];
\t\t\t\t\telse
\t\t\t\t\t latched_rd <= irq_state[0] ? 4 : 3;
\t\t\t\tend else begin
if (ENABLE_IRQ && ((decoder_trigger && !irq_active && |(irq_pending & ~irq_mask)) || irq_state)) begin
if(delintreg!=0) delintreg <= delintreg - 1;
end
if (ENABLE_IRQ && (decoder_trigger || do_waitirq) && instr_waitirq) begin
\t\t\t\t\tif (irq_pending) begin
\t\t\t\t\t\tlatched_store <= 1;
\t\t\t\t\t\treg_out <= irq_pending;
\t\t\t\t\t\treg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
\t\t\t\t\t\tmem_do_rinst <= 1;
\t\t\t\t\tend else
\t\t\t\t\t\tdo_waitirq <= 1;
\t\t\t\tend else
\t\t\t\tif (decoder_trigger) begin
\t\t\t\t\t`debug($display("-- %t", $time);)
\t\t\t\t\tirq_delay <= irq_active;
\t\t\t\t\treg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
\t\t\t\t\tif (ENABLE_TRACE)
\t\t\t\t\t\tlatched_trace <= 1;
\t\t\t\t\tif (ENABLE_COUNTERS) begin
\t\t\t\t\t\tcount_instr <= count_instr + 1;
\t\t\t\t\t\tif (!ENABLE_COUNTERS64) count_instr[63:32] <= 0;
\t\t\t\t\tend
\t\t\t\t\tif (instr_jal) begin
\t\t\t\t\t\tmem_do_rinst <= 1;
\t\t\t\t\t\treg_next_pc <= current_pc + decoded_imm_uj;
\t\t\t\t\t\tlatched_branch <= 1;
\t\t\t\t\tend else begin
\t\t\t\t\t\tmem_do_rinst <= 0;
\t\t\t\t\t\tmem_do_prefetch <= !instr_jalr && !instr_retirq;
\t\t\t\t\t\tcpu_state <= cpu_state_ld_rs1;
\t\t\t\t\tend
\t\t\t\tend
end
\t\t\tend
\t\t\tcpu_state_ld_rs1: begin
\t\t\t\treg_op1 <= \'bx;
\t\t\t\treg_op2 <= \'bx;
\t\t\t\t(* parallel_case *)
\t\t\t\tcase (1\'b1)
\t\t\t\t\t(CATCH_ILLINSN || WITH_PCPI) && instr_trap: begin
\t\t\t\t\t\tif (WITH_PCPI) begin
\t\t\t\t\t\t\t`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
\t\t\t\t\t\t\treg_op1 <= cpuregs_rs1;
\t\t\t\t\t\t\tdbg_rs1val <= cpuregs_rs1;
\t\t\t\t\t\t\tdbg_rs1val_valid <= 1;
\t\t\t\t\t\t\tif (ENABLE_REGS_DUALPORT) begin
\t\t\t\t\t\t\t\tpcpi_valid <= 1;
\t\t\t\t\t\t\t\t`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
\t\t\t\t\t\t\t\treg_sh <= cpuregs_rs2;
\t\t\t\t\t\t\t\treg_op2 <= cpuregs_rs2;
\t\t\t\t\t\t\t\tdbg_rs2val <= cpuregs_rs2;
\t\t\t\t\t\t\t\tdbg_rs2val_valid <= 1;
\t\t\t\t\t\t\t\tif (pcpi_int_ready) begin
\t\t\t\t\t\t\t\t\tmem_do_rinst <= 1;
\t\t\t\t\t\t\t\t\tpcpi_valid <= 0;
\t\t\t\t\t\t\t\t\treg_out <= pcpi_int_rd;
\t\t\t\t\t\t\t\t\tlatched_store <= pcpi_int_wr;
\t\t\t\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\t\t\t\tend else
\t\t\t\t\t\t\t\tif (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin
\t\t\t\t\t\t\t\t\tpcpi_valid <= 0;
\t\t\t\t\t\t\t\t\t`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
\t\t\t\t\t\t\t\t\tif (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
\t\t\t\t\t\t\t\t\t\tnext_irq_pending[irq_ebreak] = 1;
\t\t\t\t\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\t\t\t\t\tend else
\t\t\t\t\t\t\t\t\t\tcpu_state <= cpu_state_trap;
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tend else begin
\t\t\t\t\t\t\t\tcpu_state <= cpu_state_ld_rs2;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend else begin
\t\t\t\t\t\t\t`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
\t\t\t\t\t\t\tif (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
\t\t\t\t\t\t\t\tnext_irq_pending[irq_ebreak] = 1;
\t\t\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\t\t\tend else
\t\t\t\t\t\t\t\tcpu_state <= cpu_state_trap;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\t\tENABLE_COUNTERS && is_rdcycle_rdcycleh_rdinstr_rdinstrh: begin
\t\t\t\t\t\t(* parallel_case, full_case *)
\t\t\t\t\t\tcase (1\'b1)
\t\t\t\t\t\t\tinstr_rdcycle:
\t\t\t\t\t\t\t\treg_out <= count_cycle[31:0];
\t\t\t\t\t\t\tinstr_rdcycleh && ENABLE_COUNTERS64:
\t\t\t\t\t\t\t\treg_out <= count_cycle[63:32];
\t\t\t\t\t\t\tinstr_rdinstr:
\t\t\t\t\t\t\t\treg_out <= count_instr[31:0];
\t\t\t\t\t\t\tinstr_rdinstrh && ENABLE_COUNTERS64:
\t\t\t\t\t\t\t\treg_out <= count_instr[63:32];
\t\t\t\t\t\tendcase
\t\t\t\t\t\tlatched_store <= 1;
\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\tend
\t\t\t\t\tis_lui_auipc_jal: begin
\t\t\t\t\t\treg_op1 <= instr_lui ? 0 : reg_pc;
\t\t\t\t\t\treg_op2 <= decoded_imm;
\t\t\t\t\t\tif (TWO_CYCLE_ALU)
\t\t\t\t\t\t\talu_wait <= 1;
\t\t\t\t\t\telse
\t\t\t\t\t\t\tmem_do_rinst <= mem_do_prefetch;
\t\t\t\t\t\tcpu_state <= cpu_state_exec;
\t\t\t\t\tend
\t\t\t\t\tENABLE_IRQ && ENABLE_IRQ_QREGS && instr_getq: begin
\t\t\t\t\t\t`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
\t\t\t\t\t\treg_out <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val_valid <= 1;
\t\t\t\t\t\tlatched_store <= 1;
\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\tend
\t\t\t\t\tENABLE_IRQ && ENABLE_IRQ_QREGS && instr_setq: begin
\t\t\t\t\t\t`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
\t\t\t\t\t\treg_out <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val_valid <= 1;
\t\t\t\t\t\tlatched_rd <= latched_rd | irqregs_offset;
\t\t\t\t\t\tlatched_store <= 1;
\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\tend
ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_delint: begin
\t\t\t\t\t\t`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, decoded_rs1 ? cpuregs[decoded_rs1] : 0);)
\t\t\t\t\t\tdelintreg <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\tend
\t\t\t\t\tENABLE_IRQ && instr_retirq: begin
\t\t\t\t\t\teoi <= 0;
\t\t\t\t\t\tirq_active <= 0;
\t\t\t\t\t\tlatched_branch <= 1;
\t\t\t\t\t\tlatched_store <= 1;
\t\t\t\t\t\t`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
\t\t\t\t\t\treg_out <= CATCH_MISALIGN ? (cpuregs_rs1 & 32\'h fffffffe) : cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val_valid <= 1;
\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\tend
\t\t\t\t\tENABLE_IRQ && instr_maskirq: begin
\t\t\t\t\t\tlatched_store <= 1;
\t\t\t\t\t\treg_out <= irq_mask;
\t\t\t\t\t\t`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
\t\t\t\t\t\tirq_mask <= cpuregs_rs1 | MASKED_IRQ;
\t\t\t\t\t\tdbg_rs1val <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val_valid <= 1;
\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\tend
\t\t\t\t\tENABLE_IRQ && ENABLE_IRQ_TIMER && instr_timer: begin
\t\t\t\t\t\tlatched_store <= 1;
\t\t\t\t\t\treg_out <= timer;
\t\t\t\t\t\t`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
\t\t\t\t\t\ttimer <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val_valid <= 1;
\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\tend
\t\t\t\t\tis_lb_lh_lw_lbu_lhu && !instr_trap: begin
\t\t\t\t\t\t`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
\t\t\t\t\t\treg_op1 <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val_valid <= 1;
\t\t\t\t\t\tcpu_state <= cpu_state_ldmem;
\t\t\t\t\t\tmem_do_rinst <= 1;
\t\t\t\t\tend
\t\t\t\t\tis_slli_srli_srai && !BARREL_SHIFTER: begin
\t\t\t\t\t\t`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
\t\t\t\t\t\treg_op1 <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val_valid <= 1;
\t\t\t\t\t\treg_sh <= decoded_rs2;
\t\t\t\t\t\tcpu_state <= cpu_state_shift;
\t\t\t\t\tend
\t\t\t\t\tis_jalr_addi_slti_sltiu_xori_ori_andi, is_slli_srli_srai && BARREL_SHIFTER: begin
\t\t\t\t\t\t`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
\t\t\t\t\t\treg_op1 <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val_valid <= 1;
\t\t\t\t\t\treg_op2 <= is_slli_srli_srai && BARREL_SHIFTER ? decoded_rs2 : decoded_imm;
\t\t\t\t\t\tif (TWO_CYCLE_ALU)
\t\t\t\t\t\t\talu_wait <= 1;
\t\t\t\t\t\telse
\t\t\t\t\t\t\tmem_do_rinst <= mem_do_prefetch;
\t\t\t\t\t\tcpu_state <= cpu_state_exec;
\t\t\t\t\tend
\t\t\t\t\tdefault: begin
\t\t\t\t\t\t`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
\t\t\t\t\t\treg_op1 <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val_valid <= 1;
\t\t\t\t\t\tif (ENABLE_REGS_DUALPORT) begin
\t\t\t\t\t\t\t`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
\t\t\t\t\t\t\treg_sh <= cpuregs_rs2;
\t\t\t\t\t\t\treg_op2 <= cpuregs_rs2;
\t\t\t\t\t\t\tdbg_rs2val <= cpuregs_rs2;
\t\t\t\t\t\t\tdbg_rs2val_valid <= 1;
\t\t\t\t\t\t\t(* parallel_case *)
\t\t\t\t\t\t\tcase (1\'b1)
\t\t\t\t\t\t\t\tis_sb_sh_sw: begin
\t\t\t\t\t\t\t\t\tcpu_state <= cpu_state_stmem;
\t\t\t\t\t\t\t\t\tmem_do_rinst <= 1;
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\tis_sll_srl_sra && !BARREL_SHIFTER: begin
\t\t\t\t\t\t\t\t\tcpu_state <= cpu_state_shift;
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\tdefault: begin
\t\t\t\t\t\t\t\t\tif (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
\t\t\t\t\t\t\t\t\t\talu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
\t\t\t\t\t\t\t\t\t\talu_wait <= 1;
\t\t\t\t\t\t\t\t\tend else
\t\t\t\t\t\t\t\t\t\tmem_do_rinst <= mem_do_prefetch;
\t\t\t\t\t\t\t\t\tcpu_state <= cpu_state_exec;
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tendcase
\t\t\t\t\t\tend else
\t\t\t\t\t\t\tcpu_state <= cpu_state_ld_rs2;
\t\t\t\t\tend
\t\t\t\tendcase
\t\t\tend
\t\t\tcpu_state_ld_rs2: begin
\t\t\t\t`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
\t\t\t\treg_sh <= cpuregs_rs2;
\t\t\t\treg_op2 <= cpuregs_rs2;
\t\t\t\tdbg_rs2val <= cpuregs_rs2;
\t\t\t\tdbg_rs2val_valid <= 1;
\t\t\t\t(* parallel_case *)
\t\t\t\tcase (1\'b1)
\t\t\t\t\tWITH_PCPI && instr_trap: begin
\t\t\t\t\t\tpcpi_valid <= 1;
\t\t\t\t\t\tif (pcpi_int_ready) begin
\t\t\t\t\t\t\tmem_do_rinst <= 1;
\t\t\t\t\t\t\tpcpi_valid <= 0;
\t\t\t\t\t\t\treg_out <= pcpi_int_rd;
\t\t\t\t\t\t\tlatched_store <= pcpi_int_wr;
\t\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\t\tend else
\t\t\t\t\t\tif (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin
\t\t\t\t\t\t\tpcpi_valid <= 0;
\t\t\t\t\t\t\t`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
\t\t\t\t\t\t\tif (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
\t\t\t\t\t\t\t\tnext_irq_pending[irq_ebreak] = 1;
\t\t\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\t\t\tend else
\t\t\t\t\t\t\t\tcpu_state <= cpu_state_trap;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\t\tis_sb_sh_sw: begin
\t\t\t\t\t\tcpu_state <= cpu_state_stmem;
\t\t\t\t\t\tmem_do_rinst <= 1;
\t\t\t\t\tend
\t\t\t\t\tis_sll_srl_sra && !BARREL_SHIFTER: begin
\t\t\t\t\t\tcpu_state <= cpu_state_shift;
\t\t\t\t\tend
\t\t\t\t\tdefault: begin
\t\t\t\t\t\tif (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
\t\t\t\t\t\t\talu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
\t\t\t\t\t\t\talu_wait <= 1;
\t\t\t\t\t\tend else
\t\t\t\t\t\t\tmem_do_rinst <= mem_do_prefetch;
\t\t\t\t\t\tcpu_state <= cpu_state_exec;
\t\t\t\t\tend
\t\t\t\tendcase
\t\t\tend
\t\t\tcpu_state_exec: begin
\t\t\t\treg_out <= reg_pc + decoded_imm;
\t\t\t\tif ((TWO_CYCLE_ALU || TWO_CYCLE_COMPARE) && (alu_wait || alu_wait_2)) begin
\t\t\t\t\tmem_do_rinst <= mem_do_prefetch && !alu_wait_2;
\t\t\t\t\talu_wait <= alu_wait_2;
\t\t\t\tend else
\t\t\t\tif (is_beq_bne_blt_bge_bltu_bgeu) begin
\t\t\t\t\tlatched_rd <= 0;
\t\t\t\t\tlatched_store <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
\t\t\t\t\tlatched_branch <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
\t\t\t\t\tif (mem_done)
\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\tif (TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0) begin
\t\t\t\t\t\tdecoder_trigger <= 0;
\t\t\t\t\t\tset_mem_do_rinst = 1;
\t\t\t\t\tend
\t\t\t\tend else begin
\t\t\t\t\tlatched_branch <= instr_jalr;
\t\t\t\t\tlatched_store <= 1;
\t\t\t\t\tlatched_stalu <= 1;
\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\tend
\t\t\tend
\t\t\tcpu_state_shift: begin
\t\t\t\tlatched_store <= 1;
\t\t\t\tif (reg_sh == 0) begin
\t\t\t\t\treg_out <= reg_op1;
\t\t\t\t\tmem_do_rinst <= mem_do_prefetch;
\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\tend else if (TWO_STAGE_SHIFT && reg_sh >= 4) begin
\t\t\t\t\t(* parallel_case, full_case *)
\t\t\t\t\tcase (1\'b1)
\t\t\t\t\t\tinstr_slli || instr_sll: reg_op1 <= reg_op1 << 4;
\t\t\t\t\t\tinstr_srli || instr_srl: reg_op1 <= reg_op1 >> 4;
\t\t\t\t\t\tinstr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 4;
\t\t\t\t\tendcase
\t\t\t\t\treg_sh <= reg_sh - 4;
\t\t\t\tend else begin
\t\t\t\t\t(* parallel_case, full_case *)
\t\t\t\t\tcase (1\'b1)
\t\t\t\t\t\tinstr_slli || instr_sll: reg_op1 <= reg_op1 << 1;
\t\t\t\t\t\tinstr_srli || instr_srl: reg_op1 <= reg_op1 >> 1;
\t\t\t\t\t\tinstr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 1;
\t\t\t\t\tendcase
\t\t\t\t\treg_sh <= reg_sh - 1;
\t\t\t\tend
\t\t\tend
\t\t\tcpu_state_stmem: begin
\t\t\t\tif (ENABLE_TRACE)
\t\t\t\t\treg_out <= reg_op2;
\t\t\t\tif (!mem_do_prefetch || mem_done) begin
\t\t\t\t\tif (!mem_do_wdata) begin
\t\t\t\t\t\t(* parallel_case, full_case *)
\t\t\t\t\t\tcase (1\'b1)
\t\t\t\t\t\t\tinstr_sb: mem_wordsize <= 2;
\t\t\t\t\t\t\tinstr_sh: mem_wordsize <= 1;
\t\t\t\t\t\t\tinstr_sw: mem_wordsize <= 0;
\t\t\t\t\t\tendcase
\t\t\t\t\t\tif (ENABLE_TRACE) begin
\t\t\t\t\t\t\ttrace_valid <= 1;
\t\t\t\t\t\t\ttrace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32\'hffffffff);
\t\t\t\t\t\tend
\t\t\t\t\t\treg_op1 <= reg_op1 + decoded_imm;
\t\t\t\t\t\tset_mem_do_wdata = 1;
\t\t\t\t\tend
\t\t\t\t\tif (!mem_do_prefetch && mem_done) begin
\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\t\tdecoder_trigger <= 1;
\t\t\t\t\t\tdecoder_pseudo_trigger <= 1;
\t\t\t\t\tend
\t\t\t\tend
\t\t\tend
\t\t\tcpu_state_ldmem: begin
\t\t\t\tlatched_store <= 1;
\t\t\t\tif (!mem_do_prefetch || mem_done) begin
\t\t\t\t\tif (!mem_do_rdata) begin
\t\t\t\t\t\t(* parallel_case, full_case *)
\t\t\t\t\t\tcase (1\'b1)
\t\t\t\t\t\t\tinstr_lb || instr_lbu: mem_wordsize <= 2;
\t\t\t\t\t\t\tinstr_lh || instr_lhu: mem_wordsize <= 1;
\t\t\t\t\t\t\tinstr_lw: mem_wordsize <= 0;
\t\t\t\t\t\tendcase
\t\t\t\t\t\tlatched_is_lu <= is_lbu_lhu_lw;
\t\t\t\t\t\tlatched_is_lh <= instr_lh;
\t\t\t\t\t\tlatched_is_lb <= instr_lb;
\t\t\t\t\t\tif (ENABLE_TRACE) begin
\t\t\t\t\t\t\ttrace_valid <= 1;
\t\t\t\t\t\t\ttrace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32\'hffffffff);
\t\t\t\t\t\tend
\t\t\t\t\t\treg_op1 <= reg_op1 + decoded_imm;
\t\t\t\t\t\tset_mem_do_rdata = 1;
\t\t\t\t\tend
\t\t\t\t\tif (!mem_do_prefetch && mem_done) begin
\t\t\t\t\t\t(* parallel_case, full_case *)
\t\t\t\t\t\tcase (1\'b1)
\t\t\t\t\t\t\tlatched_is_lu: reg_out <= mem_rdata_word;
\t\t\t\t\t\t\tlatched_is_lh: reg_out <= $signed(mem_rdata_word[15:0]);
\t\t\t\t\t\t\tlatched_is_lb: reg_out <= $signed(mem_rdata_word[7:0]);
\t\t\t\t\t\tendcase
\t\t\t\t\t\tdecoder_trigger <= 1;
\t\t\t\t\t\tdecoder_pseudo_trigger <= 1;
\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\tend
\t\t\t\tend
\t\t\tend
\t\tendcase
\t\tif (CATCH_MISALIGN && resetn && (mem_do_rdata || mem_do_wdata)) begin
\t\t\tif (mem_wordsize == 0 && reg_op1[1:0] != 0) begin
\t\t\t\t`debug($display("MISALIGNED WORD: 0x%08x", reg_op1);)
\t\t\t\tif (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
\t\t\t\t\tnext_irq_pending[irq_buserror] = 1;
\t\t\t\tend else
\t\t\t\t\tcpu_state <= cpu_state_trap;
\t\t\tend
\t\t\tif (mem_wordsize == 1 && reg_op1[0] != 0) begin
\t\t\t\t`debug($display("MISALIGNED HALFWORD: 0x%08x", reg_op1);)
\t\t\t\tif (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
\t\t\t\t\tnext_irq_pending[irq_buserror] = 1;
\t\t\t\tend else
\t\t\t\t\tcpu_state <= cpu_state_trap;
\t\t\tend
\t\tend
\t\tif (CATCH_MISALIGN && resetn && mem_do_rinst && (COMPRESSED_ISA ? reg_pc[0] : |reg_pc[1:0])) begin
\t\t\t`debug($display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);)
\t\t\tif (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
\t\t\t\tnext_irq_pending[irq_buserror] = 1;
\t\t\tend else
\t\t\t\tcpu_state <= cpu_state_trap;
\t\tend
\t\tif (!CATCH_ILLINSN && decoder_trigger_q && !decoder_pseudo_trigger_q && instr_ecall_ebreak) begin
\t\t\tcpu_state <= cpu_state_trap;
\t\tend
\t\tif (!resetn || mem_done) begin
\t\t\tmem_do_prefetch <= 0;
\t\t\tmem_do_rinst <= 0;
\t\t\tmem_do_rdata <= 0;
\t\t\tmem_do_wdata <= 0;
\t\tend
\t\tif (set_mem_do_rinst)
\t\t\tmem_do_rinst <= 1;
\t\tif (set_mem_do_rdata)
\t\t\tmem_do_rdata <= 1;
\t\tif (set_mem_do_wdata)
\t\t\tmem_do_wdata <= 1;
\t\tirq_pending <= next_irq_pending & ~MASKED_IRQ;
\t\tif (!CATCH_MISALIGN) begin
\t\t\tif (COMPRESSED_ISA) begin
\t\t\t\treg_pc[0] <= 0;
\t\t\t\treg_next_pc[0] <= 0;
\t\t\tend else begin
\t\t\t\treg_pc[1:0] <= 0;
\t\t\t\treg_next_pc[1:0] <= 0;
\t\t\tend
\t\tend
\t\tcurrent_pc = \'bx;
\tend
`ifdef RISCV_FORMAL
\treg dbg_irq_call;
\treg dbg_irq_enter;
\treg [31:0] dbg_irq_ret;
\talways @(posedge clk) begin
\t\trvfi_valid <= resetn && (launch_next_insn || trap) && dbg_valid_insn;
\t\trvfi_order <= resetn ? rvfi_order + rvfi_valid : 0;
\t\trvfi_insn <= dbg_insn_opcode;
\t\trvfi_rs1_addr <= dbg_rs1val_valid ? dbg_insn_rs1 : 0;
\t\trvfi_rs2_addr <= dbg_rs2val_valid ? dbg_insn_rs2 : 0;
\t\trvfi_pc_rdata <= dbg_insn_addr;
\t\trvfi_rs1_rdata <= dbg_rs1val_valid ? dbg_rs1val : 0;
\t\trvfi_rs2_rdata <= dbg_rs2val_valid ? dbg_rs2val : 0;
\t\trvfi_trap <= trap;
\t\trvfi_halt <= trap;
\t\trvfi_intr <= dbg_irq_enter;
\t\tif (!resetn) begin
\t\t\tdbg_irq_call <= 0;
\t\t\tdbg_irq_enter <= 0;
\t\tend else
\t\tif (rvfi_valid) begin
\t\t\tdbg_irq_call <= 0;
\t\t\tdbg_irq_enter <= dbg_irq_call;
\t\tend else
\t\tif (irq_state == 1) begin
\t\t\tdbg_irq_call <= 1;
\t\t\tdbg_irq_ret <= next_pc;
\t\tend
\t\tif (!resetn) begin
\t\t\trvfi_rd_addr <= 0;
\t\t\trvfi_rd_wdata <= 0;
\t\tend else
\t\tif (cpuregs_write && !irq_state) begin
\t\t\trvfi_rd_addr <= latched_rd;
\t\t\trvfi_rd_wdata <= latched_rd ? cpuregs_wrdata : 0;
\t\tend else
\t\tif (rvfi_valid) begin
\t\t\trvfi_rd_addr <= 0;
\t\t\trvfi_rd_wdata <= 0;
\t\tend
\t\tcasez (dbg_insn_opcode)
\t\t\t32\'b 0000000_?????_000??_???_?????_0001011: begin // getq
\t\t\t\trvfi_rs1_addr <= 0;
\t\t\t\trvfi_rs1_rdata <= 0;
\t\t\tend
\t\t\t32\'b 0000001_?????_?????_???_000??_0001011: begin // setq
\t\t\t\trvfi_rd_addr <= 0;
\t\t\t\trvfi_rd_wdata <= 0;
\t\t\tend
\t\t\t32\'b 0000010_?????_00000_???_00000_0001011: begin // retirq
\t\t\t\trvfi_rs1_addr <= 0;
\t\t\t\trvfi_rs1_rdata <= 0;
\t\t\tend
\t\tendcase
\t\tif (!dbg_irq_call) begin
\t\t\tif (dbg_mem_instr) begin
\t\t\t\trvfi_mem_addr <= 0;
\t\t\t\trvfi_mem_rmask <= 0;
\t\t\t\trvfi_mem_wmask <= 0;
\t\t\t\trvfi_mem_rdata <= 0;
\t\t\t\trvfi_mem_wdata <= 0;
\t\t\tend else
\t\t\tif (dbg_mem_valid && dbg_mem_ready) begin
\t\t\t\trvfi_mem_addr <= dbg_mem_addr;
\t\t\t\trvfi_mem_rmask <= dbg_mem_wstrb ? 0 : ~0;
\t\t\t\trvfi_mem_wmask <= dbg_mem_wstrb;
\t\t\t\trvfi_mem_rdata <= dbg_mem_rdata;
\t\t\t\trvfi_mem_wdata <= dbg_mem_wdata;
\t\t\tend
\t\tend
\tend
\talways @* begin
\t\trvfi_pc_wdata = dbg_irq_call ? dbg_irq_ret : dbg_insn_addr;
\tend
`endif
\t// Formal Verification
`ifdef FORMAL
\treg [3:0] last_mem_nowait;
\talways @(posedge clk)
\t\tlast_mem_nowait <= {last_mem_nowait, mem_ready || !mem_valid};
\t// stall the memory interface for max 4 cycles
\trestrict property (|last_mem_nowait || mem_ready || !mem_valid);
\t// resetn low in first cycle, after that resetn high
\trestrict property (resetn != $initstate);
\t// this just makes it much easier to read traces. uncomment as needed.
\t// assume property (mem_valid || !mem_ready);
\treg ok;
\talways @* begin
\t\tif (resetn) begin
\t\t\t// instruction fetches are read-only
\t\t\tif (mem_valid && mem_instr)
\t\t\t\tassert (mem_wstrb == 0);
\t\t\t// cpu_state must be valid
\t\t\tok = 0;
\t\t\tif (cpu_state == cpu_state_trap) ok = 1;
\t\t\tif (cpu_state == cpu_state_fetch) ok = 1;
\t\t\tif (cpu_state == cpu_state_ld_rs1) ok = 1;
\t\t\tif (cpu_state == cpu_state_ld_rs2) ok = !ENABLE_REGS_DUALPORT;
\t\t\tif (cpu_state == cpu_state_exec) ok = 1;
\t\t\tif (cpu_state == cpu_state_shift) ok = 1;
\t\t\tif (cpu_state == cpu_state_stmem) ok = 1;
\t\t\tif (cpu_state == cpu_state_ldmem) ok = 1;
\t\t\tassert (ok);
\t\tend
\tend
\treg last_mem_la_read = 0;
\treg last_mem_la_write = 0;
\treg [31:0] last_mem_la_addr;
\treg [31:0] last_mem_la_wdata;
\treg [3:0] last_mem_la_wstrb = 0;
\talways @(posedge clk) begin
\t\tlast_mem_la_read <= mem_la_read;
\t\tlast_mem_la_write <= mem_la_write;
\t\tlast_mem_la_addr <= mem_la_addr;
\t\tlast_mem_la_wdata <= mem_la_wdata;
\t\tlast_mem_la_wstrb <= mem_la_wstrb;
\t\tif (last_mem_la_read) begin
\t\t\tassert(mem_valid);
\t\t\tassert(mem_addr == last_mem_la_addr);
\t\t\tassert(mem_wstrb == 0);
\t\tend
\t\tif (last_mem_la_write) begin
\t\t\tassert(mem_valid);
\t\t\tassert(mem_addr == last_mem_la_addr);
\t\t\tassert(mem_wdata == last_mem_la_wdata);
\t\t\tassert(mem_wstrb == last_mem_la_wstrb);
\t\tend
\t\tif (mem_la_read || mem_la_write) begin
\t\t\tassert(!mem_valid || mem_ready);
\t\tend
\tend
`endif
endmodule
// This is a simple example implementation of PICORV32_REGS.
// Use the PICORV32_REGS mechanism if you want to use custom
// memory resources to implement the processor register file.
// Note that your implementation must match the requirements of
// the PicoRV32 configuration. (e.g. QREGS, etc)
module picorv32_regs (
\tinput clk, wen,
\tinput [5:0] waddr,
\tinput [5:0] raddr1,
\tinput [5:0] raddr2,
\tinput [31:0] wdata,
\toutput [31:0] rdata1,
\toutput [31:0] rdata2
);
\treg [31:0] regs [0:30];
\talways @(posedge clk)
\t\tif (wen) regs[~waddr[4:0]] <= wdata;
\tassign rdata1 = regs[~raddr1[4:0]];
\tassign rdata2 = regs[~raddr2[4:0]];
endmodule
/***************************************************************
* picorv32_pcpi_mul
***************************************************************/
module picorv32_pcpi_mul #(
\tparameter STEPS_AT_ONCE = 1,
\tparameter CARRY_CHAIN = 4
) (
\tinput clk, resetn,
\tinput pcpi_valid,
\tinput [31:0] pcpi_insn,
\tinput [31:0] pcpi_rs1,
\tinput [31:0] pcpi_rs2,
\toutput reg pcpi_wr,
\toutput reg [31:0] pcpi_rd,
\toutput reg pcpi_wait,
\toutput reg pcpi_ready
);
\treg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu;
\twire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu};
\twire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu};
\twire instr_rs1_signed = |{instr_mulh, instr_mulhsu};
\twire instr_rs2_signed = |{instr_mulh};
\treg pcpi_wait_q;
\twire mul_start = pcpi_wait && !pcpi_wait_q;
\talways @(posedge clk) begin
\t\tinstr_mul <= 0;
\t\tinstr_mulh <= 0;
\t\tinstr_mulhsu <= 0;
\t\tinstr_mulhu <= 0;
\t\tif (resetn && pcpi_valid && pcpi_insn[6:0] == 7\'b0110011 && pcpi_insn[31:25] == 7\'b0000001) begin
\t\t\tcase (pcpi_insn[14:12])
\t\t\t\t3\'b000: instr_mul <= 1;
\t\t\t\t3\'b001: instr_mulh <= 1;
\t\t\t\t3\'b010: instr_mulhsu <= 1;
\t\t\t\t3\'b011: instr_mulhu <= 1;
\t\t\tendcase
\t\tend
\t\tpcpi_wait <= instr_any_mul;
\t\tpcpi_wait_q <= pcpi_wait;
\tend
\treg [63:0] rs1, rs2, rd, rdx;
\treg [63:0] next_rs1, next_rs2, this_rs2;
\treg [63:0] next_rd, next_rdx, next_rdt;
\treg [6:0] mul_counter;
\treg mul_waiting;
\treg mul_finish;
\tinteger i, j;
\t// carry save accumulator
\talways @* begin
\t\tnext_rd = rd;
\t\tnext_rdx = rdx;
\t\tnext_rs1 = rs1;
\t\tnext_rs2 = rs2;
\t\tfor (i = 0; i < STEPS_AT_ONCE; i=i+1) begin
\t\t\tthis_rs2 = next_rs1[0] ? next_rs2 : 0;
\t\t\tif (CARRY_CHAIN == 0) begin
\t\t\t\tnext_rdt = next_rd ^ next_rdx ^ this_rs2;
\t\t\t\tnext_rdx = ((next_rd & next_rdx) | (next_rd & this_rs2) | (next_rdx & this_rs2)) << 1;
\t\t\t\tnext_rd = next_rdt;
\t\t\tend else begin
\t\t\t\tnext_rdt = 0;
\t\t\t\tfor (j = 0; j < 64; j = j + CARRY_CHAIN)
\t\t\t\t\t{next_rdt[j+CARRY_CHAIN-1], next_rd[j +: CARRY_CHAIN]} =
\t\t\t\t\t\t\tnext_rd[j +: CARRY_CHAIN] + next_rdx[j +: CARRY_CHAIN] + this_rs2[j +: CARRY_CHAIN];
\t\t\t\tnext_rdx = next_rdt << 1;
\t\t\tend
\t\t\tnext_rs1 = next_rs1 >> 1;
\t\t\tnext_rs2 = next_rs2 << 1;
\t\tend
\tend
\talways @(posedge clk) begin
\t\tmul_finish <= 0;
\t\tif (!resetn) begin
\t\t\tmul_waiting <= 1;
\t\tend else
\t\tif (mul_waiting) begin
\t\t\tif (instr_rs1_signed)
\t\t\t\trs1 <= $signed(pcpi_rs1);
\t\t\telse
\t\t\t\trs1 <= $unsigned(pcpi_rs1);
\t\t\tif (instr_rs2_signed)
\t\t\t\trs2 <= $signed(pcpi_rs2);
\t\t\telse
\t\t\t\trs2 <= $unsigned(pcpi_rs2);
\t\t\trd <= 0;
\t\t\trdx <= 0;
\t\t\tmul_counter <= (instr_any_mulh ? 63 - STEPS_AT_ONCE : 31 - STEPS_AT_ONCE);
\t\t\tmul_waiting <= !mul_start;
\t\tend else begin
\t\t\trd <= next_rd;
\t\t\trdx <= next_rdx;
\t\t\trs1 <= next_rs1;
\t\t\trs2 <= next_rs2;
\t\t\tmul_counter <= mul_counter - STEPS_AT_ONCE;
\t\t\tif (mul_counter[6]) begin
\t\t\t\tmul_finish <= 1;
\t\t\t\tmul_waiting <= 1;
\t\t\tend
\t\tend
\tend
\talways @(posedge clk) begin
\t\tpcpi_wr <= 0;
\t\tpcpi_ready <= 0;
\t\tif (mul_finish && resetn) begin
\t\t\tpcpi_wr <= 1;
\t\t\tpcpi_ready <= 1;
\t\t\tpcpi_rd <= instr_any_mulh ? rd >> 32 : rd;
\t\tend
\tend
endmodule
module picorv32_pcpi_fast_mul #(
\tparameter EXTRA_MUL_FFS = 0,
\tparameter EXTRA_INSN_FFS = 0,
\tparameter MUL_CLKGATE = 0
) (
\tinput clk, resetn,
\tinput pcpi_valid,
\tinput [31:0] pcpi_insn,
\tinput [31:0] pcpi_rs1,
\tinput [31:0] pcpi_rs2,
\toutput pcpi_wr,
\toutput [31:0] pcpi_rd,
\toutput pcpi_wait,
\toutput pcpi_ready
);
\treg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu;
\twire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu};
\twire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu};
\twire instr_rs1_signed = |{instr_mulh, instr_mulhsu};
\twire instr_rs2_signed = |{instr_mulh};
\treg shift_out;
\treg [3:0] active;
\treg [32:0] rs1, rs2, rs1_q, rs2_q;
\treg [63:0] rd, rd_q;
\twire pcpi_insn_valid = pcpi_valid && pcpi_insn[6:0] == 7\'b0110011 && pcpi_insn[31:25] == 7\'b0000001;
\treg pcpi_insn_valid_q;
\talways @* begin
\t\tinstr_mul = 0;
\t\tinstr_mulh = 0;
\t\tinstr_mulhsu = 0;
\t\tinstr_mulhu = 0;
\t\tif (resetn && (EXTRA_INSN_FFS ? pcpi_insn_valid_q : pcpi_insn_valid)) begin
\t\t\tcase (pcpi_insn[14:12])
\t\t\t\t3\'b000: instr_mul = 1;
\t\t\t\t3\'b001: instr_mulh = 1;
\t\t\t\t3\'b010: instr_mulhsu = 1;
\t\t\t\t3\'b011: instr_mulhu = 1;
\t\t\tendcase
\t\tend
\tend
\talways @(posedge clk) begin
\t\tpcpi_insn_valid_q <= pcpi_insn_valid;
\t\tif (!MUL_CLKGATE || active[0]) begin
\t\t\trs1_q <= rs1;
\t\t\trs2_q <= rs2;
\t\tend
\t\tif (!MUL_CLKGATE || active[1]) begin
\t\t\trd <= $signed(EXTRA_MUL_FFS ? rs1_q : rs1) * $signed(EXTRA_MUL_FFS ? rs2_q : rs2);
\t\tend
\t\tif (!MUL_CLKGATE || active[2]) begin
\t\t\trd_q <= rd;
\t\tend
\tend
\talways @(posedge clk) begin
\t\tif (instr_any_mul && !(EXTRA_MUL_FFS ? active[3:0] : active[1:0])) begin
\t\t\tif (instr_rs1_signed)
\t\t\t\trs1 <= $signed(pcpi_rs1);
\t\t\telse
\t\t\t\trs1 <= $unsigned(pcpi_rs1);
\t\t\tif (instr_rs2_signed)
\t\t\t\trs2 <= $signed(pcpi_rs2);
\t\t\telse
\t\t\t\trs2 <= $unsigned(pcpi_rs2);
\t\t\tactive[0] <= 1;
\t\tend else begin
\t\t\tactive[0] <= 0;
\t\tend
\t\tactive[3:1] <= active;
\t\tshift_out <= instr_any_mulh;
\t\tif (!resetn)
\t\t\tactive <= 0;
\tend
\tassign pcpi_wr = active[EXTRA_MUL_FFS ? 3 : 1];
\tassign pcpi_wait = 0;
\tassign pcpi_ready = active[EXTRA_MUL_FFS ? 3 : 1];
`ifdef RISCV_FORMAL_ALTOPS
\tassign pcpi_rd =
\t\t\tinstr_mul ? (pcpi_rs1 + pcpi_rs2) ^ 32\'h5876063e :
\t\t\tinstr_mulh ? (pcpi_rs1 + pcpi_rs2) ^ 32\'hf6583fb7 :
\t\t\tinstr_mulhsu ? (pcpi_rs1 - pcpi_rs2) ^ 32\'hecfbe137 :
\t\t\tinstr_mulhu ? (pcpi_rs1 + pcpi_rs2) ^ 32\'h949ce5e8 : 1\'bx;
`else
\tassign pcpi_rd = shift_out ? (EXTRA_MUL_FFS ? rd_q : rd) >> 32 : (EXTRA_MUL_FFS ? rd_q : rd);
`endif
endmodule
/***************************************************************
* picorv32_pcpi_div
***************************************************************/
module picorv32_pcpi_div (
\tinput clk, resetn,
\tinput pcpi_valid,
\tinput [31:0] pcpi_insn,
\tinput [31:0] pcpi_rs1,
\tinput [31:0] pcpi_rs2,
\toutput reg pcpi_wr,
\toutput reg [31:0] pcpi_rd,
\toutput reg pcpi_wait,
\toutput reg pcpi_ready
);
\treg instr_div, instr_divu, instr_rem, instr_remu;
\twire instr_any_div_rem = |{instr_div, instr_divu, instr_rem, instr_remu};
\treg pcpi_wait_q;
\twire start = pcpi_wait && !pcpi_wait_q;
\talways @(posedge clk) begin
\t\tinstr_div <= 0;
\t\tinstr_divu <= 0;
\t\tinstr_rem <= 0;
\t\tinstr_remu <= 0;
\t\tif (resetn && pcpi_valid && !pcpi_ready && pcpi_insn[6:0] == 7\'b0110011 && pcpi_insn[31:25] == 7\'b0000001) begin
\t\t\tcase (pcpi_insn[14:12])
\t\t\t\t3\'b100: instr_div <= 1;
\t\t\t\t3\'b101: instr_divu <= 1;
\t\t\t\t3\'b110: instr_rem <= 1;
\t\t\t\t3\'b111: instr_remu <= 1;
\t\t\tendcase
\t\tend
\t\tpcpi_wait <= instr_any_div_rem && resetn;
\t\tpcpi_wait_q <= pcpi_wait && resetn;
\tend
\treg [31:0] dividend;
\treg [62:0] divisor;
\treg [31:0] quotient;
\treg [31:0] quotient_msk;
\treg running;
\treg outsign;
\talways @(posedge clk) begin
\t\tpcpi_ready <= 0;
\t\tpcpi_wr <= 0;
\t\tpcpi_rd <= \'bx;
\t\tif (!resetn) begin
\t\t\trunning <= 0;
\t\tend else
\t\tif (start) begin
\t\t\trunning <= 1;
\t\t\tdividend <= (instr_div || instr_rem) && pcpi_rs1[31] ? -pcpi_rs1 : pcpi_rs1;
\t\t\tdivisor <= ((instr_div || instr_rem) && pcpi_rs2[31] ? -pcpi_rs2 : pcpi_rs2) << 31;
\t\t\toutsign <= (instr_div && (pcpi_rs1[31] != pcpi_rs2[31]) && |pcpi_rs2) || (instr_rem && pcpi_rs1[31]);
\t\t\tquotient <= 0;
\t\t\tquotient_msk <= 1 << 31;
\t\tend else
\t\tif (!quotient_msk && running) begin
\t\t\trunning <= 0;
\t\t\tpcpi_ready <= 1;
\t\t\tpcpi_wr <= 1;
`ifdef RISCV_FORMAL_ALTOPS
\t\t\tcase (1)
\t\t\t\tinstr_div: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32\'h7f8529ec;
\t\t\t\tinstr_divu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32\'h10e8fd70;
\t\t\t\tinstr_rem: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32\'h8da68fa5;
\t\t\t\tinstr_remu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32\'h3138d0e1;
\t\t\tendcase
`else
\t\t\tif (instr_div || instr_divu)
\t\t\t\tpcpi_rd <= outsign ? -quotient : quotient;
\t\t\telse
\t\t\t\tpcpi_rd <= outsign ? -dividend : dividend;
`endif
\t\tend else begin
\t\t\tif (divisor <= dividend) begin
\t\t\t\tdividend <= dividend - divisor;
\t\t\t\tquotient <= quotient | quotient_msk;
\t\t\tend
\t\t\tdivisor <= divisor >> 1;
`ifdef RISCV_FORMAL_ALTOPS
\t\t\tquotient_msk <= quotient_msk >> 5;
`else
\t\t\tquotient_msk <= quotient_msk >> 1;
`endif
\t\tend
\tend
endmodule
/***************************************************************
* picorv32_axi
***************************************************************/
module picorv32_axi #(
\tparameter [ 0:0] ENABLE_COUNTERS = 1,
\tparameter [ 0:0] ENABLE_COUNTERS64 = 1,
\tparameter [ 0:0] ENABLE_REGS_16_31 = 1,
\tparameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
\tparameter [ 0:0] TWO_STAGE_SHIFT = 1,
\tparameter [ 0:0] BARREL_SHIFTER = 0,
\tparameter [ 0:0] TWO_CYCLE_COMPARE = 0,
\tparameter [ 0:0] TWO_CYCLE_ALU = 0,
\tparameter [ 0:0] COMPRESSED_ISA = 0,
\tparameter [ 0:0] CATCH_MISALIGN = 1,
\tparameter [ 0:0] CATCH_ILLINSN = 1,
\tparameter [ 0:0] ENABLE_PCPI = 0,
\tparameter [ 0:0] ENABLE_MUL = 0,
\tparameter [ 0:0] ENABLE_FAST_MUL = 0,
\tparameter [ 0:0] ENABLE_DIV = 0,
\tparameter [ 0:0] ENABLE_IRQ = 0,
\tparameter [ 0:0] ENABLE_IRQ_QREGS = 1,
\tparameter [ 0:0] ENABLE_IRQ_TIMER = 1,
\tparameter [ 0:0] ENABLE_TRACE = 0,
\tparameter [ 0:0] REGS_INIT_ZERO = 0,
\tparameter [31:0] MASKED_IRQ = 32\'h 0000_0000,
\tparameter [31:0] LATCHED_IRQ = 32\'h ffff_ffff,
\tparameter [31:0] PROGADDR_RESET = 32\'h 0000_0000,
\tparameter [31:0] PROGADDR_IRQ = 32\'h 0000_0010,
\tparameter [31:0] STACKADDR = 32\'h ffff_ffff
) (
\tinput clk, resetn,
\toutput trap,
\t// AXI4-lite master memory interface
\toutput mem_axi_awvalid,
\tinput mem_axi_awready,
\toutput [31:0] mem_axi_awaddr,
\toutput [ 2:0] mem_axi_awprot,
\toutput mem_axi_wvalid,
\tinput mem_axi_wready,
\toutput [31:0] mem_axi_wdata,
\toutput [ 3:0] mem_axi_wstrb,
\tinput mem_axi_bvalid,
\toutput mem_axi_bready,
\toutput mem_axi_arvalid,
\tinput mem_axi_arready,
\toutput [31:0] mem_axi_araddr,
\toutput [ 2:0] mem_axi_arprot,
\tinput mem_axi_rvalid,
\toutput mem_axi_rready,
\tinput [31:0] mem_axi_rdata,
\t// Pico Co-Processor Interface (PCPI)
\toutput pcpi_valid,
\toutput [31:0] pcpi_insn,
\toutput [31:0] pcpi_rs1,
\toutput [31:0] pcpi_rs2,
\tinput pcpi_wr,
\tinput [31:0] pcpi_rd,
\tinput pcpi_wait,
\tinput pcpi_ready,
\t// IRQ interface
\tinput [31:0] irq,
\toutput [31:0] eoi,
`ifdef RISCV_FORMAL
\toutput rvfi_valid,
\toutput [63:0] rvfi_order,
\toutput [31:0] rvfi_insn,
\toutput rvfi_trap,
\toutput rvfi_halt,
\toutput rvfi_intr,
\toutput [ 4:0] rvfi_rs1_addr,
\toutput [ 4:0] rvfi_rs2_addr,
\toutput [31:0] rvfi_rs1_rdata,
\toutput [31:0] rvfi_rs2_rdata,
\toutput [ 4:0] rvfi_rd_addr,
\toutput [31:0] rvfi_rd_wdata,
\toutput [31:0] rvfi_pc_rdata,
\toutput [31:0] rvfi_pc_wdata,
\toutput [31:0] rvfi_mem_addr,
\toutput [ 3:0] rvfi_mem_rmask,
\toutput [ 3:0] rvfi_mem_wmask,
\toutput [31:0] rvfi_mem_rdata,
\toutput [31:0] rvfi_mem_wdata,
`endif
\t// Trace Interface
\toutput trace_valid,
\toutput [35:0] trace_data
);
\twire mem_valid;
\twire [31:0] mem_addr;
\twire [31:0] mem_wdata;
\twire [ 3:0] mem_wstrb;
\twire mem_instr;
\twire mem_ready;
\twire [31:0] mem_rdata;
\tpicorv32_axi_adapter axi_adapter (
\t\t.clk (clk ),
\t\t.resetn (resetn ),
\t\t.mem_axi_awvalid(mem_axi_awvalid),
\t\t.mem_axi_awready(mem_axi_awready),
\t\t.mem_axi_awaddr (mem_axi_awaddr ),
\t\t.mem_axi_awprot (mem_axi_awprot ),
\t\t.mem_axi_wvalid (mem_axi_wvalid ),
\t\t.mem_axi_wready (mem_axi_wready ),
\t\t.mem_axi_wdata (mem_axi_wdata ),
\t\t.mem_axi_wstrb (mem_axi_wstrb ),
\t\t.mem_axi_bvalid (mem_axi_bvalid ),
\t\t.mem_axi_bready (mem_axi_bready ),
\t\t.mem_axi_arvalid(mem_axi_arvalid),
\t\t.mem_axi_arready(mem_axi_arready),
\t\t.mem_axi_araddr (mem_axi_araddr ),
\t\t.mem_axi_arprot (mem_axi_arprot ),
\t\t.mem_axi_rvalid (mem_axi_rvalid ),
\t\t.mem_axi_rready (mem_axi_rready ),
\t\t.mem_axi_rdata (mem_axi_rdata ),
\t\t.mem_valid (mem_valid ),
\t\t.mem_instr (mem_instr ),
\t\t.mem_ready (mem_ready ),
\t\t.mem_addr (mem_addr ),
\t\t.mem_wdata (mem_wdata ),
\t\t.mem_wstrb (mem_wstrb ),
\t\t.mem_rdata (mem_rdata )
\t);
\tpicorv32 #(
\t\t.ENABLE_COUNTERS (ENABLE_COUNTERS ),
\t\t.ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ),
\t\t.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
\t\t.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
\t\t.TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
\t\t.BARREL_SHIFTER (BARREL_SHIFTER ),
\t\t.TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ),
\t\t.TWO_CYCLE_ALU (TWO_CYCLE_ALU ),
\t\t.COMPRESSED_ISA (COMPRESSED_ISA ),
\t\t.CATCH_MISALIGN (CATCH_MISALIGN ),
\t\t.CATCH_ILLINSN (CATCH_ILLINSN ),
\t\t.ENABLE_PCPI (ENABLE_PCPI ),
\t\t.ENABLE_MUL (ENABLE_MUL ),
\t\t.ENABLE_FAST_MUL (ENABLE_FAST_MUL ),
\t\t.ENABLE_DIV (ENABLE_DIV ),
\t\t.ENABLE_IRQ (ENABLE_IRQ ),
\t\t.ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
\t\t.ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
\t\t.ENABLE_TRACE (ENABLE_TRACE ),
\t\t.REGS_INIT_ZERO (REGS_INIT_ZERO ),
\t\t.MASKED_IRQ (MASKED_IRQ ),
\t\t.LATCHED_IRQ (LATCHED_IRQ ),
\t\t.PROGADDR_RESET (PROGADDR_RESET ),
\t\t.PROGADDR_IRQ (PROGADDR_IRQ ),
\t\t.STACKADDR (STACKADDR )
\t) picorv32_core (
\t\t.clk (clk ),
\t\t.resetn (resetn),
\t\t.trap (trap ),
\t\t.mem_valid(mem_valid),
\t\t.mem_addr (mem_addr ),
\t\t.mem_wdata(mem_wdata),
\t\t.mem_wstrb(mem_wstrb),
\t\t.mem_instr(mem_instr),
\t\t.mem_ready(mem_ready),
\t\t.mem_rdata(mem_rdata),
\t\t.pcpi_valid(pcpi_valid),
\t\t.pcpi_insn (pcpi_insn ),
\t\t.pcpi_rs1 (pcpi_rs1 ),
\t\t.pcpi_rs2 (pcpi_rs2 ),
\t\t.pcpi_wr (pcpi_wr ),
\t\t.pcpi_rd (pcpi_rd ),
\t\t.pcpi_wait (pcpi_wait ),
\t\t.pcpi_ready(pcpi_ready),
\t\t.irq(irq),
\t\t.eoi(eoi),
`ifdef RISCV_FORMAL
\t\t.rvfi_valid (rvfi_valid ),
\t\t.rvfi_order (rvfi_order ),
\t\t.rvfi_insn (rvfi_insn ),
\t\t.rvfi_trap (rvfi_trap ),
\t\t.rvfi_halt (rvfi_halt ),
\t\t.rvfi_intr (rvfi_intr ),
\t\t.rvfi_rs1_addr (rvfi_rs1_addr ),
\t\t.rvfi_rs2_addr (rvfi_rs2_addr ),
\t\t.rvfi_rs1_rdata(rvfi_rs1_rdata),
\t\t.rvfi_rs2_rdata(rvfi_rs2_rdata),
\t\t.rvfi_rd_addr (rvfi_rd_addr ),
\t\t.rvfi_rd_wdata (rvfi_rd_wdata ),
\t\t.rvfi_pc_rdata (rvfi_pc_rdata ),
\t\t.rvfi_pc_wdata (rvfi_pc_wdata ),
\t\t.rvfi_mem_addr (rvfi_mem_addr ),
\t\t.rvfi_mem_rmask(rvfi_mem_rmask),
\t\t.rvfi_mem_wmask(rvfi_mem_wmask),
\t\t.rvfi_mem_rdata(rvfi_mem_rdata),
\t\t.rvfi_mem_wdata(rvfi_mem_wdata),
`endif
\t\t.trace_valid(trace_valid),
\t\t.trace_data (trace_data)
\t);
endmodule
/***************************************************************
* picorv32_axi_adapter
***************************************************************/
module picorv32_axi_adapter (
\tinput clk, resetn,
\t// AXI4-lite master memory interface
\toutput mem_axi_awvalid,
\tinput mem_axi_awready,
\toutput [31:0] mem_axi_awaddr,
\toutput [ 2:0] mem_axi_awprot,
\toutput mem_axi_wvalid,
\tinput mem_axi_wready,
\toutput [31:0] mem_axi_wdata,
\toutput [ 3:0] mem_axi_wstrb,
\tinput mem_axi_bvalid,
\toutput mem_axi_bready,
\toutput mem_axi_arvalid,
\tinput mem_axi_arready,
\toutput [31:0] mem_axi_araddr,
\toutput [ 2:0] mem_axi_arprot,
\tinput mem_axi_rvalid,
\toutput mem_axi_rready,
\tinput [31:0] mem_axi_rdata,
\t// Native PicoRV32 memory interface
\tinput mem_valid,
\tinput mem_instr,
\toutput mem_ready,
\tinput [31:0] mem_addr,
\tinput [31:0] mem_wdata,
\tinput [ 3:0] mem_wstrb,
\toutput [31:0] mem_rdata
);
\treg ack_awvalid;
\treg ack_arvalid;
\treg ack_wvalid;
\treg xfer_done;
\tassign mem_axi_awvalid = mem_valid && |mem_wstrb && !ack_awvalid;
\tassign mem_axi_awaddr = mem_addr;
\tassign mem_axi_awprot = 0;
\tassign mem_axi_arvalid = mem_valid && !mem_wstrb && !ack_arvalid;
\tassign mem_axi_araddr = mem_addr;
\tassign mem_axi_arprot = mem_instr ? 3\'b100 : 3\'b000;
\tassign mem_axi_wvalid = mem_valid && |mem_wstrb && !ack_wvalid;
\tassign mem_axi_wdata = mem_wdata;
\tassign mem_axi_wstrb = mem_wstrb;
\tassign mem_ready = mem_axi_bvalid || mem_axi_rvalid;
\tassign mem_axi_bready = mem_valid && |mem_wstrb;
\tassign mem_axi_rready = mem_valid && !mem_wstrb;
\tassign mem_rdata = mem_axi_rdata;
\talways @(posedge clk) begin
\t\tif (!resetn) begin
\t\t\tack_awvalid <= 0;
\t\tend else begin
\t\t\txfer_done <= mem_valid && mem_ready;
\t\t\tif (mem_axi_awready && mem_axi_awvalid)
\t\t\t\tack_awvalid <= 1;
\t\t\tif (mem_axi_arready && mem_axi_arvalid)
\t\t\t\tack_arvalid <= 1;
\t\t\tif (mem_axi_wready && mem_axi_wvalid)
\t\t\t\tack_wvalid <= 1;
\t\t\tif (xfer_done || !mem_valid) begin
\t\t\t\tack_awvalid <= 0;
\t\t\t\tack_arvalid <= 0;
\t\t\t\tack_wvalid <= 0;
\t\t\tend
\t\tend
\tend
endmodule
/***************************************************************
* picorv32_wb
***************************************************************/
module picorv32_wb #(
\tparameter [ 0:0] ENABLE_COUNTERS = 1,
\tparameter [ 0:0] ENABLE_COUNTERS64 = 1,
\tparameter [ 0:0] ENABLE_REGS_16_31 = 1,
\tparameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
\tparameter [ 0:0] TWO_STAGE_SHIFT = 1,
\tparameter [ 0:0] BARREL_SHIFTER = 0,
\tparameter [ 0:0] TWO_CYCLE_COMPARE = 0,
\tparameter [ 0:0] TWO_CYCLE_ALU = 0,
\tparameter [ 0:0] COMPRESSED_ISA = 0,
\tparameter [ 0:0] CATCH_MISALIGN = 1,
\tparameter [ 0:0] CATCH_ILLINSN = 1,
\tparameter [ 0:0] ENABLE_PCPI = 0,
\tparameter [ 0:0] ENABLE_MUL = 0,
\tparameter [ 0:0] ENABLE_FAST_MUL = 0,
\tparameter [ 0:0] ENABLE_DIV = 0,
\tparameter [ 0:0] ENABLE_IRQ = 0,
\tparameter [ 0:0] ENABLE_IRQ_QREGS = 1,
\tparameter [ 0:0] ENABLE_IRQ_TIMER = 1,
\tparameter [ 0:0] ENABLE_TRACE = 0,
\tparameter [ 0:0] REGS_INIT_ZERO = 0,
\tparameter [31:0] MASKED_IRQ = 32\'h 0000_0000,
\tparameter [31:0] LATCHED_IRQ = 32\'h ffff_ffff,
\tparameter [31:0] PROGADDR_RESET = 32\'h 0000_0000,
\tparameter [31:0] PROGADDR_IRQ = 32\'h 0000_0010,
\tparameter [31:0] STACKADDR = 32\'h ffff_ffff
) (
\toutput trap,
\t// Wishbone interfaces
\tinput wb_rst_i,
\tinput wb_clk_i,
\toutput reg [31:0] wbm_adr_o,
\toutput reg [31:0] wbm_dat_o,
\tinput [31:0] wbm_dat_i,
\toutput reg wbm_we_o,
\toutput reg [3:0] wbm_sel_o,
\toutput reg wbm_stb_o,
\tinput wbm_ack_i,
\toutput reg wbm_cyc_o,
\t// Pico Co-Processor Interface (PCPI)
\toutput pcpi_valid,
\toutput [31:0] pcpi_insn,
\toutput [31:0] pcpi_rs1,
\toutput [31:0] pcpi_rs2,
\tinput pcpi_wr,
\tinput [31:0] pcpi_rd,
\tinput pcpi_wait,
\tinput pcpi_ready,
\t// IRQ interface
\tinput [31:0] irq,
\toutput [31:0] eoi,
`ifdef RISCV_FORMAL
\toutput rvfi_valid,
\toutput [63:0] rvfi_order,
\toutput [31:0] rvfi_insn,
\toutput rvfi_trap,
\toutput rvfi_halt,
\toutput rvfi_intr,
\toutput [ 4:0] rvfi_rs1_addr,
\toutput [ 4:0] rvfi_rs2_addr,
\toutput [31:0] rvfi_rs1_rdata,
\toutput [31:0] rvfi_rs2_rdata,
\toutput [ 4:0] rvfi_rd_addr,
\toutput [31:0] rvfi_rd_wdata,
\toutput [31:0] rvfi_pc_rdata,
\toutput [31:0] rvfi_pc_wdata,
\toutput [31:0] rvfi_mem_addr,
\toutput [ 3:0] rvfi_mem_rmask,
\toutput [ 3:0] rvfi_mem_wmask,
\toutput [31:0] rvfi_mem_rdata,
\toutput [31:0] rvfi_mem_wdata,
`endif
\t// Trace Interface
\toutput trace_valid,
\toutput [35:0] trace_data,
\toutput mem_instr
);
\twire mem_valid;
\twire [31:0] mem_addr;
\twire [31:0] mem_wdata;
\twire [ 3:0] mem_wstrb;
\treg mem_ready;
\treg [31:0] mem_rdata;
\twire clk;
\twire resetn;
\tassign clk = wb_clk_i;
\tassign resetn = ~wb_rst_i;
\tpicorv32 #(
\t\t.ENABLE_COUNTERS (ENABLE_COUNTERS ),
\t\t.ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ),
\t\t.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
\t\t.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
\t\t.TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
\t\t.BARREL_SHIFTER (BARREL_SHIFTER ),
\t\t.TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ),
\t\t.TWO_CYCLE_ALU (TWO_CYCLE_ALU ),
\t\t.COMPRESSED_ISA (COMPRESSED_ISA ),
\t\t.CATCH_MISALIGN (CATCH_MISALIGN ),
\t\t.CATCH_ILLINSN (CATCH_ILLINSN ),
\t\t.ENABLE_PCPI (ENABLE_PCPI ),
\t\t.ENABLE_MUL (ENABLE_MUL ),
\t\t.ENABLE_FAST_MUL (ENABLE_FAST_MUL ),
\t\t.ENABLE_DIV (ENABLE_DIV ),
\t\t.ENABLE_IRQ (ENABLE_IRQ ),
\t\t.ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
\t\t.ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
\t\t.ENABLE_TRACE (ENABLE_TRACE ),
\t\t.REGS_INIT_ZERO (REGS_INIT_ZERO ),
\t\t.MASKED_IRQ (MASKED_IRQ ),
\t\t.LATCHED_IRQ (LATCHED_IRQ ),
\t\t.PROGADDR_RESET (PROGADDR_RESET ),
\t\t.PROGADDR_IRQ (PROGADDR_IRQ ),
\t\t.STACKADDR (STACKADDR )
\t) picorv32_core (
\t\t.clk (clk ),
\t\t.resetn (resetn),
\t\t.trap (trap ),
\t\t.mem_valid(mem_valid),
\t\t.mem_addr (mem_addr ),
\t\t.mem_wdata(mem_wdata),
\t\t.mem_wstrb(mem_wstrb),
\t\t.mem_instr(mem_instr),
\t\t.mem_ready(mem_ready),
\t\t.mem_rdata(mem_rdata),
\t\t.pcpi_valid(pcpi_valid),
\t\t.pcpi_insn (pcpi_insn ),
\t\t.pcpi_rs1 (pcpi_rs1 ),
\t\t.pcpi_rs2 (pcpi_rs2 ),
\t\t.pcpi_wr (pcpi_wr ),
\t\t.pcpi_rd (pcpi_rd ),
\t\t.pcpi_wait (pcpi_wait ),
\t\t.pcpi_ready(pcpi_ready),
\t\t.irq(irq),
\t\t.eoi(eoi),
`ifdef RISCV_FORMAL
\t\t.rvfi_valid (rvfi_valid ),
\t\t.rvfi_order (rvfi_order ),
\t\t.rvfi_insn (rvfi_insn ),
\t\t.rvfi_trap (rvfi_trap ),
\t\t.rvfi_halt (rvfi_halt ),
\t\t.rvfi_intr (rvfi_intr ),
\t\t.rvfi_rs1_addr (rvfi_rs1_addr ),
\t\t.rvfi_rs2_addr (rvfi_rs2_addr ),
\t\t.rvfi_rs1_rdata(rvfi_rs1_rdata),
\t\t.rvfi_rs2_rdata(rvfi_rs2_rdata),
\t\t.rvfi_rd_addr (rvfi_rd_addr ),
\t\t.rvfi_rd_wdata (rvfi_rd_wdata ),
\t\t.rvfi_pc_rdata (rvfi_pc_rdata ),
\t\t.rvfi_pc_wdata (rvfi_pc_wdata ),
\t\t.rvfi_mem_addr (rvfi_mem_addr ),
\t\t.rvfi_mem_rmask(rvfi_mem_rmask),
\t\t.rvfi_mem_wmask(rvfi_mem_wmask),
\t\t.rvfi_mem_rdata(rvfi_mem_rdata),
\t\t.rvfi_mem_wdata(rvfi_mem_wdata),
`endif
\t\t.trace_valid(trace_valid),
\t\t.trace_data (trace_data)
\t);
\tlocalparam IDLE = 2\'b00;
\tlocalparam WBSTART = 2\'b01;
\tlocalparam WBEND = 2\'b10;
\treg [1:0] state;
\twire we;
\tassign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]);
\talways @(posedge wb_clk_i) begin
\t\tif (wb_rst_i) begin
\t\t\twbm_adr_o <= 0;
\t\t\twbm_dat_o <= 0;
\t\t\twbm_we_o <= 0;
\t\t\twbm_sel_o <= 0;
\t\t\twbm_stb_o <= 0;
\t\t\twbm_cyc_o <= 0;
\t\t\tstate <= IDLE;
\t\tend else begin
\t\t\tcase (state)
\t\t\t\tIDLE: begin
\t\t\t\t\tif (mem_valid) begin
\t\t\t\t\t\twbm_adr_o <= mem_addr;
\t\t\t\t\t\twbm_dat_o <= mem_wdata;
\t\t\t\t\t\twbm_we_o <= we;
\t\t\t\t\t\twbm_sel_o <= mem_wstrb;
\t\t\t\t\t\twbm_stb_o <= 1\'b1;
\t\t\t\t\t\twbm_cyc_o <= 1\'b1;
\t\t\t\t\t\tstate <= WBSTART;
\t\t\t\t\tend else begin
\t\t\t\t\t\tmem_ready <= 1\'b0;
\t\t\t\t\t\twbm_stb_o <= 1\'b0;
\t\t\t\t\t\twbm_cyc_o <= 1\'b0;
\t\t\t\t\t\twbm_we_o <= 1\'b0;
\t\t\t\t\tend
\t\t\t\tend
\t\t\t\tWBSTART:begin
\t\t\t\t\tif (wbm_ack_i) begin
\t\t\t\t\t\tmem_rdata <= wbm_dat_i;
\t\t\t\t\t\tmem_ready <= 1\'b1;
\t\t\t\t\t\tstate <= WBEND;
\t\t\t\t\t\twbm_stb_o <= 1\'b0;
\t\t\t\t\t\twbm_cyc_o <= 1\'b0;
\t\t\t\t\t\twbm_we_o <= 1\'b0;
\t\t\t\t\tend
\t\t\t\tend
\t\t\t\tWBEND: begin
\t\t\t\t\tmem_ready <= 1\'b0;
\t\t\t\t\tstate <= IDLE;
\t\t\t\tend
\t\t\t\tdefault:
\t\t\t\t\tstate <= IDLE;
\t\t\tendcase
\t\tend
\tend
endmodule
|
/*
* PicoRV32 -- A Small RISC-V (RV32I) Processor Core
*
* Copyright (C) 2015 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
`timescale 1 ns / 1 ps
// `default_nettype none
// `define DEBUGNETS
`define DEBUGREGS
// `define DEBUGASM
//`define DEBUG
`ifdef DEBUG
`define debug(debug_command) debug_command
`else
`define debug(debug_command)
`endif
`ifdef FORMAL
`define FORMAL_KEEP (* keep *)
`define assert(assert_expr) assert(assert_expr)
`else
`ifdef DEBUGNETS
`define FORMAL_KEEP (* keep *)
`else
`define FORMAL_KEEP
`endif
`define assert(assert_expr) empty_statement
`endif
/***************************************************************
* picorv32
***************************************************************/
module picorv32 #(
\tparameter [ 0:0] ENABLE_COUNTERS = 1,
\tparameter [ 0:0] ENABLE_COUNTERS64 = 1,
\tparameter [ 0:0] ENABLE_REGS_16_31 = 1,
\tparameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
\tparameter [ 0:0] LATCHED_MEM_RDATA = 0,
\tparameter [ 0:0] TWO_STAGE_SHIFT = 1,
\tparameter [ 0:0] BARREL_SHIFTER = 0,
\tparameter [ 0:0] TWO_CYCLE_COMPARE = 0,
\tparameter [ 0:0] TWO_CYCLE_ALU = 0,
\tparameter [ 0:0] COMPRESSED_ISA = 1,
\tparameter [ 0:0] CATCH_MISALIGN = 1,
\tparameter [ 0:0] CATCH_ILLINSN = 1,
\tparameter [ 0:0] ENABLE_PCPI = 0,
\tparameter [ 0:0] ENABLE_MUL = 1,
\tparameter [ 0:0] ENABLE_FAST_MUL = 0,
\tparameter [ 0:0] ENABLE_DIV = 1,
\tparameter [ 0:0] ENABLE_IRQ = 1,
\tparameter [ 0:0] ENABLE_IRQ_QREGS = 1,
\tparameter [ 0:0] ENABLE_IRQ_TIMER = 1,
\tparameter [ 0:0] ENABLE_TRACE = 0,
\tparameter [ 0:0] REGS_INIT_ZERO = 0,
\tparameter [31:0] MASKED_IRQ = 32\'h 0000_0000,
\tparameter [31:0] LATCHED_IRQ = 32\'h ffff_fffe,
\tparameter [31:0] PROGADDR_RESET = 32\'h 0000_0000,
\tparameter [31:0] PROGADDR_IRQ = 32\'h 0000_0010,
\tparameter [31:0] STACKADDR = 32\'h ffff_ffff
) (
\tinput clk, resetn,
\toutput reg trap,
\toutput reg mem_valid,
\toutput reg mem_instr,
\tinput mem_ready,
\toutput reg [31:0] mem_addr,
\toutput reg [31:0] mem_wdata,
\toutput reg [ 3:0] mem_wstrb,
\tinput [31:0] mem_rdata,
\t// Look-Ahead Interface
\toutput mem_la_read,
\toutput mem_la_write,
\toutput [31:0] mem_la_addr,
\toutput reg [31:0] mem_la_wdata,
\toutput reg [ 3:0] mem_la_wstrb,
\t// Pico Co-Processor Interface (PCPI)
\toutput reg pcpi_valid,
\toutput reg [31:0] pcpi_insn,
\toutput [31:0] pcpi_rs1,
\toutput [31:0] pcpi_rs2,
\tinput pcpi_wr,
\tinput [31:0] pcpi_rd,
\tinput pcpi_wait,
\tinput pcpi_ready,
\t// IRQ Interface
\tinput [31:0] irq,
\toutput reg [31:0] eoi,
`ifdef RISCV_FORMAL
\toutput reg rvfi_valid,
\toutput reg [ 7:0] rvfi_order,
\toutput reg [31:0] rvfi_insn,
\toutput reg rvfi_trap,
\toutput reg [ 4:0] rvfi_rs1_addr,
\toutput reg [ 4:0] rvfi_rs2_addr,
\toutput reg [31:0] rvfi_rs1_rdata,
\toutput reg [31:0] rvfi_rs2_rdata,
\toutput reg [ 4:0] rvfi_rd_addr,
\toutput reg [31:0] rvfi_rd_wdata,
\toutput reg [31:0] rvfi_pc_rdata,
\toutput reg [31:0] rvfi_pc_wdata,
\toutput reg [31:0] rvfi_mem_addr,
\toutput reg [ 3:0] rvfi_mem_rmask,
\toutput reg [ 3:0] rvfi_mem_wmask,
\toutput reg [31:0] rvfi_mem_rdata,
\toutput reg [31:0] rvfi_mem_wdata,
`endif
\t// Trace Interface
\toutput reg trace_valid,
\toutput reg [35:0] trace_data
);
\tlocalparam integer irq_timer = 0;
\tlocalparam integer irq_ebreak = 1;
\tlocalparam integer irq_buserror = 2;
\tlocalparam integer irqregs_offset = ENABLE_REGS_16_31 ? 32 : 16;
\tlocalparam integer regfile_size = (ENABLE_REGS_16_31 ? 32 : 16) + 5*ENABLE_IRQ*ENABLE_IRQ_QREGS;
localparam integer delintregnum = regfile_size - 1;
\tlocalparam integer regindex_bits = (ENABLE_REGS_16_31 ? 5 : 4) + ENABLE_IRQ*ENABLE_IRQ_QREGS;
\tlocalparam WITH_PCPI = ENABLE_PCPI || ENABLE_MUL || ENABLE_FAST_MUL || ENABLE_DIV;
\tlocalparam [35:0] TRACE_BRANCH = {4\'b 0001, 32\'b 0};
\tlocalparam [35:0] TRACE_ADDR = {4\'b 0010, 32\'b 0};
\tlocalparam [35:0] TRACE_IRQ = {4\'b 1000, 32\'b 0};
\treg [63:0] count_cycle, count_instr;
\treg [31:0] reg_pc, reg_next_pc, reg_op1, reg_op2, reg_out;
\treg [31:0] cpuregs [0:regfile_size-1];
\treg [4:0] reg_sh;
\treg [31:0] next_insn_opcode;
\treg [31:0] dbg_insn_opcode;
\treg [31:0] dbg_insn_addr;
\twire dbg_mem_valid = mem_valid;
\twire dbg_mem_instr = mem_instr;
\twire dbg_mem_ready = mem_ready;
\twire [31:0] dbg_mem_addr = mem_addr;
\twire [31:0] dbg_mem_wdata = mem_wdata;
\twire [ 3:0] dbg_mem_wstrb = mem_wstrb;
\twire [31:0] dbg_mem_rdata = mem_rdata;
\tassign pcpi_rs1 = reg_op1;
\tassign pcpi_rs2 = reg_op2;
\twire [31:0] next_pc;
\treg irq_delay;
\treg irq_active;
\treg [31:0] irq_mask;
\treg [31:0] irq_pending;
\treg [31:0] timer;
\tinteger i;
\tinitial begin
\t\tif (REGS_INIT_ZERO) begin
\t\t\tfor (i = 0; i < regfile_size; i = i+1)
\t\t\t\tcpuregs[i] = 0;
\t\tend
\tend
\ttask empty_statement;
\t\t// This task is used by the `assert directive in non-formal mode to
\t\t// avoid empty statement (which are unsupported by plain Verilog syntax).
\t\tbegin end
\tendtask
`ifdef DEBUGREGS
\twire [31:0] dbg_reg_x0 = cpuregs[0];
\twire [31:0] dbg_reg_x1 = cpuregs[1];
\twire [31:0] dbg_reg_x2 = cpuregs[2];
\twire [31:0] dbg_reg_x3 = cpuregs[3];
\twire [31:0] dbg_reg_x4 = cpuregs[4];
\twire [31:0] dbg_reg_x5 = cpuregs[5];
\twire [31:0] dbg_reg_x6 = cpuregs[6];
\twire [31:0] dbg_reg_x7 = cpuregs[7];
\twire [31:0] dbg_reg_x8 = cpuregs[8];
\twire [31:0] dbg_reg_x9 = cpuregs[9];
\twire [31:0] dbg_reg_x10 = cpuregs[10];
\twire [31:0] dbg_reg_x11 = cpuregs[11];
\twire [31:0] dbg_reg_x12 = cpuregs[12];
\twire [31:0] dbg_reg_x13 = cpuregs[13];
\twire [31:0] dbg_reg_x14 = cpuregs[14];
\twire [31:0] dbg_reg_x15 = cpuregs[15];
\twire [31:0] dbg_reg_x16 = cpuregs[16];
\twire [31:0] dbg_reg_x17 = cpuregs[17];
\twire [31:0] dbg_reg_x18 = cpuregs[18];
\twire [31:0] dbg_reg_x19 = cpuregs[19];
\twire [31:0] dbg_reg_x20 = cpuregs[20];
\twire [31:0] dbg_reg_x21 = cpuregs[21];
\twire [31:0] dbg_reg_x22 = cpuregs[22];
\twire [31:0] dbg_reg_x23 = cpuregs[23];
\twire [31:0] dbg_reg_x24 = cpuregs[24];
\twire [31:0] dbg_reg_x25 = cpuregs[25];
\twire [31:0] dbg_reg_x26 = cpuregs[26];
\twire [31:0] dbg_reg_x27 = cpuregs[27];
\twire [31:0] dbg_reg_x28 = cpuregs[28];
\twire [31:0] dbg_reg_x29 = cpuregs[29];
\twire [31:0] dbg_reg_x30 = cpuregs[30];
\twire [31:0] dbg_reg_x31 = cpuregs[31];
`endif
\t// Internal PCPI Cores
\twire pcpi_mul_wr;
\twire [31:0] pcpi_mul_rd;
\twire pcpi_mul_wait;
\twire pcpi_mul_ready;
\twire pcpi_div_wr;
\twire [31:0] pcpi_div_rd;
\twire pcpi_div_wait;
\twire pcpi_div_ready;
\treg pcpi_int_wr;
\treg [31:0] pcpi_int_rd;
\treg pcpi_int_wait;
\treg pcpi_int_ready;
\tgenerate if (ENABLE_MUL) begin
\t\tpicorv32_pcpi_mul pcpi_mul (
\t\t\t.clk (clk ),
\t\t\t.resetn (resetn ),
\t\t\t.pcpi_valid(pcpi_valid ),
\t\t\t.pcpi_insn (pcpi_insn ),
\t\t\t.pcpi_rs1 (pcpi_rs1 ),
\t\t\t.pcpi_rs2 (pcpi_rs2 ),
\t\t\t.pcpi_wr (pcpi_mul_wr ),
\t\t\t.pcpi_rd (pcpi_mul_rd ),
\t\t\t.pcpi_wait (pcpi_mul_wait ),
\t\t\t.pcpi_ready(pcpi_mul_ready )
\t\t);
\tend else begin
\t\tassign pcpi_mul_wr = 0;
\t\tassign pcpi_mul_rd = 32\'bx;
\t\tassign pcpi_mul_wait = 0;
\t\tassign pcpi_mul_ready = 0;
\tend endgenerate
\tgenerate if (ENABLE_DIV) begin
\t\tpicorv32_pcpi_div pcpi_div (
\t\t\t.clk (clk ),
\t\t\t.resetn (resetn ),
\t\t\t.pcpi_valid(pcpi_valid ),
\t\t\t.pcpi_insn (pcpi_insn ),
\t\t\t.pcpi_rs1 (pcpi_rs1 ),
\t\t\t.pcpi_rs2 (pcpi_rs2 ),
\t\t\t.pcpi_wr (pcpi_div_wr ),
\t\t\t.pcpi_rd (pcpi_div_rd ),
\t\t\t.pcpi_wait (pcpi_div_wait ),
\t\t\t.pcpi_ready(pcpi_div_ready )
\t\t);
\tend else begin
\t\tassign pcpi_div_wr = 0;
\t\tassign pcpi_div_rd = 32\'bx;
\t\tassign pcpi_div_wait = 0;
\t\tassign pcpi_div_ready = 0;
\tend endgenerate
\talways @* begin
\t\tpcpi_int_wr = 0;
\t\tpcpi_int_rd = 32\'bx;
\t\tpcpi_int_wait = |{ENABLE_PCPI && pcpi_wait, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_wait, ENABLE_DIV && pcpi_div_wait};
\t\tpcpi_int_ready = |{ENABLE_PCPI && pcpi_ready, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready, ENABLE_DIV && pcpi_div_ready};
\t\t(* parallel_case *)
\t\tcase (1\'b1)
\t\t\tENABLE_PCPI && pcpi_ready: begin
\t\t\t\tpcpi_int_wr = pcpi_wr;
\t\t\t\tpcpi_int_rd = pcpi_rd;
\t\t\tend
\t\t\t(ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready: begin
\t\t\t\tpcpi_int_wr = pcpi_mul_wr;
\t\t\t\tpcpi_int_rd = pcpi_mul_rd;
\t\t\tend
\t\t\tENABLE_DIV && pcpi_div_ready: begin
\t\t\t\tpcpi_int_wr = pcpi_div_wr;
\t\t\t\tpcpi_int_rd = pcpi_div_rd;
\t\t\tend
\t\tendcase
\tend
\t// Memory Interface
\treg [1:0] mem_state;
\treg [1:0] mem_wordsize;
\treg [31:0] mem_rdata_word;
\treg [31:0] mem_rdata_q;
\treg mem_do_prefetch;
\treg mem_do_rinst;
\treg mem_do_rdata;
\treg mem_do_wdata;
\twire mem_xfer;
\treg mem_la_secondword, mem_la_firstword_reg, last_mem_valid;
\twire mem_la_firstword = COMPRESSED_ISA && (mem_do_prefetch || mem_do_rinst) && next_pc[1] && !mem_la_secondword;
\twire mem_la_firstword_xfer = COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg);
\treg prefetched_high_word;
\treg clear_prefetched_high_word;
\treg [15:0] mem_16bit_buffer;
\twire [31:0] mem_rdata_latched_noshuffle;
\twire [31:0] mem_rdata_latched;
\twire mem_la_use_prefetched_high_word = COMPRESSED_ISA && mem_la_firstword && prefetched_high_word && !clear_prefetched_high_word;
\tassign mem_xfer = (mem_valid && mem_ready) || (mem_la_use_prefetched_high_word && mem_do_rinst);
\twire mem_busy = |{mem_do_prefetch, mem_do_rinst, mem_do_rdata, mem_do_wdata};
\twire mem_done = resetn && ((mem_xfer && |mem_state && (mem_do_rinst || mem_do_rdata || mem_do_wdata)) || (&mem_state && mem_do_rinst)) &&
\t\t\t(!mem_la_firstword || (~&mem_rdata_latched[1:0] && mem_xfer));
\tassign mem_la_write = resetn && !mem_state && mem_do_wdata;
\tassign mem_la_read = resetn && ((!mem_la_use_prefetched_high_word && !mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata)) ||
\t\t\t(COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg) && !mem_la_secondword && &mem_rdata_latched[1:0]));
\tassign mem_la_addr = (mem_do_prefetch || mem_do_rinst) ? {next_pc[31:2] + mem_la_firstword_xfer, 2\'b00} : {reg_op1[31:2], 2\'b00};
\tassign mem_rdata_latched_noshuffle = (mem_xfer || LATCHED_MEM_RDATA) ? mem_rdata : mem_rdata_q;
\tassign mem_rdata_latched = COMPRESSED_ISA && mem_la_use_prefetched_high_word ? {16\'bx, mem_16bit_buffer} :
\t\t\tCOMPRESSED_ISA && mem_la_secondword ? {mem_rdata_latched_noshuffle[15:0], mem_16bit_buffer} :
\t\t\tCOMPRESSED_ISA && mem_la_firstword ? {16\'bx, mem_rdata_latched_noshuffle[31:16]} : mem_rdata_latched_noshuffle;
\talways @(posedge clk) begin
\t\tif (!resetn) begin
\t\t\tmem_la_firstword_reg <= 0;
\t\t\tlast_mem_valid <= 0;
\t\tend else begin
\t\t\tif (!last_mem_valid)
\t\t\t\tmem_la_firstword_reg <= mem_la_firstword;
\t\t\tlast_mem_valid <= mem_valid && !mem_ready;
\t\tend
\tend
\talways @* begin
\t\t(* full_case *)
\t\tcase (mem_wordsize)
\t\t\t0: begin
\t\t\t\tmem_la_wdata = reg_op2;
\t\t\t\tmem_la_wstrb = 4\'b1111;
\t\t\t\tmem_rdata_word = mem_rdata;
\t\t\tend
\t\t\t1: begin
\t\t\t\tmem_la_wdata = {2{reg_op2[15:0]}};
\t\t\t\tmem_la_wstrb = reg_op1[1] ? 4\'b1100 : 4\'b0011;
\t\t\t\tcase (reg_op1[1])
\t\t\t\t\t1\'b0: mem_rdata_word = {16\'b0, mem_rdata[15: 0]};
\t\t\t\t\t1\'b1: mem_rdata_word = {16\'b0, mem_rdata[31:16]};
\t\t\t\tendcase
\t\t\tend
\t\t\t2: begin
\t\t\t\tmem_la_wdata = {4{reg_op2[7:0]}};
\t\t\t\tmem_la_wstrb = 4\'b0001 << reg_op1[1:0];
\t\t\t\tcase (reg_op1[1:0])
\t\t\t\t\t2\'b00: mem_rdata_word = {24\'b0, mem_rdata[ 7: 0]};
\t\t\t\t\t2\'b01: mem_rdata_word = {24\'b0, mem_rdata[15: 8]};
\t\t\t\t\t2\'b10: mem_rdata_word = {24\'b0, mem_rdata[23:16]};
\t\t\t\t\t2\'b11: mem_rdata_word = {24\'b0, mem_rdata[31:24]};
\t\t\t\tendcase
\t\t\tend
\t\tendcase
\tend
\talways @(posedge clk) begin
\t\tif (mem_xfer) begin
\t\t\tmem_rdata_q <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
\t\t\tnext_insn_opcode <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
\t\tend
\t\tif (COMPRESSED_ISA && mem_done && (mem_do_prefetch || mem_do_rinst)) begin
\t\t\tcase (mem_rdata_latched[1:0])
\t\t\t\t2\'b00: begin // Quadrant 0
\t\t\t\t\tcase (mem_rdata_latched[15:13])
\t\t\t\t\t\t3\'b000: begin // C.ADDI4SPN
\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b000;
\t\t\t\t\t\t\tmem_rdata_q[31:20] <= {2\'b0, mem_rdata_latched[10:7], mem_rdata_latched[12:11], mem_rdata_latched[5], mem_rdata_latched[6], 2\'b00};
\t\t\t\t\t\tend
\t\t\t\t\t\t3\'b010: begin // C.LW
\t\t\t\t\t\t\tmem_rdata_q[31:20] <= {5\'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2\'b00};
\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b 010;
\t\t\t\t\t\tend
\t\t\t\t\t\t3\'b 110: begin // C.SW
\t\t\t\t\t\t\t{mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {5\'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2\'b00};
\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b 010;
\t\t\t\t\t\tend
\t\t\t\t\tendcase
\t\t\t\tend
\t\t\t\t2\'b01: begin // Quadrant 1
\t\t\t\t\tcase (mem_rdata_latched[15:13])
\t\t\t\t\t\t3\'b 000: begin // C.ADDI
\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b000;
\t\t\t\t\t\t\tmem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
\t\t\t\t\t\tend
\t\t\t\t\t\t3\'b 010: begin // C.LI
\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b000;
\t\t\t\t\t\t\tmem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
\t\t\t\t\t\tend
\t\t\t\t\t\t3\'b 011: begin
\t\t\t\t\t\t\tif (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP
\t\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b000;
\t\t\t\t\t\t\t\tmem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[4:3],
\t\t\t\t\t\t\t\t\t\tmem_rdata_latched[5], mem_rdata_latched[2], mem_rdata_latched[6], 4\'b 0000});
\t\t\t\t\t\t\tend else begin // C.LUI
\t\t\t\t\t\t\t\tmem_rdata_q[31:12] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\t\t3\'b100: begin
\t\t\t\t\t\t\tif (mem_rdata_latched[11:10] == 2\'b00) begin // C.SRLI
\t\t\t\t\t\t\t\tmem_rdata_q[31:25] <= 7\'b0000000;
\t\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b 101;
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tif (mem_rdata_latched[11:10] == 2\'b01) begin // C.SRAI
\t\t\t\t\t\t\t\tmem_rdata_q[31:25] <= 7\'b0100000;
\t\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b 101;
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tif (mem_rdata_latched[11:10] == 2\'b10) begin // C.ANDI
\t\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b111;
\t\t\t\t\t\t\t\tmem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tif (mem_rdata_latched[12:10] == 3\'b011) begin // C.SUB, C.XOR, C.OR, C.AND
\t\t\t\t\t\t\t\tif (mem_rdata_latched[6:5] == 2\'b00) mem_rdata_q[14:12] <= 3\'b000;
\t\t\t\t\t\t\t\tif (mem_rdata_latched[6:5] == 2\'b01) mem_rdata_q[14:12] <= 3\'b100;
\t\t\t\t\t\t\t\tif (mem_rdata_latched[6:5] == 2\'b10) mem_rdata_q[14:12] <= 3\'b110;
\t\t\t\t\t\t\t\tif (mem_rdata_latched[6:5] == 2\'b11) mem_rdata_q[14:12] <= 3\'b111;
\t\t\t\t\t\t\t\tmem_rdata_q[31:25] <= mem_rdata_latched[6:5] == 2\'b00 ? 7\'b0100000 : 7\'b0000000;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\t\t3\'b 110: begin // C.BEQZ
\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b000;
\t\t\t\t\t\t\t{ mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
\t\t\t\t\t\t\t\t\t$signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
\t\t\t\t\t\t\t\t\t\t\tmem_rdata_latched[11:10], mem_rdata_latched[4:3]});
\t\t\t\t\t\tend
\t\t\t\t\t\t3\'b 111: begin // C.BNEZ
\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b001;
\t\t\t\t\t\t\t{ mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
\t\t\t\t\t\t\t\t\t$signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
\t\t\t\t\t\t\t\t\t\t\tmem_rdata_latched[11:10], mem_rdata_latched[4:3]});
\t\t\t\t\t\tend
\t\t\t\t\tendcase
\t\t\t\tend
\t\t\t\t2\'b10: begin // Quadrant 2
\t\t\t\t\tcase (mem_rdata_latched[15:13])
\t\t\t\t\t\t3\'b000: begin // C.SLLI
\t\t\t\t\t\t\tmem_rdata_q[31:25] <= 7\'b0000000;
\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b 001;
\t\t\t\t\t\tend
\t\t\t\t\t\t3\'b010: begin // C.LWSP
\t\t\t\t\t\t\tmem_rdata_q[31:20] <= {4\'b0, mem_rdata_latched[3:2], mem_rdata_latched[12], mem_rdata_latched[6:4], 2\'b00};
\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b 010;
\t\t\t\t\t\tend
\t\t\t\t\t\t3\'b100: begin
\t\t\t\t\t\t\tif (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] == 0) begin // C.JR
\t\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b000;
\t\t\t\t\t\t\t\tmem_rdata_q[31:20] <= 12\'b0;
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tif (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV
\t\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b000;
\t\t\t\t\t\t\t\tmem_rdata_q[31:25] <= 7\'b0000000;
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tif (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR
\t\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b000;
\t\t\t\t\t\t\t\tmem_rdata_q[31:20] <= 12\'b0;
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tif (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD
\t\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b000;
\t\t\t\t\t\t\t\tmem_rdata_q[31:25] <= 7\'b0000000;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\t\t3\'b110: begin // C.SWSP
\t\t\t\t\t\t\t{mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {4\'b0, mem_rdata_latched[8:7], mem_rdata_latched[12:9], 2\'b00};
\t\t\t\t\t\t\tmem_rdata_q[14:12] <= 3\'b 010;
\t\t\t\t\t\tend
\t\t\t\t\tendcase
\t\t\t\tend
\t\t\tendcase
\t\tend
\tend
\talways @(posedge clk) begin
\t\tif (resetn && !trap) begin
\t\t\tif (mem_do_prefetch || mem_do_rinst || mem_do_rdata)
\t\t\t\t`assert(!mem_do_wdata);
\t\t\tif (mem_do_prefetch || mem_do_rinst)
\t\t\t\t`assert(!mem_do_rdata);
\t\t\tif (mem_do_rdata)
\t\t\t\t`assert(!mem_do_prefetch && !mem_do_rinst);
\t\t\tif (mem_do_wdata)
\t\t\t\t`assert(!(mem_do_prefetch || mem_do_rinst || mem_do_rdata));
\t\t\tif (mem_state == 2 || mem_state == 3)
\t\t\t\t`assert(mem_valid || mem_do_prefetch);
\t\tend
\tend
\talways @(posedge clk) begin
\t\tif (!resetn || trap) begin
\t\t\tif (!resetn)
\t\t\t\tmem_state <= 0;
\t\t\tif (!resetn || mem_ready)
\t\t\t\tmem_valid <= 0;
\t\t\tmem_la_secondword <= 0;
\t\t\tprefetched_high_word <= 0;
\t\tend else begin
\t\t\tif (mem_la_read || mem_la_write) begin
\t\t\t\tmem_addr <= mem_la_addr;
\t\t\t\tmem_wstrb <= mem_la_wstrb & {4{mem_la_write}};
\t\t\tend
\t\t\tif (mem_la_write) begin
\t\t\t\tmem_wdata <= mem_la_wdata;
\t\t\tend
\t\t\tcase (mem_state)
\t\t\t\t0: begin
\t\t\t\t\tif (mem_do_prefetch || mem_do_rinst || mem_do_rdata) begin
\t\t\t\t\t\tmem_valid <= !mem_la_use_prefetched_high_word;
\t\t\t\t\t\tmem_instr <= mem_do_prefetch || mem_do_rinst;
\t\t\t\t\t\tmem_wstrb <= 0;
\t\t\t\t\t\tmem_state <= 1;
\t\t\t\t\tend
\t\t\t\t\tif (mem_do_wdata) begin
\t\t\t\t\t\tmem_valid <= 1;
\t\t\t\t\t\tmem_instr <= 0;
\t\t\t\t\t\tmem_state <= 2;
\t\t\t\t\tend
\t\t\t\tend
\t\t\t\t1: begin
\t\t\t\t\t`assert(mem_wstrb == 0);
\t\t\t\t\t`assert(mem_do_prefetch || mem_do_rinst || mem_do_rdata);
\t\t\t\t\t`assert(mem_valid == !mem_la_use_prefetched_high_word);
\t\t\t\t\t`assert(mem_instr == (mem_do_prefetch || mem_do_rinst));
\t\t\t\t\tif (mem_xfer) begin
\t\t\t\t\t\tif (COMPRESSED_ISA && mem_la_read) begin
\t\t\t\t\t\t\tmem_valid <= 1;
\t\t\t\t\t\t\tmem_la_secondword <= 1;
\t\t\t\t\t\t\tif (!mem_la_use_prefetched_high_word)
\t\t\t\t\t\t\t\tmem_16bit_buffer <= mem_rdata[31:16];
\t\t\t\t\t\tend else begin
\t\t\t\t\t\t\tmem_valid <= 0;
\t\t\t\t\t\t\tmem_la_secondword <= 0;
\t\t\t\t\t\t\tif (COMPRESSED_ISA && !mem_do_rdata) begin
\t\t\t\t\t\t\t\tif (~&mem_rdata[1:0] || mem_la_secondword) begin
\t\t\t\t\t\t\t\t\tmem_16bit_buffer <= mem_rdata[31:16];
\t\t\t\t\t\t\t\t\tprefetched_high_word <= 1;
\t\t\t\t\t\t\t\tend else begin
\t\t\t\t\t\t\t\t\tprefetched_high_word <= 0;
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tmem_state <= mem_do_rinst || mem_do_rdata ? 0 : 3;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tend
\t\t\t\t2: begin
\t\t\t\t\t`assert(mem_wstrb != 0);
\t\t\t\t\t`assert(mem_do_wdata);
\t\t\t\t\tif (mem_xfer) begin
\t\t\t\t\t\tmem_valid <= 0;
\t\t\t\t\t\tmem_state <= 0;
\t\t\t\t\tend
\t\t\t\tend
\t\t\t\t3: begin
\t\t\t\t\t`assert(mem_wstrb == 0);
\t\t\t\t\t`assert(mem_do_prefetch);
\t\t\t\t\tif (mem_do_rinst) begin
\t\t\t\t\t\tmem_state <= 0;
\t\t\t\t\tend
\t\t\t\tend
\t\t\tendcase
\t\tend
\t\tif (clear_prefetched_high_word)
\t\t\tprefetched_high_word <= 0;
\tend
\t// Instruction Decoder
\treg instr_lui, instr_auipc, instr_jal, instr_jalr;
\treg instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu;
\treg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw;
\treg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai;
\treg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and;
\treg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak;
\treg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer;
reg instr_delint;
\twire instr_trap;
\treg [regindex_bits-1:0] decoded_rd, decoded_rs1, decoded_rs2;
\treg [31:0] decoded_imm, decoded_imm_uj;
\treg decoder_trigger;
\treg decoder_trigger_q;
\treg decoder_pseudo_trigger;
\treg decoder_pseudo_trigger_q;
\treg compressed_instr;
\treg is_lui_auipc_jal;
\treg is_lb_lh_lw_lbu_lhu;
\treg is_slli_srli_srai;
\treg is_jalr_addi_slti_sltiu_xori_ori_andi;
\treg is_sb_sh_sw;
\treg is_sll_srl_sra;
\treg is_lui_auipc_jal_jalr_addi_add_sub;
\treg is_slti_blt_slt;
\treg is_sltiu_bltu_sltu;
\treg is_beq_bne_blt_bge_bltu_bgeu;
\treg is_lbu_lhu_lw;
\treg is_alu_reg_imm;
\treg is_alu_reg_reg;
\treg is_compare;
\tassign instr_trap = (CATCH_ILLINSN || WITH_PCPI) && !{instr_lui, instr_auipc, instr_jal, instr_jalr,
\t\t\tinstr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu,
\t\t\tinstr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw,
\t\t\tinstr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai,
\t\t\tinstr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and,
\t\t\tinstr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh,
\t\t\tinstr_getq, instr_setq, instr_delint, instr_retirq, instr_maskirq, instr_waitirq, instr_timer};
\t
\twire is_rdcycle_rdcycleh_rdinstr_rdinstrh;
\tassign is_rdcycle_rdcycleh_rdinstr_rdinstrh = |{instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh};
\treg [63:0] new_ascii_instr;
\t`FORMAL_KEEP reg [63:0] dbg_ascii_instr;
\t`FORMAL_KEEP reg [31:0] dbg_insn_imm;
\t`FORMAL_KEEP reg [4:0] dbg_insn_rs1;
\t`FORMAL_KEEP reg [4:0] dbg_insn_rs2;
\t`FORMAL_KEEP reg [4:0] dbg_insn_rd;
\t`FORMAL_KEEP reg [31:0] dbg_rs1val;
\t`FORMAL_KEEP reg [31:0] dbg_rs2val;
\t`FORMAL_KEEP reg dbg_rs1val_valid;
\t`FORMAL_KEEP reg dbg_rs2val_valid;
\talways @* begin
\t\tnew_ascii_instr = "";
\t\tif (instr_lui) new_ascii_instr = "lui";
\t\tif (instr_auipc) new_ascii_instr = "auipc";
\t\tif (instr_jal) new_ascii_instr = "jal";
\t\tif (instr_jalr) new_ascii_instr = "jalr";
\t\tif (instr_beq) new_ascii_instr = "beq";
\t\tif (instr_bne) new_ascii_instr = "bne";
\t\tif (instr_blt) new_ascii_instr = "blt";
\t\tif (instr_bge) new_ascii_instr = "bge";
\t\tif (instr_bltu) new_ascii_instr = "bltu";
\t\tif (instr_bgeu) new_ascii_instr = "bgeu";
\t\tif (instr_lb) new_ascii_instr = "lb";
\t\tif (instr_lh) new_ascii_instr = "lh";
\t\tif (instr_lw) new_ascii_instr = "lw";
\t\tif (instr_lbu) new_ascii_instr = "lbu";
\t\tif (instr_lhu) new_ascii_instr = "lhu";
\t\tif (instr_sb) new_ascii_instr = "sb";
\t\tif (instr_sh) new_ascii_instr = "sh";
\t\tif (instr_sw) new_ascii_instr = "sw";
\t\tif (instr_addi) new_ascii_instr = "addi";
\t\tif (instr_slti) new_ascii_instr = "slti";
\t\tif (instr_sltiu) new_ascii_instr = "sltiu";
\t\tif (instr_xori) new_ascii_instr = "xori";
\t\tif (instr_ori) new_ascii_instr = "ori";
\t\tif (instr_andi) new_ascii_instr = "andi";
\t\tif (instr_slli) new_ascii_instr = "slli";
\t\tif (instr_srli) new_ascii_instr = "srli";
\t\tif (instr_srai) new_ascii_instr = "srai";
\t\tif (instr_add) new_ascii_instr = "add";
\t\tif (instr_sub) new_ascii_instr = "sub";
\t\tif (instr_sll) new_ascii_instr = "sll";
\t\tif (instr_slt) new_ascii_instr = "slt";
\t\tif (instr_sltu) new_ascii_instr = "sltu";
\t\tif (instr_xor) new_ascii_instr = "xor";
\t\tif (instr_srl) new_ascii_instr = "srl";
\t\tif (instr_sra) new_ascii_instr = "sra";
\t\tif (instr_or) new_ascii_instr = "or";
\t\tif (instr_and) new_ascii_instr = "and";
\t\tif (instr_rdcycle) new_ascii_instr = "rdcycle";
\t\tif (instr_rdcycleh) new_ascii_instr = "rdcycleh";
\t\tif (instr_rdinstr) new_ascii_instr = "rdinstr";
\t\tif (instr_rdinstrh) new_ascii_instr = "rdinstrh";
\t\tif (instr_getq) new_ascii_instr = "getq";
\t\tif (instr_setq) new_ascii_instr = "setq";
if (instr_delint) new_ascii_instr = "delint";
\t\tif (instr_retirq) new_ascii_instr = "retirq";
\t\tif (instr_maskirq) new_ascii_instr = "maskirq";
\t\tif (instr_waitirq) new_ascii_instr = "waitirq";
\t\tif (instr_timer) new_ascii_instr = "timer";
\tend
\treg [63:0] q_ascii_instr;
\treg [31:0] q_insn_imm;
\treg [31:0] q_insn_opcode;
\treg [4:0] q_insn_rs1;
\treg [4:0] q_insn_rs2;
\treg [4:0] q_insn_rd;
\treg dbg_next;
\twire launch_next_insn;
\treg dbg_valid_insn;
\treg [63:0] cached_ascii_instr;
\treg [31:0] cached_insn_imm;
\treg [31:0] cached_insn_opcode;
\treg [4:0] cached_insn_rs1;
\treg [4:0] cached_insn_rs2;
\treg [4:0] cached_insn_rd;
\talways @(posedge clk) begin
\t\tq_ascii_instr <= dbg_ascii_instr;
\t\tq_insn_imm <= dbg_insn_imm;
\t\tq_insn_opcode <= dbg_insn_opcode;
\t\tq_insn_rs1 <= dbg_insn_rs1;
\t\tq_insn_rs2 <= dbg_insn_rs2;
\t\tq_insn_rd <= dbg_insn_rd;
\t\tdbg_next <= launch_next_insn;
\t\tif (!resetn || trap)
\t\t\tdbg_valid_insn <= 0;
\t\telse if (launch_next_insn)
\t\t\tdbg_valid_insn <= 1;
\t\tif (decoder_trigger_q) begin
\t\t\tcached_ascii_instr <= new_ascii_instr;
\t\t\tcached_insn_imm <= decoded_imm;
\t\t\tif (&next_insn_opcode[1:0])
\t\t\t\tcached_insn_opcode <= next_insn_opcode;
\t\t\telse
\t\t\t\tcached_insn_opcode <= {16\'b0, next_insn_opcode[15:0]};
\t\t\tcached_insn_rs1 <= decoded_rs1;
\t\t\tcached_insn_rs2 <= decoded_rs2;
\t\t\tcached_insn_rd <= decoded_rd;
\t\tend
\t\tif (launch_next_insn) begin
\t\t\tdbg_insn_addr <= next_pc;
\t\tend
\tend
\talways @* begin
\t\tdbg_ascii_instr = q_ascii_instr;
\t\tdbg_insn_imm = q_insn_imm;
\t\tdbg_insn_opcode = q_insn_opcode;
\t\tdbg_insn_rs1 = q_insn_rs1;
\t\tdbg_insn_rs2 = q_insn_rs2;
\t\tdbg_insn_rd = q_insn_rd;
\t\tif (dbg_next) begin
\t\t\tif (decoder_pseudo_trigger_q) begin
\t\t\t\tdbg_ascii_instr = cached_ascii_instr;
\t\t\t\tdbg_insn_imm = cached_insn_imm;
\t\t\t\tdbg_insn_opcode = cached_insn_opcode;
\t\t\t\tdbg_insn_rs1 = cached_insn_rs1;
\t\t\t\tdbg_insn_rs2 = cached_insn_rs2;
\t\t\t\tdbg_insn_rd = cached_insn_rd;
\t\t\tend else begin
\t\t\t\tdbg_ascii_instr = new_ascii_instr;
\t\t\t\tif (&next_insn_opcode[1:0])
\t\t\t\t\tdbg_insn_opcode = next_insn_opcode;
\t\t\t\telse
\t\t\t\t\tdbg_insn_opcode = {16\'b0, next_insn_opcode[15:0]};
\t\t\t\tdbg_insn_imm = decoded_imm;
\t\t\t\tdbg_insn_rs1 = decoded_rs1;
\t\t\t\tdbg_insn_rs2 = decoded_rs2;
\t\t\t\tdbg_insn_rd = decoded_rd;
\t\t\tend
\t\tend
\tend
`ifdef DEBUGASM
\talways @(posedge clk) begin
\t\tif (dbg_next) begin
\t\t\t$display("debugasm %x %x %s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "*");
\t\tend
\tend
`endif
`ifdef DEBUG
\talways @(posedge clk) begin
\t\tif (dbg_next) begin
\t\t\tif (&dbg_insn_opcode[1:0])
\t\t\t\t$display("DECODE: 0x%08x 0x%08x %-0s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
\t\t\telse
\t\t\t\t$display("DECODE: 0x%08x 0x%04x %-0s", dbg_insn_addr, dbg_insn_opcode[15:0], dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
\t\tend
\tend
`endif
\talways @(posedge clk) begin
\t\tis_lui_auipc_jal <= |{instr_lui, instr_auipc, instr_jal};
\t\tis_lui_auipc_jal_jalr_addi_add_sub <= |{instr_lui, instr_auipc, instr_jal, instr_jalr, instr_addi, instr_add, instr_sub};
\t\tis_slti_blt_slt <= |{instr_slti, instr_blt, instr_slt};
\t\tis_sltiu_bltu_sltu <= |{instr_sltiu, instr_bltu, instr_sltu};
\t\tis_lbu_lhu_lw <= |{instr_lbu, instr_lhu, instr_lw};
\t\tis_compare <= |{is_beq_bne_blt_bge_bltu_bgeu, instr_slti, instr_slt, instr_sltiu, instr_sltu};
\t\tif (mem_do_rinst && mem_done) begin
\t\t\tinstr_lui <= mem_rdata_latched[6:0] == 7\'b0110111;
\t\t\tinstr_auipc <= mem_rdata_latched[6:0] == 7\'b0010111;
\t\t\tinstr_jal <= mem_rdata_latched[6:0] == 7\'b1101111;
\t\t\tinstr_jalr <= mem_rdata_latched[6:0] == 7\'b1100111 && mem_rdata_latched[14:12] == 3\'b000;
\t\t\tinstr_retirq <= mem_rdata_latched[6:0] == 7\'b0001011 && mem_rdata_latched[31:25] == 7\'b0000010 && ENABLE_IRQ;
\t\t\tinstr_waitirq <= mem_rdata_latched[6:0] == 7\'b0001011 && mem_rdata_latched[31:25] == 7\'b0000100 && ENABLE_IRQ;
\t\t\tis_beq_bne_blt_bge_bltu_bgeu <= mem_rdata_latched[6:0] == 7\'b1100011;
\t\t\tis_lb_lh_lw_lbu_lhu <= mem_rdata_latched[6:0] == 7\'b0000011;
\t\t\tis_sb_sh_sw <= mem_rdata_latched[6:0] == 7\'b0100011;
\t\t\tis_alu_reg_imm <= mem_rdata_latched[6:0] == 7\'b0010011;
\t\t\tis_alu_reg_reg <= mem_rdata_latched[6:0] == 7\'b0110011;
\t\t\t{ decoded_imm_uj[31:20], decoded_imm_uj[10:1], decoded_imm_uj[11], decoded_imm_uj[19:12], decoded_imm_uj[0] } <= $signed({mem_rdata_latched[31:12], 1\'b0});
\t\t\tdecoded_rd <= mem_rdata_latched[11:7];
\t\t\tdecoded_rs1 <= mem_rdata_latched[19:15];
\t\t\tdecoded_rs2 <= mem_rdata_latched[24:20];
\t\t\tif (mem_rdata_latched[6:0] == 7\'b0001011 && mem_rdata_latched[31:25] == 7\'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS)
\t\t\t\tdecoded_rs1[regindex_bits-1] <= 1; // instr_getq
\t\t\tif (mem_rdata_latched[6:0] == 7\'b0001011 && mem_rdata_latched[31:25] == 7\'b0000010 && ENABLE_IRQ)
\t\t\t\tdecoded_rs1 <= ENABLE_IRQ_QREGS ? irqregs_offset : 3; // instr_retirq
\t\t\tcompressed_instr <= 0;
\t\t\tif (COMPRESSED_ISA && mem_rdata_latched[1:0] != 2\'b11) begin
\t\t\t\tcompressed_instr <= 1;
\t\t\t\tdecoded_rd <= 0;
\t\t\t\tdecoded_rs1 <= 0;
\t\t\t\tdecoded_rs2 <= 0;
\t\t\t\t{ decoded_imm_uj[31:11], decoded_imm_uj[4], decoded_imm_uj[9:8], decoded_imm_uj[10], decoded_imm_uj[6],
\t\t\t\t decoded_imm_uj[7], decoded_imm_uj[3:1], decoded_imm_uj[5], decoded_imm_uj[0] } <= $signed({mem_rdata_latched[12:2], 1\'b0});
\t\t\t\tcase (mem_rdata_latched[1:0])
\t\t\t\t\t2\'b00: begin // Quadrant 0
\t\t\t\t\t\tcase (mem_rdata_latched[15:13])
\t\t\t\t\t\t\t3\'b000: begin // C.ADDI4SPN
\t\t\t\t\t\t\t\tis_alu_reg_imm <= |mem_rdata_latched[12:5];
\t\t\t\t\t\t\t\tdecoded_rs1 <= 2;
\t\t\t\t\t\t\t\tdecoded_rd <= 8 + mem_rdata_latched[4:2];
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t3\'b010: begin // C.LW
\t\t\t\t\t\t\t\tis_lb_lh_lw_lbu_lhu <= 1;
\t\t\t\t\t\t\t\tdecoded_rs1 <= 8 + mem_rdata_latched[9:7];
\t\t\t\t\t\t\t\tdecoded_rd <= 8 + mem_rdata_latched[4:2];
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t3\'b110: begin // C.SW
\t\t\t\t\t\t\t\tis_sb_sh_sw <= 1;
\t\t\t\t\t\t\t\tdecoded_rs1 <= 8 + mem_rdata_latched[9:7];
\t\t\t\t\t\t\t\tdecoded_rs2 <= 8 + mem_rdata_latched[4:2];
\t\t\t\t\t\t\tend
\t\t\t\t\t\tendcase
\t\t\t\t\tend
\t\t\t\t\t2\'b01: begin // Quadrant 1
\t\t\t\t\t\tcase (mem_rdata_latched[15:13])
\t\t\t\t\t\t\t3\'b000: begin // C.NOP / C.ADDI
\t\t\t\t\t\t\t\tis_alu_reg_imm <= 1;
\t\t\t\t\t\t\t\tdecoded_rd <= mem_rdata_latched[11:7];
\t\t\t\t\t\t\t\tdecoded_rs1 <= mem_rdata_latched[11:7];
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t3\'b001: begin // C.JAL
\t\t\t\t\t\t\t\tinstr_jal <= 1;
\t\t\t\t\t\t\t\tdecoded_rd <= 1;
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t3\'b 010: begin // C.LI
\t\t\t\t\t\t\t\tis_alu_reg_imm <= 1;
\t\t\t\t\t\t\t\tdecoded_rd <= mem_rdata_latched[11:7];
\t\t\t\t\t\t\t\tdecoded_rs1 <= 0;
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t3\'b 011: begin
\t\t\t\t\t\t\t\tif (mem_rdata_latched[12] || mem_rdata_latched[6:2]) begin
\t\t\t\t\t\t\t\t\tif (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP
\t\t\t\t\t\t\t\t\t\tis_alu_reg_imm <= 1;
\t\t\t\t\t\t\t\t\t\tdecoded_rd <= mem_rdata_latched[11:7];
\t\t\t\t\t\t\t\t\t\tdecoded_rs1 <= mem_rdata_latched[11:7];
\t\t\t\t\t\t\t\t\tend else begin // C.LUI
\t\t\t\t\t\t\t\t\t\tinstr_lui <= 1;
\t\t\t\t\t\t\t\t\t\tdecoded_rd <= mem_rdata_latched[11:7];
\t\t\t\t\t\t\t\t\t\tdecoded_rs1 <= 0;
\t\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t3\'b100: begin
\t\t\t\t\t\t\t\tif (!mem_rdata_latched[11] && !mem_rdata_latched[12]) begin // C.SRLI, C.SRAI
\t\t\t\t\t\t\t\t\tis_alu_reg_imm <= 1;
\t\t\t\t\t\t\t\t\tdecoded_rd <= 8 + mem_rdata_latched[9:7];
\t\t\t\t\t\t\t\t\tdecoded_rs1 <= 8 + mem_rdata_latched[9:7];
\t\t\t\t\t\t\t\t\tdecoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\tif (mem_rdata_latched[11:10] == 2\'b10) begin // C.ANDI
\t\t\t\t\t\t\t\t\tis_alu_reg_imm <= 1;
\t\t\t\t\t\t\t\t\tdecoded_rd <= 8 + mem_rdata_latched[9:7];
\t\t\t\t\t\t\t\t\tdecoded_rs1 <= 8 + mem_rdata_latched[9:7];
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\tif (mem_rdata_latched[12:10] == 3\'b011) begin // C.SUB, C.XOR, C.OR, C.AND
\t\t\t\t\t\t\t\t\tis_alu_reg_reg <= 1;
\t\t\t\t\t\t\t\t\tdecoded_rd <= 8 + mem_rdata_latched[9:7];
\t\t\t\t\t\t\t\t\tdecoded_rs1 <= 8 + mem_rdata_latched[9:7];
\t\t\t\t\t\t\t\t\tdecoded_rs2 <= 8 + mem_rdata_latched[4:2];
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t3\'b101: begin // C.J
\t\t\t\t\t\t\t\tinstr_jal <= 1;
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t3\'b110: begin // C.BEQZ
\t\t\t\t\t\t\t\tis_beq_bne_blt_bge_bltu_bgeu <= 1;
\t\t\t\t\t\t\t\tdecoded_rs1 <= 8 + mem_rdata_latched[9:7];
\t\t\t\t\t\t\t\tdecoded_rs2 <= 0;
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t3\'b111: begin // C.BNEZ
\t\t\t\t\t\t\t\tis_beq_bne_blt_bge_bltu_bgeu <= 1;
\t\t\t\t\t\t\t\tdecoded_rs1 <= 8 + mem_rdata_latched[9:7];
\t\t\t\t\t\t\t\tdecoded_rs2 <= 0;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tendcase
\t\t\t\t\tend
\t\t\t\t\t2\'b10: begin // Quadrant 2
\t\t\t\t\t\tcase (mem_rdata_latched[15:13])
\t\t\t\t\t\t\t3\'b000: begin // C.SLLI
\t\t\t\t\t\t\t\tif (!mem_rdata_latched[12]) begin
\t\t\t\t\t\t\t\t\tis_alu_reg_imm <= 1;
\t\t\t\t\t\t\t\t\tdecoded_rd <= mem_rdata_latched[11:7];
\t\t\t\t\t\t\t\t\tdecoded_rs1 <= mem_rdata_latched[11:7];
\t\t\t\t\t\t\t\t\tdecoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t3\'b010: begin // C.LWSP
\t\t\t\t\t\t\t\tif (mem_rdata_latched[11:7]) begin
\t\t\t\t\t\t\t\t\tis_lb_lh_lw_lbu_lhu <= 1;
\t\t\t\t\t\t\t\t\tdecoded_rd <= mem_rdata_latched[11:7];
\t\t\t\t\t\t\t\t\tdecoded_rs1 <= 2;
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t3\'b100: begin
\t\t\t\t\t\t\t\tif (mem_rdata_latched[12] == 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JR
\t\t\t\t\t\t\t\t\tinstr_jalr <= 1;
\t\t\t\t\t\t\t\t\tdecoded_rd <= 0;
\t\t\t\t\t\t\t\t\tdecoded_rs1 <= mem_rdata_latched[11:7];
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\tif (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV
\t\t\t\t\t\t\t\t\tis_alu_reg_reg <= 1;
\t\t\t\t\t\t\t\t\tdecoded_rd <= mem_rdata_latched[11:7];
\t\t\t\t\t\t\t\t\tdecoded_rs1 <= 0;
\t\t\t\t\t\t\t\t\tdecoded_rs2 <= mem_rdata_latched[6:2];
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\tif (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR
\t\t\t\t\t\t\t\t\tinstr_jalr <= 1;
\t\t\t\t\t\t\t\t\tdecoded_rd <= 1;
\t\t\t\t\t\t\t\t\tdecoded_rs1 <= mem_rdata_latched[11:7];
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\tif (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD
\t\t\t\t\t\t\t\t\tis_alu_reg_reg <= 1;
\t\t\t\t\t\t\t\t\tdecoded_rd <= mem_rdata_latched[11:7];
\t\t\t\t\t\t\t\t\tdecoded_rs1 <= mem_rdata_latched[11:7];
\t\t\t\t\t\t\t\t\tdecoded_rs2 <= mem_rdata_latched[6:2];
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t3\'b110: begin // C.SWSP
\t\t\t\t\t\t\t\tis_sb_sh_sw <= 1;
\t\t\t\t\t\t\t\tdecoded_rs1 <= 2;
\t\t\t\t\t\t\t\tdecoded_rs2 <= mem_rdata_latched[6:2];
\t\t\t\t\t\t\tend
\t\t\t\t\t\tendcase
\t\t\t\t\tend
\t\t\t\tendcase
\t\t\tend
\t\tend
\t\tif (decoder_trigger && !decoder_pseudo_trigger) begin
\t\t\tpcpi_insn <= WITH_PCPI ? mem_rdata_q : \'bx;
\t\t\tinstr_beq <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3\'b000;
\t\t\tinstr_bne <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3\'b001;
\t\t\tinstr_blt <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3\'b100;
\t\t\tinstr_bge <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3\'b101;
\t\t\tinstr_bltu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3\'b110;
\t\t\tinstr_bgeu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3\'b111;
\t\t\tinstr_lb <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3\'b000;
\t\t\tinstr_lh <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3\'b001;
\t\t\tinstr_lw <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3\'b010;
\t\t\tinstr_lbu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3\'b100;
\t\t\tinstr_lhu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3\'b101;
\t\t\tinstr_sb <= is_sb_sh_sw && mem_rdata_q[14:12] == 3\'b000;
\t\t\tinstr_sh <= is_sb_sh_sw && mem_rdata_q[14:12] == 3\'b001;
\t\t\tinstr_sw <= is_sb_sh_sw && mem_rdata_q[14:12] == 3\'b010;
\t\t\tinstr_addi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3\'b000;
\t\t\tinstr_slti <= is_alu_reg_imm && mem_rdata_q[14:12] == 3\'b010;
\t\t\tinstr_sltiu <= is_alu_reg_imm && mem_rdata_q[14:12] == 3\'b011;
\t\t\tinstr_xori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3\'b100;
\t\t\tinstr_ori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3\'b110;
\t\t\tinstr_andi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3\'b111;
\t\t\tinstr_slli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3\'b001 && mem_rdata_q[31:25] == 7\'b0000000;
\t\t\tinstr_srli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3\'b101 && mem_rdata_q[31:25] == 7\'b0000000;
\t\t\tinstr_srai <= is_alu_reg_imm && mem_rdata_q[14:12] == 3\'b101 && mem_rdata_q[31:25] == 7\'b0100000;
\t\t\tinstr_add <= is_alu_reg_reg && mem_rdata_q[14:12] == 3\'b000 && mem_rdata_q[31:25] == 7\'b0000000;
\t\t\tinstr_sub <= is_alu_reg_reg && mem_rdata_q[14:12] == 3\'b000 && mem_rdata_q[31:25] == 7\'b0100000;
\t\t\tinstr_sll <= is_alu_reg_reg && mem_rdata_q[14:12] == 3\'b001 && mem_rdata_q[31:25] == 7\'b0000000;
\t\t\tinstr_slt <= is_alu_reg_reg && mem_rdata_q[14:12] == 3\'b010 && mem_rdata_q[31:25] == 7\'b0000000;
\t\t\tinstr_sltu <= is_alu_reg_reg && mem_rdata_q[14:12] == 3\'b011 && mem_rdata_q[31:25] == 7\'b0000000;
\t\t\tinstr_xor <= is_alu_reg_reg && mem_rdata_q[14:12] == 3\'b100 && mem_rdata_q[31:25] == 7\'b0000000;
\t\t\tinstr_srl <= is_alu_reg_reg && mem_rdata_q[14:12] == 3\'b101 && mem_rdata_q[31:25] == 7\'b0000000;
\t\t\tinstr_sra <= is_alu_reg_reg && mem_rdata_q[14:12] == 3\'b101 && mem_rdata_q[31:25] == 7\'b0100000;
\t\t\tinstr_or <= is_alu_reg_reg && mem_rdata_q[14:12] == 3\'b110 && mem_rdata_q[31:25] == 7\'b0000000;
\t\t\tinstr_and <= is_alu_reg_reg && mem_rdata_q[14:12] == 3\'b111 && mem_rdata_q[31:25] == 7\'b0000000;
\t\t\tinstr_rdcycle <= ((mem_rdata_q[6:0] == 7\'b1110011 && mem_rdata_q[31:12] == \'b11000000000000000010) ||
\t\t\t (mem_rdata_q[6:0] == 7\'b1110011 && mem_rdata_q[31:12] == \'b11000000000100000010)) && ENABLE_COUNTERS;
\t\t\tinstr_rdcycleh <= ((mem_rdata_q[6:0] == 7\'b1110011 && mem_rdata_q[31:12] == \'b11001000000000000010) ||
\t\t\t (mem_rdata_q[6:0] == 7\'b1110011 && mem_rdata_q[31:12] == \'b11001000000100000010)) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
\t\t\tinstr_rdinstr <= (mem_rdata_q[6:0] == 7\'b1110011 && mem_rdata_q[31:12] == \'b11000000001000000010) && ENABLE_COUNTERS;
\t\t\tinstr_rdinstrh <= (mem_rdata_q[6:0] == 7\'b1110011 && mem_rdata_q[31:12] == \'b11001000001000000010) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
\t\t\tinstr_ecall_ebreak <= ((mem_rdata_q[6:0] == 7\'b1110011 && !mem_rdata_q[31:21] && !mem_rdata_q[19:7]) ||
\t\t\t\t\t(COMPRESSED_ISA && mem_rdata_q[15:0] == 16\'h9002));
\t\t\tinstr_getq <= mem_rdata_q[6:0] == 7\'b0001011 && mem_rdata_q[31:25] == 7\'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
\t\t\tinstr_setq <= mem_rdata_q[6:0] == 7\'b0001011 && mem_rdata_q[31:25] == 7\'b0000001 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
instr_delint <= mem_rdata_q[6:0] == 7\'b0001011 && mem_rdata_q[31:25] == 7\'b0000110 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
\t\t\tinstr_maskirq <= mem_rdata_q[6:0] == 7\'b0001011 && mem_rdata_q[31:25] == 7\'b0000011 && ENABLE_IRQ;
\t\t\tinstr_timer <= mem_rdata_q[6:0] == 7\'b0001011 && mem_rdata_q[31:25] == 7\'b0000101 && ENABLE_IRQ && ENABLE_IRQ_TIMER;
\t\t\tis_slli_srli_srai <= is_alu_reg_imm && |{
\t\t\t\tmem_rdata_q[14:12] == 3\'b001 && mem_rdata_q[31:25] == 7\'b0000000,
\t\t\t\tmem_rdata_q[14:12] == 3\'b101 && mem_rdata_q[31:25] == 7\'b0000000,
\t\t\t\tmem_rdata_q[14:12] == 3\'b101 && mem_rdata_q[31:25] == 7\'b0100000
\t\t\t};
\t\t\tis_jalr_addi_slti_sltiu_xori_ori_andi <= instr_jalr || is_alu_reg_imm && |{
\t\t\t\tmem_rdata_q[14:12] == 3\'b000,
\t\t\t\tmem_rdata_q[14:12] == 3\'b010,
\t\t\t\tmem_rdata_q[14:12] == 3\'b011,
\t\t\t\tmem_rdata_q[14:12] == 3\'b100,
\t\t\t\tmem_rdata_q[14:12] == 3\'b110,
\t\t\t\tmem_rdata_q[14:12] == 3\'b111
\t\t\t};
\t\t\tis_sll_srl_sra <= is_alu_reg_reg && |{
\t\t\t\tmem_rdata_q[14:12] == 3\'b001 && mem_rdata_q[31:25] == 7\'b0000000,
\t\t\t\tmem_rdata_q[14:12] == 3\'b101 && mem_rdata_q[31:25] == 7\'b0000000,
\t\t\t\tmem_rdata_q[14:12] == 3\'b101 && mem_rdata_q[31:25] == 7\'b0100000
\t\t\t};
\t\t\tis_lui_auipc_jal_jalr_addi_add_sub <= 0;
\t\t\tis_compare <= 0;
\t\t\t(* parallel_case *)
\t\t\tcase (1\'b1)
\t\t\t\tinstr_jal:
\t\t\t\t\tdecoded_imm <= decoded_imm_uj;
\t\t\t\t|{instr_lui, instr_auipc}:
\t\t\t\t\tdecoded_imm <= mem_rdata_q[31:12] << 12;
\t\t\t\t|{instr_jalr, is_lb_lh_lw_lbu_lhu, is_alu_reg_imm}:
\t\t\t\t\tdecoded_imm <= $signed(mem_rdata_q[31:20]);
\t\t\t\tis_beq_bne_blt_bge_bltu_bgeu:
\t\t\t\t\tdecoded_imm <= $signed({mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8], 1\'b0});
\t\t\t\tis_sb_sh_sw:
\t\t\t\t\tdecoded_imm <= $signed({mem_rdata_q[31:25], mem_rdata_q[11:7]});
\t\t\t\tdefault:
\t\t\t\t\tdecoded_imm <= 1\'bx;
\t\t\tendcase
\t\tend
\t\tif (!resetn) begin
\t\t\tis_beq_bne_blt_bge_bltu_bgeu <= 0;
\t\t\tis_compare <= 0;
\t\t\tinstr_beq <= 0;
\t\t\tinstr_bne <= 0;
\t\t\tinstr_blt <= 0;
\t\t\tinstr_bge <= 0;
\t\t\tinstr_bltu <= 0;
\t\t\tinstr_bgeu <= 0;
\t\t\tinstr_addi <= 0;
\t\t\tinstr_slti <= 0;
\t\t\tinstr_sltiu <= 0;
\t\t\tinstr_xori <= 0;
\t\t\tinstr_ori <= 0;
\t\t\tinstr_andi <= 0;
\t\t\tinstr_add <= 0;
\t\t\tinstr_sub <= 0;
\t\t\tinstr_sll <= 0;
\t\t\tinstr_slt <= 0;
\t\t\tinstr_sltu <= 0;
\t\t\tinstr_xor <= 0;
\t\t\tinstr_srl <= 0;
\t\t\tinstr_sra <= 0;
\t\t\tinstr_or <= 0;
\t\t\tinstr_and <= 0;
\t\tend
\tend
\t// Main State Machine
\tlocalparam cpu_state_trap = 8\'b10000000;
\tlocalparam cpu_state_fetch = 8\'b01000000;
\tlocalparam cpu_state_ld_rs1 = 8\'b00100000;
\tlocalparam cpu_state_ld_rs2 = 8\'b00010000;
\tlocalparam cpu_state_exec = 8\'b00001000;
\tlocalparam cpu_state_shift = 8\'b00000100;
\tlocalparam cpu_state_stmem = 8\'b00000010;
\tlocalparam cpu_state_ldmem = 8\'b00000001;
\treg [7:0] cpu_state;
\treg [1:0] irq_state;
\t`FORMAL_KEEP reg [127:0] dbg_ascii_state;
\talways @* begin
\t\tdbg_ascii_state = "";
\t\tif (cpu_state == cpu_state_trap) dbg_ascii_state = "trap";
\t\tif (cpu_state == cpu_state_fetch) dbg_ascii_state = "fetch";
\t\tif (cpu_state == cpu_state_ld_rs1) dbg_ascii_state = "ld_rs1";
\t\tif (cpu_state == cpu_state_ld_rs2) dbg_ascii_state = "ld_rs2";
\t\tif (cpu_state == cpu_state_exec) dbg_ascii_state = "exec";
\t\tif (cpu_state == cpu_state_shift) dbg_ascii_state = "shift";
\t\tif (cpu_state == cpu_state_stmem) dbg_ascii_state = "stmem";
\t\tif (cpu_state == cpu_state_ldmem) dbg_ascii_state = "ldmem";
\tend
\treg set_mem_do_rinst;
\treg set_mem_do_rdata;
\treg set_mem_do_wdata;
\treg latched_store;
\treg latched_stalu;
\treg latched_branch;
\treg latched_compr;
\treg latched_trace;
\treg latched_is_lu;
\treg latched_is_lh;
\treg latched_is_lb;
\treg [regindex_bits-1:0] latched_rd;
\treg [31:0] current_pc;
\tassign next_pc = latched_store && latched_branch ? reg_out & ~1 : reg_next_pc;
\treg [3:0] pcpi_timeout_counter;
\treg pcpi_timeout;
\treg [31:0] next_irq_pending;
\treg do_waitirq;
\treg [31:0] alu_out, alu_out_q;
\treg alu_out_0, alu_out_0_q;
\treg alu_wait, alu_wait_2;
\treg [31:0] alu_add_sub;
\treg [31:0] alu_shl, alu_shr;
\treg alu_eq, alu_ltu, alu_lts;
\tgenerate if (TWO_CYCLE_ALU) begin
\t\talways @(posedge clk) begin
\t\t\talu_add_sub <= instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
\t\t\talu_eq <= reg_op1 == reg_op2;
\t\t\talu_lts <= $signed(reg_op1) < $signed(reg_op2);
\t\t\talu_ltu <= reg_op1 < reg_op2;
\t\t\talu_shl <= reg_op1 << reg_op2[4:0];
\t\t\talu_shr <= $signed({instr_sra || instr_srai ? reg_op1[31] : 1\'b0, reg_op1}) >>> reg_op2[4:0];
\t\tend
\tend else begin
\t\talways @* begin
\t\t\talu_add_sub = instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
\t\t\talu_eq = reg_op1 == reg_op2;
\t\t\talu_lts = $signed(reg_op1) < $signed(reg_op2);
\t\t\talu_ltu = reg_op1 < reg_op2;
\t\t\talu_shl = reg_op1 << reg_op2[4:0];
\t\t\talu_shr = $signed({instr_sra || instr_srai ? reg_op1[31] : 1\'b0, reg_op1}) >>> reg_op2[4:0];
\t\tend
\tend endgenerate
\talways @* begin
\t\talu_out_0 = \'bx;
\t\t(* parallel_case, full_case *)
\t\tcase (1\'b1)
\t\t\tinstr_beq:
\t\t\t\talu_out_0 = alu_eq;
\t\t\tinstr_bne:
\t\t\t\talu_out_0 = !alu_eq;
\t\t\tinstr_bge:
\t\t\t\talu_out_0 = !alu_lts;
\t\t\tinstr_bgeu:
\t\t\t\talu_out_0 = !alu_ltu;
\t\t\tis_slti_blt_slt && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
\t\t\t\talu_out_0 = alu_lts;
\t\t\tis_sltiu_bltu_sltu && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
\t\t\t\talu_out_0 = alu_ltu;
\t\tendcase
\t\talu_out = \'bx;
\t\t(* parallel_case, full_case *)
\t\tcase (1\'b1)
\t\t\tis_lui_auipc_jal_jalr_addi_add_sub:
\t\t\t\talu_out = alu_add_sub;
\t\t\tis_compare:
\t\t\t\talu_out = alu_out_0;
\t\t\tinstr_xori || instr_xor:
\t\t\t\talu_out = reg_op1 ^ reg_op2;
\t\t\tinstr_ori || instr_or:
\t\t\t\talu_out = reg_op1 | reg_op2;
\t\t\tinstr_andi || instr_and:
\t\t\t\talu_out = reg_op1 & reg_op2;
\t\t\tBARREL_SHIFTER && (instr_sll || instr_slli):
\t\t\t\talu_out = alu_shl;
\t\t\tBARREL_SHIFTER && (instr_srl || instr_srli || instr_sra || instr_srai):
\t\t\t\talu_out = alu_shr;
\t\tendcase
`ifdef RISCV_FORMAL_BLACKBOX_ALU
\t\talu_out_0 = $anyseq;
\t\talu_out = $anyseq;
`endif
\tend
\treg clear_prefetched_high_word_q;
\talways @(posedge clk) clear_prefetched_high_word_q <= clear_prefetched_high_word;
\talways @* begin
\t\tclear_prefetched_high_word = clear_prefetched_high_word_q;
\t\tif (!prefetched_high_word)
\t\t\tclear_prefetched_high_word = 0;
\t\tif (latched_branch || irq_state || !resetn)
\t\t\tclear_prefetched_high_word = COMPRESSED_ISA;
\tend
\treg cpuregs_write;
\treg [31:0] cpuregs_wrdata;
\treg [31:0] cpuregs_rs1;
\treg [31:0] cpuregs_rs'b'2;
\treg [regindex_bits-1:0] decoded_rs;
\talways @* begin
\t\tcpuregs_write = 0;
\t\tcpuregs_wrdata = \'bx;
\t\tif (cpu_state == cpu_state_fetch) begin
\t\t\t(* parallel_case *)
\t\t\tcase (1\'b1)
\t\t\t\tlatched_branch: begin
\t\t\t\t\tcpuregs_wrdata = reg_pc + (latched_compr ? 2 : 4);
\t\t\t\t\tcpuregs_write = 1;
\t\t\t\tend
\t\t\t\tlatched_store && !latched_branch: begin
\t\t\t\t\tcpuregs_wrdata = latched_stalu ? alu_out_q : reg_out;
\t\t\t\t\tcpuregs_write = 1;
\t\t\t\tend
\t\t\t\tENABLE_IRQ && irq_state[0]: begin
\t\t\t\t\tcpuregs_wrdata = reg_next_pc | latched_compr;
\t\t\t\t\tcpuregs_write = 1;
\t\t\t\tend
\t\t\t\tENABLE_IRQ && irq_state[1]: begin
\t\t\t\t\tcpuregs_wrdata = irq_pending & ~irq_mask;
\t\t\t\t\tcpuregs_write = 1;
\t\t\t\tend
\t\t\tendcase
\t\tend
\tend
\talways @(posedge clk) begin
\t\tif (resetn && cpuregs_write)
\t\t\tcpuregs[latched_rd] <= cpuregs_wrdata;
\tend
\talways @* begin
\t\tdecoded_rs = \'bx;
\t\tif (ENABLE_REGS_DUALPORT) begin
`ifndef RISCV_FORMAL_BLACKBOX_REGS
\t\t\tcpuregs_rs1 = decoded_rs1 ? cpuregs[decoded_rs1] : 0;
\t\t\tcpuregs_rs2 = decoded_rs2 ? cpuregs[decoded_rs2] : 0;
`else
\t\t\tcpuregs_rs1 = decoded_rs1 ? $anyseq : 0;
\t\t\tcpuregs_rs2 = decoded_rs2 ? $anyseq : 0;
`endif
\t\tend else begin
\t\t\tdecoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
`ifndef RISCV_FORMAL_BLACKBOX_REGS
\t\t\tcpuregs_rs1 = decoded_rs ? cpuregs[decoded_rs] : 0;
`else
\t\t\tcpuregs_rs1 = decoded_rs ? $anyseq : 0;
`endif
\t\t\tcpuregs_rs2 = cpuregs_rs1;
\t\tend
\tend
\tassign launch_next_insn = cpu_state == cpu_state_fetch && decoder_trigger && (!ENABLE_IRQ || irq_delay || irq_active || !(irq_pending & ~irq_mask));
\talways @(posedge clk) begin
\t\ttrap <= 0;
\t\treg_sh <= \'bx;
\t\treg_out <= \'bx;
\t\tset_mem_do_rinst = 0;
\t\tset_mem_do_rdata = 0;
\t\tset_mem_do_wdata = 0;
\t\talu_out_0_q <= alu_out_0;
\t\talu_out_q <= alu_out;
\t\talu_wait <= 0;
\t\talu_wait_2 <= 0;
\t\tif (launch_next_insn) begin
\t\t\tdbg_rs1val <= \'bx;
\t\t\tdbg_rs2val <= \'bx;
\t\t\tdbg_rs1val_valid <= 0;
\t\t\tdbg_rs2val_valid <= 0;
\t\tend
\t\tif (WITH_PCPI && CATCH_ILLINSN) begin
\t\t\tif (resetn && pcpi_valid && !pcpi_int_wait) begin
\t\t\t\tif (pcpi_timeout_counter)
\t\t\t\t\tpcpi_timeout_counter <= pcpi_timeout_counter - 1;
\t\t\tend else
\t\t\t\tpcpi_timeout_counter <= ~0;
\t\t\tpcpi_timeout <= !pcpi_timeout_counter;
\t\tend
\t\tif (ENABLE_COUNTERS) begin
\t\t\tcount_cycle <= resetn ? count_cycle + 1 : 0;
\t\t\tif (!ENABLE_COUNTERS64) count_cycle[63:32] <= 0;
\t\tend else begin
\t\t\tcount_cycle <= \'bx;
\t\t\tcount_instr <= \'bx;
\t\tend
\t\tnext_irq_pending = ENABLE_IRQ ? irq_pending & LATCHED_IRQ : \'bx;
\t\tif (ENABLE_IRQ && ENABLE_IRQ_TIMER && timer) begin
\t\t\tif (timer - 1 == 0)
\t\t\t\tnext_irq_pending[irq_timer] = 1;
\t\t\ttimer <= timer - 1;
\t\tend
\t\tif (ENABLE_IRQ) begin
\t\t\tnext_irq_pending = next_irq_pending | irq;
\t\tend
\t\tdecoder_trigger <= mem_do_rinst && mem_done;
\t\tdecoder_trigger_q <= decoder_trigger;
\t\tdecoder_pseudo_trigger <= 0;
\t\tdecoder_pseudo_trigger_q <= decoder_pseudo_trigger;
\t\tdo_waitirq <= 0;
\t\ttrace_valid <= 0;
\t\tif (!ENABLE_TRACE)
\t\t\ttrace_data <= \'bx;
\t\tif (!resetn) begin
\t\t\treg_pc <= PROGADDR_RESET;
\t\t\treg_next_pc <= PROGADDR_RESET;
\t\t\tif (ENABLE_COUNTERS)
\t\t\t\tcount_instr <= 0;
\t\t\tlatched_store <= 0;
\t\t\tlatched_stalu <= 0;
\t\t\tlatched_branch <= 0;
\t\t\tlatched_trace <= 0;
\t\t\tlatched_is_lu <= 0;
\t\t\tlatched_is_lh <= 0;
\t\t\tlatched_is_lb <= 0;
\t\t\tpcpi_valid <= 0;
\t\t\tpcpi_timeout <= 0;
\t\t\tirq_active <= 0;
\t\t\tirq_delay <= 0;
\t\t\tirq_mask <= ~0;
\t\t\tnext_irq_pending = 0;
\t\t\tirq_state <= 0;
\t\t\teoi <= 0;
\t\t\ttimer <= 0;
\t\t\tif (~STACKADDR) begin
\t\t\t\tlatched_store <= 1;
\t\t\t\tlatched_rd <= 2;
\t\t\t\treg_out <= STACKADDR;
\t\t\tend
\t\t\tcpu_state <= cpu_state_fetch;
if (ENABLE_IRQ_QREGS)
\t\t\t\tcpuregs[delintregnum] <= 0;
\t\tend else
\t\t(* parallel_case, full_case *)
\t\tcase (cpu_state)
\t\t\tcpu_state_trap: begin
\t\t\t\ttrap <= 1;
\t\t\tend
\t\t\tcpu_state_fetch: begin
\t\t\t\tmem_do_rinst <= !decoder_trigger && !do_waitirq;
\t\t\t\tmem_wordsize <= 0;
\t\t\t\tcurrent_pc = reg_next_pc;
\t\t\t\t(* parallel_case *)
\t\t\t\tcase (1\'b1)
\t\t\t\t\tlatched_branch: begin
\t\t\t\t\t\tcurrent_pc = latched_store ? (latched_stalu ? alu_out_q : reg_out) & ~1 : reg_next_pc;
\t\t\t\t\t\t`debug($display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + (latched_compr ? 2 : 4), current_pc);)
\t\t\t\t\t\tcpuregs[latched_rd] <= reg_pc + (latched_compr ? 2 : 4);
\t\t\t\t\tend
\t\t\t\t\tlatched_store && !latched_branch: begin
\t\t\t\t\t\t`debug($display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out);)
\t\t\t\t\t\tcpuregs[latched_rd] <= latched_stalu ? alu_out_q : reg_out;
\t\t\t\t\tend
\t\t\t\t\tENABLE_IRQ && irq_state[0]: begin
\t\t\t\t\t\tcpuregs[latched_rd] <= current_pc;
\t\t\t\t\t\tcurrent_pc = PROGADDR_IRQ;
\t\t\t\t\t\tirq_active <= 1;
\t\t\t\t\t\tmem_do_rinst <= 1;
\t\t\t\t\tend
\t\t\t\t\tENABLE_IRQ && irq_state[1]: begin
\t\t\t\t\t\teoi <= irq_pending & ~irq_mask;
\t\t\t\t\t\tcpuregs[latched_rd] <= irq_pending & ~irq_mask;
\t\t\t\t\t\tnext_irq_pending = next_irq_pending & irq_mask;
\t\t\t\t\tend
\t\t\t\tendcase
\t\t\t\tif (ENABLE_TRACE && latched_trace) begin
\t\t\t\t\tlatched_trace <= 0;
\t\t\t\t\ttrace_valid <= 1;
\t\t\t\t\tif (latched_branch)
\t\t\t\t\t\ttrace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_BRANCH | (current_pc & 32\'hfffffffe);
\t\t\t\t\telse
\t\t\t\t\t\ttrace_data <= (irq_active ? TRACE_IRQ : 0) | (latched_stalu ? alu_out_q : reg_out);
\t\t\t\tend
\t\t\t\treg_pc <= current_pc;
\t\t\t\treg_next_pc <= current_pc;
\t\t\t\tlatched_store <= 0;
\t\t\t\tlatched_stalu <= 0;
\t\t\t\tlatched_branch <= 0;
\t\t\t\tlatched_is_lu <= 0;
\t\t\t\tlatched_is_lh <= 0;
\t\t\t\tlatched_is_lb <= 0;
\t\t\t\tlatched_rd <= decoded_rd;
\t\t\t\tlatched_compr <= compressed_instr;
\t\t\t\tif (!cpuregs[delintregnum] && ENABLE_IRQ && ((decoder_trigger && !irq_active && !irq_delay && |(irq_pending & ~irq_mask)) || irq_state)) begin
\t\t\t\t\tirq_state <=
\t\t\t\t\t\tirq_state == 2\'b00 ? 2\'b01 :
\t\t\t\t\t\tirq_state == 2\'b01 ? 2\'b10 : 2\'b00;
\t\t\t\t\tlatched_compr <= latched_compr;
\t\t\t\t\tif (ENABLE_IRQ_QREGS)
\t\t\t\t\t\tlatched_rd <= irqregs_offset | irq_state[0];
\t\t\t\t\telse
\t\t\t\t\t latched_rd <= irq_state[0] ? 4 : 3;
\t\t\t\tend else begin
if (ENABLE_IRQ && ((decoder_trigger && !irq_active && |(irq_pending & ~irq_mask)) || irq_state)) begin
if(cpuregs[delintregnum]!=0) cpuregs[delintregnum] <= cpuregs[delintregnum] - 1;
end
if (ENABLE_IRQ && (decoder_trigger || do_waitirq) && instr_waitirq) begin
\t\t\t\t\tif (irq_pending) begin
\t\t\t\t\t\tlatched_store <= 1;
\t\t\t\t\t\treg_out <= irq_pending;
\t\t\t\t\t\treg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
\t\t\t\t\t\tmem_do_rinst <= 1;
\t\t\t\t\tend else
\t\t\t\t\t\tdo_waitirq <= 1;
\t\t\t\tend else
\t\t\t\tif (decoder_trigger) begin
\t\t\t\t\t`debug($display("-- %-0t", $time);)
\t\t\t\t\tirq_delay <= irq_active;
\t\t\t\t\treg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
\t\t\t\t\tif (ENABLE_TRACE)
\t\t\t\t\t\tlatched_trace <= 1;
\t\t\t\t\tif (ENABLE_COUNTERS) begin
\t\t\t\t\t\tcount_instr <= count_instr + 1;
\t\t\t\t\t\tif (!ENABLE_COUNTERS64) count_instr[63:32] <= 0;
\t\t\t\t\tend
\t\t\t\t\tif (instr_jal) begin
\t\t\t\t\t\tmem_do_rinst <= 1;
\t\t\t\t\t\treg_next_pc <= current_pc + decoded_imm_uj;
\t\t\t\t\t\tlatched_branch <= 1;
\t\t\t\t\tend else begin
\t\t\t\t\t\tmem_do_rinst <= 0;
\t\t\t\t\t\tmem_do_prefetch <= !instr_jalr && !instr_retirq;
\t\t\t\t\t\tcpu_state <= cpu_state_ld_rs1;
\t\t\t\t\tend
\t\t\t\tend
end
\t\t\tend
\t\t\tcpu_state_ld_rs1: begin
\t\t\t\treg_op1 <= \'bx;
\t\t\t\treg_op2 <= \'bx;
\t\t\t\t(* parallel_case *)
\t\t\t\tcase (1\'b1)
\t\t\t\t\t(CATCH_ILLINSN || WITH_PCPI) && instr_trap: begin
\t\t\t\t\t\tif (WITH_PCPI) begin
\t\t\t\t\t\t\t`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
\t\t\t\t\t\t\treg_op1 <= cpuregs_rs1;
\t\t\t\t\t\t\tdbg_rs1val <= cpuregs_rs1;
\t\t\t\t\t\t\tdbg_rs1val_valid <= 1;
\t\t\t\t\t\t\tif (ENABLE_REGS_DUALPORT) begin
\t\t\t\t\t\t\t\tpcpi_valid <= 1;
\t\t\t\t\t\t\t\t`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
\t\t\t\t\t\t\t\treg_sh <= cpuregs_rs2;
\t\t\t\t\t\t\t\treg_op2 <= cpuregs_rs2;
\t\t\t\t\t\t\t\tdbg_rs2val <= cpuregs_rs2;
\t\t\t\t\t\t\t\tdbg_rs2val_valid <= 1;
\t\t\t\t\t\t\t\tif (pcpi_int_ready) begin
\t\t\t\t\t\t\t\t\tmem_do_rinst <= 1;
\t\t\t\t\t\t\t\t\tpcpi_valid <= 0;
\t\t\t\t\t\t\t\t\treg_out <= pcpi_int_rd;
\t\t\t\t\t\t\t\t\tlatched_store <= pcpi_int_wr;
\t\t\t\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\t\t\t\tend else
\t\t\t\t\t\t\t\tif (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin
\t\t\t\t\t\t\t\t\tpcpi_valid <= 0;
\t\t\t\t\t\t\t\t\t`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
\t\t\t\t\t\t\t\t\tif (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
\t\t\t\t\t\t\t\t\t\tnext_irq_pending[irq_ebreak] = 1;
\t\t\t\t\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\t\t\t\t\tend else
\t\t\t\t\t\t\t\t\t\tcpu_state <= cpu_state_trap;
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tend else begin
\t\t\t\t\t\t\t\tcpu_state <= cpu_state_ld_rs2;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend else begin
\t\t\t\t\t\t\t`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
\t\t\t\t\t\t\tif (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
\t\t\t\t\t\t\t\tnext_irq_pending[irq_ebreak] = 1;
\t\t\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\t\t\tend else
\t\t\t\t\t\t\t\tcpu_state <= cpu_state_trap;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\t\tENABLE_COUNTERS && is_rdcycle_rdcycleh_rdinstr_rdinstrh: begin
\t\t\t\t\t\t(* parallel_case, full_case *)
\t\t\t\t\t\tcase (1\'b1)
\t\t\t\t\t\t\tinstr_rdcycle:
\t\t\t\t\t\t\t\treg_out <= count_cycle[31:0];
\t\t\t\t\t\t\tinstr_rdcycleh && ENABLE_COUNTERS64:
\t\t\t\t\t\t\t\treg_out <= count_cycle[63:32];
\t\t\t\t\t\t\tinstr_rdinstr:
\t\t\t\t\t\t\t\treg_out <= count_instr[31:0];
\t\t\t\t\t\t\tinstr_rdinstrh && ENABLE_COUNTERS64:
\t\t\t\t\t\t\t\treg_out <= count_instr[63:32];
\t\t\t\t\t\tendcase
\t\t\t\t\t\tlatched_store <= 1;
\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\tend
\t\t\t\t\tis_lui_auipc_jal: begin
\t\t\t\t\t\treg_op1 <= instr_lui ? 0 : reg_pc;
\t\t\t\t\t\treg_op2 <= decoded_imm;
\t\t\t\t\t\tif (TWO_CYCLE_ALU)
\t\t\t\t\t\t\talu_wait <= 1;
\t\t\t\t\t\telse
\t\t\t\t\t\t\tmem_do_rinst <= mem_do_prefetch;
\t\t\t\t\t\tcpu_state <= cpu_state_exec;
\t\t\t\t\tend
\t\t\t\t\tENABLE_IRQ && ENABLE_IRQ_QREGS && instr_getq: begin
\t\t\t\t\t\t`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
\t\t\t\t\t\treg_out <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val_valid <= 1;
\t\t\t\t\t\tlatched_store <= 1;
\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\tend
\t\t\t\t\tENABLE_IRQ && ENABLE_IRQ_QREGS && instr_setq: begin
\t\t\t\t\t\t`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
\t\t\t\t\t\treg_out <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val_valid <= 1;
\t\t\t\t\t\tlatched_rd <= latched_rd | irqregs_offset;
\t\t\t\t\t\tlatched_store <= 1;
\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\tend
ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_delint: begin
\t\t\t\t\t\t`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, decoded_rs1 ? cpuregs[decoded_rs1] : 0);)
\t\t\t\t\t\treg_out <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
\t\t\t\t\t\tlatched_rd <= delintregnum;
\t\t\t\t\t\tlatched_store <= 1;
\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\tend
\t\t\t\t\tENABLE_IRQ && instr_retirq: begin
\t\t\t\t\t\teoi <= 0;
\t\t\t\t\t\tirq_active <= 0;
\t\t\t\t\t\tlatched_branch <= 1;
\t\t\t\t\t\tlatched_store <= 1;
\t\t\t\t\t\t`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
\t\t\t\t\t\treg_out <= CATCH_MISALIGN ? (cpuregs_rs1 & 32\'h fffffffe) : cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val_valid <= 1;
\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\tend
\t\t\t\t\tENABLE_IRQ && instr_maskirq: begin
\t\t\t\t\t\tlatched_store <= 1;
\t\t\t\t\t\treg_out <= irq_mask;
\t\t\t\t\t\t`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
\t\t\t\t\t\tirq_mask <= cpuregs_rs1 | MASKED_IRQ;
\t\t\t\t\t\tdbg_rs1val <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val_valid <= 1;
\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\tend
\t\t\t\t\tENABLE_IRQ && ENABLE_IRQ_TIMER && instr_timer: begin
\t\t\t\t\t\tlatched_store <= 1;
\t\t\t\t\t\treg_out <= timer;
\t\t\t\t\t\t`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
\t\t\t\t\t\ttimer <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val_valid <= 1;
\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\tend
\t\t\t\t\tis_lb_lh_lw_lbu_lhu && !instr_trap: begin
\t\t\t\t\t\t`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
\t\t\t\t\t\treg_op1 <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val_valid <= 1;
\t\t\t\t\t\tcpu_state <= cpu_state_ldmem;
\t\t\t\t\t\tmem_do_rinst <= 1;
\t\t\t\t\tend
\t\t\t\t\tis_slli_srli_srai && !BARREL_SHIFTER: begin
\t\t\t\t\t\t`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
\t\t\t\t\t\treg_op1 <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val_valid <= 1;
\t\t\t\t\t\treg_sh <= decoded_rs2;
\t\t\t\t\t\tcpu_state <= cpu_state_shift;
\t\t\t\t\tend
\t\t\t\t\tis_jalr_addi_slti_sltiu_xori_ori_andi, is_slli_srli_srai && BARREL_SHIFTER: begin
\t\t\t\t\t\t`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
\t\t\t\t\t\treg_op1 <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val_valid <= 1;
\t\t\t\t\t\treg_op2 <= is_slli_srli_srai && BARREL_SHIFTER ? decoded_rs2 : decoded_imm;
\t\t\t\t\t\tif (TWO_CYCLE_ALU)
\t\t\t\t\t\t\talu_wait <= 1;
\t\t\t\t\t\telse
\t\t\t\t\t\t\tmem_do_rinst <= mem_do_prefetch;
\t\t\t\t\t\tcpu_state <= cpu_state_exec;
\t\t\t\t\tend
\t\t\t\t\tdefault: begin
\t\t\t\t\t\t`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
\t\t\t\t\t\treg_op1 <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val <= cpuregs_rs1;
\t\t\t\t\t\tdbg_rs1val_valid <= 1;
\t\t\t\t\t\tif (ENABLE_REGS_DUALPORT) begin
\t\t\t\t\t\t\t`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
\t\t\t\t\t\t\treg_sh <= cpuregs_rs2;
\t\t\t\t\t\t\treg_op2 <= cpuregs_rs2;
\t\t\t\t\t\t\tdbg_rs2val <= cpuregs_rs2;
\t\t\t\t\t\t\tdbg_rs2val_valid <= 1;
\t\t\t\t\t\t\t(* parallel_case *)
\t\t\t\t\t\t\tcase (1\'b1)
\t\t\t\t\t\t\t\tis_sb_sh_sw: begin
\t\t\t\t\t\t\t\t\tcpu_state <= cpu_state_stmem;
\t\t\t\t\t\t\t\t\tmem_do_rinst <= 1;
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\tis_sll_srl_sra && !BARREL_SHIFTER: begin
\t\t\t\t\t\t\t\t\tcpu_state <= cpu_state_shift;
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\tdefault: begin
\t\t\t\t\t\t\t\t\tif (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
\t\t\t\t\t\t\t\t\t\talu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
\t\t\t\t\t\t\t\t\t\talu_wait <= 1;
\t\t\t\t\t\t\t\t\tend else
\t\t\t\t\t\t\t\t\t\tmem_do_rinst <= mem_do_prefetch;
\t\t\t\t\t\t\t\t\tcpu_state <= cpu_state_exec;
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tendcase
\t\t\t\t\t\tend else
\t\t\t\t\t\t\tcpu_state <= cpu_state_ld_rs2;
\t\t\t\t\tend
\t\t\t\tendcase
\t\t\tend
\t\t\tcpu_state_ld_rs2: begin
\t\t\t\t`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
\t\t\t\treg_sh <= cpuregs_rs2;
\t\t\t\treg_op2 <= cpuregs_rs2;
\t\t\t\tdbg_rs2val <= cpuregs_rs2;
\t\t\t\tdbg_rs2val_valid <= 1;
\t\t\t\t(* parallel_case *)
\t\t\t\tcase (1\'b1)
\t\t\t\t\tWITH_PCPI && instr_trap: begin
\t\t\t\t\t\tpcpi_valid <= 1;
\t\t\t\t\t\tif (pcpi_int_ready) begin
\t\t\t\t\t\t\tmem_do_rinst <= 1;
\t\t\t\t\t\t\tpcpi_valid <= 0;
\t\t\t\t\t\t\treg_out <= pcpi_int_rd;
\t\t\t\t\t\t\tlatched_store <= pcpi_int_wr;
\t\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\t\tend else
\t\t\t\t\t\tif (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin
\t\t\t\t\t\t\tpcpi_valid <= 0;
\t\t\t\t\t\t\t`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
\t\t\t\t\t\t\tif (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
\t\t\t\t\t\t\t\tnext_irq_pending[irq_ebreak] = 1;
\t\t\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\t\t\tend else
\t\t\t\t\t\t\t\tcpu_state <= cpu_state_trap;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\t\tis_sb_sh_sw: begin
\t\t\t\t\t\tcpu_state <= cpu_state_stmem;
\t\t\t\t\t\tmem_do_rinst <= 1;
\t\t\t\t\tend
\t\t\t\t\tis_sll_srl_sra && !BARREL_SHIFTER: begin
\t\t\t\t\t\tcpu_state <= cpu_state_shift;
\t\t\t\t\tend
\t\t\t\t\tdefault: begin
\t\t\t\t\t\tif (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
\t\t\t\t\t\t\talu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
\t\t\t\t\t\t\talu_wait <= 1;
\t\t\t\t\t\tend else
\t\t\t\t\t\t\tmem_do_rinst <= mem_do_prefetch;
\t\t\t\t\t\tcpu_state <= cpu_state_exec;
\t\t\t\t\tend
\t\t\t\tendcase
\t\t\tend
\t\t\tcpu_state_exec: begin
\t\t\t\treg_out <= reg_pc + decoded_imm;
\t\t\t\tif ((TWO_CYCLE_ALU || TWO_CYCLE_COMPARE) && (alu_wait || alu_wait_2)) begin
\t\t\t\t\tmem_do_rinst <= mem_do_prefetch && !alu_wait_2;
\t\t\t\t\talu_wait <= alu_wait_2;
\t\t\t\tend else
\t\t\t\tif (is_beq_bne_blt_bge_bltu_bgeu) begin
\t\t\t\t\tlatched_rd <= 0;
\t\t\t\t\tlatched_store <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
\t\t\t\t\tlatched_branch <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
\t\t\t\t\tif (mem_done)
\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\tif (TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0) begin
\t\t\t\t\t\tdecoder_trigger <= 0;
\t\t\t\t\t\tset_mem_do_rinst = 1;
\t\t\t\t\tend
\t\t\t\tend else begin
\t\t\t\t\tlatched_branch <= instr_jalr;
\t\t\t\t\tlatched_store <= 1;
\t\t\t\t\tlatched_stalu <= 1;
\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\tend
\t\t\tend
\t\t\tcpu_state_shift: begin
\t\t\t\tlatched_store <= 1;
\t\t\t\tif (reg_sh == 0) begin
\t\t\t\t\treg_out <= reg_op1;
\t\t\t\t\tmem_do_rinst <= mem_do_prefetch;
\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\tend else if (TWO_STAGE_SHIFT && reg_sh >= 4) begin
\t\t\t\t\t(* parallel_case, full_case *)
\t\t\t\t\tcase (1\'b1)
\t\t\t\t\t\tinstr_slli || instr_sll: reg_op1 <= reg_op1 << 4;
\t\t\t\t\t\tinstr_srli || instr_srl: reg_op1 <= reg_op1 >> 4;
\t\t\t\t\t\tinstr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 4;
\t\t\t\t\tendcase
\t\t\t\t\treg_sh <= reg_sh - 4;
\t\t\t\tend else begin
\t\t\t\t\t(* parallel_case, full_case *)
\t\t\t\t\tcase (1\'b1)
\t\t\t\t\t\tinstr_slli || instr_sll: reg_op1 <= reg_op1 << 1;
\t\t\t\t\t\tinstr_srli || instr_srl: reg_op1 <= reg_op1 >> 1;
\t\t\t\t\t\tinstr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 1;
\t\t\t\t\tendcase
\t\t\t\t\treg_sh <= reg_sh - 1;
\t\t\t\tend
\t\t\tend
\t\t\tcpu_state_stmem: begin
\t\t\t\tif (ENABLE_TRACE)
\t\t\t\t\treg_out <= reg_op2;
\t\t\t\tif (!mem_do_prefetch || mem_done) begin
\t\t\t\t\tif (!mem_do_wdata) begin
\t\t\t\t\t\t(* parallel_case, full_case *)
\t\t\t\t\t\tcase (1\'b1)
\t\t\t\t\t\t\tinstr_sb: mem_wordsize <= 2;
\t\t\t\t\t\t\tinstr_sh: mem_wordsize <= 1;
\t\t\t\t\t\t\tinstr_sw: mem_wordsize <= 0;
\t\t\t\t\t\tendcase
\t\t\t\t\t\tif (ENABLE_TRACE) begin
\t\t\t\t\t\t\ttrace_valid <= 1;
\t\t\t\t\t\t\ttrace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32\'hffffffff);
\t\t\t\t\t\tend
\t\t\t\t\t\treg_op1 <= reg_op1 + decoded_imm;
\t\t\t\t\t\tset_mem_do_wdata = 1;
\t\t\t\t\tend
\t\t\t\t\tif (!mem_do_prefetch && mem_done) begin
\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\t\tdecoder_trigger <= 1;
\t\t\t\t\t\tdecoder_pseudo_trigger <= 1;
\t\t\t\t\tend
\t\t\t\tend
\t\t\tend
\t\t\tcpu_state_ldmem: begin
\t\t\t\tlatched_store <= 1;
\t\t\t\tif (!mem_do_prefetch || mem_done) begin
\t\t\t\t\tif (!mem_do_rdata) begin
\t\t\t\t\t\t(* parallel_case, full_case *)
\t\t\t\t\t\tcase (1\'b1)
\t\t\t\t\t\t\tinstr_lb || instr_lbu: mem_wordsize <= 2;
\t\t\t\t\t\t\tinstr_lh || instr_lhu: mem_wordsize <= 1;
\t\t\t\t\t\t\tinstr_lw: mem_wordsize <= 0;
\t\t\t\t\t\tendcase
\t\t\t\t\t\tlatched_is_lu <= is_lbu_lhu_lw;
\t\t\t\t\t\tlatched_is_lh <= instr_lh;
\t\t\t\t\t\tlatched_is_lb <= instr_lb;
\t\t\t\t\t\tif (ENABLE_TRACE) begin
\t\t\t\t\t\t\ttrace_valid <= 1;
\t\t\t\t\t\t\ttrace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32\'hffffffff);
\t\t\t\t\t\tend
\t\t\t\t\t\treg_op1 <= reg_op1 + decoded_imm;
\t\t\t\t\t\tset_mem_do_rdata = 1;
\t\t\t\t\tend
\t\t\t\t\tif (!mem_do_prefetch && mem_done) begin
\t\t\t\t\t\t(* parallel_case, full_case *)
\t\t\t\t\t\tcase (1\'b1)
\t\t\t\t\t\t\tlatched_is_lu: reg_out <= mem_rdata_word;
\t\t\t\t\t\t\tlatched_is_lh: reg_out <= $signed(mem_rdata_word[15:0]);
\t\t\t\t\t\t\tlatched_is_lb: reg_out <= $signed(mem_rdata_word[7:0]);
\t\t\t\t\t\tendcase
\t\t\t\t\t\tdecoder_trigger <= 1;
\t\t\t\t\t\tdecoder_pseudo_trigger <= 1;
\t\t\t\t\t\tcpu_state <= cpu_state_fetch;
\t\t\t\t\tend
\t\t\t\tend
\t\t\tend
\t\tendcase
\t\tif (CATCH_MISALIGN && resetn && (mem_do_rdata || mem_do_wdata)) begin
\t\t\tif (mem_wordsize == 0 && reg_op1[1:0] != 0) begin
\t\t\t\t`debug($display("MISALIGNED WORD: 0x%08x", reg_op1);)
\t\t\t\tif (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
\t\t\t\t\tnext_irq_pending[irq_buserror] = 1;
\t\t\t\tend else
\t\t\t\t\tcpu_state <= cpu_state_trap;
\t\t\tend
\t\t\tif (mem_wordsize == 1 && reg_op1[0] != 0) begin
\t\t\t\t`debug($display("MISALIGNED HALFWORD: 0x%08x", reg_op1);)
\t\t\t\tif (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
\t\t\t\t\tnext_irq_pending[irq_buserror] = 1;
\t\t\t\tend else
\t\t\t\t\tcpu_state <= cpu_state_trap;
\t\t\tend
\t\tend
\t\tif (CATCH_MISALIGN && resetn && mem_do_rinst && (COMPRESSED_ISA ? reg_pc[0] : |reg_pc[1:0])) begin
\t\t\t`debug($display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);)
\t\t\tif (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
\t\t\t\tnext_irq_pending[irq_buserror] = 1;
\t\t\tend else
\t\t\t\tcpu_state <= cpu_state_trap;
\t\tend
\t\tif (!CATCH_ILLINSN && decoder_trigger_q && !decoder_pseudo_trigger_q && instr_ecall_ebreak) begin
\t\t\tcpu_state <= cpu_state_trap;
\t\tend
\t\tif (!resetn || mem_done) begin
\t\t\tmem_do_prefetch <= 0;
\t\t\tmem_do_rinst <= 0;
\t\t\tmem_do_rdata <= 0;
\t\t\tmem_do_wdata <= 0;
\t\tend
\t\tif (set_mem_do_rinst)
\t\t\tmem_do_rinst <= 1;
\t\tif (set_mem_do_rdata)
\t\t\tmem_do_rdata <= 1;
\t\tif (set_mem_do_wdata)
\t\t\tmem_do_wdata <= 1;
\t\tirq_pending <= next_irq_pending & ~MASKED_IRQ;
\t\tif (!CATCH_MISALIGN) begin
\t\t\tif (COMPRESSED_ISA) begin
\t\t\t\treg_pc[0] <= 0;
\t\t\t\treg_next_pc[0] <= 0;
\t\t\tend else begin
\t\t\t\treg_pc[1:0] <= 0;
\t\t\t\treg_next_pc[1:0] <= 0;
\t\t\tend
\t\tend
\t\tcurrent_pc = \'bx;
\tend
`ifdef RISCV_FORMAL
\talways @(posedge clk) begin
\t\trvfi_valid <= resetn && (launch_next_insn || trap) && dbg_valid_insn;
\t\trvfi_order <= 0;
\t\trvfi_insn <= dbg_insn_opcode;
\t\trvfi_rs1_addr <= dbg_rs1val_valid ? dbg_insn_rs1 : 0;
\t\trvfi_rs2_addr <= dbg_rs2val_valid ? dbg_insn_rs2 : 0;
\t\trvfi_pc_rdata <= dbg_insn_addr;
\t\trvfi_rs1_rdata <= dbg_rs1val_valid ? dbg_rs1val : 0;
\t\trvfi_rs2_rdata <= dbg_rs2val_valid ? dbg_rs2val : 0;
\t\trvfi_trap <= trap;
\t\tif (!resetn) begin
\t\t\trvfi_rd_addr <= 0;
\t\t\trvfi_rd_wdata <= 0;
\t\tend else
\t\tif (cpuregs_write) begin
\t\t\trvfi_rd_addr <= latched_rd;
\t\t\trvfi_rd_wdata <= latched_rd ? cpuregs_wrdata : 0;
\t\tend else
\t\tif (rvfi_valid) begin
\t\t\trvfi_rd_addr <= 0;
\t\t\trvfi_rd_wdata <= 0;
\t\tend
\t\tif (dbg_mem_instr) begin
\t\t\trvfi_mem_addr <= 0;
\t\t\trvfi_mem_rmask <= 0;
\t\t\trvfi_mem_wmask <= 0;
\t\t\trvfi_mem_rdata <= 0;
\t\t\trvfi_mem_wdata <= 0;
\t\tend else
\t\tif (dbg_mem_valid && dbg_mem_ready) begin
\t\t\trvfi_mem_addr <= dbg_mem_addr;
\t\t\trvfi_mem_rmask <= dbg_mem_wstrb ? 0 : ~0;
\t\t\trvfi_mem_wmask <= dbg_mem_wstrb;
\t\t\trvfi_mem_rdata <= dbg_mem_rdata;
\t\t\trvfi_mem_wdata <= dbg_mem_wdata;
\t\tend
\tend
\talways @* begin
\t\trvfi_pc_wdata = dbg_insn_addr;
\tend
`endif
\t// Formal Verification
`ifdef FORMAL
\treg [3:0] last_mem_nowait;
\talways @(posedge clk)
\t\tlast_mem_nowait <= {last_mem_nowait, mem_ready || !mem_valid};
\t// stall the memory interface for max 4 cycles
\trestrict property (|last_mem_nowait || mem_ready || !mem_valid);
\t// resetn low in first cycle, after that resetn high
\trestrict property (resetn != $initstate);
\t// this just makes it much easier to read traces. uncomment as needed.
\t// assume property (mem_valid || !mem_ready);
\treg ok;
\talways @* begin
\t\tif (resetn) begin
\t\t\t// instruction fetches are read-only
\t\t\tif (mem_valid && mem_instr)
\t\t\t\tassert (mem_wstrb == 0);
\t\t\t// cpu_state must be valid
\t\t\tok = 0;
\t\t\tif (cpu_state == cpu_state_trap) ok = 1;
\t\t\tif (cpu_state == cpu_state_fetch) ok = 1;
\t\t\tif (cpu_state == cpu_state_ld_rs1) ok = 1;
\t\t\tif (cpu_state == cpu_state_ld_rs2) ok = !ENABLE_REGS_DUALPORT;
\t\t\tif (cpu_state == cpu_state_exec) ok = 1;
\t\t\tif (cpu_state == cpu_state_shift) ok = 1;
\t\t\tif (cpu_state == cpu_state_stmem) ok = 1;
\t\t\tif (cpu_state == cpu_state_ldmem) ok = 1;
\t\t\tassert (ok);
\t\tend
\tend
\treg last_mem_la_read = 0;
\treg last_mem_la_write = 0;
\treg [31:0] last_mem_la_addr;
\treg [31:0] last_mem_la_wdata;
\treg [3:0] last_mem_la_wstrb = 0;
\talways @(posedge clk) begin
\t\tlast_mem_la_read <= mem_la_read;
\t\tlast_mem_la_write <= mem_la_write;
\t\tlast_mem_la_addr <= mem_la_addr;
\t\tlast_mem_la_wdata <= mem_la_wdata;
\t\tlast_mem_la_wstrb <= mem_la_wstrb;
\t\tif (last_mem_la_read) begin
\t\t\tassert(mem_valid);
\t\t\tassert(mem_addr == last_mem_la_addr);
\t\t\tassert(mem_wstrb == 0);
\t\tend
\t\tif (last_mem_la_write) begin
\t\t\tassert(mem_valid);
\t\t\tassert(mem_addr == last_mem_la_addr);
\t\t\tassert(mem_wdata == last_mem_la_wdata);
\t\t\tassert(mem_wstrb == last_mem_la_wstrb);
\t\tend
\t\tif (mem_la_read || mem_la_write) begin
\t\t\tassert(!mem_valid || mem_ready);
\t\tend
\tend
`endif
endmodule
/***************************************************************
* picorv32_pcpi_mul
***************************************************************/
module picorv32_pcpi_mul #(
\tparameter STEPS_AT_ONCE = 1,
\tparameter CARRY_CHAIN = 4
) (
\tinput clk, resetn,
\tinput pcpi_valid,
\tinput [31:0] pcpi_insn,
\tinput [31:0] pcpi_rs1,
\tinput [31:0] pcpi_rs2,
\toutput reg pcpi_wr,
\toutput reg [31:0] pcpi_rd,
\toutput reg pcpi_wait,
\toutput reg pcpi_ready
);
\treg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu;
\twire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu};
\twire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu};
\twire instr_rs1_signed = |{instr_mulh, instr_mulhsu};
\twire instr_rs2_signed = |{instr_mulh};
\treg pcpi_wait_q;
\twire mul_start = pcpi_wait && !pcpi_wait_q;
\talways @(posedge clk) begin
\t\tinstr_mul <= 0;
\t\tinstr_mulh <= 0;
\t\tinstr_mulhsu <= 0;
\t\tinstr_mulhu <= 0;
\t\tif (resetn && pcpi_valid && pcpi_insn[6:0] == 7\'b0110011 && pcpi_insn[31:25] == 7\'b0000001) begin
\t\t\tcase (pcpi_insn[14:12])
\t\t\t\t3\'b000: instr_mul <= 1;
\t\t\t\t3\'b001: instr_mulh <= 1;
\t\t\t\t3\'b010: instr_mulhsu <= 1;
\t\t\t\t3\'b011: instr_mulhu <= 1;
\t\t\tendcase
\t\tend
\t\tpcpi_wait <= instr_any_mul;
\t\tpcpi_wait_q <= pcpi_wait;
\tend
\treg [63:0] rs1, rs2, rd, rdx;
\treg [63:0] next_rs1, next_rs2, this_rs2;
\treg [63:0] next_rd, next_rdx, next_rdt;
\treg [6:0] mul_counter;
\treg mul_waiting;
\treg mul_finish;
\tinteger i, j;
\t// carry save accumulator
\talways @* begin
\t\tnext_rd = rd;
\t\tnext_rdx = rdx;
\t\tnext_rs1 = rs1;
\t\tnext_rs2 = rs2;
\t\tfor (i = 0; i < STEPS_AT_ONCE; i=i+1) begin
\t\t\tthis_rs2 = next_rs1[0] ? next_rs2 : 0;
\t\t\tif (CARRY_CHAIN == 0) begin
\t\t\t\tnext_rdt = next_rd ^ next_rdx ^ this_rs2;
\t\t\t\tnext_rdx = ((next_rd & next_rdx) | (next_rd & this_rs2) | (next_rdx & this_rs2)) << 1;
\t\t\t\tnext_rd = next_rdt;
\t\t\tend else begin
\t\t\t\tnext_rdt = 0;
\t\t\t\tfor (j = 0; j < 64; j = j + CARRY_CHAIN)
\t\t\t\t\t{next_rdt[j+CARRY_CHAIN-1], next_rd[j +: CARRY_CHAIN]} =
\t\t\t\t\t\t\tnext_rd[j +: CARRY_CHAIN] + next_rdx[j +: CARRY_CHAIN] + this_rs2[j +: CARRY_CHAIN];
\t\t\t\tnext_rdx = next_rdt << 1;
\t\t\tend
\t\t\tnext_rs1 = next_rs1 >> 1;
\t\t\tnext_rs2 = next_rs2 << 1;
\t\tend
\tend
\talways @(posedge clk) begin
\t\tmul_finish <= 0;
\t\tif (!resetn) begin
\t\t\tmul_waiting <= 1;
\t\tend else
\t\tif (mul_waiting) begin
\t\t\tif (instr_rs1_signed)
\t\t\t\trs1 <= $signed(pcpi_rs1);
\t\t\telse
\t\t\t\trs1 <= $unsigned(pcpi_rs1);
\t\t\tif (instr_rs2_signed)
\t\t\t\trs2 <= $signed(pcpi_rs2);
\t\t\telse
\t\t\t\trs2 <= $unsigned(pcpi_rs2);
\t\t\trd <= 0;
\t\t\trdx <= 0;
\t\t\tmul_counter <= (instr_any_mulh ? 63 - STEPS_AT_ONCE : 31 - STEPS_AT_ONCE);
\t\t\tmul_waiting <= !mul_start;
\t\tend else begin
\t\t\trd <= next_rd;
\t\t\trdx <= next_rdx;
\t\t\trs1 <= next_rs1;
\t\t\trs2 <= next_rs2;
\t\t\tmul_counter <= mul_counter - STEPS_AT_ONCE;
\t\t\tif (mul_counter[6]) begin
\t\t\t\tmul_finish <= 1;
\t\t\t\tmul_waiting <= 1;
\t\t\tend
\t\tend
\tend
\talways @(posedge clk) begin
\t\tpcpi_wr <= 0;
\t\tpcpi_ready <= 0;
\t\tif (mul_finish && resetn) begin
\t\t\tpcpi_wr <= 1;
\t\t\tpcpi_ready <= 1;
\t\t\tpcpi_rd <= instr_any_mulh ? rd >> 32 : rd;
\t\tend
\tend
endmodule
module picorv32_pcpi_fast_mul #(
\tparameter EXTRA_MUL_FFS = 0,
\tparameter EXTRA_INSN_FFS = 0,
\tparameter MUL_CLKGATE = 0
) (
\tinput clk, resetn,
\tinput pcpi_valid,
\tinput [31:0] pcpi_insn,
\tinput [31:0] pcpi_rs1,
\tinput [31:0] pcpi_rs2,
\toutput pcpi_wr,
\toutput [31:0] pcpi_rd,
\toutput pcpi_wait,
\toutput pcpi_ready
);
\treg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu;
\twire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu};
\twire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu};
\twire instr_rs1_signed = |{instr_mulh, instr_mulhsu};
\twire instr_rs2_signed = |{instr_mulh};
\treg shift_out;
\treg [3:0] active;
\treg [32:0] rs1, rs2, rs1_q, rs2_q;
\treg [63:0] rd, rd_q;
\twire pcpi_insn_valid = pcpi_valid && pcpi_insn[6:0] == 7\'b0110011 && pcpi_insn[31:25] == 7\'b0000001;
\treg pcpi_insn_valid_q;
\talways @* begin
\t\tinstr_mul = 0;
\t\tinstr_mulh = 0;
\t\tinstr_mulhsu = 0;
\t\tinstr_mulhu = 0;
\t\tif (resetn && (EXTRA_INSN_FFS ? pcpi_insn_valid_q : pcpi_insn_valid)) begin
\t\t\tcase (pcpi_insn[14:12])
\t\t\t\t3\'b000: instr_mul = 1;
\t\t\t\t3\'b001: instr_mulh = 1;
\t\t\t\t3\'b010: instr_mulhsu = 1;
\t\t\t\t3\'b011: instr_mulhu = 1;
\t\t\tendcase
\t\tend
\tend
\talways @(posedge clk) begin
\t\tpcpi_insn_valid_q <= pcpi_insn_valid;
\t\tif (!MUL_CLKGATE || active[0]) begin
\t\t\trs1_q <= rs1;
\t\t\trs2_q <= rs2;
\t\tend
\t\tif (!MUL_CLKGATE || active[1]) begin
\t\t\trd <= $signed(EXTRA_MUL_FFS ? rs1_q : rs1) * $signed(EXTRA_MUL_FFS ? rs2_q : rs2);
\t\tend
\t\tif (!MUL_CLKGATE || active[2]) begin
\t\t\trd_q <= rd;
\t\tend
\tend
\talways @(posedge clk) begin
\t\tif (instr_any_mul && !(EXTRA_MUL_FFS ? active[3:0] : active[1:0])) begin
\t\t\tif (instr_rs1_signed)
\t\t\t\trs1 <= $signed(pcpi_rs1);
\t\t\telse
\t\t\t\trs1 <= $unsigned(pcpi_rs1);
\t\t\tif (instr_rs2_signed)
\t\t\t\trs2 <= $signed(pcpi_rs2);
\t\t\telse
\t\t\t\trs2 <= $unsigned(pcpi_rs2);
\t\t\tactive[0] <= 1;
\t\tend else begin
\t\t\tactive[0] <= 0;
\t\tend
\t\tactive[3:1] <= active;
\t\tshift_out <= instr_any_mulh;
\t\tif (!resetn)
\t\t\tactive <= 0;
\tend
\tassign pcpi_wr = active[EXTRA_MUL_FFS ? 3 : 1];
\tassign pcpi_wait = 0;
\tassign pcpi_ready = active[EXTRA_MUL_FFS ? 3 : 1];
\tassign pcpi_rd = shift_out ? (EXTRA_MUL_FFS ? rd_q : rd) >> 32 : (EXTRA_MUL_FFS ? rd_q : rd);
endmodule
/***************************************************************
* picorv32_pcpi_div
***************************************************************/
module picorv32_pcpi_div (
\tinput clk, resetn,
\tinput pcpi_valid,
\tinput [31:0] pcpi_insn,
\tinput [31:0] pcpi_rs1,
\tinput [31:0] pcpi_rs2,
\toutput reg pcpi_wr,
\toutput reg [31:0] pcpi_rd,
\toutput reg pcpi_wait,
\toutput reg pcpi_ready
);
\treg instr_div, instr_divu, instr_rem, instr_remu;
\twire instr_any_div_rem = |{instr_div, instr_divu, instr_rem, instr_remu};
\treg pcpi_wait_q;
\twire start = pcpi_wait && !pcpi_wait_q;
\talways @(posedge clk) begin
\t\tinstr_div <= 0;
\t\tinstr_divu <= 0;
\t\tinstr_rem <= 0;
\t\tinstr_remu <= 0;
\t\tif (resetn && pcpi_valid && !pcpi_ready && pcpi_insn[6:0] == 7\'b0110011 && pcpi_insn[31:25] == 7\'b0000001) begin
\t\t\tcase (pcpi_insn[14:12])
\t\t\t\t3\'b100: instr_div <= 1;
\t\t\t\t3\'b101: instr_divu <= 1;
\t\t\t\t3\'b110: instr_rem <= 1;
\t\t\t\t3\'b111: instr_remu <= 1;
\t\t\tendcase
\t\tend
\t\tpcpi_wait <= instr_any_div_rem;
\t\tpcpi_wait_q <= pcpi_wait;
\tend
\treg [31:0] dividend;
\treg [62:0] divisor;
\treg [31:0] quotient;
\treg [31:0] quotient_msk;
\treg running;
\treg outsign;
\talways @(posedge clk) begin
\t\tpcpi_ready <= 0;
\t\tpcpi_wr <= 0;
\t\tpcpi_rd <= \'bx;
\t\tif (!resetn) begin
\t\t\trunning <= 0;
\t\tend else
\t\tif (start) begin
\t\t\trunning <= 1;
\t\t\tdividend <= (instr_div || instr_rem) && pcpi_rs1[31] ? -pcpi_rs1 : pcpi_rs1;
\t\t\tdivisor <= ((instr_div || instr_rem) && pcpi_rs2[31] ? -pcpi_rs2 : pcpi_rs2) << 31;
\t\t\toutsign <= (instr_div && (pcpi_rs1[31] != pcpi_rs2[31]) && |pcpi_rs2) || (instr_rem && pcpi_rs1[31]);
\t\t\tquotient <= 0;
\t\t\tquotient_msk <= 1 << 31;
\t\tend else
\t\tif (!quotient_msk && running) begin
\t\t\trunning <= 0;
\t\t\tpcpi_ready <= 1;
\t\t\tpcpi_wr <= 1;
\t\t\tif (instr_div || instr_divu)
\t\t\t\tpcpi_rd <= outsign ? -quotient : quotient;
\t\t\telse
\t\t\t\tpcpi_rd <= outsign ? -dividend : dividend;
\t\tend else begin
\t\t\tif (divisor <= dividend) begin
\t\t\t\tdividend <= dividend - divisor;
\t\t\t\tquotient <= quotient | quotient_msk;
\t\t\tend
\t\t\tdivisor <= divisor >> 1;
\t\t\tquotient_msk <= quotient_msk >> 1;
\t\tend
\tend
endmodule
/***************************************************************
* picorv32_axi
***************************************************************/
module picorv32_axi #(
\tparameter [ 0:0] ENABLE_COUNTERS = 1,
\tparameter [ 0:0] ENABLE_COUNTERS64 = 1,
\tparameter [ 0:0] ENABLE_REGS_16_31 = 1,
\tparameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
\tparameter [ 0:0] TWO_STAGE_SHIFT = 1,
\tparameter [ 0:0] BARREL_SHIFTER = 0,
\tparameter [ 0:0] TWO_CYCLE_COMPARE = 0,
\tparameter [ 0:0] TWO_CYCLE_ALU = 0,
\tparameter [ 0:0] COMPRESSED_ISA = 0,
\tparameter [ 0:0] CATCH_MISALIGN = 1,
\tparameter [ 0:0] CATCH_ILLINSN = 1,
\tparameter [ 0:0] ENABLE_PCPI = 0,
\tparameter [ 0:0] ENABLE_MUL = 0,
\tparameter [ 0:0] ENABLE_FAST_MUL = 0,
\tparameter [ 0:0] ENABLE_DIV = 0,
\tparameter [ 0:0] ENABLE_IRQ = 0,
\tparameter [ 0:0] ENABLE_IRQ_QREGS = 1,
\tparameter [ 0:0] ENABLE_IRQ_TIMER = 1,
\tparameter [ 0:0] ENABLE_TRACE = 0,
\tparameter [ 0:0] REGS_INIT_ZERO = 0,
\tparameter [31:0] MASKED_IRQ = 32\'h 0000_0000,
\tparameter [31:0] LATCHED_IRQ = 32\'h ffff_ffff,
\tparameter [31:0] PROGADDR_RESET = 32\'h 0000_0000,
\tparameter [31:0] PROGADDR_IRQ = 32\'h 0000_0010,
\tparameter [31:0] STACKADDR = 32\'h ffff_ffff
) (
\tinput clk, resetn,
\toutput trap,
\t// AXI4-lite master memory interface
\toutput mem_axi_awvalid,
\tinput mem_axi_awready,
\toutput [31:0] mem_axi_awaddr,
\toutput [ 2:0] mem_axi_awprot,
\toutput mem_axi_wvalid,
\tinput mem_axi_wready,
\toutput [31:0] mem_axi_wdata,
\toutput [ 3:0] mem_axi_wstrb,
\tinput mem_axi_bvalid,
\toutput mem_axi_bready,
\toutput mem_axi_arvalid,
\tinput mem_axi_arready,
\toutput [31:0] mem_axi_araddr,
\toutput [ 2:0] mem_axi_arprot,
\tinput mem_axi_rvalid,
\toutput mem_axi_rready,
\tinput [31:0] mem_axi_rdata,
\t// Pico Co-Processor Interface (PCPI)
\toutput pcpi_valid,
\toutput [31:0] pcpi_insn,
\toutput [31:0] pcpi_rs1,
\toutput [31:0] pcpi_rs2,
\tinput pcpi_wr,
\tinput [31:0] pcpi_rd,
\tinput pcpi_wait,
\tinput pcpi_ready,
\t// IRQ interface
\tinput [31:0] irq,
\toutput [31:0] eoi,
`ifdef RISCV_FORMAL
\toutput rvfi_valid,
\toutput [ 7:0] rvfi_order,
\toutput [31:0] rvfi_insn,
\toutput rvfi_trap,
\toutput [ 4:0] rvfi_rs1_addr,
\toutput [ 4:0] rvfi_rs2_addr,
\toutput [31:0] rvfi_rs1_rdata,
\toutput [31:0] rvfi_rs2_rdata,
\toutput [ 4:0] rvfi_rd_addr,
\toutput [31:0] rvfi_rd_wdata,
\toutput [31:0] rvfi_pc_rdata,
\toutput [31:0] rvfi_pc_wdata,
\toutput [31:0] rvfi_mem_addr,
\toutput [ 3:0] rvfi_mem_rmask,
\toutput [ 3:0] rvfi_mem_wmask,
\toutput [31:0] rvfi_mem_rdata,
\toutput [31:0] rvfi_mem_wdata,
`endif
\t// Trace Interface
\toutput trace_valid,
\toutput [35:0] trace_data
);
\twire mem_valid;
\twire [31:0] mem_addr;
\twire [31:0] mem_wdata;
\twire [ 3:0] mem_wstrb;
\twire mem_instr;
\twire mem_ready;
\twire [31:0] mem_rdata;
\tpicorv32_axi_adapter axi_adapter (
\t\t.clk (clk ),
\t\t.resetn (resetn ),
\t\t.mem_axi_awvalid(mem_axi_awvalid),
\t\t.mem_axi_awready(mem_axi_awready),
\t\t.mem_axi_awaddr (mem_axi_awaddr ),
\t\t.mem_axi_awprot (mem_axi_awprot ),
\t\t.mem_axi_wvalid (mem_axi_wvalid ),
\t\t.mem_axi_wready (mem_axi_wready ),
\t\t.mem_axi_wdata (mem_axi_wdata ),
\t\t.mem_axi_wstrb (mem_axi_wstrb ),
\t\t.mem_axi_bvalid (mem_axi_bvalid ),
\t\t.mem_axi_bready (mem_axi_bready ),
\t\t.mem_axi_arvalid(mem_axi_arvalid),
\t\t.mem_axi_arready(mem_axi_arready),
\t\t.mem_axi_araddr (mem_axi_araddr ),
\t\t.mem_axi_arprot (mem_axi_arprot ),
\t\t.mem_axi_rvalid (mem_axi_rvalid ),
\t\t.mem_axi_rready (mem_axi_rready ),
\t\t.mem_axi_rdata (mem_axi_rdata ),
\t\t.mem_valid (mem_valid ),
\t\t.mem_instr (mem_instr ),
\t\t.mem_ready (mem_ready ),
\t\t.mem_addr (mem_addr ),
\t\t.mem_wdata (mem_wdata ),
\t\t.mem_wstrb (mem_wstrb ),
\t\t.mem_rdata (mem_rdata )
\t);
\tpicorv32 #(
\t\t.ENABLE_COUNTERS (ENABLE_COUNTERS ),
\t\t.ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ),
\t\t.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
\t\t.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
\t\t.TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
\t\t.BARREL_SHIFTER (BARREL_SHIFTER ),
\t\t.TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ),
\t\t.TWO_CYCLE_ALU (TWO_CYCLE_ALU ),
\t\t.COMPRESSED_ISA (COMPRESSED_ISA ),
\t\t.CATCH_MISALIGN (CATCH_MISALIGN ),
\t\t.CATCH_ILLINSN (CATCH_ILLINSN ),
\t\t.ENABLE_PCPI (ENABLE_PCPI ),
\t\t.ENABLE_MUL (ENABLE_MUL ),
\t\t.ENABLE_FAST_MUL (ENABLE_FAST_MUL ),
\t\t.ENABLE_DIV (ENABLE_DIV ),
\t\t.ENABLE_IRQ (ENABLE_IRQ ),
\t\t.ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
\t\t.ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
\t\t.ENABLE_TRACE (ENABLE_TRACE ),
\t\t.REGS_INIT_ZERO (REGS_INIT_ZERO ),
\t\t.MASKED_IRQ (MASKED_IRQ ),
\t\t.LATCHED_IRQ (LATCHED_IRQ ),
\t\t.PROGADDR_RESET (PROGADDR_RESET ),
\t\t.PROGADDR_IRQ (PROGADDR_IRQ ),
\t\t.STACKADDR (STACKADDR )
\t) picorv32_core (
\t\t.clk (clk ),
\t\t.resetn (resetn),
\t\t.trap (trap ),
\t\t.mem_valid(mem_valid),
\t\t.mem_addr (mem_addr ),
\t\t.mem_wdata(mem_wdata),
\t\t.mem_wstrb(mem_wstrb),
\t\t.mem_instr(mem_instr),
\t\t.mem_ready(mem_ready),
\t\t.mem_rdata(mem_rdata),
\t\t.pcpi_valid(pcpi_valid),
\t\t.pcpi_insn (pcpi_insn ),
\t\t.pcpi_rs1 (pcpi_rs1 ),
\t\t.pcpi_rs2 (pcpi_rs2 ),
\t\t.pcpi_wr (pcpi_wr ),
\t\t.pcpi_rd (pcpi_rd ),
\t\t.pcpi_wait (pcpi_wait ),
\t\t.pcpi_ready(pcpi_ready),
\t\t.irq(irq),
\t\t.eoi(eoi),
`ifdef RISCV_FORMAL
\t\t.rvfi_valid (rvfi_valid ),
\t\t.rvfi_order (rvfi_order ),
\t\t.rvfi_insn (rvfi_insn ),
\t\t.rvfi_trap (rvfi_trap ),
\t\t.rvfi_rs1_addr (rvfi_rs1_addr ),
\t\t.rvfi_rs2_addr (rvfi_rs2_addr ),
\t\t.rvfi_rs1_rdata(rvfi_rs1_rdata),
\t\t.rvfi_rs2_rdata(rvfi_rs2_rdata),
\t\t.rvfi_rd_addr (rvfi_rd_addr ),
\t\t.rvfi_rd_wdata (rvfi_rd_wdata ),
\t\t.rvfi_pc_rdata (rvfi_pc_rdata ),
\t\t.rvfi_pc_wdata (rvfi_pc_wdata ),
\t\t.rvfi_mem_addr (rvfi_mem_addr ),
\t\t.rvfi_mem_rmask(rvfi_mem_rmask),
\t\t.rvfi_mem_wmask(rvfi_mem_wmask),
\t\t.rvfi_mem_rdata(rvfi_mem_rdata),
\t\t.rvfi_mem_wdata(rvfi_mem_wdata),
`endif
\t\t.trace_valid(trace_valid),
\t\t.trace_data (trace_data)
\t);
endmodule
/***************************************************************
* picorv32_axi_adapter
***************************************************************/
module picorv32_axi_adapter (
\tinput clk, resetn,
\t// AXI4-lite master memory interface
\toutput mem_axi_awvalid,
\tinput mem_axi_awready,
\toutput [31:0] mem_axi_awaddr,
\toutput [ 2:0] mem_axi_awprot,
\toutput mem_axi_wvalid,
\tinput mem_axi_wready,
\toutput [31:0] mem_axi_wdata,
\toutput [ 3:0] mem_axi_wstrb,
\tinput mem_axi_bvalid,
\toutput mem_axi_bready,
\toutput mem_axi_arvalid,
\tinput mem_axi_arready,
\toutput [31:0] mem_axi_araddr,
\toutput [ 2:0] mem_axi_arprot,
\tinput mem_axi_rvalid,
\toutput mem_axi_rready,
\tinput [31:0] mem_axi_rdata,
\t// Native PicoRV32 memory interface
\tinput mem_valid,
\tinput mem_instr,
\toutput mem_ready,
\tinput [31:0] mem_addr,
\tinput [31:0] mem_wdata,
\tinput [ 3:0] mem_wstrb,
\toutput [31:0] mem_rdata
);
\treg ack_awvalid;
\treg ack_arvalid;
\treg ack_wvalid;
\treg xfer_done;
\tassign mem_axi_awvalid = mem_valid && |mem_wstrb && !ack_awvalid;
\tassign mem_axi_awaddr = mem_addr;
\tassign mem_axi_awprot = 0;
\tassign mem_axi_arvalid = mem_valid && !mem_wstrb && !ack_arvalid;
\tassign mem_axi_araddr = mem_addr;
\tassign mem_axi_arprot = mem_instr ? 3\'b100 : 3\'b000;
\tassign mem_axi_wvalid = mem_valid && |mem_wstrb && !ack_wvalid;
\tassign mem_axi_wdata = mem_wdata;
\tassign mem_axi_wstrb = mem_wstrb;
\tassign mem_ready = mem_axi_bvalid || mem_axi_rvalid;
\tassign mem_axi_bready = mem_valid && |mem_wstrb;
\tassign mem_axi_rready = mem_valid && !mem_wstrb;
\tassign mem_rdata = mem_axi_rdata;
\talways @(posedge clk) begin
\t\tif (!resetn) begin
\t\t\tack_awvalid <= 0;
\t\tend else begin
\t\t\txfer_done <= mem_valid && mem_ready;
\t\t\tif (mem_axi_awready && mem_axi_awvalid)
\t\t\t\tack_awvalid <= 1;
\t\t\tif (mem_axi_arready && mem_axi_arvalid)
\t\t\t\tack_arvalid <= 1;
\t\t\tif (mem_axi_wready && mem_axi_wvalid)
\t\t\t\tack_wvalid <= 1;
\t\t\tif (xfer_done || !mem_valid) begin
\t\t\t\tack_awvalid <= 0;
\t\t\t\tack_arvalid <= 0;
\t\t\t\tack_wvalid <= 0;
\t\t\tend
\t\tend
\tend
endmodule
/***************************************************************
* picorv32_wb
***************************************************************/
module picorv32_wb #(
\tparameter [ 0:0] ENABLE_COUNTERS = 1,
\tparameter [ 0:0] ENABLE_COUNTERS64 = 1,
\tparameter [ 0:0] ENABLE_REGS_16_31 = 1,
\tparameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
\tparameter [ 0:0] TWO_STAGE_SHIFT = 1,
\tparameter [ 0:0] BARREL_SHIFTER = 0,
\tparameter [ 0:0] TWO_CYCLE_COMPARE = 0,
\tparameter [ 0:0] TWO_CYCLE_ALU = 0,
\tparameter [ 0:0] COMPRESSED_ISA = 0,
\tparameter [ 0:0] CATCH_MISALIGN = 1,
\tparameter [ 0:0] CATCH_ILLINSN = 1,
\tparameter [ 0:0] ENABLE_PCPI = 0,
\tparameter [ 0:0] ENABLE_MUL = 0,
\tparameter [ 0:0] ENABLE_FAST_MUL = 0,
\tparameter [ 0:0] ENABLE_DIV = 0,
\tparameter [ 0:0] ENABLE_IRQ = 0,
\tparameter [ 0:0] ENABLE_IRQ_QREGS = 1,
\tparameter [ 0:0] ENABLE_IRQ_TIMER = 1,
\tparameter [ 0:0] ENABLE_TRACE = 0,
\tparameter [ 0:0] REGS_INIT_ZERO = 0,
\tparameter [31:0] MASKED_IRQ = 32\'h 0000_0000,
\tparameter [31:0] LATCHED_IRQ = 32\'h ffff_ffff,
\tparameter [31:0] PROGADDR_RESET = 32\'h 0000_0000,
\tparameter [31:0] PROGADDR_IRQ = 32\'h 0000_0010,
\tparameter [31:0] STACKADDR = 32\'h ffff_ffff
) (
\toutput trap,
\t// Wishbone interfaces
\tinput wb_rst_i,
\tinput wb_clk_i,
\toutput reg [31:0] wbm_adr_o,
\toutput reg [31:0] wbm_dat_o,
\tinput [31:0] wbm_dat_i,
\toutput reg wbm_we_o,
\toutput reg [3:0] wbm_sel_o,
\toutput reg wbm_stb_o,
\tinput wbm_ack_i,
\toutput reg wbm_cyc_o,
\t// Pico Co-Processor Interface (PCPI)
\toutput pcpi_valid,
\toutput [31:0] pcpi_insn,
\toutput [31:0] pcpi_rs1,
\toutput [31:0] pcpi_rs2,
\tinput pcpi_wr,
\tinput [31:0] pcpi_rd,
\tinput pcpi_wait,
\tinput pcpi_ready,
\t// IRQ interface
\tinput [31:0] irq,
\toutput [31:0] eoi,
`ifdef RISCV_FORMAL
\toutput rvfi_valid,
\toutput [ 7:0] rvfi_order,
\toutput [31:0] rvfi_insn,
\toutput rvfi_trap,
\toutput [ 4:0] rvfi_rs1_addr,
\toutput [ 4:0] rvfi_rs2_addr,
\toutput [31:0] rvfi_rs1_rdata,
\toutput [31:0] rvfi_rs2_rdata,
\toutput [ 4:0] rvfi_rd_addr,
\toutput [31:0] rvfi_rd_wdata,
\toutput [31:0] rvfi_pc_rdata,
\toutput [31:0] rvfi_pc_wdata,
\toutput [31:0] rvfi_mem_addr,
\toutput [ 3:0] rvfi_mem_rmask,
\toutput [ 3:0] rvfi_mem_wmask,
\toutput [31:0] rvfi_mem_rdata,
\toutput [31:0] rvfi_mem_wdata,
`endif
\t// Trace Interface
\toutput trace_valid,
\toutput [35:0] trace_data,
\toutput mem_instr
);
\twire mem_valid;
\twire [31:0] mem_addr;
\twire [31:0] mem_wdata;
\twire [ 3:0] mem_wstrb;
\treg mem_ready;
\treg [31:0] mem_rdata;
\twire clk;
\twire resetn;
\tassign clk = wb_clk_i;
\tassign resetn = ~wb_rst_i;
\tpicorv32 #(
\t\t.ENABLE_COUNTERS (ENABLE_COUNTERS ),
\t\t.ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ),
\t\t.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
\t\t.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
\t\t.TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
\t\t.BARREL_SHIFTER (BARREL_SHIFTER ),
\t\t.TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ),
\t\t.TWO_CYCLE_ALU (TWO_CYCLE_ALU ),
\t\t.COMPRESSED_ISA (COMPRESSED_ISA ),
\t\t.CATCH_MISALIGN (CATCH_MISALIGN ),
\t\t.CATCH_ILLINSN (CATCH_ILLINSN ),
\t\t.ENABLE_PCPI (ENABLE_PCPI ),
\t\t.ENABLE_MUL (ENABLE_MUL ),
\t\t.ENABLE_FAST_MUL (ENABLE_FAST_MUL ),
\t\t.ENABLE_DIV (ENABLE_DIV ),
\t\t.ENABLE_IRQ (ENABLE_IRQ ),
\t\t.ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
\t\t.ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
\t\t.ENABLE_TRACE (ENABLE_TRACE ),
\t\t.REGS_INIT_ZERO (REGS_INIT_ZERO ),
\t\t.MASKED_IRQ (MASKED_IRQ ),
\t\t.LATCHED_IRQ (LATCHED_IRQ ),
\t\t.PROGADDR_RESET (PROGADDR_RESET ),
\t\t.PROGADDR_IRQ (PROGADDR_IRQ ),
\t\t.STACKADDR (STACKADDR )
\t) picorv32_core (
\t\t.clk (clk ),
\t\t.resetn (resetn),
\t\t.trap (trap ),
\t\t.mem_valid(mem_valid),
\t\t.mem_addr (mem_addr ),
\t\t.mem_wdata(mem_wdata),
\t\t.mem_wstrb(mem_wstrb),
\t\t.mem_instr(mem_instr),
\t\t.mem_ready(mem_ready),
\t\t.mem_rdata(mem_rdata),
\t\t.pcpi_valid(pcpi_valid),
\t\t.pcpi_insn (pcpi_insn ),
\t\t.pcpi_rs1 (pcpi_rs1 ),
\t\t.pcpi_rs2 (pcpi_rs2 ),
\t\t.pcpi_wr (pcpi_wr ),
\t\t.pcpi_rd (pcpi_rd ),
\t\t.pcpi_wait (pcpi_wait ),
\t\t.pcpi_ready(pcpi_ready),
\t\t.irq(irq),
\t\t.eoi(eoi),
`ifdef RISCV_FORMAL
\t\t.rvfi_valid (rvfi_valid ),
\t\t.rvfi_order (rvfi_order ),
\t\t.rvfi_insn (rvfi_insn ),
\t\t.rvfi_trap (rvfi_trap ),
\t\t.rvfi_rs1_addr (rvfi_rs1_addr ),
\t\t.rvfi_rs2_addr (rvfi_rs2_addr ),
\t\t.rvfi_rs1_rdata(rvfi_rs1_rdata),
\t\t.rvfi_rs2_rdata(rvfi_rs2_rdata),
\t\t.rvfi_rd_addr (rvfi_rd_addr ),
\t\t.rvfi_rd_wdata (rvfi_rd_wdata ),
\t\t.rvfi_pc_rdata (rvfi_pc_rdata ),
\t\t.rvfi_pc_wdata (rvfi_pc_wdata ),
\t\t.rvfi_mem_addr (rvfi_mem_addr ),
\t\t.rvfi_mem_rmask(rvfi_mem_rmask),
\t\t.rvfi_mem_wmask(rvfi_mem_wmask),
\t\t.rvfi_mem_rdata(rvfi_mem_rdata),
\t\t.rvfi_mem_wdata(rvfi_mem_wdata),
`endif
\t\t.trace_valid(trace_valid),
\t\t.trace_data (trace_data)
\t);
\tlocalparam IDLE = 2\'b00;
\tlocalparam WBSTART = 2\'b01;
\tlocalparam WBEND = 2\'b10;
\treg [1:0] state;
\twire we;
\tassign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]);
\talways @(posedge wb_clk_i) begin
\t\tif (wb_rst_i) begin
\t\t\twbm_adr_o <= 0;
\t\t\twbm_dat_o <= 0;
\t\t\twbm_we_o <= 0;
\t\t\twbm_sel_o <= 0;
\t\t\twbm_stb_o <= 0;
\t\t\twbm_cyc_o <= 0;
\t\t\tstate <= IDLE;
\t\tend else begin
\t\t\tcase (state)
\t\t\t\tIDLE: begin
\t\t\t\t\tif (mem_valid) begin
\t\t\t\t\t\twbm_adr_o <= mem_addr;
\t\t\t\t\t\twbm_dat_o <= mem_wdata;
\t\t\t\t\t\twbm_we_o <= we;
\t\t\t\t\t\twbm_sel_o <= mem_wstrb;
\t\t\t\t\t\twbm_stb_o <= 1\'b1;
\t\t\t\t\t\twbm_cyc_o <= 1\'b1;
\t\t\t\t\t\tstate <= WBSTART;
\t\t\t\t\tend else begin
\t\t\t\t\t\tmem_ready <= 1\'b0;
\t\t\t\t\t\twbm_stb_o <= 1\'b0;
\t\t\t\t\t\twbm_cyc_o <= 1\'b0;
\t\t\t\t\t\twbm_we_o <= 1\'b0;
\t\t\t\t\tend
\t\t\t\tend
\t\t\t\tWBSTART:begin
\t\t\t\t\tif (wbm_ack_i) begin
\t\t\t\t\t\tmem_rdata <= wbm_dat_i;
\t\t\t\t\t\tmem_ready <= 1\'b1;
\t\t\t\t\t\tstate <= WBEND;
\t\t\t\t\t\twbm_stb_o <= 1\'b0;
\t\t\t\t\t\twbm_cyc_o <= 1\'b0;
\t\t\t\t\t\twbm_we_o <= 1\'b0;
\t\t\t\t\tend
\t\t\t\tend
\t\t\t\tWBEND: begin
\t\t\t\t\tmem_ready <= 1\'b0;
\t\t\t\t\tstate <= IDLE;
\t\t\t\tend
\t\t\t\tdefault:
\t\t\t\t\tstate <= IDLE;
\t\t\tendcase
\t\tend
\tend
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_watchdog.v
//
// *Module Description:
// Watchdog Timer
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module omsp_watchdog (
// OUTPUTs
per_dout, // Peripheral data output
wdt_irq, // Watchdog-timer interrupt
wdt_reset, // Watchdog-timer reset
wdt_wkup, // Watchdog Wakeup
wdtifg, // Watchdog-timer interrupt flag
wdtnmies, // Watchdog-timer NMI edge selection
// INPUTs
aclk, // ACLK
aclk_en, // ACLK enable
dbg_freeze, // Freeze Watchdog counter
mclk, // Main system clock
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_we, // Peripheral write enable (high active)
por, // Power-on reset
puc_rst, // Main system reset
scan_enable, // Scan enable (active during scan shifting)
scan_mode, // Scan mode
smclk, // SMCLK
smclk_en, // SMCLK enable
wdtie, // Watchdog timer interrupt enable
wdtifg_irq_clr, // Watchdog-timer interrupt flag irq accepted clear
wdtifg_sw_clr, // Watchdog-timer interrupt flag software clear
wdtifg_sw_set // Watchdog-timer interrupt flag software set
);
// OUTPUTs
//=========
output [15:0] per_dout; // Peripheral data output
output wdt_irq; // Watchdog-timer interrupt
output wdt_reset; // Watchdog-timer reset
output wdt_wkup; // Watchdog Wakeup
output wdtifg; // Watchdog-timer interrupt flag
output wdtnmies; // Watchdog-timer NMI edge selection
// INPUTs
//=========
input aclk; // ACLK
input aclk_en; // ACLK enable
input dbg_freeze; // Freeze Watchdog counter
input mclk; // Main system clock
input [13:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input por; // Power-on reset
input puc_rst; // Main system reset
input scan_enable; // Scan enable (active during scan shifting)
input scan_mode; // Scan mode
input smclk; // SMCLK
input smclk_en; // SMCLK enable
input wdtie; // Watchdog timer interrupt enable
input wdtifg_irq_clr; // Clear Watchdog-timer interrupt flag
input wdtifg_sw_clr; // Watchdog-timer interrupt flag software clear
input wdtifg_sw_set; // Watchdog-timer interrupt flag software set
//=============================================================================
// 1) PARAMETER DECLARATION
//=============================================================================
// Register base address (must be aligned to decoder bit width)
parameter [14:0] BASE_ADDR = 15\'h0120;
// Decoder bit width (defines how many bits are considered for address decoding)
parameter DEC_WD = 2;
// Register addresses offset
parameter [DEC_WD-1:0] WDTCTL = \'h0;
// Register one-hot decoder utilities
parameter DEC_SZ = (1 << DEC_WD);
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1\'b0}}, 1\'b1};
// Register one-hot decoder
parameter [DEC_SZ-1:0] WDTCTL_D = (BASE_REG << WDTCTL);
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Local register selection
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
// Register local address
wire [DEC_WD-1:0] reg_addr = {per_addr[DEC_WD-2:0], 1\'b0};
// Register address decode
wire [DEC_SZ-1:0] reg_dec = (WDTCTL_D & {DEC_SZ{(reg_addr==WDTCTL)}});
// Read/Write probes
wire reg_write = |per_we & reg_sel;
wire reg_read = ~|per_we & reg_sel;
// Read/Write vectors
wire [DEC_SZ-1:0] reg_wr = reg_dec & {DEC_SZ{reg_write}};
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
//============================================================================
// 3) REGISTERS
//============================================================================
// WDTCTL Register
//-----------------
// WDTNMI is not implemented and therefore masked
reg [7:0] wdtctl;
wire wdtctl_wr = reg_wr[WDTCTL];
`ifdef CLOCK_GATING
wire mclk_wdtctl;
omsp_clock_gate clock_gate_wdtctl (.gclk(mclk_wdtctl),
.clk (mclk), .enable(wdtctl_wr), .scan_enable(scan_enable));
`else
wire UNUSED_scan_enable = scan_enable;
wire mclk_wdtctl = mclk;
`endif
`ifdef NMI
parameter [7:0] WDTNMIES_MASK = 8\'h40;
`else
parameter [7:0] WDTNMIES_MASK = 8\'h00;
`endif
`ifdef ASIC_CLOCKING
`ifdef WATCHDOG_MUX
parameter [7:0] WDTSSEL_MASK = 8\'h04;
`else
parameter [7:0] WDTSSEL_MASK = 8\'h00;
`endif
`else
parameter [7:0] WDTSSEL_MASK = 8\'h04;
`endif
parameter [7:0] WDTCTL_MASK = (8\'b1001_0011 | WDTSSEL_MASK | WDTNMIES_MASK);
always @ (posedge mclk_wdtctl or posedge puc_rst)
if (puc_rst) wdtctl <= 8\'h00;
`ifdef CLOCK_GATING
else wdtctl <= per_din[7:0] & WDTCTL_MASK;
`else
else if (wdtctl_wr) wdtctl <= per_din[7:0] & WDTCTL_MASK;
`endif
wire wdtpw_error = wdtctl_wr & (per_din[15:8]!=8\'h5a);
wire wdttmsel = wdtctl[4];
wire wdtnmies = wdtctl[6];
//============================================================================
// 4) DATA OUTPUT GENERATION
//============================================================================
`ifdef NMI
parameter [7:0] WDTNMI_RD_MASK = 8\'h20;
`else
parameter [7:0] WDTNMI_RD_MASK = 8\'h00;
`endif
`ifdef WATCHDOG_MUX
parameter [7:0] WDTSSEL_RD_MASK = 8\'h00;
`else
`ifdef WATCHDOG_NOMUX_ACLK
parameter [7:0] WDTSSEL_RD_MASK = 8\'h04;
`else
parameter [7:0] WDTSSEL_RD_MASK = 8\'h00;
`endif
`endif
parameter [7:0] WDTCTL_RD_MASK = WDTNMI_RD_MASK | WDTSSEL_RD_MASK;
// Data output mux
wire [15:0] wdtctl_rd = {8\'h69, wdtctl | WDTCTL_RD_MASK} & {16{reg_rd[WDTCTL]}};
wire [15:0] per_dout = wdtctl_rd;
//=============================================================================
// 5) WATCHDOG TIMER (ASIC IMPLEMENTATION)
//=============================================================================
`ifdef ASIC_CLOCKING
// Watchdog clock source selection
//---------------------------------
wire wdt_clk;
`ifdef WATCHDOG_MUX
omsp_clock_mux clock_mux_watchdog (
.clk_out (wdt_clk),
.clk_in0 (smclk),
.clk_in1 (aclk),
.reset (puc_rst),
.scan_mode (scan_mode),
.select_in (wdtctl[2])
);
`else
`ifdef WATCHDOG_NOMUX_ACLK
assign wdt_clk = aclk;
wire UNUSED_smclk = smclk;
`else
wire UNUSED_aclk = aclk;
assign wdt_clk = smclk;
`endif
`endif
// Reset synchronizer for the watchdog local clock domain
//--------------------------------------------------------
wire wdt_rst_noscan;
wire wdt_rst;
// Reset Synchronizer
omsp_sync_reset sync_reset_por (
.rst_s (wdt_rst_noscan),
.clk (wdt_clk),
.rst_a (puc_rst)
);
// Scan Reset Mux
omsp_scan_mux scan_mux_wdt_rst (
.scan_mode (scan_mode),
.data_in_scan (puc_rst),
.data_in_func (wdt_rst_noscan),
.data_out (wdt_rst)
);
// Watchog counter clear (synchronization)
//-----------------------------------------
// Toggle bit whenever the watchog needs to be cleared
reg wdtcnt_clr_toggle;
wire wdtcnt_clr_detect = (wdtctl_wr & per_din[3]);
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) wdtcnt_clr_toggle <= 1\'b0;
else if (wdtcnt_clr_detect) wdtcnt_clr_toggle <= ~wdtcnt_clr_toggle;
// Synchronization
wire wdtcnt_clr_sync;
omsp_sync_cell sync_cell_wdtcnt_clr (
.data_out (wdtcnt_clr_sync),
.data_in (wdtcnt_clr_toggle),
.clk (wdt_clk),
.rst (wdt_rst)
);
// Edge detection
reg wdtcnt_clr_sync_dly;
always @ (posedge wdt_clk or posedge wdt_rst)
if (wdt_rst) wdtcnt_clr_sync_dly <= 1\'b0;
else wdtcnt_clr_sync_dly <= wdtcnt_clr_sync;
wire wdtqn_edge;
wire wdtcnt_clr = (wdtcnt_clr_sync ^ wdtcnt_clr_sync_dly) | wdtqn_edge;
// Watchog counter increment (synchronization)
//----------------------------------------------
wire wdtcnt_incr;
omsp_sync_cell sync_cell_wdtcnt_incr (
.data_out (wdtcnt_incr),
.data_in (~wdtctl[7] & ~dbg_freeze),
.clk (wdt_clk),
.rst (wdt_rst)
);
// Watchdog 16 bit counter
//--------------------------
reg [15:0] wdtcnt;
wire [15:0] wdtcnt_nxt = wdtcnt+16\'h0001;
`ifdef CLOCK_GATING
wire wdtcnt_en = wdtcnt_clr | wdtcnt_incr;
wire wdt_clk_cnt;
omsp_clock_gate clock_gate_wdtcnt (.gclk(wdt_clk_cnt),
.clk (wdt_clk), .enable(wdtcnt_en), .scan_enable(scan_enable));
`else
wire wdt_clk_cnt = wdt_clk;
`endif
always @ (posedge wdt_clk_cnt or posedge wdt_rst)
if (wdt_rst) wdtcnt <= 16\'h0000;
else if (wdtcnt_clr) wdtcnt <= 16\'h0000;
`ifdef CLOCK_GATING
else wdtcnt <= wdtcnt_nxt;
`else
else if (wdtcnt_incr) wdtcnt <= wdtcnt_nxt;
`endif
// Local synchronizer for the wdtctl.WDTISx
// configuration (note that we can live with
// a full bus synchronizer as it won\'t hurt
// if we get a wrong WDTISx value for a
// single clock cycle)
//--------------------------------------------
reg [1:0] wdtisx_s;
reg [1:0] wdtisx_ss;
always @ (posedge wdt_clk_cnt or posedge wdt_rst)
if (wdt_rst)
begin
wdtisx_s <= 2\'h0;
wdtisx_ss <= 2\'h0;
end
else
begin
wdtisx_s <= wdtctl[1:0];
wdtisx_ss <= wdtisx_s;
end
// Interval selection mux
//--------------------------
reg wdtqn;
always @(wdtisx_ss or wdtcnt_nxt)
case(wdtisx_ss)
2\'b00 : wdtqn = wdtcnt_nxt[15];
2\'b01 : wdtqn = wdtcnt_nxt[13];
2\'b10 : wdtqn = wdtcnt_nxt[9];
default: wdtqn = wdtcnt_nxt[6];
endcase
// Watchdog event detection
//-----------------------------
// Interval end detection
assign wdtqn_edge = (wdtqn & wdtcnt_incr);
// Toggle bit for the transmition to the MCLK domain
reg wdt_evt_toggle;
always @ (posedge wdt_clk_cnt or posedge wdt_rst)
if (wdt_rst) wdt_evt_toggle <= 1\'b0;
else if (wdtqn_edge) wdt_evt_toggle <= ~wdt_evt_toggle;
// Synchronize in the MCLK domain
wire wdt_evt_toggle_sync;
omsp_sync_cell sync_cell_wdt_evt (
.data_out (wdt_evt_toggle_sync),
.data_in (wdt_evt_toggle),
.clk (mclk),
.rst (puc_rst)
);
// Delay for edge detection of the toggle bit
reg wdt_evt_toggle_sync_dly;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) wdt_evt_toggle_sync_dly <= 1\'b0;
else wdt_evt_toggle_sync_dly <= wdt_evt_toggle_sync;
wire wdtifg_evt = (wdt_evt_toggle_sync_dly ^ wdt_evt_toggle_sync) | wdtpw_error;
// Watchdog wakeup generation
//-------------------------------------------------------------
// Clear wakeup when the watchdog flag is cleared (glitch free)
reg wdtifg_clr_reg;
wire wdtifg_clr;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) wdtifg_clr_reg <= 1\'b1;
else wdtifg_clr_reg <= wdtifg_clr;
// Set wakeup when the watchdog event is detected (glitch free)
reg wdtqn_edge_reg;
always @ (posedge wdt_clk_cnt or posedge wdt_rst)
if (wdt_rst) wdtqn_edge_reg <= 1\'b0;
else wdtqn_edge_reg <= wdtqn_edge;
// Watchdog wakeup cell
wire wdt_wkup_pre;
omsp_wakeup_cell wakeup_cell_wdog (
.wkup_out (wdt_wkup_pre), // Wakup signal (asynchronous)
.scan_clk (mclk), // Scan clock
.scan_mode (scan_mode), // Scan mode
.scan_rst (puc_rst), // Scan reset
.wkup_clear (wdtifg_clr_reg), // Glitch free wakeup event clear
.wkup_event (wdtqn_edge_reg) // Glitch free asynchronous wakeup event
);
// When not in HOLD, the watchdog can generate a wakeup when:
// - in interval mode (if interrupts are enabled)
// - in reset mode (always)
reg wdt_wkup_en;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) wdt_wkup_en <= 1\'b0;
else wdt_wkup_en <= ~wdtctl[7] & (~wdttmsel | (wdttmsel & wdtie));
// Make wakeup when not enabled
wire wdt_wkup;
omsp_and_gate and_wdt_wkup (.y(wdt_wkup), .a(wdt_wkup_pre), .b(wdt_wkup_en));
// Watchdog interrupt flag
//------------------------------
reg wdtifg;
wire wdtifg_set = wdtifg_evt | wdtifg_sw_set;
assign wdtifg_clr = (wdtifg_irq_clr & wdttmsel) | wdtifg_sw_clr;
always @ (posedge mclk or posedge por)
if (por) wdtifg <= 1\'b0;
else if (wdtifg_set) wdtifg <= 1\'b1;
else if (wdtifg_clr) wdtifg <= 1\'b0;
// Watchdog interrupt generation
//---------------------------------
wire wdt_irq = wdttmsel & wdtifg & wdtie;
// Watchdog reset generation
//-----------------------------
reg wdt_reset;
always @ (posedge mclk or posedge por)
if (por) wdt_reset <= 1\'b0;
else wdt_reset <= wdtpw_error | (wdtifg_set & ~wdttmsel);
// LINT cleanup
wire UNUSED_smclk_en = smclk_en;
wire UNUSED_aclk_en = aclk_en;
//=============================================================================
// 6) WATCHDOG TIMER (FPGA IMPLEMENTATION)
//=============================================================================
`else
// Watchdog clock source selection
//---------------------------------
wire clk_src_en = wdtctl[2] ? aclk_en : smclk_en;
// Watchdog 16 bit counter
//--------------------------
reg [15:0] wdtcnt;
wire wdtifg_evt;
wire wdtcnt_clr = (wdtctl_wr & per_din[3]) | wdtifg_evt;
wire wdtcnt_incr = ~wdtctl[7] & clk_src_en & ~dbg_freeze;
wire [15:0] wdtcnt_nxt = wdtcnt+16\'h0001;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) wdtcnt <= 16\'h0000;
else if (wdtcnt_clr) wdtcnt <= 16\'h0000;
else if (wdtcnt_incr) wdtcnt <= wdtcnt_nxt;
// Interval selection mux
//--------------------------
reg wdtqn;
always @(wdtctl or wdtcnt_nxt)
case(wdtctl[1:0])
2\'b00 : wdtqn = wdtcnt_nxt[15];
2\'b01 : wdtqn = wdtcnt_nxt[13];
2\'b10 : wdtqn = wdtcnt_nxt[9];
default: wdtqn = wdtcnt_nxt[6];
endcase
// Watchdog event detection
//-----------------------------
assign wdtifg_evt = (wdtqn & wdtcnt_incr) | wdtpw_error;
// Watchdog interrupt flag
//------------------------------
reg wdtifg;
wire wdtifg_set = wdtifg_evt | wdtifg_sw_set;
wire wdtifg_clr = (wdtifg_irq_clr & wdttmsel) | wdtifg_sw_clr;
always @ (posedge mclk or posedge por)
if (por) wdtifg <= 1\'b0;
else if (wdtifg_set) wdtifg <= 1\'b1;
else if (wdtifg_clr) wdtifg <= 1\'b0;
// Watchdog interrupt generation
//---------------------------------
wire wdt_irq = wdttmsel & wdtifg & wdtie;
wire wdt_wkup = 1\'b0;
// Watchdog reset generation
//-----------------------------
reg wdt_reset;
always @ (posedge mclk or posedge por)
if (por) wdt_reset <= 1\'b0;
else wdt_reset <= wdtpw_error | (wdtifg_set & ~wdttmsel);
// LINT cleanup
wire UNUSED_scan_mode = scan_mode;
wire UNUSED_smclk = smclk;
wire UNUSED_aclk = aclk;
`endif
wire [15:0] UNUSED_per_din = per_din;
endmodule // omsp_watchdog
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_alu.v
//
// *Module Description:
// openMSP430 ALU
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module omsp_alu (
// OUTPUTs
alu_out, // ALU output value
alu_out_add, // ALU adder output value
alu_stat, // ALU Status {V,N,Z,C}
alu_stat_wr, // ALU Status write {V,N,Z,C}
// INPUTs
dbg_halt_st, // Halt/Run status from CPU
exec_cycle, // Instruction execution cycle
inst_alu, // ALU control signals
inst_bw, // Decoded Inst: byte width
inst_jmp, // Decoded Inst: Conditional jump
inst_so, // Single-operand arithmetic
op_dst, // Destination operand
op_src, // Source operand
status // R2 Status {V,N,Z,C}
);
// OUTPUTs
//=========
output [15:0] alu_out; // ALU output value
output [15:0] alu_out_add; // ALU adder output value
output [3:0] alu_stat; // ALU Status {V,N,Z,C}
output [3:0] alu_stat_wr; // ALU Status write {V,N,Z,C}
// INPUTs
//=========
input dbg_halt_st; // Halt/Run status from CPU
input exec_cycle; // Instruction execution cycle
input [11:0] inst_alu; // ALU control signals
input inst_bw; // Decoded Inst: byte width
input [7:0] inst_jmp; // Decoded Inst: Conditional jump
input [7:0] inst_so; // Single-operand arithmetic
input [15:0] op_dst; // Destination operand
input [15:0] op_src; // Source operand
input [3:0] status; // R2 Status {V,N,Z,C}
//=============================================================================
// 1) FUNCTIONS
//=============================================================================
function [4:0] bcd_add;
input [3:0] X;
input [3:0] Y;
input C_;
reg [4:0] Z_;
begin
Z_ = {1\'b0,X}+{1\'b0,Y}+{4\'b0000,C_};
if (Z_<5\'d10) bcd_add = Z_;
else bcd_add = Z_+5\'d6;
end
endfunction
//=============================================================================
// 2) INSTRUCTION FETCH/DECODE CONTROL STATE MACHINE
//=============================================================================
// SINGLE-OPERAND ARITHMETIC:
//-----------------------------------------------------------------------------
// Mnemonic S-Reg, Operation Status bits
// D-Reg, V N Z C
//
// RRC dst C->MSB->...LSB->C * * * *
// RRA dst MSB->MSB->...LSB->C 0 * * *
// SWPB dst Swap bytes - - - -
// SXT dst Bit7->Bit8...Bit15 0 * * *
// PUSH src SP-2->SP, src->@SP - - - -
// CALL dst SP-2->SP, PC+2->@SP, dst->PC - - - -
// RETI TOS->SR, SP+2->SP, TOS->PC, SP+2->SP * * * *
//
//-----------------------------------------------------------------------------
// TWO-OPERAND ARITHMETIC:
//-----------------------------------------------------------------------------
// Mnemonic S-Reg, Operation Status bits
// D-Reg, V N Z C
//
// MOV src,dst src -> dst - - - -
// ADD src,dst src + dst -> dst * * * *
// ADDC src,dst src + dst + C -> dst * * * *
// SUB src,dst dst + ~src + 1 -> dst * * * *
// SUBC src,dst dst + ~src + C -> dst * * * *
// CMP src,dst dst + ~src + 1 * * * *
// DADD src,dst src + dst + C -> dst (decimaly) * * * *
// BIT src,dst src & dst 0 * * *
// BIC src,dst ~src & dst -> dst - - - -
// BIS src,dst src | dst -> dst - - - -
// XOR src,dst src ^ dst -> dst * * * *
// AND src,dst src & dst -> dst 0 * * *
//
//-----------------------------------------------------------------------------
// * the status bit is affected
// - the status bit is not affected
// 0 the status bit is cleared
// 1 the status bit is set
//-----------------------------------------------------------------------------
// Invert source for substract and compare instructions.
wire op_src_inv_cmd = exec_cycle & (inst_alu[`ALU_SRC_INV]);
wire [15:0] op_src_inv = {16{op_src_inv_cmd}} ^ op_src;
// Mask the bit 8 for the Byte instructions for correct flags generation
wire op_bit8_msk = ~exec_cycle | ~inst_bw;
wire [16:0] op_src_in = {1\'b0, {op_src_inv[15:8] & {8{op_bit8_msk}}}, op_src_inv[7:0]};
wire [16:0] op_dst_in = {1\'b0, {op_dst[15:8] & {8{op_bit8_msk}}}, op_dst[7:0]};
// Clear the source operand (= jump offset) for conditional jumps
wire jmp_not_taken = (inst_jmp[`JL] & ~(status[3]^status[2])) |
(inst_jmp[`JGE] & (status[3]^status[2])) |
(inst_jmp[`JN] & ~status[2]) |
(inst_jmp[`JC] & ~status[0]) |
(inst_jmp[`JNC] & status[0]) |
(inst_jmp[`JEQ] & ~status[1]) |
(inst_jmp[`JNE] & status[1]);
wire [16:0] op_src_in_jmp = op_src_in & {17{~jmp_not_taken}};
// Adder / AND / OR / XOR
wire [16:0] alu_add = op_src_in_jmp + op_dst_in;
wire [16:0] alu_and = op_src_in & op_dst_in;
wire [16:0] alu_or = op_src_in | op_dst_in;
wire [16:0] alu_xor = op_src_in ^ op_dst_in;
// Incrementer
wire alu_inc = exec_cycle & ((inst_alu[`ALU_INC_C] & status[0]) |
inst_alu[`ALU_INC]);
wire [16:0] alu_add_inc = alu_add + {16\'h0000, alu_inc};
// Decimal adder (DADD)
wire [4:0] alu_dadd0 = bcd_add(op_src_in[3:0], op_dst_in[3:0], status[0]);
wire [4:0] alu_dadd1 = bcd_add(op_src_in[7:4], op_dst_in[7:4], alu_dadd0[4]);
wire [4:0] alu_dadd2 = bcd_add(op_src_in[11:8], op_dst_in[11:8], alu_dadd1[4]);
wire [4:0] alu_dadd3 = bcd_add(op_src_in[15:12], op_dst_in[15:12],alu_dadd2[4]);
wire [16:0] alu_dadd = {alu_dadd3, alu_dadd2[3:0], alu_dadd1[3:0], alu_dadd0[3:0]};
// Shifter for rotate instructions (RRC & RRA)
wire alu_shift_msb = inst_so[`RRC] ? status[0] :
inst_bw ? op_src[7] : op_src[15];
wire alu_shift_7 = inst_bw ? alu_shift_msb : op_src[8];
wire [16:0] alu_shift = {1\'b0, alu_shift_msb, op_src[15:9], alu_shift_7, op_src[7:1]};
// Swap bytes / Extend Sign
wire [16:0] alu_swpb = {1\'b0, op_src[7:0],op_src[15:8]};
wire [16:0] alu_sxt = {1\'b0, {8{op_src[7]}},op_src[7:0]};
// Combine short paths toghether to simplify final ALU mux
wire alu_short_thro = ~(inst_alu[`ALU_AND] |
inst_alu[`ALU_OR] |
inst_alu[`ALU_XOR] |
inst_alu[`ALU_SHIFT] |
inst_so[`SWPB] |
inst_so[`SXT]);
wire [16:0] alu_short = ({17{inst_alu[`ALU_AND]}} & alu_and) |
({17{inst_alu[`ALU_OR]}} & alu_or) |
({17{inst_alu[`ALU_XOR]}} & alu_xor) |
({17{inst_alu[`ALU_SHIFT]}} & alu_shift) |
({17{inst_so[`SWPB]}} & alu_swpb) |
({17{inst_so[`SXT]}} & alu_sxt) |
({17{alu_short_thro}} & op_src_in);
// ALU output mux
wire [16:0] alu_out_nxt = (inst_so[`IRQ] | dbg_halt_st |
inst_alu[`ALU_ADD]) ? alu_add_inc :
inst_alu[`ALU_DADD] ? alu_dadd : alu_short;
assign alu_out = alu_out_nxt[15:0];
assign alu_out_add = alu_add[15:0];
//-----------------------------------------------------------------------------
// STATUS FLAG GENERATION
//-----------------------------------------------------------------------------
wire V_xor = inst_bw ? (op_src_in[7] & op_dst_in[7]) :
(op_src_in[15] & op_dst_in[15]);
wire V = inst_bw ? ((~op_src_in[7] & ~op_dst_in[7] & alu_out[7]) |
( op_src_in[7] & op_dst_in[7] & ~alu_out[7])) :
((~op_src_in[15] & ~op_dst_in[15] & alu_out[15]) |
( op_src_in[15] & op_dst_in[15] & ~alu_out[15]));
wire N = inst_bw ? alu_out[7] : alu_out[15];
wire Z = inst_bw ? (alu_out[7:0]==0) : (alu_out==0);
wire C = inst_bw ? alu_out[8] : alu_out_nxt[16];
assign alu_stat = inst_alu[`ALU_SHIFT] ? {1\'b0, N,Z,op_src_in[0]} :
inst_alu[`ALU_STAT_7] ? {1\'b0, N,Z,~Z} :
inst_alu[`ALU_XOR] ? {V_xor,N,Z,~Z} : {V,N,Z,C};
assign alu_stat_wr = (inst_alu[`ALU_STAT_F] & exec_cycle) ? 4\'b1111 : 4\'b0000;
// LINT cleanup
wire UNUSED_inst_so_rra = inst_so[`RRA];
wire UNUSED_inst_so_push = inst_so[`PUSH];
wire UNUSED_inst_so_call = inst_so[`CALL];
wire UNUSED_inst_so_reti = inst_so[`RETI];
wire UNUSED_inst_jmp = inst_jmp[`JMP];
wire UNUSED_inst_alu = inst_alu[`EXEC_NO_WR];
endmodule // omsp_alu
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_multiplier.v
//
// *Module Description:
// 16x16 Hardware multiplier.
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 23 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module omsp_multiplier (
// OUTPUTs
per_dout, // Peripheral data output
// INPUTs
mclk, // Main system clock
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_we, // Peripheral write enable (high active)
puc_rst, // Main system reset
scan_enable // Scan enable (active during scan shifting)
);
// OUTPUTs
//=========
output [15:0] per_dout; // Peripheral data output
// INPUTs
//=========
input mclk; // Main system clock
input [13:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input puc_rst; // Main system reset
input scan_enable; // Scan enable (active during scan shifting)
//=============================================================================
// 1) PARAMETER/REGISTERS & WIRE DECLARATION
//=============================================================================
// Register base address (must be aligned to decoder bit width)
parameter [14:0] BASE_ADDR = 15\'h0130;
// Decoder bit width (defines how many bits are considered for address decoding)
parameter DEC_WD = 4;
// Register addresses offset
parameter [DEC_WD-1:0] OP1_MPY = \'h0,
OP1_MPYS = \'h2,
OP1_MAC = \'h4,
OP1_MACS = \'h6,
OP2 = \'h8,
RESLO = \'hA,
RESHI = \'hC,
SUMEXT = \'hE;
// Register one-hot decoder utilities
parameter DEC_SZ = (1 << DEC_WD);
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1\'b0}}, 1\'b1};
// Register one-hot decoder
parameter [DEC_SZ-1:0] OP1_MPY_D = (BASE_REG << OP1_MPY),
OP1_MPYS_D = (BASE_REG << OP1_MPYS),
OP1_MAC_D = (BASE_REG << OP1_MAC),
OP1_MACS_D = (BASE_REG << OP1_MACS),
OP2_D = (BASE_REG << OP2),
RESLO_D = (BASE_REG << RESLO),
RESHI_D = (BASE_REG << RESHI),
SUMEXT_D = (BASE_REG << SUMEXT);
// Wire pre-declarations
wire result_wr;
wire result_clr;
wire early_read;
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Local register selection
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
// Register local address
wire [DEC_WD-1:0] reg_addr = {per_addr[DEC_WD-2:0], 1\'b0};
// Register address decode
wire [DEC_SZ-1:0] reg_dec = (OP1_MPY_D & {DEC_SZ{(reg_addr == OP1_MPY )}}) |
(OP1_MPYS_D & {DEC_SZ{(reg_addr == OP1_MPYS )}}) |
(OP1_MAC_D & {DEC_SZ{(reg_addr == OP1_MAC )}}) |
(OP1_MACS_D & {DEC_SZ{(reg_addr == OP1_MACS )}}) |
(OP2_D & {DEC_SZ{(reg_addr == OP2 )}}) |
(RESLO_D & {DEC_SZ{(reg_addr == RESLO )}}) |
(RESHI_D & {DEC_SZ{(reg_addr == RESHI )}}) |
(SUMEXT_D & {DEC_SZ{(reg_addr == SUMEXT )}});
// Read/Write probes
wire reg_write = |per_we & reg_sel;
wire reg_read = ~|per_we & reg_sel;
// Read/Write vectors
wire [DEC_SZ-1:0] reg_wr = reg_dec & {DEC_SZ{reg_write}};
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
// Masked input data for byte access
wire [15:0] per_din_msk = per_din & {{8{per_we[1]}}, 8\'hff};
//============================================================================
// 3) REGISTERS
//============================================================================
// OP1 Register
//-----------------
reg [15:0] op1;
wire op1_wr = reg_wr[OP1_MPY] |
reg_wr[OP1_MPYS] |
reg_wr[OP1_MAC] |
reg_wr[OP1_MACS];
`ifdef CLOCK_GATING
wire mclk_op1;
omsp_clock_gate clock_gate_op1 (.gclk(mclk_op1),
.clk (mclk), .enable(op1_wr), .scan_enable(scan_enable));
`else
wire UNUSED_scan_enable = scan_enable;
wire mclk_op1 = mclk;
`endif
always @ (posedge mclk_op1 or posedge puc_rst)
if (puc_rst) op1 <= 16\'h0000;
`ifdef CLOCK_GATING
else op1 <= per_din_msk;
`else
else if (op1_wr) op1 <= per_din_msk;
`endif
wire [15:0] op1_rd = op1;
// OP2 Register
//-----------------
reg [15:0] op2;
wire op2_wr = reg_wr[OP2];
`ifdef CLOCK_GATING
wire mclk_op2;
omsp_clock_gate clock_gate_op2 (.gclk(mclk_op2),
.clk (mclk), .enable(op2_wr), .scan_enable(scan_enable));
`else
wire mclk_op2 = mclk;
`endif
always @ (posedge mclk_op2 or posedge puc_rst)
if (puc_rst) op2 <= 16\'h0000;
`ifdef CLOCK_GATING
else op2 <= per_din_msk;
`else
else if (op2_wr) op2 <= per_din_msk;
`endif
wire [15:0] op2_rd = op2;
// RESLO Register
//-----------------
reg [15:0] reslo;
wire [15:0] reslo_nxt;
wire reslo_wr = reg_wr[RESLO];
`ifdef CLOCK_GATING
wire reslo_en = reslo_wr | result_clr | result_wr;
wire mclk_reslo;
omsp_clock_gate clock_gate_reslo (.gclk(mclk_reslo),
.clk (mclk), .enable(reslo_en), .scan_enable(scan_enable));
`else
wire mclk_reslo = mclk;
`endif
always @ (posedge mclk_reslo or posedge puc_rst)
if (puc_rst) reslo <= 16\'h0000;
else if (reslo_wr) reslo <= per_din_msk;
else if (result_clr) reslo <= 16\'h0000;
`ifdef CLOCK_GATING
else reslo <= reslo_nxt;
`else
else if (result_wr) reslo <= reslo_nxt;
`endif
wire [15:0] reslo_rd = early_read ? reslo_nxt : reslo;
// RESHI Register
//-----------------
reg [15:0] reshi;
wire [15:0] reshi_nxt;
wire reshi_wr = reg_wr[RESHI];
`ifdef CLOCK_GATING
wire reshi_en = reshi_wr | result_clr | result_wr;
wire mclk_reshi;
omsp_clock_gate clock_gate_reshi (.gclk(mclk_reshi),
.clk (mclk), .enable(reshi_en), .scan_enable(scan_enable));
`else
wire mclk_reshi = mclk;
`endif
always @ (posedge mclk_reshi or posedge puc_rst)
if (puc_rst) reshi <= 16\'h0000;
else if (reshi_wr) reshi <= per_din_msk;
else if (result_clr) reshi <= 16\'h0000;
`ifdef CLOCK_GATING
else reshi <= reshi_nxt;
`else
else if (result_wr) reshi <= reshi_nxt;
`endif
wire [15:0] reshi_rd = early_read ? reshi_nxt : reshi;
// SUMEXT Register
//-----------------
reg [1:0] sumext_s;
wire [1:0] sumext_s_nxt;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) sumext_s <= 2\'b00;
else if (op2_wr) sumext_s <= 2\'b00;
else if (result_wr) sumext_s <= sumext_s_nxt;
wire [15:0] sumext_nxt = {{14{sumext_s_nxt[1]}}, sumext_s_nxt};
wire [15:0] sumext = {{14{sumext_s[1]}}, sumext_s};
wire [15:0] sumext_rd = early_read ? sumext_nxt : sumext;
//============================================================================
// 4) DATA OUTPUT GENERATION
//============================================================================
// Data output mux
wire [15:0] op1_mux = op1_rd & {16{reg_rd[OP1_MPY] |
reg_rd[OP1_MPYS] |
reg_rd[OP1_MAC] |
reg_rd[OP1_MACS]}};
wire [15:0] op2_mux = op2_rd & {16{reg_rd[OP2]}};
wire [15:0] reslo_mux = reslo_rd & {16{reg_rd[RESLO]}};
wire [15:0] reshi_mux = reshi_rd & {16{reg_rd[RESHI]}};
wire [15:0] sumext_mux = sumext_rd & {16{reg_rd[SUMEXT]}};
wire [15:0] per_dout = op1_mux |
op2_mux |
reslo_mux |
reshi_mux |
sumext_mux;
//============================================================================
// 5) HARDWARE MULTIPLIER FUNCTIONAL LOGIC
//============================================================================
// Multiplier configuration
//--------------------------
// Detect signed mode
reg sign_sel;
always @ (posedge mclk_op1 or posedge puc_rst)
if (puc_rst) sign_sel <= 1\'b0;
`ifdef CLOCK_GATING
else sign_sel <= reg_wr[OP1_MPYS] | reg_wr[OP1_MACS];
`else
else if (op1_wr) sign_sel <= reg_wr[OP1_MPYS] | reg_wr[OP1_MACS];
`endif
// Detect accumulate mode
reg acc_sel;
always @ (posedge mclk_op1 or posedge puc_rst)
if (puc_rst) acc_sel <= 1\'b0;
`ifdef CLOCK_GATING
else acc_sel <= reg_wr[OP1_MAC] | reg_wr[OP1_MACS];
`else
else if (op1_wr) acc_sel <= reg_wr[OP1_MAC] | reg_wr[OP1_MACS];
`endif
// Detect whenever the RESHI and RESLO registers should be cleared
assign result_clr = op2_wr & ~acc_sel;
// Combine RESHI & RESLO
wire [31:0] result = {reshi, reslo};
// 16x16 Multiplier (result computed in 1 clock cycle)
//-----------------------------------------------------
`ifdef MPY_16x16
// Detect start of a multiplication
reg cycle;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cycle <= 1\'b0;
else cycle <= op2_wr;
assign result_wr = cycle;
// Expand the operands to support signed & unsigned operations
wire signed [16:0] op1_xp = {sign_sel & op1[15], op1};
wire signed [16:0] op2_xp = {sign_sel & op2[15], op2};
// 17x17 signed multiplication
wire signed [33:0] product = op1_xp * op2_xp;
// Accumulate
wire [32:0] result_nxt = {1\'b0, result} + {1\'b0, product[31:0]};
// Next register values
assign reslo_nxt = result_nxt[15:0];
assign reshi_nxt = result_nxt[31:16];
assign sumext_s_nxt = sign_sel ? {2{result_nxt[31]}} :
{1\'b0, result_nxt[32]};
// Since the MAC is completed within 1 clock cycle,
// an early read can\'t happen.
assign early_read = 1\'b0;
// 16x8 Multiplier (result computed in 2 clock cycles)
//-----------------------------------------------------
`else
// Detect start of a multiplication
reg [1:0] cycle;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cycle <= 2\'b00;
else cycle <= {cycle[0], op2_wr};
assign result_wr = |cycle;
// Expand the operands to support signed & unsigned operations
wire signed [16:0] op1_xp = {sign_sel & op1[15], op1};
wire signed [8:0] op2_hi_xp = {sign_sel & op2[15], op2[15:8]};
wire signed [8:0] op2_lo_xp = { 1\'b0, op2[7:0]};
wire signed [8:0] op2_xp = cycle[0] ? op2_hi_xp : op2_lo_xp;
// 17x9 signed multiplication
wire signed [25:0] product = op1_xp * op2_xp;
wire [31:0] product_xp = cycle[0] ? {product[23:0], 8\'h00} :
{{8{sign_sel & product[23]}}, product[23:0]};
// Accumulate
wire [32:0] result_nxt = {1\'b0, result} + {1\'b0, product_xp[31:0]};
// Next register values
assign reslo_nxt = result_nxt[15:0];
assign reshi_nxt = result_nxt[31:16];
assign sumext_s_nxt = sign_sel ? {2{result_nxt[31]}} :
{1\'b0, result_nxt[32] | sumext_s[0]};
// Since the MAC is completed within 2 clock cycle,
// an early read can happen during the second cycle.
assign early_read = cycle[1];
`endif
endmodule // omsp_multiplier
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: template_periph_8b.v
//
// *Module Description:
// 8 bit peripheral template.
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
module template_periph_8b (
// OUTPUTs
per_dout, // Peripheral data output
// INPUTs
mclk, // Main system clock
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_we, // Peripheral write enable (high active)
puc_rst // Main system reset
);
// OUTPUTs
//=========
output [15:0] per_dout; // Peripheral data output
// INPUTs
//=========
input mclk; // Main system clock
input [13:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input puc_rst; // Main system reset
//=============================================================================
// 1) PARAMETER DECLARATION
//=============================================================================
// Register base address (must be aligned to decoder bit width)
parameter [14:0] BASE_ADDR = 15\'h0090;
// Decoder bit width (defines how many bits are considered for address decoding)
parameter DEC_WD = 2;
// Register addresses offset
parameter [DEC_WD-1:0] CNTRL1 = \'h0,
CNTRL2 = \'h1,
CNTRL3 = \'h2,
CNTRL4 = \'h3;
// Register one-hot decoder utilities
parameter DEC_SZ = (1 << DEC_WD);
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1\'b0}}, 1\'b1};
// Register one-hot decoder
parameter [DEC_SZ-1:0] CNTRL1_D = (BASE_REG << CNTRL1),
CNTRL2_D = (BASE_REG << CNTRL2),
CNTRL3_D = (BASE_REG << CNTRL3),
CNTRL4_D = (BASE_REG << CNTRL4);
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Local register selection
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
// Register local address
wire [DEC_WD-1:0] reg_addr = {1\'b0, per_addr[DEC_WD-2:0]};
// Register address decode
wire [DEC_SZ-1:0] reg_dec = (CNTRL1_D & {DEC_SZ{(reg_addr==(CNTRL1 >>1))}}) |
(CNTRL2_D & {DEC_SZ{(reg_addr==(CNTRL2 >>1))}}) |
(CNTRL3_D & {DEC_SZ{(reg_addr==(CNTRL3 >>1))}}) |
(CNTRL4_D & {DEC_SZ{(reg_addr==(CNTRL4 >>1))}});
// Read/Write probes
wire reg_lo_write = per_we[0] & reg_sel;
wire reg_hi_write = per_we[1] & reg_sel;
wire reg_read = ~|per_we & reg_sel;
// Read/Write vectors
wire [DEC_SZ-1:0] reg_hi_wr = reg_dec & {DEC_SZ{reg_hi_write}};
wire [DEC_SZ-1:0] reg_lo_wr = reg_dec & {DEC_SZ{reg_lo_write}};
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
//============================================================================
// 3) REGISTERS
//============================================================================
// CNTRL1 Register
//-----------------
reg [7:0] cntrl1;
wire cntrl1_wr = CNTRL1[0] ? reg_hi_wr[CNTRL1] : reg_lo_wr[CNTRL1];
wire [7:0] cntrl1_nxt = CNTRL1[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cntrl1 <= 8\'h00;
else if (cntrl1_wr) cntrl1 <= cntrl1_nxt;
// CNTRL2 Register
//-----------------
reg [7:0] cntrl2;
wire cntrl2_wr = CNTRL2[0] ? reg_hi_wr[CNTRL2] : reg_lo_wr[CNTRL2];
wire [7:0] cntrl2_nxt = CNTRL2[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cntrl2 <= 8\'h00;
else if (cntrl2_wr) cntrl2 <= cntrl2_nxt;
// CNTRL3 Register
//-----------------
reg [7:0] cntrl3;
wire cntrl3_wr = CNTRL3[0] ? reg_hi_wr[CNTRL3] : reg_lo_wr[CNTRL3];
wire [7:0] cntrl3_nxt = CNTRL3[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cntrl3 <= 8\'h00;
else if (cntrl3_wr) cntrl3 <= cntrl3_nxt;
// CNTRL4 Register
//-----------------
reg [7:0] cntrl4;
wire cntrl4_wr = CNTRL4[0] ? reg_hi_wr[CNTRL4] : reg_lo_wr[CNTRL4];
wire [7:0] cntrl4_nxt = CNTRL4[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cntrl4 <= 8\'h00;
else if (cntrl4_wr) cntrl4 <= cntrl4_nxt;
//============================================================================
// 4) DATA OUTPUT GENERATION
//============================================================================
// Data output mux
wire [15:0] cntrl1_rd = {8\'h00, (cntrl1 & {8{reg_rd[CNTRL1]}})} << (8 & {4{CNTRL1[0]}});
wire [15:0] cntrl2_rd = {8\'h00, (cntrl2 & {8{reg_rd[CNTRL2]}})} << (8 & {4{CNTRL2[0]}});
wire [15:0] cntrl3_rd = {8\'h00, (cntrl3 & {8{reg_rd[CNTRL3]}})} << (8 & {4{CNTRL3[0]}});
wire [15:0] cntrl4_rd = {8\'h00, (cntrl4 & {8{reg_rd[CNTRL4]}})} << (8 & {4{CNTRL4[0]}});
wire [15:0] per_dout = cntrl1_rd |
cntrl2_rd |
cntrl3_rd |
cntrl4_rd;
endmodule // template_periph_8b
|
`timescale 1 ns / 1 ps
module system (
\tinput clk,
\tinput resetn,
`ifndef verilator
output sck,
output cs,
output mosi,
input miso,
output txd,
\t input rxd,
`endif
\toutput trap
);
\t// 32768 32bit words = 128kB memory
\tparameter MEM_SIZE = 32768;
integer tb_idx;
\twire mem_valid;
\twire mem_instr;
\treg mem_ready;
reg mem_ready_last;
\twire [31:0] mem_addr;
\twire [31:0] mem_wdata;
\twire [3:0] mem_wstrb;
\treg [31:0] mem_rdata;
wire [31:0] irqs;
wire [31:0] eois;
wire spi_cs;
wire uart_cs;
wire uart_done;
wire mem_cs;
wire [3:0] wstrb;
wire wr;
wire rd;
wire [31:0] spi_rdata;
wire spi_done;
wire [31:0] uart_rdata;
\t\t
\tpicorv32 picorv32_core (
\t\t.clk (clk ),
\t\t.resetn (resetn ),
\t\t.trap (trap ),
\t\t.mem_valid (mem_valid ),
\t\t.mem_instr (mem_instr ),
\t\t.mem_ready (mem_ready ),
\t\t.mem_addr (mem_addr ),
\t\t.mem_wdata (mem_wdata ),
\t\t.mem_wstrb (mem_wstrb ),
\t\t.mem_rdata (mem_rdata ),
.irq(irqs),
.eoi(eois)
\t);
`ifdef verilator
simsd sd(
\t\t.clk(clk),
\t\t.cs(spi_cs),
\t\t.bus_addr(mem_addr),
\t\t.bus_wr_val(mem_wdata),
\t\t.bus_bytesel(mem_wstrb && mem_ready),
\t\t.bus_ack(spi_done),
\t\t.bus_data(spi_rdata)
);
`else
spi #(
.CLOCK_FREQ_HZ(50000000),
.CS_LENGTH(1)
) sd (
\t\t.clk(clk),
.resetn(resetn),
.ctrl_addr(mem_addr),
.ctrl_wdat(mem_wdata),
.ctrl_rdat(spi_rdata),
.ctrl_wr(spi_cs && wr),
.ctrl_rd(spi_cs && rd),
.ctrl_done(spi_done),
.sclk(sck),
.mosi(mosi),
.miso(miso),
.cs(cs)
);
\t\t\t\t
\t\t rs232 uart(
\t\t .clk(clk),
\t\t .resetn(resetn),
\t\t .ctrl_wr(uart_cs && wr),
\t\t .ctrl_rd(uart_cs && rd),
\t\t .ctrl_addr(mem_addr),
\t\t .ctrl_wdat(mem_wdata),
\t\t .ctrl_rdat(uart_rdata),
\t\t .ctrl_done(uart_done),
\t\t .rxd(rxd),
\t\t .txd(txd)
\t\t );
`endif
assign irqs[31:1] = 31\'b0;
assign spi_cs = mem_addr[31:4] == 28\'h4000000 && mem_valid;
assign uart_cs = mem_addr[31:4] == 32\'h2000000 && mem_valid;
assign mem_cs = (mem_addr >> 2) < MEM_SIZE && mem_valid;
assign wr = |mem_wstrb && !mem_ready;
assign rd = !mem_wstrb && !mem_ready;
\t\t
reg [3:0][7:0] memory [0:MEM_SIZE-1];
\tinitial begin
// for (tb_idx=0; tb_idx < MEM_SIZE; tb_idx=tb_idx+1)
// memory[tb_idx] = 32\'b0;
$readmemh("../firmware.hex", memory);
end
\treg [31:0] m_read_data;
\treg m_read_en;
\talways @(posedge clk) begin
\t\t\tm_read_en <= 0;
\t\t\tmem_ready <= mem_valid && !mem_ready_last && !mem_ready && m_read_en;
mem_ready_last <= mem_ready;
\t\t\t(* parallel_case *)
\t\t\tcase (1)
\t\t\t\tmem_cs:
begin
if(wr) begin
if (mem_wstrb[0]) memory[mem_addr >> 2][0] <= mem_wdata[ 7: 0];
\t\t\t\t\t\t\t\t\t\tif (mem_wstrb[1]) memory[mem_addr >> 2][1] <= mem_wdata[15: 8];
\t\t\t\t\t\t\t\t\t\tif (mem_wstrb[2]) memory[mem_addr >> 2][2] <= mem_wdata[23:16];
\t\t\t\t\t\t\t\t\t\tif (mem_wstrb[3]) memory[mem_addr >> 2][3] <= mem_wdata[31:24];
mem_ready <= 1;
end
\tm_read_en <= 1;
\t\t\t\t m_read_data[31:0]<= memory[mem_addr >> 2];\t\t\t\t\t\t
\t\t\t\t mem_rdata <= m_read_data;
\t\t\t\tend
\t\t\t\t
spi_cs : begin
if(rd) begin
\t\t\t\t\tm_read_en <= spi_done;
mem_rdata <= spi_rdata;
end
if(wr) mem_ready <= spi_done;
\t\t\t\tend
\t\t\t\tuart_cs: begin
if(rd) begin
\tm_read_en <= uart_done;
mem_rdata <= uart_rdata;
end
if(wr) begin
mem_ready <= uart_done;
`ifdef verilator
if (resetn) $write("%c", mem_wdata);
\t \t\t\t\t mem_ready <= 1;
\t\t\t\t `endif
\t\t\t end
end
\t\t\tendcase
\t\tend
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_dbg_uart.v
//
// *Module Description:
// Debug UART communication interface (8N1, Half-duplex)
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module omsp_dbg_uart (
// OUTPUTs
dbg_addr, // Debug register address
dbg_din, // Debug register data input
dbg_rd, // Debug register data read
dbg_uart_txd, // Debug interface: UART TXD
dbg_wr, // Debug register data write
// INPUTs
dbg_clk, // Debug unit clock
dbg_dout, // Debug register data output
dbg_rd_rdy, // Debug register data is ready for read
dbg_rst, // Debug unit reset
dbg_uart_rxd, // Debug interface: UART RXD
mem_burst, // Burst on going
mem_burst_end, // End TX/RX burst
mem_burst_rd, // Start TX burst
mem_burst_wr, // Start RX burst
mem_bw // Burst byte width
);
// OUTPUTs
//=========
output [5:0] dbg_addr; // Debug register address
output [15:0] dbg_din; // Debug register data input
output dbg_rd; // Debug register data read
output dbg_uart_txd; // Debug interface: UART TXD
output dbg_wr; // Debug register data write
// INPUTs
//=========
input dbg_clk; // Debug unit clock
input [15:0] dbg_dout; // Debug register data output
input dbg_rd_rdy; // Debug register data is ready for read
input dbg_rst; // Debug unit reset
input dbg_uart_rxd; // Debug interface: UART RXD
input mem_burst; // Burst on going
input mem_burst_end; // End TX/RX burst
input mem_burst_rd; // Start TX burst
input mem_burst_wr; // Start RX burst
input mem_bw; // Burst byte width
//=============================================================================
// 1) UART RECEIVE LINE SYNCHRONIZTION & FILTERING
//=============================================================================
// Synchronize RXD input
//--------------------------------
`ifdef SYNC_DBG_UART_RXD
wire uart_rxd_n;
omsp_sync_cell sync_cell_uart_rxd (
.data_out (uart_rxd_n),
.data_in (~dbg_uart_rxd),
.clk (dbg_clk),
.rst (dbg_rst)
);
wire uart_rxd = ~uart_rxd_n;
`else
wire uart_rxd = dbg_uart_rxd;
`endif
// RXD input buffer
//--------------------------------
reg [1:0] rxd_buf;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) rxd_buf <= 2\'h3;
else rxd_buf <= {rxd_buf[0], uart_rxd};
// Majority decision
//------------------------
reg rxd_maj;
wire rxd_maj_nxt = (uart_rxd & rxd_buf[0]) |
(uart_rxd & rxd_buf[1]) |
(rxd_buf[0] & rxd_buf[1]);
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) rxd_maj <= 1\'b1;
else rxd_maj <= rxd_maj_nxt;
wire rxd_s = rxd_maj;
wire rxd_fe = rxd_maj & ~rxd_maj_nxt;
wire rxd_re = ~rxd_maj & rxd_maj_nxt;
wire rxd_edge = rxd_maj ^ rxd_maj_nxt;
//=============================================================================
// 2) UART STATE MACHINE
//=============================================================================
// Receive state
//------------------------
reg [2:0] uart_state;
reg [2:0] uart_state_nxt;
wire sync_done;
wire xfer_done;
reg [19:0] xfer_buf;
wire [19:0] xfer_buf_nxt;
// State machine definition
parameter RX_SYNC = 3\'h0;
parameter RX_CMD = 3\'h1;
parameter RX_DATA1 = 3\'h2;
parameter RX_DATA2 = 3\'h3;
parameter TX_DATA1 = 3\'h4;
parameter TX_DATA2 = 3\'h5;
// State transition
always @(uart_state or xfer_buf_nxt or mem_burst or mem_burst_wr or mem_burst_rd or mem_burst_end or mem_bw)
case (uart_state)
RX_SYNC : uart_state_nxt = RX_CMD;
RX_CMD : uart_state_nxt = mem_burst_wr ?
(mem_bw ? RX_DATA2 : RX_DATA1) :
mem_burst_rd ?
(mem_bw ? TX_DATA2 : TX_DATA1) :
(xfer_buf_nxt[`DBG_UART_WR] ?
(xfer_buf_nxt[`DBG_UART_BW] ? RX_DATA2 : RX_DATA1) :
(xfer_buf_nxt[`DBG_UART_BW] ? TX_DATA2 : TX_DATA1));
RX_DATA1 : uart_state_nxt = RX_DATA2;
RX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
(mem_bw ? RX_DATA2 : RX_DATA1) :
RX_CMD;
TX_DATA1 : uart_state_nxt = TX_DATA2;
TX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
(mem_bw ? TX_DATA2 : TX_DATA1) :
RX_CMD;
// pragma coverage off
default : uart_state_nxt = RX_CMD;
// pragma coverage on
endcase
// State machine
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) uart_state <= RX_SYNC;
else if (xfer_done | sync_done |
mem_burst_wr | mem_burst_rd) uart_state <= uart_state_nxt;
// Utility signals
wire cmd_valid = (uart_state==RX_CMD) & xfer_done;
wire rx_active = (uart_state==RX_DATA1) | (uart_state==RX_DATA2) | (uart_state==RX_CMD);
wire tx_active = (uart_state==TX_DATA1) | (uart_state==TX_DATA2);
//=============================================================================
// 3) UART SYNCHRONIZATION
//=============================================================================
// After DBG_RST, the host needs to fist send a synchronization character (0x80)
// If this feature doesn\'t work properly, it is possible to disable it by
// commenting the DBG_UART_AUTO_SYNC define in the openMSP430.inc file.
reg sync_busy;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) sync_busy <= 1\'b0;
else if ((uart_state==RX_SYNC) & rxd_fe) sync_busy <= 1\'b1;
else if ((uart_state==RX_SYNC) & rxd_re) sync_busy <= 1\'b0;
assign sync_done = (uart_state==RX_SYNC) & rxd_re & sync_busy;
`ifdef DBG_UART_AUTO_SYNC
reg [`DBG_UART_XFER_CNT_W+2:0] sync_cnt;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) sync_cnt <= {{`DBG_UART_XFER_CNT_W{1\'b1}}, 3\'b000};
else if (sync_busy | (~sync_busy & sync_cnt[2])) sync_cnt <= sync_cnt+{{`DBG_UART_XFER_CNT_W+2{1\'b0}}, 1\'b1};
wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = sync_cnt[`DBG_UART_XFER_CNT_W+2:3];
`else
wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = `DBG_UART_CNT;
`endif
//=============================================================================
// 4) UART RECEIVE / TRANSMIT
//=============================================================================
// Transfer counter
//------------------------
reg [3:0] xfer_bit;
reg [`DBG_UART_XFER_CNT_W-1:0] xfer_cnt;
wire txd_start = dbg_rd_rdy | (xfer_done & (uart_state==TX_DATA1));
wire rxd_start = (xfer_bit==4\'h0) & rxd_fe & ((uart_state!=RX_SYNC));
wire xfer_bit_inc = (xfer_bit!=4\'h0) & (xfer_cnt=={`DBG_UART_XFER_CNT_W{1\'b0}});
assign xfer_done = rx_active ? (xfer_bit==4\'ha) : (xfer_bit==4\'hb);
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) xfer_bit <= 4\'h0;
else if (txd_start | rxd_start) xfer_bit <= 4\'h1;
else if (xfer_done) xfer_bit <= 4\'h0;
else if (xfer_bit_inc) xfer_bit <= xfer_bit+4\'h1;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) xfer_cnt <= {`DBG_UART_XFER_CNT_W{1\'b0}};
else if (rx_active & rxd_edge) xfer_cnt <= {1\'b0, bit_cnt_max[`DBG_UART_XFER_CNT_W-1:1]};
else if (txd_start | xfer_bit_inc) xfer_cnt <= bit_cnt_max;
else if (|xfer_cnt) xfer_cnt <= xfer_cnt+{`DBG_UART_XFER_CNT_W{1\'b1}};
// Receive/Transmit buffer
//-------------------------
assign xfer_buf_nxt = {rxd_s, xfer_buf[19:1]};
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) xfer_buf <= 20\'h00000;
else if (dbg_rd_rdy) xfer_buf <= {1\'b1, dbg_dout[15:8], 2\'b01, dbg_dout[7:0], 1\'b0};
else if (xfer_bit_inc) xfer_buf <= xfer_buf_nxt;
// Generate TXD output
//------------------------
reg dbg_uart_txd;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_uart_txd <= 1\'b1;
else if (xfer_bit_inc & tx_active) dbg_uart_txd <= xfer_buf[0];
//=============================================================================
// 5) INTERFACE TO DEBUG REGISTERS
//=============================================================================
reg [5:0] dbg_addr;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_addr <= 6\'h00;
else if (cmd_valid) dbg_addr <= xfer_buf_nxt[`DBG_UART_ADDR];
reg dbg_bw;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_bw <= 1\'b0;
else if (cmd_valid) dbg_bw <= xfer_buf_nxt[`DBG_UART_BW];
wire dbg_din_bw = mem_burst ? mem_bw : dbg_bw;
wire [15:0] dbg_din = dbg_din_bw ? {8\'h00, xfer_buf_nxt[18:11]} :
{xfer_buf_nxt[18:11], xfer_buf_nxt[9:2]};
wire dbg_wr = (xfer_done & (uart_state==RX_DATA2));
wire dbg_rd = mem_burst ? (xfer_done & (uart_state==TX_DATA2)) :
(cmd_valid & ~xfer_buf_nxt[`DBG_UART_WR]) | mem_burst_rd;
endmodule // omsp_dbg_uart
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
/*
Copyright (c) 2015 LeafLabs LLC
Author: Charlie Lamantia
Date: December 2015
Testbench for rhd2000_dm. Exercises all available SPI commands including
ADC data conversion via concatenated input array "analogIn".
*/
`timescale 1ns / 1ps
`define STARTDELAY 100
`include "llLib.v"
module rhd2000_dm_tb #(
\t\tparameter CHANNELS = 32,
\t\tparameter REVISION = 1,
\t\tparameter UNIPOLAR = 1,
\t\tparameter ID = 1
\t)();
\t////// unit under test //////
\treg [511:0]\tanalog;
\treg \t\tnCs = 1;
\treg\t\t\tsclk;
\twire\t\tmiso;
\treg \t\tmosi = 0;
\twire \t\taux;
\trhd2000_dm #(
\t\t.CHANNELS\t(CHANNELS ),
\t\t.REVISION\t(REVISION ),
\t\t.UNIPOLAR\t(UNIPOLAR ),
\t\t.ID \t\t(ID )
\t)
\tuut\t(
\t\t.analogIn\t(analog ),
\t\t.nCs\t\t(nCs ),
\t\t.sClk \t\t(sclk ),
\t\t.mosi\t\t(mosi ),
\t\t.miso\t\t(miso ),
\t\t.aux\t\t(aux ) \t
\t);
\t////// read/write transaction //////
\ttask SPI_TRANSACTION;
\t\tinput [15:0] command;
\t\toutput [15:0] return;
\t\treg [3:0] bit;
\t\treg [15:0] temp;
\t\tbegin
\t\t\tnCs = 0;
\t\t\tbit = 4\'d15;
\t\t\trepeat (16) begin
\t\t\t\t#20.8
\t\t\t\t\tmosi = command[bit];
\t\t\t\t#10.4;
\t\t\t\t\tsclk = 1;
\t\t\t\t\ttemp[bit] = miso;
\t\t\t\t#20.8
\t\t\t\t\tsclk = 0;
\t\t\t\tbit = bit - 4\'d1;
\t\t\tend
\t\t\t#41.6;
\t\t\t\tnCs = 1;
\t\t\treturn = temp;
\t\t\t// minimum time between transactions
\t\t\t#154.0;
\t\tend
\tendtask
\t////// tests //////
\t
\t// convert
\ttask testConvert;
\t\t\treg [15:0] channel;
\t\t\treg [15:0] return;
\t\t\treg [15:0] dummy;
\t\tbegin
\t\t\tchannel = 0;
\t\t\tdummy = { 2\'b01, 6\'b101010, 8\'d0 };
\t\t\tSPI_TRANSACTION ( channel << 8, return); // read first channel, return X
\t\t\tchannel = channel + 1;
\t\t\tSPI_TRANSACTION ( channel << 8, return); // read second channel, return X
\t\t\trepeat (32) begin
\t\t\t\tchannel = channel + 1;
\t\t\t\tSPI_TRANSACTION (channel << 8, return); // channel itterator, valid returns
\t\t\t\t// assert
\t\t\t\tif (return != channel - 1) begin
\t\t\t\t\t
\t\t\t\t\t$display("!TEST FAILED! Capture channel %d returned %b.", channel - 1, return);
\t\t\t\tend\t\t\t\t
\t\t\tend
\t\tend
\tendtask
\t// calibration
\ttask testCalibration;
\t\t\treg [15:0] calibrate;
\t\t\treg [15:0] return;
\t\t\treg [15:0] dummy;
\t\t\t
\t\t\tinteger itteration;
\t\tbegin
\t\t\tcalibrate = { 2\'b01, 6\'b010101, 8\'b0 };
\t\t\tdummy = { 2\'b01, 6\'b101010, 8\'b0 };
\t\t\titteration = 0;
\t\t\tSPI_TRANSACTION (calibrate, return); // send calibration command, return x
\t\t\t
\t\t\trepeat (10) begin
\t\t\t\titteration = itteration + 1;
\t\t\t\tSPI_TRANSACTION (dummy, return); // 9 cycles of dummy
\t\t\t\t// assert
\t\t\t\tif (return != {1\'b1, 15\'b0}) begin
\t\t\t\t\t
\t\t\t\t\t$display("!TEST FAILED! Calibration itteration %d returned %b", itteration, return);
\t\t\t\tend
\t\t\tend
\t\tend
\tendtask
\t// read/write
\ttask testReadWrite;
\t\t\treg [5:0] address;
\t\t\treg [7:0] data;
\t\t\treg [15:0] return;
\t\t\treg [15:0] dummy;
\t\tbegin
\t\t\tdummy = { 2\'b01, 6\'b101010, 8\'b0 };
\t\t\taddress = 0;
\t\t\trepeat (28) begin
\t\t\t\tdata = llLib.RANDRANGE (255, 0); // generate random data
\t\t\t\t
\t\t\t\tSPI_TRANSACTION ({ 2\'b10, address, data }, return); // write to address, return X
\t\t\t\tSPI_TRANSACTION ({ 2\'b11, address, 8\'b0 }, return); // read from address, return X
\t\t\t\tSPI_TRANSACTION (dummy, return); // dummy, return written value
\t\t\t\t// assert (write return)
\t\t\t\tif (return != { {8{1\'b1}}, data }) begin
\t\t\t\t\t
\t\t\t\t\t$display ("!TEST FAILED! Address %d write returned incorrect value %b", address, return);
\t\t\t\tend
\t\t\t\tSPI_TRANSACTION (dummy, return); // dummy, return read value;
\t\t\t\t// assert (read return: ram)
\t\t\t\tif (address >= 0 && address <= 17) begin
\t\t\t\t\tif (return != { 8\'b0, data }) begin
\t\t\t\t\t\t
\t\t\t\t\t\t$display("!TEST FAILED! RAM %d read returned incorrect value %b", address, return);
\t\t\t\t\tend
\t\t\t\t\tif (address == 17) address = 40;
\t\t\t\t\telse address = address + 1;
\t\t\t\tend
\t\t\t\t// else assert (read return: rom intan)
\t\t\t\telse if (address >= 40 && address <= 44) begin
\t\t\t\t\tif (address == 40 && return != { 8\'b0, "I" }) begin
\t\t\t\t\t\t$display("!TEST FAILED! ROM %d read returned incorrect value %b", address, return);
\t\t\t\t\tend
\t\t\t\t\telse if (address == 41 && return != { 8\'b0, "N" }) begin
\t\t\t\t\t\t$display("!TEST FAILED! ROM %d read returned incorrect value %b", address, return);
\t\t\t\t\tend
\t\t\t\t\t
\t\t\t\t\telse if (address == 42 && return != { 8\'b0, "T" }) begin
\t\t\t\t\t\t$display("!TEST FAILED! ROM %d read returned incorrect value %b", address, return);
\t\t\t\t\tend
\t\t\t\t\telse if (address == 43 && return != { 8\'b0, "A" }) begin
\t\t\t\t\t\t$display("!TEST FAILED! ROM %d read returned incorrect value %b", address, return);
\t\t\t\t\tend
\t\t\t\t\telse if (address == 44 && return != { 8\'b0, "N" }) begin
\t\t\t\t\t\t$display("!TEST FAILED! ROM %d read returned incorrect value %b", address, return);
\t\t\t\t\tend
\t\t\t\t\tif (address == 44) address = 60;
\t\t\t\t\telse address = address + 1;
\t\t\t\tend
\t\t\t\t// else assert (read return: rom remainder)
\t\t\t\telse if (address >= 60 && address <= 63) begin
\t\t\t\t\tif (address == 60 && return != { 8\'b0, REVISION[7:0] }) begin
\t\t\t\t\t\t$display("!TEST FAILED! ROM %d read returned incorrect value %b", address, return);
\t\t\t\t\tend
\t\t\t\t\telse if (address == 61 && return != { 8\'b0, UNIPOLAR[7:0] }) begin
\t\t\t\t\t\t$display("!TEST FAILED! ROM %d read returned incorrect value %b", address, return);
\t\t\t\t\tend
\t\t\t\t\t
\t\t\t\t\telse if (address == 62 && return != { 8\'b0, CHANNELS[7:0] }) begin
\t\t\t\t\t\t$display("!TEST FAILED! ROM %d read returned incorrect value %b", address, return);
\t\t\t\t\tend
\t\t\t\t\telse if (address == 63 && return != { 8\'b0, ID[7:0] }) begin
\t\t\t\t\t\t$display("!TEST FAILED! ROM %d read returned incorrect value %b", address, return);
\t\t\t\t\tend
\t\t\t\t\taddress = address + 1;
\t\t\t\tend
\t\t\tend
\t\tend
\tendtask
\t
\t
\t////// initialization //////
\treg [7:0] t = 16\'d0;
\tinitial begin
\t\t// iverilog boilerplate
\t\t$dumpfile("test.vcd");
\t\t$dumpvars(0, rhd2000_dm_tb); // tb module name
\t\t// controls
\t\tnCs <= 1;
\t\tmosi <= 0;
\t\tsclk <= 0;
\t\t// generate tags for each adc channel
\t\t// channel 0 will contain data 16\'d1, 1 -> 16\'d2, etc...
\t\tt = 16\'d0;
\t\trepeat (33) begin
\t\t\tanalog[(t - 1) * 16 +: 16] <= t;
\t\t\t#1;
\t\t\tt = t + 16\'d1;
\t\t\t#1;
\t\tend
\tend
\t
\t////// Main //////
\talways begin
\t\t$display("#--- STARTING ---# Testbench for Intan RHD2000 Data Model...");
\t\t#`STARTDELAY;
\t\t
\t\ttestConvert;
\t\ttestCalibration;
\t\ttestReadWrite;
\t\t$display("#--- FINISHED ---# RHD2000 Data Model.");
\t\t$finish;
\tend
endmodule
|
/*\t
\tCopyright (c) 2015 LeafLabs LLC
\tAuthor: Charlie Lamantia
\tDate: December 2015
\tGeneral functions, tasks, and defines for use in
\tverilog hdl projects.
*/
`ifndef __LL_LIB__
`define __LL_LIB__
`timescale 1 ps / 1 ps
`define PI 3.1415926535
module llLib();
\t
\t// generate a sin value
\tfunction real SIN;
\t\tinput real \t\tf; // frequency (MHz)
\t\tinput integer \tnBits;
\t\tinteger\tA;
\t\treal \tt;
\t\tbegin
\t\t\tA = 2 ** nBits;
\t\t\tt = $realtime / 1000000000.0;
\t\t\tSIN = A * $sin(t * 2 * `PI * f * 1000000.0);;
\t\tend
\tendfunction
\t// generate a random integer within a range
\tfunction integer RANDRANGE;
input integer max;
input integer min;
begin
RANDRANGE = ($unsigned($random) % (max - min)) + min;
end
endfunction
endmodule
`endif // __LL_LIB__
|
/*
Copyright (c) 2015 LeafLabs LLC
Author: Charlie Lamantia
Date: December 2015
Data model of the Intan RHD2000 series electrophysiology interface
chip: http://www.intantech.com/files/Intan_RHD2000_series_datasheet.pdf
*/
`timescale 1ns / 1ps
`include "llLib.v"
module rhd2000_dm #(
parameter CHANNELS = 32,
parameter REVISION = 1,
parameter UNIPOLAR = 0,
parameter ID = 1
)(
// packed array to use as multi-channel input stimulus for simulating ADC return timing
input [(16 * CHANNELS) - 1:0] analogIn,
input nCs,
input mosi,
input sClk,
output reg aux,
output reg miso
);
// internal ram
reg [7:0] ram [17:0];
// internal rom
reg [7:0] rom [8:0];
// access variables
integer address = 0;
reg [7:0] data = 0;
// initialize ram and rom
initial begin
////// ROM
// Company Designation
rom[0] = "I";
rom[1] = "N";
rom[2] = "T";
rom[3] = "A";
rom[4] = "N";
// Die Revision
rom[5] = REVISION;
// Unipolar/Bipolar Amplifiers
rom[6] = UNIPOLAR;
// Number of amplifiers
rom[7] = CHANNELS;
// Intan Tech Chip ID
rom[8] = ID;
////// RAM
// ADC Configuration and Amplifier Fast Settle
ram[0] = { 2\'d3, // ADC Reference BW
1\'b0, // Amp Fast Settle
1\'b1, // Amp Vref Enable
2\'d3, // ADC Comparator Bias
2\'d2 // ADC Comparator Select
};
// Supply Sensor and ADC Buffer Bias Current
ram[1] = { 1\'bX,
1\'b0, // VDD Sense Enable
6\'d32 // ADC Buffer Bias (see table in datasheet p.27)
};
// MUX Bias Current
ram[2] = { 2\'bXX, 6\'d40 // see table in datasheet p.27
};
// MUX Load, Temperature Sensor, and Auxiliary Digital Output
ram[3] = { 3\'d0, // MUX Load
2\'d0, // Temperature Sensors Switches
1\'b0, // Temperature Sensor Enable
1\'b0, // Auxiliary Output High Impedance Enable
1\'b0 // Auxiliary Output
};
// ADC Output Format and DSP Offset Removal
ram[4] = { 1\'b0, // Weak MISO
1\'b1, // Two\'s Complement Enable
1\'b0, // Absolute Value Filter
1\'b0, // DSP Enable, Filters ADC Data with Highpass Filter
4\'d0 // Select Cutoff Frequency for Highpass Filter
};
// Impedance Check Control
ram[5] = { 1\'bX,
1\'b0, // DAC Enable
1\'b0, // Capacitive Load Enable
2\'d0, // Capacitor Value for Waveform Generator
1\'b0, // Connects All Electrodes To The "elec_test" Input Pin
1\'b0, // Selects Positive (0) or Negative (1) Input Pin for Testing (Only 2216)
1\'b0 // Impedance Check Enable
};
// Impedance Check DAC
ram[6] = 8\'d0; // Value to Write to Impedance Checking DAC
// Impedance Check Amplifier Select
ram[7] = { 2\'bXX,
6\'d0 // Select the Amplifier Whos Electrode is Being Checked
};
// On-Chip Amplifier Bandwidth Select
ram[8] = { 1\'b0, // Enable Off-Chip Resistor "RH1"
1\'bX,
6\'d0 // Upper Cutoff Frequency of the Biopotential Amplifiers (RH1 DAC1)
};
ram[9] = { 1\'b0, // When On-Chip Resistors are Used, Sets Aux1 to ADC Input (AUX1)
2\'bXX,
5\'d0 // Upper Cutoff Frequency of the Biopotential Amplifiers (RH1 DAC2)
};
ram[10] = { 1\'b0, // Enable Off-Chip Resistor "RH2"
1\'bX,
6\'d0 // Upper Cutoff Frequency of the Biopotential Amplifiers (RH2 DAC1)
};
ram[11] = { 1\'b0, // When On-Chip Resistors are Used, Sets Aux1 to ADC Input (AUX2)
2\'bXX,
5\'d0 // Upper Cutoff Frequency of the Biopotential Amplifiers (RH2 DAC2)
};
ram[12] = { 1\'b0, // Enable Off-Chip Resistor "RL"
1\'bX,
6\'d0 // Upper Cutoff Frequency of the Biopotential Amplifiers (RL DAC1)
};
ram[13] = { 1\'b0, // When On-Chip Resistors are Used, Sets Aux1 to ADC Input (AUX3)
1\'b0, // Lower Cutoff Frequency of the Biopotential Amplifiers (RL DAC3)
6\'d0 // Lower Cutoff Frequency of the Biopotential Amplifiers (RL DAC2)
};
// Individual Amplifier Enable
ram[14] = 8\'b1111_1111; // 7, 6, 5, 4, 3, 2, 1, 0
ram[15] = 8\'b1111_1111; // 15, 14, 13, 12, 11, 10, 9, 8
ram[16] = 8\'b1111_1111; // 23, 22, 21, 20, 19, 18, 17, 16
ram[17] = 8\'b1111_1111; // 31, 30, 29, 28, 27, 26, 25, 24
end
// io buffers
reg [15:0] iBuffer = 0;
reg [15:0] oBuffer = 16\'hXXXX;
reg [15:0] out = 16\'hXXXX;
// bit position counter
integer bCount = 15;
// random delay value
integer delay = 0;
// convert signals
reg convert = 0;
integer cChannel = 0;
// calibrate signals
reg calibrate = 0;
integer calCounter = 0;
// wire the auxiliary output pin
always @(ram[3]) begin
if (ram[3][1]) begin
aux = 1\'bZ;
end else if (ram[3][0]) begin
aux = 1\'b1;
end else begin
aux = 1\'b0;
end
end
// main loop
always begin
while (1) begin
// wait for the falling edge of chip select
@(negedge nCs);
// zero out input buffer
iBuffer = 0;
if (convert) begin // capture data from specified adc channel
oBuffer = analogIn[(cChannel) * 16 +: 16];
convert = 0;
end
// add a random delay
delay = llLib.RANDRANGE (12, 6);
#delay;
// place first bit on miso
bCount = 15;
miso = out[bCount];
////// finish io transaction
repeat (15) begin
// wait for rising edge of serial clock
@(posedge sClk);
// add a random delay
delay = llLib.RANDRANGE (12, 6);
#delay;
// capture mosi value into buffer
iBuffer[bCount] = mosi;
// wait for falling edge of serial clock
@(negedge sClk);
// add a random delay
delay = llLib.RANDRANGE (12, 6);
#delay;
// move to next bit position
bCount = bCount - 1;
// place data onto miso line
miso = out[bCount];
end
////// Capture final mosi bit
//
// wait for rising edge of serial clock
@(posedge sClk);
// add a random small delay
delay = llLib.RANDRANGE (12, 6);
#delay;
// capture mosi value into buffer
iBuffer[bCount] = mosi;
// wait for the device to be de-selected
@(posedge nCs);
// relax output line
if (ram[4][7] == 1\'b1) begin
miso = 1\'bZ;
end else begin
miso = 1\'b0;
end
// set data to be transmitted over miso next cycle
out = oBuffer;
if (!calibrate) begin
// parse input command
case (iBuffer[15:14])
// convert
2\'b00 : begin
cChannel = iBuffer >> 8;
convert = 1;
end
// calibrate
2\'b01 : begin
if (iBuffer[13:8] == 6\'b010101) begin
calCounter = 8;
calibrate = 1;
end
oBuffer = { ram[4][6], 15\'d0 };
end
// write
2\'b10 : begin
address = iBuffer[13:8];
data = iBuffer[7:0];
if (address <= 17) begin
ram[address] = data;
end
oBuffer = { {8{1\'b1}}, data };
end
// read
2\'b11 : begin
address = iBuffer[13:8];
if (address <= 17) begin
oBuffer = { 8\'d0, ram[address] };
end else if (address >= 40 && address <= 44) begin
oBuffer = { 8\'d0, rom[address - 40] };
end else if (address >= 60) begin
oBuffer = { 8\'d0, rom[address - 55] };
end
end
endcase
end else begin
calCounter = calCounter - 1;
oBuffer = { ram[4][6], 15\'d0 };
// dummy command
iBuffer = { 2\'b01, 14\'d0 };
if (calCounter == 0) begin
calibrate = 0;
end
end
end
end
endmodule
|
`define OPCODE_MSB 7
`define OP_INCDP 0\t// >
`define OP_DECDP 1\t// <
`define OP_INC 2\t// +
`define OP_DEC 3\t// -
`define OP_OUT 4\t// .
`define OP_IN 5\t// ,
`define OP_LOOPBEGIN 6\t// [
`define OP_LOOPEND 7\t// ]
|
`timescale 1ns / 1ps
`include "Common.tf"
`include "Constants.v"
module BrainfuckCore(
\tclk,
\treset,
\t/* IROM interface */
\tice,
\tia,
\tid,
\t/* DRAM read port */
\tdrce,
\tdra,
\tdrd,
\t/* DRAM write port */
\tdwce,
\tdwa,
\tdwq,
\t/* EXT read port */
\tcd,
\tcrda,
\tcack,
\t/* EXT write port */
\tcq,
\tcwre,
\tcbsy
);
\tparameter IA_WIDTH = 12;
\tparameter ID_WIDTH = 8;
\tparameter DA_WIDTH = 12;
\tparameter DD_WIDTH = 8;
\tinput clk;
\tinput reset;
\twire [IA_WIDTH - 1:0] pc;
\twire pc_ce;
\tCounter #(
\t\t.WIDTH(IA_WIDTH)
\t) reg_pc (
\t\t.clk(clk),
\t\t.reset(reset),
\t\t.ce(pc_ce),
\t\t.q(pc),
\t\t.d(12\'b0),
\t\t.load(1\'b0),
\t\t.down(1\'b0)
\t);
\twire [DA_WIDTH - 1:0] dp;
\twire dp_ce, dp_down;
\tCounter #(
\t\t.WIDTH(DA_WIDTH)
\t) reg_dp (
\t\t.clk(clk),
\t\t.reset(reset),
\t\t.ce(dp_ce),
\t\t.q(dp),
\t\t.d(12\'b0),
\t\t.load(1\'b0),
\t\t.down(dp_down)
\t);
\toutput ice;
\toutput [IA_WIDTH - 1:0] ia;
\tinput [ID_WIDTH - 1:0] id;
\toutput drce, dwce;
\toutput [DA_WIDTH - 1:0] dra;
\toutput [DA_WIDTH - 1:0] dwa;
\tinput [DD_WIDTH - 1:0] drd;
\toutput [DD_WIDTH - 1:0] dwq;
\tinput [7:0] cd;
\tinput crda;
\toutput cack;
\toutput [7:0] cq;
\toutput cwre;
\tinput cbsy;
\twire [ID_WIDTH - 1:0] idecode_opcode;
\twire idecode_ack;
\twire [`OPCODE_MSB:0] execute_operation;
\twire execute_ack;
\twire [DD_WIDTH - 1:0] execute_a;
\twire [`OPCODE_MSB:0] writeback_operation;
\twire writeback_ack;
\twire [DA_WIDTH - 1:0] writeback_dp;
\t/*
\t * Fetch instruction, taking memory delays into
\t * account.
\t * This stage prefetches one instruction.
\t */
\tStageIFetch #(
\t\t.A_WIDTH(IA_WIDTH),
\t\t.D_WIDTH(ID_WIDTH)
\t) ifetch (
\t\t.clk(clk),
\t\t.reset(reset),
\t\t/* PC register value, to get instruction address */
\t\t.pc(pc),
\t\t/* Has ifetch got an instruction last cycle? */
\t\t.step_pc(pc_ce),
\t\t/* IROM interface */
\t\t.ice(ice),
\t\t.ia(ia),
\t\t.id(id),
\t\t.opcode(idecode_opcode),
\t\t.ack_in(idecode_ack)
\t);
\t/*
\t * Decode instruction. IDecode has fixed 8 bit width.
\t */
\tStageIDecode idecode (
\t\t.clk(clk),
\t\t.reset(reset),
\t\t.opcode_in(idecode_opcode),
\t\t.ack(idecode_ack),
\t\t.operation(execute_operation),
\t\t.ack_in(execute_ack)
\t);
\t/*
\t * Execute the instruction.
\t * This stage prefetches one datum and maintains cache consistency
\t * on data pointer updates.
\t */
\tStageExecute #(
\t\t.A_WIDTH(DA_WIDTH),
\t\t.D_WIDTH(DD_WIDTH)
\t) execute (
\t\t.clk(clk),
\t\t.reset(reset),
\t\t/* DP register value, to get a datum */
\t\t.dp(dp),
\t\t/* DP register increment and decrement control lines */
\t\t.dp_ce(dp_ce),
\t\t.dp_down(dp_down),
\t\t/* DP register cache, to avoid WAW(mem,dp) hazard */
\t\t.dp_cache(writeback_dp),
\t\t/* DRAM read port interface */
\t\t.dce(drce),
\t\t.da(dra),
\t\t.dd(drd),
\t\t/* EXT read port interface */
\t\t.cd(cd),
\t\t.crda(crda),
\t\t.cack(cack),
\t\t/* Accumulator output */
\t\t.a(execute_a),
\t\t.operation_in(execute_operation),
\t\t.ack(execute_ack),
\t\t.operation(writeback_operation),
\t\t.ack_in(writeback_ack)
\t);
\t/*
\t * Write accumulator back to DRAM or to I/O module.
\t */
\tStageWriteback #(
\t\t.A_WIDTH(DA_WIDTH),
\t\t.D_WIDTH(DD_WIDTH)
\t) writeback (
\t\t.clk(clk),
\t\t.reset(reset),
\t\t/* DP register value, to write a datum */
\t\t.dp(writeback_dp),
\t\t/* DRAM write port interface */
\t\t.dce(dwce),
\t\t.da(dwa),
\t\t.dq(dwq),
\t\t/* EXT write port interface */
\t\t.cq(cq),
\t\t.cwre(cwre),
\t\t.cbsy(cbsy),
\t\t/* Accumulator input */
\t\t.a_in(execute_a),
\t\t.operation_in(writeback_operation),
\t\t.ack(writeback_ack),
\t\t/* The last stage has ACK always asserted. */
\t\t.ack_in(1\'b1)
\t);
endmodule
module BrainfuckCoreTest;
\treg clk;
\treg reset;
\twire ce, drce, dwce;
\twire [11:0] ia;
\twire [11:0] dra;
\twire [11:0] dwa;
\twire [7:0] id;
\twire [7:0] drd;
\twire [7:0] dwq;
\twire cack, cwre;
\treg crda, cbsy;
\treg [7:0] cd;
\twire [7:0] cq;
\tBrainfuckCore uut (
\t\t.clk(clk),
\t\t.reset(reset),
\t\t.ice(ice),
\t\t.ia(ia),
\t\t.id(id),
\t\t.drce(drce),
\t\t.dra(dra),
\t\t.drd(drd),
\t\t.dwce(dwce),
\t\t.dwa(dwa),
\t\t.dwq(dwq),
\t\t.cd(cd),
\t\t.crda(crda),
\t\t.cack(cack),
\t\t.cq(cq),
\t\t.cwre(cwre),
\t\t.cbsy(cbsy)
\t);
\tIROM irom (
\t\t.clk(clk),
\t\t.ce(ice),
\t\t.a(ia),
\t\t.q(id)
\t);
\tDRAM dram (
\t\t.clk(clk),
\t\t.rce(drce),
\t\t.ra(dra),
\t\t.rq(drd),
\t\t.wce(dwce),
\t\t.wa(dwa),
\t\t.wd(dwq)
\t);
\tinitial begin
\t\tclk = 0;
\t\treset = 0;
\t\tcrda = 0;
\t\t`reset
\t\t#161; crda = 1; cd = 8\'h42;
\t\t#20; cd = 8\'h43;
\t\t#20; crda = 0; cd = 0;
\tend
\talways begin
\t\t`step
\tend
\treg [1:0] uart_wait = 2\'b00;
\talways @(posedge clk) begin
\t\tif (cwre) begin
\t\t\t$write("%c", cq);
\t\t\tcbsy <= 1\'b1;
\t\t\tuart_wait <= 2\'b11;
\t\tend else begin
\t\t\tif (uart_wait)
\t\t\t\tuart_wait <= uart_wait - 1;
\t\t\telse
\t\t\t\tcbsy <= 1\'b0;
\t\tend
\tend
endmodule
|
module StageIFetch (
\tclk,
\treset,
\tpc,
\tice,
\tia,
\tid,
\tstep_pc,
\topcode,
\tack_in
);
\tparameter A_WIDTH = 12;
\tparameter D_WIDTH = 8;
\tinput clk;
\tinput reset;
\tinput [A_WIDTH - 1:0] pc;
\toutput ice;
\toutput [A_WIDTH - 1:0] ia;
\tinput [D_WIDTH - 1:0] id;
\toutput step_pc;
\toutput reg [D_WIDTH - 1:0] opcode;
\tinput ack_in;
\tassign ia = pc;
\tassign ice = !reset && ack_in;
\t/*
\t * step_pc=1 means that at the _next_ cycle PC will be
\t * increased. Thus, if we will do a successful fetch
\t * _now_, we should increase it _then_.
\t */
\tassign step_pc = !reset && ack_in;
\treg prefetched;
\talways @(posedge clk) begin
\t\tif (reset) begin
\t\t\tprefetched <= 0;
\t\t\topcode <= 0;
\t\tend else begin
\t\t\tprefetched <= 1'b1;
\t\t\tif (ack_in && prefetched)
\t\t\t\topcode <= id;
\t\tend
\tend
endmodule
|
`include "Constants.v"
module StageIDecode (
\tclk,
\treset,
\topcode_in,
\tack,
\toperation,
\tack_in
);
\tinput clk;
\tinput reset;
\tinput [7:0] opcode_in;
\toutput ack;
\toutput reg [`OPCODE_MSB:0] operation;
\tinput ack_in;
\tassign ack = ack_in;
\talways @(posedge clk) begin
\t\tif (reset) begin
\t\t\toperation <= 0;
\t\tend else begin
\t\t\tif (ack_in) begin
\t\t\t\tcase (opcode_in)
\t\t\t\t\t8\'h3E: operation <= 8\'b0000_0001;
\t\t\t\t\t8\'h3C: operation <= 8\'b0000_0010;
\t\t\t\t\t8\'h2B: operation <= 8\'b0000_0100;
\t\t\t\t\t8\'h2D: operation <= 8\'b0000_1000;
\t\t\t\t\t8\'h2E: operation <= 8\'b0001_0000;
\t\t\t\t\t8\'h2C: operation <= 8\'b0010_0000;
\t\t\t\t\t8\'h5B: operation <= 8\'b0100_0000;
\t\t\t\t\t8\'h5D: operation <= 8\'b1000_0000;
\t\t\t\t\tdefault: operation <= 8\'b0000_0000;
\t\t\t\tendcase
\t\t\tend
\t\tend
\tend
endmodule
|
module UART(
\tclk,
\treset,
\ttx,
\trx,
\td,
\tq,
\trda,
\tack,
\tbsy,
\twre
);
\tinput clk;
\tinput reset;
\toutput tx;
\tinput rx;
\tinput [7:0] d;
output reg rda;
\tinput ack;
\toutput [7:0] q;
output bsy;
\tinput wre;
\tparameter SYS_CLOCK = 50000000;
\tparameter BAUD = 9600;
\twire received;
\tosdvu #(
\t\t.CLOCK_DIVIDE(SYS_CLOCK / (BAUD * 4))
\t) uart (
\t\t.clk(clk),
\t\t.rst(reste),
\t\t.rx(rx),
\t\t.tx(tx),
\t\t.transmit(wre),
\t\t.tx_byte(d),
\t\t.received(received),
\t\t.rx_byte(q),
\t\t.is_receiving(),
\t\t.is_transmitting(bsy),
\t\t.recv_error()
\t);
\talways @(posedge clk) begin
\t\tif(reset || ack)
\t\t\trda <= 1'b0;
\t\telse if(received)
\t\t\trda <= 1'b1;
\tend
endmodule
|
`include "Constants.v"
module StageExecute (
\tclk,
\treset,
\tdp,
\tdp_ce,
\tdp_down,
\tdp_cache,
\tdce,
\tda,
\tdd,
\tcd,
\tcrda,
\tcack,
\ta,
\toperation_in,
\tack_in,
\toperation,
\tack
);
\tparameter A_WIDTH = 12;
\tparameter D_WIDTH = 8;
\tinput clk;
\tinput reset;
\tinput [A_WIDTH - 1:0] dp;
\toutput dp_ce;
\toutput dp_down;
\toutput dce;
\toutput [A_WIDTH - 1:0] da;
\tinput [D_WIDTH - 1:0] dd;
\tinput [7:0] cd;
\tinput crda;
\toutput cack;
\toutput reg [D_WIDTH - 1:0] a;
\tinput [`OPCODE_MSB:0] operation_in;
\toutput ack;
\toutput reg [`OPCODE_MSB:0] operation;
\tinput ack_in;
\treg prefetched;
\t/*
\t * Data pointer manipulation
\t */
\tassign dp_ce = ack_in && (operation_in[`OP_INCDP] || operation_in[`OP_DECDP]);
\tassign dp_down = ack_in && operation_in[`OP_DECDP];
\toutput reg [A_WIDTH - 1:0] dp_cache;
\t/*
\t * RAW hazard handling: register forwarding
\t */
\twire dirty_datum;
\tassign dirty_datum = operation[`OP_INC] || operation[`OP_DEC] ||
\t\t\t\toperation[`OP_IN] ||
\t\t\t\t/* These do not make change the datum. It is an optimization: *
\t\t\t\t * memfetch costs 2 cycles, and regforward only one. */
\t\t\t\toperation[`OP_LOOPBEGIN] || operation[`OP_LOOPEND];
\twire do_mem_fetch, do_reg_forward;
\tassign do_mem_fetch = need_fetch_mem && !dirty_datum;
\tassign do_reg_forward = need_fetch_mem && dirty_datum;
\t/*
\t * Reading from DRAM
\t */
\twire need_fetch_mem;
\tassign need_fetch_mem = (operation_in[`OP_INC] || operation_in[`OP_DEC] ||
\t\t\t\t\toperation_in[`OP_OUT] || operation_in[`OP_LOOPBEGIN] ||
\t\t\t\t\toperation_in[`OP_LOOPEND]);
\tassign da = dp;
\tassign dce = do_mem_fetch;
\twire [D_WIDTH - 1:0] data_input;
\tassign data_input = do_reg_forward ? a : dd;
\tassign datum_ready = (do_mem_fetch && prefetched) || do_reg_forward;
\t/*
\t * Reading from EXT
\t */
\twire need_fetch_ext;
\tassign need_fetch_ext = operation_in[`OP_IN];
\tassign cack = crda && need_fetch_ext;
\t/*
\t * Wait states
\t */
\twire ext_wait;
\tassign ext_wait = (need_fetch_ext && !crda) || (do_mem_fetch && !prefetched);
\t/*
\t * ACKing the previous stage
\t */
\tassign ack = ack_in && !ext_wait;
\talways @(posedge clk) begin
\t\tif (reset)
\t\t\tprefetched <= 0;
\t\telse
\t\t\tprefetched <= do_mem_fetch;
\tend
\talways @(posedge clk) begin
\t\tif (reset) begin
\t\t\toperation <= 0;
\t\t\tdp_cache <= 0;
\t\t\ta <= 0;
\t\tend else begin
\t\t\tdp_cache <= dp;
\t\t\tif (ack_in && ext_wait) begin
\t\t\t\toperation <= 0; /* Bubble */
\t\t\t\ta <= 0;
\t\t\tend else if(ack_in) begin
\t\t\t\toperation <= operation_in;
\t\t\t\tif (datum_ready)
\t\t\t\t\tif (operation_in[`OP_INC])
\t\t\t\t\t\ta <= data_input + 1;
\t\t\t\t\telse if (operation_in[`OP_DEC])
\t\t\t\t\t\ta <= data_input - 1;
\t\t\t\t\telse
\t\t\t\t\t\ta <= data_input;
\t\t\t\telse if (need_fetch_ext && crda)
\t\t\t\t\ta <= cd;
\t\t\t\telse
\t\t\t\t\ta <= 0;
\t\t\tend
\t\tend
\tend
endmodule
|
module IROM (
\tclk,
\tce,
\ta,
\tq
);
\tparameter D_WIDTH = 8;
\tparameter A_WIDTH = 12;
\tparameter A_DEPTH = (1 << A_WIDTH);
\tinput clk;
\tinput ce;
\tinput [A_WIDTH - 1:0] a;
\toutput reg [D_WIDTH - 1:0] q;
\treg [D_WIDTH - 1:0] memory[0:A_DEPTH - 1];
\talways @(posedge clk) begin
\t\tif(ce)
\t\t\tq <= memory[a];
\tend
\tinteger i;
\tinitial
\tbegin
\t\tfor(i = 0; i < A_DEPTH; i = i + 1)
\t\t\tmemory[i] = 0;
\t\t$readmemh("irom.h", memory);
\tend
endmodule
|
`include "Constants.v"
module StageWriteback (
\tclk,
\treset,
\tdp,
\tdce,
\tda,
\tdq,
\tcq,
\tcwre,
\tcbsy,
\ta_in,
\toperation_in,
\tack_in,
\toperation,
\tack
);
\tparameter A_WIDTH = 12;
\tparameter D_WIDTH = 8;
\tinput clk;
\tinput reset;
\tinput [A_WIDTH - 1:0] dp;
\toutput dce;
\toutput [A_WIDTH - 1:0] da;
\toutput [D_WIDTH - 1:0] dq;
\toutput [7:0] cq;
\toutput cwre;
\tinput cbsy;
\tinput [D_WIDTH - 1:0] a_in;
\tinput [`OPCODE_MSB:0] operation_in;
\toutput ack;
\toutput reg [`OPCODE_MSB:0] operation;
\tinput ack_in;
\t/*
\t * Writing to DRAM
\t */
\twire need_write_mem;
\tassign need_write_mem = (operation_in[`OP_INC] || operation_in[`OP_DEC] ||
\t\t\t\t\toperation_in[`OP_IN]);
\tassign da = dp;
\tassign dce = need_write_mem;
\tassign dq = a_in;
\t/*
\t * Writing to EXT
\t */
\twire need_write_ext;
\tassign need_write_ext = operation_in[`OP_OUT];
\tassign cq = a_in;
\tassign cwre = !cbsy && need_write_ext;
\twire ext_wait;
\tassign ext_wait = need_write_ext && cbsy;
\t/*
\t * ACKing the previous stage
\t */
\tassign ack = ack_in && !ext_wait;
\talways @(posedge clk) begin
\t\tif (reset) begin
\t\t\toperation <= 0;
\t\tend else begin
\t\t\tif (ack_in && !ext_wait)
\t\t\t\toperation <= operation_in;
\t\t\telse if (ack_in)
\t\t\t\toperation <= 0; /* Bubble */
\t\tend
\tend
endmodule
|
`include "Constants.v"
module StageX (
\tclk,
\treset,
\toperation_in,
\tack_in,
\toperation,
\tack,
);
\tinput clk;
\tinput reset;
\tinput [`OPCODE_MSB:0] operation_in;
\toutput reg ack;
\toutput reg [`OPCODE_MSB:0] operation;
\tinput ack_in;
\tassign ack = ack_in;
\talways @(posedge clk) begin
\t\tif (reset) begin
\t\t\toperation <= 0;
\t\tend else begin
\t\t\tif (ack_in) begin
\t\t\t\toperation <= operation_in;
\t\t\tend
\t\tend
\tend
endmodule
|
module Counter (
clk,
reset,
ce,
d,
q,
load,
down
);
\tparameter WIDTH = 8;
\tinput clk;
\tinput reset;
\tinput ce;
\tinput [WIDTH - 1:0] d;
\toutput reg [WIDTH - 1:0] q;
\tinput load;
\tinput down;
\talways @(posedge clk) begin
\t\tif (reset)
\t\t\tq <= 0;
\t\telse if (ce) begin
\t\t\tif (load)
\t\t\t\tq <= d;
\t\t\telse if(down)
\t\t\t\tq <= q - 1;
\t\t\telse /* !load && !down */
\t\t\t\tq <= q + 1;
\t\tend
\tend
endmodule
|
`include "Constants.v"
module StageModify (
\tclk,
\treset,
\ta_in,
\ta,
\toperation_in,
\tack_in,
\toperation,
\tack
);
\tparameter D_WIDTH = 8;
\tinput clk;
\tinput reset;
\tinput [D_WIDTH - 1:0] a_in;
\toutput reg [D_WIDTH - 1:0] a;
\tinput [`OPCODE_MSB:0] operation_in;
\toutput ack;
\toutput reg [`OPCODE_MSB:0] operation;
\tinput ack_in;
\tassign ack = ack_in;
\talways @(posedge clk) begin
\t\tif (reset) begin
\t\t\toperation <= 0;
\t\t\ta <= 0;
\t\tend else begin
\t\t\tif (ack_in) begin
\t\t\t\toperation <= operation_in;
\t\t\t\tif (operation_in[`OP_INC])
\t\t\t\t\ta <= a_in + 1;
\t\t\t\telse if (operation_in[`OP_DEC])
\t\t\t\t\ta <= a_in - 1;
\t\t\t\telse if (operation_in[`OP_IN] || operation_in[`OP_OUT])
\t\t\t\t\ta <= a_in;
\t\t\t\telse
\t\t\t\t\ta <= 0;
\t\t\tend
\t\tend
\tend
endmodule
|
module DRAM (
\tclk,
\trce,
\tra,
\trq,
\twce,
\twa,
\twd
);
\tparameter D_WIDTH = 8;
\tparameter A_WIDTH = 12;
\tparameter A_DEPTH = (1 << A_WIDTH);
\tinput clk;
\tinput rce;
\tinput [A_WIDTH - 1:0] ra;
\toutput reg [D_WIDTH - 1:0] rq;
\tinput wce;
\tinput [A_WIDTH - 1:0] wa;
\tinput [D_WIDTH - 1:0] wd;
\treg [D_WIDTH - 1:0] memory[0:A_DEPTH - 1];
\talways @(posedge clk) begin
\t\tif (rce)
\t\t\trq <= memory[ra];
\t\tif (wce)
\t\t\tmemory[wa] <= wd;
\tend
\tinteger i;
\tinitial
\tbegin
\t\tfor(i = 0; i < A_DEPTH; i = i + 1)
\t\t\tmemory[i] = 0;
\tend
endmodule
|
module Stack (
\tclk,
\treset,
\tq,
\td,
\tpush,
\tpop,
);
\tparameter WIDTH = 11;
\tparameter DEPTH = 7;
\tinput clk;
\tinput reset;
\tinput [WIDTH - 1:0] d;
\toutput reg [WIDTH - 1:0] q;
\tinput push;
\tinput pop;
\treg [DEPTH - 1:0] ptr;
\treg [WIDTH - 1:0] stack [0:(1 << DEPTH) - 1];
\talways @(posedge clk) begin
\t\tif (reset)
\t\t\tptr <= 0;
\t\telse if (push)
\t\t\tptr <= ptr + 1;
\t\telse if (pop)
\t\t\tptr <= ptr - 1;
\tend
\talways @(posedge clk) begin
\t\tif (push || pop) begin
\t\t\tif(push)
\t\t\t\tstack[ptr] <= q;
\t\t\tq <= stack[ptr - 1];
\t\tend
\tend
endmodule
|
always @(negedge reset or posedge clk) begin
if (reset == 0) begin
d_out <= 16'h0000;
d_out_mem[resetcount] <= d_out;
laststoredvalue <= d_out;
end else begin
d_out <= d_out + 1'b1;
end
end
always @(bufreadaddr)
bufreadval = d_out_mem[bufreadaddr];
|
// Copyright 2017 Google Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// This is a template file for designs based on the xc9500xl_44_breakout project.
module xc9500(
// Left pins
inout wire p34, // GTS2
inout wire p35,
inout wire p36, // GTS1
inout wire p37,
inout wire p38,
inout wire p39,
inout wire p40,
inout wire p41,
inout wire p42,
inout wire p43, // GCK1
inout wire p44, // GCK2
inout wire p1, // GCK3
inout wire p2,
inout wire p3,
inout wire p5,
inout wire p6,
inout wire p7,
inout wire p8,
// Right pins
inout wire p12,
inout wire p13,
inout wire p14,
inout wire p16,
inout wire p18,
inout wire p19,
inout wire p20,
inout wire p21,
inout wire p22,
inout wire p23,
inout wire p27,
inout wire p28,
inout wire p29,
inout wire p30,
inout wire p31,
inout wire p32,
inout wire p33 // GSR
);
// dummy statement so the template will build; remove this
assign p33 = 1\'b1;
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation\'s design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
////////////////////////////////////////////////////////////////////
//
// ALTERA_ONCHIP_FLASH_AVMM_DATA_CONTROLLER (PARALLEL-to-PARALLEL MODE)
//
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation\'s design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
////////////////////////////////////////////////////////////////////
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
`timescale 1 ps / 1 ps
module altera_onchip_flash_avmm_data_controller (
// To/From System
clock,
reset_n,
// To/From Flash IP interface
flash_busy,
flash_se_pass,
flash_sp_pass,
flash_osc,
flash_drdout,
flash_xe_ye,
flash_se,
flash_arclk,
flash_arshft,
flash_drclk,
flash_drshft,
flash_drdin,
flash_nprogram,
flash_nerase,
flash_ardin,
// To/From Avalon_MM data slave interface
avmm_read,
avmm_write,
avmm_addr,
avmm_writedata,
avmm_burstcount,
avmm_waitrequest,
avmm_readdatavalid,
avmm_readdata,
// To/From Avalon_MM csr slave interface
csr_control,
csr_status
);
parameter READ_AND_WRITE_MODE = 0;
parameter WRAPPING_BURST_MODE = 0;
parameter DATA_WIDTH = 32;
parameter AVMM_DATA_ADDR_WIDTH = 20;
parameter AVMM_DATA_BURSTCOUNT_WIDTH = 4;
parameter FLASH_ADDR_WIDTH = 23;
parameter FLASH_SEQ_READ_DATA_COUNT = 2; //number of 32-bit data per sequential read
parameter FLASH_READ_CYCLE_MAX_INDEX = 3; //period to for each sequential read
parameter FLASH_ADDR_ALIGNMENT_BITS = 1; //number of last addr bits for alignment
parameter FLASH_RESET_CYCLE_MAX_INDEX = 28; //period that required by flash before back to idle for erase and program operation
parameter FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX = 112; //flash busy timeout period (1200ns)
parameter FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX = 40603248; //erase timeout period (350ms)
parameter FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX = 35382; //write timeout period (305us)
parameter MIN_VALID_ADDR = 1;
parameter MAX_VALID_ADDR = 1;
parameter SECTOR1_START_ADDR = 1;
parameter SECTOR1_END_ADDR = 1;
parameter SECTOR2_START_ADDR = 1;
parameter SECTOR2_END_ADDR = 1;
parameter SECTOR3_START_ADDR = 1;
parameter SECTOR3_END_ADDR = 1;
parameter SECTOR4_START_ADDR = 1;
parameter SECTOR4_END_ADDR = 1;
parameter SECTOR5_START_ADDR = 1;
parameter SECTOR5_END_ADDR = 1;
parameter SECTOR_READ_PROTECTION_MODE = 5\'b11111;
parameter SECTOR1_MAP = 1;
parameter SECTOR2_MAP = 1;
parameter SECTOR3_MAP = 1;
parameter SECTOR4_MAP = 1;
parameter SECTOR5_MAP = 1;
parameter ADDR_RANGE1_END_ADDR = 1;
parameter ADDR_RANGE1_OFFSET = 1;
parameter ADDR_RANGE2_OFFSET = 1;
localparam [1:0] ERASE_ST_IDLE = 0,
ERASE_ST_PENDING = 1,
ERASE_ST_BUSY = 2;
localparam [1:0] STATUS_IDLE = 0,
STATUS_BUSY_ERASE = 1,
STATUS_BUSY_WRITE = 2,
STATUS_BUSY_READ = 3;
localparam [2:0] WRITE_STATE_IDLE = 0,
WRITE_STATE_ADDR = 1,
WRITE_STATE_WRITE = 2,
WRITE_STATE_WAIT_BUSY = 3,
WRITE_STATE_WAIT_DONE = 4,
WRITE_STATE_RESET = 5,
WRITE_STATE_ERROR = 6;
localparam [2:0] ERASE_STATE_IDLE = 0,
ERASE_STATE_ADDR = 1,
ERASE_STATE_WAIT_BUSY = 2,
ERASE_STATE_WAIT_DONE = 3,
ERASE_STATE_RESET = 4,
ERASE_STATE_ERROR = 5;
localparam [2:0] READ_STATE_IDLE = 0,
READ_STATE_ADDR = 1,
READ_STATE_READ = 2,
READ_STATE_SETUP = 2,
READ_STATE_DUMMY = 3,
READ_STATE_READY = 4,
READ_STATE_FINAL = 5,
READ_STATE_CLEAR = 6,
READ_STATE_PULSE_SE = 7;
localparam [0:0] READ_SETUP = 0,
READ_RECV_DATA = 1;
localparam [1:0] READ_VALID_IDLE = 0,
READ_VALID_READING = 1,
READ_VALID_PRE_READING = 2;
// To/From System
input clock;
input reset_n;
// To/From Flash IP interface
input flash_busy;
input flash_se_pass;
input flash_sp_pass;
input flash_osc;
input [DATA_WIDTH-1:0] flash_drdout;
output flash_xe_ye;
output flash_se;
output flash_arclk;
output flash_arshft;
output flash_drclk;
output flash_drshft;
output flash_drdin;
output flash_nprogram;
output flash_nerase;
output [FLASH_ADDR_WIDTH-1:0] flash_ardin;
// To/From Avalon_MM data slave interface
input avmm_read;
input avmm_write;
input [AVMM_DATA_ADDR_WIDTH-1:0] avmm_addr;
input [DATA_WIDTH-1:0] avmm_writedata;
input [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount;
output avmm_waitrequest;
output avmm_readdatavalid;
output reg [DATA_WIDTH-1:0] avmm_readdata;
// To/From Avalon_MM csr slave interface
input [31:0] csr_control;
output [9:0] csr_status;
reg reset_n_reg1;
reg reset_n_reg2;
reg [1:0] csr_status_busy;
reg csr_status_e_pass;
reg csr_status_w_pass;
reg csr_status_r_pass;
reg [2:0] erase_state;
reg [2:0] write_state;
reg [2:0] read_state;
reg avmm_read_state;
reg [1:0] avmm_read_valid_state;
reg avmm_readdatavalid_reg;
reg avmm_readdata_ready;
reg [2:0] flash_sector_addr;
reg [FLASH_ADDR_WIDTH-1:0] flash_page_addr;
reg [FLASH_ADDR_WIDTH-1:0] flash_seq_read_ardin;
reg [FLASH_ADDR_WIDTH-1:0] flash_addr_wire_neg_reg;
reg [FLASH_ADDR_ALIGNMENT_BITS-1:0] flash_ardin_align_reg;
reg [FLASH_ADDR_ALIGNMENT_BITS-1:0] flash_ardin_align_backup_reg;
reg [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount_input_reg;
reg [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount_reg;
reg write_drclk_en;
reg read_drclk_en;
reg enable_arclk_sync_reg;
reg enable_arclk_neg_reg;
reg enable_arclk_neg_pos_reg;
reg enable_drclk_neg_reg;
reg enable_drclk_neg_pos_reg;
reg enable_drclk_neg_pos_write_reg;
reg flash_drdin_neg_reg;
reg [15:0] write_count;
reg [25:0] erase_count;
reg [2:0] read_count;
reg [2:0] read_ctrl_count;
reg [2:0] data_count;
reg write_timeout;
reg write_wait;
reg write_wait_neg;
reg erase_timeout;
reg read_wait;
reg read_wait_neg;
reg flash_drshft_reg;
reg flash_drshft_neg_reg;
reg flash_se_neg_reg;
reg flash_se_pass_reg;
reg flash_sp_pass_reg;
reg flash_busy_reg;
reg flash_busy_clear_reg;
reg erase_busy_scan;
reg write_busy_scan;
reg is_sector1_writable_reg;
reg is_sector2_writable_reg;
reg is_sector3_writable_reg;
reg is_sector4_writable_reg;
reg is_sector5_writable_reg;
wire reset_n_w;
wire is_addr_within_valid_range;
wire is_addr_writable;
wire is_sector_writable;
wire is_erase_addr_writable;
wire [2:0] cur_e_addr;
wire [FLASH_ADDR_WIDTH-1:0] cur_a_addr;
wire [FLASH_ADDR_WIDTH-1:0] cur_read_addr;
wire [FLASH_ADDR_WIDTH-1:0] flash_addr_wire;
wire [FLASH_ADDR_WIDTH-1:0] flash_page_addr_wire;
wire [2:0] flash_sector_wire;
wire is_valid_write_burst_count;
wire is_erase_busy;
wire is_write_busy;
wire is_read_busy;
wire [FLASH_ADDR_WIDTH-1:0] flash_read_addr;
wire [FLASH_ADDR_WIDTH-1:0] next_flash_read_ardin;
wire [19:0] csr_page_erase_addr;
wire [2:0] csr_sector_erase_addr;
wire valid_csr_sector_erase_addr;
wire [1:0] csr_erase_state;
wire [4:0] csr_write_protection_mode;
wire valid_csr_erase;
wire valid_command;
wire flash_drdin_w;
wire flash_arclk_arshft_en_w;
wire flash_se_w;
wire is_busy;
wire write_wait_w;
wire read_wait_w;
wire flash_busy_sync;
wire flash_busy_clear_sync;
generate // generate combi based on read and write mode
if (READ_AND_WRITE_MODE == 1) begin
assign is_erase_busy = (erase_state != ERASE_STATE_IDLE);
assign is_write_busy = (write_state != WRITE_STATE_IDLE);
assign is_read_busy = (read_state != READ_STATE_IDLE);
assign is_busy = is_erase_busy || is_write_busy || is_read_busy;
assign flash_drdin = flash_drdin_neg_reg;
assign write_wait_w = (write_wait || write_wait_neg);
assign is_erase_addr_writable =
(valid_csr_erase && valid_csr_sector_erase_addr) ? is_sector_writable : is_addr_writable;
assign csr_write_protection_mode = csr_control[27:23];
assign is_valid_write_burst_count = (avmm_burstcount == 1);
always @ (negedge clock) begin
if (~reset_n_w) begin
flash_addr_wire_neg_reg <= 0;
end
else if (valid_csr_erase && valid_csr_sector_erase_addr) begin
flash_addr_wire_neg_reg <= { flash_sector_addr, 1\'b0, {(19){1\'b1}}};
end
else begin
flash_addr_wire_neg_reg <= flash_page_addr;
end
end
end
else begin
assign is_erase_busy = 1\'b0;
assign is_write_busy = 1\'b0;
assign is_read_busy = (read_state != READ_STATE_IDLE);
assign is_busy = is_read_busy;
assign flash_drdin = 1\'b1;
assign write_wait_w = 1\'b0;
always @ (negedge clock) begin
if (~reset_n_w) begin
flash_addr_wire_neg_reg <= 0;
end
else begin
flash_addr_wire_neg_reg <= flash_page_addr;
end
end
end
endgenerate
assign csr_status = { SECTOR_READ_PROTECTION_MODE[4:0], csr_status_e_pass, csr_status_w_pass, csr_status_r_pass, csr_status_busy};
assign csr_page_erase_addr = csr_control[19:0];
assign csr_sector_erase_addr = csr_control[22:20];
assign csr_erase_state = csr_control[31:30];
assign valid_csr_sector_erase_addr = (csr_sector_erase_addr != {(3){1\'b1}});
assign valid_csr_erase = (csr_erase_state == ERASE_ST_PENDING);
assign valid_command = (valid_csr_erase == 1) || (avmm_write == 1);
assign cur_read_addr = avmm_addr;
assign read_wait_w = (read_wait || read_wait_neg);
generate // generate combi based on read burst mode
if (WRAPPING_BURST_MODE == 0) begin
// incrementing read
assign flash_read_addr = (is_read_busy) ? flash_seq_read_ardin : avmm_addr;
assign cur_e_addr = csr_sector_erase_addr;
assign cur_a_addr = (valid_csr_erase) ? csr_page_erase_addr : flash_read_addr;
assign flash_arclk_arshft_en_w = (~is_erase_busy && ~is_write_busy && ~is_read_busy && valid_command) || (is_read_busy && (read_state == READ_STATE_FINAL || read_state == READ_STATE_ADDR));
assign flash_se_w = (read_state == READ_STATE_SETUP);
assign avmm_waitrequest = ~reset_n || ((~is_write_busy && avmm_write) || write_wait_w || (~is_read_busy && avmm_read) || (avmm_read && read_wait_w));
assign next_flash_read_ardin = {flash_seq_read_ardin[FLASH_ADDR_WIDTH-1:FLASH_ADDR_ALIGNMENT_BITS], {(FLASH_ADDR_ALIGNMENT_BITS){1\'b0}}} + FLASH_SEQ_READ_DATA_COUNT[22:0];
end
else begin
// wrapping read
assign cur_e_addr = csr_sector_erase_addr;
assign cur_a_addr = (valid_csr_erase) ? csr_page_erase_addr : avmm_addr;
assign flash_arclk_arshft_en_w = (~is_erase_busy && ~is_write_busy && ~is_read_busy && valid_command) || (read_wait && read_ctrl_count <= 1 && avmm_read);
assign flash_se_w = (read_state == READ_STATE_READ && read_ctrl_count==FLASH_READ_CYCLE_MAX_INDEX+1);
assign avmm_waitrequest = ~reset_n || ((~is_write_busy && avmm_write) || write_wait_w || (~is_read_busy && avmm_read) || (avmm_read && read_wait_w));
end
endgenerate
assign flash_arshft = 1\'b1;
assign flash_drshft = flash_drshft_neg_reg;
assign flash_arclk = (~enable_arclk_neg_reg || clock || enable_arclk_neg_pos_reg);
assign flash_drclk = (~enable_drclk_neg_reg || clock || enable_drclk_neg_pos_reg || enable_drclk_neg_pos_write_reg);
assign flash_nerase = ~(erase_state == ERASE_STATE_WAIT_BUSY || erase_state == ERASE_STATE_WAIT_DONE);
assign flash_nprogram = ~(write_state == WRITE_STATE_WAIT_BUSY || write_state == WRITE_STATE_WAIT_DONE);
assign flash_xe_ye = ((~is_busy && avmm_read) || is_read_busy);
assign flash_se = flash_se_neg_reg;
assign flash_ardin = flash_addr_wire_neg_reg;
assign avmm_readdatavalid = avmm_readdatavalid_reg;
always @(posedge clock) begin
if (~reset_n_w | ~csr_status_r_pass) begin
avmm_readdata <= 32\'hffffffff;
end
else begin
avmm_readdata <= flash_drdout;
end
end
// avoid async reset removal issue
assign reset_n_w = reset_n_reg2;
// initial register
initial begin
csr_status_busy = STATUS_IDLE;
csr_status_e_pass = 0;
csr_status_w_pass = 0;
csr_status_r_pass = 0;
avmm_burstcount_input_reg = {(AVMM_DATA_BURSTCOUNT_WIDTH){1\'b0}};
avmm_burstcount_reg = {(AVMM_DATA_BURSTCOUNT_WIDTH){1\'b0}};
erase_state = ERASE_STATE_IDLE;
write_state = WRITE_STATE_IDLE;
read_state = READ_STATE_IDLE;
avmm_read_state = READ_SETUP;
avmm_read_valid_state = READ_VALID_IDLE;
avmm_readdatavalid_reg = 0;
avmm_readdata_ready = 0;
flash_sector_addr = 0;
flash_page_addr = 0;
flash_ardin_align_reg = {(FLASH_ADDR_ALIGNMENT_BITS){1\'b0}};
flash_ardin_align_backup_reg = {(FLASH_ADDR_ALIGNMENT_BITS){1\'b0}};
write_drclk_en = 0;
read_drclk_en = 0;
flash_drshft_reg = 1;
flash_drshft_neg_reg = 1;
flash_busy_reg = 0;
flash_busy_clear_reg = 0;
flash_se_neg_reg = 0;
flash_se_pass_reg = 0;
flash_sp_pass_reg = 0;
erase_busy_scan = 0;
write_busy_scan = 0;
flash_seq_read_ardin = 0;
enable_arclk_neg_reg = 0;
enable_arclk_neg_pos_reg = 0;
enable_drclk_neg_reg = 0;
enable_drclk_neg_pos_reg = 0;
enable_drclk_neg_pos_write_reg = 0;
flash_drdin_neg_reg = 0;
write_count = 0;
erase_count = 0;
read_ctrl_count = 0;
data_count = 0;
write_timeout = 0;
erase_timeout = 0;
write_wait = 0;
write_wait_neg = 0;
reset_n_reg1 = 0;
reset_n_reg2 = 0;
read_wait = 0;
read_wait_neg = 0;
read_count = 0;
is_sector1_writable_reg = 0;
is_sector2_writable_reg = 0;
is_sector3_writable_reg = 0;
is_sector4_writable_reg = 0;
is_sector5_writable_reg = 0;
end
// -------------------------------------------------------------------
// Avoid async reset removal issue
// -------------------------------------------------------------------
always @ (negedge reset_n or posedge clock) begin
if (~reset_n) begin
{reset_n_reg2, reset_n_reg1} <= 2\'b0;
end
else begin
{reset_n_reg2, reset_n_reg1} <= {reset_n_reg1, 1\'b1};
end
end
// -------------------------------------------------------------------
// Sync combinational output before feeding into flash
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
enable_arclk_sync_reg <= 0;
end
else begin
enable_arclk_sync_reg <= flash_arclk_arshft_en_w;
end
end
// -------------------------------------------------------------------
// Get rid of the race condition between different dynamic clock. Trigger clock enable in early half cycle.
// -------------------------------------------------------------------
always @ (negedge clock) begin
if (~reset_n_w) begin
enable_arclk_neg_reg <= 0;
enable_drclk_neg_reg <= 0;
flash_drshft_neg_reg <= 1;
flash_se_neg_reg <= 0;
write_wait_neg <= 0;
read_wait_neg <= 0;
end
else begin
enable_arclk_neg_reg <= enable_arclk_sync_reg;
enable_drclk_neg_reg <= (write_drclk_en || read_drclk_en);
flash_drshft_neg_reg <= flash_drshft_reg;
flash_se_neg_reg <= flash_se_w;
write_wait_neg <= write_wait;
read_wait_neg <= read_wait;
end
end
// -------------------------------------------------------------------
// Get rid of glitch for pos clock
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
enable_arclk_neg_pos_reg <= 0;
end
else begin
enable_arclk_neg_pos_reg <= enable_arclk_neg_reg;
end
end
// -------------------------------------------------------------------
// Pine line page address path
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
flash_page_addr <= 0;
end
else begin
flash_page_addr <= flash_page_addr_wire;
end
end
generate // generate always block based on read and write mode. Write and erase operation is unnecessary in read only mode.
if (READ_AND_WRITE_MODE == 1) begin
// -------------------------------------------------------------------
// Pine line sector address path
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
flash_sector_addr <= 0;
end
else begin
flash_sector_addr <= flash_sector_wire;
end
end
// -------------------------------------------------------------------
// Minitor flash pass signal and update CSR busy status
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
flash_se_pass_reg <= 0;
flash_sp_pass_reg <= 0;
csr_status_busy <= STATUS_IDLE;
end
else begin
flash_se_pass_reg <= flash_se_pass;
flash_sp_pass_reg <= flash_sp_pass;
if (is_erase_busy) begin
csr_status_busy <= STATUS_BUSY_ERASE;
end
else if (is_write_busy) begin
csr_status_busy <= STATUS_BUSY_WRITE;
end
else if (is_read_busy) begin
csr_status_busy <= STATUS_BUSY_READ;
end
else begin
csr_status_busy <= STATUS_IDLE;
end
end
end
// -------------------------------------------------------------------
// Monitor and store flash busy signal, it may faster then the clock
// -------------------------------------------------------------------
wire busy_scan;
assign busy_scan = (erase_busy_scan || write_busy_scan);
always @ (negedge reset_n or negedge busy_scan or posedge flash_osc) begin
if (~reset_n || ~busy_scan) begin
flash_busy_reg <= 0;
flash_busy_clear_reg <= 0;
end
else if (flash_busy_reg) begin
flash_busy_reg <= flash_busy_reg;
flash_busy_clear_reg <= ~flash_busy;
end
else begin
flash_busy_reg <= flash_busy;
flash_busy_clear_reg <= 0;
end
end
altera_std_synchronizer #(
.depth (2)
) stdsync_busy (
.clk(clock), // clock
.din(flash_busy_reg), // busy signal
.dout(flash_busy_sync), // busy signal which reg to clock
.reset_n(reset_n) // active low reset
);
altera_std_synchronizer #(
.depth (2)
) stdsync_busy_clear (
.clk(clock), // clock
.din(flash_busy_clear_reg), // busy signal
.dout(flash_busy_clear_sync), // busy signal which reg to clock
.reset_n(reset_n) // active low reset
);
// -------------------------------------------------------------------
// Get rid of the race condition of shftreg signal (drdin), add half cycle delay to the data
// -------------------------------------------------------------------
always @ (negedge clock) begin
if (~reset_n_w) begin
flash_drdin_neg_reg <= 1;
end
else begin
flash_drdin_neg_reg <= flash_drdin_w;
end
end
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Write Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
write_state <= WRITE_STATE_IDLE;
write_wait <= 0;
end
else begin
case (write_state)
WRITE_STATE_IDLE: begin
// reset all register
write_count <= 0;
write_timeout <= 1\'b0;
write_busy_scan <= 1\'b0;
enable_drclk_neg_pos_write_reg <= 0;
// check command
if (avmm_write) begin
if (~valid_csr_erase && ~is_erase_busy && ~is_read_busy) begin
write_state <= WRITE_STATE_ADDR;
write_wait <= 1;
end
end
end
WRITE_STATE_ADDR: begin
if (is_addr_writable && is_valid_write_burst_count) begin
write_count <= DATA_WIDTH[5:0];
write_state <= WRITE_STATE_WRITE;
end
else begin
write_wait <= 0;
write_count <= 2;
write_state <= WRITE_STATE_ERROR;
end
end
WRITE_STATE_WRITE: begin
if (write_count != 0) begin
write_drclk_en <= 1;
write_count <= write_count - 16\'d1;
end
else begin
enable_drclk_neg_pos_write_reg <= 1;
write_drclk_en <= 0;
write_busy_scan <= 1\'b1;
write_count <= FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_WAIT_BUSY;
end
end
WRITE_STATE_WAIT_BUSY: begin
if (flash_busy_sync) begin
write_count <= FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_WAIT_DONE;
end
else begin
if (write_count != 0)
write_count <= write_count - 16\'d1;
else begin
write_timeout <= 1\'b1;
write_count <= FLASH_RESET_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_RESET;
end
end
end
WRITE_STATE_WAIT_DONE: begin
if (flash_busy_clear_sync) begin
write_count <= FLASH_RESET_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_RESET;
end
else begin
if (write_count != 0) begin
write_count <= write_count - 16\'d1;
end
else begin
write_timeout <= 1\'b1;
write_count <= FLASH_RESET_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_RESET;
end
end
end
WRITE_STATE_RESET: begin
write_busy_scan <= 1\'b0;
if (write_timeout) begin
csr_status_w_pass <= 1\'b0;
end
else begin
csr_status_w_pass <= flash_sp_pass_reg;
end
if (write_count == 1) begin
write_wait <= 0;
end
if (write_count != 0) begin
write_count <= write_count - 16\'d1;
end
else begin
write_state <= WRITE_STATE_IDLE;
end
end
WRITE_STATE_ERROR: begin
csr_status_w_pass <= 1\'b0;
if (write_count == 1) begin
write_wait <= 0;
end
if (write_count != 0) begin
write_count <= write_count - 16\'d1;
end
else begin
write_state <= WRITE_STATE_IDLE;
end
end
default: begin
write_state <= WRITE_STATE_IDLE;
end
endcase
end
end
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Erase Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
erase_state <= ERASE_STATE_IDLE;
end
else begin
case (erase_state)
ERASE_STATE_IDLE: begin
// reset all register
erase_count <= 0;
erase_timeout <= 1\'b0;
erase_busy_scan <= 1\'b0;
// check command
if (valid_csr_erase && ~is_write_busy && ~is_read_busy) begin
erase_state <= ERASE_STATE_ADDR;
end
end
ERASE_STATE_ADDR: begin
if (is_erase_addr_writable) begin
erase_busy_scan <= 1\'b1;
erase_count <= FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_WAIT_BUSY;
end
else begin
erase_count <= 2;
erase_state <= ERASE_STATE_ERROR;
end
end
ERASE_STATE_WAIT_BUSY: begin
if (flash_busy_sync) begin
erase_count <= FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_WAIT_DONE;
end
else begin
if (erase_count != 0)
erase_count <= erase_count - 26\'d1;
else begin
erase_timeout <= 1\'b1;
erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_RESET;
end
end
end
ERASE_STATE_WAIT_DONE: begin
if (flash_busy_clear_sync) begin
erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_RESET;
end
else begin
if (erase_count != 0) begin
erase_count <= erase_count - 26\'d1;
end
else begin
erase_timeout <= 1\'b1;
erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_RESET;
end
end
end
ERASE_STATE_RESET: begin
erase_busy_scan <= 1\'b0;
if (erase_timeout) begin
csr_status_e_pass <= 1\'b0;
end
else begin
csr_status_e_pass <= flash_se_pass_reg;
end
if (erase_count != 0) begin
erase_count <= erase_count - 26\'d1;
end
else begin
erase_state <= ERASE_STATE_IDLE;
end
end
ERASE_STATE_ERROR: begin
csr_status_e_pass <= 1\'b0;
if (erase_count != 0) begin
erase_count <= erase_count - 26\'d1;
end
else begin
erase_state <= ERASE_STATE_IDLE;
end
end
default: begin
erase_state <= ERASE_STATE_IDLE;
end
endcase
end
end
end
endgenerate
generate // generate always block for read operation based on read burst mode.
if (WRAPPING_BURST_MODE == 0) begin
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Increamenting Burst Read Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
read_state <= READ_STATE_IDLE;
read_wait <= 0;
end
else begin
case (read_state)
READ_STATE_IDLE: begin
// reset all register
avmm_read_state <= READ_SETUP;
avmm_readdata_ready <= 0;
flash_ardin_align_reg <= 0;
read_ctrl_count <= 0;
avmm_burstcount_input_reg <= 0;
enable_drclk_neg_pos_reg <= 0;
read_drclk_en <= 0;
flash_drshft_reg <= 1;
// check command
if (avmm_read) begin
if (~valid_csr_erase && ~is_erase_busy && ~is_write_busy) begin
read_wait <= 1;
read_state <= READ_STATE_ADDR;
flash_seq_read_ardin <= avmm_addr;
avmm_burstcount_input_reg <= avmm_burstcount;
end
end
end
READ_STATE_ADDR: begin
if (is_addr_within_valid_range) begin
csr_status_r_pass <= 1;
end
else begin
csr_status_r_pass <= 0;
end
read_wait <= 0;
read_state <= READ_STATE_PULSE_SE;
end
READ_STATE_PULSE_SE: begin
read_wait <= 1;
\t\t read_state <= READ_STATE_SETUP;
end
// incrementing read
READ_STATE_SETUP: begin
if (next_flash_read_ardin > MAX_VALID_ADDR) begin
flash_seq_read_ardin <= MIN_VALID_ADDR[FLASH_ADDR_WIDTH-1:0];
end
else begin
flash_seq_read_ardin <= next_flash_read_ardin;
end
flash_ardin_align_reg <= flash_seq_read_ardin[FLASH_ADDR_ALIGNMENT_BITS-1:0];
if (FLASH_READ_CYCLE_MAX_INDEX[2:0] > 2) begin
read_ctrl_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0] - 3\'d2;
read_state <= READ_STATE_DUMMY;
end
else begin
read_state <= READ_STATE_READY;
end
end
READ_STATE_DUMMY: begin
if (read_ctrl_count > 1) begin
read_ctrl_count <= read_ctrl_count - 3\'d1;
end
else begin
read_state <= READ_STATE_READY;
end
end
READ_STATE_READY: begin
if (avmm_read_state == READ_SETUP) begin
avmm_readdata_ready <= 1;
end
read_drclk_en <= 1;
flash_drshft_reg <= 0;
read_state <= READ_STATE_FINAL;
end
READ_STATE_FINAL: begin
flash_drshft_reg <= 1;
avmm_readdata_ready <= 0;
avmm_read_state <= READ_RECV_DATA;
if ((avmm_read_state == READ_RECV_DATA) && (avmm_burstcount_reg == 0)) begin
read_state <= READ_STATE_CLEAR;
read_drclk_en <= 0;
enable_drclk_neg_pos_reg <= 1;
end
else begin
read_state <= READ_STATE_PULSE_SE;
end
end
// Dummy state to clear arclk glitch
READ_STATE_CLEAR: begin
read_wait <= 0;
read_state <= READ_STATE_IDLE;
end
default: begin
read_state <= READ_STATE_IDLE;
end
endcase
end
end
end
else begin
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Wrapping Burst Read Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
read_state <= READ_STATE_IDLE;
read_wait <= 0;
end
else begin
case (read_state)
READ_STATE_IDLE: begin
// reset all register
avmm_readdata_ready <= 0;
flash_ardin_align_reg <= 0;
read_ctrl_count <= 0;
enable_drclk_neg_pos_reg <= 0;
flash_drshft_reg <= 1;
read_drclk_en <= 0;
avmm_burstcount_input_reg <= 0;
// check command
if (avmm_read) begin
if (~valid_csr_erase && ~is_erase_busy && ~is_write_busy) begin
read_wait <= 1;
read_state <= READ_STATE_ADDR;
avmm_burstcount_input_reg <= avmm_burstcount;
end
end
end
READ_STATE_ADDR: begin
read_wait <= 0;
if (is_addr_within_valid_range) begin
csr_status_r_pass <= 1;
end
else begin
csr_status_r_pass <= 0;
end
read_state <= READ_STATE_PULSE_SE;
read_ctrl_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0] + 3\'d1;
end
READ_STATE_PULSE_SE: begin
read_wait <= 1;
\t\t read_state <= READ_STATE_READ;
end
// wrapping read
READ_STATE_READ: begin
// read control signal
if (read_ctrl_count > 0) begin
read_ctrl_count <= read_ctrl_count - 3\'d1;
end
if (read_ctrl_count == 2) begin
avmm_readdata_ready <= 1;
read_drclk_en <= 1;
flash_drshft_reg <= 0;
end
else begin
flash_drshft_reg <= 1;
end
if (avmm_read && ~read_wait) begin
read_wait <= 1;
end
if (avmm_readdata_ready || read_ctrl_count == 0) begin
avmm_readdata_ready <= 0;
if (avmm_read) begin
avmm_burstcount_input_reg <= avmm_burstcount;
read_state <= READ_STATE_ADDR;
end
end
// read data signal
if (read_count > 0) begin
read_count <= read_count - 3\'d1;
end
else begin
if (avmm_readdata_ready) begin
read_count <= FLASH_SEQ_READ_DATA_COUNT[2:0] - 3\'d1;
end
end
// back to idle if both control and read cycle are finished
if (read_ctrl_count == 0 && read_count == 0 && ~avmm_read) begin
read_state <= READ_STATE_IDLE;
read_drclk_en <= 0;
read_wait <= 0;
enable_drclk_neg_pos_reg <= 1;
end
end
default: begin
read_state <= READ_STATE_IDLE;
end
endcase
end
end
end
endgenerate
generate // generate readdatavalid control signal always block based on read burst mode.
if (WRAPPING_BURST_MODE == 0) begin
// -------------------------------------------------------------------
// Control readdatavalid signal - incrementing read
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_burstcount_reg <= 0;
avmm_readdatavalid_reg <= 0;
flash_ardin_align_backup_reg <= 0;
data_count <= 0;
end
else begin
case (avmm_read_valid_state)
READ_VALID_IDLE: begin
if (avmm_readdata_ready) begin
data_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0];
avmm_read_valid_state <= READ_VALID_PRE_READING;
avmm_burstcount_reg <= avmm_burstcount_input_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1\'b0}}, 1\'b1};
flash_ardin_align_backup_reg <= flash_ardin_align_reg;
end
end
READ_VALID_PRE_READING: begin
avmm_readdatavalid_reg <= 1;
avmm_read_valid_state <= READ_VALID_READING;
end
READ_VALID_READING: begin
if (avmm_burstcount_reg == 0) begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_readdatavalid_reg <= 0;
end
else begin
if (data_count > 0) begin
if ((FLASH_READ_CYCLE_MAX_INDEX - data_count + 1 + flash_ardin_align_backup_reg) < FLASH_SEQ_READ_DATA_COUNT) begin
avmm_readdatavalid_reg <= 1;
avmm_burstcount_reg <= avmm_burstcount_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1\'b0}}, 1\'b1};
end
else begin
avmm_readdatavalid_reg <= 0;
end
data_count <= data_count - 3\'d1;
end
else begin
flash_ardin_align_backup_reg <= 0;
data_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0];
avmm_read_valid_state <= READ_VALID_PRE_READING;
avmm_burstcount_reg <= avmm_burstcount_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1\'b0}}, 1\'b1};
end
end
end
default: begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_burstcount_reg <= 0;
avmm_readdatavalid_reg <= 0;
flash_ardin_align_backup_reg <= 0;
data_count <= 0;
end
endcase
end
end
end
else begin
// -------------------------------------------------------------------
// Control readdatavalid signal - wrapping read with fixed burst count
// Burst count
// 1~2 - ZB8
// 1~4 - all other devices
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_readdatavalid_reg <= 0;
end
else begin
case (avmm_read_valid_state)
READ_VALID_IDLE: begin
data_count <= 0;
if (avmm_readdata_ready) begin
data_count <= avmm_burstcount_input_reg - 3\'d1;
avmm_read_valid_state <= READ_VALID_PRE_READING;
end
end
READ_VALID_PRE_READING: begin
avmm_readdatavalid_reg <= 1;
avmm_read_valid_state <= READ_VALID_READING;
end
READ_VALID_READING: begin
if (data_count > 0) begin
data_count <= data_count - 3\'d1;
end
else begin
if (avmm_readdata_ready) begin
data_count <= avmm_burstcount_input_reg - 3\'d1;
end
else begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_readdatavalid_reg <= 0;
end
end
end
default: begin
avmm_read_valid_state <= READ_VALID_IDLE;
end
endcase
end
end
end
endgenerate
generate // generate shiftreg based on read and write mode. Unnecessary in read only mode.
if (READ_AND_WRITE_MODE == 1) begin
// -------------------------------------------------------------------
// Instantiate a shift register to send the data to UFM serially (load parallel)
// -------------------------------------------------------------------
lpm_shiftreg # (
.lpm_type ("LPM_SHIFTREG"),
.lpm_width (DATA_WIDTH),
.lpm_direction ("LEFT")
) ufm_data_shiftreg (
.data(avmm_writedata),
.clock(clock),
.enable(write_state == WRITE_STATE_WRITE),
.load(write_count == DATA_WIDTH),
.shiftout(flash_drdin_w),
.aclr(write_state == WRITE_STATE_IDLE)
);
end
endgenerate
altera_onchip_flash_address_range_check # (
.MIN_VALID_ADDR(MIN_VALID_ADDR),
.MAX_VALID_ADDR(MAX_VALID_ADDR)
) address_range_checker (
.address(cur_read_addr),
.is_addr_within_valid_range(is_addr_within_valid_range)
);
altera_onchip_flash_convert_address # (
.ADDR_RANGE1_END_ADDR(ADDR_RANGE1_END_ADDR),
.ADDR_RANGE1_OFFSET(ADDR_RANGE1_OFFSET),
.ADDR_RANGE2_OFFSET(ADDR_RANGE2_OFFSET)
) address_convertor (
.address(cur_a_addr),
.flash_addr(flash_page_addr_wire)
);
generate // sector address convertsion is unnecessary in read only mode
if (READ_AND_WRITE_MODE == 1) begin
// pipe line addr legality check logic
always @ (posedge clock) begin
if (~reset_n_w) begin
is_sector1_writable_reg <= 1\'b0;
is_sector2_writable_reg <= 1\'b0;
is_sector3_writable_reg <= 1\'b0;
is_sector4_writable_reg <= 1\'b0;
is_sector5_writable_reg <= 1\'b0;
end
else begin
is_sector1_writable_reg <= ~(csr_write_protection_mode[0] || SECTOR_READ_PROTECTION_MODE[0]);
is_sector2_writable_reg <= ~(csr_write_protection_mode[1] || SECTOR_READ_PROTECTION_MODE[1]);
is_sector3_writable_reg <= ~(csr_write_protection_mode[2] || SECTOR_READ_PROTECTION_MODE[2]);
is_sector4_writable_reg <= ~(csr_write_protection_mode[3] || SECTOR_READ_PROTECTION_MODE[3]);
is_sector5_writable_reg <= ~(csr_write_protection_mode[4] || SECTOR_READ_PROTECTION_MODE[4]);
end
end
altera_onchip_flash_a_address_write_protection_check # (
.SECTOR1_START_ADDR(SECTOR1_START_ADDR),
.SECTOR1_END_ADDR(SECTOR1_END_ADDR),
.SECTOR2_START_ADDR(SECTOR2_START_ADDR),
.SECTOR2_END_ADDR(SECTOR2_END_ADDR),
.SECTOR3_START_ADDR(SECTOR3_START_ADDR),
.SECTOR3_END_ADDR(SECTOR3_END_ADDR),
.SECTOR4_START_ADDR(SECTOR4_START_ADDR),
.SECTOR4_END_ADDR(SECTOR4_END_ADDR),
.SECTOR5_START_ADDR(SECTOR5_START_ADDR),
.SECTOR5_END_ADDR(SECTOR5_END_ADDR)
) access_address_write_protection_checker (
.address(cur_a_addr),
.is_sector1_writable(is_sector1_writable_reg),
.is_sector2_writable(is_sector2_writable_reg),
.is_sector3_writable(is_sector3_writable_reg),
.is_sector4_writable(is_sector4_writable_reg),
.is_sector5_writable(is_sector5_writable_reg),
.is_addr_writable(is_addr_writable)
);
altera_onchip_flash_s_address_write_protection_check sector_address_write_protection_checker (
.address(cur_e_addr[2:0]),
.is_sector1_writable(is_sector1_writable_reg),
.is_sector2_writable(is_sector2_writable_reg),
.is_sector3_writable(is_sector3_writable_reg),
.is_sector4_writable(is_sector4_writable_reg),
.is_sector5_writable(is_sector5_writable_reg),
.is_addr_writable(is_sector_writable)
);
altera_onchip_flash_convert_sector # (
.SECTOR1_MAP(SECTOR1_MAP),
.SECTOR2_MAP(SECTOR2_MAP),
.SECTOR3_MAP(SECTOR3_MAP),
.SECTOR4_MAP(SECTOR4_MAP),
.SECTOR5_MAP(SECTOR5_MAP)
) sector_convertor (
.sector(cur_e_addr[2:0]),
.flash_sector(flash_sector_wire)
);
end
endgenerate
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation\'s design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
////////////////////////////////////////////////////////////////////
//
// ALTERA_INT_OSC
//
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation\'s design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
////////////////////////////////////////////////////////////////////
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
`timescale 1 ps / 1 ps
module altera_int_osc
\t(
\tclkout,
\toscena);
\tparameter DEVICE_FAMILY = "MAX 10";
\tparameter DEVICE_ID = "08";
\tparameter CLOCK_FREQUENCY = "dummy";
\t
\toutput clkout;
\tinput oscena;
\t
\twire wire_clkout;
\t
\tassign clkout = wire_clkout;
\t\t
\t// -------------------------------------------------------------------
\t// Instantiate wysiwyg for chipidblock according to device family
\t// -------------------------------------------------------------------\t
\tgenerate
\t\tif (DEVICE_FAMILY == "MAX 10") begin
\t\t\tfiftyfivenm_oscillator # (\t//MAX 10
\t\t\t\t.device_id(DEVICE_ID),
\t\t\t\t.clock_frequency(CLOCK_FREQUENCY)
\t\t\t) oscillator_dut (
\t\t\t\t.clkout(wire_clkout),
\t\t\t\t.clkout1(),
\t\t\t\t.oscena(oscena));
\t\t\tend
\tendgenerate
\t
endmodule //altera_int_osc
//VALID FILE
|
// Copyright 2019 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// Verilog for the XC95144XL chip onboard an a3000_rom_emulator board.
// This connects to the host machine pins (rom_A, rom_nCS, rom_D), most flash
// signals (flash_A, flash0_DQ, flash1_DQ, flash_nCE, flash_nOE, flash_nWE --
// flash_nREADY and flash_nRESET are driven by the on-board microcontroller),
// and the SPI port on the microcontroller (cpld_{MOSI, SS, SCK, MISO}).
// In normal operation (allowing_arm_access==1), rom_A is simply passed
// through to flash_A, with rom_nCS driving both flash_nCE and flash_nOE (with
// flash_nWE==1). rom_D is tristated when rom_nCS == 1, and flash_{0, 1}_DQ
// are passed through to rom_D when rom_nCS == 0.
// When the microcontroller wants to take over, it drives an 8-byte SPI
// transaction:
// read: <allowing_arm_access> 1 <A x 22> <0 x 40> -- data returned in final 32 bits
// write: <allowing_arm_access> 0 <A x 22> <data x 32> <0 x 8>
// If allowing_arm_access == 1, the read or write will be ignored, and all the
// transaction will do is give access to the flash back to the host machine.
module a3000_rom_emulator(
// connections to archimedes motherboard
inout wire [31:0] rom_D, // ARM data bus
input wire [19:0] rom_A, // LA21:2
input wire rom_nCS, // MEMC Romcs*
input wire rom_nOE, // Lionrw (latched IO nR/W) on a Risc PC, debug everywhere else
// connections to two flash chips
output wire [21:0] flash_A,
inout wire [15:0] flash0_DQ,
inout wire [15:0] flash1_DQ,
output wire flash_nCE,
output wire flash_nOE,
output wire flash_nWE,
// 48MHz clock
input wire cpld_clock_from_mcu,
// 5V line from ROM socket, used to attempt to detect if the host machine is
// powered. Unreliable, so it\'s safest to just not fit D2, which ensures
// that the CPLD is only ever powered from rom_5V and prevents the board
// from attempting to power the host system if something goes wrong.
input wire rom_5V,
// SPI connection to MCU
input wire cpld_MOSI, // doubles as serial RXD when cpld_SS=1
input wire cpld_SS,
input wire cpld_SCK,
output wire cpld_MISO // doubles as serial TXD when cpld_SS=1
);
// set to 1 for v2 boards and v1 with Risc PC adapter
parameter use_output_enable_signal_from_host = 1;
wire host_output_enable;
assign host_output_enable = use_output_enable_signal_from_host ? rom_nOE : 1\'b0;
// set to 1 once the power signal has been wired to rom_5V
parameter use_power_signal_from_host = 1;
wire host_power_on;
assign host_power_on = use_power_signal_from_host ? rom_5V : 1\'b1;
// ----- ARM-MCU comms with handshaking -- better than bit-banged serial, but won\'t fit in XC95144) -----
// enable/disable arm-mcu comms
parameter enable_comms = 0;
// width of the buffer used to communicate between the ARM and MCU; requires 2x this in registers.
parameter comms_buffer_width = 1;
reg [comms_buffer_width-1:0] mcu_to_arm_buffer;
reg mcu_to_arm_write_state = 1\'b0; // toggles when cpld receives byte from MCU
reg mcu_to_arm_write_state_sync = 1\'b0; // synchronized to cpld_clock_from_mcu (48MHz)
reg mcu_to_arm_read_state = 1\'b0; // toggles when ARM reads byte from buffer
reg mcu_to_arm_read_state_sync = 1\'b0; // synchronized to cpld_SCK
reg [comms_buffer_width-1:0] arm_to_mcu_buffer;
reg arm_to_mcu_write_state = 1\'b0; // toggles when cpld receives byte from ARM
reg arm_to_mcu_write_state_sync = 1\'b0; // synchronized to cpld_SCK
reg arm_to_mcu_read_state = 1\'b0; // toggles when MCU reads byte from buffer
reg arm_to_mcu_read_state_sync = 1\'b0; // synchronized to cpld_clock_from_mcu (48MHz)
// ----- Hacky bit-banged serial comms; actually works but requires more work on ARM side -----
// enable/disable hacky bit banged serial comms
parameter enable_bitbang_serial = !enable_comms;
// for bit-banged serial comms
reg cpld_TXD_sync = 1\'b1; // synchronized to rom_nCS falling edge
reg cpld_MISO_TXD = 1\'b1; // value to assign to cpld_MISO when cpld_SS==1
// ---- SPI registers -----
// SPI MISO output
reg cpld_MISO_int = 1\'b1; // MISO when cpld_SS==0
// counts up to 63
reg [5:0] spi_bit_count = 6\'b0;
// 1 if the SPI transaction is a read, 0 for a write
reg spi_rnw = 1\'b1;
// Address value in SPI transaction
reg [21:0] spi_A = 22\'b0;
// Data value in SPI transaction
reg [31:0] spi_D = 32\'b0;
// 1 when an SPI transaction wants flash_nCE low (and flash_nOE for reads)
reg accessing_flash = 1\'b0;
// 1 when an SPI transaction wants flash_nWE low
reg writing_flash = 1\'b0;
// ----- Config registers -----
// 1 to pass host accesses through to the flash, 0 to control flash from SPI
reg allowing_arm_access = 1\'b1;
// 1 to use rom_A[19] (LA21) and provide 4MB of flash, 0 to ignore it and provide 2MB
reg use_la21 = 1\'b0;
// 1 to use rom_A[18] (LA20) for a 2+MB bank, 0 for a 1MB bank
reg use_la20 = 1\'b1;
// Flash bank selected; bit 1 is ignored if use_la21==1, bit 0 is ignored if use_la20==1
reg [3:0] flash_bank = 4\'b0;
// ----- Read-sensitive ROM locations -----
// 1 when rom_A is pointing at the top 16 bytes (4 words) of ROM
wire accessing_signal_ROM;
assign accessing_signal_ROM = (
rom_A[18:2] == 17\'b11111111111111111
&& (use_la21 == 1\'b0 || rom_A[19] == 1\'b1)
) ? 1\'b1 : 1\'b0; // TODO this can prob be 18:2==17\'b1...1 because we only need 2 bits
// synchronize mcu-to-arm signals when romcs goes active.
// any metastability should settle by the time these values are read.
always @(negedge rom_nCS) begin
mcu_to_arm_write_state_sync <= mcu_to_arm_write_state;
arm_to_mcu_read_state_sync <= arm_to_mcu_read_state;
if (enable_bitbang_serial) begin
// synchronize MOSI / TXD
cpld_TXD_sync <= cpld_MOSI;
end
end
// synchronizer for romcs*
`define DOUBLE_SYNC_ROMCS
reg romcs_sync = 0;
`ifdef DOUBLE_SYNC_ROMCS
reg romcs_pre_sync = 0;
`endif
// pulse length measurement for romcs*
reg [2:0] romcs_pulse_length = 3\'b0;
// synchronization for SPI signals
reg sck_sync, sck_last;
reg ss_sync;
reg mosi_sync;
always @(posedge cpld_clock_from_mcu) begin
// Synchronize SPI signals so we can do everything with one clock
{sck_last, sck_sync} <= {sck_sync, cpld_SCK};
ss_sync <= cpld_SS;
mosi_sync <= cpld_MOSI;
// Synchronize Romcs*
`ifdef DOUBLE_SYNC_ROMCS
{romcs_sync, romcs_pre_sync} <= {romcs_pre_sync, rom_nCS};
`else
romcs_sync <= rom_nCS;
`endif
if (romcs_sync == 1\'b1) begin
romcs_pulse_length <= 3\'b0;
end else begin
if (romcs_pulse_length != 3\'b111) begin
// don\'t allow the counter to wrap
romcs_pulse_length <= romcs_pulse_length + 1;
end
if (romcs_pulse_length == 3\'b110) begin
// pulse length of synchronized romcs = 6, which means
// we\'re about 180 ns into the pulse, and safely past
// the point where MEMC might change its mind and
// bring romcs* high again.
// see if rom_A is pointing at the last 2kB of ROM, i.e.
// the last 512 words. rom_A[9:2] contain a data byte
// for us, and rom_A[10] is RnW.
if (accessing_signal_ROM == 1\'b1) begin
if (rom_A[1] == 1\'b0) begin
if (enable_comms) begin
// ARM is writing data for the MCU
arm_to_mcu_buffer <= rom_A[comms_buffer_width+1:2];
arm_to_mcu_write_state <= !arm_to_mcu_write_state;
end
if (enable_bitbang_serial) begin
cpld_MISO_TXD <= rom_A[0];
end
end else begin
if (enable_comms) begin
// ARM is reading data from the MCU
mcu_to_arm_read_state <= !mcu_to_arm_read_state;
end
end
end
end
end
end
// latched nR/W (Lionrw) on a Risc PC, debug everywhere else
// (see use_output_enable_signal_from_host above)
// assign rom_nOE = 1\'bZ;
// assign rom_nOE = cpld_TXD_sync; // DEBUG: bit-banged serial
// assign rom_nOE = cpld_MOSI; // DEBUG: bit-banged serial
// assign rom_nOE = cpld_MISO_TXD; // DEBUG: bit-banged serial
// assign rom_nOE = romcs_sync[1]; // DEBUG: synchronized romcs
// assign rom_nOE = clock_divider[0]; // DEBUG
// assign rom_nOE = cpld_clock_from_mcu; // DEBUG
// assign rom_nOE = cpld_SCK; // DEBUG
wire n_selected; // Romcs* low and power high
assign n_selected = (rom_nCS == 1\'b0 && host_power_on == 1\'b1 && host_output_enable == 1\'b0) ? 1\'b0 : 1\'b1;
// ARM data bus
assign rom_D = n_selected == 1\'b1 ? 32\'bZ : (
allowing_arm_access == 1\'b1 ? (
// Pass flash output through to rom_D
// DEBUG actually should be mcu_to_arm_buffer, but this lets us loopback
(accessing_signal_ROM == 1\'b1 && rom_A[1] == 1\'b1) ? {
enable_bitbang_serial ? {flash1_DQ, flash0_DQ[15:1], cpld_TXD_sync}
: (enable_comms ? {flash1_DQ, flash0_DQ[15:3], mcu_to_arm_write_state_sync, arm_to_mcu_read_state_sync, mcu_to_arm_buffer}
: {flash1_DQ, flash0_DQ})
} :
{flash1_DQ, flash0_DQ}
) : (
// allowing_arm_access == 1\'b0; we can\'t handle a flash access now
// The intention below was to make all ROM reads return "mov pc, #0x3400000" (32\'he3a0f50d)
// during programming, so the system might jump to the start of the ROM
// afterward. It didn\'t seem to do anything though, so I\'ve removed it.
// 32\'hE3A0F50E // mov pc, #0x3800000
// 32\'hE3A0F000 // mov pc, #0
32\'bZ
)
);
// Flash chip address lines
assign flash_A = allowing_arm_access == 1\'b1 ? (
// If LA21 is connected, use top two bits of flash_bank and LA21:2.
// If disconnected, use three bits of flash_bank and LA20:2.
// use_la21 == 1\'b1 ? {flash_bank[2:1], rom_A} : {flash_bank, rom_A[18:0]}
{
flash_bank[3:2],
(use_la21 == 1\'b1 ? rom_A[19] : flash_bank[1]),
(use_la20 == 1\'b1 ? rom_A[18] : flash_bank[0]),
rom_A[17:0]
}
) : (
spi_A
);
// Flash chip data lines
assign flash0_DQ = allowing_arm_access == 1\'b1 ? 16\'bZ : (accessing_flash == 1\'b1 && spi_rnw == 1\'b0 ? spi_D[15:0] : 16\'bZ);
assign flash1_DQ = allowing_arm_access == 1\'b1 ? 16\'bZ : (accessing_flash == 1\'b1 && spi_rnw == 1\'b0 ? spi_D[31:16] : 16\'bZ);
// Flash chip control lines
assign flash_nCE = allowing_arm_access == 1\'b1 ? n_selected : (accessing_flash == 1\'b1 ? 1\'b0 : 1\'b1);
assign flash_nOE = allowing_arm_access == 1\'b1 ? n_selected : (accessing_flash == 1\'b1 && spi_rnw == 1\'b1 ? 1\'b0 : 1\'b1);
assign flash_nWE = allowing_arm_access == 1\'b1 ? 1\'b1 : (writing_flash == 1\'b1 ? 1\'b0 : 1\'b1);
// Uncomment to use the 48MHz clock for everything including SPI
// `define SYNC_SPI_AGAINST_GLOBAL_CLOCK
`ifdef SYNC_SPI_AGAINST_GLOBAL_CLOCK
always @(posedge cpld_clock_from_mcu) begin
`else
always @(posedge cpld_SCK or posedge cpld_SS) begin
`endif
`ifdef SYNC_SPI_AGAINST_GLOBAL_CLOCK
if (ss_sync == 1\'b1) begin
`else
if (cpld_SS == 1\'b1) begin
`endif
accessing_flash <= 1\'b0;
spi_bit_count <= 6\'b0;
end else
`ifdef SYNC_SPI_AGAINST_GLOBAL_CLOCK
if (sck_sync == 1\'b1 && sck_last == 1\'b0)
`endif
begin
// $display("\
SPI tick! mosi=%d", cpld_MOSI);
// the master device should bring cpld_SS high between every transaction.
// SPI is big-endian; send the MSB first and clock into the LSB.
// Address to output delay is 70ns for a read, and /CE can be raised
// straight away after. With a 24MHz (42ns) SPI clock plus transit delays,
// that means three clocks to be safe:
// t=0: Set up address and drop /CE and /OE
// t=2ck: Read data, raise /CE and /OE
// For writes, the cycle time is 60ns, write pulse width is 25ns, write
// pulse high is 20ns, and address hold time is 45ns. Ideally four clocks:
// t=0: Set up address and data and drop /CE
// t=1ck: Drop /WR
// t=2ck: Raise /WR
// t=3ck: Raise /CE
// So for reads: 0=arm 1=rnw 2-23=A 24-31=0 32-63=data (setting up A from 2-23, reading at 31)
// And for writes: 0=arm 1=rnw 2-23=A 24-55=data 56-63=0 (setting up A and D from 2-55, /CE low from 56-59, /WR low from 57-58)
if (spi_bit_count == 0) begin
allowing_arm_access <= cpld_MOSI;
arm_to_mcu_write_state_sync <= arm_to_mcu_write_state; // TODO use this
mcu_to_arm_read_state_sync <= mcu_to_arm_read_state; // TODO use this
// $display("SPI: Set allowing_arm_access to %d", cpld_MOSI);
end else if (allowing_arm_access == 1) begin
if (spi_bit_count < 8) begin
// allowing ARM access: rest of SPI transaction (one byte) is a control message
// bit 0-1: unused
// bit 2: use_la21
// bit 3: use_la20
// bit 4-7: flash_bank
{use_la21, use_la20, flash_bank} <= {use_la20, flash_bank, cpld_MOSI};
end else if (spi_bit_count == 12) begin
if (enable_comms) begin
// mcu has data for me
mcu_to_arm_write_state <= cpld_MOSI;
spi_D[31] <= arm_to_mcu_write_state; // HACK: 41.6ns to resolve metastability
// TODO toggle write state rather than copy
end
end else if (spi_bit_count == 13) begin
if (enable_comms) begin
// mcu has buffer space for me to transmit
arm_to_mcu_read_state <= cpld_MOSI;
// TODO toggle read state rather than copy
spi_D[31] <= mcu_to_arm_read_state; // HACK: 41.6ns to resolve metastability
end
end else if (spi_bit_count == 14) begin
if (enable_comms) begin
// data bit from mcu
// TODO only replace if there\'s room
// (can dispense with this if we really need the space)
mcu_to_arm_buffer <= {cpld_MOSI};
spi_D[31] <= arm_to_mcu_buffer[0]; // HACK: 41.6ns to resolve metastability
end
end
end else begin
// not allowing ARM access: rest of SPI transaction is a flash access request
if (spi_bit_count == 1) begin
spi_rnw <= cpld_MOSI;
end else if (spi_bit_count < 24) begin // 22 bit address in spi bits 2-23
spi_A <= {spi_A[20:0], cpld_MOSI};
end else if (spi_rnw == 1\'b1) begin
// FLASH READ
// 24-31=0 32-63=data (setting up A from 2-23, /CE+/OE low at 24,reading at 31)
if (spi_bit_count == 24) begin
// start read
accessing_flash <= 1\'b1;
end else if (spi_bit_count == 31) begin
// end read
spi_D <= {flash1_DQ, flash0_DQ};
accessing_flash <= 1\'b0;
end else if (spi_bit_count >= 32) begin
spi_D <= {spi_D[30:0], 1\'b0};
end
end else if (spi_rnw == 1\'b0) begin
// FLASH WRITE
// 24-55=data 56-63=0 (setting up A and D from 2-55, /CE low from 56-59, /WR low from 57-58)
if (spi_bit_count < 56) begin
spi_D <= {spi_D[30:0], cpld_MOSI};
end
if (spi_bit_count == 56) begin
accessing_flash <= 1\'b1;
end
if (spi_bit_count == 57) begin
writing_flash <= 1\'b1;
end
if (spi_bit_count == 58) begin
writing_flash <= 1\'b0;
end
if (spi_bit_count == 59) begin
accessing_flash <= 1\'b0;
end
end
end
spi_bit_count <= spi_bit_count + 1;
end
end
always @(negedge cpld_SCK) begin
cpld_MISO_int <= spi_D[31];
if (enable_comms) begin
if (spi_bit_count == 12) begin
// we have data for mcu
// cpld_MISO <= arm_to_mcu_write_state_sync;
// TODO toggle write state rather than copy
end else if (spi_bit_count == 13) begin
// we have buffer space for mcu to transmit
// cpld_MISO <= mcu_to_arm_read_state_sync;
// TODO toggle read state rather than copy
end else if (spi_bit_count == 14) begin
// data bit from arm
// TODO only replace if there\'s room
// (can dispense with this if we really need the space)
// cpld_MISO <= arm_to_mcu_buffer[0];
end
end
end
// output cpld_MISO_TXD when cpld_SS==1 and the bit-banged serial port is enabled
assign cpld_MISO = (enable_bitbang_serial && cpld_SS == 1\'b1) ? cpld_MISO_TXD : cpld_MISO_int;
endmodule
|
// Copyright 2018 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`timescale 1ns/100ps
`include "master_updateable_megarom.v"
`define assert(condition, message) if(!(condition)) begin $display(message); $finish(1); end
module master_updateable_megarom_tb;
// test clock
reg clk;
// inputs to the module under test
wire [7:0] D; // inout, but we only care about it when it\'s an output
reg [16:0] bbc_A = 16\'b0; // driven by BBC
reg [1:0] cpld_JP = 2\'b00; // driven externally
// outputs from the module under test
wire [18:0] flash_A;
wire flash_nOE;
wire flash_nWE;
// test spi feeder
reg spi_ss = 1\'b1;
reg spi_sck = 1\'b0;
reg spi_mosi = 1\'b0;
wire spi_miso;
reg [31:0] spi_shift;
reg [31:0] spi_d;
reg spi_start = 0; // drive this high for one clk pulse to start an spi transaction
reg [5:0] spi_count;
// module under test
master_updateable_megarom dut(
.D(D),
.bbc_A(bbc_A),
.flash_A(flash_A),
.flash_nOE(flash_nOE),
.flash_nWE(flash_nWE),
.cpld_SCK_in(spi_sck),
.cpld_MOSI(spi_mosi),
.cpld_SS(spi_ss),
.cpld_MISO(spi_miso),
.cpld_JP(cpld_JP)
);
// clock driver
initial begin
clk = 1\'b0;
forever #9 clk = ~clk;
end
// spi process
always @(posedge clk) begin
if (spi_start == 1\'b1) begin
$display("- start SPI transaction");
spi_ss <= 1\'b0;
spi_count <= 6\'d32;
spi_mosi <= spi_d[31]; // first bit
spi_shift <= {spi_d[30:0], 1\'b0};
spi_sck <= 1\'b0;
end else if (spi_ss == 1\'b0) begin
if (spi_count == 0) begin
$display("- end SPI transaction with spi_shift=%x (A %x, rnw %x, wdata %x, rdata %x)",
spi_shift, spi_shift[31:13], spi_shift[12], spi_shift[11:4], spi_shift[7:0]);
spi_ss <= 1\'b1; // end of transaction
end else if (spi_sck == 1\'b0) begin
spi_sck <= 1\'b1;
end else begin
// mid-transaction
spi_mosi <= spi_shift[31];
spi_shift <= {spi_shift[30:0], spi_miso};
spi_count <= spi_count - 1;
spi_sck <= 1\'b0;
end;
end
end
always @(negedge dut.allowing_bbc_access) begin
$display("disallowing bbc access");
end
always @(posedge dut.allowing_bbc_access) begin
$display("allowing bbc access");
end
always @(negedge flash_nOE) begin
$display("flash_nOE low with flash_A=%x", flash_A);
end
// flash fixture always reads 0x42
assign D = (flash_nOE == 1\'b0) ? 8\'h42 : 8\'hZZ;
always @(posedge flash_nOE) begin
$display("flash_nOE high with flash_A=%x", flash_A);
end
always @(negedge flash_nWE) begin
$display("flash_nWE low with flash_A=%x and D=%x", flash_A, D);
end
always @(posedge flash_nWE) begin
$display("flash_nWE high with flash_A=%x and D=%x", flash_A, D);
end
initial begin
$display("running master_updateable_megarom_tb");
$dumpfile("master_updateable_megarom_tb.vcd");
$dumpvars(0, master_updateable_megarom_tb);
$display("start");
repeat(10) @(posedge clk);
// check that we start out letting the BBC control the flash
`assert(dut.allowing_bbc_access == 1\'b1, "FAIL: not allowing bbc access initially");
$display("\
Setting bbc_A to 12345");
bbc_A <= 17\'h12345;
$display("\
TEST that ffffff00 disables BBC access");
spi_d <= 32\'hffffff00;
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
@(posedge clk);
`assert(dut.allowing_bbc_access == 1\'b0, "FAIL: ffffff00 didn\'t disable bbc access");
$display("\
TEST that ffffffff reenables BBC access");
spi_d <= 32\'hffffffff;
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
@(posedge clk);
`assert(dut.allowing_bbc_access == 1\'b1, "FAIL: 32 1\'s didn\'t reenable bbc access");
$display("\
TEST that we can write to the flash (51234)");
// message format for a WRITE: 17 address bits, rnw, 8 data bits, 6 zeros (32 bits total)
// with the write happening during the six zeros
spi_d <= {19\'b1010001001000110100, 1\'b0, 8\'b10001001, 4\'b0000};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
`assert(dut.allowing_bbc_access == 1\'b0, "FAIL: write operation unlocked bbc access");
$display("\
TEST that we can read from the flash (70f0f)");
// message format for a READ: 17 address bits, rnw, 14 zeros (32 bits total)
// with the data byte returned in the final 8 bits
spi_d <= {19\'b1110000111100001111, 1\'b1, 12\'b0};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
`assert(dut.allowing_bbc_access == 1\'b0, "FAIL: write operation unlocked bbc access");
$display("\
TEST that the unlock process appears correct");
spi_d <= {19\'h5555, 1\'b0, 8\'hAA, 4\'b0};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
spi_d <= {19\'h2AAA, 1\'b0, 8\'h55, 4\'b0};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
spi_d <= {19\'h5555, 1\'b0, 8\'h90, 4\'b0};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
spi_d <= {19\'h0, 1\'b1, 12\'b0};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
spi_d <= {19\'h1, 1\'b1, 12\'b0};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
spi_d <= {19\'h5555, 1\'b0, 8\'hF0, 4\'b0};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
$display("^^^ expect write 5555, write 2AAA, write 5555, read 0, read 1, write 5555");
// finish off
$display("running out the clock");
repeat(1000) @(posedge clk);
$display("PASS");
$finish;
end
endmodule
|
// Copyright 2018 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// Simple send-only UART
module uart(
input wire clock, // main clock
output reg txd = 1\'b1,
input wire [23:0] tx_data,
output reg tx_empty = 1\'b1, // \'1\' when tx_data can take a new byte
input wire transmit // pulse \'1\' when tx_data is valid
);
// clock divider to get baud rate. 82M / 115.2k = 712, giving 115.169 kb/s
parameter divide_count = 712;
// clock divider, assuming divide_count <= 1023
reg [9:0] divider = 0;
// shift register -- (start bit + 8 data bits + 1 stop bit) x 3 bytes
reg [29:0] shifter;
// how many bits to shift -- counts down from 30
reg [4:0] shift_count = 0;
always @(posedge clock) begin
// trying making this synchronous to debug missing transfers
// that could possibly be to do with the fifo in elk_interface...
// previously this was:
// assign tx_empty = (shift_count == 0) ? 1\'b1 : 1\'b0;
tx_empty = (shift_count == 0) ? 1\'b1 : 1\'b0;
// note that we can get slightly lower latency by setting this inside the loop that
// decrements shift_count, but that only happens on divider expiry and this happens
// every clock, so having it out here only slows it down 12 ns!
// accept a new byte to send
if (tx_empty == 1\'b1 && transmit == 1\'b1) begin
$display("accept new byte from tx_data");
// shifter <= {tx_data, 1\'b0}; // 8-bit
shifter <= {1\'b1, tx_data[23:16], 1\'b0, 1\'b1, tx_data[15:8], 1\'b0, 1\'b1, tx_data[7:0], 1\'b0}; // 24-bit
shift_count <= 31;
tx_empty <= 1\'b0;
end
// divider divides clock down to the serial bit rate (x 4 for reception?)
if (divider == divide_count) begin
divider <= 1;
// transmit a bit on divider expiry
if (shift_count != 0) begin
txd <= shifter[0];
// shift right
shifter <= {1\'b1, shifter[29:1]};
shift_count <= shift_count - 5\'d1;
end
end else begin
divider <= divider + 10\'d1;
end
end
endmodule
|
module internal_osc (
\toscena,
\tclkout);\t
\tinput\t\toscena;
\toutput\t\tclkout;
endmodule
|
// Copyright 2018 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// Verilog implementation of the Econet wire protocol.
// This is traditionally implemented using a MC68B54 chip:
// https://www.heyrick.co.uk/econet/mc6854fixed.pdf
// All Econet transactions use a \'four way handshake\':
//
// Scout frame:
// A sends: <flag> <B> <B> <A> <A> <ctrl> <port> <CRC> <CRC> <flag>
//
// Ack frame:
// B sends: <flag> <flag> <flag> ... (while busy)
// then: <flag> <A> <A> <B> <B> <CRC> <CRC> <flag>
//
// Data frame:
// A sends: <flag> <B> <B> <A> <A> <data...> <CRC> <CRC> <flag>
//
// Second ack frame:
// B sends: <flag> <A> <A> <B> <B> <CRC> <CRC> <flag>
// Bytes are sent LSB-first.
// Zero insertion/deletion: after transmitting 11111, a zero is inserted.
// After receiving 11111, a zero is deleted.
// 01111110 = flag
// 1111111 = abort (and line idles at 1)
// We communicate with the MCU over a synchronous serial interface, which in
// practice is half-duplex because there\'s no need to transmit information in
// the opposite direction from the Econet line.
// mcu_is_transmitting line selects the direction. When it transitions,
// everything gets reset.
// Right now this uses 64/72 MCs in an XC9572XL device.
module econet(
// to MCU
input wire clock_24m, // 24 MHz serial clock
output reg serial_cpld_to_mcu = 1\'b1, // USRT txd (connect to MCU\'s rxd)
input wire serial_mcu_to_cpld, // USRT rxd (connect to MCU\'s txd)
input wire mcu_is_transmitting, // direction select for the USRT; 1=mcu transmitting, 0 = cpld can transmit
output reg outputting_frame = 1\'b0, // 1 when we\'re sending a frame, 0 when idle or underrun
output wire serial_buffer_empty, // 1 when the MCU can send a new byte
input wire drive_econet_clock, // 1 when the MCU wants us to drive econet_clock_D with econet_clock_from_mcu
input wire econet_clock_from_mcu, // clock signal from MCU to copy to econet_clock_D
// to sn65c1168 dual differential transceiver
input wire econet_data_R, // received data
output wire econet_data_D, // transmitted data
output wire econet_data_DE, // 1 to transmit data, 0 otherwise
input wire econet_clock_R, // received clock
output wire econet_clock_D, // transmitted clock
output wire econet_clock_DE, // 1 to transmit clock, 0 otherwise
// to collision detect circuit
input wire collision_detect,
// Econet module pins, left to right on bottom of board
// These are currently used to output debug signals
input wire nNETINT,
input wire RnW,
input wire nADLC,
input wire PHI2,
input wire A0,
input wire A1,
output wire [7:0] D, // D0..D7 from left to right
output wire nRESET,
// ... followed by GND, and 5V is in the bottom right corner
// Dummy inputs for unused pins that connect to the MCU
input wire PA18,
input wire PA19,
input wire PA22,
input wire PA23
);
// So... how should this be implemented in the CPLD? Matching the input for
// the \'flag\' and \'abort\' codes is fairly straightforward.
// --- INPUT SYNC ---
reg [2:0] econet_clock_sync = 3\'b0;
reg [2:0] econet_data_sync = 3\'b0;
reg [2:0] mcu_is_transmitting_sync = 3\'b0;
// --- SERIAL PORT ---
reg [9:0] serial_shifter = 10\'b1111111111; // Start bit + 9 data bits
reg [3:0] serial_bit_count = 4\'b0; // Send/receive countdown from 11 (start + 9 + stop)
reg serial_input_buffer_full = 1\'b0;
assign serial_buffer_empty = !serial_input_buffer_full && (serial_bit_count == 0);
// --- ECONET ---
// The ATSAMD21 USRT supports 9-bit words, so the CPLD can send 9\'b0xxxxxxxx
// for a data word and 9\'b1xxxxxxxx for anything else (9\'b101111110 for a
// flag, 9\'b1xxxxxxxx for an abort or any garbage). When the MCU wants to
// send a flag, it can send 9\'b101111110 ("send raw 01111110") and when it
// wants to send data it can send 9\'b011111111 (which results in 111110111
// actually getting sent).
// Implement bit stuffing by generally thinking in bytes but having a \'raw\'
// flag that is sent as a 9th bit from the MCU.
reg [2:0] econet_bit_count = 0; // Bit # we\'re currently sending or receiving
reg [2:0] econet_ones_count = 0; // # of ones seen in a row (0-7)
reg [7:0] econet_shifter = 0; // 8-bit output shift register
reg econet_output_raw = 1\'b0; // If 1, don\'t bit stuff
reg econet_transmitting = 1\'b0; // Flag to say we\'re currently outputting from the shift register
reg econet_initiate_abort = 1\'b0; // Something went wrong: send an abort (raw 0xFF)
wire econet_clock_out;
reg econet_data_out = 1\'b1; // Passed through to econet_data_D
// rev1 PCB is buggy and has data input and clock input and output inverted.
// (Data output is the only correct one.)
reg buggy_rev1_pcb = 1\'b1;
assign econet_data_DE = outputting_frame;
assign econet_data_D = econet_data_out;
assign econet_clock_DE = drive_econet_clock;
assign econet_clock_out = econet_clock_from_mcu;
assign econet_clock_D = econet_clock_out ^ buggy_rev1_pcb;
wire econet_clock;
assign econet_clock = drive_econet_clock ? econet_clock_from_mcu : (econet_clock_R ^ buggy_rev1_pcb);
// A bunch of debug outputs using the Econet module pins along the bottom of the board
assign nRESET = mcu_is_transmitting_sync[2]; //DEBUG
assign D[7] = serial_mcu_to_cpld; //DEBUG
assign D[6] = serial_cpld_to_mcu; //serial_buffer_empty; //DEBUG
assign D[5] = serial_input_buffer_full; //DEBUG
assign D[4] = econet_initiate_abort; //DEBUG
assign D[3] = econet_transmitting; //DEBUG
assign D[2] = outputting_frame; //DEBUG
always @(negedge clock_24m) begin
// FALLING edge of serial clock: update value on serial_cpld_to_mcu
serial_cpld_to_mcu <= mcu_is_transmitting_sync[2] ? 1\'b1 : serial_shifter[0];
// if (!mcu_is_transmitting && serial_bit_count != 0) $display("outputting bit to serial port: %b", serial_shifter[0]);
end
always @(posedge clock_24m) begin
// RISING edge of serial clock: sample value on serial_mcu_to_cpld
// To save on CPLD space, the entire system is half-duplex, driven by the
// mcu_is_transmitting line. When this line changes, the whole system is
// reset, throwing away any half-transmitted or half-received data.
// Synchronize signals from the Econet line. tRDS = 50ns and tRDH = 60ns,
// and our clock period is 42ns, so we\'ll have a tight enough sample.
econet_clock_sync <= {econet_clock_sync[1:0], econet_clock};
econet_data_sync <= {econet_data_sync[1:0], (econet_data_R ^ buggy_rev1_pcb)};
mcu_is_transmitting_sync <= {mcu_is_transmitting_sync[1:0], mcu_is_transmitting};
if (mcu_is_transmitting_sync[2] != mcu_is_transmitting_sync[1]) begin // DIRECTION CHANGE
serial_bit_count <= 0;
serial_input_buffer_full <= 1\'b0;
serial_shifter[0] <= 1\'b1;
econet_initiate_abort <= 1\'b0;
econet_transmitting <= 1\'b0;
econet_bit_count <= 0;
econet_ones_count <= 7;
end else if (mcu_is_transmitting_sync[2] == 1\'b1) begin // RECEIVE FROM MCU, TRANSMIT TO ECONET
// TODO figure out if we need to synchronize mcu_is_transmitting, or
// if it\'s already synchronous w.r.t the USRT clock
// SERIAL PORT RECEIVER
if (serial_bit_count == 0) begin
if (serial_mcu_to_cpld == 1\'b0) begin
// Received a start bit; start a transfer
serial_bit_count <= 10;
end
end else if (serial_bit_count == 1) begin
// Receiving a stop bit
if (serial_mcu_to_cpld == 1\'b1) begin
// Received data!
if (serial_input_buffer_full == 1\'b1) begin
// Buffer overrun; abort the frame.
econet_initiate_abort <= 1\'b1;
end else begin
serial_input_buffer_full <= 1\'b1;
end
end else begin
// Frame error; ignore byte and crash
//TODO
end
serial_bit_count <= 0;
end else begin
// Receiving 9 bits from the serial port, LSB-first
serial_shifter <= {serial_mcu_to_cpld, serial_shifter[8:1]};
serial_bit_count <= serial_bit_count - 1;
end
// COPY FROM SERIAL PORT TO ECONET REGISTER
// Push a byte into the output shift register if necessary
if (econet_transmitting == 1\'b0) begin
if (econet_initiate_abort == 1\'b1) begin
// We\'re sending an abort, probably because we got a buffer
// overrun (on receiption). This will cancel the current frame.
// If we get a buffer underrun on transmission, we probably
// just bomb out and let the line idle state abort our frame.
serial_input_buffer_full <= 1\'b0;
outputting_frame <= 1\'b1;
econet_transmitting <= 1\'b1;
econet_output_raw <= 1\'b1;
econet_shifter <= 8\'b11111111;
econet_bit_count <= 3\'b0;
end else if (serial_input_buffer_full == 1\'b1) begin
// We\'ve received a byte from the MCU and want to transmit it.
// Make room for the next byte from the MCU.
serial_input_buffer_full <= 1\'b0;
// When we\'re not transmitting, we ignore anything without
// the \'raw\' byte.
if (serial_shifter[8] == 1\'b1) begin
// new frames always start with a raw (flag) byte
outputting_frame <= 1\'b1;
end
econet_transmitting <= 1\'b1;
// 0x1XX = 8 raw bits; 0x0XX = 8 bits with zero stuffing
econet_output_raw <= serial_shifter[8];
econet_shifter <= serial_shifter[7:0];
econet_bit_count <= 3\'b0;
end
end
// ECONET TRANSMITTER
if (econet_clock_sync[2] == 1\'b1 && econet_clock_sync[1] == 1\'b0) begin
// FALLING ECONET CLOCK EDGE: FLIP OUTPUT
if (outputting_frame == 1\'b1) begin
if (econet_transmitting == 1\'b0) begin
// Buffer underrun: we\'re in a frame and it\'s time to output a bit, but we have nothing
outputting_frame <= 1\'b0;
// Reset line to \'1\' when idling, so we don\'t get a glitch when we start driving again
econet_data_out <= 1\'b1;
end
end
if (econet_transmitting == 1\'b0) begin
// econet_data_D should idle high
// econet_data_out <= 1\'b1;
end else begin
// Transmit even if we\'re not inside a frame, to avoid deadlocks
// shift out a bit (LSB first) and increment/zero ones count as necessary
econet_data_out <= econet_shifter[0];
// TODO verify that this always sends a 0 after five 1 bits,
// even at the end of a transmission (i.e. verify that sending
// 00011111 then a flag results in 000111110 01111110).
// See: https://stardot.org.uk/forums/viewtopic.php?p=130412#p130412
if (econet_output_raw == 1\'b0 && econet_ones_count == 4 && econet_shifter[0] == 1\'b1) begin
// set next bit to 0 for stuffing
econet_ones_count <= 0;
econet_shifter[0] <= 1\'b0;
end else begin
if (econet_shifter[0] == 1\'b1) begin
econet_ones_count <= econet_ones_count + 1;
end else begin
econet_ones_count <= 0;
end
econet_shifter <= {1\'b1, econet_shifter[7:1]};
econet_bit_count <= econet_bit_count + 1;
end
// econet_bit_count counts from 0-7 as the 8 bits are shifted out.
if (econet_bit_count == 7) begin
// we just finished transmitting a byte. signal to controller
// that we need our shifter refilled.
econet_transmitting <= 1\'b0;
end
end
end
end else begin // mcu_is_transmitting == 1\'b0; TRANSMIT TO MCU, RECEIVE FROM ECONET
// SERIAL PORT TRANSMITTER
if (serial_bit_count != 0) begin
// --- MCU is receiving; we can drive serial_cpld_to_mcu ---
serial_shifter <= {1\'b1, serial_shifter[9:1]};
serial_bit_count <= serial_bit_count - 1;
end
// ECONET RECEIVER
if (econet_clock_sync[2] == 1\'b0 && econet_clock_sync[1] == 1\'b1) begin
// RISING ECONET CLOCK EDGE: SAMPLE INPUT
if (econet_ones_count == 7 && econet_data_sync[2] == 1\'b1) begin
// Stay in reset
end else if (econet_ones_count == 6 && econet_data_sync[2] == 1\'b1) begin
// Reset!
econet_ones_count <= econet_ones_count + 1;
econet_bit_count <= 0;
end else if (econet_ones_count == 6 && econet_data_sync[2] == 1\'b0) begin
// Just received a flag
// Probably safe to assume this will never cause a serial overrun, as this would require an Econet line rate over 2MHz.
$display("received flag: put 1+%02x (1+%b) in serial shifter", {econet_shifter[6:0], 1\'b0}, {econet_shifter[6:0], 1\'b0});
serial_shifter <= {
1\'b1, // it\'s a flag
{econet_data_sync[2],
econet_shifter[0],
econet_shifter[1],
econet_shifter[2],
econet_shifter[3],
econet_shifter[4],
econet_shifter[5],
econet_shifter[6]}, // flag byte
1\'b0 // start bit
};
serial_bit_count <= 11;
econet_ones_count <= 1\'b0;
econet_bit_count <= 0;
end else if (econet_ones_count == 5 && econet_data_sync[2] == 1\'b0) begin
// Just read a stuffed zero
// Reset ones count and skip this bit
econet_ones_count <= 0;
end else begin
// Read a normal bit
// Increment or reset ones count
if (econet_data_sync[2] == 1\'b1) begin
econet_ones_count <= econet_ones_count + 1;
end else begin
econet_ones_count <= 0;
end
// Shift it into the receive register
econet_shifter <= {econet_shifter[6:0], econet_data_sync[2]};
// $display("econet_shifter about to be %b", {econet_shifter[6:0], econet_data_sync[2]});
econet_bit_count <= econet_bit_count + 1;
if (econet_bit_count == 7) begin
// Probably safe to assume this will never cause a serial overrun, as this would require an Econet line rate over 2MHz.
$display("received byte: put 0+%02x (0+%b) in serial shifter", {econet_shifter[6:0], econet_data_sync[2]}, {econet_shifter[6:0], econet_data_sync[2]});
serial_shifter <= {
1\'b0, // it\'s data (not a flag)
{econet_data_sync[2],
econet_shifter[0],
econet_shifter[1],
econet_shifter[2],
econet_shifter[3],
econet_shifter[4],
econet_shifter[5],
econet_shifter[6]}, // data byte
1\'b0 // start bit
};
serial_bit_count <= 11;
end
end
end // rising econet_clock edge
end // !mcu_is_transmitting
end
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
////////////////////////////////////////////////////////////////////
//
// ALTERA_ONCHIP_FLASH_AVMM_CSR_CONTROLLER
//
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
////////////////////////////////////////////////////////////////////
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
`timescale 1 ps / 1 ps
module altera_onchip_flash_avmm_csr_controller (
\t// To/From System
\tclock,
\treset_n,
\t// To/From Avalon_MM csr slave interface
\tavmm_read,
\tavmm_write,
\tavmm_addr,
\tavmm_writedata,
\tavmm_readdata,
\t
\t// To/From Avalon_MM data slave interface
\tcsr_status,
\tcsr_control
);
\tparameter AVMM_CSR_DATA_WIDTH = 32;
\tlocalparam [1:0]\tERASE_ST_IDLE = 0,
\t\t\t\t\t\tERASE_ST_PENDING = 1,
\t\t\t\t\t\tERASE_ST_BUSY = 2;
\tlocalparam [1:0]\tSTATUS_IDLE = 0,
\t\t\t\t\t\tSTATUS_BUSY_ERASE = 1,
\t\t\t\t\t\tSTATUS_BUSY_WRITE = 2,
\t\t\t\t\t\tSTATUS_BUSY_READ = 3;
\t// To/From System
\tinput clock;
\tinput reset_n;
\t// To/From Avalon_MM csr slave interface
\tinput avmm_read;
\tinput avmm_write;
\tinput avmm_addr;
\tinput [AVMM_CSR_DATA_WIDTH-1:0] avmm_writedata;
\toutput [AVMM_CSR_DATA_WIDTH-1:0] avmm_readdata;
\t
\t// To/From Avalon_MM data slave interface
\tinput [9:0] csr_status;
\toutput [31:0] csr_control;
\t
\treg [22:0] csr_sector_page_erase_addr_reg;
\treg [4:0] csr_wp_mode;
\treg [1:0] csr_erase_state;
\treg csr_control_access;
\treg reset_n_reg1;
\treg reset_n_reg2;
\twire reset_n_w;
\twire is_idle;
\twire is_erase_busy;
\twire valid_csr_erase_addr;
\twire valid_csr_write;
\twire [31:0] csr_control_signal;
\twire [22:0] csr_erase_addr;
\tassign is_idle = (csr_status[1:0] == STATUS_IDLE);
\tassign is_erase_busy = (csr_status[1:0] == STATUS_BUSY_ERASE);
\tassign csr_erase_addr = avmm_writedata[22:0];
\tassign valid_csr_erase_addr = (csr_erase_addr != {(23){1'b1}});
\tassign valid_csr_write = (avmm_write & avmm_addr);\t\t
\tassign csr_control_signal = { csr_erase_state, {(2){1'b1}}, csr_wp_mode, csr_sector_page_erase_addr_reg };
\tassign csr_control = csr_control_signal;
\tassign avmm_readdata = (csr_control_access) ? csr_control_signal : { {(22){1'b1}}, csr_status[9:0] };
\t// avoid async reset removal issue
\tassign reset_n_w = reset_n_reg2;
\t
\t// Initiate register value for simulation. The initiate value can't be xx
\tinitial begin
\t\tcsr_sector_page_erase_addr_reg <= {(23){1'b1}};
\t\tcsr_wp_mode = {(5){1'b1}};
\t\tcsr_erase_state = ERASE_ST_IDLE;
\t\tcsr_control_access = 1'b0;
\t\treset_n_reg1 = 1'b0;
\t\treset_n_reg2 = 1'b0;
\tend
\t// -------------------------------------------------------------------
\t// Avoid async reset removal issue
\t// -------------------------------------------------------------------
\talways @ (negedge reset_n or posedge clock) begin
\t\tif (~reset_n) begin
\t\t\t{reset_n_reg2, reset_n_reg1} <= 2'b0;
\t\tend
\t\telse begin
\t\t\t{reset_n_reg2, reset_n_reg1} <= {reset_n_reg1, 1'b1};
\t\tend
\tend
\t
\t// -------------------------------------------------------------------
\t// Avalon_MM read/write
\t// -------------------------------------------------------------------\t\t
\talways @ (posedge clock) begin
\t\t
\t\t// synchronous reset
\t\tif (~reset_n_w) begin
\t\t\t// reset all register
\t\t\tcsr_sector_page_erase_addr_reg <= {(23){1'b1}};
\t\t\tcsr_wp_mode <= {(5){1'b1}};
\t\t\tcsr_erase_state <= ERASE_ST_IDLE;
\t\t\tcsr_control_access <= 1'b0;
\t\tend
\t\telse begin
\t\t\t// store read address
\t\t\tif (avmm_read) begin
\t\t\t\tcsr_control_access <= avmm_addr;
\t\t\tend
\t\t
\t\t\t// write control register
\t\t\tif (valid_csr_write) begin
\t\t\t\tcsr_wp_mode <= avmm_writedata[27:23];
\t\t\t\tif (is_idle) begin
\t\t\t\t\tcsr_sector_page_erase_addr_reg <= avmm_writedata[22:0];
\t\t\t\tend
\t\t\tend
\t\t
\t\t\t// erase control fsm
\t\t\tcase (csr_erase_state)
\t\t\t\tERASE_ST_IDLE:
\t\t\t\t\tif (is_idle && valid_csr_write && valid_csr_erase_addr) begin
\t\t\t\t\t\tcsr_erase_state <= ERASE_ST_PENDING;
\t\t\t\t\tend
\t\t\t\tERASE_ST_PENDING:
\t\t\t\t\tif (is_erase_busy) begin
\t\t\t\t\t\tcsr_erase_state <= ERASE_ST_BUSY;
\t\t\t\t\tend
\t\t\t\tERASE_ST_BUSY:
\t\t\t\t\tif (is_idle) begin
\t\t\t\t\t\tcsr_erase_state <= ERASE_ST_IDLE;
\t\t\t\t\tend
\t\t\t\tdefault: begin
\t\t\t\t\tcsr_erase_state <= ERASE_ST_IDLE;
\t\t\t\tend
\t\t\tendcase
\t\tend
\t\t
\tend
endmodule
|
// Copyright 2018 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`timescale 1ns/100ps
`include "uart_rx.v"
`include "uart.v"
module uart_tb;
integer i;
// transmit side
reg clk, transmit;
reg [23:0] tx_data;
wire txd, tx_empty;
// receive side
wire [7:0] rx_data;
wire rx_full;
reg rx_ack = 1; // insta-ack everything
// transmit uart to test my receiver
uart #(
.divide_count(20)
) test_uart(
.clock(clk),
.txd(txd),
.tx_data(tx_data),
.tx_empty(tx_empty),
.transmit(transmit)
);
uart_rx #(
.divide_count(5)
) test_uart_rx(
.clock(clk),
.rxd(txd), // attached to transmitter
.rx_data(rx_data),
.rx_full(rx_full),
.ack(rx_ack)
);
initial begin
clk = 1\'b0;
forever #9 clk = ~clk;
end
initial begin
$display("running uart_tb");
$dumpfile("uart_rx_tb.vcd");
$dumpvars(0, uart_tb);
$display("start");
transmit = 0;
repeat(8) @(posedge clk);
$display("transmit");
tx_data = 24\'b111111110000000010110010;
transmit = 1;
@(posedge clk);
#1 transmit = 0;
$display("observe");
@(posedge tx_empty);
tx_data = 8\'h00;
transmit = 1;
@(posedge clk);
#1 transmit = 0;
@(posedge tx_empty);
repeat(100) @(posedge clk);
$display("stop now");
$finish;
end
endmodule
|
`timescale 1ns/100ps
`include "econet.v"
`define assert(condition, message) if(!(condition)) begin $display(message); $finish(1); end
module econet_tb;
reg clk;
wire mcu_txd;
reg mcu_rxd = 1\'b1;
reg mcu_is_transmitting;
wire outputting_frame, serial_buffer_empty;
wire econet_data_R, econet_data_D, econet_clock_D;
wire econet_clock_R, econet_data_DE, econet_clock_DE;
econet test_econet(
.clock_24m(clk),
.serial_cpld_to_mcu(mcu_txd),
.serial_mcu_to_cpld(mcu_rxd),
.mcu_is_transmitting(mcu_is_transmitting),
.outputting_frame(outputting_frame),
.serial_buffer_empty(serial_buffer_empty),
.drive_econet_clock(1\'b0),
.econet_data_R(econet_data_R),
.econet_data_D(econet_data_D),
.econet_data_DE(econet_data_DE),
.econet_clock_R(econet_clock_R),
.econet_clock_D(econet_clock_D),
.econet_clock_DE(econet_clock_DE)
);
reg econet_data_R_pre = 1\'b1, econet_clock_R_pre = 1\'b1;
assign econet_clock_R = econet_clock_R_pre ^ test_econet.buggy_rev1_pcb;
assign econet_data_R = econet_data_R_pre ^ test_econet.buggy_rev1_pcb;
initial begin
// 24 MHz clock, with 1/48 us = #10, so #480 = 1us
clk = 1\'b0;
forever #10 clk = ~clk;
end
initial begin
econet_clock_R_pre = 1\'b1;
// 1us up, 4us down
forever begin
#480 econet_clock_R_pre = 1\'b0;
#1920 econet_clock_R_pre = 1\'b1;
end
end
// econet
reg [56:0] test_econet_receive_shifter;
reg [7:0] test_bits_to_shift_into_econet = 0;
// write to econet line on falling clock edge
always @(negedge econet_clock_R_pre) begin
if (test_bits_to_shift_into_econet != 0) begin
econet_data_R_pre <= test_econet_receive_shifter[56];
test_econet_receive_shifter <= {test_econet_receive_shifter[55:0], 1\'b1};
test_bits_to_shift_into_econet <= test_bits_to_shift_into_econet - 1;
end
end
// serial port (MCU side)
reg [9:0] test_serial_output_buffer = 10\'b1111111111;
reg [8:0] test_serial_send_byte = 0;
reg [3:0] test_serial_output_bit = 0; // counts down from 10
reg test_serial_output_start = 1\'b0; // set high to trigger a serial transmission
wire test_serial_output_empty;
assign test_serial_output_empty = (test_serial_output_bit == 0);
reg [3:0] test_serial_input_bit = 0;
reg [8:0] test_serial_input_buffer = 0, test_serial_received_byte = 0;
reg test_serial_input_full = 1\'b0, test_serial_input_overrun = 1\'b0;
always @(posedge clk) begin
if (test_serial_input_bit == 0) begin
// waiting for start bit
if (mcu_txd == 1\'b0) begin
// got start bit
test_serial_input_bit <= 1;
end
end else begin
if (test_serial_input_bit == 10) begin
if (mcu_txd == 1\'b1) begin
// Received byte
$display("Byte received on serial port: $%03x (%b)", test_serial_input_buffer, test_serial_input_buffer);
if (test_serial_input_full == 1\'b1) begin
test_serial_input_overrun <= 1\'b1;
end else begin
test_serial_input_full <= 1\'b1;
test_serial_received_byte <= test_serial_input_buffer;
end
end else begin
$display("FRAMING ERROR receiving byte from serial port");
end
test_serial_input_bit <= 0;
end else begin
// Shift value on mcu_txd in from left
test_serial_input_buffer <= {mcu_txd, test_serial_input_buffer[8:1]};
// $display("shift bit %b into test_serial_input_buffer; previously %b", mcu_txd, test_serial_input_buffer);
// bits 1-9 = data bits
test_serial_input_bit <= test_serial_input_bit + 1;
end
end
end
always @(negedge clk) begin
if (test_serial_output_start == 1\'b1 && test_serial_output_empty == 1\'b1) begin
// Kick off new transmission
$display("[serial] starting new transmission");
test_serial_output_buffer <= {test_serial_send_byte, 1\'b0};
test_serial_output_bit <= 10;
end else begin
// Change value on mcu_rxd and shift output buffer right one
mcu_rxd <= test_serial_output_buffer[0];
test_serial_output_buffer <= {1\'b1, test_serial_output_buffer[9:1]};
// Track if we\'re in a transmission or not
if (test_serial_output_bit != 0) begin
test_serial_output_bit <= test_serial_output_bit - 1;
if (test_serial_output_bit == 1) begin
$display("[serial] byte transmitted");
end
end
end
end
initial begin
$display("econet_tb");
$dumpfile("econet_tb.vcd");
$dumpvars(0, econet_tb);
$display("--- TESTING SENDING DATA TO ECONET ---");
// enable tx
#100 mcu_is_transmitting = 1\'b1;
// send flag
$display("send flag 01111110");
wait (test_serial_output_empty == 1\'b1);
#1 test_serial_send_byte = 10\'b101111110;
test_serial_output_start <= 1\'b1;
wait (test_serial_output_empty == 1\'b0);
#1 test_serial_output_start <= 1\'b0;
$display("wait for flag request to finish going out over the serial port");
wait (test_serial_output_empty == 1\'b1);
$display("wait for serial port to be ready to receive another byte");
wait (serial_buffer_empty == 1\'b1);
// send byte
$display("send byte 011111(0)10");
#1 test_serial_send_byte = 10\'b001111110;
test_serial_output_start <= 1\'b1;
wait (test_serial_output_empty == 1\'b0);
#1 test_serial_output_start <= 1\'b0;
wait (test_serial_output_empty == 1\'b1);
wait (serial_buffer_empty == 1\'b1);
// send byte
$display("send byte 01000010");
#1 test_serial_send_byte = 10\'h42;
test_serial_output_start <= 1\'b1;
wait (test_serial_output_empty == 1\'b0);
#1 test_serial_output_start <= 1\'b0;
wait (test_serial_output_empty == 1\'b1);
wait (serial_buffer_empty == 1\'b1);
// send byte
$display("send byte 11111(0)111");
#1 test_serial_send_byte = 10\'hff;
test_serial_output_start <= 1\'b1;
wait (test_serial_output_empty == 1\'b0);
#1 test_serial_output_start <= 1\'b0;
wait (test_serial_output_empty == 1\'b1);
wait (serial_buffer_empty == 1\'b1);
// send flag
$display("send flag 01111110");
#1 test_serial_send_byte = 10\'b101111110;
test_serial_output_start <= 1\'b1;
wait (test_serial_output_empty == 1\'b0);
#1 test_serial_output_start <= 1\'b0;
wait (test_serial_output_empty == 1\'b1);
wait (serial_buffer_empty == 1\'b1);
// disable tx
wait (outputting_frame == 1\'b0);
mcu_is_transmitting = 1\'b0;
$display("done transmitting frame");
mcu_is_transmitting = 1\'b0;
// test receiving a frame from the econet
// enable rx
mcu_is_transmitting = 1\'b0;
#10000 $display("--- TESTING RECEIVING DATA FROM ECONET ---");
`assert(mcu_txd == 1\'b1, "FAIL: mcu_txd should be idle (1) when not transmitting");
$display("start sending test data on econet_clock_R");
test_econet_receive_shifter = {
8\'b01111110, // initial flag (17e)
8\'b10101010, // aa
8\'b01010101, // 55
8\'b10101010, // aa
9\'b111110111, // ff
8\'b00000000, // 00
8\'b01111110 // final flag (17e)
};
wait (econet_clock_R == 1\'b0);
test_bits_to_shift_into_econet = 64;
wait (test_serial_input_full == 1\'b1);
`assert(test_serial_input_buffer == 9\'h17e, "FAIL: expected 17e");
test_serial_input_full = 1\'b0;
wait (test_serial_input_full == 1\'b1);
`assert(test_serial_input_buffer == 9\'haa, "FAIL: expected aa");
test_serial_input_full = 1\'b0;
wait (test_serial_input_full == 1\'b1);
`assert(test_serial_input_buffer == 9\'h55, "FAIL: expected 55");
test_serial_input_full = 1\'b0;
wait (test_serial_input_full == 1\'b1);
`assert(test_serial_input_buffer == 9\'haa, "FAIL: expected aa");
test_serial_input_full = 1\'b0;
wait (test_serial_input_full == 1\'b1);
`assert(test_serial_input_buffer == 9\'hff, "FAIL: expected ff");
test_serial_input_full = 1\'b0;
wait (test_serial_input_full == 1\'b1);
`assert(test_serial_input_buffer == 9\'h0, "FAIL: expected 00");
test_serial_input_full = 1\'b0;
wait (test_serial_input_full == 1\'b1);
`assert(test_serial_input_buffer == 9\'h17e, "FAIL: expected 17e");
test_serial_input_full = 1\'b0;
wait (test_bits_to_shift_into_econet == 0);
$display("TODO test reception of bad frame");
$display("TODO test turnaround back to sending");
$display("TODO test bad serial input");
$display("econet_test done");
#1000 $finish;
end
// Failsafe
initial begin
#1000000 $display("TIMEOUT -- EXITING");
$finish;
end
endmodule
|
// Copyright 2018 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// Receive-only UART
// IDLE state -- rxd high
// READING state -- clocking in bits
// STOP_BIT state -- waiting for stop bit, then sending the data out rx_data
module uart_rx(
input wire clock, // main clock
input wire rxd, // rxd pin
output reg [7:0] rx_data, // received data output register
output reg rx_full = 1\'b0, // \'1\' when rx_data is valid
input wire ack // pulse \'1\' to ack rx_data and allow a new byte
);
// clock divider to get baud rate x 4. 82M / 115.2k / 4 = 178, giving 115.169 kb/s
parameter divide_count = 178;
reg [9:0] divider = 0; // 0-1023
// state machine
parameter IDLE = 0, READING = 1, STOP_BIT = 2;
reg [1:0] state = 0;
// input shift register
reg [7:0] shifter;
// how many bits to shift (0-7)
reg [2:0] shift_count;
// sync external rxd signal
reg [2:0] rxd_sync;
// timer to sample the bit right in the center (0-7)
reg [2:0] bit_timer;
always @(posedge clock) begin
if (ack == 1\'b1) begin
rx_full <= 1\'b0;
end
rxd_sync <= {rxd_sync[1:0], rxd};
// divider divides clock down to the serial bit rate (x 4 for reception)
if (state == IDLE) begin
// hold divider
divider = 3;
// look for a falling edge on rxd
if (rxd_sync[2] == 0) begin
bit_timer <= 3\'d5;
state <= READING;
shift_count <= 7;
end
end else begin // READING or STOP_BIT state
if (divider != divide_count) begin
divider <= divider + 10\'d1;
end else begin
// divider just hit its target -- reset it
divider <= 1;
if (bit_timer != 0) begin
bit_timer <= bit_timer - 3\'d1;
end else begin
// it\'s time to sample a bit on divider + bit_timer expiry
// uart is little-endian, so we shift in from the left.
if (state == STOP_BIT) begin
if (rxd_sync[2] == 1\'b1) begin
rx_full <= 1\'b1;
rx_data <= shifter;
end;
state <= IDLE;
end else begin
shifter <= {rxd_sync[2], shifter[7:1]};
if (shift_count == 0) begin
state <= STOP_BIT;
end else begin
shift_count <= shift_count - 3\'d1;
end
end
bit_timer <= 3;
end
end
if (divider == 0) begin
end
end
end
endmodule
|
// Copyright 2018 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
module master_updateable_megarom(
inout wire [7:0] D,
input wire [16:0] bbc_A,
output wire [18:0] flash_A,
output wire flash_nOE,
output wire flash_nWE,
input wire cpld_SCK_in,
// Clock output so we can throw it on a BUFG.
// TODO this doesn\'t seem to work. maybe the
// signal needs to be internally generated,
// as opposed to just a copy of cpld_SCK_in?
//output wire cpld_SCK,
input wire cpld_MOSI,
input wire cpld_SS,
output reg cpld_MISO,
input wire [1:0] cpld_JP
);
assign cpld_SCK = cpld_SCK_in;
// 1 when installed in a Master 128, 0 when installed in a Model B
reg installed_in_bbc_master = 1\'b0;
// flash bank to use for BBC reads
reg [1:0] flash_bank = 2\'b0;
// When installed in a Model B, this decodes A16 from cpld_JP
wire model_b_A16;
// We\'re always selected when installed as a Master 128 MOS ROM, but when
// installed in a Model B, this decodes /CE from cpld_JP
wire bbc_nCE;
// address value from SPI transaction
reg [18:0] spi_A = 19\'b0;
// data value from SPI transaction
reg [7:0] spi_D = 8\'b0;
// 1 to pass the bbc_A through to flash_A, 0 to use A instead
reg allowing_bbc_access_int = 1\'b1;
// overrideable version of the above
wire allowing_bbc_access;
// 1 to drive flash_nOE or flash_nWR
reg accessing_memory = 1\'b0;
wire reading_memory;
wire writing_memory;
// 1 for read (drive flash_nOE), 0 for write (drive flash_nWR)
reg rnw = 1\'b0;
// 1 to pass spi_D through to D
reg driving_bus = 1\'b0;
// counts up to 31
reg [4:0] spi_bit_count = 5\'b0;
// this is controllable for debugging:
assign allowing_bbc_access = allowing_bbc_access_int; // normal operation
// assign allowing_bbc_access = 1\'b0; // never allow bbc access, for debugging
// We\'re either passing bbc_A through to flash_A, with D tristated, or we\'re
// controlling both and ignoring bbc_A.
assign flash_A = (allowing_bbc_access == 1\'b1)
? (installed_in_bbc_master
? {flash_bank, bbc_A} // Master 128
: {flash_bank, model_b_A16, bbc_A[15:0]}) // Model B
: spi_A;
// when installed in a Model B, we need to decode A16 and nCE from cpld_JP.
assign model_b_A16 = cpld_JP[0];
assign bbc_nCE = installed_in_bbc_master
? 1\'b0 // Master 128
: (cpld_JP[0] && cpld_JP[1]); // Model B
// assert OE
assign reading_memory = accessing_memory && rnw;
assign flash_nOE = !((allowing_bbc_access && !bbc_nCE && !bbc_A[16]) // A16=nOE
|| reading_memory);
// assert WE and D when the BBC is disabled and we\'re doing a memory write
assign writing_memory = accessing_memory && !rnw;
assign flash_nWE = !(!allowing_bbc_access && writing_memory);
// drive D when writing
assign D = (allowing_bbc_access == 1\'b0 && (driving_bus == 1\'b1 && rnw == 1\'b0)) ? spi_D : 8\'bZZZZZZZZ;
always @(posedge cpld_SCK or posedge cpld_SS) begin
if (cpld_SS == 1\'b1) begin
accessing_memory <= 1\'b0;
driving_bus <= 1\'b0;
spi_bit_count <= 6\'b000000;
end else begin
// the master device should bring cpld_SS high between every transaction.
// SPI is big-endian; send the MSB first and clock into the LSB.
// to block out the BBC and enable flash access: send ffffff00. to reenable
// the BBC, send 32 bits of ones. the final bit sets \'allowing_bbc_access\'.
// message format for a WRITE that blocks the BBC after: 19 address bits,
// rnw, 8 data bits, 4 zeros, with the write happening during the six zeros.
// message format for a READ that blocks the BBC after: 19 address bits,
// rnw, 12 zeros, with the data byte returned in the final 8 bits.
// so if you want to do a single read and reenable BBC access afterward,
// send 19 address bits, then 1000000000001.
// the flash chip only needs a 40ns low pulse on /CE + /WE, and its read
// access time is 55-70ns. we hold /OE for reads or /WE for writes low for
// three SCK periods, so for a 70ns flash chip, the SPI clock period must be
// less than 42.8 MHz.
if (spi_bit_count < 19) begin
spi_A <= {spi_A[17:0], cpld_MOSI};
end else if (spi_bit_count == 19) begin
rnw <= cpld_MOSI;
// Disable BBC access if it\'s enabled. We do this here rather than just
// masking it with cpld_SS, so the board will run in ROM mode when the
// microcontroller is disconnected. If we got 19 clocks on cpld_SCK
// with cpld_SS=0, it\'s pretty safe to say that a microcontroller is
// indeed connected and active.
allowing_bbc_access_int <= 1\'b0;
end else if (rnw == 1\'b1) begin
// 0-18 address, 19 rnw, 20-23 access, 24-31 data out
if (spi_bit_count == 20) begin
// start read
accessing_memory <= 1\'b1;
end else if (spi_bit_count == 23) begin
// end read
accessing_memory <= 1\'b0;
spi_D <= D;
end else if (spi_bit_count >= 24) begin
spi_D <= {spi_D[6:0], 1\'b0};
end
end else if (rnw == 1\'b0) begin
// 0-18 address, 19 rnw, 20-27 data in, 28-31 access
if (spi_bit_count < 28) begin
spi_D <= {spi_D[6:0], cpld_MOSI};
driving_bus <= 1\'b1;
end
if (spi_bit_count == 28) begin
accessing_memory <= 1\'b1;
end
if (spi_bit_count == 30) begin
accessing_memory <= 1\'b0;
end
end
if (spi_bit_count == 31) begin
driving_bus <= 1\'b0;
allowing_bbc_access_int <= cpld_MOSI;
end
spi_bit_count <= spi_bit_count + 1;
end
end
always @(negedge cpld_SCK) begin
if (spi_bit_count < 19) begin
cpld_MISO <= spi_bit_count[0]; // should toggle and result in data & ffffe00 == 55554000
end else begin
cpld_MISO <= spi_D[7];
end
end
endmodule
|
// Copyright 2018 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`timescale 1ns/100ps
`include "uart.v"
module uart_tb;
reg clk, transmit;
reg [23:0] tx_data;
wire txd, tx_empty;
integer i;
// use a small clock divider for visibility
uart #(
.divide_count(5)
) test_uart(
.clock(clk),
.txd(txd),
.tx_data(tx_data),
.tx_empty(tx_empty),
.transmit(transmit)
);
initial begin
clk = 1\'b0;
forever #9 clk = ~clk;
end
initial begin
$display("running uart_tb");
$dumpfile("uart.vcd");
$dumpvars(0, uart_tb);
$display("start");
transmit = 0;
repeat(8) @(posedge clk);
$display("transmit");
tx_data = 24\'b111111110000000010110010;
transmit = 1;
@(posedge clk);
#1 transmit = 0;
$display("observe");
@(posedge tx_empty);
tx_data = 8\'h00;
transmit = 1;
@(posedge clk);
#1 transmit = 0;
@(posedge tx_empty);
repeat(8) @(posedge clk);
$display("stop now");
$finish;
end
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation\'s design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
////////////////////////////////////////////////////////////////////
//
// ALTERA_INT_OSC
//
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation\'s design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
////////////////////////////////////////////////////////////////////
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
`timescale 1 ps / 1 ps
module altera_int_osc
\t(
\tclkout,
\toscena);
\tparameter DEVICE_FAMILY = "MAX 10";
\tparameter DEVICE_ID = "08";
\tparameter CLOCK_FREQUENCY = "dummy";
\t
\toutput clkout;
\tinput oscena;
\t
\twire wire_clkout;
\t
\tassign clkout = wire_clkout;
\t\t
\t// -------------------------------------------------------------------
\t// Instantiate wysiwyg for chipidblock according to device family
\t// -------------------------------------------------------------------\t
\tgenerate
\t\tif (DEVICE_FAMILY == "MAX 10") begin
\t\t\tfiftyfivenm_oscillator # (\t//MAX 10
\t\t\t\t.device_id(DEVICE_ID),
\t\t\t\t.clock_frequency(CLOCK_FREQUENCY)
\t\t\t) oscillator_dut (
\t\t\t\t.clkout(wire_clkout),
\t\t\t\t.clkout1(),
\t\t\t\t.oscena(oscena));
\t\t\tend
\tendgenerate
\t
endmodule //altera_int_osc
//VALID FILE
|
\tinternal_osc u0 (
\t\t.oscena (<connected-to-oscena>), // oscena.oscena
\t\t.clkout (<connected-to-clkout>) // clkout.clk
\t);
|
module bus_scope_main(
\toutput wire [31:0] fx3_D
);
assign fx3_D = 32'bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ;
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation\'s design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
////////////////////////////////////////////////////////////////////
//
// ALTERA_ONCHIP_FLASH
//
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation\'s design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
////////////////////////////////////////////////////////////////////
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
`timescale 1 ps / 1 ps
module altera_onchip_flash (
\t// To/From System
\tclock,
\treset_n,
\t
\t// To/From Avalon_MM data slave interface
\tavmm_data_read,
\tavmm_data_write,
\tavmm_data_addr,
\tavmm_data_writedata,
\tavmm_data_burstcount,
\tavmm_data_waitrequest,
\tavmm_data_readdatavalid,
\tavmm_data_readdata,
\t
\t// To/From Avalon_MM csr slave interface
\tavmm_csr_read,
\tavmm_csr_write,
\tavmm_csr_addr,
\tavmm_csr_writedata,
\tavmm_csr_readdata
);
\tparameter DEVICE_FAMILY = "MAX 10";
\tparameter PART_NAME = "Unknown";
\tparameter IS_DUAL_BOOT = "False";
\tparameter IS_ERAM_SKIP = "False";
\tparameter IS_COMPRESSED_IMAGE = "False";
\tparameter INIT_FILENAME = "";
\t// simulation only start
\tparameter DEVICE_ID = "08";
\tparameter INIT_FILENAME_SIM = "";
\t// simulation only end
\tparameter PARALLEL_MODE = 0;
\tparameter READ_AND_WRITE_MODE = 0;
\tparameter WRAPPING_BURST_MODE = 0;
\t
\tparameter AVMM_CSR_DATA_WIDTH = 32;
\tparameter AVMM_DATA_DATA_WIDTH = 32;
\tparameter AVMM_DATA_ADDR_WIDTH = 20;
\tparameter AVMM_DATA_BURSTCOUNT_WIDTH = 13;
\tparameter FLASH_DATA_WIDTH = 32;
\tparameter FLASH_ADDR_WIDTH = 23;
\tparameter FLASH_SEQ_READ_DATA_COUNT = 2;\t//number of 32-bit data per sequential read. only need in parallel mode.
\tparameter FLASH_READ_CYCLE_MAX_INDEX = 3;\t//period to for each sequential read. only need in parallel mode.
\tparameter FLASH_ADDR_ALIGNMENT_BITS = 1; \t//number of last addr bits for alignment. only need in parallel mode.
\tparameter FLASH_RESET_CYCLE_MAX_INDEX = 28;\t//period that required by flash before back to idle for erase and program operation
\tparameter FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX = 112; //flash busy timeout period (960ns)
\tparameter FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX = 40603248; //erase timeout period (350ms)
\tparameter FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX = 35382; //write timeout period (305us)
\tparameter MIN_VALID_ADDR = 1;
\tparameter MAX_VALID_ADDR = 1;
\tparameter MIN_UFM_VALID_ADDR = 1;
\tparameter MAX_UFM_VALID_ADDR = 1;
\tparameter SECTOR1_START_ADDR = 1;
\tparameter SECTOR1_END_ADDR = 1;
\tparameter SECTOR2_START_ADDR = 1;
\tparameter SECTOR2_END_ADDR = 1;
\tparameter SECTOR3_START_ADDR = 1;
\tparameter SECTOR3_END_ADDR = 1;
\tparameter SECTOR4_START_ADDR = 1;
\tparameter SECTOR4_END_ADDR = 1;
\tparameter SECTOR5_START_ADDR = 1;
\tparameter SECTOR5_END_ADDR = 1;
\tparameter SECTOR_READ_PROTECTION_MODE = 5\'b11111;
\tparameter SECTOR1_MAP = 1;
\tparameter SECTOR2_MAP = 1;
\tparameter SECTOR3_MAP = 1;
\tparameter SECTOR4_MAP = 1;
\tparameter SECTOR5_MAP = 1;
\tparameter ADDR_RANGE1_END_ADDR = 1;
\tparameter ADDR_RANGE1_OFFSET = 1;
\tparameter ADDR_RANGE2_OFFSET = 1;
\t
\t// To/From System
\tinput clock;
\tinput reset_n;
\t// To/From Avalon_MM data slave interface
\tinput avmm_data_read;
\tinput avmm_data_write;
\tinput [AVMM_DATA_ADDR_WIDTH-1:0] avmm_data_addr;
\tinput [AVMM_DATA_DATA_WIDTH-1:0] avmm_data_writedata;
\tinput [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_data_burstcount;
\toutput avmm_data_waitrequest;
\toutput avmm_data_readdatavalid;
\toutput [AVMM_DATA_DATA_WIDTH-1:0] avmm_data_readdata;
\t// To/From Avalon_MM csr slave interface
\tinput avmm_csr_read;
\tinput avmm_csr_write;
\tinput avmm_csr_addr;
\tinput [AVMM_CSR_DATA_WIDTH-1:0] avmm_csr_writedata;
\toutput [AVMM_CSR_DATA_WIDTH-1:0] avmm_csr_readdata;
\twire [AVMM_DATA_DATA_WIDTH-1:0] avmm_data_readdata_wire;
\twire [AVMM_CSR_DATA_WIDTH-1:0] avmm_csr_readdata_wire;
\twire [31:0] csr_control_wire;
\twire [9:0] csr_status_wire;
\twire [FLASH_ADDR_WIDTH-1:0] flash_ardin_wire;
\twire [FLASH_DATA_WIDTH-1:0] flash_drdout_wire;
\twire flash_busy;
\twire flash_se_pass;
\twire flash_sp_pass;
\twire flash_osc;
\twire flash_xe_ye;
\twire flash_se;
\twire flash_arclk;
\twire flash_arshft;
\twire flash_drclk;
\twire flash_drshft;
\twire flash_drdin;
\twire flash_nprogram;
\twire flash_nerase;
\twire flash_par_en;
\twire flash_xe_ye_wire;
\twire flash_se_wire;
\t
\tassign avmm_data_readdata = avmm_data_readdata_wire;
\tgenerate
\t\tif (READ_AND_WRITE_MODE == 0) begin
\t\t\tassign avmm_csr_readdata = 32\'hffffffff;
\t\t\tassign csr_control_wire = 32\'h3fffffff;
\t\tend
\t\telse begin
\t\t\tassign avmm_csr_readdata = avmm_csr_readdata_wire;
\t\tend
\tendgenerate
\tgenerate
\t\tif (DEVICE_ID == "02" || DEVICE_ID == "01") begin
\t\t\tassign flash_par_en = 1\'b1;
\t\t\tassign flash_xe_ye = 1\'b1;
\t\t\tassign flash_se = 1\'b1;
\t\tend
\t\telse begin
\t\t\tassign flash_par_en = PARALLEL_MODE[0];
\t\t\tassign flash_xe_ye = flash_xe_ye_wire;
\t\t\tassign flash_se = flash_se_wire;
\t\tend
\tendgenerate
\t
\tgenerate
\t\tif (READ_AND_WRITE_MODE) begin
\t\t\t// -------------------------------------------------------------------
\t\t\t// Instantiate a Avalon_MM csr slave controller
\t\t\t// -------------------------------------------------------------------\t
\t\t\taltera_onchip_flash_avmm_csr_controller avmm_csr_controller (
\t\t\t\t// To/From System
\t\t\t\t.clock(clock),
\t\t\t\t.reset_n(reset_n),
\t\t\t\t// To/From Avalon_MM csr slave interface
\t\t\t\t.avmm_read(avmm_csr_read),
\t\t\t\t.avmm_write(avmm_csr_write),
\t\t\t\t.avmm_addr(avmm_csr_addr),
\t\t\t\t.avmm_writedata(avmm_csr_writedata),
\t\t\t\t.avmm_readdata(avmm_csr_readdata_wire),
\t\t
\t\t\t\t// To/From Avalon_MM data slave interface
\t\t\t\t.csr_control(csr_control_wire),
\t\t\t\t.csr_status(csr_status_wire)
\t\t\t);
\t\tend
\tendgenerate
\t// -------------------------------------------------------------------
\t// Instantiate a Avalon_MM data slave controller
\t// -------------------------------------------------------------------\t
\taltera_onchip_flash_avmm_data_controller # (
\t\t.READ_AND_WRITE_MODE (READ_AND_WRITE_MODE),
\t\t.WRAPPING_BURST_MODE (WRAPPING_BURST_MODE),
\t\t.AVMM_DATA_ADDR_WIDTH (AVMM_DATA_ADDR_WIDTH),
\t\t.AVMM_DATA_BURSTCOUNT_WIDTH (AVMM_DATA_BURSTCOUNT_WIDTH),
\t\t.FLASH_SEQ_READ_DATA_COUNT (FLASH_SEQ_READ_DATA_COUNT),
\t\t.FLASH_READ_CYCLE_MAX_INDEX (FLASH_READ_CYCLE_MAX_INDEX),
\t\t.FLASH_ADDR_ALIGNMENT_BITS (FLASH_ADDR_ALIGNMENT_BITS),
\t\t.FLASH_RESET_CYCLE_MAX_INDEX (FLASH_RESET_CYCLE_MAX_INDEX),
\t\t.FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX (FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX),
\t\t.FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX (FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX),
\t\t.FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX (FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX),
\t\t.MIN_VALID_ADDR (MIN_VALID_ADDR),
\t\t.MAX_VALID_ADDR (MAX_VALID_ADDR),
\t\t.SECTOR1_START_ADDR (SECTOR1_START_ADDR),
\t\t.SECTOR1_END_ADDR (SECTOR1_END_ADDR),
\t\t.SECTOR2_START_ADDR (SECTOR2_START_ADDR),
\t\t.SECTOR2_END_ADDR (SECTOR2_END_ADDR),
\t\t.SECTOR3_START_ADDR (SECTOR3_START_ADDR),
\t\t.SECTOR3_END_ADDR (SECTOR3_END_ADDR),
\t\t.SECTOR4_START_ADDR (SECTOR4_START_ADDR),
\t\t.SECTOR4_END_ADDR (SECTOR4_END_ADDR),
\t\t.SECTOR5_START_ADDR (SECTOR5_START_ADDR),
\t\t.SECTOR5_END_ADDR (SECTOR5_END_ADDR),
\t\t.SECTOR_READ_PROTECTION_MODE (SECTOR_READ_PROTECTION_MODE),
\t\t.SECTOR1_MAP (SECTOR1_MAP),
\t\t.SECTOR2_MAP (SECTOR2_MAP),
\t\t.SECTOR3_MAP (SECTOR3_MAP),
\t\t.SECTOR4_MAP (SECTOR4_MAP),
\t\t.SECTOR5_MAP (SECTOR5_MAP),
\t\t.ADDR_RANGE1_END_ADDR (ADDR_RANGE1_END_ADDR),
\t\t.ADDR_RANGE1_OFFSET (ADDR_RANGE1_OFFSET),
\t\t.ADDR_RANGE2_OFFSET (ADDR_RANGE2_OFFSET)
\t) avmm_data_controller (
\t\t// To/From System
\t\t.clock(clock),
\t\t.reset_n(reset_n),
\t\t
\t\t// To/From Flash IP interface
\t\t.flash_busy(flash_busy),
\t\t.flash_se_pass(flash_se_pass),
\t\t.flash_sp_pass(flash_sp_pass),
\t\t.flash_osc(flash_osc),
\t\t.flash_drdout(flash_drdout_wire),
\t\t.flash_xe_ye(flash_xe_ye_wire),
\t\t.flash_se(flash_se_wire),
\t\t.flash_arclk(flash_arclk),
\t\t.flash_arshft(flash_arshft),
\t\t.flash_drclk(flash_drclk),
\t\t.flash_drshft(flash_drshft),
\t\t.flash_drdin(flash_drdin),
\t\t.flash_nprogram(flash_nprogram),
\t\t.flash_nerase(flash_nerase),
\t\t.flash_ardin(flash_ardin_wire),
\t\t// To/From Avalon_MM data slave interface
\t\t.avmm_read(avmm_data_read),
\t\t.avmm_write(avmm_data_write),
\t\t.avmm_addr(avmm_data_addr),
\t\t.avmm_writedata(avmm_data_writedata),
\t\t.avmm_burstcount(avmm_data_burstcount),
\t\t.avmm_waitrequest(avmm_data_waitrequest),
\t\t.avmm_readdatavalid(avmm_data_readdatavalid),
\t\t.avmm_readdata(avmm_data_readdata_wire),
\t\t// To/From Avalon_MM csr slave interface
\t\t.csr_control(csr_control_wire),
\t\t.csr_status(csr_status_wire)
\t);
\t
\t// -------------------------------------------------------------------
\t// Instantiate wysiwyg for onchip flash block
\t// -------------------------------------------------------------------
\taltera_onchip_flash_block # (
\t
\t\t.DEVICE_FAMILY (DEVICE_FAMILY),
\t\t.PART_NAME (PART_NAME),
\t\t.IS_DUAL_BOOT (IS_DUAL_BOOT),
\t\t.IS_ERAM_SKIP (IS_ERAM_SKIP),
\t\t.IS_COMPRESSED_IMAGE (IS_COMPRESSED_IMAGE),
\t\t.INIT_FILENAME (INIT_FILENAME),
\t\t.MIN_VALID_ADDR (MIN_VALID_ADDR),
\t\t.MAX_VALID_ADDR (MAX_VALID_ADDR),
\t\t.MIN_UFM_VALID_ADDR (MIN_UFM_VALID_ADDR),
\t\t.MAX_UFM_VALID_ADDR (MAX_UFM_VALID_ADDR),
\t\t.ADDR_RANGE1_END_ADDR (ADDR_RANGE1_END_ADDR),
\t\t.ADDR_RANGE1_OFFSET (ADDR_RANGE1_OFFSET),
\t\t.ADDR_RANGE2_OFFSET (ADDR_RANGE2_OFFSET),
\t\t// simulation only start
\t\t.DEVICE_ID (DEVICE_ID),
\t\t.INIT_FILENAME_SIM (INIT_FILENAME_SIM)
\t\t// simulation only end
\t\t
\t) altera_onchip_flash_block (
\t\t.xe_ye(flash_xe_ye),
\t\t.se(flash_se),
\t\t.arclk(flash_arclk),
\t\t.arshft(flash_arshft),
\t\t.ardin(flash_ardin_wire),
\t\t.drclk(flash_drclk),
\t\t.drshft(flash_drshft),
\t\t.drdin(flash_drdin),
\t\t.nprogram(flash_nprogram),
\t\t.nerase(flash_nerase),
\t\t.nosc_ena(1\'b0),
\t\t.par_en(flash_par_en),
\t\t.drdout(flash_drdout_wire),
\t\t.busy(flash_busy),
\t\t.se_pass(flash_se_pass),
\t\t.sp_pass(flash_sp_pass),
\t\t.osc(flash_osc)
\t);
\t
\t
endmodule //altera_onchip_flash
//VALID FILE
|
// Copyright 2019 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`timescale 1ns/100ps
`include "qpi_flash.v"
`define assert(condition, message) if(!(condition)) begin $display("ASSERTION FAILED: %s", message); $finish(1); end
module qpi_flash_test;
// test clock
reg clk;
// inputs to the module under test
wire ready;
reg reset = 0;
reg read = 0;
reg [23:0] addr = 0;
reg passthrough = 0;
reg passthrough_nCE;
reg passthrough_SCK;
reg passthrough_MOSI;
// outputs from the module under test
wire [7:0] data_out;
// connections to the outside world
wire flash_SCK;
wire flash_nCE;
wire flash_IO0;
wire flash_IO1;
wire flash_IO2;
wire flash_IO3;
reg driving_IO = 0;
reg [3:0] output_IO = 4\'bz;
assign flash_IO3 = output_IO[3];
assign flash_IO2 = output_IO[2];
assign flash_IO1 = output_IO[1];
assign flash_IO0 = output_IO[0];
// test spi feeder
reg spi_ss = 1\'b1;
reg spi_sck = 1\'b0;
reg spi_mosi = 1\'b0;
wire spi_miso;
`define SHIFT_HIGH 63
reg [`SHIFT_HIGH:0] spi_shift;
reg [8:0] shift_count = 0;
reg waiting_for_reset = 0;
reg reset_wait_finished = 0;
reg [31:0] reset_wait_count = 0;
// module under test
qpi_flash dut(
.clk(clk),
.ready(ready),
.reset(reset),
.read(read),
.addr(addr),
.data_out(data_out),
.passthrough(passthrough),
.passthrough_nCE(passthrough_nCE),
.passthrough_SCK(passthrough_SCK),
.passthrough_MOSI(passthrough_MOSI),
.flash_nCE(flash_nCE),
.flash_SCK(flash_SCK),
.flash_IO0(flash_IO0),
.flash_IO1(flash_IO1),
.flash_IO2(flash_IO2),
.flash_IO3(flash_IO3)
);
// clock driver
initial begin
clk = 1\'b0;
forever #9 clk = ~clk;
end
always @(posedge dut.ready) begin
$display("rising edge on ready");
end
always @(negedge dut.reset) begin
$display("falling edge on reset");
end
always @(negedge dut.read) begin
$display("falling edge on read");
end
always @(negedge flash_nCE) begin
$display("falling edge on flash_nCE");
shift_count <= 0;
end
always @(posedge flash_SCK) begin
if (dut.qpi_mode == 1) begin
spi_shift <= {spi_shift[`SHIFT_HIGH-4:0], flash_IO3, flash_IO2, flash_IO1, flash_IO0};
$display("rising QPI edge with output nybble %x", {flash_IO3, flash_IO2, flash_IO1, flash_IO0});
shift_count <= shift_count + 4;
end else begin
spi_shift <= {spi_shift[`SHIFT_HIGH-1:0], flash_IO0};
// $display("rising SPI edge with MOSI %x", flash_IO0);
shift_count <= shift_count + 1;
end
end
always @(negedge flash_SCK) begin
if (shift_count == 8) begin
$display("-> output byte %x", spi_shift[7:0]);
shift_count <= 0;
end
end
always @(posedge clk) begin
if (ready == 1 || reset_wait_count > 10000) begin
reset_wait_finished <= 1;
end else if (reset_wait_finished == 0) begin
reset_wait_count <= reset_wait_count + 1;
end
end
initial begin
$display("running qpi_flash_test");
$dumpfile("qpi_flash_test.vcd");
$dumpvars(0, qpi_flash_test);
$display("start");
reset <= 1;
repeat(10) @(posedge clk);
reset <= 0;
waiting_for_reset <= 1;
reset_wait_count <= 0;
reset_wait_finished <= 0;
@(posedge reset_wait_finished);
`assert(ready == 1\'b1, "FAIL: device not ready");
$display("\
\
Reset successful; trying a read (0 alignment)");
addr <= 24\'h123454;
read <= 1;
@(posedge clk);
read <= 0;
// wait for 4 qpi bytes
repeat(8) @(negedge flash_SCK);
// now push some data
output_IO <= 4\'hA;
@(negedge flash_SCK);
output_IO <= 4\'hB;
@(negedge flash_SCK);
// output_IO <= 4\'hC;
// @(negedge flash_SCK);
// output_IO <= 4\'hD;
// @(negedge flash_SCK);
// output_IO <= 4\'hE;
// @(negedge flash_SCK);
// output_IO <= 4\'hF;
// @(negedge flash_SCK);
// output_IO <= 4\'h1;
// @(negedge flash_SCK);
// output_IO <= 4\'h2;
// @(negedge flash_SCK);
output_IO <= 4\'bz;
// wait for end of txn
@(posedge flash_nCE);
$display("Read transaction finished, by the looks of things; shifter == %x", dut.shifter);
// `assert(dut.shifter[31:0] == 32\'habcdef12, "shift value incorrect");
$display("data_out == %x", data_out);
`assert(data_out == 8\'hab, "data_out incorrect");
// $finish;
// $display("\
\
Reset successful; trying a read (1 alignment)");
// addr <= 24\'h000005;
// read <= 1;
// @(posedge clk);
// read <= 0;
// // wait for 4 qpi bytes
// repeat(8) @(negedge flash_SCK);
// // now push some data
// output_IO <= 4\'h1;
// @(negedge flash_SCK);
// output_IO <= 4\'h2;
// @(negedge flash_SCK);
// output_IO <= 4\'h3;
// @(negedge flash_SCK);
// output_IO <= 4\'h4;
// @(negedge flash_SCK);
// // output_IO <= 4\'h5;
// // @(negedge flash_SCK);
// // output_IO <= 4\'h6;
// // @(negedge flash_SCK);
// // output_IO <= 4\'h7;
// // @(negedge flash_SCK);
// // output_IO <= 4\'h8;
// // @(negedge flash_SCK);
// output_IO <= 4\'bz;
// // wait for end of txn
// @(posedge flash_nCE);
// $display("Read transaction finished, by the looks of things; shifter == %x", dut.shifter);
// // `assert(dut.shifter[31:0] == 32\'h12345678, "shift value incorrect");
// $display("data_out == %x", data_out);
// `assert(data_out == 8\'h34, "data_out incorrect");
// $display("\
\
Reset successful; trying a read (2 alignment)");
// addr <= 24\'hfffff2;
// read <= 1;
// @(posedge clk);
// read <= 0;
// // wait for 4 qpi bytes
// repeat(8) @(negedge flash_SCK);
// // now push some data
// output_IO <= 4\'h1;
// @(negedge flash_SCK);
// output_IO <= 4\'ha;
// @(negedge flash_SCK);
// output_IO <= 4\'h2;
// @(negedge flash_SCK);
// output_IO <= 4\'hb;
// @(negedge flash_SCK);
// output_IO <= 4\'h3;
// @(negedge flash_SCK);
// output_IO <= 4\'hc;
// @(negedge flash_SCK);
// // output_IO <= 4\'h4;
// // @(negedge flash_SCK);
// // output_IO <= 4\'hd;
// // @(negedge flash_SCK);
// output_IO <= 4\'bz;
// // wait for end of txn
// @(posedge flash_nCE);
// $display("Read transaction finished, by the looks of things; shifter == %x", dut.shifter);
// // `assert(dut.shifter[31:0] == 32\'h1a2b3c4d, "shift value incorrect");
// $display("data_out == %x", data_out);
// `assert(data_out == 8\'h3c, "data_out incorrect");
// $display("\
\
Reset successful; trying a read (3 alignment)");
// addr <= 24\'hcccc5b;
// read <= 1;
// @(posedge clk);
// read <= 0;
// // wait for 4 qpi bytes
// repeat(8) @(negedge flash_SCK);
// // now push some data
// output_IO <= 4\'hf;
// @(negedge flash_SCK);
// output_IO <= 4\'h9;
// @(negedge flash_SCK);
// output_IO <= 4\'he;
// @(negedge flash_SCK);
// output_IO <= 4\'h8;
// @(negedge flash_SCK);
// output_IO <= 4\'hd;
// @(negedge flash_SCK);
// output_IO <= 4\'h7;
// @(negedge flash_SCK);
// output_IO <= 4\'hc;
// @(negedge flash_SCK);
// output_IO <= 4\'h6;
// @(negedge flash_SCK);
// output_IO <= 4\'bz;
// // wait for end of txn
// @(posedge flash_nCE);
// $display("Read transaction finished, by the looks of things; shifter == %x", dut.shifter);
// // `assert(dut.shifter[31:0] == 32\'hf9e8d7c6, "shift value incorrect");
// $display("data_out == %x", data_out);
// `assert(data_out == 8\'hc6, "data_out incorrect");
// finish off
$display("running out the clock");
repeat(32) @(posedge clk);
$display("PASS");
$finish;
end
endmodule
|
// Copyright 2019 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// QPI flash interface
// Targetted at Winbond W25Q128JV (16MB QPI)
// We use the Fast Read Quad I/O (EBh) instruction in QPI mode, and enable
// Continuous Read Mode.
// First request:
// EB AA AA AA MM -> DO
// Subsequent requests:
// AA AA AA MM -> DO
// Format of the mode bits (MM):
// M7-6: xx
// M5-4: 10 to enable Continuous Read Mode
// M3-0: xxxx
// So 00100000 (0x20) will enter Continuous Read Mode
// To exit Continuous Read Mode, it\'s recommended to go into SPI mode (IO1-3
// don\'t care) and clock in 0xFFFF (sixteen clocks). Won\'t this cause a clash
// on the first query though?
// Probably want to do two transactions with spi_mode==1, clocking in 0xFF
// (eight clocks) each time. If we\'re in QPI continuous read mode, this will
// register as an address of FF FF FF and a mode of FF. If we\'re in QPI mode,
// it will register as an FF command, which exits QPI mode.
// READ COMMAND OPTIONS
// Fast Read (0Bh) in QPI Mode with 2 dummy clocks:
// \\ 0B AA AA AA 00 DD / = 13 clocks
// Fast Read Quad I/O (EBh) in QPI Mode with 2 dummy clocks (used for the Mode byte)
// \\ EB AA AA AA 20 DD / = 13 clocks for first request
// \\ AA AA AA 20 DD / = 11 clocks for subsequent requests
// The datasheet suggests that in QPI mode, addresses may need to be aligned
// on a 4-byte boundary, but this doesn\'t seem to be the case.
module qpi_flash(
// Fast clock for flash
input wire clk,
// Control interface; all signals synchronous w.r.t. clk
// Active high to indicate that the module can accept a read command
output reg ready = 0,
// Active high reset; when this transitions low, the module will
// initialize the flash chip.
input wire reset,
// Active high read instruction; pulse this for one clock with valid addr
// to start a read. When finished, ready will go high and data_out will
// be valid.
input wire read,
// Bus
input wire [23:0] addr,
// input wire [7:0] data_in, // one day...
output reg [7:0] data_out = 8\'hFF,
// Passthrough
input wire passthrough,
input wire passthrough_nCE,
input wire passthrough_SCK,
input wire passthrough_MOSI,
// Flash pins
output reg flash_nCE = 1,
output reg flash_SCK = 0,
inout wire flash_IO0,
inout wire flash_IO1,
inout wire flash_IO2,
inout wire flash_IO3
);
// Setup/hold notes:
// - Don\'t change /CS within 3ns of a rising clock edge. (min 3ns clk to flash_nCE)
// - IO* setup 1ns hold 2ns w.r.t. SCK. (min 2ns clk to flash_IO*)
// Reset: state register
reg [3:0] reset_state = 0;
`define RESET_START 0
`define RESET_DISABLE_CONT_READ 1
`define RESET_DISABLE_QPI 2
`define RESET_RESET_CHIP 3
`define RESET_WAIT_CHIP 4
`define RESET_ENTER_QPI 5
`define RESET_SET_DUMMY_CLOCKS 6
`define RESET_ENTER_CONT_READ 7
`define RESET_TEST_CONT_READ 8
`define RESET_SET_READY 9
`define RESET_DONE 10
// Reset: 30us counter
reg [12:0] reset_delay_counter = 13\'b0;
// Shifter for IO[3:0]
reg [39:0] shifter = 0;
reg [6:0] shift_count = 0;
// Tracking previous passthrough value so we can reset after a passthrough ends
reg last_passthrough = 0;
// IO state
reg spi_mode = 1\'b0; // IO0 output, IO1 input, IO2/3 tristate
reg qpi_mode = 1\'b0;
reg qpi_output = 1\'b0; // if qpi_mode == 1, this means we\'re in the output phase
reg [5:0] qpi_output_count = 0; // countdown to turnaround
`define TXN_IDLE 0
`define TXN_START 1
`define TXN_RUNNING 2
`define TXN_FINISH 3
`define TXN_DONE 4
reg [2:0] txn_state = `TXN_IDLE;
reg reading = 0;
// Output register
reg [3:0] output_IO = 4\'b0;
// Drive flash_IO* correctly depending on mode
assign flash_IO0 = (spi_mode == 1\'b1 || qpi_output == 1\'b1) ? output_IO[0] : 1\'bZ;
assign flash_IO1 = (qpi_output == 1\'b1) ? output_IO[1] : 1\'bZ;
assign flash_IO2 = (qpi_output == 1\'b1) ? output_IO[2] : 1\'bZ;
assign flash_IO3 = (qpi_output == 1\'b1) ? output_IO[3] : 1\'bZ;
always @(posedge clk) begin
// Lowest priority: read by MCU
if (read == 1\'b1) begin
$display("Read triggered with addr %x", addr);
qpi_output_count <= 6\'d24 + 6\'d8; // output address and mode byte
// 4-byte alignment
// shifter <= {addr[23:2], 2\'b00, 8\'h20, 8\'b0}; // addr & ~3
// shift_count <= 7\'d24 + 7\'d8 + 7\'d8 + (7\'d8 * addr[1:0]); // read 1-4 data bytes
// 1-byte alignment (seems to work, despite what the datasheet says...)
shifter <= {addr, 8\'h20, 8\'b0};
shift_count <= 7\'d24 + 7\'d8 + 7\'d8; // read one data byte
txn_state <= `TXN_START;
reading <= 1;
ready <= 0;
// When running at 2MHz with an internal 6502, we have to be stable
// while cpu_clken==1, but we have 7 x 62.5ns 16MHz clocks = 42 x
// 96MHz clocks = 437.5 ns for memory access.
// With running at 2MHz with an external 6502, we have 280 ns after
// allowing for 170 ns address setup (30ns PHI0-PHI2 delay, 140ns
// PHI2-A setup) and 50ns data hold.
// The current read algorithm here will take 1 + (24 + 8 + 32) / 2 + 3
// clocks (two clocks to transmit 4 bits in the data phase) = 36 x
// 10.42 ns = 375.12 ns, so it should work with an internal T65 but
// not an external 6502 yet.
end
if (reading && txn_state == `TXN_DONE) begin
reading <= 0;
ready <= 1;
data_out <= shifter[7:0];
end
// Medium priority: SPI passthrough for MCU-driven SPI
if (passthrough == 1\'b1) begin
spi_mode <= 1\'b1;
qpi_mode <= 0;
qpi_output <= 1\'b0;
flash_nCE <= passthrough_nCE;
flash_SCK <= passthrough_SCK;
output_IO[0] <= passthrough_MOSI;
end
last_passthrough <= passthrough;
if (last_passthrough == 1\'b1 && passthrough == 1\'b0) begin
// Reset line after passthrough is disabled
flash_nCE <= 1\'b1;
flash_SCK <= 1\'b0;
output_IO[0] <= 1\'b0;
// Re-enter QPI mode
//reset_state <= `RESET_START; // DEBUG don\'t reset after passthrough
end
// Execute SPI requests
if (spi_mode == 1\'b1) begin
case (txn_state)
`TXN_START : begin
flash_nCE <= 1\'b0;
output_IO[0] = shifter[39];
shifter <= {shifter[38:0], 1\'b0};
txn_state <= `TXN_RUNNING;
end
`TXN_RUNNING : begin
if (shift_count == 0) begin
txn_state <= `TXN_FINISH;
end else if (flash_SCK == 1\'b0) begin
// Rising SCK edge
flash_SCK <= 1\'b1;
end else begin
// Falling SCK edge; clock data in and out
flash_SCK <= 1\'b0;
output_IO[0] = shifter[39];
shifter <= {shifter[38:0], flash_IO1};
shift_count <= shift_count - 1;
end
end
`TXN_FINISH : begin
flash_nCE <= 1\'b1;
txn_state <= `TXN_DONE;
end
endcase
end
// Execute QPI requests
if (qpi_mode == 1\'b1) begin
case (txn_state)
`TXN_START : begin
flash_nCE <= 1\'b0;
output_IO <= shifter[39:36];
shifter <= {shifter[35:0], 4\'b0};
qpi_output <= 1;
txn_state <= `TXN_RUNNING;
end
`TXN_RUNNING : begin
if (shift_count == 0) begin
txn_state <= `TXN_FINISH;
end else if (flash_SCK == 1\'b0) begin
// Rising SCK edge
flash_SCK <= 1\'b1;
end else begin
// Falling SCK edge; clock data in and out
flash_SCK <= 1\'b0;
output_IO <= shifter[39:36];
shifter <= {shifter[35:0], flash_IO3, flash_IO2, flash_IO1, flash_IO0};
shift_count <= shift_count - 7\'d4;
if (qpi_output_count == 4) begin
qpi_output <= 0;
end else begin
qpi_output_count <= qpi_output_count - 6\'d4;
end
if (qpi_output == 0 && shift_count == 7\'d4) begin
data_out <= {shifter[3:0], flash_IO3, flash_IO2, flash_IO1, flash_IO0};
end
end
end
`TXN_FINISH : begin
flash_nCE <= 1\'b1;
qpi_output <= 1\'b0;
txn_state <= `TXN_DONE;
end
endcase
end
// Highest priority: reset
case (reset_state)
`RESET_START : begin
// During flash programming, the QE (Quad Enable) bit is set, and
// it\'s non-volatile, so we don\'t need to deal with that here.
reset_state <= `RESET_DISABLE_CONT_READ;
end
`RESET_DISABLE_CONT_READ : begin
// Start with a single-byte (FF) SPI transaction to disable
// continuous read mode, if enabled.
case (txn_state)
`TXN_IDLE : begin
$display("qpi_flash: Disabling continuous read");
shifter <= 40\'hFF00000000;
shift_count <= 8;
txn_state <= `TXN_START;
end
`TXN_DONE : begin
txn_state <= `TXN_IDLE;
reset_state <= `RESET_DISABLE_QPI;
end
endcase
end
`RESET_DISABLE_QPI : begin
// Now a second single-byte (FF) SPI transaction, to disable
// QPI mode, if enabled.
case (txn_state)
`TXN_IDLE : begin
$display("qpi_flash: Disabling QPI mode");
shifter <= 40\'hFF00000000;
shift_count <= 8;
txn_state <= `TXN_START;
end
`TXN_DONE : begin
txn_state <= `TXN_IDLE;
reset_state <= `RESET_ENTER_QPI;
// reset_state <= `RESET_SET_READY; // Disable QPI for testing
end
endcase
end
//`RESET_RESET_CHIP: begin
// // Now a two-byte (66 99) SPI transaction to reset the chip.
// case (txn_state)
// `TXN_IDLE : begin
// shifter <= 40\'h6699000000;
// shift_count <= 8;
// end
// `TXN_DONE : begin
// txn_state <= `TXN_IDLE;
// reset_state <= `RESET_WAIT_CHIP;
// end
// endcase
//end
//`RESET_WAIT_CHIP : begin
// // Now delay 30us (2880 96MHz clocks using reset_delay_counter) to
// // let the chip reset finish.
// //TODO
// reset_state <= `RESET_ENTER_QPI;
//end
`RESET_ENTER_QPI : begin
// Now a one-byte (38) SPI transaction to enter QPI mode.
case (txn_state)
`TXN_IDLE : begin
$display("qpi_flash: Entering QPI mode");
shifter <= 40\'h3800000000;
shift_count <= 8;
txn_state <= `TXN_START;
end
`TXN_DONE : begin
txn_state <= `TXN_IDLE;
reset_state <= `RESET_SET_DUMMY_CLOCKS;
spi_mode <= 0;
qpi_mode <= 1;
// reset_state <= `RESET_SET_READY; // DEBUG skip QPI transactions
end
endcase
end
`RESET_SET_DUMMY_CLOCKS : begin
// Now a two-byte (C0 00) QPI transaction to set 2 dummy clocks
// (which is what we need below 50 MHz).
case (txn_state)
`TXN_IDLE : begin
$display("qpi_flash: Setting read params");
shifter <= 40\'hC000000000;
shift_count <= 16;
qpi_output_count <= 20; // Remain in output state after txn
txn_state <= `TXN_START;
end
`TXN_DONE : begin
txn_state <= `TXN_IDLE;
reset_state <= `RESET_ENTER_CONT_READ;
end
endcase
end
`RESET_ENTER_CONT_READ : begin
// Now a five-byte (EB 00 00 00 20) QPI transaction to enter
// continuous read mode.
case (txn_state)
`TXN_IDLE : begin
$display("qpi_flash: Entering continuous read mode");
// shifter <= 40\'hEB00000020;
// shifter <= 40\'hEB00000120; // test unaligned read; expect ab
// shifter <= 40\'hEB00000220; // test unaligned read; expect 8e
shifter <= 40\'hEB00000320; // test unaligned read; expect 82 (or 4c with single byte read)
// shift_count <= 72; // read 4 bytes at the end
shift_count <= 48; // read one byte at the end
qpi_output_count <= 40;
txn_state <= `TXN_START;
end
`TXN_DONE : begin
txn_state <= `TXN_IDLE;
reset_state <= `RESET_TEST_CONT_READ;
end
endcase
end
`RESET_TEST_CONT_READ : begin
// Try aa four-byte (00 00 00 20) QPI read
case (txn_state)
`TXN_IDLE : begin
$display("qpi_flash: Testing continuous read mode");
shifter <= 40\'h0000072000; // test unaligned read; expect 1b
shift_count <= 40; // read one byte at the end
qpi_output_count <= 32;
txn_state <= `TXN_START;
end
`TXN_DONE : begin
txn_state <= `TXN_IDLE;
reset_state <= `RESET_SET_READY;
end
endcase
end
`RESET_SET_READY : begin
// Now set ready = 1\'b1 and go to normal operation
$display("qpi_flash: Reset done");
ready <= 1;
reset_state <= `RESET_DONE;
end
`RESET_DONE : begin
// Normal operation!
end
default : begin
// ERROR
end
endcase
if (reset == 1\'b1) begin
ready <= 1\'b0;
flash_nCE <= 1\'b1;
flash_SCK <= 1\'b0;
output_IO <= 4\'b0;
spi_mode <= 1\'b1;
qpi_mode <= 1\'b0;
qpi_output <= 1\'b0;
reading <= 0;
reset_state <= `RESET_START;
end
end
endmodule
|
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|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
////////////////////////////////////////////////////////////////////
//
// ALTERA_ONCHIP_FLASH_UTIL
//
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
////////////////////////////////////////////////////////////////////
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
`timescale 1 ps / 1 ps
module altera_onchip_flash_address_range_check (
address,
is_addr_within_valid_range
);
parameter FLASH_ADDR_WIDTH = 23;
parameter MIN_VALID_ADDR = 1;
parameter MAX_VALID_ADDR = 1;
input [FLASH_ADDR_WIDTH-1:0] address;
output is_addr_within_valid_range;
assign is_addr_within_valid_range = (address >= MIN_VALID_ADDR) && (address <= MAX_VALID_ADDR);
endmodule
module altera_onchip_flash_address_write_protection_check (
use_sector_addr,
address,
write_protection_mode,
is_addr_writable
);
parameter FLASH_ADDR_WIDTH = 23;
parameter SECTOR1_START_ADDR = 1;
parameter SECTOR1_END_ADDR = 1;
parameter SECTOR2_START_ADDR = 1;
parameter SECTOR2_END_ADDR = 1;
parameter SECTOR3_START_ADDR = 1;
parameter SECTOR3_END_ADDR = 1;
parameter SECTOR4_START_ADDR = 1;
parameter SECTOR4_END_ADDR = 1;
parameter SECTOR5_START_ADDR = 1;
parameter SECTOR5_END_ADDR = 1;
parameter SECTOR_READ_PROTECTION_MODE = 5'b11111;
input use_sector_addr;
input [FLASH_ADDR_WIDTH-1:0] address;
input [4:0] write_protection_mode;
output is_addr_writable;
wire is_sector1_addr;
wire is_sector2_addr;
wire is_sector3_addr;
wire is_sector4_addr;
wire is_sector5_addr;
wire is_sector1_writable;
wire is_sector2_writable;
wire is_sector3_writable;
wire is_sector4_writable;
wire is_sector5_writable;
assign is_sector1_addr = (use_sector_addr) ? (address == 1) : ((address >= SECTOR1_START_ADDR) && (address <= SECTOR1_END_ADDR));
assign is_sector2_addr = (use_sector_addr) ? (address == 2) : ((address >= SECTOR2_START_ADDR) && (address <= SECTOR2_END_ADDR));
assign is_sector3_addr = (use_sector_addr) ? (address == 3) : ((address >= SECTOR3_START_ADDR) && (address <= SECTOR3_END_ADDR));
assign is_sector4_addr = (use_sector_addr) ? (address == 4) : ((address >= SECTOR4_START_ADDR) && (address <= SECTOR4_END_ADDR));
assign is_sector5_addr = (use_sector_addr) ? (address == 5) : ((address >= SECTOR5_START_ADDR) && (address <= SECTOR5_END_ADDR));
assign is_sector1_writable = ~(write_protection_mode[0] || SECTOR_READ_PROTECTION_MODE[0]);
assign is_sector2_writable = ~(write_protection_mode[1] || SECTOR_READ_PROTECTION_MODE[1]);
assign is_sector3_writable = ~(write_protection_mode[2] || SECTOR_READ_PROTECTION_MODE[2]);
assign is_sector4_writable = ~(write_protection_mode[3] || SECTOR_READ_PROTECTION_MODE[3]);
assign is_sector5_writable = ~(write_protection_mode[4] || SECTOR_READ_PROTECTION_MODE[4]);
assign is_addr_writable = ((is_sector1_writable && is_sector1_addr) ||
(is_sector2_writable && is_sector2_addr) ||
(is_sector3_writable && is_sector3_addr) ||
(is_sector4_writable && is_sector4_addr) ||
(is_sector5_writable && is_sector5_addr));
endmodule
module altera_onchip_flash_s_address_write_protection_check (
address,
is_sector1_writable,
is_sector2_writable,
is_sector3_writable,
is_sector4_writable,
is_sector5_writable,
is_addr_writable
);
input [2:0] address;
input is_sector1_writable;
input is_sector2_writable;
input is_sector3_writable;
input is_sector4_writable;
input is_sector5_writable;
output is_addr_writable;
wire is_sector1_addr;
wire is_sector2_addr;
wire is_sector3_addr;
wire is_sector4_addr;
wire is_sector5_addr;
assign is_sector1_addr = (address == 1);
assign is_sector2_addr = (address == 2);
assign is_sector3_addr = (address == 3);
assign is_sector4_addr = (address == 4);
assign is_sector5_addr = (address == 5);
assign is_addr_writable = ((is_sector1_writable && is_sector1_addr) ||
(is_sector2_writable && is_sector2_addr) ||
(is_sector3_writable && is_sector3_addr) ||
(is_sector4_writable && is_sector4_addr) ||
(is_sector5_writable && is_sector5_addr));
endmodule
module altera_onchip_flash_a_address_write_protection_check (
address,
is_sector1_writable,
is_sector2_writable,
is_sector3_writable,
is_sector4_writable,
is_sector5_writable,
is_addr_writable
);
parameter FLASH_ADDR_WIDTH = 23;
parameter SECTOR1_START_ADDR = 1;
parameter SECTOR1_END_ADDR = 1;
parameter SECTOR2_START_ADDR = 1;
parameter SECTOR2_END_ADDR = 1;
parameter SECTOR3_START_ADDR = 1;
parameter SECTOR3_END_ADDR = 1;
parameter SECTOR4_START_ADDR = 1;
parameter SECTOR4_END_ADDR = 1;
parameter SECTOR5_START_ADDR = 1;
parameter SECTOR5_END_ADDR = 1;
input [FLASH_ADDR_WIDTH-1:0] address;
input is_sector1_writable;
input is_sector2_writable;
input is_sector3_writable;
input is_sector4_writable;
input is_sector5_writable;
output is_addr_writable;
wire is_sector1_addr;
wire is_sector2_addr;
wire is_sector3_addr;
wire is_sector4_addr;
wire is_sector5_addr;
assign is_sector1_addr = ((address >= SECTOR1_START_ADDR) && (address <= SECTOR1_END_ADDR));
assign is_sector2_addr = ((address >= SECTOR2_START_ADDR) && (address <= SECTOR2_END_ADDR));
assign is_sector3_addr = ((address >= SECTOR3_START_ADDR) && (address <= SECTOR3_END_ADDR));
assign is_sector4_addr = ((address >= SECTOR4_START_ADDR) && (address <= SECTOR4_END_ADDR));
assign is_sector5_addr = ((address >= SECTOR5_START_ADDR) && (address <= SECTOR5_END_ADDR));
assign is_addr_writable = ((is_sector1_writable && is_sector1_addr) ||
(is_sector2_writable && is_sector2_addr) ||
(is_sector3_writable && is_sector3_addr) ||
(is_sector4_writable && is_sector4_addr) ||
(is_sector5_writable && is_sector5_addr));
endmodule
module altera_onchip_flash_convert_address (
address,
flash_addr
);
parameter FLASH_ADDR_WIDTH = 23;
parameter ADDR_RANGE1_END_ADDR = 1;
parameter ADDR_RANGE1_OFFSET = 1;
parameter ADDR_RANGE2_OFFSET = 1;
input [FLASH_ADDR_WIDTH-1:0] address;
output [FLASH_ADDR_WIDTH-1:0] flash_addr;
assign flash_addr = (address <= ADDR_RANGE1_END_ADDR[FLASH_ADDR_WIDTH-1:0]) ?
(address + ADDR_RANGE1_OFFSET[FLASH_ADDR_WIDTH-1:0]) :
(address + ADDR_RANGE2_OFFSET[FLASH_ADDR_WIDTH-1:0]);
endmodule
module altera_onchip_flash_convert_sector (
sector,
flash_sector
);
parameter SECTOR1_MAP = 1;
parameter SECTOR2_MAP = 1;
parameter SECTOR3_MAP = 1;
parameter SECTOR4_MAP = 1;
parameter SECTOR5_MAP = 1;
input [2:0] sector;
output [2:0] flash_sector;
assign flash_sector =
(sector == 1) ? SECTOR1_MAP[2:0] :
(sector == 2) ? SECTOR2_MAP[2:0] :
(sector == 3) ? SECTOR3_MAP[2:0] :
(sector == 4) ? SECTOR4_MAP[2:0] :
(sector == 5) ? SECTOR5_MAP[2:0] :
3'd0; // Set to 0 for invalid sector ID
endmodule
module altera_onchip_flash_counter (
clock,
reset,
count
);
input clock;
input reset;
output [4:0] count;
reg [4:0] count_reg;
assign count = count_reg;
initial begin
count_reg = 0;
end
always @ (posedge reset or posedge clock) begin
if (reset) begin
count_reg <= 0;
end
else begin
count_reg <= count_reg + 5'd1;
end
end
endmodule
|
// Copyright 2018 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`timescale 1ns/100ps
`include "a3000_rom_emulator.v"
`define assert(condition, message) if(!(condition)) begin $display(message); $finish(1); end
module a3000_rom_emulator_tb;
// test clock
reg clk;
// inputs to the module under test
wire [31:0] arm_D; // inout, but we only care about it when it\'s an output
reg [19:0] arm_A = 16\'b0; // driven by ARM
// outputs from the module under test
wire [21:0] flash_A;
wire [31:0] flash_D;
wire flash_nCE;
wire flash_nOE;
wire flash_nWE;
assign flash_D = (flash_nCE == 1\'b0 && flash_nOE == 1\'b0) ? {10\'b1010101010, flash_A} : 32\'bZ;
// test spi feeder
reg spi_ss = 1\'b1;
reg spi_sck = 1\'b0;
reg spi_mosi = 1\'b0;
wire spi_miso;
reg [63:0] spi_shift;
reg [63:0] spi_d;
reg spi_start = 0; // drive this high for one clk pulse to start an spi transaction
reg [6:0] spi_count;
reg rom_nCS = 1\'b0;
reg rom_nOE = 1\'b0;
reg rom_5V = 1\'b1;
// module under test
a3000_rom_emulator dut(
.rom_nOE(rom_nOE),
.rom_D(arm_D),
.rom_A(arm_A),
.rom_nCS(rom_nCS),
.flash_A(flash_A),
.flash0_DQ(flash_D[15:0]),
.flash1_DQ(flash_D[31:16]),
.flash_nCE(flash_nCE),
.flash_nOE(flash_nOE),
.flash_nWE(flash_nWE),
.cpld_clock_from_mcu(cpld_clock_from_mcu),
.rom_5V(rom_5V),
.cpld_MOSI(spi_mosi),
.cpld_SS(spi_ss),
.cpld_SCK(spi_sck),
.cpld_MISO(spi_miso)
);
// clock driver
initial begin
clk = 1\'b0;
forever #9 clk = ~clk;
end
// spi process
always @(posedge clk) begin
if (spi_start == 1\'b1) begin
$display("- start SPI transaction with spi_d=%x", spi_d);
spi_ss <= 1\'b0;
spi_count <= 7\'d64;
spi_mosi <= spi_d[63]; // first bit
spi_shift <= {spi_d[62:0], 1\'b0};
spi_sck <= 1\'b0;
end else if (spi_ss == 1\'b0) begin
if (spi_count == 0) begin
$display("- end SPI transaction with spi_shift=%x (arm acc %x, rnw %x, A %x, wdata %x, rdata %x)",
spi_shift, spi_shift[63], spi_shift[62], spi_shift[61:40], spi_shift[39:8], spi_shift[31:0]);
spi_ss <= 1\'b1; // end of transaction
end else if (spi_sck == 1\'b0) begin
spi_sck <= 1\'b1;
end else begin
// mid-transaction
spi_mosi <= spi_shift[63];
spi_shift <= {spi_shift[62:0], spi_miso};
spi_count <= spi_count - 1;
spi_sck <= 1\'b0;
end;
end
end
always @(negedge dut.allowing_arm_access) begin
$display("disallowing ARM access");
end
always @(posedge dut.allowing_arm_access) begin
$display("allowing ARM access");
end
always @(negedge flash_nOE) begin
$display("flash_nOE low with flash_A=%x (flash_D=%x)", flash_A, flash_D);
end
always @(posedge flash_nOE) begin
$display("flash_nOE high with flash_A=%x (flash_D=%x)", flash_A, flash_D);
end
always @(negedge flash_nWE) begin
$display("flash_nWE low with flash_A=%x and flash_D=%x", flash_A, flash_D);
end
always @(posedge flash_nWE) begin
$display("flash_nWE high with flash_A=%x and flash_D=%x", flash_A, flash_D);
end
initial begin
$display("running a3000_rom_emulator_tb");
$dumpfile("a3000_rom_emulator_tb.vcd");
$dumpvars(0, a3000_rom_emulator_tb);
$display("start");
repeat(10) @(posedge clk);
// check that we start out letting the ARM control the flash
`assert(dut.allowing_arm_access == 1\'b1, "FAIL: not allowing ARM access initially");
$display("\
Setting arm_A to 12345");
arm_A <= 17\'h12345;
$display("\
TEST that 7fffffffffffffff disables ARM access");
spi_d <= 64\'h7fffffffffffffff;
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
@(posedge clk);
`assert(dut.allowing_arm_access == 1\'b0, "FAIL: ffffff00 didn\'t disable ARM access");
$display("\
TEST that ffffffffffffffff reenables ARM access");
spi_d <= 64\'hffffffffffffffff;
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
@(posedge clk);
`assert(dut.allowing_arm_access == 1\'b1, "FAIL: 32 1\'s didn\'t reenable ARM access");
$display("\
TEST that we can write to the flash (A 51234 D 12345678)");
// message format for a WRITE: acc, rnw, a[22], d[32], 8\'b0
// with the write happening during the six zeros
spi_d <= {1\'b0, 1\'b0, 22\'b1010001001000110100, 32\'h12345678, 8\'b0};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
`assert(dut.allowing_arm_access == 1\'b0, "FAIL: write operation unlocked ARM access");
$display("\
TEST that we can read from the flash (70f0f)");
// message format for a WRITE: acc, rnw, a[22], 8\'b0, d[32]
// with the data byte returned in the final 8 bits
spi_d <= {1\'b0, 1\'b1, 22\'b1110000111100001111, 40\'b0};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
`assert(dut.allowing_arm_access == 1\'b0, "FAIL: write operation unlocked ARM access");
$display("\
TEST that the unlock process appears correct");
$display("unlock: write AA to 5555");
spi_d <= {1\'b0, 1\'b0, 22\'h5555, 32\'hAA, 8\'b0};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
$display("unlock: write 55 to 2AAA");
spi_d <= {1\'b0, 1\'b0, 22\'h2AAA, 32\'h55, 8\'b0};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
$display("unlock: write 90 to 5555");
spi_d <= {1\'b0, 1\'b0, 22\'h5555, 32\'h90, 8\'b0};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
$display("unlock: read 0");
spi_d <= {1\'b0, 1\'b1, 32\'h0000, 40\'b0};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
$display("unlock: read 1");
spi_d <= {1\'b0, 1\'b1, 32\'h0001, 40\'b0};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
$display("unlock: write F0 to 5555");
spi_d <= {1\'b0, 1\'b0, 22\'h5555, 32\'hF0, 8\'b0};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
$display("^^^ expect write 5555, write 2AAA, write 5555, read 0, read 1, write 5555");
// finish off
$display("running out the clock");
repeat(1000) @(posedge clk);
$display("PASS");
$finish;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:40:21 03/23/2015
// Design Name:
// Module Name: serial_interface
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module serial_interface #(
parameter CLK_RATE = 50000000,
parameter SERIAL_BAUD_RATE = 500000
)(
input clk,
input rst,
\t
\t //Serial Signals
\t output tx,
input rx,
\t
\t // Serial TX User Interface
input [7:0] tx_data,
input new_tx_data,
output tx_busy,
input tx_block,
// Serial Rx User Interface
output [7:0] rx_data,
output new_rx_data
);
// CLK_PER_BIT is the number of cycles each 'bit' lasts for
// rtoi converts a 'real' number to an 'integer'
parameter CLK_PER_BIT = $rtoi($ceil(CLK_RATE/SERIAL_BAUD_RATE));
serial_rx #(.CLK_PER_BIT(CLK_PER_BIT)) serial_rx (
.clk(clk),
.rst(rst),
.rx(rx),
.data(rx_data),
.new_data(new_rx_data)
);
serial_tx #(.CLK_PER_BIT(CLK_PER_BIT)) serial_tx (
.clk(clk),
.rst(rst),
.tx(tx),
.block(tx_block),
.busy(tx_busy),
.data(tx_data),
.new_data(new_tx_data)
);
\t
endmodule
|
module spi_addressing (
\tinput clk,
input rst,
// SPI Signals
output spi_miso,
input spi_mosi,
input spi_sck,
input spi_ss,
// Register interface signals
output [5:0] reg_addr,
output write,
output new_req,
output [7:0] write_value,
input [7:0] read_value,
\toutput in_transaction
);
wire spi_done;
wire [7:0] spi_dout;
wire frame_start, frame_end;
wire spi_miso_m;
spi_slave spi_slave (
.clk(clk),
.rst(n_rdy),
.ss(spi_ss),
.mosi(spi_mosi),
.miso(spi_miso_m),
.sck(spi_sck),
.done(spi_done),
.din(read_value),
.dout(spi_dout),
.frame_start(frame_start),
.frame_end(frame_end)
);
localparam STATE_SIZE = 2;
localparam IDLE = 0,
ADDR = 1,
WRITE = 2,
READ = 3;
reg [STATE_SIZE-1:0] state_d, state_q;
reg [7:0] write_value_d, write_value_q;
reg write_d, write_q;
reg auto_inc_d, auto_inc_q;
reg [5:0] reg_addr_d, reg_addr_q;
reg new_req_d, new_req_q;
reg first_write_d, first_write_q;
assign reg_addr = reg_addr_q;
assign write = write_q;
assign new_req = new_req_q;
assign write_value = write_value_q;
assign spi_miso = !spi_ss ? spi_miso_m : 1'bZ;
assign in_transaction = !spi_ss;
always @(*) begin
write_value_d = write_value_q;
write_d = write_q;
auto_inc_d = auto_inc_q;
reg_addr_d = reg_addr_q;
new_req_d = 1'b0;
state_d = state_q;
first_write_d = first_write_q;
case (state_q)
IDLE: begin
if (frame_start)
state_d = ADDR;
end
ADDR: begin
if (spi_done) begin
first_write_d = 1'b1;
{write_d, auto_inc_d, reg_addr_d} = spi_dout;
if (spi_dout[7]) begin
state_d = WRITE;
end else begin
state_d = READ;
new_req_d = 1'b1;
end
end
end
WRITE: begin
if (spi_done) begin
first_write_d = 1'b0;
if (auto_inc_q && !first_write_q)
reg_addr_d = reg_addr_q + 1'b1;
new_req_d = 1'b1;
write_value_d = spi_dout;
end
end
READ: begin
if (spi_done) begin
if (auto_inc_q)
reg_addr_d = reg_addr_q + 1'b1;
new_req_d = 1'b1;
end
end
default: state_d = IDLE;
endcase
if (frame_end)
state_d = IDLE;
end
always @(posedge clk) begin
if (rst) begin
state_q <= IDLE;
end else begin
state_q <= state_d;
end
write_value_q <= write_value_d;
write_q <= write_d;
auto_inc_q <= auto_inc_d;
reg_addr_q <= reg_addr_d;
new_req_q <= new_req_d;
first_write_q <= first_write_d;
end
endmodule
|
module serial_rx #(
parameter CLK_PER_BIT = 50
)(
input clk,
input rst,
input rx,
output [7:0] data,
output new_data
);
// clog2 is 'ceiling of log base 2' which gives you the number of bits needed to store a value
parameter CTR_SIZE = $clog2(CLK_PER_BIT);
localparam STATE_SIZE = 2;
localparam IDLE = 2'd0,
WAIT_HALF = 2'd1,
WAIT_FULL = 2'd2,
WAIT_HIGH = 2'd3;
reg [CTR_SIZE-1:0] ctr_d, ctr_q;
reg [2:0] bit_ctr_d, bit_ctr_q;
reg [7:0] data_d, data_q;
reg new_data_d, new_data_q;
reg [STATE_SIZE-1:0] state_d, state_q = IDLE;
reg rx_d, rx_q;
assign new_data = new_data_q;
assign data = data_q;
always @(*) begin
rx_d = rx;
state_d = state_q;
ctr_d = ctr_q;
bit_ctr_d = bit_ctr_q;
data_d = data_q;
new_data_d = 1'b0;
case (state_q)
IDLE: begin
bit_ctr_d = 3'b0;
ctr_d = 1'b0;
if (rx_q == 1'b0) begin
state_d = WAIT_HALF;
end
end
WAIT_HALF: begin
ctr_d = ctr_q + 1'b1;
if (ctr_q == (CLK_PER_BIT >> 1)) begin
ctr_d = 1'b0;
state_d = WAIT_FULL;
end
end
WAIT_FULL: begin
ctr_d = ctr_q + 1'b1;
if (ctr_q == CLK_PER_BIT - 1) begin
data_d = {rx_q, data_q[7:1]};
bit_ctr_d = bit_ctr_q + 1'b1;
ctr_d = 1'b0;
if (bit_ctr_q == 3'd7) begin
state_d = WAIT_HIGH;
new_data_d = 1'b1;
end
end
end
WAIT_HIGH: begin
if (rx_q == 1'b1) begin
state_d = IDLE;
end
end
default: begin
state_d = IDLE;
end
endcase
end
always @(posedge clk) begin
if (rst) begin
ctr_q <= 1'b0;
bit_ctr_q <= 3'b0;
new_data_q <= 1'b0;
state_q <= IDLE;
end else begin
ctr_q <= ctr_d;
bit_ctr_q <= bit_ctr_d;
new_data_q <= new_data_d;
state_q <= state_d;
end
rx_q <= rx_d;
data_q <= data_d;
end
endmodule
|
module spi_slave(
input clk,
input rst,
input ss,
input mosi,
output miso,
input sck,
output done,
input [7:0] din,
output [7:0] dout,
output reg frame_start,
output reg frame_end
);
reg mosi_d, mosi_q;
reg ss_d, ss_q;
reg sck_d, sck_q;
reg sck_old_d, sck_old_q;
reg [7:0] data_d, data_q;
reg done_d, done_q;
reg [2:0] bit_ct_d, bit_ct_q;
reg [7:0] dout_d, dout_q;
reg miso_d, miso_q;
reg frame_d, frame_q;
assign miso = miso_q;
assign done = done_q;
assign dout = dout_q;
always @(*) begin
ss_d = ss;
mosi_d = mosi;
miso_d = miso_q;
sck_d = sck;
sck_old_d = sck_q;
data_d = data_q;
done_d = 1'b0;
bit_ct_d = bit_ct_q;
dout_d = dout_q;
frame_d = ss_q;
frame_start = 1'b0;
frame_end = 1'b0;
if (frame_q == 1'b1 && ss_q == 1'b0)
frame_start = 1'b1;
if (frame_q == 1'b0 && ss_q == 1'b1)
frame_end = 1'b1;
if (ss_q) begin
bit_ct_d = 3'b0;
data_d = din;
miso_d = data_q[7];
end else begin
if (!sck_old_q && sck_q) begin // rising edge
data_d = {data_q[6:0], mosi_q};
bit_ct_d = bit_ct_q + 1'b1;
if (bit_ct_q == 3'b111) begin
dout_d = {data_q[6:0], mosi_q};
done_d = 1'b1;
end
end else if (sck_old_q && !sck_q) begin // falling edge
miso_d = data_q[7];
end else if (!sck_q) begin
if (bit_ct_q == 3'd0) begin
miso_d = din[7];
data_d = din;
end
end
end
end
always @(posedge clk) begin
if (rst) begin
done_q <= 1'b0;
bit_ct_q <= 3'b0;
dout_q <= 8'b0;
miso_q <= 1'b1;
end else begin
done_q <= done_d;
bit_ct_q <= bit_ct_d;
dout_q <= dout_d;
miso_q <= miso_d;
end
sck_q <= sck_d;
mosi_q <= mosi_d;
ss_q <= ss_d;
data_q <= data_d;
sck_old_q <= sck_old_d;
frame_q <= frame_d;
end
endmodule
|
module mojo_com_logic #(
\tparameter ADDR_SPACE = 256
)(
\tinput clk,
\tinput rst,
\t//SPI Addressing Interface
\tinput [ADDR_SPACE_BITS-1:0] reg_addr,
\tinput write,
\tinput new_req,
\tinput [7:0] write_value,
\toutput [7:0] read_value,
\tinput in_transaction,
\t//Interface, doesn't guarantee atomicity
\toutput [8*ADDR_SPACE-1:0] rx_arr,
\toutput rx_busy,
\toutput new_rx,
\tinput [8*ADDR_SPACE-1:0] tx_arr,
\toutput tx_busy
\t//DEBUG params
\t/*
\t, output [ADDR_BIT_COUNT - 1:0] cur_addr,
\toutput [ADDR_BIT_COUNT - 1:0] end_addr,
\toutput [STATE_SIZE - 1:0] cur_state
\t*/
);
parameter ADDR_SPACE_BITS = $clog2(ADDR_SPACE);
parameter WORD_SIZE = 8;
parameter ADDR_BITS = ADDR_SPACE * 8; //Number of bits in addressable arrs
parameter ADDR_BIT_COUNT = $clog2(ADDR_BITS); //Number of bits to address all bits
//Interface setup
reg [ADDR_BITS-1:0] rx_arr_q, rx_arr_d;
reg rx_busy_q, rx_busy_d, tx_busy_q, tx_busy_d, new_rx_q, new_rx_d;
assign rx_arr = rx_arr_q;
assign rx_busy = rx_busy_q;
assign new_rx = new_rx_q;
assign tx_busy = tx_busy_q;
//SPI addressing setup
reg [7:0] read_value_d, read_value_q;
assign read_value = read_value_q;
//Other stuff
reg old_write_d, old_write_q, old_transaction_d, old_transaction_q;
always @(*) begin
read_value_d = read_value_q;
\told_write_d = old_write_q;
\told_transaction_d = in_transaction;
\trx_busy_d = in_transaction;
\ttx_busy_d = in_transaction;
\tnew_rx_d = new_rx_q;
\trx_arr_d = rx_arr_q;
if (new_req) begin
\t\t//Read by default
\t\tread_value_d = tx_arr[{reg_addr,3'b0}+:WORD_SIZE];
\t\t//Write in certain cases
\t\tif (write) begin
\t\t\trx_arr_d[{reg_addr,3'b0}+:WORD_SIZE] = write_value;
\t\tend
end
\tif (in_transaction) begin
\t\told_write_d = write;
\tend else begin
\t\t//Falling edge of transaction and was written
\t\tnew_rx_d = old_transaction_q & old_write_q;
\tend
end
always @(posedge clk) begin
if (rst) begin
\t\tread_value_q <= 0;
\t\trx_busy_q <= 0;
\t\ttx_busy_q <= 0;
\t\tnew_rx_q <= 0;
\t\trx_arr_q <= 0;
\t\told_write_q <= 0;
\t\told_transaction_q <= 0;
end else begin
\t\tread_value_q <= read_value_d;
\t\trx_busy_q <= rx_busy_d;
\t\ttx_busy_q <= tx_busy_d;
\t\tnew_rx_q <= new_rx_d;
\t\trx_arr_q <= rx_arr_d;
\t\told_write_q <= old_write_d;
\t\told_transaction_q <= old_transaction_d;
end
end
endmodule
|
module mojo_com #(
\tparameter ADDR_SPACE = 64 //addr is last 6 bits
)(
\tinput clk,
\tinput rst,
\t//SPI connections
\tinput ss,
\tinput sck,
\tinput mosi,
\toutput miso,
\t//Interface, doesn't guarantee atomicity
\toutput [8*ADDR_SPACE-1:0] rx_arr,
\toutput rx_busy,
\toutput new_rx,
\tinput [8*ADDR_SPACE-1:0] tx_arr,
\toutput tx_busy
);
parameter ADDR_BITS = $clog2(ADDR_SPACE);
//SPI addressing setup
wire [ADDR_BITS-1:0] reg_addr;
wire [7:0] write_value, read_value;
wire write, new_req, in_transaction;
spi_addressing spi_interface(
\t.clk(clk),
\t.rst(rst),
\t//SPI pins
\t.spi_ss(ss),
\t.spi_sck(sck),
\t.spi_mosi(mosi),
\t.spi_miso(miso),
\t//Interface
\t.reg_addr(reg_addr),
\t.write(write),
\t.new_req(new_req),
\t.write_value(write_value),
\t.read_value(read_value),
\t.in_transaction(in_transaction)
);
mojo_com_logic #(.ADDR_SPACE(ADDR_SPACE)) com_logic (
\t.clk(clk),
\t.rst(rst),
\t//SPI addressing interface
\t.reg_addr(reg_addr),
\t.write(write),
\t.new_req(new_req),
\t.write_value(write_value),
\t.read_value(read_value),
\t.in_transaction(in_transaction),
\t//Interface
\t.rx_arr(rx_arr),
\t.rx_busy(rx_busy),
\t.new_rx(new_rx),
\t.tx_arr(tx_arr),
\t.tx_busy(tx_busy)
);
endmodule
|
module message_printer (
input clk,
input rst,
output [7:0] tx_data,
output reg new_tx_data,
input tx_busy,
input [7:0] rx_data,
input new_rx_data
);
localparam STATE_SIZE = 2;
localparam IDLE = 0,
PRINT_MESSAGE = 1,
\t\t\t WAIT_FIRST = 2,
\t\t\t END = 3;
localparam MESSAGE_LEN = 2;
reg [STATE_SIZE-1:0] state_d, state_q;
reg [3:0] addr_d, addr_q;
reg [7:0] send_data_d, send_data_q;
wire [7:0] s_data;
message_rom message_rom (
.clk(clk),
.addr(addr_q),
.data(s_data)
);
assign tx_data = send_data_q;
always @(*) begin
state_d = state_q; // default values
addr_d = addr_q; // needed to prevent latches
new_tx_data = 1\'b0;
\t send_data_d = send_data_q;
case (state_q)
IDLE: begin
addr_d = 4\'d0;
if (new_rx_data) begin
\t\t\t\t\t send_data_d = rx_data;
state_d = WAIT_FIRST;
\t\t\t\tend
end
\t\t WAIT_FIRST: begin
\t\t\t\tif (!tx_busy) begin
\t\t\t\t\tnew_tx_data = 1\'b1;
\t\t\t\t\tstate_d = PRINT_MESSAGE;
\t\t\t\tend
\t\t end
PRINT_MESSAGE: begin
if (!tx_busy) begin
new_tx_data = 1\'b1;
addr_d = addr_q + 1\'b1;
if (addr_q == MESSAGE_LEN-1) begin
state_d = END;
\t\t\t\t\t\t send_data_d = "\
";
\t\t\t\t\t end
end
end
\t\t END: begin
\t\t\t\tif(!tx_busy) begin
\t\t\t\t\tnew_tx_data = 1\'b1;
\t\t\t\t\tstate_d = IDLE;
\t\t\t\tend
\t\t end
default: state_d = IDLE;
endcase
end
always @(posedge clk) begin
if (rst) begin
state_q <= IDLE;
\t\t send_data_q <= "\
";
end else begin
state_q <= state_d;
\t\t send_data_q <= send_data_d;
end
addr_q <= addr_d;
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:09:24 03/26/2015
// Design Name: mojo_com
// Module Name: /home/michael/Projects/mojo/ultrasonic-fountain/hardware/mojo_com_test.v
// Project Name: Mojo-Base
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: mojo_com
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module mojo_com_test;
\t// Inputs
\treg clk;
\treg rst;
\t//reg rx;
\tlocalparam DATA_SIZE = 1;
\treg [DATA_SIZE * 8 -1:0] tx_arr;
\t// Outputs
\t//wire tx;
\treg [DATA_SIZE * 8 -1:0] rx_arr;
\t//wire rx_busy;
\t//wire new_rx;
\t//wire tx_busy;
\t// Instantiate the Unit Under Test (UUT)
\t/*
\tmojo_com uut (
\t\t.clk(clk),
\t\t.rst(rst),
\t\t.tx(tx),
\t\t.rx(rx),
\t\t.rx_arr(rx_arr),
\t\t.rx_busy(rx_busy),
\t\t.new_rx(new_rx),
\t\t.tx_arr(tx_arr),
\t\t.tx_busy(tx_busy)
\t);
\t*/
\tassign tx_arr = 8'h01;
\t\t//{8'h01,8'h01,8'h02,8'hff,96'b0};
\treg [7:0] tmp_tx_q, tmp_tx_d;
\treg [0:0] addr_q, addr_d;
\talways @(*) begin
\t\taddr_d = addr_q + 1;
\t\ttmp_tx_d = tx_arr[addr_q+:7];
rx_arr[addr_q+:7] = tmp_tx_q;
\tend
\talways @(posedge clk) begin
\t\tif(rst) begin
\t\t\taddr_q <= 0;
\t\t\ttmp_tx_q <= 0;
\t\tend else begin
\t\t\taddr_q <= addr_d;
\t\t\ttmp_tx_q <= tmp_tx_d;
\t\tend
\tend
\tinitial begin
\t\t// Initialize Inputs
clk = 1'b0;
rst = 1'b1;
repeat(4) #10 clk = ~clk;
rst = 1'b0;
forever #10 clk = ~clk; // generate a clock
end
\t
initial begin
@(negedge rst); // wait for reset
repeat(17) @(posedge clk); //wait for trigger to finish, 10us
$finish;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:57:12 03/23/2015
// Design Name:
// Module Name: message_rom
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module message_rom (
input clk,
input [3:0] addr,
output [7:0] data
);
wire [7:0] rom_data [13:0];
assign rom_data[0] = "H";
assign rom_data[1] = "e";
assign rom_data[2] = "l";
assign rom_data[3] = "l";
assign rom_data[4] = "o";
assign rom_data[5] = " ";
assign rom_data[6] = "W";
assign rom_data[7] = "o";
assign rom_data[8] = "r";
assign rom_data[9] = "l";
assign rom_data[10] = "d";
assign rom_data[11] = "!";
assign rom_data[12] = "\
";
assign rom_data[13] = "\\r";
reg [7:0] data_d, data_q;
assign data = data_q;
always @(*) begin
if (addr > 4\'d13)
data_d = " ";
else
data_d = rom_data[addr];
end
always @(posedge clk) begin
data_q <= data_d;
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:07:01 03/24/2015
// Design Name: hcsr04
// Module Name: /home/michael/Projects/mojo/ultrasonic-fountain/hcsr04_test.v
// Project Name: Mojo-Base
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: hcsr04
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module hcsr04_test;
\t// Inputs
\treg rst;
\treg clk;
\treg measure;
\treg echo;
\t// Outputs
\twire [15:0] ticks;
\twire valid;
\twire trigger;
\twire clk_10us;
\tclk_divider #(.DIV(500)) clk_10usmodule(
\t\t.rst(rst),
\t\t.clk(clk),
\t\t.div_clk(clk_10us)
\t);
\t// Instantiate the Unit Under Test (UUT)
\thcsr04 #(
\t\t.TRIGGER_DURATION(1),
\t\t.MAX_COUNT(3800)
\t)\tuut (
\t\t.rst(rst),
\t\t.clk(clk),
\t\t.tclk(clk_10us),
\t\t.measure(measure),
\t\t.echo(echo),
\t\t.ticks(ticks),
\t\t.valid(valid),
\t\t.trigger(trigger)
\t);
\tinitial begin
\t\t// Initialize Inputs
\t\trst = 0;
\t\tclk = 0;
\t\tmeasure = 0;
\t\techo = 0;
clk = 1'b0;
rst = 1'b1;
repeat(4) #10 clk = ~clk;
rst = 1'b0;
forever #10 clk = ~clk; // generate a clock
end
initial begin
measure = 0; // initial value
@(negedge rst); // wait for reset
measure = 1;
repeat(5000) @(posedge clk); //wait for trigger to finish, 10us
echo = 1;
repeat(100000) @(posedge clk); //echo for 10ms
\t\t echo = 0;
\t\t repeat (100000) @(posedge clk);
$finish;
end
endmodule
|
module serial_tx #(
parameter CLK_PER_BIT = 50
)(
input clk,
input rst,
output tx,
input block,
output busy,
input [7:0] data,
input new_data
);
// clog2 is 'ceiling of log base 2' which gives you the number of bits needed to store a value
parameter CTR_SIZE = $clog2(CLK_PER_BIT);
localparam STATE_SIZE = 2;
localparam IDLE = 2'd0,
START_BIT = 2'd1,
DATA = 2'd2,
STOP_BIT = 2'd3;
reg [CTR_SIZE-1:0] ctr_d, ctr_q;
reg [2:0] bit_ctr_d, bit_ctr_q;
reg [7:0] data_d, data_q;
reg [STATE_SIZE-1:0] state_d, state_q = IDLE;
reg tx_d, tx_q;
reg busy_d, busy_q;
reg block_d, block_q;
assign tx = tx_q;
assign busy = busy_q;
always @(*) begin
block_d = block;
ctr_d = ctr_q;
bit_ctr_d = bit_ctr_q;
data_d = data_q;
state_d = state_q;
busy_d = busy_q;
case (state_q)
IDLE: begin
if (block_q) begin
busy_d = 1'b1;
tx_d = 1'b1;
end else begin
busy_d = 1'b0;
tx_d = 1'b1;
bit_ctr_d = 3'b0;
ctr_d = 1'b0;
if (new_data) begin
data_d = data;
state_d = START_BIT;
busy_d = 1'b1;
end
end
end
START_BIT: begin
busy_d = 1'b1;
ctr_d = ctr_q + 1'b1;
tx_d = 1'b0;
if (ctr_q == CLK_PER_BIT - 1) begin
ctr_d = 1'b0;
state_d = DATA;
end
end
DATA: begin
busy_d = 1'b1;
tx_d = data_q[bit_ctr_q];
ctr_d = ctr_q + 1'b1;
if (ctr_q == CLK_PER_BIT - 1) begin
ctr_d = 1'b0;
bit_ctr_d = bit_ctr_q + 1'b1;
if (bit_ctr_q == 7) begin
state_d = STOP_BIT;
end
end
end
STOP_BIT: begin
busy_d = 1'b1;
tx_d = 1'b1;
ctr_d = ctr_q + 1'b1;
if (ctr_q == CLK_PER_BIT - 1) begin
state_d = IDLE;
end
end
default: begin
state_d = IDLE;
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_q <= IDLE;
tx_q <= 1'b1;
end else begin
state_q <= state_d;
tx_q <= tx_d;
end
block_q <= block_d;
data_q <= data_d;
bit_ctr_q <= bit_ctr_d;
ctr_q <= ctr_d;
busy_q <= busy_d;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:47:35 03/24/2015
// Design Name:
// Module Name: clk_divider
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: DIV min is 2, don't do 1 or 0
//
//////////////////////////////////////////////////////////////////////////////////
module clk_divider #(
\tparameter DIV = 2
)(
\tinput rst,
\tinput clk,
\toutput div_clk
);
\t
parameter CTR_SIZE = $clog2(DIV);
\t reg [CTR_SIZE-1:0] ctr_d, ctr_q;
\t reg div_clk_d, div_clk_q;
\t assign div_clk = div_clk_q;
\t
\t always @(*) begin
\t\tdiv_clk_d = div_clk_q;
\t\tctr_d = ctr_q + 1;
\t\t//Div clk goes high at 0, and lasts period of clk
\t\tif (ctr_q == 0) begin
\t\t\tdiv_clk_d = 1;
\t\tend else begin
\t\t\tdiv_clk_d = 0;
\t\tend
\t\t//Restart when reach DIV cnts
\t\tif(ctr_q == DIV-1) begin
\t\t\tctr_d = 0;
\t\tend
\t end
\t always @(posedge clk) begin
\t\tif (rst) begin
\t\t\tdiv_clk_q <= 0;
\t\t\tctr_q <= 0;
\t\tend else begin
\t\t\tdiv_clk_q <= div_clk_d;
\t\t\tctr_q <= ctr_d;
\t\tend
\t end
\t
endmodule
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