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// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
// Date : Sat May 16 15:33:04 2015
// Host : Dtysky running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// b:/Complex_Mind/FPGA-Imaging-Library/Point/ContrastTransform/HDL/ContrastTransform.srcs/sources_1/ip/Multiplier12x24CT/Multiplier12x24CT_funcsim.v
// Design : Multiplier12x24CT
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "mult_gen_v12_0,Vivado 2014.4" *) (* CHECK_LICENSE_TYPE = "Multiplier12x24CT,mult_gen_v12_0,{}" *)
(* core_generation_info = "Multiplier12x24CT,mult_gen_v12_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=artix7,C_HAS_CE=0,C_HAS_SCLR=1,C_LATENCY=3,C_A_WIDTH=12,C_A_TYPE=1,C_B_WIDTH=24,C_B_TYPE=1,C_OUT_HIGH=35,C_OUT_LOW=12,C_MULT_TYPE=1,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}" *)
(* NotValidForBitStream *)
module Multiplier12x24CT
(CLK,
A,
B,
SCLR,
P);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) input CLK;
input [11:0]A;
input [23:0]B;
(* x_interface_info = "xilinx.com:signal:reset:1.0 sclr_intf RST" *) input SCLR;
output [23:0]P;
wire [11:0]A;
wire [23:0]B;
wire CLK;
wire [23:0]P;
wire SCLR;
wire [47:0]NLW_U0_PCASC_UNCONNECTED;
wire [1:0]NLW_U0_ZERO_DETECT_UNCONNECTED;
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "12" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "24" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "3" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "1" *)
(* C_OPTIMIZE_GOAL = "1" *)
(* C_OUT_HIGH = "35" *)
(* C_OUT_LOW = "12" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* DONT_TOUCH *)
(* downgradeipidentifiedwarnings = "yes" *)
Multiplier12x24CT_mult_gen_v12_0__parameterized0 U0
(.A(A),
.B(B),
.CE(1\'b1),
.CLK(CLK),
.P(P),
.PCASC(NLW_U0_PCASC_UNCONNECTED[47:0]),
.SCLR(SCLR),
.ZERO_DETECT(NLW_U0_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule
(* ORIG_REF_NAME = "mult_gen_v12_0" *) (* C_VERBOSITY = "0" *) (* C_MODEL_TYPE = "0" *)
(* C_OPTIMIZE_GOAL = "1" *) (* C_XDEVICEFAMILY = "artix7" *) (* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *) (* C_LATENCY = "3" *) (* C_A_WIDTH = "12" *)
(* C_A_TYPE = "1" *) (* C_B_WIDTH = "24" *) (* C_B_TYPE = "1" *)
(* C_OUT_HIGH = "35" *) (* C_OUT_LOW = "12" *) (* C_MULT_TYPE = "1" *)
(* C_CE_OVERRIDES_SCLR = "0" *) (* C_CCM_IMP = "0" *) (* C_B_VALUE = "10000001" *)
(* C_HAS_ZERO_DETECT = "0" *) (* C_ROUND_OUTPUT = "0" *) (* C_ROUND_PT = "0" *)
(* downgradeipidentifiedwarnings = "yes" *)
module Multiplier12x24CT_mult_gen_v12_0__parameterized0
(CLK,
A,
B,
CE,
SCLR,
ZERO_DETECT,
P,
PCASC);
input CLK;
input [11:0]A;
input [23:0]B;
input CE;
input SCLR;
output [1:0]ZERO_DETECT;
output [23:0]P;
output [47:0]PCASC;
wire [11:0]A;
wire [23:0]B;
wire CE;
wire CLK;
wire [23:0]P;
wire [47:0]PCASC;
wire SCLR;
wire [1:0]ZERO_DETECT;
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "12" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "24" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "3" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "1" *)
(* C_OPTIMIZE_GOAL = "1" *)
(* C_OUT_HIGH = "35" *)
(* C_OUT_LOW = "12" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* downgradeipidentifiedwarnings = "yes" *)
Multiplier12x24CT_mult_gen_v12_0_viv__parameterized0 i_mult
(.A(A),
.B(B),
.CE(CE),
.CLK(CLK),
.P(P),
.PCASC(PCASC),
.SCLR(SCLR),
.ZERO_DETECT(ZERO_DETECT));
endmodule
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`pragma protect key_block
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8336)
`pragma protect data_block
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vc+9LhvUp7z5PsPiBNc=
`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
/*
:Project
FPGA-Imaging-Library
:Design
FixedRoundSigned
:Function
Round for signed fixed number.
Give the first output after 3 cycles.
:Module
Main module
:Version
1.0
:Modified
2015-05-16
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module FixedRoundSigned1(
\tclk,
\tfixed_num,
\tround,
\toverflow
\t);
\tparameter num_width = 42;
\tparameter fixed_pos = 16;
\tparameter res_width = 12;
\tinput clk;
\tinput signed [num_width - 1 : 0] fixed_num;
\toutput reg signed [res_width : 0] round;
\toutput reg overflow;
\treg signed [num_width - 1 : 0] num_orig;
\treg num_orig_sflag, num_orig_rflag, reg_overflow;
\treg signed [res_width : 0] num_comp;
\talways @(posedge clk) begin
\t\tnum_orig <= fixed_num[num_width - 1] == 0 ? fixed_num :
\t\t\t{fixed_num[num_width - 1], ~(fixed_num[num_width - 2 : 0] - 1)};
\t\tnum_comp <= num_orig[num_width - 1] == 0 ?
\t\t\t{num_orig[num_width - 1], num_orig[res_width + fixed_pos - 1 : fixed_pos]} :
\t\t\t{num_orig[num_width - 1], ~num_orig[res_width + fixed_pos - 1 : fixed_pos] + 1};
\t\treg_overflow <= num_orig[num_width - 2 : res_width + fixed_pos] == 0 ? 0 : 1;
\t\toverflow <= reg_overflow;
\t\tnum_orig_sflag <= num_orig[num_width - 1];
\t\tnum_orig_rflag <= num_orig[fixed_pos - 1];
\t\t//Why not use num_comp[25] to judge? : if 0
\t\tcase(num_orig_sflag)
\t\t\t0 : round <= num_orig_rflag == 0 ? num_comp : num_comp + 1;
\t\t\t1 : round <= num_orig_rflag == 0 ? num_comp : num_comp - 1;
\t\t\tdefault : /* default */;
\t\tendcase
\tend
endmodule
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
CountGenerator
:Function
For generating counts from xilinx.
Give the first output after 0 cycle while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-31
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module CountGenerator(
\tclk,
\trst_n,
\tin_enable,
\tin_data,
\tout_ready,
\tout_data,
\tcount_x,
\tcount_y);
\t/*
\t::description
\tThis module's working mode.
\t::range
\t0 for Pipline, 1 for Req-ack
\t*/
\tparameter work_mode = 0;
\t/*
\t::description
\tThis module's WR mode.
\t::range
\t0 for Write, 1 for Read
\t*/
\tparameter data_width = 8;
\t/*
\t::description
\tWidth of image.
\t::range
\t1 - 4096
\t*/
\tparameter im_width = 320;
\t/*
\t::description
\tHeight of image.
\t::range
\t1 - 4096
\t*/
\tparameter im_height = 240;
\t/*
\t::description
\tThe bits of width of image.
\t::range
\tDepend on width of image
\t*/
\tparameter im_width_bits = 9;
\t/*
\t::description
\tClock.
\t*/
\tinput clk;
\t/*
\t::description
\tReset, active low.
\t*/
\tinput rst_n;
\t/*
\t::description
\tInput data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
\t*/
\tinput in_enable;
\t/*
\t::description
\tInput data, it must be synchronous with in_enable.
\t*/
\tinput [data_width - 1 : 0] in_data;
\t/*
\t::description
\tOutput data ready, in both two mode, it will be high while the out_data can be read.
\t*/
\toutput out_ready;
\t/*
\t::description
\tOutput data, it will be synchronous with out_ready.
\t*/
\toutput[data_width - 1 : 0] out_data;
\t/*
\t::description
\tCount for x.
\t*/
\toutput reg[im_width_bits - 1 : 0] count_x;
\t/*
\t::description
\tCount for y.
\t*/
\toutput reg[im_width_bits - 1 : 0] count_y;
\tassign out_ready = in_enable;
\tassign out_data = out_ready ? in_data : 0;
\tgenerate
\t\tif(work_mode == 0) begin
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\tcount_x <= 0;
\t\t\t\telse if(count_x == im_width - 1)
\t\t\t\t\tcount_x <= 0;
\t\t\t\telse
\t\t\t\t\tcount_x <= count_x + 1;
\t\t\tend
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\tcount_y <= 0;
\t\t\t\telse if(count_x == im_width - 1 && count_y == im_height - 1)
\t\t\t\t\tcount_y <= 0;
\t\t\t\telse if(count_x == im_width - 1)
\t\t\t\t\tcount_y <= count_y + 1;
\t\t\t\telse
\t\t\t\t\tcount_y <= count_y;
\t\t\tend
\t\tend else begin
\t\t\talways @(posedge in_enable or negedge rst_n) begin
\t\t\t\tif(~rst_n)
\t\t\t\t\tcount_x <= 0;
\t\t\t\telse if(count_x == im_width - 1)
\t\t\t\t\tcount_x <= 0;
\t\t\t\telse
\t\t\t\t\tcount_x <= count_x + 1;
\t\t\tend
\t\t\talways @(posedge in_enable or negedge rst_n) begin
\t\t\t\tif(~rst_n)
\t\t\t\t\tcount_y <= 0;
\t\t\t\telse if(count_x == im_width - 1 && count_y == im_height - 1)
\t\t\t\t\tcount_y <= 0;
\t\t\t\telse if(count_x == im_width - 1)
\t\t\t\t\tcount_y <= count_y + 1;
\t\t\t\telse
\t\t\t\t\tcount_y <= count_y;
\t\t\tend
\t\tend
\tendgenerate
endmodule
|
/*
:Project
FPGA-Imaging-Library
:Design
True2Comp
:Function
Convert true code to complemental code.
:Module
Main module
:Version
1.0
:Modified
2015-05-01
Copyright (C) 2015 Dai Tianyu (dtysky)
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://ifl.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module True2Comp(
\ttrue,
\tcomplement);
\tparameter data_channel = 1;
\tparameter data_width = 17;
\tinput[data_channel * data_width - 1 : 0] true;
\toutput[data_channel * data_width - 1 : 0] complement;
\tgenvar i;
\tgenerate
\t\t`define h (i + 1) * data_width - 1
\t\t`define l i * data_width
\t\tfor (i = 0; i < data_channel; i = i + 1) begin
\t\t\tassign complement[`h : `l] = true[`h] == 0 ?
\t\t\t\ttrue[`h : `l] : {1'b1, ~true[`h - 1 : `l] + 1};
\t\tend
\t\t`undef h
\t\t`undef l
\tendgenerate
endmodule
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
RankFilter
:Function
Local filter - Rank filter, it always used for denoising with preserving edge.
It will give the first output after sum_stage + 2 cycles while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-21
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
`define full_win_width window_width * window_width
module RankFifter(
\tclk,
\trst_n,
\trank,
\tin_enable,
\tin_data,
\tout_ready,
\tout_data);
\t/*
\t::description
\tThis module's working mode.
\t::range
\t0 for Pipeline, 1 for Req-ack
\t*/
\tparameter[0 : 0] work_mode = 0;
\t/*
\t::description
\tThe width(and height) of window.
\t::range
\t2 - 15
\t*/
\tparameter[3 : 0] window_width = 3;
\t/*
\t::description
\tColor's bit width.
\t::range
\t1 - 12
\t*/
\tparameter[3 : 0] color_width = 8;
\t/*
\t::description
\tStage of sum.
\t::range
\tDepend on width of window, int(log8(window_width^2)) + 1
\t*/
\tparameter[2 : 0] sum_stage = 2;
\t/*
\t::description
\tWidth bits of full size of window.
\t::range
\tDepend on width of window
\t*/
\tparameter full_win_bits = 4;
\t/*
\t::description
\tClock.
\t*/
\tinput clk;
\t/*
\t::description
\tReset, active low.
\t*/
\tinput rst_n;
\t/*
\t::description
\tFilter's rank, if half of full size of window, this module working as median filter, etc.
\t*/
\tinput[full_win_bits - 1 : 0] rank;
\t/*
\t::description
\tInput data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
\t*/
\tinput in_enable;
\t/*
\t::description
\tInput data, it must be synchronous with in_enable.
\t*/
\tinput [color_width * window_width * window_width - 1 : 0] in_data;
\t/*
\t::description
\tOutput data ready, in both two mode, it will be high while the out_data can be read.
\t*/
\toutput out_ready;
\t/*
\t::description
\tOutput data, it will be synchronous with out_ready.
\t*/
\toutput[color_width - 1 : 0] out_data;
\t
\treg[color_width - 1 : 0] reg_in_data[0 : `full_win_width - 1];
\treg[`full_win_width - 1 : 0] big_flag[0 : `full_win_width - 1];
\twire[`full_win_width - 1 : 0] rank_list;
\twire[full_win_bits - 1 : 0] rank_res;
\treg[3 : 0] con_enable;
\treg[color_width - 1 : 0] reg_out_data;
\tgenvar i, j, k;
\tgenerate
\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\tif(~rst_n || ~in_enable)
\t\t\t\tcon_enable <= 0;
\t\t\telse if(con_enable == sum_stage + 3)
\t\t\t\tcon_enable <= con_enable;
\t\t\telse
\t\t\t\tcon_enable <= con_enable + 1;
\t\tend
\t\tassign out_ready = con_enable == sum_stage + 3 ? 1 : 0;
\t\tfor (i = 0; i < `full_win_width; i = i + 1) begin
\t\t\tif(work_mode == 0) begin
\t\t\t\talways @(*)
\t\t\t\t\treg_in_data[i] = in_data[(i + 1) * color_width - 1 : i * color_width];
\t\t\tend else begin
\t\t\t\talways @(posedge in_enable)
\t\t\t\t\treg_in_data[i] = in_data[(i + 1) * color_width - 1 : i * color_width];
\t\t\tend
\t\tend
\t\tif(work_mode == 0) begin : pipemode
\t\t\tfor (i = 0; i < sum_stage + 2; i = i + 1) begin : buffer
\t\t\t\treg[color_width - 1 : 0] b[0 : `full_win_width - 1];
\t\t\t\tfor (j = 0; j < `full_win_width; j = j + 1) begin
\t\t\t\t\tif(i == 0) begin
\t\t\t\t\t\talways @(posedge clk)
\t\t\t\t\t\t\tb[j] <= reg_in_data[j];
\t\t\t\t\tend else begin
\t\t\t\t\t\talways @(posedge clk)
\t\t\t\t\t\t\tb[j] <= buffer[i - 1].b[j];
\t\t\t\t\tend
\t\t\t\tend
\t\t\tend
\t\tend
\t\tfor (i = 0; i < `full_win_width; i = i + 1) begin
\t\t\talways @(posedge clk)
\t\t\t\tbig_flag[i][i] <= 0;
\t\tend
\t\tfor (i = 0; i < `full_win_width; i = i + 1) begin
\t\t\tfor (j = i + 1; j < `full_win_width; j = j + 1) begin
\t\t\t\talways @(posedge clk) begin
\t\t\t\t\tif(reg_in_data[i] >= reg_in_data[j]) begin
\t\t\t\t\t\tbig_flag[i][j] <= 1;
\t\t\t\t\t\tbig_flag[j][i] <= 0;
\t\t\t\t\tend else begin
\t\t\t\t\t\tbig_flag[i][j] <= 0;
\t\t\t\t\t\tbig_flag[j][i] <= 1;
\t\t\t\t\tend
\t\t\t\tend
\t\t\tend
\t\tend
\t\tfor (i = 0; i < sum_stage; i = i + 1) begin : pipe
\t\t\tfor (k = 0; k < `full_win_width; k = k + 1) begin : pixel
\t\t\t\treg[((`full_win_width - 1) >> 3 * (sum_stage - i)) + 3 : 0] sum[0 : (`full_win_width - 1) >> 3 * (i + 1)];
\t\t\t\tfor (j = 0; j < ((`full_win_width - 1) >> 3 * (i + 1)) + 1; j = j + 1) begin
\t\t\t\t\tif(i == 0) begin
\t\t\t\t\t\tif(`full_win_width - j * 8 >= 8) begin
\t\t\t\t\t\t\talways @(posedge clk)
\t\t\t\t\t\t\t\tsum[j] <= big_flag[k][8 * j + 0] + big_flag[k][8 * j + 1] + big_flag[k][8 * j + 2] + big_flag[k][8 * j + 3] + big_flag[k][8 * j + 4] + big_flag[k][8 * j + 5] + big_flag[k][8 * j + 6] + big_flag[k][8 * j + 7];
\t\t\t\t\t\tend else begin
\t\t\t\t\t\t\tcase (`full_win_width % 8)
\t\t\t\t\t\t\t\t1 : always @(posedge clk)
\t\t\t\t\t\t\t\t\t\tsum[j] <= big_flag[k][8 * j + 0];
\t\t\t\t\t\t\t\t2 : always @(posedge clk)
\t\t\t\t\t\t\t\t\t\tsum[j] <= big_flag[k][8 * j + 0] + big_flag[k][8 * j + 1];
\t\t\t\t\t\t\t\t3 : always @(posedge clk)
\t\t\t\t\t\t\t\t\t\tsum[j] <= big_flag[k][8 * j + 0] + big_flag[k][8 * j + 1] + big_flag[k][8 * j + 2];
\t\t\t\t\t\t\t\t4 : always @(posedge clk)
\t\t\t\t\t\t\t\t\t\tsum[j] <= big_flag[k][8 * j + 0] + big_flag[k][8 * j + 1] + big_flag[k][8 * j + 2] + big_flag[k][8 * j + 3];
\t\t\t\t\t\t\t\t5 : always @(posedge clk)
\t\t\t\t\t\t\t\t\t\tsum[j] <= big_flag[k][8 * j + 0] + big_flag[k][8 * j + 1] + big_flag[k][8 * j + 2] + big_flag[k][8 * j + 3] + big_flag[k][8 * j + 4];
\t\t\t\t\t\t\t\t6 : always @(posedge clk)
\t\t\t\t\t\t\t\t\t\tsum[j] <= big_flag[k][8 * j + 0] + big_flag[k][8 * j + 1] + big_flag[k][8 * j + 2] + big_flag[k][8 * j + 3] + big_flag[k][8 * j + 4] + big_flag[k][8 * j + 5];
\t\t\t\t\t\t\t\t7 : always @(posedge clk)
\t\t\t\t\t\t\t\t\t\tsum[j] <= big_flag[k][8 * j + 0] + big_flag[k][8 * j + 1] + big_flag[k][8 * j + 2] + big_flag[k][8 * j + 3] + big_flag[k][8 * j + 4] + big_flag[k][8 * j + 5] + big_flag[k][8 * j + 6];
\t\t\t\t\t\t\t\tdefault : /* default */;
\t\t\t\t\t\t\tendcase
\t\t\t\t\t\tend
\t\t\t\t\tend else begin
\t\t\t\t\t\tif((`full_win_width >> 3 * i) - j * 8 >= 8) begin
\t\t\t\t\t\t\talways @(posedge clk)
\t\t\t\t\t\t\t\tsum[j] <= pipe[i - 1].pixel[k].sum[8 * j + 0] + pipe[i - 1].pixel[k].sum[8 * j + 1] + pipe[i - 1].pixel[k].sum[8 * j + 2] + pipe[i - 1].pixel[k].sum[8 * j + 3] + pipe[i - 1].pixel[k].sum[8 * j + 4] + pipe[i - 1].pixel[k].sum[8 * j + 5] + pipe[i - 1].pixel[k].sum[8 * j + 6] + pipe[i - 1].pixel[k].sum[8 * j + 7];
\t\t\t\t\t\tend else begin
\t\t\t\t\t\t\tcase ((`full_win_width >> 3 * i) % 8 + 1)
\t\t\t\t\t\t\t\t1 : always @(posedge clk)
\t\t\t\t\t\t\t\t\t\tsum[j] <= pipe[i - 1].pixel[k].sum[8 * j + 0];
\t\t\t\t\t\t\t\t2 : always @(posedge clk)
\t\t\t\t\t\t\t\t\t\tsum[j] <= pipe[i - 1].pixel[k].sum[8 * j + 0] + pipe[i - 1].pixel[k].sum[8 * j + 1];
\t\t\t\t\t\t\t\t3 : always @(posedge clk)
\t\t\t\t\t\t\t\t\t\tsum[j] <= pipe[i - 1].pixel[k].sum[8 * j + 0] + pipe[i - 1].pixel[k].sum[8 * j + 1] + pipe[i - 1].pixel[k].sum[8 * j + 2];
\t\t\t\t\t\t\t\t4 : always @(posedge clk)
\t\t\t\t\t\t\t\t\t\tsum[j] <= pipe[i - 1].pixel[k].sum[8 * j + 0] + pipe[i - 1].pixel[k].sum[8 * j + 1] + pipe[i - 1].pixel[k].sum[8 * j + 2] + pipe[i - 1].pixel[k].sum[8 * j + 3];
\t\t\t\t\t\t\t\t5 : always @(posedge clk)
\t\t\t\t\t\t\t\t\t\tsum[j] <= pipe[i - 1].pixel[k].sum[8 * j + 0] + pipe[i - 1].pixel[k].sum[8 * j + 1] + pipe[i - 1].pixel[k].sum[8 * j + 2] + pipe[i - 1].pixel[k].sum[8 * j + 3] + pipe[i - 1].pixel[k].sum[8 * j + 4];
\t\t\t\t\t\t\t\t6 : always @(posedge clk)
\t\t\t\t\t\t\t\t\t\tsum[j] <= pipe[i - 1].pixel[k].sum[8 * j + 0] + pipe[i - 1].pixel[k].sum[8 * j + 1] + pipe[i - 1].pixel[k].sum[8 * j + 2] + pipe[i - 1].pixel[k].sum[8 * j + 3] + pipe[i - 1].pixel[k].sum[8 * j + 4] + pipe[i - 1].pixel[k].sum[8 * j + 5];
\t\t\t\t\t\t\t\t7 : always @(posedge clk)
\t\t\t\t\t\t\t\t\t\tsum[j] <= pipe[i - 1].pixel[k].sum[8 * j + 0] + pipe[i - 1].pixel[k].sum[8 * j + 1] + pipe[i - 1].pixel[k].sum[8 * j + 2] + pipe[i - 1].pixel[k].sum[8 * j + 3] + pipe[i - 1].pixel[k].sum[8 * j + 4] + pipe[i - 1].pixel[k].sum[8 * j + 5] + pipe[i - 1].pixel[k].sum[8 * j + 6];
\t\t\t\t\t\t\t\tdefault : /* default */;
\t\t\t\t\t\t\tendcase
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tend
\t\t\tend
\t\tend
\t\tfor (i = 0; i < `full_win_width; i = i + 1) begin
\t\t\tassign rank_list[i] = pipe[sum_stage - 1].pixel[i].sum[0] == rank ? 1 : 0;
\t\tend
\t\tEncoder #(window_width, full_win_bits) ED(rank_list, rank_res);
\t\tif(work_mode == 0) begin
\t\t\talways @(posedge clk) reg_out_data <= pipemode.buffer[sum_stage + 1].b[rank_res];
\t\tend else begin
\t\t\talways @(posedge clk) reg_out_data <= reg_in_data[rank_res];
\t\tend
\t\tassign out_data = out_ready ? reg_out_data : 0;
\tendgenerate
endmodule
`undef full_win_width
|
module camCap(
\tinput pclk,
\tinput vsync,
\tinput href,
\tinput[7:0] d,
\toutput[16:0] addr,
\toutput reg[15:0] dout,
\toutput reg we,
\toutput wclk
\t);
\treg [15:0] d_latch;
\treg [16:0] address;
\treg [16:0] address_next;
\treg [1:0] wr_hold;
\treg [1:0] cnt;
\tinitial d_latch = 16'b0;
\tinitial address = 19'b0;
\tinitial address_next = 19'b0;
\tinitial wr_hold = 2'b0;
\tinitial cnt = 2'b0;
\tassign addr = address;
\tassign wclk = pclk;
\talways@(posedge pclk)begin
\t\tif( vsync ==1) begin
\t\t\t address <=17'b0;
\t\t\t address_next <= 17'b0;
\t\t\t wr_hold <= 2'b0;
\t\t\t cnt <= 2'b0;
\t\tend else begin
\t\t\tif(address<76800)
\t\t\t\taddress <= address_next;
\t\t\telse
\t\t\t\taddress <= 76800;
\t\t\twe <= wr_hold[1];
\t\t\twr_hold <= {wr_hold[0] , (href &&( ! wr_hold[0])) };
\t\t\td_latch <= {d_latch[7:0] , d};
\t\t\tif (wr_hold[1] == 1) begin
\t\t\t\taddress_next <= address_next+1;
\t\t\t\tdout[15:0] <= d_latch[15:0];
\t\t\tend
\t\tend;
\tend
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: None
// Engineer: Dai Tianyu (dtysky)
//
// Create Date: 2015/04/07 18:01:07
// Design Name:
// Module Name: Mux4
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependenrgb24es:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Mux4(sel, i0, i1, i2, i3, o);
\tparameter data_width = 8;
\tinput[1 : 0] sel;
\tinput[data_width - 1 : 0] i0;
\tinput[data_width - 1 : 0] i1;
\tinput[data_width - 1 : 0] i2;
\tinput[data_width - 1 : 0] i3;
\toutput[data_width - 1 : 0] o;
\t
\treg[data_width - 1 : 0] reg_o;
\talways @(*) begin
\t\tcase (sel)
\t\t\t0 : reg_o <= i0;
\t\t\t1 : reg_o <= i1;
\t\t\t2 : reg_o <= i2;
\t\t\t3 : reg_o <= i3;
\t\t\tdefault : /* default */;
\t\tendcase
\tend
\tassign o = reg_o;
endmodule
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
FrameController2
:Function
Controlling a frame(block ram etc.), writing or reading with counts.
For controlling a BlockRAM from xilinx.
Give the first output after mul_delay + 2 + ram_read_latency cycles while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-25
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module FrameController2(
\tclk,
\trst_n,
\tin_count_x,
\tin_count_y,
\tin_enable,
\tin_data,
\tout_ready,
\tout_data,
\tram_addr);
\t/*
\t::description
\tThis module\'s working mode.
\t::range
\t0 for Pipline, 1 for Req-ack
\t*/
\tparameter work_mode = 0;
\t/*
\t::description
\tThis module\'s WR mode.
\t::range
\t0 for Write, 1 for Read
\t*/
\tparameter wr_mode = 0;
\t/*
\t::description
\tData bit width.
\t*/
\tparameter data_width = 8;
\t/*
\t::description
\tWidth of image.
\t::range
\t1 - 4096
\t*/
\tparameter im_width = 320;
\t/*
\t::description
\tHeight of image.
\t::range
\t1 - 4096
\t*/
\tparameter im_height = 240;
\t/*
\t::description
\tThe bits of width of image.
\t::range
\tDepend on width of image
\t*/
\tparameter im_width_bits = 9;
\t/*
\t::description
\tAddress bit width of a ram for storing this image.
\t::range
\tDepend on im_width and im_height.
\t*/
\tparameter addr_width = 17;
\t/*
\t::description
\tRL of RAM, in xilinx 7-series device, it is 2.
\t::range
\t0 - 15, Depend on your using ram.
\t*/
\tparameter ram_read_latency = 2;
\t/*
\t::description
\tDelay for multiplier.
\t::range
\tDepend on your multilpliers\' configurations
\t*/
\tparameter mul_delay = 3;
\t/*
\t::description
\tClock.
\t*/
\tinput clk;
\t/*
\t::description
\tReset, active low.
\t*/
\tinput rst_n;
\t/*
\t::description
\tInput pixel count for width.
\t*/
\tinput[im_width_bits - 1 : 0] in_count_x;
\t/*
\t::description
\tInput pixel count for height.
\t*/
\tinput[im_width_bits - 1 : 0] in_count_y;
\t/*
\t::description
\tInput data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
\t*/
\tinput in_enable;
\t/*
\t::description
\tInput data, it must be synchronous with in_enable.
\t*/
\tinput [data_width - 1 : 0] in_data;
\t/*
\t::description
\tOutput data ready, in both two mode, it will be high while the out_data can be read.
\t*/
\toutput out_ready;
\t/*
\t::description
\tOutput data, it will be synchronous with out_ready.
\t*/
\toutput[data_width - 1 : 0] out_data;
\t/*
\t::description
\tAddress for ram.
\t*/
\toutput[addr_width - 1 : 0] ram_addr;
\treg[3 : 0] con_enable;
\treg[im_width_bits - 1 : 0] reg_in_count_x;
\treg[im_width_bits - 1 : 0] reg_in_count_y;
\treg[addr_width - 1 : 0] reg_addr;
\twire[11 : 0] mul_a, mul_b;
\twire[23 : 0] mul_p;
\tassign mul_a = {{(12 - im_width_bits){1\'b0}}, in_count_y};
\tassign mul_b = im_width;
\tgenvar i;
\tgenerate
\t\t/*
\t\t::description
\t\tMultiplier for Unsigned 12bits x Unsigned 12bits, used for creating address for frame.
\t\tYou can configure the multiplier by yourself, then change the "mul_delay".
\t\tYou can not change the ports\' configurations!
\t\t*/
\t\tMultiplier12x12FR2 Mul(.CLK(clk), .A(mul_a), .B(mul_b), .SCLR(~rst_n), .P(mul_p));
\t\tfor (i = 0; i < mul_delay; i = i + 1) begin : conut_buffer
\t\t\treg[im_width_bits - 1 : 0] b;
\t\t\tif(i == 0) begin
\t\t\t\talways @(posedge clk)
\t\t\t\t\tb <= in_count_x;
\t\t\tend else begin
\t\t\t\talways @(posedge clk)
\t\t\t\t\tb <= conut_buffer[i - 1].b;
\t\t\tend
\t\tend
\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\tif(~rst_n || ~in_enable) begin
\t\t\t\treg_addr <= 0;
\t\t\tend else begin
\t\t\t\treg_addr <= mul_p + conut_buffer[mul_delay - 1].b;
\t\t\tend
\t\tend
\t\tassign ram_addr = reg_addr;
\t\tif(wr_mode == 0) begin
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\tcon_enable <= 0;
\t\t\t\telse if(con_enable == mul_delay + 1)
\t\t\t\t\tcon_enable <= con_enable;
\t\t\t\telse
\t\t\t\t\tcon_enable <= con_enable + 1;
\t\t\tend
\t\t\tassign out_ready = con_enable == mul_delay + 1 ? 1 : 0;
\t\t\tif(work_mode == 0) begin
\t\t\t\tfor (i = 0; i < mul_delay + 1; i = i + 1) begin : buffer
\t\t\t\t\treg[data_width - 1 : 0] b;
\t\t\t\t\tif(i == 0) begin
\t\t\t\t\t\talways @(posedge clk)
\t\t\t\t\t\t\tb <= in_data;
\t\t\t\t\tend else begin
\t\t\t\t\t\talways @(posedge clk)
\t\t\t\t\t\t\tb <= buffer[i - 1].b;
\t\t\t\t\tend
\t\t\t\tend
\t\t\t\tassign out_data = out_ready ? buffer[mul_delay].b : 0;
\t\t\tend else begin
\t\t\t\treg[data_width - 1 : 0] reg_out_data;
\t\t\t\talways @(posedge in_enable)
\t\t\t\t\treg_out_data = in_data;
\t\t\t\tassign out_data = out_ready ? reg_out_data : 0;
\t\t\tend
\t\tend else begin
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\tcon_enable <= 0;
\t\t\t\telse if (con_enable == mul_delay + 1 + ram_read_latency)
\t\t\t\t\tcon_enable <= con_enable;
\t\t\t\telse
\t\t\t\t\tcon_enable <= con_enable + 1;
\t\t\tend
\t\t\tassign out_data = out_ready ? in_data : 0;
\t\t\tassign out_ready = con_enable == mul_delay + 1 + ram_read_latency ? 1 : 0;
\t\tend
\tendgenerate
endmodule
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
WindowGenerator
:Function
Generate window.
The lowest "color_width" bits of "out_data" is the top left corner pixel of the window!
In pipeline mode, it will give the first output after window_width / 2 + 1 cycles while the input enable.
In req-ack mode, before the first window can be output, it will give a input ack for every req, then you can give the next input data.
:Module
Main module
:Version
1.0
:Modified
2015-05-19
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module WindowGenerator(
\tclk,
\trst_n,
\tin_enable,
\tin_data,
\tout_ready,
\tout_data,
\tinput_ack
\t);
\t/*
\t::description
\tThis module\'s working mode.
\t::range
\t0 for Pipline, 1 for Req-ack
\t*/
\tparameter[0 : 0] work_mode = 0;
\t/*
\t::description
\tThe width(and height) of window.
\t::range
\t2 - 15
\t*/
\tparameter[3 : 0] window_width = 3;
\t/*
\t::description
\tColor\'s bit wide.
\t::range
\t1 - 12
\t*/
\tparameter[3: 0] color_width = 8;
\tparameter[2 : 0] window_width_half = window_width >> 1;
\t/*
\t::description
\tClock.
\t*/
\tinput clk;
\t/*
\t::description
\tReset, active low.
\t*/
\tinput rst_n;
\t/*
\t::description
\tInput data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
\t*/
\tinput in_enable;
\t/*
\t::description
\tInput data, it must be synchronous with in_enable.
\t*/
\tinput [color_width * window_width - 1 : 0] in_data;
\t/*
\t::description
\tOutput data ready, in both two mode, it will be high while the out_data can be read.
\t*/
\toutput out_ready;
\t/*
\t::description
\tOutput data, it will be synchronous with out_ready.
\t*/
\toutput[color_width * window_width * window_width - 1 : 0] out_data;
\t/*
\t::description
\tInput ack, only used for req-ack mode, this port will give a ack while the input_data received.
\t*/
\toutput input_ack;
\treg[color_width * window_width - 1 : 0] reg_out_data[0 : window_width - 1];
\treg[3 : 0] con_init;
\tgenvar y;
\tgenvar x;
\tgenerate
\t\tif(work_mode == 0) begin
\t\t\tassign input_ack = 0;
\t\t\treg reg_out_ready;
\t\t\tassign out_ready = reg_out_ready;
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable) begin
\t\t\t\t\tcon_init <= 0;
\t\t\t\t\treg_out_ready <= 0;
\t\t\t\tend else if(con_init == window_width_half) begin
\t\t\t\t\tcon_init <= con_init;
\t\t\t\t\treg_out_ready <= 1;
\t\t\t\tend else begin
\t\t\t\t\tcon_init <= con_init + 1;
\t\t\t\t\treg_out_ready <= 0;
\t\t\t\tend
\t\t\tend
\t\t\tfor (y = 0; y < window_width; y = y + 1) begin
\t\t\t\tfor (x = 0; x < window_width; x = x + 1) begin
\t\t\t\t\tif (x == 0) begin
\t\t\t\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\t\t\t\treg_out_data[y][(x + 1) * color_width - 1 : x * color_width] <= 0;
\t\t\t\t\t\t\telse
\t\t\t\t\t\t\t\treg_out_data[y][(x + 1) * color_width - 1 : x * color_width] <= in_data[(y + 1) * color_width - 1 : y * color_width];
\t\t\t\t\t\tend
\t\t\t\t\tend else begin
\t\t\t\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\t\t\t\treg_out_data[y][(x + 1) * color_width - 1 : x * color_width] <= 0;
\t\t\t\t\t\t\telse
\t\t\t\t\t\t\t\treg_out_data[y][(x + 1) * color_width - 1 : x * color_width] <= reg_out_data[y][x * color_width - 1 : (x - 1)* color_width];
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tend
\t\t\t\tassign out_data[(y + 1) * color_width * window_width - 1 : y * color_width * window_width] =
\t\t\t\t\tout_ready ? reg_out_data[y] : 0;
\t\t\tend
\t\tend else begin
\t\t\treg in_enable_last;
\t\t\talways @(posedge clk)
\t\t\t\tin_enable_last <= in_enable;
\t\t\treg reg_input_ack;
\t\t\tassign input_ack = reg_input_ack;
\t\t\talways @(posedge clk or negedge rst_n) begin
\t\t\t\tif(~rst_n)
\t\t\t\t\tcon_init <= 0;
\t\t\t\telse if(con_init == window_width_half + 1)
\t\t\t\t\tcon_init <= con_init;
\t\t\t\telse if(~in_enable_last & in_enable)
\t\t\t\t\tcon_init <= con_init + 1;
\t\t\t\telse
\t\t\t\t\tcon_init <= con_init;
\t\t\tend
\t\t\tassign out_ready = con_init == window_width_half + 1 ? 1 : 0;
\t\t\talways @(posedge clk or negedge rst_n) begin
\t\t\t\tif(~rst_n)
\t\t\t\t\treg_input_ack <= 0;
\t\t\t\telse if(~in_enable_last & in_enable)
\t\t\t\t\treg_input_ack <= 1;
\t\t\t\telse if(in_enable_last & ~in_enable)
\t\t\t\t\treg_input_ack <= 0;
\t\t\tend
\t\t\tfor (y = 0; y < window_width; y = y + 1) begin
\t\t\t\tfor (x = 0; x < window_width; x = x + 1) begin
\t\t\t\t\tif (x == 0) begin
\t\t\t\t\t\talways @(posedge clk or negedge rst_n) begin
\t\t\t\t\t\t\tif(~rst_n)
\t\t\t\t\t\t\t\treg_out_data[y][(x + 1) * color_width - 1 : x * color_width] <= 0;
\t\t\t\t\t\t\telse if(~in_enable_last & in_enable)
\t\t\t\t\t\t\t\treg_out_data[y][(x + 1) * color_width - 1 : x * color_width] <= in_data[(y + 1) * color_width - 1 : y * color_width];
\t\t\t\t\t\t\telse
\t\t\t\t\t\t\t\treg_out_data[y][(x + 1) * color_width - 1 : x * color_width] <= reg_out_data[y][(x + 1) * color_width - 1 : x * color_width];
\t\t\t\t\t\tend
\t\t\t\t\tend else begin
\t\t\t\t\t\talways @(posedge clk or negedge rst_n) begin
\t\t\t\t\t\t\tif(~rst_n)
\t\t\t\t\t\t\t\treg_out_data[y][(x + 1) * color_width - 1 : x * color_width] <= 0;
\t\t\t\t\t\t\telse if(~in_enable_last & in_enable)
\t\t\t\t\t\t\t\treg_out_data[y][(x + 1) * color_width - 1 : x * color_width] <= reg_out_data[y][x * color_width - 1 : (x - 1)* color_width];
\t\t\t\t\t\t\telse
\t\t\t\t\t\t\t\treg_out_data[y][(x + 1) * color_width - 1 : x * color_width] <= reg_out_data[y][(x + 1) * color_width - 1 : x * color_width];
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tend
\t\t\t\tassign out_data[(y + 1) * color_width * window_width - 1 : y * color_width * window_width] =
\t\t\t\t\tout_ready ? reg_out_data[y] : 0;
\t\t\tend
\t\tend
\t\t
\tendgenerate
endmodule
|
/*
:Project
FPGA-Imaging-Library
:Design
True2Comp
:Function
Convert true code to complemental code.
:Module
Main module
:Version
1.0
:Modified
2015-05-01
Copyright (C) 2015 Dai Tianyu (dtysky)
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://ifl.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module True2Comp(
\ttrue,
\tcomplement);
\tparameter data_channel = 1;
\tparameter data_width = 17;
\tinput[data_channel * data_width - 1 : 0] true;
\toutput[data_channel * data_width - 1 : 0] complement;
\tgenvar i;
\tgenerate
\t\t`define h (i + 1) * data_width - 1
\t\t`define l i * data_width
\t\tfor (i = 0; i < data_channel; i = i + 1) begin
\t\t\tassign complement[`h : `l] = true[`h] == 0 ?
\t\t\t\ttrue[`h : `l] : {1'b1, ~true[`h - 1 : `l] + 1};
\t\tend
\t\t`undef h
\t\t`undef l
\tendgenerate
endmodule
|
`timescale 1 ns / 1 ps
\tmodule BoardInit_AXI_v1_0 #
\t(
\t\t// Users to add parameters here
\t\tparameter integer im_bits_width = 9,
\t\tparameter integer color_width = 8,
\t\tparameter integer window_width = 8,
\t\t// User parameters ends
\t\t// Do not modify the parameters beyond this line
\t\t// Width of S_AXI data bus
\t\tparameter integer C_S00_AXI_DATA_WIDTH\t= 32,
\t\t// Width of S_AXI address bus
\t\tparameter integer C_S00_AXI_ADDR_WIDTH\t= 7
\t)
\t(
\t\t// Users to add ports here
\t\tinput wire rst_n,
\t\tinput wire pll_locked,
\t\toutput wire rst_all_n,
\t\toutput wire th_mode,
\t\toutput wire[color_width - 1 : 0] th1,
\t\toutput wire[color_width - 1 : 0] th2,
\t\toutput wire[23 : 0] ct_scale,
\t\toutput wire signed[color_width : 0] lm_gain,
\t\toutput wire[3 : 0] rank,
\t\toutput wire ed_mode,
\t\toutput wire[window_width * window_width - 1 : 0] ed_template,
\t\toutput wire[window_width * window_width - 1 : 0] mt_template,
\t\toutput wire[im_bits_width - 1 : 0] crop_top,crop_bottom,crop_left,crop_right,
\t\toutput wire[1 : 0] mirror_mode,
\t\toutput wire signed[im_bits_width : 0] offset_x, offset_y,
\t\toutput wire [23 : 0] scale_x, scale_y,
\t\toutput wire signed[24 : 0] sh_u, sh_v,
\t\toutput wire[8 : 0] angle,
\t\toutput wire[31 : 0] sels,
\t\t// User ports ends
\t\t// Do not modify the ports beyond this line
\t\t// Ports of Axi Slave Bus Interface S00_AXI
\t\tinput wire s00_axi_aclk,
\t\tinput wire s00_axi_aresetn,
\t\tinput wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
\t\tinput wire [2 : 0] s00_axi_awprot,
\t\tinput wire s00_axi_awvalid,
\t\toutput wire s00_axi_awready,
\t\tinput wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
\t\tinput wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
\t\tinput wire s00_axi_wvalid,
\t\toutput wire s00_axi_wready,
\t\toutput wire [1 : 0] s00_axi_bresp,
\t\toutput wire s00_axi_bvalid,
\t\tinput wire s00_axi_bready,
\t\tinput wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
\t\tinput wire [2 : 0] s00_axi_arprot,
\t\tinput wire s00_axi_arvalid,
\t\toutput wire s00_axi_arready,
\t\toutput wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
\t\toutput wire [1 : 0] s00_axi_rresp,
\t\toutput wire s00_axi_rvalid,
\t\tinput wire s00_axi_rready
\t);
// Instantiation of Axi Bus Interface S00_AXI
\tBoardInit_AXI_v1_0_S00_AXI # (
\t\t.im_bits_width(im_bits_width),
\t\t.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
\t\t.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
\t) BoardInit_AXI_v1_0_S00_AXI_inst (
\t\t.rst_n(rst_n),
\t\t.pll_locked(pll_locked),
\t\t.rst_all_n(rst_all_n),
\t\t.th_mode(th_mode),
\t\t.th1(th1),
\t\t.th2(th2),
\t\t.lm_gain(lm_gain),
\t\t.ct_scale(ct_scale),
\t\t.rank(rank),
\t\t.ed_mode(ed_mode),
\t\t.ed_template(ed_template),
\t\t.mt_template(mt_template),
\t\t.crop_top(crop_top),
\t\t.crop_bottom(crop_bottom),
\t\t.crop_left(crop_left),
\t\t.crop_right(crop_right),
\t\t.mirror_mode(mirror_mode),
\t\t.offset_x(offset_x),
\t\t.offset_y(offset_y),
\t\t.scale_x(scale_x),
\t\t.scale_y(scale_y),
\t\t.sh_u(sh_u),
\t\t.sh_v(sh_v),
\t\t.angle(angle),
\t\t.sels(sels),
\t\t.S_AXI_ACLK(s00_axi_aclk),
\t\t.S_AXI_ARESETN(s00_axi_aresetn),
\t\t.S_AXI_AWADDR(s00_axi_awaddr),
\t\t.S_AXI_AWPROT(s00_axi_awprot),
\t\t.S_AXI_AWVALID(s00_axi_awvalid),
\t\t.S_AXI_AWREADY(s00_axi_awready),
\t\t.S_AXI_WDATA(s00_axi_wdata),
\t\t.S_AXI_WSTRB(s00_axi_wstrb),
\t\t.S_AXI_WVALID(s00_axi_wvalid),
\t\t.S_AXI_WREADY(s00_axi_wready),
\t\t.S_AXI_BRESP(s00_axi_bresp),
\t\t.S_AXI_BVALID(s00_axi_bvalid),
\t\t.S_AXI_BREADY(s00_axi_bready),
\t\t.S_AXI_ARADDR(s00_axi_araddr),
\t\t.S_AXI_ARPROT(s00_axi_arprot),
\t\t.S_AXI_ARVALID(s00_axi_arvalid),
\t\t.S_AXI_ARREADY(s00_axi_arready),
\t\t.S_AXI_RDATA(s00_axi_rdata),
\t\t.S_AXI_RRESP(s00_axi_rresp),
\t\t.S_AXI_RVALID(s00_axi_rvalid),
\t\t.S_AXI_RREADY(s00_axi_rready)
\t);
\t// Add user logic here
\t// User logic ends
\tendmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: None
// Engineer: Dai Tianyu (dtysky)
//
// Create Date: 2015/04/07 18:01:07
// Design Name:
// Module Name: DataSplit4
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependenrgb24es:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DataSplit4(i, o0, o1, o2, o3);
\tparameter data_width = 1;
\tinput[4 * data_width - 1 : 0] i;
\toutput[data_width - 1 : 0] o0, o1, o2, o3;
\tassign o0 = i[1 * data_width - 1 : 0 * data_width];
\tassign o1 = i[2 * data_width - 1 : 1 * data_width];
\tassign o2 = i[3 * data_width - 1 : 2 * data_width];
\tassign o3 = i[4 * data_width - 1 : 3 * data_width];
endmodule
|
/*
:Project
FPGA-Imaging-Library
:Design
FrameController
:Function
For controlling a BlockRAM from xilinx.
Give the first output after ram_read_latency cycles while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-12
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module FrameController(
\tclk,
\trst_n,
\tin_enable,
\tin_data,
\tout_ready,
\tout_data,
\tram_addr);
\t/*
\t::description
\tThis module's working mode.
\t::range
\t0 for Pipline, 1 for Req-ack
\t*/
\tparameter work_mode = 0;
\t/*
\t::description
\tThis module's WR mode.
\t::range
\t0 for Write, 1 for Read
\t*/
\tparameter wr_mode = 0;
\t/*
\t::description
\tData bit width.
\t*/
\tparameter data_width = 8;
\t/*
\t::description
\tWidth of image.
\t::range
\t1 - 4096
\t*/
\tparameter im_width = 320;
\t/*
\t::description
\tHeight of image.
\t::range
\t1 - 4096
\t*/
\tparameter im_height = 240;
\t/*
\t::description
\tAddress bit width of a ram for storing this image.
\t::range
\tDepend on im_width and im_height.
\t*/
\tparameter addr_width = 17;
\t/*
\t::description
\tRL of RAM, in xilinx 7-series device, it is 2.
\t::range
\t0 - 15, Depend on your using ram.
\t*/
\tparameter ram_read_latency = 2;
\t/*
\t::description
\tThe first row you want to storing, used for eliminating offset.
\t::range
\tDepend on your input offset.
\t*/
\tparameter row_init = 0;
\t/*
\t::description
\tClock.
\t*/
\tinput clk;
\t/*
\t::description
\tReset, active low.
\t*/
\tinput rst_n;
\t/*
\t::description
\tInput data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
\t*/
\tinput in_enable;
\t/*
\t::description
\tInput data, it must be synchronous with in_enable.
\t*/
\tinput [data_width - 1 : 0] in_data;
\t/*
\t::description
\tOutput data ready, in both two mode, it will be high while the out_data can be read.
\t*/
\toutput out_ready;
\t/*
\t::description
\tOutput data, it will be synchronous with out_ready.
\t*/
\toutput[data_width - 1 : 0] out_data;
\t/*
\t::description
\tAddress for ram.
\t*/
\toutput[addr_width - 1 : 0] ram_addr;
\treg[addr_width - 1 : 0] reg_ram_addr;
\treg[3 : 0] con_ready;
\tassign ram_addr = reg_ram_addr;
\tassign out_data = out_ready ? in_data : 0;
\tgenerate
\t\tif(wr_mode == 0) begin
\t\t\tif(work_mode == 0) begin
\t\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\t\treg_ram_addr <= row_init * im_width;
\t\t\t\t\telse if(reg_ram_addr == im_width * im_height - 1)
\t\t\t\t\t\treg_ram_addr <= 0;
\t\t\t\t\telse
\t\t\t\t\t\treg_ram_addr <= reg_ram_addr + 1;
\t\t\t\tend
\t\t\tend else begin
\t\t\t\talways @(posedge in_enable or negedge rst_n) begin
\t\t\t\t\tif(~rst_n)
\t\t\t\t\t\treg_ram_addr <= row_init * im_width - 1;
\t\t\t\t\telse if(reg_ram_addr == im_width * im_height - 1)
\t\t\t\t\t\treg_ram_addr <= 0;
\t\t\t\t\telse
\t\t\t\t\t\treg_ram_addr <= reg_ram_addr + 1;
\t\t\t\tend
\t\t\tend
\t\t\tassign out_ready = ~rst_n || ~in_enable ? 0 : 1;
\t\tend else begin
\t\t\tif(work_mode == 0) begin
\t\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\t\treg_ram_addr <= 0;
\t\t\t\t\telse if(reg_ram_addr == im_width * im_height - 1)
\t\t\t\t\t\treg_ram_addr <= 0;
\t\t\t\t\telse
\t\t\t\t\t\treg_ram_addr <= reg_ram_addr + 1;
\t\t\t\tend
\t\t\tend else begin
\t\t\t\talways @(posedge in_enable or negedge rst_n) begin
\t\t\t\t\tif(~rst_n)
\t\t\t\t\t\treg_ram_addr <= 0 - 1;
\t\t\t\t\telse if(reg_ram_addr == im_width * im_height - 1)
\t\t\t\t\t\treg_ram_addr <= 0;
\t\t\t\t\telse
\t\t\t\t\t\treg_ram_addr <= reg_ram_addr + 1;
\t\t\t\tend
\t\t\tend
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\tcon_ready <= 0;
\t\t\t\telse if (con_ready == ram_read_latency)
\t\t\t\t\tcon_ready <= con_ready;
\t\t\t\telse
\t\t\t\t\tcon_ready <= con_ready + 1;
\t\t\tend
\t\t\tassign out_ready = con_ready == ram_read_latency ? 1 : 0;
\t\tend
\tendgenerate
endmodule
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
Mirror
:Function
Getting a mirror of your given image.
Give the first output after 1 cycle while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-26
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module Mirror(
\tclk,
\trst_n,
\tmode,
\tin_enable,
\tin_data,
\tin_count_x,
\tin_count_y,
\tout_ready,
\tout_data,
\tout_count_x,
\tout_count_y);
\t/*
\t::description
\tThis module's working mode.
\t::range
\t0 for Pipline, 1 for Req-ack
\t*/
\tparameter work_mode = 0;
\t/*
\t::description
\tData bit width.
\t*/
\tparameter data_width = 8;
\t/*
\t::description
\tWidth of image.
\t::range
\t1 - 4096
\t*/
\tparameter im_width = 320;
\t/*
\t::description
\tHeight of image.
\t::range
\t1 - 4096
\t*/
\tparameter im_height = 240;
\t/*
\t::description
\tThe bits of width of image.
\t::range
\tDepend on width of image
\t*/
\tparameter im_width_bits = 9;
\t/*
\t::description
\tClock.
\t*/
\tinput clk;
\t/*
\t::description
\tReset, active low.
\t*/
\tinput rst_n;
\t/*
\t::description
\tMode for mirror.
\t::range
\t00 for horizontal, 01 for vertical, 10 or 11 for all
\t*/
\tinput [1 : 0] mode;
\t/*
\t::description
\tInput data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
\t*/
\tinput in_enable;
\t/*
\t::description
\tInput data, it must be synchronous with in_enable.
\t*/
\tinput [data_width - 1 : 0] in_data;
\t/*
\t::description
\tInput pixel count for width.
\t*/
\tinput[im_width_bits - 1 : 0] in_count_x;
\t/*
\t::description
\tInput pixel count for height.
\t*/
\tinput[im_width_bits - 1 : 0] in_count_y;
\t/*
\t::description
\tOutput data ready, in both two mode, it will be high while the out_data can be read.
\t*/
\toutput out_ready;
\t/*
\t::description
\tOutput data, it will be synchronous with out_ready.
\t*/
\toutput[data_width - 1 : 0] out_data;
\t/*
\t::description
\tOutput pixel count for height.
\t*/
\toutput[im_width_bits - 1 : 0] out_count_x;
\t/*
\t::description
\tOutput pixel count for height.
\t*/
\toutput[im_width_bits - 1 : 0] out_count_y;
\treg[im_width_bits - 1 : 0] reg_out_x, reg_out_y;
\treg[data_width - 1 : 0] reg_out_data;
\treg reg_out_ready;
\tgenerate
\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\tif(~rst_n || ~in_enable)
\t\t\t\treg_out_ready <= 0;
\t\t\telse
\t\t\t\treg_out_ready <= 1;
\t\tend
\t\tif(work_mode == 0) begin
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\treg_out_data <= 0;
\t\t\t\telse
\t\t\t\t\treg_out_data <= in_data;
\t\t\tend
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\treg_out_x <= 0;
\t\t\t\telse begin
\t\t\t\t\tcase (mode)
\t\t\t\t\t\t1 : reg_out_x <= in_count_x;
\t\t\t\t\t\tdefault : reg_out_x <= im_width - 1 - in_count_x;
\t\t\t\t\tendcase
\t\t\t\tend
\t\t\tend
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\treg_out_y <= 0;
\t\t\t\telse begin
\t\t\t\t\tcase (mode)
\t\t\t\t\t\t0 : reg_out_y <= in_count_y;
\t\t\t\t\t\tdefault : reg_out_y <= im_height - 1 - in_count_y;
\t\t\t\t\tendcase
\t\t\t\tend
\t\t\tend
\t\tend else begin
\t\t\treg in_enable_last;
\t\t\talways @(posedge clk)
\t\t\t\tin_enable_last <= in_enable;
\t\t\talways @(posedge clk or negedge rst_n) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\treg_out_data <= 0;
\t\t\t\telse if(~in_enable_last & in_enable)
\t\t\t\t\treg_out_data <= in_data;
\t\t\t\telse
\t\t\t\t\treg_out_data <= reg_out_data;
\t\t\tend
\t\t\talways @(posedge clk or negedge rst_n) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\treg_out_x <= 0;
\t\t\t\telse if(~in_enable_last & in_enable) begin
\t\t\t\t\tcase (mode)
\t\t\t\t\t\t1 : reg_out_x <= in_count_x;
\t\t\t\t\t\tdefault : reg_out_x <= im_width - 1 - in_count_x;
\t\t\t\t\tendcase
\t\t\t\tend else
\t\t\t\t\treg_out_x <= reg_out_x;
\t\t\tend
\t\t\talways @(posedge clk or negedge rst_n) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\treg_out_y <= 0;
\t\t\t\telse if(~in_enable_last & in_enable) begin
\t\t\t\t\tcase (mode)
\t\t\t\t\t\t0 : reg_out_y <= in_count_y;
\t\t\t\t\t\tdefault : reg_out_y <= im_height - 1 - in_count_y;
\t\t\t\t\tendcase
\t\t\t\tend else
\t\t\t\t\treg_out_y <= reg_out_y;
\t\t\tend
\t\tend
\tendgenerate
\tassign out_ready = reg_out_ready;
\tassign out_count_x = reg_out_x;
\tassign out_count_y = reg_out_y;
\tassign out_data = reg_out_data;
endmodule
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
MeanFilter
:Function
Local filter - Mean filter, it always used for smoothing images.
It will give the first output after sum_stage + 1 cycles while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-20
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
`define full_win_width window_width * window_width
module MeanFilter(
\tclk,
\trst_n,
\tin_enable,
\tin_data,
\tout_ready,
\tout_data);
\t/*
\t::description
\tThis module's working mode.
\t::range
\t0 for Pipeline, 1 for Req-ack
\t*/
\tparameter[0 : 0] work_mode = 0;
\t/*
\t::description
\tThe width(and height) of window.
\t::range
\t2 - 15
\t*/
\tparameter[3 : 0] window_width = 3;
\t/*
\t::description
\tColor's bit wide.
\t::range
\t1 - 12
\t*/
\tparameter[3: 0] color_width = 8;
\t/*
\t::description
\tStage of sum.
\t::range
\tDepend on width of window, log2(window_width^2)
\t*/
\tparameter sum_stage = 3;
\t/*
\t::description
\tClock.
\t*/
\tinput clk;
\t/*
\t::description
\tReset, active low.
\t*/
\tinput rst_n;
\t/*
\t::description
\tInput data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
\t*/
\tinput in_enable;
\t/*
\t::description
\tInput data, it must be synchronous with in_enable.
\t*/
\tinput [color_width * window_width * window_width - 1 : 0] in_data;
\t/*
\t::description
\tOutput data ready, in both two mode, it will be high while the out_data can be read.
\t*/
\toutput out_ready;
\t/*
\t::description
\tOutput data, it will be synchronous with out_ready.
\t*/
\toutput[color_width - 1 : 0] out_data;
\treg[color_width - 1 : 0] reg_in_data[0 : `full_win_width - 1];
\treg[color_width - 1 : 0] reg_out_data;
\twire[color_width + `full_win_width - 1 : 0] sum_all;
\treg[3 : 0] con_enable;
\tgenvar i, j;
\tgenerate
\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\tif(~rst_n || ~in_enable)
\t\t\t\tcon_enable <= 0;
\t\t\telse if(con_enable == sum_stage + 1)
\t\t\t\tcon_enable <= con_enable;
\t\t\telse
\t\t\t\tcon_enable <= con_enable + 1;
\t\tend
\t\tassign out_ready = con_enable == sum_stage + 1 ? 1 : 0;
\t\tfor (i = 0; i < `full_win_width; i = i + 1) begin
\t\t\tif(work_mode == 0) begin
\t\t\t\talways @(*)
\t\t\t\t\treg_in_data[i] = in_data[(i + 1) * color_width - 1 : i * color_width];
\t\t\tend else begin
\t\t\t\talways @(posedge in_enable)
\t\t\t\t\treg_in_data[i] = in_data[(i + 1) * color_width - 1 : i * color_width];
\t\t\tend
\t\tend
\t\tfor (i = 0; i < sum_stage; i = i + 1) begin : pipe
\t\t\treg[color_width + `full_win_width - 1 : 0] sum[0 : (`full_win_width >> i + 1) - 1];
\t\t\tfor (j = 0; j < `full_win_width >> i + 1; j = j + 1) begin
\t\t\t\tif(i == 0) begin
\t\t\t\t\tif(j == 0 && ((`full_win_width >> i) % 2 != 0)) begin
\t\t\t\t\t\talways @(posedge clk)
\t\t\t\t\t\t\tsum[j] <=
\t\t\t\t\t\t\t\treg_in_data[`full_win_width - 1] +
\t\t\t\t\t\t\t\treg_in_data[2 * j] +
\t\t\t\t\t\t\t\treg_in_data[2 * j + 1];
\t\t\t\t\tend else begin
\t\t\t\t\t\talways @(posedge clk)
\t\t\t\t\t\t\tsum[j] <=
\t\t\t\t\t\t\t\treg_in_data[2 * j] +
\t\t\t\t\t\t\t\treg_in_data[2 * j + 1];
\t\t\t\t\tend
\t\t\t\tend else begin
\t\t\t\t\tif(j == 0 && ((`full_win_width >> i) % 2 != 0)) begin
\t\t\t\t\t\talways @(posedge clk)
\t\t\t\t\t\t\tsum[j] <= pipe[i - 1].sum[(`full_win_width >> i) - 1] + pipe[i - 1].sum[2 * j] + pipe[i - 1].sum[2 * j + 1];
\t\t\t\t\tend else begin
\t\t\t\t\t\talways @(posedge clk)
\t\t\t\t\t\t\tsum[j] <= pipe[i - 1].sum[2 * j] + pipe[i - 1].sum[2 * j + 1];
\t\t\t\t\tend
\t\t\t\tend
\t\t\tend
\t\tend
\t\tassign sum_all = pipe[sum_stage - 1].sum[0];
\t\tcase (window_width)
\t\t \t2 : always @(posedge clk) reg_out_data <= sum_all >> 2;
\t\t \t3 : always @(posedge clk) reg_out_data <= (sum_all >> 4) + (sum_all >> 5) + (sum_all >> 6);
\t\t \t4 : always @(posedge clk) reg_out_data <= sum_all >> 4;
\t\t \t5 : always @(posedge clk) reg_out_data <= (sum_all >> 5) + (sum_all >> 7) + (sum_all >> 10);
\t\t \t6 : always @(posedge clk) reg_out_data <= (sum_all >> 6) + (sum_all >> 7) + (sum_all >> 8);
\t\t \t7 : always @(posedge clk) reg_out_data <= (sum_all >> 6) + (sum_all >> 8) + (sum_all >> 10);
\t\t \t8 : always @(posedge clk) reg_out_data <= sum_all >> 6;
\t\t \t9 : always @(posedge clk) reg_out_data <= (sum_all >> 7) + (sum_all >> 8) + (sum_all >> 11);
\t\t \t10 : always @(posedge clk) reg_out_data <= (sum_all >> 7) + (sum_all >> 9) + (sum_all >> 13);
\t\t \t11 : always @(posedge clk) reg_out_data <= (sum_all >> 7) + (sum_all >> 12) + (sum_all >> 13);
\t\t \t12 : always @(posedge clk) reg_out_data <= (sum_all >> 8) + (sum_all >> 9) + (sum_all >> 10);
\t\t \t13 : always @(posedge clk) reg_out_data <= (sum_all >> 8) + (sum_all >> 9) + (sum_all >> 14);
\t\t \t14 : always @(posedge clk) reg_out_data <= (sum_all >> 8) + (sum_all >> 10) + (sum_all >> 12);
\t\t \t15 : always @(posedge clk) reg_out_data <= (sum_all >> 8) + (sum_all >> 11);
\t\t \tdefault : /* default */;
\t\tendcase
\t\tassign out_data = out_ready ? reg_out_data : 0;
\tendgenerate
endmodule
`undef full_win_width
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
// Date : Mon May 25 17:58:01 2015
// Host : Dtysky running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// b:/Complex_Mind/FPGA-Imaging-Library/Master/Generator/FrameController2/HDL/FrameController2.srcs/sources_1/ip/Multiplier12x12FR2/Multiplier12x12FR2_funcsim.v
// Design : Multiplier12x12FR2
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "mult_gen_v12_0,Vivado 2014.4" *) (* CHECK_LICENSE_TYPE = "Multiplier12x12FR2,mult_gen_v12_0,{}" *)
(* core_generation_info = "Multiplier12x12FR2,mult_gen_v12_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=zynq,C_HAS_CE=0,C_HAS_SCLR=1,C_LATENCY=3,C_A_WIDTH=12,C_A_TYPE=1,C_B_WIDTH=12,C_B_TYPE=1,C_OUT_HIGH=23,C_OUT_LOW=0,C_MULT_TYPE=1,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}" *)
(* NotValidForBitStream *)
module Multiplier12x12FR2
(CLK,
A,
B,
SCLR,
P);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) input CLK;
input [11:0]A;
input [11:0]B;
(* x_interface_info = "xilinx.com:signal:reset:1.0 sclr_intf RST" *) input SCLR;
output [23:0]P;
wire [11:0]A;
wire [11:0]B;
wire CLK;
wire [23:0]P;
wire SCLR;
wire [47:0]NLW_U0_PCASC_UNCONNECTED;
wire [1:0]NLW_U0_ZERO_DETECT_UNCONNECTED;
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "12" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "12" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "3" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "1" *)
(* C_OPTIMIZE_GOAL = "1" *)
(* C_OUT_HIGH = "23" *)
(* C_OUT_LOW = "0" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* DONT_TOUCH *)
(* downgradeipidentifiedwarnings = "yes" *)
Multiplier12x12FR2_mult_gen_v12_0__parameterized0 U0
(.A(A),
.B(B),
.CE(1\'b1),
.CLK(CLK),
.P(P),
.PCASC(NLW_U0_PCASC_UNCONNECTED[47:0]),
.SCLR(SCLR),
.ZERO_DETECT(NLW_U0_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule
(* ORIG_REF_NAME = "mult_gen_v12_0" *) (* C_VERBOSITY = "0" *) (* C_MODEL_TYPE = "0" *)
(* C_OPTIMIZE_GOAL = "1" *) (* C_XDEVICEFAMILY = "zynq" *) (* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *) (* C_LATENCY = "3" *) (* C_A_WIDTH = "12" *)
(* C_A_TYPE = "1" *) (* C_B_WIDTH = "12" *) (* C_B_TYPE = "1" *)
(* C_OUT_HIGH = "23" *) (* C_OUT_LOW = "0" *) (* C_MULT_TYPE = "1" *)
(* C_CE_OVERRIDES_SCLR = "0" *) (* C_CCM_IMP = "0" *) (* C_B_VALUE = "10000001" *)
(* C_HAS_ZERO_DETECT = "0" *) (* C_ROUND_OUTPUT = "0" *) (* C_ROUND_PT = "0" *)
(* downgradeipidentifiedwarnings = "yes" *)
module Multiplier12x12FR2_mult_gen_v12_0__parameterized0
(CLK,
A,
B,
CE,
SCLR,
ZERO_DETECT,
P,
PCASC);
input CLK;
input [11:0]A;
input [11:0]B;
input CE;
input SCLR;
output [1:0]ZERO_DETECT;
output [23:0]P;
output [47:0]PCASC;
wire [11:0]A;
wire [11:0]B;
wire CE;
wire CLK;
wire [23:0]P;
wire [47:0]PCASC;
wire SCLR;
wire [1:0]ZERO_DETECT;
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "12" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "12" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "3" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "1" *)
(* C_OPTIMIZE_GOAL = "1" *)
(* C_OUT_HIGH = "23" *)
(* C_OUT_LOW = "0" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* downgradeipidentifiedwarnings = "yes" *)
Multiplier12x12FR2_mult_gen_v12_0_viv__parameterized0 i_mult
(.A(A),
.B(B),
.CE(CE),
.CLK(CLK),
.P(P),
.PCASC(PCASC),
.SCLR(SCLR),
.ZERO_DETECT(ZERO_DETECT));
endmodule
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`pragma protect key_block
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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`pragma protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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`pragma protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7328)
`pragma protect data_block
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`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
ContrastTransform
:Function
Change the contrast of an image.
Give the first output after mul_delay + 1 cycles while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-16
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module ContrastTransform(
\tclk,
\trst_n,
\tct_scale,
\tin_enable,
\tin_data,
\tout_ready,
\tout_data
);
\t/*
\t::description
\tThis module\'s working mode.
\t::range
\t0 for Pipelines, 1 for Req-ack
\t*/
\tparameter[0 : 0] work_mode = 0;
\t/*
\t::description
\tChannels for color, 1 for gray, 3 for rgb, etc.
\t*/
\tparameter color_channels = 3;
\t/*
\t::description
\tColor\'s bit wide
\t::range
\t1 - 12
\t*/
\tparameter[3: 0] color_width = 8;
\t/*
\t::description
\tDelay for multiplier.
\t::range
\tDepend on your multilpliers\' configurations
\t*/
\tparameter mul_delay = 3;
\t/*
\t::description
\tClock.
\t*/
\tinput clk;
\t/*
\t::description
\tReset, active low.
\t*/
\tinput rst_n;
\t/*
\t::description
\tScale for contrast, fixed, 12bits.12bits.
\t*/
\tinput[23 : 0] ct_scale;
\t/*
\t::description
\tInput data enable, in pipelines mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be changes.
\t*/
\tinput in_enable;
\t/*
\t::description
\tInput data, it must be synchronous with in_enable.
\t*/
\tinput [color_channels * color_width - 1 : 0] in_data;
\t/*
\t::description
\tOutput data ready, in both two mode, it will be high while the out_data can be read.
\t*/
\toutput out_ready;
\t/*
\t::description
\tOutput data, it will be synchronous with out_ready.
\t*/
\toutput[color_channels * color_width - 1 : 0] out_data;
\treg[2 : 0] con_enable;
\tgenvar i;
\tgenerate
\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\tif(~rst_n || ~in_enable)
\t\t\t\tcon_enable <= 0;
\t\t\telse if(con_enable == mul_delay + 1)
\t\t\t\tcon_enable <= con_enable;
\t\t\telse
\t\t\t\tcon_enable <= con_enable +1;
\t\tend
\t\tassign out_ready = con_enable == mul_delay + 1 ? 1 : 0;
\t\t`define h (i + 1) * color_width - 1
\t\t`define l i * color_width
\t\tfor (i = 0; i < color_channels; i = i + 1) begin: channel
\t\t\twire[11 : 0] mul_a;
\t\t\twire[23 : 0] mul_b;
\t\t\twire[23 : 0] mul_p;
\t\t\tif(work_mode == 0) begin
\t\t\t\tassign mul_a = in_data[`h : `l];
\t\t\t\tassign mul_b = ct_scale;
\t\t\tend else begin
\t\t\t\treg[11 : 0] reg_mul_a;
\t\t\t\treg[23 : 0] reg_mul_b;
\t\t\t\talways @(posedge in_enable) begin
\t\t\t\t\treg_mul_a = in_data[`h : `l];
\t\t\t\t\treg_mul_b = ct_scale;
\t\t\t\tend
\t\t\t\tassign mul_a = reg_mul_a;
\t\t\t\tassign mul_b = reg_mul_b;
\t\t\tend
\t\t\t/*
\t\t\t::description
\t\t\tMultiplier for Unsigned 12bits x Unsigned 24bits, used for fixed multiplication.
\t\t\tYou can configure the multiplier by yourself, then change the "mul_delay".
\t\t\tAll Multiplier\'s pipeline stage must be same, you can not change the ports\' configurations!
\t\t\t*/
\t\t\tMultiplier12x24CT Mul(.CLK(clk), .A(mul_a), .B(mul_b), .SCLR(~rst_n), .P(mul_p));
\t\t\t//For overflow
\t\t\treg [color_width - 1 : 0] out_buffer;
\t\t\talways @(posedge clk) begin
\t\t\t\tout_buffer <= mul_p[23 : color_width] != 0 ?
\t\t\t\t\t{color_width{1\'b1}} :
\t\t\t\t\tmul_p[color_width - 1 : 0];
\t\t\tend
\t\t\tassign out_data[`h : `l] = out_ready ? out_buffer : 0;
\t\t\t
\t\tend
\t\t`undef h
\t\t`undef l
\tendgenerate
endmodule
|
`timescale 1 ns / 1 ps
`include "BoardInit_AXI_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2\'b00
`define RESPONSE_EXOKAY 2\'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2\'b01
`define BURST_TYPE_WRAP 2\'b10
// AMBA AXI4 Lite Range Constants
`define S00_AXI_MAX_BURST_LENGTH 1
`define S00_AXI_DATA_BUS_WIDTH 32
`define S00_AXI_ADDRESS_BUS_WIDTH 32
`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
module BoardInit_AXI_v1_0_tb;
\treg tb_ACLK;
\treg tb_ARESETn;
\t// Create an instance of the example tb
\t`BD_WRAPPER dut (.ACLK(tb_ACLK),
\t\t\t\t.ARESETN(tb_ARESETn));
\t// Local Variables
\t// AMBA S00_AXI AXI4 Lite Local Reg
\treg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
\treg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
\treg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
\treg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
\treg [3-1:0] S00_AXI_mtestProtection_lite;
\tinteger S00_AXI_mtestvectorlite; // Master side testvector
\tinteger S00_AXI_mtestdatasizelite;
\tinteger result_slave_lite;
\t// Simple Reset Generator and test
\tinitial begin
\t\ttb_ARESETn = 1\'b0;
\t #500;
\t\t// Release the reset on the posedge of the clk.
\t\t@(posedge tb_ACLK);
\t tb_ARESETn = 1\'b1;
\t\t@(posedge tb_ACLK);
\tend
\t// Simple Clock Generator
\tinitial tb_ACLK = 1\'b0;
\talways #10 tb_ACLK = !tb_ACLK;
\t//------------------------------------------------------------------------
\t// TEST LEVEL API: CHECK_RESPONSE_OKAY
\t//------------------------------------------------------------------------
\t// Description:
\t// CHECK_RESPONSE_OKAY(lite_response)
\t// This task checks if the return lite_response is equal to OKAY
\t//------------------------------------------------------------------------
\ttask automatic CHECK_RESPONSE_OKAY;
\t\tinput [`RESP_BUS_WIDTH-1:0] response;
\t\tbegin
\t\t if (response !== `RESPONSE_OKAY) begin
\t\t\t $display("TESTBENCH ERROR! lite_response is not OKAY",
\t\t\t\t "\
expected = 0x%h",`RESPONSE_OKAY,
\t\t\t\t "\
actual = 0x%h",response);
\t\t $stop;
\t\t end
\t\tend
\tendtask
\t//------------------------------------------------------------------------
\t// TEST LEVEL API: COMPARE_LITE_DATA
\t//------------------------------------------------------------------------
\t// Description:
\t// COMPARE_LITE_DATA(expected,actual)
\t// This task checks if the actual data is equal to the expected data.
\t// X is used as don\'t care but it is not permitted for the full vector
\t// to be don\'t care.
\t//------------------------------------------------------------------------
\ttask automatic COMPARE_LITE_DATA;
\t\tinput expected;
\t\tinput actual;
\t\tbegin
\t\t\tif (expected === \'hx || actual === \'hx) begin
\t\t\t\t$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all \'x\'!");
\t\t result_slave_lite = 0;
\t\t $stop;
\t\t end
\t\t\tif (actual != expected) begin
\t\t\t\t$display("TESTBENCH ERROR! Data expected is not equal to actual.",
\t\t\t\t "\
expected = 0x%h",expected,
\t\t\t\t "\
actual = 0x%h",actual);
\t\t result_slave_lite = 0;
\t\t $stop;
\t\t end
\t\t\telse
\t\t\tbegin
\t\t\t $display("TESTBENCH Passed! Data expected is equal to actual.",
\t\t\t "\
expected = 0x%h",expected,
\t\t\t "\
actual = 0x%h",actual);
\t\t\tend
\t\tend
\tendtask
\ttask automatic S00_AXI_TEST;
\t\tbegin
\t\t\t$display("---------------------------------------------------------");
\t\t\t$display("EXAMPLE TEST : S00_AXI");
\t\t\t$display("Simple register write and read example");
\t\t\t$display("---------------------------------------------------------");
\t\t\tS00_AXI_mtestvectorlite = 0;
\t\t\tS00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
\t\t\tS00_AXI_mtestProtection_lite = 0;
\t\t\tS00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
\t\t\t result_slave_lite = 1;
\t\t\tfor (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
\t\t\tbegin
\t\t\t dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
\t\t\t\t S00_AXI_mtestProtection_lite,
\t\t\t\t S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
\t\t\t\t S00_AXI_mtestdatasizelite,
\t\t\t\t S00_AXI_lite_response);
\t\t\t $display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
\t\t\t CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
\t\t\t dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
\t\t\t\t S00_AXI_mtestProtection_lite,
\t\t\t\t S00_AXI_rd_data_lite,
\t\t\t\t S00_AXI_lite_response);
\t\t\t $display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
\t\t\t CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
\t\t\t COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
\t\t\t $display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
\t\t\t S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32\'h00000004;
\t\t\tend
\t\t\t$display("---------------------------------------------------------");
\t\t\t$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
\t\t\t\tif ( result_slave_lite ) begin
\t\t\t\t\t$display("PTGEN_TEST: PASSED!");
\t\t\t\tend\telse begin
\t\t\t\t\t$display("PTGEN_TEST: FAILED!");
\t\t\t\tend\t\t\t\t\t\t\t
\t\t\t$display("---------------------------------------------------------");
\t\tend
\tendtask
\t// Create the test vectors
\tinitial begin
\t\t// When performing debug enable all levels of INFO messages.
\t\twait(tb_ARESETn === 0) @(posedge tb_ACLK);
\t\twait(tb_ARESETn === 1) @(posedge tb_ACLK);
\t\twait(tb_ARESETn === 1) @(posedge tb_ACLK);
\t\twait(tb_ARESETn === 1) @(posedge tb_ACLK);
\t\twait(tb_ARESETn === 1) @(posedge tb_ACLK);
\t\tdut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
\t\t// Create test data vectors
\t\tS00_AXI_test_data_lite[0] = 32\'h0101FFFF;
\t\tS00_AXI_test_data_lite[1] = 32\'habcd0001;
\t\tS00_AXI_test_data_lite[2] = 32\'hdead0011;
\t\tS00_AXI_test_data_lite[3] = 32\'hbeef0011;
\tend
\t// Drive the BFM
\tinitial begin
\t\t// Wait for end of reset
\t\twait(tb_ARESETn === 0) @(posedge tb_ACLK);
\t\twait(tb_ARESETn === 1) @(posedge tb_ACLK);
\t\twait(tb_ARESETn === 1) @(posedge tb_ACLK);
\t\twait(tb_ARESETn === 1) @(posedge tb_ACLK);
\t\twait(tb_ARESETn === 1) @(posedge tb_ACLK);
\t\tS00_AXI_TEST();
\tend
endmodule
|
/*
:Project
FPGA-Imaging-Library
:Design
FrameController2
:Function
Controlling a frame(block ram etc.), writing or reading with counts.
For controlling a BlockRAM from xilinx.
Give the first output after mul_delay + 2 + ram_read_latency cycles while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-25
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module FrameController2(
\tclk,
\trst_n,
\tin_count_x,
\tin_count_y,
\tin_enable,
\tin_data,
\tout_ready,
\tout_data,
\tram_addr);
\t/*
\t::description
\tThis module\'s working mode.
\t::range
\t0 for Pipline, 1 for Req-ack
\t*/
\tparameter work_mode = 0;
\t/*
\t::description
\tThis module\'s WR mode.
\t::range
\t0 for Write, 1 for Read
\t*/
\tparameter wr_mode = 0;
\t/*
\t::description
\tData bit width.
\t*/
\tparameter data_width = 8;
\t/*
\t::description
\tWidth of image.
\t::range
\t1 - 4096
\t*/
\tparameter im_width = 320;
\t/*
\t::description
\tHeight of image.
\t::range
\t1 - 4096
\t*/
\tparameter im_height = 240;
\t/*
\t::description
\tThe bits of width of image.
\t::range
\tDepend on width of image
\t*/
\tparameter im_width_bits = 9;
\t/*
\t::description
\tAddress bit width of a ram for storing this image.
\t::range
\tDepend on im_width and im_height.
\t*/
\tparameter addr_width = 17;
\t/*
\t::description
\tRL of RAM, in xilinx 7-series device, it is 2.
\t::range
\t0 - 15, Depend on your using ram.
\t*/
\tparameter ram_read_latency = 2;
\t/*
\t::description
\tDelay for multiplier.
\t::range
\tDepend on your multilpliers\' configurations
\t*/
\tparameter mul_delay = 3;
\t/*
\t::description
\tClock.
\t*/
\tinput clk;
\t/*
\t::description
\tReset, active low.
\t*/
\tinput rst_n;
\t/*
\t::description
\tInput pixel count for width.
\t*/
\tinput[im_width_bits - 1 : 0] in_count_x;
\t/*
\t::description
\tInput pixel count for height.
\t*/
\tinput[im_width_bits - 1 : 0] in_count_y;
\t/*
\t::description
\tInput data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
\t*/
\tinput in_enable;
\t/*
\t::description
\tInput data, it must be synchronous with in_enable.
\t*/
\tinput [data_width - 1 : 0] in_data;
\t/*
\t::description
\tOutput data ready, in both two mode, it will be high while the out_data can be read.
\t*/
\toutput out_ready;
\t/*
\t::description
\tOutput data, it will be synchronous with out_ready.
\t*/
\toutput[data_width - 1 : 0] out_data;
\t/*
\t::description
\tAddress for ram.
\t*/
\toutput[addr_width - 1 : 0] ram_addr;
\treg[3 : 0] con_enable;
\treg[im_width_bits - 1 : 0] reg_in_count_x;
\treg[im_width_bits - 1 : 0] reg_in_count_y;
\treg[addr_width - 1 : 0] reg_addr;
\twire[11 : 0] mul_a, mul_b;
\twire[23 : 0] mul_p;
\tassign mul_a = {{(12 - im_width_bits){1\'b0}}, in_count_y};
\tassign mul_b = im_width;
\tgenvar i;
\tgenerate
\t\t/*
\t\t::description
\t\tMultiplier for Unsigned 12bits x Unsigned 12bits, used for creating address for frame.
\t\tYou can configure the multiplier by yourself, then change the "mul_delay".
\t\tYou can not change the ports\' configurations!
\t\t*/
\t\tMultiplier12x12FR2 Mul(.CLK(clk), .A(mul_a), .B(mul_b), .SCLR(~rst_n), .P(mul_p));
\t\tfor (i = 0; i < mul_delay; i = i + 1) begin : conut_buffer
\t\t\treg[im_width_bits - 1 : 0] b;
\t\t\tif(i == 0) begin
\t\t\t\talways @(posedge clk)
\t\t\t\t\tb <= in_count_x;
\t\t\tend else begin
\t\t\t\talways @(posedge clk)
\t\t\t\t\tb <= conut_buffer[i - 1].b;
\t\t\tend
\t\tend
\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\tif(~rst_n || ~in_enable) begin
\t\t\t\treg_addr <= 0;
\t\t\tend else begin
\t\t\t\treg_addr <= mul_p + conut_buffer[mul_delay - 1].b;
\t\t\tend
\t\tend
\t\tassign ram_addr = reg_addr;
\t\tif(wr_mode == 0) begin
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\tcon_enable <= 0;
\t\t\t\telse if(con_enable == mul_delay + 1)
\t\t\t\t\tcon_enable <= con_enable;
\t\t\t\telse
\t\t\t\t\tcon_enable <= con_enable + 1;
\t\t\tend
\t\t\tassign out_ready = con_enable == mul_delay + 1 ? 1 : 0;
\t\t\tif(work_mode == 0) begin
\t\t\t\tfor (i = 0; i < mul_delay + 1; i = i + 1) begin : buffer
\t\t\t\t\treg[data_width - 1 : 0] b;
\t\t\t\t\tif(i == 0) begin
\t\t\t\t\t\talways @(posedge clk)
\t\t\t\t\t\t\tb <= in_data;
\t\t\t\t\tend else begin
\t\t\t\t\t\talways @(posedge clk)
\t\t\t\t\t\t\tb <= buffer[i - 1].b;
\t\t\t\t\tend
\t\t\t\tend
\t\t\t\tassign out_data = out_ready ? buffer[mul_delay].b : 0;
\t\t\tend else begin
\t\t\t\treg[data_width - 1 : 0] reg_out_data;
\t\t\t\talways @(posedge in_enable)
\t\t\t\t\treg_out_data = in_data;
\t\t\t\tassign out_data = out_ready ? reg_out_data : 0;
\t\t\tend
\t\tend else begin
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\tcon_enable <= 0;
\t\t\t\telse if (con_enable == mul_delay + 1 + ram_read_latency)
\t\t\t\t\tcon_enable <= con_enable;
\t\t\t\telse
\t\t\t\t\tcon_enable <= con_enable + 1;
\t\t\tend
\t\t\tassign out_data = out_ready ? in_data : 0;
\t\t\tassign out_ready = con_enable == mul_delay + 1 + ram_read_latency ? 1 : 0;
\t\tend
\tendgenerate
endmodule
|
/*
:Project
FPGA-Imaging-Library
:Design
FrameController
:Function
For controlling a BlockRAM from xilinx.
Give the first output after ram_read_latency cycles while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-12
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module FrameController(
\tclk,
\trst_n,
\tin_enable,
\tin_data,
\tout_ready,
\tout_data,
\tram_addr);
\t/*
\t::description
\tThis module's working mode.
\t::range
\t0 for Pipline, 1 for Req-ack
\t*/
\tparameter work_mode = 0;
\t/*
\t::description
\tThis module's WR mode.
\t::range
\t0 for Write, 1 for Read
\t*/
\tparameter wr_mode = 0;
\t/*
\t::description
\tData bit width.
\t*/
\tparameter data_width = 8;
\t/*
\t::description
\tWidth of image.
\t::range
\t1 - 4096
\t*/
\tparameter im_width = 320;
\t/*
\t::description
\tHeight of image.
\t::range
\t1 - 4096
\t*/
\tparameter im_height = 240;
\t/*
\t::description
\tAddress bit width of a ram for storing this image.
\t::range
\tDepend on im_width and im_height.
\t*/
\tparameter addr_width = 17;
\t/*
\t::description
\tRL of RAM, in xilinx 7-series device, it is 2.
\t::range
\t0 - 15, Depend on your using ram.
\t*/
\tparameter ram_read_latency = 2;
\t/*
\t::description
\tThe first row you want to storing, used for eliminating offset.
\t::range
\tDepend on your input offset.
\t*/
\tparameter row_init = 0;
\t/*
\t::description
\tClock.
\t*/
\tinput clk;
\t/*
\t::description
\tReset, active low.
\t*/
\tinput rst_n;
\t/*
\t::description
\tInput data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
\t*/
\tinput in_enable;
\t/*
\t::description
\tInput data, it must be synchronous with in_enable.
\t*/
\tinput [data_width - 1 : 0] in_data;
\t/*
\t::description
\tOutput data ready, in both two mode, it will be high while the out_data can be read.
\t*/
\toutput out_ready;
\t/*
\t::description
\tOutput data, it will be synchronous with out_ready.
\t*/
\toutput[data_width - 1 : 0] out_data;
\t/*
\t::description
\tAddress for ram.
\t*/
\toutput[addr_width - 1 : 0] ram_addr;
\treg[addr_width - 1 : 0] reg_ram_addr;
\treg[3 : 0] con_ready;
\tassign ram_addr = reg_ram_addr;
\tassign out_data = out_ready ? in_data : 0;
\tgenerate
\t\tif(wr_mode == 0) begin
\t\t\tif(work_mode == 0) begin
\t\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\t\treg_ram_addr <= row_init * im_width;
\t\t\t\t\telse if(reg_ram_addr == im_width * im_height - 1)
\t\t\t\t\t\treg_ram_addr <= 0;
\t\t\t\t\telse
\t\t\t\t\t\treg_ram_addr <= reg_ram_addr + 1;
\t\t\t\tend
\t\t\tend else begin
\t\t\t\talways @(posedge in_enable or negedge rst_n) begin
\t\t\t\t\tif(~rst_n)
\t\t\t\t\t\treg_ram_addr <= row_init * im_width - 1;
\t\t\t\t\telse if(reg_ram_addr == im_width * im_height - 1)
\t\t\t\t\t\treg_ram_addr <= 0;
\t\t\t\t\telse
\t\t\t\t\t\treg_ram_addr <= reg_ram_addr + 1;
\t\t\t\tend
\t\t\tend
\t\t\tassign out_ready = ~rst_n || ~in_enable ? 0 : 1;
\t\tend else begin
\t\t\tif(work_mode == 0) begin
\t\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\t\treg_ram_addr <= 0;
\t\t\t\t\telse if(reg_ram_addr == im_width * im_height - 1)
\t\t\t\t\t\treg_ram_addr <= 0;
\t\t\t\t\telse
\t\t\t\t\t\treg_ram_addr <= reg_ram_addr + 1;
\t\t\t\tend
\t\t\tend else begin
\t\t\t\talways @(posedge in_enable or negedge rst_n) begin
\t\t\t\t\tif(~rst_n)
\t\t\t\t\t\treg_ram_addr <= 0 - 1;
\t\t\t\t\telse if(reg_ram_addr == im_width * im_height - 1)
\t\t\t\t\t\treg_ram_addr <= 0;
\t\t\t\t\telse
\t\t\t\t\t\treg_ram_addr <= reg_ram_addr + 1;
\t\t\t\tend
\t\t\tend
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\tcon_ready <= 0;
\t\t\t\telse if (con_ready == ram_read_latency)
\t\t\t\t\tcon_ready <= con_ready;
\t\t\t\telse
\t\t\t\t\tcon_ready <= con_ready + 1;
\t\t\tend
\t\t\tassign out_ready = con_ready == ram_read_latency ? 1 : 0;
\t\tend
\tendgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: None
// Engineer: Dai Tianyu (dtysky)
//
// Create Date: 2015/04/07 18:01:07
// Design Name:
// Module Name: Mux8
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependenrgb24es:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Mux8(sel, i0, i1, i2, i3, i4, i5, i6, i7, o);
\tparameter data_width = 8;
\tinput[2 : 0] sel;
\tinput[data_width - 1 : 0] i0;
\tinput[data_width - 1 : 0] i1;
\tinput[data_width - 1 : 0] i2;
\tinput[data_width - 1 : 0] i3;
\tinput[data_width - 1 : 0] i4;
\tinput[data_width - 1 : 0] i5;
\tinput[data_width - 1 : 0] i6;
\tinput[data_width - 1 : 0] i7;
\toutput[data_width - 1 : 0] o;
\t
\treg[data_width - 1 : 0] reg_o;
\talways @(*) begin
\t\tcase (sel)
\t\t\t0 : reg_o <= i0;
\t\t\t1 : reg_o <= i1;
\t\t\t2 : reg_o <= i2;
\t\t\t3 : reg_o <= i3;
\t\t\t4 : reg_o <= i4;
\t\t\t5 : reg_o <= i5;
\t\t\t6 : reg_o <= i6;
\t\t\t7 : reg_o <= i7;
\t\t\tdefault : /* default */;
\t\tendcase
\tend
\tassign o = reg_o;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: None
// Engineer: Dai Tianyu (dtysky)
//
// Create Date: 2015/04/07 18:01:07
// Design Name:
// Module Name: DataCombin3
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependenrgb24es:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DataCombin3(i0, i1, i2, o);
\tparameter data_width = 1;
\tinput[data_width - 1 : 0] i0, i1, i2;
\toutput[3 * data_width - 1 : 0] o;
\tassign o = {i2, i1, i0};
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2014/08/30 11:01:22
// Design Name:
// Module Name: Bram8x320x240
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Bram8x320x240(
input [7:0] dina,
input [16:0] addra,
input clka,wea,clkb,
output [7:0] doutb,
input [16:0] addrb
);
BlcokRam8x320x240 u_fb(
.clka ( clka),
.wea (wea),
.addra( addra),
.dina ( dina),
.clkb ( clkb),
.addrb ( addrb),
.doutb ( doutb)
);
endmodule
|
/*
:Project
FPGA-Imaging-Library
:Design
FrameController2
:Function
Controlling a frame(block ram etc.), writing or reading with counts.
For controlling a BlockRAM from xilinx.
Give the first output after mul_delay + 2 + ram_read_latency cycles while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-25
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module FrameController2(
\tclk,
\trst_n,
\tin_count_x,
\tin_count_y,
\tin_enable,
\tin_data,
\tout_ready,
\tout_data,
\tram_addr);
\t/*
\t::description
\tThis module\'s working mode.
\t::range
\t0 for Pipline, 1 for Req-ack
\t*/
\tparameter work_mode = 0;
\t/*
\t::description
\tThis module\'s WR mode.
\t::range
\t0 for Write, 1 for Read
\t*/
\tparameter wr_mode = 0;
\t/*
\t::description
\tData bit width.
\t*/
\tparameter data_width = 8;
\t/*
\t::description
\tWidth of image.
\t::range
\t1 - 4096
\t*/
\tparameter im_width = 320;
\t/*
\t::description
\tHeight of image.
\t::range
\t1 - 4096
\t*/
\tparameter im_height = 240;
\t/*
\t::description
\tThe bits of width of image.
\t::range
\tDepend on width of image
\t*/
\tparameter im_width_bits = 9;
\t/*
\t::description
\tAddress bit width of a ram for storing this image.
\t::range
\tDepend on im_width and im_height.
\t*/
\tparameter addr_width = 17;
\t/*
\t::description
\tRL of RAM, in xilinx 7-series device, it is 2.
\t::range
\t0 - 15, Depend on your using ram.
\t*/
\tparameter ram_read_latency = 2;
\t/*
\t::description
\tDelay for multiplier.
\t::range
\tDepend on your multilpliers\' configurations
\t*/
\tparameter mul_delay = 3;
\t/*
\t::description
\tClock.
\t*/
\tinput clk;
\t/*
\t::description
\tReset, active low.
\t*/
\tinput rst_n;
\t/*
\t::description
\tInput pixel count for width.
\t*/
\tinput[im_width_bits - 1 : 0] in_count_x;
\t/*
\t::description
\tInput pixel count for height.
\t*/
\tinput[im_width_bits - 1 : 0] in_count_y;
\t/*
\t::description
\tInput data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
\t*/
\tinput in_enable;
\t/*
\t::description
\tInput data, it must be synchronous with in_enable.
\t*/
\tinput [data_width - 1 : 0] in_data;
\t/*
\t::description
\tOutput data ready, in both two mode, it will be high while the out_data can be read.
\t*/
\toutput out_ready;
\t/*
\t::description
\tOutput data, it will be synchronous with out_ready.
\t*/
\toutput[data_width - 1 : 0] out_data;
\t/*
\t::description
\tAddress for ram.
\t*/
\toutput[addr_width - 1 : 0] ram_addr;
\treg[3 : 0] con_enable;
\treg[im_width_bits - 1 : 0] reg_in_count_x;
\treg[im_width_bits - 1 : 0] reg_in_count_y;
\treg[addr_width - 1 : 0] reg_addr;
\twire[11 : 0] mul_a, mul_b;
\twire[23 : 0] mul_p;
\tassign mul_a = {{(12 - im_width_bits){1\'b0}}, in_count_y};
\tassign mul_b = im_width;
\tgenvar i;
\tgenerate
\t\t/*
\t\t::description
\t\tMultiplier for Unsigned 12bits x Unsigned 12bits, used for creating address for frame.
\t\tYou can configure the multiplier by yourself, then change the "mul_delay".
\t\tYou can not change the ports\' configurations!
\t\t*/
\t\tMultiplier12x12FR2 Mul(.CLK(clk), .A(mul_a), .B(mul_b), .SCLR(~rst_n), .P(mul_p));
\t\tfor (i = 0; i < mul_delay; i = i + 1) begin : conut_buffer
\t\t\treg[im_width_bits - 1 : 0] b;
\t\t\tif(i == 0) begin
\t\t\t\talways @(posedge clk)
\t\t\t\t\tb <= in_count_x;
\t\t\tend else begin
\t\t\t\talways @(posedge clk)
\t\t\t\t\tb <= conut_buffer[i - 1].b;
\t\t\tend
\t\tend
\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\tif(~rst_n || ~in_enable) begin
\t\t\t\treg_addr <= 0;
\t\t\tend else begin
\t\t\t\treg_addr <= mul_p + conut_buffer[mul_delay - 1].b;
\t\t\tend
\t\tend
\t\tassign ram_addr = reg_addr;
\t\tif(wr_mode == 0) begin
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\tcon_enable <= 0;
\t\t\t\telse if(con_enable == mul_delay + 1)
\t\t\t\t\tcon_enable <= con_enable;
\t\t\t\telse
\t\t\t\t\tcon_enable <= con_enable + 1;
\t\t\tend
\t\t\tassign out_ready = con_enable == mul_delay + 1 ? 1 : 0;
\t\t\tif(work_mode == 0) begin
\t\t\t\tfor (i = 0; i < mul_delay + 1; i = i + 1) begin : buffer
\t\t\t\t\treg[data_width - 1 : 0] b;
\t\t\t\t\tif(i == 0) begin
\t\t\t\t\t\talways @(posedge clk)
\t\t\t\t\t\t\tb <= in_data;
\t\t\t\t\tend else begin
\t\t\t\t\t\talways @(posedge clk)
\t\t\t\t\t\t\tb <= buffer[i - 1].b;
\t\t\t\t\tend
\t\t\t\tend
\t\t\t\tassign out_data = out_ready ? buffer[mul_delay].b : 0;
\t\t\tend else begin
\t\t\t\treg[data_width - 1 : 0] reg_out_data;
\t\t\t\talways @(posedge in_enable)
\t\t\t\t\treg_out_data = in_data;
\t\t\t\tassign out_data = out_ready ? reg_out_data : 0;
\t\t\tend
\t\tend else begin
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\tcon_enable <= 0;
\t\t\t\telse if (con_enable == mul_delay + 1 + ram_read_latency)
\t\t\t\t\tcon_enable <= con_enable;
\t\t\t\telse
\t\t\t\t\tcon_enable <= con_enable + 1;
\t\t\tend
\t\t\tassign out_data = out_ready ? in_data : 0;
\t\t\tassign out_ready = con_enable == mul_delay + 1 + ram_read_latency ? 1 : 0;
\t\tend
\tendgenerate
endmodule
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
ThresholdLocal
:Function
Local thresholding by Threshold from filters.
It will give the first output after 1 cycle while the tow input both enable.
ref_enable must enable after in_enable !
:Module
Main module
:Version
1.0
:Modified
2015-05-22
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module ThresholdLocal(
\tclk,
\trst_n,
\tin_enable,
\tin_data,
\tref_enable,
\tref_data,
\tout_ready,
\tout_data);
\t/*
\t::description
\tThis module's working mode.
\t::range
\t0 for Pipline, 1 for Req-ack
\t*/
\tparameter[0 : 0] work_mode = 0;
\t/*
\t::description
\tThe width(and height) of input window, if input is not a window, set it to 1.
\t::range
\t1 - 15
\t*/
\tparameter[3 : 0] in_window_width = 1;
\t/*
\t::description
\tColor's bit width.
\t::range
\t1 - 12
\t*/
\tparameter[3 : 0] color_width = 8;
\t/*
\t::description
\tThe possible max cycles from in_enable to ref_enable.
\t*/
\tparameter max_delay = 8;
\t/*
\t::description
\tWidth bits of max delay.
\t::range
\tDepend on max delay
\t*/
\tparameter max_delay_bits = 4;
\t/*
\t::description
\tClock.
\t*/
\tinput clk;
\t/*
\t::description
\tReset, active low.
\t*/
\tinput rst_n;
\t/*
\t::description
\tFilter's rank, if half of full size of window, this module working as median filter, etc.
\t*/
\tinput in_enable;
\t/*
\t::description
\tInput data, it must be synchronous with in_enable.
\t*/
\tinput [color_width * in_window_width * in_window_width - 1 : 0] in_data;
\t/*
\t::description
\tThreshold enable.
\t*/
\tinput ref_enable;
\t/*
\t::description
\tThreshold, used as threshold for thresholding, it must be synchronous with ref_enable.
\t*/
\tinput[color_width - 1 : 0] ref_data;
\t/*
\t::description
\tOutput data ready, in both two mode, it will be high while the out_data can be read.
\t*/
\toutput out_ready;
\t/*
\t::description
\tOutput data, it will be synchronous with out_ready.
\t*/
\toutput out_data;
\treg reg_out_ready;
\treg reg_out_data;
\treg[max_delay_bits - 1 : 0] con_out;
\tgenvar i, j;
\tgenerate
\t\tif(work_mode == 0) begin
\t\t\treg[color_width - 1 : 0] buffer[0 : max_delay - 1];
\t\t\twire[max_delay - 1 : 0] res;
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\tcon_out <= 0;
\t\t\t\telse if(con_out == max_delay)
\t\t\t\t\tcon_out <= con_out;
\t\t\t\telse if(~ref_enable)
\t\t\t\t\tcon_out <= con_out + 1;
\t\t\t\telse
\t\t\t\t\tcon_out <= con_out;
\t\t\tend
\t\t\talways @(posedge clk or negedge rst_n or negedge ref_enable) begin
\t\t\t\tif(~rst_n || ~ref_enable) begin
\t\t\t\t\treg_out_ready <= 0;
\t\t\t\t\treg_out_data <= 0;
\t\t\t\tend else begin
\t\t\t\t\treg_out_ready <= 1;
\t\t\t\t\treg_out_data <= res[con_out - 1];
\t\t\t\tend
\t\t\tend
\t\t\tfor (i = 0; i < max_delay; i = i + 1) begin
\t\t\t\tif(i == 0) begin
\t\t\t\t\talways @(posedge clk)
\t\t\t\t\t\tbuffer[i] <= in_data[((in_window_width * in_window_width >> 1) + 1) * color_width - 1 : (in_window_width * in_window_width >> 1) * color_width];
\t\t\t\tend else begin
\t\t\t\t\talways @(posedge clk)
\t\t\t\t\t\tbuffer[i] <= buffer[i - 1];
\t\t\t\tend
\t\t\t\tassign res[i] = buffer[i] < ref_data ? 0 : 1;
\t\t\tend
\t\tend else begin
\t\t\talways @(posedge clk or negedge rst_n or negedge ref_enable) begin
\t\t\t\tif(~rst_n || ~ref_enable) begin
\t\t\t\t\treg_out_ready <= 0;
\t\t\t\t\treg_out_data <= 0;
\t\t\t\tend else begin
\t\t\t\t\treg_out_ready <= 1;
\t\t\t\t\treg_out_data <= in_data < ref_data ? 0 : 1;
\t\t\t\tend
\t\t\tend
\t\tend
\t\tassign out_ready = reg_out_ready;
\t\tassign out_data = reg_out_data;
\tendgenerate
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
// Date : Mon May 25 17:58:01 2015
// Host : Dtysky running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// b:/Complex_Mind/FPGA-Imaging-Library/Master/Generator/FrameController2/HDL/FrameController2.srcs/sources_1/ip/Multiplier12x12FR2/Multiplier12x12FR2_funcsim.v
// Design : Multiplier12x12FR2
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "mult_gen_v12_0,Vivado 2014.4" *) (* CHECK_LICENSE_TYPE = "Multiplier12x12FR2,mult_gen_v12_0,{}" *)
(* core_generation_info = "Multiplier12x12FR2,mult_gen_v12_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=zynq,C_HAS_CE=0,C_HAS_SCLR=1,C_LATENCY=3,C_A_WIDTH=12,C_A_TYPE=1,C_B_WIDTH=12,C_B_TYPE=1,C_OUT_HIGH=23,C_OUT_LOW=0,C_MULT_TYPE=1,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}" *)
(* NotValidForBitStream *)
module Multiplier12x12FR2
(CLK,
A,
B,
SCLR,
P);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) input CLK;
input [11:0]A;
input [11:0]B;
(* x_interface_info = "xilinx.com:signal:reset:1.0 sclr_intf RST" *) input SCLR;
output [23:0]P;
wire [11:0]A;
wire [11:0]B;
wire CLK;
wire [23:0]P;
wire SCLR;
wire [47:0]NLW_U0_PCASC_UNCONNECTED;
wire [1:0]NLW_U0_ZERO_DETECT_UNCONNECTED;
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "12" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "12" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "3" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "1" *)
(* C_OPTIMIZE_GOAL = "1" *)
(* C_OUT_HIGH = "23" *)
(* C_OUT_LOW = "0" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* DONT_TOUCH *)
(* downgradeipidentifiedwarnings = "yes" *)
Multiplier12x12FR2_mult_gen_v12_0__parameterized0 U0
(.A(A),
.B(B),
.CE(1\'b1),
.CLK(CLK),
.P(P),
.PCASC(NLW_U0_PCASC_UNCONNECTED[47:0]),
.SCLR(SCLR),
.ZERO_DETECT(NLW_U0_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule
(* ORIG_REF_NAME = "mult_gen_v12_0" *) (* C_VERBOSITY = "0" *) (* C_MODEL_TYPE = "0" *)
(* C_OPTIMIZE_GOAL = "1" *) (* C_XDEVICEFAMILY = "zynq" *) (* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *) (* C_LATENCY = "3" *) (* C_A_WIDTH = "12" *)
(* C_A_TYPE = "1" *) (* C_B_WIDTH = "12" *) (* C_B_TYPE = "1" *)
(* C_OUT_HIGH = "23" *) (* C_OUT_LOW = "0" *) (* C_MULT_TYPE = "1" *)
(* C_CE_OVERRIDES_SCLR = "0" *) (* C_CCM_IMP = "0" *) (* C_B_VALUE = "10000001" *)
(* C_HAS_ZERO_DETECT = "0" *) (* C_ROUND_OUTPUT = "0" *) (* C_ROUND_PT = "0" *)
(* downgradeipidentifiedwarnings = "yes" *)
module Multiplier12x12FR2_mult_gen_v12_0__parameterized0
(CLK,
A,
B,
CE,
SCLR,
ZERO_DETECT,
P,
PCASC);
input CLK;
input [11:0]A;
input [11:0]B;
input CE;
input SCLR;
output [1:0]ZERO_DETECT;
output [23:0]P;
output [47:0]PCASC;
wire [11:0]A;
wire [11:0]B;
wire CE;
wire CLK;
wire [23:0]P;
wire [47:0]PCASC;
wire SCLR;
wire [1:0]ZERO_DETECT;
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "12" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "12" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "3" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "1" *)
(* C_OPTIMIZE_GOAL = "1" *)
(* C_OUT_HIGH = "23" *)
(* C_OUT_LOW = "0" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* downgradeipidentifiedwarnings = "yes" *)
Multiplier12x12FR2_mult_gen_v12_0_viv__parameterized0 i_mult
(.A(A),
.B(B),
.CE(CE),
.CLK(CLK),
.P(P),
.PCASC(PCASC),
.SCLR(SCLR),
.ZERO_DETECT(ZERO_DETECT));
endmodule
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`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
/*
:Project
FPGA-Imaging-Library
:Design
FixedRoundUnsigned
:Function
Round for unsigned fixed number.
Give the first output after 1 cycle.
:Module
Main module
:Version
1.0
:Modified
2015-05-16
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module FixedRoundUnsigned(
\tclk,
\tfixed_num,
\trounded_num
\t);
\tparameter num_width = 42;
\tparameter fixed_pos = 16;
\tinput clk;
\tinput [num_width - 1 : 0] fixed_num;
\toutput [num_width - fixed_pos - 1 : 0] rounded_num;
\treg [num_width - fixed_pos - 1 : 0] reg_rounded_num;
\tassign rounded_num = reg_rounded_num;
\talways @(posedge clk)
\t\treg_rounded_num <= fixed_num[fixed_pos - 1] == 0 ?
\t\t\tfixed_num[num_width -1 : fixed_pos] :
\t\t\tfixed_num[num_width -1 : fixed_pos] + 1;
endmodule
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
Graying
:Function
Covert RGB images to gray-scale images.
Users can configure the multipliers by themselves.
Give the first output after mul_delay + 2 cycles while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-12
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module Graying(
\tclk,
\trst_n,
\tin_enable,
\tin_data,
\tout_ready,
\tout_data
);
\t/*
\t::description
\tThis module\'s working mode.
\t::range
\t0 for Pipeline, 1 for Req-ack
\t*/
\tparameter work_mode = 0;
\t/*
\t::description
\tColor\'s bit width.
\t::range
\t1 - 12
\t*/
\tparameter color_width = 8;
\t/*
\t::description
\tDelay for multiplier.
\t::range
\tDepend your multilpliers\' configurations
\t*/
\tparameter mul_delay = 3;
\t/*
\t::description
\tClock.
\t*/
\tinput clk;
\t/*
\t::description
\tReset, active low.
\t*/
\tinput rst_n;
\t/*
\t::description
\tInput data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be changes.
\t*/
\tinput in_enable;
\t/*
\t::description
\tInput data, it must be synchronous with in_enable.
\t*/
\tinput [3 * color_width - 1 : 0] in_data;
\t/*
\t::description
\tOutput data ready, in both two mode, it will be high while the out_data can be read.
\t*/
\toutput out_ready;
\t/*
\t::description
\tOutput data, it will be synchronous with out_ready.
\t*/
\toutput[color_width - 1 : 0] out_data;
\treg[color_width - 1 : 0] reg_out_data;
\treg[color_width - 1 : 0] r, g, b;
\twire[10 : 0] mul_r;
\twire[11 : 0] mul_g;
\twire[8 : 0] mul_b;
\treg[2 : 0] con_enable;
\tgenvar i;
\tgenerate
\t\tif(work_mode == 0) begin
\t\t\talways @(*) begin
\t\t\t\tr = in_data[3 * color_width - 1 : 2 * color_width];
\t\t\t\tg = in_data[2 * color_width - 1 : 1 * color_width];
\t\t\t\tb = in_data[1 * color_width - 1 : 0 * color_width];
\t\t\tend
\t\tend else begin
\t\t\talways @(posedge in_enable) begin
\t\t\t\tr = in_data[3 * color_width - 1 : 2 * color_width];
\t\t\t\tg = in_data[2 * color_width - 1 : 1 * color_width];
\t\t\t\tb = in_data[1 * color_width - 1 : 0 * color_width];
\t\t\tend
\t\tend
\t
\t\t/*
\t\t::description
\t\tMultiplier for Unsigned 12bits x 0.299, used for red channel.
\t\tYou can configure the multiplier by yourself, then change the "mul_delay".
\t\tAll Multiplier\'s pipeline stage must be same, you can not change the ports\' configurations!
\t\t*/
\t\tMultiplierRedx0d299 MulRed(.CLK (clk), .A({{12 - color_width{1\'b0}} ,r}), .SCLR(~rst_n), .P(mul_r));
\t\t/*
\t\t::description
\t\tMultiplier for Unsigned 12bits x 0.587, used for green channel.
\t\tYou can configure the multiplier by yourself, then change the "mul_delay".
\t\tAll Multiplier\'s pipeline stage must be same, you can not change the ports\' configurations!
\t\t*/
\t\tMultiplierGreenx0d587 MulGreen(.CLK (clk), .A({{12 - color_width{1\'b0}} ,g}), .SCLR(~rst_n), .P(mul_g));
\t\t/*
\t\t::description
\t\tMultiplier for Unsigned 12bits x 0.114, used for blue channel.
\t\tYou can configure the multiplier by yourself, then change the "mul_delay".
\t\tAll Multiplier\'s pipeline stage must be same, you can not change the ports\' configurations!
\t\t*/
\t\tMultiplierBluex0d114 MulBlue(.CLK (clk), .A({{12 - color_width{1\'b0}} ,b}), .SCLR(~rst_n), .P(mul_b));
\t\treg[11 : 0] mul_g_buffer;
\t\treg[color_width - 1 : 0] sum_tmp;
\t\talways @(posedge clk) begin
\t\t\tmul_g_buffer <= mul_g;
\t\t\tsum_tmp <= mul_r + mul_b;
\t\tend
\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\tif(~rst_n || ~in_enable) begin
\t\t\t\treg_out_data <= 0;
\t\t\tend else begin
\t\t\t\treg_out_data <= sum_tmp + mul_g_buffer;
\t\t\tend
\t\tend
\t\tassign out_data = out_ready ? reg_out_data : 0;
\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\tif(~rst_n || ~in_enable)
\t\t\t\tcon_enable <= 0;
\t\t\telse if(con_enable == mul_delay + 2)
\t\t\t\tcon_enable <= con_enable;
\t\t\telse
\t\t\t\tcon_enable <= con_enable + 1;
\t\tend
\t\tassign out_ready = con_enable == mul_delay + 2 ? 1 : 0;
\tendgenerate
endmodule
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
FrameController
:Function
For controlling a BlockRAM from xilinx.
Give the first output after ram_read_latency cycles while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-12
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module FrameController(
\tclk,
\trst_n,
\tin_enable,
\tin_data,
\tout_ready,
\tout_data,
\tram_addr);
\t/*
\t::description
\tThis module's working mode.
\t::range
\t0 for Pipline, 1 for Req-ack
\t*/
\tparameter work_mode = 0;
\t/*
\t::description
\tThis module's WR mode.
\t::range
\t0 for Write, 1 for Read
\t*/
\tparameter wr_mode = 0;
\t/*
\t::description
\tData bit width.
\t*/
\tparameter data_width = 8;
\t/*
\t::description
\tWidth of image.
\t::range
\t1 - 4096
\t*/
\tparameter im_width = 320;
\t/*
\t::description
\tHeight of image.
\t::range
\t1 - 4096
\t*/
\tparameter im_height = 240;
\t/*
\t::description
\tAddress bit width of a ram for storing this image.
\t::range
\tDepend on im_width and im_height.
\t*/
\tparameter addr_width = 17;
\t/*
\t::description
\tRL of RAM, in xilinx 7-series device, it is 2.
\t::range
\t0 - 15, Depend on your using ram.
\t*/
\tparameter ram_read_latency = 2;
\t/*
\t::description
\tThe first row you want to storing, used for eliminating offset.
\t::range
\tDepend on your input offset.
\t*/
\tparameter row_init = 0;
\t/*
\t::description
\tClock.
\t*/
\tinput clk;
\t/*
\t::description
\tReset, active low.
\t*/
\tinput rst_n;
\t/*
\t::description
\tInput data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
\t*/
\tinput in_enable;
\t/*
\t::description
\tInput data, it must be synchronous with in_enable.
\t*/
\tinput [data_width - 1 : 0] in_data;
\t/*
\t::description
\tOutput data ready, in both two mode, it will be high while the out_data can be read.
\t*/
\toutput out_ready;
\t/*
\t::description
\tOutput data, it will be synchronous with out_ready.
\t*/
\toutput[data_width - 1 : 0] out_data;
\t/*
\t::description
\tAddress for ram.
\t*/
\toutput[addr_width - 1 : 0] ram_addr;
\treg[addr_width - 1 : 0] reg_ram_addr;
\treg[3 : 0] con_ready;
\tassign ram_addr = reg_ram_addr;
\tassign out_data = out_ready ? in_data : 0;
\tgenerate
\t\tif(wr_mode == 0) begin
\t\t\tif(work_mode == 0) begin
\t\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\t\treg_ram_addr <= row_init * im_width;
\t\t\t\t\telse if(reg_ram_addr == im_width * im_height - 1)
\t\t\t\t\t\treg_ram_addr <= 0;
\t\t\t\t\telse
\t\t\t\t\t\treg_ram_addr <= reg_ram_addr + 1;
\t\t\t\tend
\t\t\tend else begin
\t\t\t\talways @(posedge in_enable or negedge rst_n) begin
\t\t\t\t\tif(~rst_n)
\t\t\t\t\t\treg_ram_addr <= row_init * im_width - 1;
\t\t\t\t\telse if(reg_ram_addr == im_width * im_height - 1)
\t\t\t\t\t\treg_ram_addr <= 0;
\t\t\t\t\telse
\t\t\t\t\t\treg_ram_addr <= reg_ram_addr + 1;
\t\t\t\tend
\t\t\tend
\t\t\tassign out_ready = ~rst_n || ~in_enable ? 0 : 1;
\t\tend else begin
\t\t\tif(work_mode == 0) begin
\t\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\t\treg_ram_addr <= 0;
\t\t\t\t\telse if(reg_ram_addr == im_width * im_height - 1)
\t\t\t\t\t\treg_ram_addr <= 0;
\t\t\t\t\telse
\t\t\t\t\t\treg_ram_addr <= reg_ram_addr + 1;
\t\t\t\tend
\t\t\tend else begin
\t\t\t\talways @(posedge in_enable or negedge rst_n) begin
\t\t\t\t\tif(~rst_n)
\t\t\t\t\t\treg_ram_addr <= 0 - 1;
\t\t\t\t\telse if(reg_ram_addr == im_width * im_height - 1)
\t\t\t\t\t\treg_ram_addr <= 0;
\t\t\t\t\telse
\t\t\t\t\t\treg_ram_addr <= reg_ram_addr + 1;
\t\t\t\tend
\t\t\tend
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\tcon_ready <= 0;
\t\t\t\telse if (con_ready == ram_read_latency)
\t\t\t\t\tcon_ready <= con_ready;
\t\t\t\telse
\t\t\t\t\tcon_ready <= con_ready + 1;
\t\t\tend
\t\t\tassign out_ready = con_ready == ram_read_latency ? 1 : 0;
\t\tend
\tendgenerate
endmodule
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
LightnessTransform
:Function
Change the lightness of an image.
Give the first output after 2 cycles while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-06
Copyright (C) 2015 Tianyu Dai (dtysky)
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module LightnessTransform(
\tclk,
\trst_n,
\tlm_gain,
\tin_enable,
\tin_data,
\tout_ready,
\tout_data
);
\t/*
\t::description
\tThis module's working mode.
\t::range
\t0 for Pipelines, 1 for Req-ack
\t*/
\tparameter[0 : 0] work_mode = 0;
\t/*
\t::description
\tChannels for color, 1 for gray, 3 for rgb, etc.
\t::range
\t1 - Inf
\t*/
\tparameter color_channels = 3;
\t/*
\t::description
\tColor's bit wide
\t::range
\t1 - 12
\t*/
\tparameter[3: 0] color_width = 8;
\t/*
\t::description
\tClock.
\t*/
\tinput clk;
\t/*
\t::description
\tReset, active low.
\t*/
\tinput rst_n;
\t/*
\t::description
\tGain for luminance, signed.
\tThe value must be true code if gain is positive, if negative, must be complemental code.
\t*/
\tinput signed [color_width : 0] lm_gain;
\t/*
\t::description
\tInput data enable, in pipelines mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be changes.
\t*/
\tinput in_enable;
\t/*
\t::description
\tInput data, it must be synchronous with in_enable.
\t*/
\tinput [color_channels * color_width - 1 : 0] in_data;
\t/*
\t::description
\tOutput data ready, in both two mode, it will be high while the out_data can be read.
\t*/
\toutput out_ready;
\t/*
\t::description
\tOutput data, it will be synchronous with out_ready.
\t*/
\toutput[color_channels * color_width - 1 : 0] out_data;
\treg[2 : 0] con_enable;
\tgenvar i;
\tgenerate
\t\t`define h (i + 1) * color_width - 1
\t\t`define l i * color_width
\t\tfor (i = 0; i < color_channels; i = i + 1) begin: channel
\t\t\twire signed[color_width : 0] in_tmp;
\t\t\tif(work_mode == 0) begin
\t\t\t\tassign in_tmp = {1'b0, in_data[`h : `l]};
\t\t\tend else begin
\t\t\t\treg signed[color_width : 0] reg_in_tmp;
\t\t\t\talways @(posedge in_enable)
\t\t\t\t\treg_in_tmp = {1'b0, in_data[`h : `l]};
\t\t\t\tassign in_tmp = reg_in_tmp;
\t\t\tend
\t\t\treg signed [color_width + 1 : 0] add_s;
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\tadd_s <= 0;
\t\t\t\telse
\t\t\t\t\tadd_s <= in_tmp + lm_gain;
\t\t\tend
\t\t\t//For overflow
\t\t\treg[color_width - 1 : 0] out_buffer;
\t\t\talways @(posedge clk) begin
\t\t\t\tif(add_s[color_width + 1] == 1)
\t\t\t\t\tout_buffer <= 0;
\t\t\t\telse if(add_s[color_width] == 1)
\t\t\t\t\tout_buffer <= {color_width{1'b1}};
\t\t\t\telse
\t\t\t\t\tout_buffer <= add_s[color_width - 1 : 0];
\t\t\tend
\t\t\tassign out_data[`h : `l] = out_ready ? out_buffer : 0;
\t\t\t
\t\tend
\t\t`undef h
\t\t`undef l
\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\tif(~rst_n || ~in_enable)
\t\t\t\tcon_enable <= 0;
\t\t\telse if(con_enable == 2)
\t\t\t\tcon_enable <= con_enable;
\t\t\telse
\t\t\t\tcon_enable <= con_enable +1;
\t\tend
\t\tassign out_ready = con_enable == 2 ? 1 : 0;
\tendgenerate
endmodule
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
Pan
:Function
Panning a image from your given offset.
Give the first output after 2 cycles while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-26
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module Pan(
\tclk,
\trst_n,
\toffset_x,
\toffset_y,
\tin_enable,
\tin_data,
\tin_count_x,
\tin_count_y,
\tout_ready,
\tout_data,
\tout_count_x,
\tout_count_y);
\t/*
\t::description
\tThis module's working mode.
\t::range
\t0 for Pipline, 1 for Req-ack
\t*/
\tparameter work_mode = 0;
\t/*
\t::description
\tData bit width.
\t*/
\tparameter data_width = 8;
\t/*
\t::description
\tWidth of image.
\t::range
\t1 - 4096
\t*/
\tparameter im_width = 320;
\t/*
\t::description
\tHeight of image.
\t::range
\t1 - 4096
\t*/
\tparameter im_height = 240;
\t/*
\t::description
\tThe bits of width of image.
\t::range
\tDepend on width of image
\t*/
\tparameter im_width_bits = 9;
\t/*
\t::description
\tClock.
\t*/
\tinput clk;
\t/*
\t::description
\tReset, active low.
\t*/
\tinput rst_n;
\t/*
\t::description
\tOffset for horizontal.
\t::range
\tThe value must be true code if offset is positive, if negative, must be complemental code.
\t*/
\tinput signed [im_width_bits : 0] offset_x;
\t/*
\t::description
\t::description
\tOffset for vertical.
\t::range
\tThe value must be true code if offset is positive, if negative, must be complemental code.
\t*/
\tinput signed [im_width_bits : 0] offset_y;
\t/*
\t::description
\tInput data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
\t*/
\tinput in_enable;
\t/*
\t::description
\tInput data, it must be synchronous with in_enable.
\t*/
\tinput [data_width - 1 : 0] in_data;
\t/*
\t::description
\tInput pixel count for width.
\t*/
\tinput[im_width_bits - 1 : 0] in_count_x;
\t/*
\t::description
\tInput pixel count for height.
\t*/
\tinput[im_width_bits - 1 : 0] in_count_y;
\t/*
\t::description
\tOutput data ready, in both two mode, it will be high while the out_data can be read.
\t*/
\toutput out_ready;
\t/*
\t::description
\tOutput data, it will be synchronous with out_ready.
\t*/
\toutput[data_width - 1 : 0] out_data;
\t/*
\t::description
\tOutput pixel count for height.
\t*/
\toutput[im_width_bits - 1 : 0] out_count_x;
\t/*
\t::description
\tOutput pixel count for height.
\t*/
\toutput[im_width_bits - 1 : 0] out_count_y;
\treg[2 : 0] con_enable;
\treg signed [im_width_bits : 0] addr_sum_x, addr_sum_y;
\treg signed [im_width_bits : 0] tmp_sum_x, tmp_sum_y;
\treg signed [im_width_bits : 0] addr_sp_x, addr_sp_y;
\treg in_range_t, in_range_b, in_range_l, in_range_r;
\tgenvar i;
\tgenerate
\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\tif(~rst_n || ~in_enable)
\t\t\t\tcon_enable <= 0;
\t\t\telse if(con_enable == 2)
\t\t\t\tcon_enable <= con_enable;
\t\t\telse
\t\t\t\tcon_enable <= con_enable + 1;
\t\tend
\t\tassign out_ready = con_enable == 2 ? 1 : 0;
\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\tif(~rst_n || ~in_enable) begin
\t\t\t\taddr_sum_x <= 0;
\t\t\t\taddr_sum_y <= 0;
\t\t\t\ttmp_sum_x <= 0;
\t\t\t\ttmp_sum_y <= 0;
\t\t\tend else begin
\t\t\t\taddr_sum_x <= in_count_x + offset_x;
\t\t\t\taddr_sum_y <= in_count_y + offset_y;
\t\t\t\ttmp_sum_x <= addr_sum_x;
\t\t\t\ttmp_sum_y <= addr_sum_y;
\t\t\tend
\t\tend
\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\tif(~rst_n || ~in_enable) begin
\t\t\t\taddr_sp_x <= 0;
\t\t\t\taddr_sp_y <= 0;
\t\t\tend else begin
\t\t\t\taddr_sp_x <= addr_sum_x < 0 ? addr_sum_x + im_width : addr_sum_x - im_width;
\t\t\t\taddr_sp_y <= addr_sum_y < 0 ? addr_sum_y + im_height : addr_sum_y - im_height;
\t\t\tend
\t\tend
\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\tif(~rst_n || ~in_enable) begin
\t\t\t\tin_range_t <= 0;
\t\t\t\tin_range_b <= 0;
\t\t\t\tin_range_l <= 0;
\t\t\t\tin_range_r <= 0;
\t\t\tend else begin
\t\t\t\tin_range_t <= addr_sum_y >= 0 ? 1 : 0;
\t\t\t\tin_range_b <= addr_sum_y < im_height ? 1 : 0;
\t\t\t\tin_range_l <= addr_sum_x >= 0 ? 1 : 0;
\t\t\t\tin_range_r <= addr_sum_x < im_width ? 1 : 0;
\t\t\tend
\t\tend
\t\tassign out_count_x = in_range_l & in_range_r & out_ready ? tmp_sum_x : addr_sp_x;
\t\tassign out_count_y = in_range_t & in_range_b & out_ready ? tmp_sum_y : addr_sp_y;
\t\tif(work_mode == 0) begin
\t\t\tfor (i = 0; i < 2; i = i + 1) begin : buffer
\t\t\t\treg[data_width - 1 : 0] b;
\t\t\t\tif(i == 0) begin
\t\t\t\t\talways @(posedge clk)
\t\t\t\t\t\tb <= in_data;
\t\t\t\tend else begin
\t\t\t\t\talways @(posedge clk)
\t\t\t\t\t\tb <= buffer[i - 1].b;
\t\t\t\tend
\t\t\tend
\t\t\tassign out_data = out_ready & in_range_t & in_range_b & in_range_l & in_range_r ? buffer[1].b : 0;
\t\tend else begin
\t\t\treg[data_width - 1 : 0] reg_in_data;
\t\t\talways @(posedge in_enable)
\t\t\t\treg_in_data <= in_data;
\t\t\tassign out_data = out_ready & in_range_t & in_range_b & in_range_l & in_range_r ? reg_in_data : 0;
\t\tend
\tendgenerate
endmodule
|
/*
:Project
FPGA-Imaging-Library
:Design
FrameController
:Function
For controlling a BlockRAM from xilinx.
Give the first output after ram_read_latency cycles while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-12
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module FrameController(
\tclk,
\trst_n,
\tin_enable,
\tin_data,
\tout_ready,
\tout_data,
\tram_addr);
\t/*
\t::description
\tThis module's working mode.
\t::range
\t0 for Pipline, 1 for Req-ack
\t*/
\tparameter work_mode = 0;
\t/*
\t::description
\tThis module's WR mode.
\t::range
\t0 for Write, 1 for Read
\t*/
\tparameter wr_mode = 0;
\t/*
\t::description
\tData bit width.
\t*/
\tparameter data_width = 8;
\t/*
\t::description
\tWidth of image.
\t::range
\t1 - 4096
\t*/
\tparameter im_width = 320;
\t/*
\t::description
\tHeight of image.
\t::range
\t1 - 4096
\t*/
\tparameter im_height = 240;
\t/*
\t::description
\tAddress bit width of a ram for storing this image.
\t::range
\tDepend on im_width and im_height.
\t*/
\tparameter addr_width = 17;
\t/*
\t::description
\tRL of RAM, in xilinx 7-series device, it is 2.
\t::range
\t0 - 15, Depend on your using ram.
\t*/
\tparameter ram_read_latency = 2;
\t/*
\t::description
\tThe first row you want to storing, used for eliminating offset.
\t::range
\tDepend on your input offset.
\t*/
\tparameter row_init = 0;
\t/*
\t::description
\tClock.
\t*/
\tinput clk;
\t/*
\t::description
\tReset, active low.
\t*/
\tinput rst_n;
\t/*
\t::description
\tInput data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
\t*/
\tinput in_enable;
\t/*
\t::description
\tInput data, it must be synchronous with in_enable.
\t*/
\tinput [data_width - 1 : 0] in_data;
\t/*
\t::description
\tOutput data ready, in both two mode, it will be high while the out_data can be read.
\t*/
\toutput out_ready;
\t/*
\t::description
\tOutput data, it will be synchronous with out_ready.
\t*/
\toutput[data_width - 1 : 0] out_data;
\t/*
\t::description
\tAddress for ram.
\t*/
\toutput[addr_width - 1 : 0] ram_addr;
\treg[addr_width - 1 : 0] reg_ram_addr;
\treg[3 : 0] con_ready;
\tassign ram_addr = reg_ram_addr;
\tassign out_data = out_ready ? in_data : 0;
\tgenerate
\t\tif(wr_mode == 0) begin
\t\t\tif(work_mode == 0) begin
\t\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\t\treg_ram_addr <= row_init * im_width;
\t\t\t\t\telse if(reg_ram_addr == im_width * im_height - 1)
\t\t\t\t\t\treg_ram_addr <= 0;
\t\t\t\t\telse
\t\t\t\t\t\treg_ram_addr <= reg_ram_addr + 1;
\t\t\t\tend
\t\t\tend else begin
\t\t\t\talways @(posedge in_enable or negedge rst_n) begin
\t\t\t\t\tif(~rst_n)
\t\t\t\t\t\treg_ram_addr <= row_init * im_width - 1;
\t\t\t\t\telse if(reg_ram_addr == im_width * im_height - 1)
\t\t\t\t\t\treg_ram_addr <= 0;
\t\t\t\t\telse
\t\t\t\t\t\treg_ram_addr <= reg_ram_addr + 1;
\t\t\t\tend
\t\t\tend
\t\t\tassign out_ready = ~rst_n || ~in_enable ? 0 : 1;
\t\tend else begin
\t\t\tif(work_mode == 0) begin
\t\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\t\treg_ram_addr <= 0;
\t\t\t\t\telse if(reg_ram_addr == im_width * im_height - 1)
\t\t\t\t\t\treg_ram_addr <= 0;
\t\t\t\t\telse
\t\t\t\t\t\treg_ram_addr <= reg_ram_addr + 1;
\t\t\t\tend
\t\t\tend else begin
\t\t\t\talways @(posedge in_enable or negedge rst_n) begin
\t\t\t\t\tif(~rst_n)
\t\t\t\t\t\treg_ram_addr <= 0 - 1;
\t\t\t\t\telse if(reg_ram_addr == im_width * im_height - 1)
\t\t\t\t\t\treg_ram_addr <= 0;
\t\t\t\t\telse
\t\t\t\t\t\treg_ram_addr <= reg_ram_addr + 1;
\t\t\t\tend
\t\t\tend
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\tcon_ready <= 0;
\t\t\t\telse if (con_ready == ram_read_latency)
\t\t\t\t\tcon_ready <= con_ready;
\t\t\t\telse
\t\t\t\t\tcon_ready <= con_ready + 1;
\t\t\tend
\t\t\tassign out_ready = con_ready == ram_read_latency ? 1 : 0;
\t\tend
\tendgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: None
// Engineer: Dai Tianyu (dtysky)
//
// Create Date: 2015/04/07 18:01:07
// Design Name:
// Module Name: DataWidthConvert
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependenrgb24es:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DataWidthConvert(i, o);
\tparameter data_width_in = 32;
\tparameter data_width_out = 4;\t
\tinput[data_width_in - 1 : 0] i;
\toutput[data_width_out - 1 : 0] o;
\tgenerate
\t\tif(data_width_in >= data_width_out) begin
\t\t\tassign o = i[data_width_in - 1 : 0];
\t\tend else begin
\t\t\tassign o = {{data_width_out - data_width_in{1'b0}} ,i};
\t\tend
\tendgenerate
endmodule
|
module IICctrl
(
\tinput\t\t\t\tiCLK,
\tinput\t\t\t\tiRST_N,
\toutput\t\t\t\tI2C_SCLK,\t
\tinout\t\t\t\tI2C_SDAT\t
);
parameter\tLUT_SIZE\t=\t170;
reg\t[7:0]\tLUT_INDEX;
wire [7:0]\tI2C_RDATA;
reg\t\t\tConfig_Done;
parameter\tCLK_Freq\t=\t25_000000;\t
parameter\tI2C_Freq\t=\t10_000;\t\t
reg\t[15:0]\tmI2C_CLK_DIV;\t\t\t\t
reg\t\t\tmI2C_CTRL_CLK;\t\t\t\t
always@(posedge iCLK or negedge iRST_N)
begin
\tif(!iRST_N)
\t\tbegin
\t\tmI2C_CLK_DIV\t<=\t0;
\t\tmI2C_CTRL_CLK\t<=\t0;
\t\tend
\telse
\t\tbegin
\t\t if( mI2C_CLK_DIV\t< (CLK_Freq/I2C_Freq)/2)
\t\t\t mI2C_CLK_DIV\t<=\tmI2C_CLK_DIV + 1'd1;
\t\t else
\t\t\t begin
\t\t\t mI2C_CLK_DIV\t<=\t0;
\t\t\tmI2C_CTRL_CLK\t<=\t~mI2C_CTRL_CLK;
\t\t\tend
\t\tend
end
reg\ti2c_en_r0, i2c_en_r1;
always@(posedge iCLK or negedge iRST_N)
begin
\tif(!iRST_N)
\t\tbegin
\t\ti2c_en_r0 <= 0;
\t\ti2c_en_r1 <= 0;
\t\tend
\telse
\t\tbegin
\t\ti2c_en_r0 <= mI2C_CTRL_CLK;
\t\ti2c_en_r1 <= i2c_en_r0;
\t\tend
end
wire\ti2c_negclk = (i2c_en_r1 & ~i2c_en_r0) ? 1'b1 : 1'b0;\t\t
wire\t\tmI2C_END;\t\t
wire\t\tmI2C_ACK;\t\t
reg\t[1:0]\tmSetup_ST;\t\t
reg\t\t\tmI2C_GO;\t\t
reg\t\t\tmI2C_WR;\t\t
always@(posedge iCLK or negedge iRST_N)\t\t
begin
\tif(!iRST_N)
\t\tbegin
\t\tConfig_Done <= 0;
\t\tLUT_INDEX\t<=\t0;
\t\tmSetup_ST\t<=\t0;
\t\tmI2C_GO\t\t<=\t0;
\t\tmI2C_WR <=\t0;\t
\t\tend
\telse if(i2c_negclk)
\t\tbegin
\t\tif(LUT_INDEX < LUT_SIZE)
\t\t\tbegin
\t\t\tConfig_Done <= 0;
\t\t\tcase(mSetup_ST)
\t\t\t0:\tbegin\t\t\t\t\t\t
\t\t\t\tif(~mI2C_END)\t\t\t\t
\t\t\t\t\tmSetup_ST\t<=\t1;\t\t
\t\t\t\telse\t\t\t\t\t\t
\t\t\t\t\tmSetup_ST\t<=\t0;\t\t\t\t
\t\t\t\tmI2C_GO\t\t<=\t1;\t\t
\t\t\t\tif(LUT_INDEX < 8'd2)\t
\t\t\t\t\tmI2C_WR <= 0;\t\t\t
\t\t\t\telse
\t\t\t\t\tmI2C_WR <= 1;\t\t\t
\t\t\t\tend
\t\t\t1:\t
\t\t\t\tbegin\t\t\t\t\t
\t\t\t\tif(mI2C_END)
\t\t\t\t\tbegin
\t\t\t\t\tmI2C_WR <=\t0;
\t\t\t\t\tmI2C_GO\t\t<=\t0;
\t\t\t\t\tif(~mI2C_ACK)\t\t\t
\t\t\t\t\t\tmSetup_ST\t<=\t2;\t
\t\t\t\t\telse
\t\t\t\t\t\tmSetup_ST\t<=\t0;\t\t\t\t\t\t
\t\t\t\t\tend
\t\t\t\tend
\t\t\t2:\tbegin\t\t\t\t\t\t
\t\t\t\tLUT_INDEX\t<=\tLUT_INDEX + 8'd1;
\t\t\t\tmSetup_ST\t<=\t0;
\t\t\t\tmI2C_GO\t\t<=\t0;
\t\t\t\tmI2C_WR <=\t0;
\t\t\t\tend
\t\t\tendcase
\t\t\tend
\t\telse
\t\t\tbegin
\t\t\tConfig_Done <= 1'b1;
\t\t\tLUT_INDEX \t<= LUT_INDEX;
\t\t\tmSetup_ST\t<=\t0;
\t\t\tmI2C_GO\t\t<=\t0;
\t\t\tmI2C_WR <=\t0;
\t\t\tend
\tend
end
wire\t[15:0]\tLUT_DATA;\t\t
I2C_OV7670_RGB565_Config\tu_I2C_OV7725_RGB565_Config
(
\t.LUT_INDEX\t\t(LUT_INDEX),
\t.LUT_DATA\t\t(LUT_DATA)
);
I2C_Controller \tu_I2C_Controller\t
(\t
\t.iCLK\t\t\t(iCLK),
\t.iRST_N\t\t\t(iRST_N),
\t\t\t\t\t\t\t
\t.I2C_CLK\t\t(mI2C_CTRL_CLK),\t
\t.I2C_EN\t\t\t(i2c_negclk),\t\t
\t.I2C_WDATA\t\t({8'h42, LUT_DATA}),
\t.I2C_SCLK\t\t(I2C_SCLK),\t\t\t
\t.I2C_SDAT\t\t(I2C_SDAT),\t\t\t
\t
\t.GO\t\t\t\t(mI2C_GO),\t\t\t
\t.WR\t\t\t\t(mI2C_WR), \t
\t.ACK\t\t\t(mI2C_ACK),\t\t\t
\t.END\t\t\t(mI2C_END),\t\t\t
\t.I2C_RDATA\t\t(I2C_RDATA)\t\t\t
);\t\t
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
// Date : Tue May 19 00:42:50 2015
// Host : Dtysky running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// b:/Complex_Mind/FPGA-Imaging-Library/Master/Generator/RowsGenerator/HDL/RowsGenerator.srcs/sources_1/ip/Fifo8xWidthRows/Fifo8xWidthRows_funcsim.v
// Design : Fifo8xWidthRows
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "fifo_generator_v12_0,Vivado 2014.4" *) (* CHECK_LICENSE_TYPE = "Fifo8xWidthRows,fifo_generator_v12_0,{}" *)
(* core_generation_info = "Fifo8xWidthRows,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=9,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=8,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=8,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=1,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=2,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=510,C_PROG_FULL_THRESH_NEGATE_VAL=509,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=9,C_RD_DEPTH=512,C_RD_FREQ=1,C_RD_PNTR_WIDTH=9,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=9,C_WR_DEPTH=512,C_WR_FREQ=1,C_WR_PNTR_WIDTH=9,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}" *)
(* NotValidForBitStream *)
module Fifo8xWidthRows
(clk,
rst,
din,
wr_en,
rd_en,
dout,
full,
empty,
data_count);
input clk;
input rst;
input [7:0]din;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en;
output [7:0]dout;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty;
output [8:0]data_count;
wire clk;
wire [8:0]data_count;
wire [7:0]din;
wire [7:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire wr_en;
wire NLW_U0_almost_empty_UNCONNECTED;
wire NLW_U0_almost_full_UNCONNECTED;
wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_overflow_UNCONNECTED;
wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_underflow_UNCONNECTED;
wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_overflow_UNCONNECTED;
wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_underflow_UNCONNECTED;
wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
wire NLW_U0_axi_b_overflow_UNCONNECTED;
wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
wire NLW_U0_axi_b_prog_full_UNCONNECTED;
wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
wire NLW_U0_axi_b_underflow_UNCONNECTED;
wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
wire NLW_U0_axi_r_overflow_UNCONNECTED;
wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
wire NLW_U0_axi_r_prog_full_UNCONNECTED;
wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
wire NLW_U0_axi_r_underflow_UNCONNECTED;
wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
wire NLW_U0_axi_w_overflow_UNCONNECTED;
wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
wire NLW_U0_axi_w_prog_full_UNCONNECTED;
wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
wire NLW_U0_axi_w_underflow_UNCONNECTED;
wire NLW_U0_axis_dbiterr_UNCONNECTED;
wire NLW_U0_axis_overflow_UNCONNECTED;
wire NLW_U0_axis_prog_empty_UNCONNECTED;
wire NLW_U0_axis_prog_full_UNCONNECTED;
wire NLW_U0_axis_sbiterr_UNCONNECTED;
wire NLW_U0_axis_underflow_UNCONNECTED;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_m_axi_arvalid_UNCONNECTED;
wire NLW_U0_m_axi_awvalid_UNCONNECTED;
wire NLW_U0_m_axi_bready_UNCONNECTED;
wire NLW_U0_m_axi_rready_UNCONNECTED;
wire NLW_U0_m_axi_wlast_UNCONNECTED;
wire NLW_U0_m_axi_wvalid_UNCONNECTED;
wire NLW_U0_m_axis_tlast_UNCONNECTED;
wire NLW_U0_m_axis_tvalid_UNCONNECTED;
wire NLW_U0_overflow_UNCONNECTED;
wire NLW_U0_prog_empty_UNCONNECTED;
wire NLW_U0_prog_full_UNCONNECTED;
wire NLW_U0_rd_rst_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_s_axis_tready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire NLW_U0_underflow_UNCONNECTED;
wire NLW_U0_valid_UNCONNECTED;
wire NLW_U0_wr_ack_UNCONNECTED;
wire NLW_U0_wr_rst_busy_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;
wire [8:0]NLW_U0_rd_data_count_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
wire [8:0]NLW_U0_wr_data_count_UNCONNECTED;
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "1" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "9" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "8" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "32" *)
(* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "32" *)
(* C_DIN_WIDTH_WDCH = "64" *)
(* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "8" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "zynq" *)
(* C_FULL_FLAGS_RST_VAL = "1" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "1" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "0" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "0" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "2" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *)
(* C_PRELOAD_REGS = "0" *)
(* C_PRIM_FIFO_TYPE = "512x36" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *)
(* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "510" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "509" *)
(* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "9" *)
(* C_RD_DEPTH = "512" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "9" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "9" *)
(* C_WR_DEPTH = "512" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "9" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
Fifo8xWidthRows_fifo_generator_v12_0__parameterized0 U0
(.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
.almost_full(NLW_U0_almost_full_UNCONNECTED),
.axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
.axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
.axi_ar_injectdbiterr(1\'b0),
.axi_ar_injectsbiterr(1\'b0),
.axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
.axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
.axi_ar_prog_empty_thresh({1\'b0,1\'b0,1\'b0,1\'b0}),
.axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
.axi_ar_prog_full_thresh({1\'b0,1\'b0,1\'b0,1\'b0}),
.axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
.axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
.axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
.axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
.axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
.axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
.axi_aw_injectdbiterr(1\'b0),
.axi_aw_injectsbiterr(1\'b0),
.axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
.axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
.axi_aw_prog_empty_thresh({1\'b0,1\'b0,1\'b0,1\'b0}),
.axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
.axi_aw_prog_full_thresh({1\'b0,1\'b0,1\'b0,1\'b0}),
.axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
.axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
.axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
.axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
.axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
.axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
.axi_b_injectdbiterr(1\'b0),
.axi_b_injectsbiterr(1\'b0),
.axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
.axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
.axi_b_prog_empty_thresh({1\'b0,1\'b0,1\'b0,1\'b0}),
.axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
.axi_b_prog_full_thresh({1\'b0,1\'b0,1\'b0,1\'b0}),
.axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
.axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
.axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
.axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
.axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
.axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
.axi_r_injectdbiterr(1\'b0),
.axi_r_injectsbiterr(1\'b0),
.axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
.axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
.axi_r_prog_empty_thresh({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
.axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
.axi_r_prog_full_thresh({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
.axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
.axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
.axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
.axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
.axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
.axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
.axi_w_injectdbiterr(1\'b0),
.axi_w_injectsbiterr(1\'b0),
.axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
.axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
.axi_w_prog_empty_thresh({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
.axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
.axi_w_prog_full_thresh({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
.axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
.axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
.axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
.axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
.axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),
.axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
.axis_injectdbiterr(1\'b0),
.axis_injectsbiterr(1\'b0),
.axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
.axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
.axis_prog_empty_thresh({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
.axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
.axis_prog_full_thresh({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
.axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),
.axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
.axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
.axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),
.backup(1\'b0),
.backup_marker(1\'b0),
.clk(clk),
.data_count(data_count),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1\'b0),
.injectsbiterr(1\'b0),
.int_clk(1\'b0),
.m_aclk(1\'b0),
.m_aclk_en(1\'b0),
.m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
.m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
.m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(1\'b0),
.m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
.m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1\'b0),
.m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
.m_axi_bid(1\'b0),
.m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1\'b0,1\'b0}),
.m_axi_buser(1\'b0),
.m_axi_bvalid(1\'b0),
.m_axi_rdata({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
.m_axi_rid(1\'b0),
.m_axi_rlast(1\'b0),
.m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
.m_axi_rresp({1\'b0,1\'b0}),
.m_axi_ruser(1\'b0),
.m_axi_rvalid(1\'b0),
.m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
.m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1\'b0),
.m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
.m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
.m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),
.m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
.m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
.m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),
.m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),
.m_axis_tready(1\'b0),
.m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),
.m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),
.m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),
.overflow(NLW_U0_overflow_UNCONNECTED),
.prog_empty(NLW_U0_prog_empty_UNCONNECTED),
.prog_empty_thresh({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
.prog_empty_thresh_assert({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
.prog_empty_thresh_negate({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
.prog_full(NLW_U0_prog_full_UNCONNECTED),
.prog_full_thresh({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
.prog_full_thresh_assert({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
.prog_full_thresh_negate({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
.rd_clk(1\'b0),
.rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[8:0]),
.rd_en(rd_en),
.rd_rst(1\'b0),
.rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
.rst(rst),
.s_aclk(1\'b0),
.s_aclk_en(1\'b0),
.s_aresetn(1\'b0),
.s_axi_araddr({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
.s_axi_arburst({1\'b0,1\'b0}),
.s_axi_arcache({1\'b0,1\'b0,1\'b0,1\'b0}),
.s_axi_arid(1\'b0),
.s_axi_arlen({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
.s_axi_arlock(1\'b0),
.s_axi_arprot({1\'b0,1\'b0,1\'b0}),
.s_axi_arqos({1\'b0,1\'b0,1\'b0,1\'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arregion({1\'b0,1\'b0,1\'b0,1\'b0}),
.s_axi_arsize({1\'b0,1\'b0,1\'b0}),
.s_axi_aruser(1\'b0),
.s_axi_arvalid(1\'b0),
.s_axi_awaddr({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
.s_axi_awburst({1\'b0,1\'b0}),
.s_axi_awcache({1\'b0,1\'b0,1\'b0,1\'b0}),
.s_axi_awid(1\'b0),
.s_axi_awlen({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
.s_axi_awlock(1\'b0),
.s_axi_awprot({1\'b0,1\'b0,1\'b0}),
.s_axi_awqos({1\'b0,1\'b0,1\'b0,1\'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1\'b0,1\'b0,1\'b0,1\'b0}),
.s_axi_awsize({1\'b0,1\'b0,1\'b0}),
.s_axi_awuser(1\'b0),
.s_axi_awvalid(1\'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1\'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1\'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
.s_axi_wid(1\'b0),
.s_axi_wlast(1\'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
.s_axi_wuser(1\'b0),
.s_axi_wvalid(1\'b0),
.s_axis_tdata({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
.s_axis_tdest(1\'b0),
.s_axis_tid(1\'b0),
.s_axis_tkeep(1\'b0),
.s_axis_tlast(1\'b0),
.s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),
.s_axis_tstrb(1\'b0),
.s_axis_tuser({1\'b0,1\'b0,1\'b0,1\'b0}),
.s_axis_tvalid(1\'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1\'b0),
.srst(1\'b0),
.underflow(NLW_U0_underflow_UNCONNECTED),
.valid(NLW_U0_valid_UNCONNECTED),
.wr_ack(NLW_U0_wr_ack_UNCONNECTED),
.wr_clk(1\'b0),
.wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[8:0]),
.wr_en(wr_en),
.wr_rst(1\'b0),
.wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule
(* ORIG_REF_NAME = "compare" *)
module Fifo8xWidthRows_compare
(comp0,
v1_reg_0,
I1);
output comp0;
input [3:0]v1_reg_0;
input I1;
wire I1;
wire comp0;
wire \
_0_gmux.gm[3].gms.ms ;
wire [3:0]v1_reg_0;
wire [2:0]\\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \\gmux.gm[0].gm1.m1_CARRY4
(.CI(1\'b0),
.CO({\
_0_gmux.gm[3].gms.ms ,\\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1\'b1),
.DI({1\'b0,1\'b0,1\'b0,1\'b0}),
.O(\\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_0));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \\gmux.gm[4].gms.ms_CARRY4
(.CI(\
_0_gmux.gm[3].gms.ms ),
.CO({\\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp0}),
.CYINIT(1\'b0),
.DI({\\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1\'b0}),
.O(\\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],I1}));
endmodule
(* ORIG_REF_NAME = "compare" *)
module Fifo8xWidthRows_compare_0
(comp1,
v1_reg_1,
I2);
output comp1;
input [3:0]v1_reg_1;
input I2;
wire I2;
wire comp1;
wire \
_0_gmux.gm[3].gms.ms ;
wire [3:0]v1_reg_1;
wire [2:0]\\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \\gmux.gm[0].gm1.m1_CARRY4
(.CI(1\'b0),
.CO({\
_0_gmux.gm[3].gms.ms ,\\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1\'b1),
.DI({1\'b0,1\'b0,1\'b0,1\'b0}),
.O(\\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_1));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \\gmux.gm[4].gms.ms_CARRY4
(.CI(\
_0_gmux.gm[3].gms.ms ),
.CO({\\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),
.CYINIT(1\'b0),
.DI({\\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1\'b0}),
.O(\\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],I2}));
endmodule
(* ORIG_REF_NAME = "compare" *)
module Fifo8xWidthRows_compare_1
(comp0,
v1_reg,
I1);
output comp0;
input [3:0]v1_reg;
input I1;
wire I1;
wire comp0;
wire \
_0_gmux.gm[3].gms.ms ;
wire [3:0]v1_reg;
wire [2:0]\\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \\gmux.gm[0].gm1.m1_CARRY4
(.CI(1\'b0),
.CO({\
_0_gmux.gm[3].gms.ms ,\\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1\'b1),
.DI({1\'b0,1\'b0,1\'b0,1\'b0}),
.O(\\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \\gmux.gm[4].gms.ms_CARRY4
(.CI(\
_0_gmux.gm[3].gms.ms ),
.CO({\\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp0}),
.CYINIT(1\'b0),
.DI({\\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1\'b0}),
.O(\\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],I1}));
endmodule
(* ORIG_REF_NAME = "compare" *)
module Fifo8xWidthRows_compare_2
(comp1,
v1_reg_1,
I2);
output comp1;
input [3:0]v1_reg_1;
input I2;
wire I2;
wire comp1;
wire \
_0_gmux.gm[3].gms.ms ;
wire [3:0]v1_reg_1;
wire [2:0]\\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \\gmux.gm[0].gm1.m1_CARRY4
(.CI(1\'b0),
.CO({\
_0_gmux.gm[3].gms.ms ,\\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1\'b1),
.DI({1\'b0,1\'b0,1\'b0,1\'b0}),
.O(\\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_1));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \\gmux.gm[4].gms.ms_CARRY4
(.CI(\
_0_gmux.gm[3].gms.ms ),
.CO({\\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),
.CYINIT(1\'b0),
.DI({\\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1\'b0}),
.O(\\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],I2}));
endmodule
(* ORIG_REF_NAME = "dc_ss" *)
module Fifo8xWidthRows_dc_ss
(O1,
DI,
S,
I4,
clk,
Q);
output [8:0]O1;
input [1:0]DI;
input [1:0]S;
input [0:0]I4;
input clk;
input [0:0]Q;
wire [1:0]DI;
wire [0:0]I4;
wire [8:0]O1;
wire [0:0]Q;
wire [1:0]S;
wire clk;
Fifo8xWidthRows_updn_cntr \\gsym_dc.dc
(.DI(DI),
.I4(I4),
.O1(O1),
.Q(Q),
.S(S),
.clk(clk));
endmodule
(* ORIG_REF_NAME = "dmem" *)
module Fifo8xWidthRows_dmem
(dout,
clk,
din,
I1,
O4,
Q,
I2,
I3,
I4,
I5,
I6,
I7,
I8,
I9,
I10,
I11,
I12,
I13,
I14,
I15,
I16,
I17,
I18,
I19,
I20,
I21,
I22,
I23,
I24,
I25,
I26,
I27,
I28,
I29,
I30,
I31,
I32,
E,
I33);
output [7:0]dout;
input clk;
input [7:0]din;
input I1;
input [8:0]O4;
input [5:0]Q;
input I2;
input I3;
input I4;
input I5;
input I6;
input I7;
input I8;
input I9;
input I10;
input I11;
input I12;
input I13;
input I14;
input I15;
input I16;
input I17;
input I18;
input I19;
input I20;
input I21;
input I22;
input I23;
input I24;
input I25;
input I26;
input I27;
input I28;
input I29;
input I30;
input I31;
input I32;
input [0:0]E;
input [0:0]I33;
wire [0:0]E;
wire I1;
wire I10;
wire I11;
wire I12;
wire I13;
wire I14;
wire I15;
wire I16;
wire I17;
wire I18;
wire I19;
wire I2;
wire I20;
wire I21;
wire I22;
wire I23;
wire I24;
wire I25;
wire I26;
wire I27;
wire I28;
wire I29;
wire I3;
wire I30;
wire I31;
wire I32;
wire [0:0]I33;
wire I4;
wire I5;
wire I6;
wire I7;
wire I8;
wire I9;
wire [8:0]O4;
wire [5:0]Q;
wire clk;
wire [7:0]din;
wire [7:0]dout;
wire n_0_RAM_reg_0_63_0_2;
wire n_0_RAM_reg_0_63_3_5;
wire n_0_RAM_reg_0_63_6_6;
wire n_0_RAM_reg_0_63_7_7;
wire n_0_RAM_reg_128_191_0_2;
wire n_0_RAM_reg_128_191_3_5;
wire n_0_RAM_reg_128_191_6_6;
wire n_0_RAM_reg_128_191_7_7;
wire n_0_RAM_reg_192_255_0_2;
wire n_0_RAM_reg_192_255_3_5;
wire n_0_RAM_reg_192_255_6_6;
wire n_0_RAM_reg_192_255_7_7;
wire n_0_RAM_reg_256_319_0_2;
wire n_0_RAM_reg_256_319_3_5;
wire n_0_RAM_reg_256_319_6_6;
wire n_0_RAM_reg_256_319_7_7;
wire n_0_RAM_reg_320_383_0_2;
wire n_0_RAM_reg_320_383_3_5;
wire n_0_RAM_reg_320_383_6_6;
wire n_0_RAM_reg_320_383_7_7;
wire n_0_RAM_reg_384_447_0_2;
wire n_0_RAM_reg_384_447_3_5;
wire n_0_RAM_reg_384_447_6_6;
wire n_0_RAM_reg_384_447_7_7;
wire n_0_RAM_reg_448_511_0_2;
wire n_0_RAM_reg_448_511_3_5;
wire n_0_RAM_reg_448_511_6_6;
wire n_0_RAM_reg_448_511_7_7;
wire n_0_RAM_reg_64_127_0_2;
wire n_0_RAM_reg_64_127_3_5;
wire n_0_RAM_reg_64_127_6_6;
wire n_0_RAM_reg_64_127_7_7;
wire \
_0_gpr1.dout_i[0]_i_2 ;
wire \
_0_gpr1.dout_i[0]_i_3 ;
wire \
_0_gpr1.dout_i[1]_i_2 ;
wire \
_0_gpr1.dout_i[1]_i_3 ;
wire \
_0_gpr1.dout_i[2]_i_2 ;
wire \
_0_gpr1.dout_i[2]_i_3 ;
wire \
_0_gpr1.dout_i[3]_i_2 ;
wire \
_0_gpr1.dout_i[3]_i_3 ;
wire \
_0_gpr1.dout_i[4]_i_2 ;
wire \
_0_gpr1.dout_i[4]_i_3 ;
wire \
_0_gpr1.dout_i[5]_i_2 ;
wire \
_0_gpr1.dout_i[5]_i_3 ;
wire \
_0_gpr1.dout_i[6]_i_2 ;
wire \
_0_gpr1.dout_i[6]_i_3 ;
wire \
_0_gpr1.dout_i[7]_i_3 ;
wire \
_0_gpr1.dout_i[7]_i_4 ;
wire n_1_RAM_reg_0_63_0_2;
wire n_1_RAM_reg_0_63_3_5;
wire n_1_RAM_reg_128_191_0_2;
wire n_1_RAM_reg_128_191_3_5;
wire n_1_RAM_reg_192_255_0_2;
wire n_1_RAM_reg_192_255_3_5;
wire n_1_RAM_reg_256_319_0_2;
wire n_1_RAM_reg_256_319_3_5;
wire n_1_RAM_reg_320_383_0_2;
wire n_1_RAM_reg_320_383_3_5;
wire n_1_RAM_reg_384_447_0_2;
wire n_1_RAM_reg_384_447_3_5;
wire n_1_RAM_reg_448_511_0_2;
wire n_1_RAM_reg_448_511_3_5;
wire n_1_RAM_reg_64_127_0_2;
wire n_1_RAM_reg_64_127_3_5;
wire n_2_RAM_reg_0_63_0_2;
wire n_2_RAM_reg_0_63_3_5;
wire n_2_RAM_reg_128_191_0_2;
wire n_2_RAM_reg_128_191_3_5;
wire n_2_RAM_reg_192_255_0_2;
wire n_2_RAM_reg_192_255_3_5;
wire n_2_RAM_reg_256_319_0_2;
wire n_2_RAM_reg_256_319_3_5;
wire n_2_RAM_reg_320_383_0_2;
wire n_2_RAM_reg_320_383_3_5;
wire n_2_RAM_reg_384_447_0_2;
wire n_2_RAM_reg_384_447_3_5;
wire n_2_RAM_reg_448_511_0_2;
wire n_2_RAM_reg_448_511_3_5;
wire n_2_RAM_reg_64_127_0_2;
wire n_2_RAM_reg_64_127_3_5;
wire [7:0]p_0_out;
wire NLW_RAM_reg_0_63_0_2_DOD_UNCONNECTED;
wire NLW_RAM_reg_0_63_3_5_DOD_UNCONNECTED;
wire NLW_RAM_reg_0_63_6_6_SPO_UNCONNECTED;
wire NLW_RAM_reg_0_63_7_7_SPO_UNCONNECTED;
wire NLW_RAM_reg_128_191_0_2_DOD_UNCONNECTED;
wire NLW_RAM_reg_128_191_3_5_DOD_UNCONNECTED;
wire NLW_RAM_reg_128_191_6_6_SPO_UNCONNECTED;
wire NLW_RAM_reg_128_191_7_7_SPO_UNCONNECTED;
wire NLW_RAM_reg_192_255_0_2_DOD_UNCONNECTED;
wire NLW_RAM_reg_192_255_3_5_DOD_UNCONNECTED;
wire NLW_RAM_reg_192_255_6_6_SPO_UNCONNECTED;
wire NLW_RAM_reg_192_255_7_7_SPO_UNCONNECTED;
wire NLW_RAM_reg_256_319_0_2_DOD_UNCONNECTED;
wire NLW_RAM_reg_256_319_3_5_DOD_UNCONNECTED;
wire NLW_RAM_reg_256_319_6_6_SPO_UNCONNECTED;
wire NLW_RAM_reg_256_319_7_7_SPO_UNCONNECTED;
wire NLW_RAM_reg_320_383_0_2_DOD_UNCONNECTED;
wire NLW_RAM_reg_320_383_3_5_DOD_UNCONNECTED;
wire NLW_RAM_reg_320_383_6_6_SPO_UNCONNECTED;
wire NLW_RAM_reg_320_383_7_7_SPO_UNCONNECTED;
wire NLW_RAM_reg_384_447_0_2_DOD_UNCONNECTED;
wire NLW_RAM_reg_384_447_3_5_DOD_UNCONNECTED;
wire NLW_RAM_reg_384_447_6_6_SPO_UNCONNECTED;
wire NLW_RAM_reg_384_447_7_7_SPO_UNCONNECTED;
wire NLW_RAM_reg_448_511_0_2_DOD_UNCONNECTED;
wire NLW_RAM_reg_448_511_3_5_DOD_UNCONNECTED;
wire NLW_RAM_reg_448_511_6_6_SPO_UNCONNECTED;
wire NLW_RAM_reg_448_511_7_7_SPO_UNCONNECTED;
wire NLW_RAM_reg_64_127_0_2_DOD_UNCONNECTED;
wire NLW_RAM_reg_64_127_3_5_DOD_UNCONNECTED;
wire NLW_RAM_reg_64_127_6_6_SPO_UNCONNECTED;
wire NLW_RAM_reg_64_127_7_7_SPO_UNCONNECTED;
RAM64M RAM_reg_0_63_0_2
(.ADDRA(O4[5:0]),
.ADDRB(O4[5:0]),
.ADDRC(O4[5:0]),
.ADDRD(Q),
.DIA(din[0]),
.DIB(din[1]),
.DIC(din[2]),
.DID(1\'b0),
.DOA(n_0_RAM_reg_0_63_0_2),
.DOB(n_1_RAM_reg_0_63_0_2),
.DOC(n_2_RAM_reg_0_63_0_2),
.DOD(NLW_RAM_reg_0_63_0_2_DOD_UNCONNECTED),
.WCLK(clk),
.WE(I1));
RAM64M RAM_reg_0_63_3_5
(.ADDRA(O4[5:0]),
.ADDRB(O4[5:0]),
.ADDRC(O4[5:0]),
.ADDRD(Q),
.DIA(din[3]),
.DIB(din[4]),
.DIC(din[5]),
.DID(1\'b0),
.DOA(n_0_RAM_reg_0_63_3_5),
.DOB(n_1_RAM_reg_0_63_3_5),
.DOC(n_2_RAM_reg_0_63_3_5),
.DOD(NLW_RAM_reg_0_63_3_5_DOD_UNCONNECTED),
.WCLK(clk),
.WE(I9));
RAM64X1D RAM_reg_0_63_6_6
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.A4(Q[4]),
.A5(Q[5]),
.D(din[6]),
.DPO(n_0_RAM_reg_0_63_6_6),
.DPRA0(O4[0]),
.DPRA1(O4[1]),
.DPRA2(O4[2]),
.DPRA3(O4[3]),
.DPRA4(O4[4]),
.DPRA5(O4[5]),
.SPO(NLW_RAM_reg_0_63_6_6_SPO_UNCONNECTED),
.WCLK(clk),
.WE(I17));
RAM64X1D RAM_reg_0_63_7_7
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.A4(Q[4]),
.A5(Q[5]),
.D(din[7]),
.DPO(n_0_RAM_reg_0_63_7_7),
.DPRA0(O4[0]),
.DPRA1(O4[1]),
.DPRA2(O4[2]),
.DPRA3(O4[3]),
.DPRA4(O4[4]),
.DPRA5(O4[5]),
.SPO(NLW_RAM_reg_0_63_7_7_SPO_UNCONNECTED),
.WCLK(clk),
.WE(I18));
RAM64M RAM_reg_128_191_0_2
(.ADDRA(O4[5:0]),
.ADDRB(O4[5:0]),
.ADDRC(O4[5:0]),
.ADDRD(Q),
.DIA(din[0]),
.DIB(din[1]),
.DIC(din[2]),
.DID(1\'b0),
.DOA(n_0_RAM_reg_128_191_0_2),
.DOB(n_1_RAM_reg_128_191_0_2),
.DOC(n_2_RAM_reg_128_191_0_2),
.DOD(NLW_RAM_reg_128_191_0_2_DOD_UNCONNECTED),
.WCLK(clk),
.WE(I3));
RAM64M RAM_reg_128_191_3_5
(.ADDRA(O4[5:0]),
.ADDRB(O4[5:0]),
.ADDRC(O4[5:0]),
.ADDRD(Q),
.DIA(din[3]),
.DIB(din[4]),
.DIC(din[5]),
.DID(1\'b0),
.DOA(n_0_RAM_reg_128_191_3_5),
.DOB(n_1_RAM_reg_128_191_3_5),
.DOC(n_2_RAM_reg_128_191_3_5),
.DOD(NLW_RAM_reg_128_191_3_5_DOD_UNCONNECTED),
.WCLK(clk),
.WE(I11));
RAM64X1D RAM_reg_128_191_6_6
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.A4(Q[4]),
.A5(Q[5]),
.D(din[6]),
.DPO(n_0_RAM_reg_128_191_6_6),
.DPRA0(O4[0]),
.DPRA1(O4[1]),
.DPRA2(O4[2]),
.DPRA3(O4[3]),
.DPRA4(O4[4]),
.DPRA5(O4[5]),
.SPO(NLW_RAM_reg_128_191_6_6_SPO_UNCONNECTED),
.WCLK(clk),
.WE(I21));
RAM64X1D RAM_reg_128_191_7_7
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.A4(Q[4]),
.A5(Q[5]),
.D(din[7]),
.DPO(n_0_RAM_reg_128_191_7_7),
.DPRA0(O4[0]),
.DPRA1(O4[1]),
.DPRA2(O4[2]),
.DPRA3(O4[3]),
.DPRA4(O4[4]),
.DPRA5(O4[5]),
.SPO(NLW_RAM_reg_128_191_7_7_SPO_UNCONNECTED),
.WCLK(clk),
.WE(I22));
RAM64M RAM_reg_192_255_0_2
(.ADDRA(O4[5:0]),
.ADDRB(O4[5:0]),
.ADDRC(O4[5:0]),
.ADDRD(Q),
.DIA(din[0]),
.DIB(din[1]),
.DIC(din[2]),
.DID(1\'b0),
.DOA(n_0_RAM_reg_192_255_0_2),
.DOB(n_1_RAM_reg_192_255_0_2),
.DOC(n_2_RAM_reg_192_255_0_2),
.DOD(NLW_RAM_reg_192_255_0_2_DOD_UNCONNECTED),
.WCLK(clk),
.WE(I4));
RAM64M RAM_reg_192_255_3_5
(.ADDRA(O4[5:0]),
.ADDRB(O4[5:0]),
.ADDRC(O4[5:0]),
.ADDRD(Q),
.DIA(din[3]),
.DIB(din[4]),
.DIC(din[5]),
.DID(1\'b0),
.DOA(n_0_RAM_reg_192_255_3_5),
.DOB(n_1_RAM_reg_192_255_3_5),
.DOC(n_2_RAM_reg_192_255_3_5),
.DOD(NLW_RAM_reg_192_255_3_5_DOD_UNCONNECTED),
.WCLK(clk),
.WE(I12));
RAM64X1D RAM_reg_192_255_6_6
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.A4(Q[4]),
.A5(Q[5]),
.D(din[6]),
.DPO(n_0_RAM_reg_192_255_6_6),
.DPRA0(O4[0]),
.DPRA1(O4[1]),
.DPRA2(O4[2]),
.DPRA3(O4[3]),
.DPRA4(O4[4]),
.DPRA5(O4[5]),
.SPO(NLW_RAM_reg_192_255_6_6_SPO_UNCONNECTED),
.WCLK(clk),
.WE(I23));
RAM64X1D RAM_reg_192_255_7_7
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.A4(Q[4]),
.A5(Q[5]),
.D(din[7]),
.DPO(n_0_RAM_reg_192_255_7_7),
.DPRA0(O4[0]),
.DPRA1(O4[1]),
.DPRA2(O4[2]),
.DPRA3(O4[3]),
.DPRA4(O4[4]),
.DPRA5(O4[5]),
.SPO(NLW_RAM_reg_192_255_7_7_SPO_UNCONNECTED),
.WCLK(clk),
.WE(I24));
RAM64M RAM_reg_256_319_0_2
(.ADDRA(O4[5:0]),
.ADDRB(O4[5:0]),
.ADDRC(O4[5:0]),
.ADDRD(Q),
.DIA(din[0]),
.DIB(din[1]),
.DIC(din[2]),
.DID(1\'b0),
.DOA(n_0_RAM_reg_256_319_0_2),
.DOB(n_1_RAM_reg_256_319_0_2),
.DOC(n_2_RAM_reg_256_319_0_2),
.DOD(NLW_RAM_reg_256_319_0_2_DOD_UNCONNECTED),
.WCLK(clk),
.WE(I5));
RAM64M RAM_reg_256_319_3_5
(.ADDRA(O4[5:0]),
.ADDRB(O4[5:0]),
.ADDRC(O4[5:0]),
.ADDRD(Q),
.DIA(din[3]),
.DIB(din[4]),
.DIC(din[5]),
.DID(1\'b0),
.DOA(n_0_RAM_reg_256_319_3_5),
.DOB(n_1_RAM_reg_256_319_3_5),
.DOC(n_2_RAM_reg_256_319_3_5),
.DOD(NLW_RAM_reg_256_319_3_5_DOD_UNCONNECTED),
.WCLK(clk),
.WE(I13));
RAM64X1D RAM_reg_256_319_6_6
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.A4(Q[4]),
.A5(Q[5]),
.D(din[6]),
.DPO(n_0_RAM_reg_256_319_6_6),
.DPRA0(O4[0]),
.DPRA1(O4[1]),
.DPRA2(O4[2]),
.DPRA3(O4[3]),
.DPRA4(O4[4]),
.DPRA5(O4[5]),
.SPO(NLW_RAM_reg_256_319_6_6_SPO_UNCONNECTED),
.WCLK(clk),
.WE(I25));
RAM64X1D RAM_reg_256_319_7_7
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.A4(Q[4]),
.A5(Q[5]),
.D(din[7]),
.DPO(n_0_RAM_reg_256_319_7_7),
.DPRA0(O4[0]),
.DPRA1(O4[1]),
.DPRA2(O4[2]),
.DPRA3(O4[3]),
.DPRA4(O4[4]),
.DPRA5(O4[5]),
.SPO(NLW_RAM_reg_256_319_7_7_SPO_UNCONNECTED),
.WCLK(clk),
.WE(I26));
RAM64M RAM_reg_320_383_0_2
(.ADDRA(O4[5:0]),
.ADDRB(O4[5:0]),
.ADDRC(O4[5:0]),
.ADDRD(Q),
.DIA(din[0]),
.DIB(din[1]),
.DIC(din[2]),
.DID(1\'b0),
.DOA(n_0_RAM_reg_320_383_0_2),
.DOB(n_1_RAM_reg_320_383_0_2),
.DOC(n_2_RAM_reg_320_383_0_2),
.DOD(NLW_RAM_reg_320_383_0_2_DOD_UNCONNECTED),
.WCLK(clk),
.WE(I6));
RAM64M RAM_reg_320_383_3_5
(.ADDRA(O4[5:0]),
.ADDRB(O4[5:0]),
.ADDRC(O4[5:0]),
.ADDRD(Q),
.DIA(din[3]),
.DIB(din[4]),
.DIC(din[5]),
.DID(1\'b0),
.DOA(n_0_RAM_reg_320_383_3_5),
.DOB(n_1_RAM_reg_320_383_3_5),
.DOC(n_2_RAM_reg_320_383_3_5),
.DOD(NLW_RAM_reg_320_383_3_5_DOD_UNCONNECTED),
.WCLK(clk),
.WE(I14));
RAM64X1D RAM_reg_320_383_6_6
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.A4(Q[4]),
.A5(Q[5]),
.D(din[6]),
.DPO(n_0_RAM_reg_320_383_6_6),
.DPRA0(O4[0]),
.DPRA1(O4[1]),
.DPRA2(O4[2]),
.DPRA3(O4[3]),
.DPRA4(O4[4]),
.DPRA5(O4[5]),
.SPO(NLW_RAM_reg_320_383_6_6_SPO_UNCONNECTED),
.WCLK(clk),
.WE(I27));
RAM64X1D RAM_reg_320_383_7_7
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.A4(Q[4]),
.A5(Q[5]),
.D(din[7]),
.DPO(n_0_RAM_reg_320_383_7_7),
.DPRA0(O4[0]),
.DPRA1(O4[1]),
.DPRA2(O4[2]),
.DPRA3(O4[3]),
.DPRA4(O4[4]),
.DPRA5(O4[5]),
.SPO(NLW_RAM_reg_320_383_7_7_SPO_UNCONNECTED),
.WCLK(clk),
.WE(I28));
RAM64M RAM_reg_384_447_0_2
(.ADDRA(O4[5:0]),
.ADDRB(O4[5:0]),
.ADDRC(O4[5:0]),
.ADDRD(Q),
.DIA(din[0]),
.DIB(din[1]),
.DIC(din[2]),
.DID(1\'b0),
.DOA(n_0_RAM_reg_384_447_0_2),
.DOB(n_1_RAM_reg_384_447_0_2),
.DOC(n_2_RAM_reg_384_447_0_2),
.DOD(NLW_RAM_reg_384_447_0_2_DOD_UNCONNECTED),
.WCLK(clk),
.WE(I7));
RAM64M RAM_reg_384_447_3_5
(.ADDRA(O4[5:0]),
.ADDRB(O4[5:0]),
.ADDRC(O4[5:0]),
.ADDRD(Q),
.DIA(din[3]),
.DIB(din[4]),
.DIC(din[5]),
.DID(1\'b0),
.DOA(n_0_RAM_reg_384_447_3_5),
.DOB(n_1_RAM_reg_384_447_3_5),
.DOC(n_2_RAM_reg_384_447_3_5),
.DOD(NLW_RAM_reg_384_447_3_5_DOD_UNCONNECTED),
.WCLK(clk),
.WE(I15));
RAM64X1D RAM_reg_384_447_6_6
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.A4(Q[4]),
.A5(Q[5]),
.D(din[6]),
.DPO(n_0_RAM_reg_384_447_6_6),
.DPRA0(O4[0]),
.DPRA1(O4[1]),
.DPRA2(O4[2]),
.DPRA3(O4[3]),
.DPRA4(O4[4]),
.DPRA5(O4[5]),
.SPO(NLW_RAM_reg_384_447_6_6_SPO_UNCONNECTED),
.WCLK(clk),
.WE(I29));
RAM64X1D RAM_reg_384_447_7_7
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.A4(Q[4]),
.A5(Q[5]),
.D(din[7]),
.DPO(n_0_RAM_reg_384_447_7_7),
.DPRA0(O4[0]),
.DPRA1(O4[1]),
.DPRA2(O4[2]),
.DPRA3(O4[3]),
.DPRA4(O4[4]),
.DPRA5(O4[5]),
.SPO(NLW_RAM_reg_384_447_7_7_SPO_UNCONNECTED),
.WCLK(clk),
.WE(I30));
RAM64M RAM_reg_448_511_0_2
(.ADDRA(O4[5:0]),
.ADDRB(O4[5:0]),
.ADDRC(O4[5:0]),
.ADDRD(Q),
.DIA(din[0]),
.DIB(din[1]),
.DIC(din[2]),
.DID(1\'b0),
.DOA(n_0_RAM_reg_448_511_0_2),
.DOB(n_1_RAM_reg_448_511_0_2),
.DOC(n_2_RAM_reg_448_511_0_2),
.DOD(NLW_RAM_reg_448_511_0_2_DOD_UNCONNECTED),
.WCLK(clk),
.WE(I8));
RAM64M RAM_reg_448_511_3_5
(.ADDRA(O4[5:0]),
.ADDRB(O4[5:0]),
.ADDRC(O4[5:0]),
.ADDRD(Q),
.DIA(din[3]),
.DIB(din[4]),
.DIC(din[5]),
.DID(1\'b0),
.DOA(n_0_RAM_reg_448_511_3_5),
.DOB(n_1_RAM_reg_448_511_3_5),
.DOC(n_2_RAM_reg_448_511_3_5),
.DOD(NLW_RAM_reg_448_511_3_5_DOD_UNCONNECTED),
.WCLK(clk),
.WE(I16));
RAM64X1D RAM_reg_448_511_6_6
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.A4(Q[4]),
.A5(Q[5]),
.D(din[6]),
.DPO(n_0_RAM_reg_448_511_6_6),
.DPRA0(O4[0]),
.DPRA1(O4[1]),
.DPRA2(O4[2]),
.DPRA3(O4[3]),
.DPRA4(O4[4]),
.DPRA5(O4[5]),
.SPO(NLW_RAM_reg_448_511_6_6_SPO_UNCONNECTED),
.WCLK(clk),
.WE(I31));
RAM64X1D RAM_reg_448_511_7_7
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.A4(Q[4]),
.A5(Q[5]),
.D(din[7]),
.DPO(n_0_RAM_reg_448_511_7_7),
.DPRA0(O4[0]),
.DPRA1(O4[1]),
.DPRA2(O4[2]),
.DPRA3(O4[3]),
.DPRA4(O4[4]),
.DPRA5(O4[5]),
.SPO(NLW_RAM_reg_448_511_7_7_SPO_UNCONNECTED),
.WCLK(clk),
.WE(I32));
RAM64M RAM_reg_64_127_0_2
(.ADDRA(O4[5:0]),
.ADDRB(O4[5:0]),
.ADDRC(O4[5:0]),
.ADDRD(Q),
.DIA(din[0]),
.DIB(din[1]),
.DIC(din[2]),
.DID(1\'b0),
.DOA(n_0_RAM_reg_64_127_0_2),
.DOB(n_1_RAM_reg_64_127_0_2),
.DOC(n_2_RAM_reg_64_127_0_2),
.DOD(NLW_RAM_reg_64_127_0_2_DOD_UNCONNECTED),
.WCLK(clk),
.WE(I2));
RAM64M RAM_reg_64_127_3_5
(.ADDRA(O4[5:0]),
.ADDRB(O4[5:0]),
.ADDRC(O4[5:0]),
.ADDRD(Q),
.DIA(din[3]),
.DIB(din[4]),
.DIC(din[5]),
.DID(1\'b0),
.DOA(n_0_RAM_reg_64_127_3_5),
.DOB(n_1_RAM_reg_64_127_3_5),
.DOC(n_2_RAM_reg_64_127_3_5),
.DOD(NLW_RAM_reg_64_127_3_5_DOD_UNCONNECTED),
.WCLK(clk),
.WE(I10));
RAM64X1D RAM_reg_64_127_6_6
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.A4(Q[4]),
.A5(Q[5]),
.D(din[6]),
.DPO(n_0_RAM_reg_64_127_6_6),
.DPRA0(O4[0]),
.DPRA1(O4[1]),
.DPRA2(O4[2]),
.DPRA3(O4[3]),
.DPRA4(O4[4]),
.DPRA5(O4[5]),
.SPO(NLW_RAM_reg_64_127_6_6_SPO_UNCONNECTED),
.WCLK(clk),
.WE(I19));
RAM64X1D RAM_reg_64_127_7_7
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.A4(Q[4]),
.A5(Q[5]),
.D(din[7]),
.DPO(n_0_RAM_reg_64_127_7_7),
.DPRA0(O4[0]),
.DPRA1(O4[1]),
.DPRA2(O4[2]),
.DPRA3(O4[3]),
.DPRA4(O4[4]),
.DPRA5(O4[5]),
.SPO(NLW_RAM_reg_64_127_7_7_SPO_UNCONNECTED),
.WCLK(clk),
.WE(I20));
LUT6 #(
.INIT(64\'hAFA0CFCFAFA0C0C0))
\\gpr1.dout_i[0]_i_2
(.I0(n_0_RAM_reg_192_255_0_2),
.I1(n_0_RAM_reg_64_127_0_2),
.I2(O4[6]),
.I3(n_0_RAM_reg_128_191_0_2),
.I4(O4[7]),
.I5(n_0_RAM_reg_0_63_0_2),
.O(\
_0_gpr1.dout_i[0]_i_2 ));
LUT6 #(
.INIT(64\'hAFA0CFCFAFA0C0C0))
\\gpr1.dout_i[0]_i_3
(.I0(n_0_RAM_reg_448_511_0_2),
.I1(n_0_RAM_reg_320_383_0_2),
.I2(O4[6]),
.I3(n_0_RAM_reg_384_447_0_2),
.I4(O4[7]),
.I5(n_0_RAM_reg_256_319_0_2),
.O(\
_0_gpr1.dout_i[0]_i_3 ));
LUT6 #(
.INIT(64\'hAFA0CFCFAFA0C0C0))
\\gpr1.dout_i[1]_i_2
(.I0(n_1_RAM_reg_192_255_0_2),
.I1(n_1_RAM_reg_64_127_0_2),
.I2(O4[6]),
.I3(n_1_RAM_reg_128_191_0_2),
.I4(O4[7]),
.I5(n_1_RAM_reg_0_63_0_2),
.O(\
_0_gpr1.dout_i[1]_i_2 ));
LUT6 #(
.INIT(64\'hAFA0CFCFAFA0C0C0))
\\gpr1.dout_i[1]_i_3
(.I0(n_1_RAM_reg_448_511_0_2),
.I1(n_1_RAM_reg_320_383_0_2),
.I2(O4[6]),
.I3(n_1_RAM_reg_384_447_0_2),
.I4(O4[7]),
.I5(n_1_RAM_reg_256_319_0_2),
.O(\
_0_gpr1.dout_i[1]_i_3 ));
LUT6 #(
.INIT(64\'hAFA0CFCFAFA0C0C0))
\\gpr1.dout_i[2]_i_2
(.I0(n_2_RAM_reg_192_255_0_2),
.I1(n_2_RAM_reg_64_127_0_2),
.I2(O4[6]),
.I3(n_2_RAM_reg_128_191_0_2),
.I4(O4[7]),
.I5(n_2_RAM_reg_0_63_0_2),
.O(\
_0_gpr1.dout_i[2]_i_2 ));
LUT6 #(
.INIT(64\'hAFA0CFCFAFA0C0C0))
\\gpr1.dout_i[2]_i_3
(.I0(n_2_RAM_reg_448_511_0_2),
.I1(n_2_RAM_reg_320_383_0_2),
.I2(O4[6]),
.I3(n_2_RAM_reg_384_447_0_2),
.I4(O4[7]),
.I5(n_2_RAM_reg_256_319_0_2),
.O(\
_0_gpr1.dout_i[2]_i_3 ));
LUT6 #(
.INIT(64\'hAFA0CFCFAFA0C0C0))
\\gpr1.dout_i[3]_i_2
(.I0(n_0_RAM_reg_192_255_3_5),
.I1(n_0_RAM_reg_64_127_3_5),
.I2(O4[6]),
.I3(n_0_RAM_reg_128_191_3_5),
.I4(O4[7]),
.I5(n_0_RAM_reg_0_63_3_5),
.O(\
_0_gpr1.dout_i[3]_i_2 ));
LUT6 #(
.INIT(64\'hAFA0CFCFAFA0C0C0))
\\gpr1.dout_i[3]_i_3
(.I0(n_0_RAM_reg_448_511_3_5),
.I1(n_0_RAM_reg_320_383_3_5),
.I2(O4[6]),
.I3(n_0_RAM_reg_384_447_3_5),
.I4(O4[7]),
.I5(n_0_RAM_reg_256_319_3_5),
.O(\
_0_gpr1.dout_i[3]_i_3 ));
LUT6 #(
.INIT(64\'hAFA0CFCFAFA0C0C0))
\\gpr1.dout_i[4]_i_2
(.I0(n_1_RAM_reg_192_255_3_5),
.I1(n_1_RAM_reg_64_127_3_5),
.I2(O4[6]),
.I3(n_1_RAM_reg_128_191_3_5),
.I4(O4[7]),
.I5(n_1_RAM_reg_0_63_3_5),
.O(\
_0_gpr1.dout_i[4]_i_2 ));
LUT6 #(
.INIT(64\'hAFA0CFCFAFA0C0C0))
\\gpr1.dout_i[4]_i_3
(.I0(n_1_RAM_reg_448_511_3_5),
.I1(n_1_RAM_reg_320_383_3_5),
.I2(O4[6]),
.I3(n_1_RAM_reg_384_447_3_5),
.I4(O4[7]),
.I5(n_1_RAM_reg_256_319_3_5),
.O(\
_0_gpr1.dout_i[4]_i_3 ));
LUT6 #(
.INIT(64\'hAFA0CFCFAFA0C0C0))
\\gpr1.dout_i[5]_i_2
(.I0(n_2_RAM_reg_192_255_3_5),
.I1(n_2_RAM_reg_64_127_3_5),
.I2(O4[6]),
.I3(n_2_RAM_reg_128_191_3_5),
.I4(O4[7]),
.I5(n_2_RAM_reg_0_63_3_5),
.O(\
_0_gpr1.dout_i[5]_i_2 ));
LUT6 #(
.INIT(64\'hAFA0CFCFAFA0C0C0))
\\gpr1.dout_i[5]_i_3
(.I0(n_2_RAM_reg_448_511_3_5),
.I1(n_2_RAM_reg_320_383_3_5),
.I2(O4[6]),
.I3(n_2_RAM_reg_384_447_3_5),
.I4(O4[7]),
.I5(n_2_RAM_reg_256_319_3_5),
.O(\
_0_gpr1.dout_i[5]_i_3 ));
LUT6 #(
.INIT(64\'hAFA0CFCFAFA0C0C0))
\\gpr1.dout_i[6]_i_2
(.I0(n_0_RAM_reg_192_255_6_6),
.I1(n_0_RAM_reg_64_127_6_6),
.I2(O4[6]),
.I3(n_0_RAM_reg_128_191_6_6),
.I4(O4[7]),
.I5(n_0_RAM_reg_0_63_6_6),
.O(\
_0_gpr1.dout_i[6]_i_2 ));
LUT6 #(
.INIT(64\'hAFA0CFCFAFA0C0C0))
\\gpr1.dout_i[6]_i_3
(.I0(n_0_RAM_reg_448_511_6_6),
.I1(n_0_RAM_reg_320_383_6_6),
.I2(O4[6]),
.I3(n_0_RAM_reg_384_447_6_6),
.I4(O4[7]),
.I5(n_0_RAM_reg_256_319_6_6),
.O(\
_0_gpr1.dout_i[6]_i_3 ));
LUT6 #(
.INIT(64\'hAFA0CFCFAFA0C0C0))
\\gpr1.dout_i[7]_i_3
(.I0(n_0_RAM_reg_192_255_7_7),
.I1(n_0_RAM_reg_64_127_7_7),
.I2(O4[6]),
.I3(n_0_RAM_reg_128_191_7_7),
.I4(O4[7]),
.I5(n_0_RAM_reg_0_63_7_7),
.O(\
_0_gpr1.dout_i[7]_i_3 ));
LUT6 #(
.INIT(64\'hAFA0CFCFAFA0C0C0))
\\gpr1.dout_i[7]_i_4
(.I0(n_0_RAM_reg_448_511_7_7),
.I1(n_0_RAM_reg_320_383_7_7),
.I2(O4[6]),
.I3(n_0_RAM_reg_384_447_7_7),
.I4(O4[7]),
.I5(n_0_RAM_reg_256_319_7_7),
.O(\
_0_gpr1.dout_i[7]_i_4 ));
FDCE #(
.INIT(1\'b0))
\\gpr1.dout_i_reg[0]
(.C(clk),
.CE(E),
.CLR(I33),
.D(p_0_out[0]),
.Q(dout[0]));
MUXF7 \\gpr1.dout_i_reg[0]_i_1
(.I0(\
_0_gpr1.dout_i[0]_i_2 ),
.I1(\
_0_gpr1.dout_i[0]_i_3 ),
.O(p_0_out[0]),
.S(O4[8]));
FDCE #(
.INIT(1\'b0))
\\gpr1.dout_i_reg[1]
(.C(clk),
.CE(E),
.CLR(I33),
.D(p_0_out[1]),
.Q(dout[1]));
MUXF7 \\gpr1.dout_i_reg[1]_i_1
(.I0(\
_0_gpr1.dout_i[1]_i_2 ),
.I1(\
_0_gpr1.dout_i[1]_i_3 ),
.O(p_0_out[1]),
.S(O4[8]));
FDCE #(
.INIT(1\'b0))
\\gpr1.dout_i_reg[2]
(.C(clk),
.CE(E),
.CLR(I33),
.D(p_0_out[2]),
.Q(dout[2]));
MUXF7 \\gpr1.dout_i_reg[2]_i_1
(.I0(\
_0_gpr1.dout_i[2]_i_2 ),
.I1(\
_0_gpr1.dout_i[2]_i_3 ),
.O(p_0_out[2]),
.S(O4[8]));
FDCE #(
.INIT(1\'b0))
\\gpr1.dout_i_reg[3]
(.C(clk),
.CE(E),
.CLR(I33),
.D(p_0_out[3]),
.Q(dout[3]));
MUXF7 \\gpr1.dout_i_reg[3]_i_1
(.I0(\
_0_gpr1.dout_i[3]_i_2 ),
.I1(\
_0_gpr1.dout_i[3]_i_3 ),
.O(p_0_out[3]),
.S(O4[8]));
FDCE #(
.INIT(1\'b0))
\\gpr1.dout_i_reg[4]
(.C(clk),
.CE(E),
.CLR(I33),
.D(p_0_out[4]),
.Q(dout[4]));
MUXF7 \\gpr1.dout_i_reg[4]_i_1
(.I0(\
_0_gpr1.dout_i[4]_i_2 ),
.I1(\
_0_gpr1.dout_i[4]_i_3 ),
.O(p_0_out[4]),
.S(O4[8]));
FDCE #(
.INIT(1\'b0))
\\gpr1.dout_i_reg[5]
(.C(clk),
.CE(E),
.CLR(I33),
.D(p_0_out[5]),
.Q(dout[5]));
MUXF7 \\gpr1.dout_i_reg[5]_i_1
(.I0(\
_0_gpr1.dout_i[5]_i_2 ),
.I1(\
_0_gpr1.dout_i[5]_i_3 ),
.O(p_0_out[5]),
.S(O4[8]));
FDCE #(
.INIT(1\'b0))
\\gpr1.dout_i_reg[6]
(.C(clk),
.CE(E),
.CLR(I33),
.D(p_0_out[6]),
.Q(dout[6]));
MUXF7 \\gpr1.dout_i_reg[6]_i_1
(.I0(\
_0_gpr1.dout_i[6]_i_2 ),
.I1(\
_0_gpr1.dout_i[6]_i_3 ),
.O(p_0_out[6]),
.S(O4[8]));
FDCE #(
.INIT(1\'b0))
\\gpr1.dout_i_reg[7]
(.C(clk),
.CE(E),
.CLR(I33),
.D(p_0_out[7]),
.Q(dout[7]));
MUXF7 \\gpr1.dout_i_reg[7]_i_2
(.I0(\
_0_gpr1.dout_i[7]_i_3 ),
.I1(\
_0_gpr1.dout_i[7]_i_4 ),
.O(p_0_out[7]),
.S(O4[8]));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module Fifo8xWidthRows_fifo_generator_ramfifo
(data_count,
dout,
empty,
full,
rd_en,
clk,
rst,
din,
wr_en);
output [8:0]data_count;
output [7:0]dout;
output empty;
output full;
input rd_en;
input clk;
input rst;
input [7:0]din;
input wr_en;
wire RST;
wire clear;
wire clk;
wire [8:0]data_count;
wire [7:0]din;
wire [7:0]dout;
wire empty;
wire full;
wire \\grss.gdc.dc/cntr_en ;
wire [3:0]\\grss.rsts/c2/v1_reg ;
wire [3:0]\\gwss.wsts/c0/v1_reg ;
wire [3:0]\\gwss.wsts/c1/v1_reg ;
wire \
_11_gntv_or_sync_fifo.gl0.wr ;
wire \
_20_gntv_or_sync_fifo.gl0.wr ;
wire \
_21_gntv_or_sync_fifo.gl0.wr ;
wire \
_22_gntv_or_sync_fifo.gl0.wr ;
wire \
_23_gntv_or_sync_fifo.gl0.wr ;
wire \
_24_gntv_or_sync_fifo.gl0.wr ;
wire \
_25_gntv_or_sync_fifo.gl0.wr ;
wire \
_26_gntv_or_sync_fifo.gl0.wr ;
wire \
_27_gntv_or_sync_fifo.gl0.wr ;
wire \
_28_gntv_or_sync_fifo.gl0.wr ;
wire \
_29_gntv_or_sync_fifo.gl0.wr ;
wire \
_30_gntv_or_sync_fifo.gl0.wr ;
wire \
_31_gntv_or_sync_fifo.gl0.wr ;
wire \
_32_gntv_or_sync_fifo.gl0.wr ;
wire \
_33_gntv_or_sync_fifo.gl0.wr ;
wire \
_34_gntv_or_sync_fifo.gl0.wr ;
wire \
_35_gntv_or_sync_fifo.gl0.wr ;
wire \
_36_gntv_or_sync_fifo.gl0.wr ;
wire \
_37_gntv_or_sync_fifo.gl0.wr ;
wire \
_38_gntv_or_sync_fifo.gl0.wr ;
wire \
_39_gntv_or_sync_fifo.gl0.wr ;
wire \
_40_gntv_or_sync_fifo.gl0.wr ;
wire \
_41_gntv_or_sync_fifo.gl0.wr ;
wire \
_42_gntv_or_sync_fifo.gl0.wr ;
wire \
_43_gntv_or_sync_fifo.gl0.wr ;
wire \
_44_gntv_or_sync_fifo.gl0.wr ;
wire \
_45_gntv_or_sync_fifo.gl0.wr ;
wire \
_46_gntv_or_sync_fifo.gl0.wr ;
wire \
_47_gntv_or_sync_fifo.gl0.wr ;
wire \
_48_gntv_or_sync_fifo.gl0.wr ;
wire \
_4'b'9_gntv_or_sync_fifo.gl0.wr ;
wire n_4_rstblk;
wire \
_50_gntv_or_sync_fifo.gl0.wr ;
wire \
_51_gntv_or_sync_fifo.gl0.wr ;
wire [8:0]p_10_out;
wire p_14_out;
wire p_18_out;
wire p_1_out;
wire [8:0]p_20_out;
wire [7:0]p_9_out;
wire ram_rd_en_i;
wire rd_en;
wire [7:0]rd_pntr_plus1;
wire rst;
wire rst_d2;
wire rst_full_gen_i;
wire wr_en;
Fifo8xWidthRows_rd_logic \\gntv_or_sync_fifo.gl0.rd
(.E(p_14_out),
.I1(\
_11_gntv_or_sync_fifo.gl0.wr ),
.I2(p_10_out),
.I3(p_9_out),
.I4(\\grss.gdc.dc/cntr_en ),
.O1(data_count),
.O2(rd_pntr_plus1),
.O3(ram_rd_en_i),
.O4(p_20_out),
.Q(clear),
.clk(clk),
.empty(empty),
.p_18_out(p_18_out),
.p_1_out(p_1_out),
.rd_en(rd_en),
.v1_reg(\\gwss.wsts/c0/v1_reg ),
.v1_reg_0(\\gwss.wsts/c1/v1_reg ),
.v1_reg_1(\\grss.rsts/c2/v1_reg ),
.wr_en(wr_en));
Fifo8xWidthRows_wr_logic \\gntv_or_sync_fifo.gl0.wr
(.AR(RST),
.E(p_14_out),
.I1(rd_pntr_plus1),
.I4(\\grss.gdc.dc/cntr_en ),
.O1(\
_11_gntv_or_sync_fifo.gl0.wr ),
.O10(\
_26_gntv_or_sync_fifo.gl0.wr ),
.O11(\
_27_gntv_or_sync_fifo.gl0.wr ),
.O12(\
_28_gntv_or_sync_fifo.gl0.wr ),
.O13(\
_29_gntv_or_sync_fifo.gl0.wr ),
.O14(\
_30_gntv_or_sync_fifo.gl0.wr ),
.O15(\
_31_gntv_or_sync_fifo.gl0.wr ),
.O16(\
_32_gntv_or_sync_fifo.gl0.wr ),
.O17(\
_33_gntv_or_sync_fifo.gl0.wr ),
.O18(\
_34_gntv_or_sync_fifo.gl0.wr ),
.O19(\
_35_gntv_or_sync_fifo.gl0.wr ),
.O2(p_9_out),
.O20(\
_36_gntv_or_sync_fifo.gl0.wr ),
.O21(\
_37_gntv_or_sync_fifo.gl0.wr ),
.O22(\
_38_gntv_or_sync_fifo.gl0.wr ),
.O23(\
_39_gntv_or_sync_fifo.gl0.wr ),
.O24(\
_40_gntv_or_sync_fifo.gl0.wr ),
.O25(\
_41_gntv_or_sync_fifo.gl0.wr ),
.O26(\
_42_gntv_or_sync_fifo.gl0.wr ),
.O27(\
_43_gntv_or_sync_fifo.gl0.wr ),
.O28(\
_44_gntv_or_sync_fifo.gl0.wr ),
.O29(\
_45_gntv_or_sync_fifo.gl0.wr ),
.O3(\
_20_gntv_or_sync_fifo.gl0.wr ),
.O30(\
_46_gntv_or_sync_fifo.gl0.wr ),
.O31(\
_47_gntv_or_sync_fifo.gl0.wr ),
.O32(\
_48_gntv_or_sync_fifo.gl0.wr ),
.O33(\
_49_gntv_or_sync_fifo.gl0.wr ),
.O34(\
_50_gntv_or_sync_fifo.gl0.wr ),
.O35(\
_51_gntv_or_sync_fifo.gl0.wr ),
.O4(p_20_out[8]),
.O5(\
_21_gntv_or_sync_fifo.gl0.wr ),
.O6(\
_22_gntv_or_sync_fifo.gl0.wr ),
.O7(\
_23_gntv_or_sync_fifo.gl0.wr ),
.O8(\
_24_gntv_or_sync_fifo.gl0.wr ),
.O9(\
_25_gntv_or_sync_fifo.gl0.wr ),
.Q(p_10_out),
.clk(clk),
.full(full),
.p_18_out(p_18_out),
.p_1_out(p_1_out),
.rd_en(rd_en),
.rst_d2(rst_d2),
.rst_full_gen_i(rst_full_gen_i),
.v1_reg(\\grss.rsts/c2/v1_reg ),
.v1_reg_0(\\gwss.wsts/c0/v1_reg ),
.v1_reg_1(\\gwss.wsts/c1/v1_reg ),
.wr_en(wr_en));
Fifo8xWidthRows_memory \\gntv_or_sync_fifo.mem
(.E(ram_rd_en_i),
.I1(\
_35_gntv_or_sync_fifo.gl0.wr ),
.I10(\
_30_gntv_or_sync_fifo.gl0.wr ),
.I11(\
_29_gntv_or_sync_fifo.gl0.wr ),
.I12(\
_28_gntv_or_sync_fifo.gl0.wr ),
.I13(\
_38_gntv_or_sync_fifo.gl0.wr ),
.I14(\
_42_gntv_or_sync_fifo.gl0.wr ),
.I15(\
_46_gntv_or_sync_fifo.gl0.wr ),
.I16(\
_50_gntv_or_sync_fifo.gl0.wr ),
.I17(\
_27_gntv_or_sync_fifo.gl0.wr ),
.I18(\
_26_gntv_or_sync_fifo.gl0.wr ),
.I19(\
_25_gntv_or_sync_fifo.gl0.wr ),
.I2(\
_34_gntv_or_sync_fifo.gl0.wr ),
.I20(\
_24_gntv_or_sync_fifo.gl0.wr ),
.I21(\
_23_gntv_or_sync_fifo.gl0.wr ),
.I22(\
_22_gntv_or_sync_fifo.gl0.wr ),
.I23(\
_21_gntv_or_sync_fifo.gl0.wr ),
.I24(\
_20_gntv_or_sync_fifo.gl0.wr ),
.I25(\
_37_gntv_or_sync_fifo.gl0.wr ),
.I26(\
_36_gntv_or_sync_fifo.gl0.wr ),
.I27(\
_41_gntv_or_sync_fifo.gl0.wr ),
.I28(\
_40_gntv_or_sync_fifo.gl0.wr ),
.I29(\
_45_gntv_or_sync_fifo.gl0.wr ),
.I3(\
_33_gntv_or_sync_fifo.gl0.wr ),
.I30(\
_44_gntv_or_sync_fifo.gl0.wr ),
.I31(\
_49_gntv_or_sync_fifo.gl0.wr ),
.I32(\
_48_gntv_or_sync_fifo.gl0.wr ),
.I33(n_4_rstblk),
.I4(\
_32_gntv_or_sync_fifo.gl0.wr ),
.I5(\
_39_gntv_or_sync_fifo.gl0.wr ),
.I6(\
_43_gntv_or_sync_fifo.gl0.wr ),
.I7(\
_47_gntv_or_sync_fifo.gl0.wr ),
.I8(\
_51_gntv_or_sync_fifo.gl0.wr ),
.I9(\
_31_gntv_or_sync_fifo.gl0.wr ),
.O4(p_20_out),
.Q(p_10_out[5:0]),
.clk(clk),
.din(din),
.dout(dout));
Fifo8xWidthRows_reset_blk_ramfifo rstblk
(.AR(RST),
.Q({clear,n_4_rstblk}),
.clk(clk),
.rst(rst),
.rst_d2(rst_d2),
.rst_full_gen_i(rst_full_gen_i));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module Fifo8xWidthRows_fifo_generator_top
(DATA_COUNT,
dout,
empty,
full,
rd_en,
clk,
rst,
din,
wr_en);
output [8:0]DATA_COUNT;
output [7:0]dout;
output empty;
output full;
input rd_en;
input clk;
input rst;
input [7:0]din;
input wr_en;
wire [8:0]DATA_COUNT;
wire clk;
wire [7:0]din;
wire [7:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire wr_en;
Fifo8xWidthRows_fifo_generator_ramfifo \\grf.rf
(.clk(clk),
.data_count(DATA_COUNT),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.rst(rst),
.wr_en(wr_en));
endmodule
(* ORIG_REF_NAME = "fifo_generator_v12_0" *) (* C_COMMON_CLOCK = "1" *) (* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "9" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "8" *)
(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "8" *) (* C_ENABLE_RLOCS = "0" *)
(* C_FAMILY = "zynq" *) (* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_BACKUP = "0" *) (* C_HAS_DATA_COUNT = "1" *)
(* C_HAS_INT_CLK = "0" *) (* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *)
(* C_HAS_RD_DATA_COUNT = "0" *) (* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *)
(* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "0" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_MEMORY_TYPE = "2" *)
(* C_MIF_FILE_NAME = "BlankString" *) (* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *)
(* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) (* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "510" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "509" *) (* C_PROG_FULL_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "9" *) (* C_RD_DEPTH = "512" *) (* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "9" *) (* C_UNDERFLOW_LOW = "0" *) (* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *) (* C_USE_EMBEDDED_REG = "0" *) (* C_USE_PIPELINE_REG = "0" *)
(* C_POWER_SAVING_MODE = "0" *) (* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_VALID_LOW = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "9" *)
(* C_WR_DEPTH = "512" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "9" *)
(* C_WR_RESPONSE_LATENCY = "1" *) (* C_MSGON_VAL = "1" *) (* C_ENABLE_RST_SYNC = "1" *)
(* C_ERROR_INJECTION_TYPE = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_INTERFACE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *) (* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_SLAVE_CE = "0" *) (* C_HAS_MASTER_CE = "0" *) (* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_AXI_ID_WIDTH = "1" *) (* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_LEN_WIDTH = "8" *) (* C_AXI_LOCK_WIDTH = "1" *) (* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_RUSER = "0" *) (* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TDEST = "0" *) (* C_HAS_AXIS_TUSER = "1" *) (* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TLAST = "0" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TKEEP = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TSTRB_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *) (* C_WRCH_TYPE = "0" *)
(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_AXIS_TYPE = "0" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *) (* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *) (* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *) (* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_USE_ECC_WACH = "0" *) (* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *)
(* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) (* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_DIN_WIDTH_WACH = "32" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *)
(* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *) (* C_DIN_WIDTH_AXIS = "1" *)
(* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *) (* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_DEPTH_RACH = "16" *) (* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *) (* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *) (* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *) (* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *) (* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *) (* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *) (* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *) (* C_REG_SLICE_MODE_AXIS = "0" *)
module Fifo8xWidthRows_fifo_generator_v12_0__parameterized0
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [7:0]din;
input wr_en;
input rd_en;
input [8:0]prog_empty_thresh;
input [8:0]prog_empty_thresh_assert;
input [8:0]prog_empty_thresh_negate;
input [8:0]prog_full_thresh;
input [8:0]prog_full_thresh_assert;
input [8:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [7:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [8:0]data_count;
output [8:0]rd_data_count;
output [8:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [9:0]axi_w_prog_full_thresh;
input [9:0]axi_w_prog_empty_thresh;
output [10:0]axi_w_data_count;
output [10:0]axi_w_wr_data_count;
output [10:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [9:0]axi_r_prog_full_thresh;
input [9:0]axi_r_prog_empty_thresh;
output [10:0]axi_r_data_count;
output [10:0]axi_r_wr_data_count;
output [10:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \\<const0> ;
wire \\<const1> ;
wire axi_ar_injectdbiterr;
wire axi_ar_injectsbiterr;
wire [3:0]axi_ar_prog_empty_thresh;
wire [3:0]axi_ar_prog_full_thresh;
wire axi_aw_injectdbiterr;
wire axi_aw_injectsbiterr;
wire [3:0]axi_aw_prog_empty_thresh;
wire [3:0]axi_aw_prog_full_thresh;
wire axi_b_injectdbiterr;
wire axi_b_injectsbiterr;
wire [3:0]axi_b_prog_empty_thresh;
wire [3:0]axi_b_prog_full_thresh;
wire axi_r_injectdbiterr;
wire axi_r_injectsbiterr;
wire [9:0]axi_r_prog_empty_thresh;
wire [9:0]axi_r_prog_full_thresh;
wire axi_w_injectdbiterr;
wire axi_w_injectsbiterr;
wire [9:0]axi_w_prog_empty_thresh;
wire [9:0]axi_w_prog_full_thresh;
wire axis_injectdbiterr;
wire axis_injectsbiterr;
wire [9:0]axis_prog_empty_thresh;
wire [9:0]axis_prog_full_thresh;
wire backup;
wire backup_marker;
wire clk;
wire [8:0]data_count;
wire [7:0]din;
wire [7:0]dout;
wire empty;
wire full;
wire injectdbiterr;
wire injectsbiterr;
wire int_clk;
wire m_aclk;
wire m_aclk_en;
wire m_axi_arready;
wire m_axi_awready;
wire [0:0]m_axi_bid;
wire [1:0]m_axi_bresp;
wire [0:0]m_axi_buser;
wire m_axi_bvalid;
wire [63:0]m_axi_rdata;
wire [0:0]m_axi_rid;
wire m_axi_rlast;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_ruser;
wire m_axi_rvalid;
wire m_axi_wready;
wire m_axis_tready;
wire [8:0]prog_empty_thresh;
wire [8:0]prog_empty_thresh_assert;
wire [8:0]prog_empty_thresh_negate;
wire [8:0]prog_full_thresh;
wire [8:0]prog_full_thresh_assert;
wire [8:0]prog_full_thresh_negate;
wire rd_clk;
wire rd_en;
wire rd_rst;
wire rst;
wire s_aclk;
wire s_aclk_en;
wire s_aresetn;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire [0:0]s_axi_aruser;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire [0:0]s_axi_awuser;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_rready;
wire [63:0]s_axi_wdata;
wire [0:0]s_axi_wid;
wire s_axi_wlast;
wire [7:0]s_axi_wstrb;
wire [0:0]s_axi_wuser;
wire s_axi_wvalid;
wire [7:0]s_axis_tdata;
wire [0:0]s_axis_tdest;
wire [0:0]s_axis_tid;
wire [0:0]s_axis_tkeep;
wire s_axis_tlast;
wire [0:0]s_axis_tstrb;
wire [3:0]s_axis_tuser;
wire s_axis_tvalid;
wire srst;
wire wr_clk;
wire wr_en;
wire wr_rst;
assign almost_empty = \\<const0> ;
assign almost_full = \\<const0> ;
assign axi_ar_data_count[4] = \\<const0> ;
assign axi_ar_data_count[3] = \\<const0> ;
assign axi_ar_data_count[2] = \\<const0> ;
assign axi_ar_data_count[1] = \\<const0> ;
assign axi_ar_data_count[0] = \\<const0> ;
assign axi_ar_dbiterr = \\<const0> ;
assign axi_ar_overflow = \\<const0> ;
assign axi_ar_prog_empty = \\<const1> ;
assign axi_ar_prog_full = \\<const0> ;
assign axi_ar_rd_data_count[4] = \\<const0> ;
assign axi_ar_rd_data_count[3] = \\<const0> ;
assign axi_ar_rd_data_count[2] = \\<const0> ;
assign axi_ar_rd_data_count[1] = \\<const0> ;
assign axi_ar_rd_data_count[0] = \\<const0> ;
assign axi_ar_sbiterr = \\<const0> ;
assign axi_ar_underflow = \\<const0> ;
assign axi_ar_wr_data_count[4] = \\<const0> ;
assign axi_ar_wr_data_count[3] = \\<const0> ;
assign axi_ar_wr_data_count[2] = \\<const0> ;
assign axi_ar_wr_data_count[1] = \\<const0> ;
assign axi_ar_wr_data_count[0] = \\<const0> ;
assign axi_aw_data_count[4] = \\<const0> ;
assign axi_aw_data_count[3] = \\<const0> ;
assign axi_aw_data_count[2] = \\<const0> ;
assign axi_aw_data_count[1] = \\<const0> ;
assign axi_aw_data_count[0] = \\<const0> ;
assign axi_aw_dbiterr = \\<const0> ;
assign axi_aw_overflow = \\<const0> ;
assign axi_aw_prog_empty = \\<const1> ;
assign axi_aw_prog_full = \\<const0> ;
assign axi_aw_rd_data_count[4] = \\<const0> ;
assign axi_aw_rd_data_count[3] = \\<const0> ;
assign axi_aw_rd_data_count[2] = \\<const0> ;
assign axi_aw_rd_data_count[1] = \\<const0> ;
assign axi_aw_rd_data_count[0] = \\<const0> ;
assign axi_aw_sbiterr = \\<const0> ;
assign axi_aw_underflow = \\<const0> ;
assign axi_aw_wr_data_count[4] = \\<const0> ;
assign axi_aw_wr_data_count[3] = \\<const0> ;
assign axi_aw_wr_data_count[2] = \\<const0> ;
assign axi_aw_wr_data_count[1] = \\<const0> ;
assign axi_aw_wr_data_count[0] = \\<const0> ;
assign axi_b_data_count[4] = \\<const0> ;
assign axi_b_data_count[3] = \\<const0> ;
assign axi_b_data_count[2] = \\<const0> ;
assign axi_b_data_count[1] = \\<const0> ;
assign axi_b_data_count[0] = \\<const0> ;
assign axi_b_dbiterr = \\<const0> ;
assign axi_b_overflow = \\<const0> ;
assign axi_b_prog_empty = \\<const1> ;
assign axi_b_prog_full = \\<const0> ;
assign axi_b_rd_data_count[4] = \\<const0> ;
assign axi_b_rd_data_count[3] = \\<const0> ;
assign axi_b_rd_data_count[2] = \\<const0> ;
assign axi_b_rd_data_count[1] = \\<const0> ;
assign axi_b_rd_data_count[0] = \\<const0> ;
assign axi_b_sbiterr = \\<const0> ;
assign axi_b_underflow = \\<const0> ;
assign axi_b_wr_data_count[4] = \\<const0> ;
assign axi_b_wr_data_count[3] = \\<const0> ;
assign axi_b_wr_data_count[2] = \\<const0> ;
assign axi_b_wr_data_count[1] = \\<const0> ;
assign axi_b_wr_data_count[0] = \\<const0> ;
assign axi_r_data_count[10] = \\<const0> ;
assign axi_r_data_count[9] = \\<const0> ;
assign axi_r_data_count[8] = \\<const0> ;
assign axi_r_data_count[7] = \\<const0> ;
assign axi_r_data_count[6] = \\<const0> ;
assign axi_r_data_count[5] = \\<const0> ;
assign axi_r_data_count[4] = \\<const0> ;
assign axi_r_data_count[3] = \\<const0> ;
assign axi_r_data_count[2] = \\<const0> ;
assign axi_r_data_count[1] = \\<const0> ;
assign axi_r_data_count[0] = \\<const0> ;
assign axi_r_dbiterr = \\<const0> ;
assign axi_r_overflow = \\<const0> ;
assign axi_r_prog_empty = \\<const1> ;
assign axi_r_prog_full = \\<const0> ;
assign axi_r_rd_data_count[10] = \\<const0> ;
assign axi_r_rd_data_count[9] = \\<const0> ;
assign axi_r_rd_data_count[8] = \\<const0> ;
assign axi_r_rd_data_count[7] = \\<const0> ;
assign axi_r_rd_data_count[6] = \\<const0> ;
assign axi_r_rd_data_count[5] = \\<const0> ;
assign axi_r_rd_data_count[4] = \\<const0> ;
assign axi_r_rd_data_count[3] = \\<const0> ;
assign axi_r_rd_data_count[2] = \\<const0> ;
assign axi_r_rd_data_count[1] = \\<const0> ;
assign axi_r_rd_data_count[0] = \\<const0> ;
assign axi_r_sbiterr = \\<const0> ;
assign axi_r_underflow = \\<const0> ;
assign axi_r_wr_data_count[10] = \\<const0> ;
assign axi_r_wr_data_count[9] = \\<const0> ;
assign axi_r_wr_data_count[8] = \\<const0> ;
assign axi_r_wr_data_count[7] = \\<const0> ;
assign axi_r_wr_data_count[6] = \\<const0> ;
assign axi_r_wr_data_count[5] = \\<const0> ;
assign axi_r_wr_data_count[4] = \\<const0> ;
assign axi_r_wr_data_count[3] = \\<const0> ;
assign axi_r_wr_data_count[2] = \\<const0> ;
assign axi_r_wr_data_count[1] = \\<const0> ;
assign axi_r_wr_data_count[0] = \\<const0> ;
assign axi_w_data_count[10] = \\<const0> ;
assign axi_w_data_count[9] = \\<const0> ;
assign axi_w_data_count[8] = \\<const0> ;
assign axi_w_data_count[7] = \\<const0> ;
assign axi_w_data_count[6] = \\<const0> ;
assign axi_w_data_count[5] = \\<const0> ;
assign axi_w_data_count[4] = \\<const0> ;
assign axi_w_data_count[3] = \\<const0> ;
assign axi_w_data_count[2] = \\<const0> ;
assign axi_w_data_count[1] = \\<const0> ;
assign axi_w_data_count[0] = \\<const0> ;
assign axi_w_dbiterr = \\<const0> ;
assign axi_w_overflow = \\<const0> ;
assign axi_w_prog_empty = \\<const1> ;
assign axi_w_prog_full = \\<const0> ;
assign axi_w_rd_data_count[10] = \\<const0> ;
assign axi_w_rd_data_count[9] = \\<const0> ;
assign axi_w_rd_data_count[8] = \\<const0> ;
assign axi_w_rd_data_count[7] = \\<const0> ;
assign axi_w_rd_data_count[6] = \\<const0> ;
assign axi_w_rd_data_count[5] = \\<const0> ;
assign axi_w_rd_data_count[4] = \\<const0> ;
assign axi_w_rd_data_count[3] = \\<const0> ;
assign axi_w_rd_data_count[2] = \\<const0> ;
assign axi_w_rd_data_count[1] = \\<const0> ;
assign axi_w_rd_data_count[0] = \\<const0> ;
assign axi_w_sbiterr = \\<const0> ;
assign axi_w_underflow = \\<const0> ;
assign axi_w_wr_data_count[10] = \\<const0> ;
assign axi_w_wr_data_count[9] = \\<const0> ;
assign axi_w_wr_data_count[8] = \\<const0> ;
assign axi_w_wr_data_count[7] = \\<const0> ;
assign axi_w_wr_data_count[6] = \\<const0> ;
assign axi_w_wr_data_count[5] = \\<const0> ;
assign axi_w_wr_data_count[4] = \\<const0> ;
assign axi_w_wr_data_count[3] = \\<const0> ;
assign axi_w_wr_data_count[2] = \\<const0> ;
assign axi_w_wr_data_count[1] = \\<const0> ;
assign axi_w_wr_data_count[0] = \\<const0> ;
assign axis_data_count[10] = \\<const0> ;
assign axis_data_count[9] = \\<const0> ;
assign axis_data_count[8] = \\<const0> ;
assign axis_data_count[7] = \\<const0> ;
assign axis_data_count[6] = \\<const0> ;
assign axis_data_count[5] = \\<const0> ;
assign axis_data_count[4] = \\<const0> ;
assign axis_data_count[3] = \\<const0> ;
assign axis_data_count[2] = \\<const0> ;
assign axis_data_count[1] = \\<const0> ;
assign axis_data_count[0] = \\<const0> ;
assign axis_dbiterr = \\<const0> ;
assign axis_overflow = \\<const0> ;
assign axis_prog_empty = \\<const1> ;
assign axis_prog_full = \\<const0> ;
assign axis_rd_data_count[10] = \\<const0> ;
assign axis_rd_data_count[9] = \\<const0> ;
assign axis_rd_data_count[8] = \\<const0> ;
assign axis_rd_data_count[7] = \\<const0> ;
assign axis_rd_data_count[6] = \\<const0> ;
assign axis_rd_data_count[5] = \\<const0> ;
assign axis_rd_data_count[4] = \\<const0> ;
assign axis_rd_data_count[3] = \\<const0> ;
assign axis_rd_data_count[2] = \\<const0> ;
assign axis_rd_data_count[1] = \\<const0> ;
assign axis_rd_data_count[0] = \\<const0> ;
assign axis_sbiterr = \\<const0> ;
assign axis_underflow = \\<const0> ;
assign axis_wr_data_count[10] = \\<const0> ;
assign axis_wr_data_count[9] = \\<const0> ;
assign axis_wr_data_count[8] = \\<const0> ;
assign axis_wr_data_count[7] = \\<const0> ;
assign axis_wr_data_count[6] = \\<const0> ;
assign axis_wr_data_count[5] = \\<const0> ;
assign axis_wr_data_count[4] = \\<const0> ;
assign axis_wr_data_count[3] = \\<const0> ;
assign axis_wr_data_count[2] = \\<const0> ;
assign axis_wr_data_count[1] = \\<const0> ;
assign axis_wr_data_count[0] = \\<const0> ;
assign dbiterr = \\<const0> ;
assign m_axi_araddr[31] = \\<const0> ;
assign m_axi_araddr[30] = \\<const0> ;
assign m_axi_araddr[29] = \\<const0> ;
assign m_axi_araddr[28] = \\<const0> ;
assign m_axi_araddr[27] = \\<const0> ;
assign m_axi_araddr[26] = \\<const0> ;
assign m_axi_araddr[25] = \\<const0> ;
assign m_axi_araddr[24] = \\<const0> ;
assign m_axi_araddr[23] = \\<const0> ;
assign m_axi_araddr[22] = \\<const0> ;
assign m_axi_araddr[21] = \\<const0> ;
assign m_axi_araddr[20] = \\<const0> ;
assign m_axi_araddr[19] = \\<const0> ;
assign m_axi_araddr[18] = \\<const0> ;
assign m_axi_araddr[17] = \\<const0> ;
assign m_axi_araddr[16] = \\<const0> ;
assign m_axi_araddr[15] = \\<const0> ;
assign m_axi_araddr[14] = \\<const0> ;
assign m_axi_araddr[13] = \\<const0> ;
assign m_axi_araddr[12] = \\<const0> ;
assign m_axi_araddr[11] = \\<const0> ;
assign m_axi_araddr[10] = \\<const0> ;
assign m_axi_araddr[9] = \\<const0> ;
assign m_axi_araddr[8] = \\<const0> ;
assign m_axi_araddr[7] = \\<const0> ;
assign m_axi_araddr[6] = \\<const0> ;
assign m_axi_araddr[5] = \\<const0> ;
assign m_axi_araddr[4] = \\<const0> ;
assign m_axi_araddr[3] = \\<const0> ;
assign m_axi_araddr[2] = \\<const0> ;
assign m_axi_araddr[1] = \\<const0> ;
assign m_axi_araddr[0] = \\<const0> ;
assign m_axi_arburst[1] = \\<const0> ;
assign m_axi_arburst[0] = \\<const0> ;
assign m_axi_arcache[3] = \\<const0> ;
assign m_axi_arcache[2] = \\<const0> ;
assign m_axi_arcache[1] = \\<const0> ;
assign m_axi_arcache[0] = \\<const0> ;
assign m_axi_arid[0] = \\<const0> ;
assign m_axi_arlen[7] = \\<const0> ;
assign m_axi_arlen[6] = \\<const0> ;
assign m_axi_arlen[5] = \\<const0> ;
assign m_axi_arlen[4] = \\<const0> ;
assign m_axi_arlen[3] = \\<const0> ;
assign m_axi_arlen[2] = \\<const0> ;
assign m_axi_arlen[1] = \\<const0> ;
assign m_axi_arlen[0] = \\<const0> ;
assign m_axi_arlock[0] = \\<const0> ;
assign m_axi_arprot[2] = \\<const0> ;
assign m_axi_arprot[1] = \\<const0> ;
assign m_axi_arprot[0] = \\<const0> ;
assign m_axi_arqos[3] = \\<const0> ;
assign m_axi_arqos[2] = \\<const0> ;
assign m_axi_arqos[1] = \\<const0> ;
assign m_axi_arqos[0] = \\<const0> ;
assign m_axi_arregion[3] = \\<const0> ;
assign m_axi_arregion[2] = \\<const0> ;
assign m_axi_arregion[1] = \\<const0> ;
assign m_axi_arregion[0] = \\<const0> ;
assign m_axi_arsize[2] = \\<const0> ;
assign m_axi_arsize[1] = \\<const0> ;
assign m_axi_arsize[0] = \\<const0> ;
assign m_axi_aruser[0] = \\<const0> ;
assign m_axi_arvalid = \\<const0> ;
assign m_axi_awaddr[31] = \\<const0> ;
assign m_axi_awaddr[30] = \\<const0> ;
assign m_axi_awaddr[29] = \\<const0> ;
assign m_axi_awaddr[28] = \\<const0> ;
assign m_axi_awaddr[27] = \\<const0> ;
assign m_axi_awaddr[26] = \\<const0> ;
assign m_axi_awaddr[25] = \\<const0> ;
assign m_axi_awaddr[24] = \\<const0> ;
assign m_axi_awaddr[23] = \\<const0> ;
assign m_axi_awaddr[22] = \\<const0> ;
assign m_axi_awaddr[21] = \\<const0> ;
assign m_axi_awaddr[20] = \\<const0> ;
assign m_axi_awaddr[19] = \\<const0> ;
assign m_axi_awaddr[18] = \\<const0> ;
assign m_axi_awaddr[17] = \\<const0> ;
assign m_axi_awaddr[16] = \\<const0> ;
assign m_axi_awaddr[15] = \\<const0> ;
assign m_axi_awaddr[14] = \\<const0> ;
assign m_axi_awaddr[13] = \\<const0> ;
assign m_axi_awaddr[12] = \\<const0> ;
assign m_axi_awaddr[11] = \\<const0> ;
assign m_axi_awaddr[10] = \\<const0> ;
assign m_axi_awaddr[9] = \\<const0> ;
assign m_axi_awaddr[8] = \\<const0> ;
assign m_axi_awaddr[7] = \\<const0> ;
assign m_axi_awaddr[6] = \\<const0> ;
assign m_axi_awaddr[5] = \\<const0> ;
assign m_axi_awaddr[4] = \\<const0> ;
assign m_axi_awaddr[3] = \\<const0> ;
assign m_axi_awaddr[2] = \\<const0> ;
assign m_axi_awaddr[1] = \\<const0> ;
assign m_axi_awaddr[0] = \\<const0> ;
assign m_axi_awburst[1] = \\<const0> ;
assign m_axi_awburst[0] = \\<const0> ;
assign m_axi_awcache[3] = \\<const0> ;
assign m_axi_awcache[2] = \\<const0> ;
assign m_axi_awcache[1] = \\<const0> ;
assign m_axi_awcache[0] = \\<const0> ;
assign m_axi_awid[0] = \\<const0> ;
assign m_axi_awlen[7] = \\<const0> ;
assign m_axi_awlen[6] = \\<const0> ;
assign m_axi_awlen[5] = \\<const0> ;
assign m_axi_awlen[4] = \\<const0> ;
assign m_axi_awlen[3] = \\<const0> ;
assign m_axi_awlen[2] = \\<const0> ;
assign m_axi_awlen[1] = \\<const0> ;
assign m_axi_awlen[0] = \\<const0> ;
assign m_axi_awlock[0] = \\<const0> ;
assign m_axi_awprot[2] = \\<const0> ;
assign m_axi_awprot[1] = \\<const0> ;
assign m_axi_awprot[0] = \\<const0> ;
assign m_axi_awqos[3] = \\<const0> ;
assign m_axi_awqos[2] = \\<const0> ;
assign m_axi_awqos[1] = \\<const0> ;
assign m_axi_awqos[0] = \\<const0> ;
assign m_axi_awregion[3] = \\<const0> ;
assign m_axi_awregion[2] = \\<const0> ;
assign m_axi_awregion[1] = \\<const0> ;
assign m_axi_awregion[0] = \\<const0> ;
assign m_axi_awsize[2] = \\<const0> ;
assign m_axi_awsize[1] = \\<const0> ;
assign m_axi_awsize[0] = \\<const0> ;
assign m_axi_awuser[0] = \\<const0> ;
assign m_axi_awvalid = \\<const0> ;
assign m_axi_bready = \\<const0> ;
assign m_axi_rready = \\<const0> ;
assign m_axi_wdata[63] = \\<const0> ;
assign m_axi_wdata[62] = \\<const0> ;
assign m_axi_wdata[61] = \\<const0> ;
assign m_axi_wdata[60] = \\<const0> ;
assign m_axi_wdata[59] = \\<const0> ;
assign m_axi_wdata[58] = \\<const0> ;
assign m_axi_wdata[57] = \\<const0> ;
assign m_axi_wdata[56] = \\<const0> ;
assign m_axi_wdata[55] = \\<const0> ;
assign m_axi_wdata[54] = \\<const0> ;
assign m_axi_wdata[53] = \\<const0> ;
assign m_axi_wdata[52] = \\<const0> ;
assign m_axi_wdata[51] = \\<const0> ;
assign m_axi_wdata[50] = \\<const0> ;
assign m_axi_wdata[49] = \\<const0> ;
assign m_axi_wdata[48] = \\<const0> ;
assign m_axi_wdata[47] = \\<const0> ;
assign m_axi_wdata[46] = \\<const0> ;
assign m_axi_wdata[45] = \\<const0> ;
assign m_axi_wdata[44] = \\<const0> ;
assign m_axi_wdata[43] = \\<const0> ;
assign m_axi_wdata[42] = \\<const0> ;
assign m_axi_wdata[41] = \\<const0> ;
assign m_axi_wdata[40] = \\<const0> ;
assign m_axi_wdata[39] = \\<const0> ;
assign m_axi_wdata[38] = \\<const0> ;
assign m_axi_wdata[37] = \\<const0> ;
assign m_axi_wdata[36] = \\<const0> ;
assign m_axi_wdata[35] = \\<const0> ;
assign m_axi_wdata[34] = \\<const0> ;
assign m_axi_wdata[33] = \\<const0> ;
assign m_axi_wdata[32] = \\<const0> ;
assign m_axi_wdata[31] = \\<const0> ;
assign m_axi_wdata[30] = \\<const0> ;
assign m_axi_wdata[29] = \\<const0> ;
assign m_axi_wdata[28] = \\<const0> ;
assign m_axi_wdata[27] = \\<const0> ;
assign m_axi_wdata[26] = \\<const0> ;
assign m_axi_wdata[25] = \\<const0> ;
assign m_axi_wdata[24] = \\<const0> ;
assign m_axi_wdata[23] = \\<const0> ;
assign m_axi_wdata[22] = \\<const0> ;
assign m_axi_wdata[21] = \\<const0> ;
assign m_axi_wdata[20] = \\<const0> ;
assign m_axi_wdata[19] = \\<const0> ;
assign m_axi_wdata[18] = \\<const0> ;
assign m_axi_wdata[17] = \\<const0> ;
assign m_axi_wdata[16] = \\<const0> ;
assign m_axi_wdata[15] = \\<const0> ;
assign m_axi_wdata[14] = \\<const0> ;
assign m_axi_wdata[13] = \\<const0> ;
assign m_axi_wdata[12] = \\<const0> ;
assign m_axi_wdata[11] = \\<const0> ;
assign m_axi_wdata[10] = \\<const0> ;
assign m_axi_wdata[9] = \\<const0> ;
assign m_axi_wdata[8] = \\<const0> ;
assign m_axi_wdata[7] = \\<const0> ;
assign m_axi_wdata[6] = \\<const0> ;
assign m_axi_wdata[5] = \\<const0> ;
assign m_axi_wdata[4] = \\<const0> ;
assign m_axi_wdata[3] = \\<const0> ;
assign m_axi_wdata[2] = \\<const0> ;
assign m_axi_wdata[1] = \\<const0> ;
assign m_axi_wdata[0] = \\<const0> ;
assign m_axi_wid[0] = \\<const0> ;
assign m_axi_wlast = \\<const0> ;
assign m_axi_wstrb[7] = \\<const0> ;
assign m_axi_wstrb[6] = \\<const0> ;
assign m_axi_wstrb[5] = \\<const0> ;
assign m_axi_wstrb[4] = \\<const0> ;
assign m_axi_wstrb[3] = \\<const0> ;
assign m_axi_wstrb[2] = \\<const0> ;
assign m_axi_wstrb[1] = \\<const0> ;
assign m_axi_wstrb[0] = \\<const0> ;
assign m_axi_wuser[0] = \\<const0> ;
assign m_axi_wvalid = \\<const0> ;
assign m_axis_tdata[7] = \\<const0> ;
assign m_axis_tdata[6] = \\<const0> ;
assign m_axis_tdata[5] = \\<const0> ;
assign m_axis_tdata[4] = \\<const0> ;
assign m_axis_tdata[3] = \\<const0> ;
assign m_axis_tdata[2] = \\<const0> ;
assign m_axis_tdata[1] = \\<const0> ;
assign m_axis_tdata[0] = \\<const0> ;
assign m_axis_tdest[0] = \\<const0> ;
assign m_axis_tid[0] = \\<const0> ;
assign m_axis_tkeep[0] = \\<const0> ;
assign m_axis_tlast = \\<const0> ;
assign m_axis_tstrb[0] = \\<const0> ;
assign m_axis_tuser[3] = \\<const0> ;
assign m_axis_tuser[2] = \\<const0> ;
assign m_axis_tuser[1] = \\<const0> ;
assign m_axis_tuser[0] = \\<const0> ;
assign m_axis_tvalid = \\<const0> ;
assign overflow = \\<const0> ;
assign prog_empty = \\<const0> ;
assign prog_full = \\<const0> ;
assign rd_data_count[8] = \\<const0> ;
assign rd_data_count[7] = \\<const0> ;
assign rd_data_count[6] = \\<const0> ;
assign rd_data_count[5] = \\<const0> ;
assign rd_data_count[4] = \\<const0> ;
assign rd_data_count[3] = \\<const0> ;
assign rd_data_count[2] = \\<const0> ;
assign rd_data_count[1] = \\<const0> ;
assign rd_data_count[0] = \\<const0> ;
assign rd_rst_busy = \\<const0> ;
assign s_axi_arready = \\<const0> ;
assign s_axi_awready = \\<const0> ;
assign s_axi_bid[0] = \\<const0> ;
assign s_axi_bresp[1] = \\<const0> ;
assign s_axi_bresp[0] = \\<const0> ;
assign s_axi_buser[0] = \\<const0> ;
assign s_axi_bvalid = \\<const0> ;
assign s_axi_rdata[63] = \\<const0> ;
assign s_axi_rdata[62] = \\<const0> ;
assign s_axi_rdata[61] = \\<const0> ;
assign s_axi_rdata[60] = \\<const0> ;
assign s_axi_rdata[59] = \\<const0> ;
assign s_axi_rdata[58] = \\<const0> ;
assign s_axi_rdata[57] = \\<const0> ;
assign s_axi_rdata[56] = \\<const0> ;
assign s_axi_rdata[55] = \\<const0> ;
assign s_axi_rdata[54] = \\<const0> ;
assign s_axi_rdata[53] = \\<const0> ;
assign s_axi_rdata[52] = \\<const0> ;
assign s_axi_rdata[51] = \\<const0> ;
assign s_axi_rdata[50] = \\<const0> ;
assign s_axi_rdata[49] = \\<const0> ;
assign s_axi_rdata[48] = \\<const0> ;
assign s_axi_rdata[47] = \\<const0> ;
assign s_axi_rdata[46] = \\<const0> ;
assign s_axi_rdata[45] = \\<const0> ;
assign s_axi_rdata[44] = \\<const0> ;
assign s_axi_rdata[43] = \\<const0> ;
assign s_axi_rdata[42] = \\<const0> ;
assign s_axi_rdata[41] = \\<const0> ;
assign s_axi_rdata[40] = \\<const0> ;
assign s_axi_rdata[39] = \\<const0> ;
assign s_axi_rdata[38] = \\<const0> ;
assign s_axi_rdata[37] = \\<const0> ;
assign s_axi_rdata[36] = \\<const0> ;
assign s_axi_rdata[35] = \\<const0> ;
assign s_axi_rdata[34] = \\<const0> ;
assign s_axi_rdata[33] = \\<const0> ;
assign s_axi_rdata[32] = \\<const0> ;
assign s_axi_rdata[31] = \\<const0> ;
assign s_axi_rdata[30] = \\<const0> ;
assign s_axi_rdata[29] = \\<const0> ;
assign s_axi_rdata[28] = \\<const0> ;
assign s_axi_rdata[27] = \\<const0> ;
assign s_axi_rdata[26] = \\<const0> ;
assign s_axi_rdata[25] = \\<const0> ;
assign s_axi_rdata[24] = \\<const0> ;
assign s_axi_rdata[23] = \\<const0> ;
assign s_axi_rdata[22] = \\<const0> ;
assign s_axi_rdata[21] = \\<const0> ;
assign s_axi_rdata[20] = \\<const0> ;
assign s_axi_rdata[19] = \\<const0> ;
assign s_axi_rdata[18] = \\<const0> ;
assign s_axi_rdata[17] = \\<const0> ;
assign s_axi_rdata[16] = \\<const0> ;
assign s_axi_rdata[15] = \\<const0> ;
assign s_axi_rdata[14] = \\<const0> ;
assign s_axi_rdata[13] = \\<const0> ;
assign s_axi_rdata[12] = \\<const0> ;
assign s_axi_rdata[11] = \\<const0> ;
assign s_axi_rdata[10] = \\<const0> ;
assign s_axi_rdata[9] = \\<const0> ;
assign s_axi_rdata[8] = \\<const0> ;
assign s_axi_rdata[7] = \\<const0> ;
assign s_axi_rdata[6] = \\<const0> ;
assign s_axi_rdata[5] = \\<const0> ;
assign s_axi_rdata[4] = \\<const0> ;
assign s_axi_rdata[3] = \\<const0> ;
assign s_axi_rdata[2] = \\<const0> ;
assign s_axi_rdata[1] = \\<const0> ;
assign s_axi_rdata[0] = \\<const0> ;
assign s_axi_rid[0] = \\<const0> ;
assign s_axi_rlast = \\<const0> ;
assign s_axi_rresp[1] = \\<const0> ;
assign s_axi_rresp[0] = \\<const0> ;
assign s_axi_ruser[0] = \\<const0> ;
assign s_axi_rvalid = \\<const0> ;
assign s_axi_wready = \\<const0> ;
assign s_axis_tready = \\<const0> ;
assign sbiterr = \\<const0> ;
assign underflow = \\<const0> ;
assign valid = \\<const0> ;
assign wr_ack = \\<const0> ;
assign wr_data_count[8] = \\<const0> ;
assign wr_data_count[7] = \\<const0> ;
assign wr_data_count[6] = \\<const0> ;
assign wr_data_count[5] = \\<const0> ;
assign wr_data_count[4] = \\<const0> ;
assign wr_data_count[3] = \\<const0> ;
assign wr_data_count[2] = \\<const0> ;
assign wr_data_count[1] = \\<const0> ;
assign wr_data_count[0] = \\<const0> ;
assign wr_rst_busy = \\<const0> ;
GND GND
(.G(\\<const0> ));
VCC VCC
(.P(\\<const1> ));
Fifo8xWidthRows_fifo_generator_v12_0_synth inst_fifo_gen
(.clk(clk),
.data_count(data_count),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.rst(rst),
.wr_en(wr_en));
endmodule
(* ORIG_REF_NAME = "fifo_generator_v12_0_synth" *)
module Fifo8xWidthRows_fifo_generator_v12_0_synth
(data_count,
dout,
empty,
full,
rd_en,
clk,
rst,
din,
wr_en);
output [8:0]data_count;
output [7:0]dout;
output empty;
output full;
input rd_en;
input clk;
input rst;
input [7:0]din;
input wr_en;
wire clk;
wire [8:0]data_count;
wire [7:0]din;
wire [7:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire wr_en;
Fifo8xWidthRows_fifo_generator_top \\gconvfifo.rf
(.DATA_COUNT(data_count),
.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.rst(rst),
.wr_en(wr_en));
endmodule
(* ORIG_REF_NAME = "memory" *)
module Fifo8xWidthRows_memory
(dout,
clk,
din,
I1,
O4,
Q,
I2,
I3,
I4,
I5,
I6,
I7,
I8,
I9,
I10,
I11,
I12,
I13,
I14,
I15,
I16,
I17,
I18,
I19,
I20,
I21,
I22,
I23,
I24,
I25,
I26,
I27,
I28,
I29,
I30,
I31,
I32,
E,
I33);
output [7:0]dout;
input clk;
input [7:0]din;
input I1;
input [8:0]O4;
input [5:0]Q;
input I2;
input I3;
input I4;
input I5;
input I6;
input I7;
input I8;
input I9;
input I10;
input I11;
input I12;
input I13;
input I14;
input I15;
input I16;
input I17;
input I18;
input I19;
input I20;
input I21;
input I22;
input I23;
input I24;
input I25;
input I26;
input I27;
input I28;
input I29;
input I30;
input I31;
input I32;
input [0:0]E;
input [0:0]I33;
wire [0:0]E;
wire I1;
wire I10;
wire I11;
wire I12;
wire I13;
wire I14;
wire I15;
wire I16;
wire I17;
wire I18;
wire I19;
wire I2;
wire I20;
wire I21;
wire I22;
wire I23;
wire I24;
wire I25;
wire I26;
wire I27;
wire I28;
wire I29;
wire I3;
wire I30;
wire I31;
wire I32;
wire [0:0]I33;
wire I4;
wire I5;
wire I6;
wire I7;
wire I8;
wire I9;
wire [8:0]O4;
wire [5:0]Q;
wire clk;
wire [7:0]din;
wire [7:0]dout;
Fifo8xWidthRows_dmem \\gdm.dm
(.E(E),
.I1(I1),
.I10(I10),
.I11(I11),
.I12(I12),
.I13(I13),
.I14(I14),
.I15(I15),
.I16(I16),
.I17(I17),
.I18(I18),
.I19(I19),
.I2(I2),
.I20(I20),
.I21(I21),
.I22(I22),
.I23(I23),
.I24(I24),
.I25(I25),
.I26(I26),
.I27(I27),
.I28(I28),
.I29(I29),
.I3(I3),
.I30(I30),
.I31(I31),
.I32(I32),
.I33(I33),
.I4(I4),
.I5(I5),
.I6(I6),
.I7(I7),
.I8(I8),
.I9(I9),
.O4(O4),
.Q(Q),
.clk(clk),
.din(din),
.dout(dout));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module Fifo8xWidthRows_rd_bin_cntr
(O1,
O2,
Q,
v1_reg,
O3,
v1_reg_1,
v1_reg_0,
I2,
comp1,
rd_en,
p_18_out,
wr_en,
p_1_out,
comp0,
I3,
E,
clk,
I1);
output O1;
output O2;
output [7:0]Q;
output [3:0]v1_reg;
output [8:0]O3;
output [3:0]v1_reg_1;
output [3:0]v1_reg_0;
input [8:0]I2;
input comp1;
input rd_en;
input p_18_out;
input wr_en;
input p_1_out;
input comp0;
input [7:0]I3;
input [0:0]E;
input clk;
input [0:0]I1;
wire [0:0]E;
wire [0:0]I1;
wire [8:0]I2;
wire [7:0]I3;
wire O1;
wire O2;
wire [8:0]O3;
wire [7:0]Q;
wire clk;
wire comp0;
wire comp1;
wire \
_0_gc0.count[8]_i_2 ;
wire p_18_out;
wire p_1_out;
wire [8:0]plusOp;
wire rd_en;
wire [8:8]rd_pntr_plus1;
wire [3:0]v1_reg;
wire [3:0]v1_reg_0;
wire [3:0]v1_reg_1;
wire wr_en;
LUT1 #(
.INIT(2\'h1))
\\gc0.count[0]_i_1
(.I0(Q[0]),
.O(plusOp[0]));
LUT2 #(
.INIT(4\'h6))
\\gc0.count[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8\'h6A))
\\gc0.count[2]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.O(plusOp[2]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16\'h7F80))
\\gc0.count[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(plusOp[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32\'h6AAAAAAA))
\\gc0.count[4]_i_1
(.I0(Q[4]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[3]),
.O(plusOp[4]));
LUT6 #(
.INIT(64\'h6AAAAAAAAAAAAAAA))
\\gc0.count[5]_i_1
(.I0(Q[5]),
.I1(Q[3]),
.I2(Q[2]),
.I3(Q[0]),
.I4(Q[1]),
.I5(Q[4]),
.O(plusOp[5]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16\'h6AAA))
\\gc0.count[6]_i_1
(.I0(Q[6]),
.I1(Q[4]),
.I2(\
_0_gc0.count[8]_i_2 ),
.I3(Q[5]),
.O(plusOp[6]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32\'h6AAAAAAA))
\\gc0.count[7]_i_1
(.I0(Q[7]),
.I1(Q[5]),
.I2(\
_0_gc0.count[8]_i_2 ),
.I3(Q[4]),
.I4(Q[6]),
.O(plusOp[7]));
LUT6 #(
.INIT(64\'h6AAAAAAAAAAAAAAA))
\\gc0.count[8]_i_1
(.I0(rd_pntr_plus1),
.I1(Q[6]),
.I2(Q[4]),
.I3(\
_0_gc0.count[8]_i_2 ),
.I4(Q[5]),
.I5(Q[7]),
.O(plusOp[8]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16\'h8000))
\\gc0.count[8]_i_2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.O(\
_0_gc0.count[8]_i_2 ));
FDCE #(
.INIT(1\'b0))
\\gc0.count_d1_reg[0]
(.C(clk),
.CE(E),
.CLR(I1),
.D(Q[0]),
.Q(O3[0]));
FDCE #(
.INIT(1\'b0))
\\gc0.count_d1_reg[1]
(.C(clk),
.CE(E),
.CLR(I1),
.D(Q[1]),
.Q(O3[1]));
FDCE #(
.INIT(1\'b0))
\\gc0.count_d1_reg[2]
(.C(clk),
.CE(E),
.CLR(I1),
.D(Q[2]),
.Q(O3[2]));
FDCE #(
.INIT(1\'b0))
\\gc0.count_d1_reg[3]
(.C(clk),
.CE(E),
.CLR(I1),
.D(Q[3]),
.Q(O3[3]));
FDCE #(
.INIT(1\'b0))
\\gc0.count_d1_reg[4]
(.C(clk),
.CE(E),
.CLR(I1),
.D(Q[4]),
.Q(O3[4]));
FDCE #(
.INIT(1\'b0))
\\gc0.count_d1_reg[5]
(.C(clk),
.CE(E),
.CLR(I1),
.D(Q[5]),
.Q(O3[5]));
FDCE #(
.INIT(1\'b0))
\\gc0.count_d1_reg[6]
(.C(clk),
.CE(E),
.CLR(I1),
.D(Q[6]),
.Q(O3[6]));
FDCE #(
.INIT(1\'b0))
\\gc0.count_d1_reg[7]
(.C(clk),
.CE(E),
.CLR(I1),
.D(Q[7]),
.Q(O3[7]));
FDCE #(
.INIT(1\'b0))
\\gc0.count_d1_reg[8]
(.C(clk),
.CE(E),
.CLR(I1),
.D(rd_pntr_plus1),
.Q(O3[8]));
FDPE #(
.INIT(1\'b1))
\\gc0.count_reg[0]
(.C(clk),
.CE(E),
.D(plusOp[0]),
.PRE(I1),
.Q(Q[0]));
FDCE #(
.INIT(1\'b0))
\\gc0.count_reg[1]
(.C(clk),
.CE(E),
.CLR(I1),
.D(plusOp[1]),
.Q(Q[1]));
FDCE #(
.INIT(1\'b0))
\\gc0.count_reg[2]
(.C(clk),
.CE(E),
.CLR(I1),
.D(plusOp[2]),
.Q(Q[2]));
FDCE #(
.INIT(1\'b0))
\\gc0.count_reg[3]
(.C(clk),
.CE(E),
.CLR(I1),
.D(plusOp[3]),
.Q(Q[3]));
FDCE #(
.INIT(1\'b0))
\\gc0.count_reg[4]
(.C(clk),
.CE(E),
.CLR(I1),
.D(plusOp[4]),
.Q(Q[4]));
FDCE #(
.INIT(1\'b0))
\\gc0.count_reg[5]
(.C(clk),
.CE(E),
.CLR(I1),
.D(plusOp[5]),
.Q(Q[5]));
FDCE #(
.INIT(1\'b0))
\\gc0.count_reg[6]
(.C(clk),
.CE(E),
.CLR(I1),
.D(plusOp[6]),
.Q(Q[6]));
FDCE #(
.INIT(1\'b0))
\\gc0.count_reg[7]
(.C(clk),
.CE(E),
.CLR(I1),
.D(plusOp[7]),
.Q(Q[7]));
FDCE #(
.INIT(1\'b0))
\\gc0.count_reg[8]
(.C(clk),
.CE(E),
.CLR(I1),
.D(plusOp[8]),
.Q(rd_pntr_plus1));
LUT4 #(
.INIT(16\'h9009))
\\gmux.gm[0].gm1.m1_i_1
(.I0(O3[1]),
.I1(I2[1]),
.I2(O3[0]),
.I3(I2[0]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16\'h9009))
\\gmux.gm[0].gm1.m1_i_1__0
(.I0(O3[1]),
.I1(I2[1]),
.I2(O3[0]),
.I3(I2[0]),
.O(v1_reg_1[0]));
LUT4 #(
.INIT(16\'h9009))
\\gmux.gm[0].gm1.m1_i_1__2
(.I0(O3[1]),
.I1(I3[1]),
.I2(O3[0]),
.I3(I3[0]),
.O(v1_reg_0[0]));
LUT4 #(
.INIT(16\'h9009))
\\gmux.gm[1].gms.ms_i_1
(.I0(O3[3]),
.I1(I2[3]),
.I2(O3[2]),
.I3(I2[2]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16\'h9009))
\\gmux.gm[1].gms.ms_i_1__0
(.I0(O3[3]),
.I1(I2[3]),
.I2(O3[2]),
.I3(I2[2]),
.O(v1_reg_1[1]));
LUT4 #(
.INIT(16\'h9009))
\\gmux.gm[1].gms.ms_i_1__2
(.I0(O3[3]),
.I1(I3[3]),
.I2(O3[2]),
.I3(I3[2]),
.O(v1_reg_0[1]));
LUT4 #(
.INIT(16\'h9009))
\\gmux.gm[2].gms.ms_i_1
(.I0(O3[5]),
.I1(I2[5]),
.I2(O3[4]),
.I3(I2[4]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16\'h9009))
\\gmux.gm[2].gms.ms_i_1__0
(.I0(O3[5]),
.I1(I2[5]),
.I2(O3[4]),
.I3(I2[4]),
.O(v1_reg_1[2]));
LUT4 #(
.INIT(16\'h9009))
\\gmux.gm[2].gms.ms_i_1__2
(.I0(O3[5]),
.I1(I3[5]),
.I2(O3[4]),
.I3(I3[4]),
.O(v1_reg_0[2]));
LUT4 #(
.INIT(16\'h9009))
\\gmux.gm[3].gms.ms_i_1
(.I0(O3[7]),
.I1(I2[7]),
.I2(O3[6]),
.I3(I2[6]),
.O(v1_reg[3]));
LUT4 #(
.INIT(16\'h9009))
\\gmux.gm[3].gms.ms_i_1__0
(.I0(O3[7]),
.I1(I2[7]),
.I2(O3[6]),
.I3(I2[6]),
.O(v1_reg_1[3]));
LUT4 #(
.INIT(16\'h9009))
\\gmux.gm[3].gms.ms_i_1__2
(.I0(O3[7]),
.I1(I3[7]),
.I2(O3[6]),
.I3(I3[6]),
.O(v1_reg_0[3]));
LUT2 #(
.INIT(4\'h9))
\\gmux.gm[4].gms.ms_i_1__0
(.I0(rd_pntr_plus1),
.I1(I2[8]),
.O(O1));
LUT6 #(
.INIT(64\'hF8F800F8F8F8F0F8))
ram_empty_i_i_1
(.I0(comp1),
.I1(rd_en),
.I2(p_18_out),
.I3(wr_en),
.I4(p_1_out),
.I5(comp0),
.O(O2));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module Fifo8xWidthRows_rd_logic
(p_18_out,
empty,
O1,
O2,
E,
O3,
v1_reg,
O4,
v1_reg_0,
I1,
v1_reg_1,
clk,
Q,
rd_en,
I2,
wr_en,
p_1_out,
I3,
I4);
output p_18_out;
output empty;
output [8:0]O1;
output [7:0]O2;
output [0:0]E;
output [0:0]O3;
output [3:0]v1_reg;
output [8:0]O4;
output [3:0]v1_reg_0;
input I1;
input [3:0]v1_reg_1;
input clk;
input [0:0]Q;
input rd_en;
input [8:0]I2;
input wr_en;
input p_1_out;
input [7:0]I3;
input [0:0]I4;
wire [0:0]E;
wire I1;
wire [8:0]I2;
wire [7:0]I3;
wire [0:0]I4;
wire [8:0]O1;
wire [7:0]O2;
wire [0:0]O3;
wire [8:0]O4;
wire [0:0]Q;
wire [3:0]\\c1/v1_reg ;
wire clk;
wire comp0;
wire comp1;
wire empty;
wire n_0_rpntr;
wire n_1_rpntr;
wire \
_4_grss.rsts ;
wire \
_5_grss.rsts ;
wire \
_6_grss.rsts ;
wire \
_7_grss.rsts ;
wire p_18_out;
wire p_1_out;
wire rd_en;
wire [3:0]v1_reg;
wire [3:0]v1_reg_0;
wire [3:0]v1_reg_1;
wire wr_en;
Fifo8xWidthRows_dc_ss \\grss.gdc.dc
(.DI({\
_6_grss.rsts ,\
_7_grss.rsts }),
.I4(I4),
.O1(O1),
.Q(Q),
.S({\
_4_grss.rsts ,\
_5_grss.rsts }),
.clk(clk));
Fifo8xWidthRows_rd_status_flags_ss \\grss.rsts
(.DI({\
_6_grss.rsts ,\
_7_grss.rsts }),
.E(E),
.I1(I1),
.I2(n_0_rpntr),
.I3(n_1_rpntr),
.I4(O1[2:1]),
.O1(p_18_out),
.O3(O3),
.Q(Q),
.S({\
_4_grss.rsts ,\
_5_grss.rsts }),
.clk(clk),
.comp0(comp0),
.comp1(comp1),
.empty(empty),
.rd_en(rd_en),
.v1_reg(\\c1/v1_reg ),
.v1_reg_1(v1_reg_1));
Fifo8xWidthRows_rd_bin_cntr rpntr
(.E(E),
.I1(Q),
.I2(I2),
.I3(I3),
.O1(n_0_rpntr),
.O2(n_1_rpntr),
.O3(O4),
.Q(O2),
.clk(clk),
.comp0(comp0),
.comp1(comp1),
.p_18_out(p_18_out),
.p_1_out(p_1_out),
.rd_en(rd_en),
.v1_reg(v1_reg),
.v1_reg_0(v1_reg_0),
.v1_reg_1(\\c1/v1_reg ),
.wr_en(wr_en));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_ss" *)
module Fifo8xWidthRows_rd_status_flags_ss
(comp0,
comp1,
O1,
empty,
S,
DI,
E,
O3,
v1_reg,
I1,
v1_reg_1,
I2,
I3,
clk,
Q,
rd_en,
I4);
output comp0;
output comp1;
output O1;
output empty;
output [1:0]S;
output [1:0]'b'DI;
output [0:0]E;
output [0:0]O3;
input [3:0]v1_reg;
input I1;
input [3:0]v1_reg_1;
input I2;
input I3;
input clk;
input [0:0]Q;
input rd_en;
input [1:0]I4;
wire [1:0]DI;
wire [0:0]E;
wire I1;
wire I2;
wire I3;
wire [1:0]I4;
wire O1;
wire [0:0]O3;
wire [0:0]Q;
wire [1:0]S;
wire clk;
wire comp0;
wire comp1;
wire empty;
wire rd_en;
wire [3:0]v1_reg;
wire [3:0]v1_reg_1;
Fifo8xWidthRows_compare_1 c1
(.I1(I1),
.comp0(comp0),
.v1_reg(v1_reg));
Fifo8xWidthRows_compare_2 c2
(.I2(I2),
.comp1(comp1),
.v1_reg_1(v1_reg_1));
LUT2 #(
.INIT(4\'hB))
\\count[3]_i_2
(.I0(O1),
.I1(rd_en),
.O(DI[1]));
LUT2 #(
.INIT(4\'h2))
\\count[3]_i_3
(.I0(rd_en),
.I1(O1),
.O(DI[0]));
LUT3 #(
.INIT(8\'hB4))
\\count[3]_i_5
(.I0(O1),
.I1(rd_en),
.I2(I4[1]),
.O(S[1]));
LUT3 #(
.INIT(8\'hB4))
\\count[3]_i_6
(.I0(O1),
.I1(rd_en),
.I2(I4[0]),
.O(S[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4\'h2))
\\gc0.count_d1[8]_i_1
(.I0(rd_en),
.I1(O1),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4\'h2))
\\gpr1.dout_i[7]_i_1
(.I0(rd_en),
.I1(O1),
.O(O3));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1\'b1))
ram_empty_fb_i_reg
(.C(clk),
.CE(1\'b1),
.D(I3),
.PRE(Q),
.Q(O1));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1\'b1))
ram_empty_i_reg
(.C(clk),
.CE(1\'b1),
.D(I3),
.PRE(Q),
.Q(empty));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module Fifo8xWidthRows_reset_blk_ramfifo
(rst_d2,
rst_full_gen_i,
AR,
Q,
clk,
rst);
output rst_d2;
output rst_full_gen_i;
output [0:0]AR;
output [1:0]Q;
input clk;
input rst;
wire [0:0]AR;
wire [1:0]Q;
wire clk;
wire \
_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 ;
wire \
_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1 ;
wire rd_rst_asreg;
wire rd_rst_asreg_d1;
wire rd_rst_asreg_d2;
wire rst;
wire rst_d1;
wire rst_d2;
wire rst_d3;
wire rst_full_gen_i;
wire wr_rst_asreg;
wire wr_rst_asreg_d1;
wire wr_rst_asreg_d2;
FDCE #(
.INIT(1\'b0))
\\grstd1.grst_full.grst_f.RST_FULL_GEN_reg
(.C(clk),
.CE(1\'b1),
.CLR(rst),
.D(rst_d3),
.Q(rst_full_gen_i));
(* ASYNC_REG *)
(* msgon = "true" *)
FDPE #(
.INIT(1\'b1))
\\grstd1.grst_full.grst_f.rst_d1_reg
(.C(clk),
.CE(1\'b1),
.D(1\'b0),
.PRE(rst),
.Q(rst_d1));
(* ASYNC_REG *)
(* msgon = "true" *)
FDPE #(
.INIT(1\'b1))
\\grstd1.grst_full.grst_f.rst_d2_reg
(.C(clk),
.CE(1\'b1),
.D(rst_d1),
.PRE(rst),
.Q(rst_d2));
(* ASYNC_REG *)
(* msgon = "true" *)
FDPE #(
.INIT(1\'b1))
\\grstd1.grst_full.grst_f.rst_d3_reg
(.C(clk),
.CE(1\'b1),
.D(rst_d2),
.PRE(rst),
.Q(rst_d3));
(* ASYNC_REG *)
(* msgon = "true" *)
FDRE #(
.INIT(1\'b0))
\
gwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg
(.C(clk),
.CE(1\'b1),
.D(rd_rst_asreg),
.Q(rd_rst_asreg_d1),
.R(1\'b0));
(* ASYNC_REG *)
(* msgon = "true" *)
FDRE #(
.INIT(1\'b0))
\
gwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg
(.C(clk),
.CE(1\'b1),
.D(rd_rst_asreg_d1),
.Q(rd_rst_asreg_d2),
.R(1\'b0));
(* ASYNC_REG *)
(* msgon = "true" *)
FDPE \
gwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(clk),
.CE(rd_rst_asreg_d1),
.D(1\'b0),
.PRE(rst),
.Q(rd_rst_asreg));
LUT2 #(
.INIT(4\'h2))
\
gwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1
(.I0(rd_rst_asreg),
.I1(rd_rst_asreg_d2),
.O(\
_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 ));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1\'b1))
\
gwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(clk),
.CE(1\'b1),
.D(1\'b0),
.PRE(\
_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 ),
.Q(Q[0]));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1\'b1))
\
gwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(clk),
.CE(1\'b1),
.D(1\'b0),
.PRE(\
_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 ),
.Q(Q[1]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDRE #(
.INIT(1\'b0))
\
gwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg
(.C(clk),
.CE(1\'b1),
.D(wr_rst_asreg),
.Q(wr_rst_asreg_d1),
.R(1\'b0));
(* ASYNC_REG *)
(* msgon = "true" *)
FDRE #(
.INIT(1\'b0))
\
gwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg
(.C(clk),
.CE(1\'b1),
.D(wr_rst_asreg_d1),
.Q(wr_rst_asreg_d2),
.R(1\'b0));
(* ASYNC_REG *)
(* msgon = "true" *)
FDPE \
gwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(clk),
.CE(wr_rst_asreg_d1),
.D(1\'b0),
.PRE(rst),
.Q(wr_rst_asreg));
LUT2 #(
.INIT(4\'h2))
\
gwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1
(.I0(wr_rst_asreg),
.I1(wr_rst_asreg_d2),
.O(\
_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1 ));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1\'b1))
\
gwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(clk),
.CE(1\'b1),
.D(1\'b0),
.PRE(\
_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1 ),
.Q(AR));
endmodule
(* ORIG_REF_NAME = "updn_cntr" *)
module Fifo8xWidthRows_updn_cntr
(O1,
DI,
S,
I4,
clk,
Q);
output [8:0]O1;
input [1:0]DI;
input [1:0]S;
input [0:0]I4;
input clk;
input [0:0]Q;
wire [1:0]DI;
wire [0:0]I4;
wire [8:0]O1;
wire [0:0]Q;
wire [1:0]S;
wire clk;
wire \
_0_count[3]_i_4 ;
wire \
_0_count[3]_i_7 ;
wire \
_0_count[7]_i_2 ;
wire \
_0_count[7]_i_3 ;
wire \
_0_count[7]_i_4 ;
wire \
_0_count[7]_i_5 ;
wire \
_0_count[8]_i_3 ;
wire \
_0_count_reg[3]_i_1 ;
wire \
_0_count_reg[7]_i_1 ;
wire \
_1_count_reg[3]_i_1 ;
wire \
_1_count_reg[7]_i_1 ;
wire \
_2_count_reg[3]_i_1 ;
wire \
_2_count_reg[7]_i_1 ;
wire \
_3_count_reg[3]_i_1 ;
wire \
_3_count_reg[7]_i_1 ;
wire \
_4_count_reg[3]_i_1 ;
wire \
_4_count_reg[7]_i_1 ;
wire \
_5_count_reg[3]_i_1 ;
wire \
_5_count_reg[7]_i_1 ;
wire \
_6_count_reg[3]_i_1 ;
wire \
_6_count_reg[7]_i_1 ;
wire \
_7_count_reg[3]_i_1 ;
wire \
_7_count_reg[7]_i_1 ;
wire \
_7_count_reg[8]_i_2 ;
wire [3:0]\\NLW_count_reg[8]_i_2_CO_UNCONNECTED ;
wire [3:1]\\NLW_count_reg[8]_i_2_O_UNCONNECTED ;
LUT2 #(
.INIT(4\'h9))
\\count[3]_i_4
(.I0(O1[2]),
.I1(O1[3]),
.O(\
_0_count[3]_i_4 ));
LUT1 #(
.INIT(2\'h1))
\\count[3]_i_7
(.I0(O1[0]),
.O(\
_0_count[3]_i_7 ));
LUT2 #(
.INIT(4\'h9))
\\count[7]_i_2
(.I0(O1[6]),
.I1(O1[7]),
.O(\
_0_count[7]_i_2 ));
LUT2 #(
.INIT(4\'h9))
\\count[7]_i_3
(.I0(O1[5]),
.I1(O1[6]),
.O(\
_0_count[7]_i_3 ));
LUT2 #(
.INIT(4\'h9))
\\count[7]_i_4
(.I0(O1[4]),
.I1(O1[5]),
.O(\
_0_count[7]_i_4 ));
LUT2 #(
.INIT(4\'h9))
\\count[7]_i_5
(.I0(O1[3]),
.I1(O1[4]),
.O(\
_0_count[7]_i_5 ));
LUT2 #(
.INIT(4\'h9))
\\count[8]_i_3
(.I0(O1[7]),
.I1(O1[8]),
.O(\
_0_count[8]_i_3 ));
FDCE #(
.INIT(1\'b0))
\\count_reg[0]
(.C(clk),
.CE(I4),
.CLR(Q),
.D(\
_7_count_reg[3]_i_1 ),
.Q(O1[0]));
FDCE #(
.INIT(1\'b0))
\\count_reg[1]
(.C(clk),
.CE(I4),
.CLR(Q),
.D(\
_6_count_reg[3]_i_1 ),
.Q(O1[1]));
FDCE #(
.INIT(1\'b0))
\\count_reg[2]
(.C(clk),
.CE(I4),
.CLR(Q),
.D(\
_5_count_reg[3]_i_1 ),
.Q(O1[2]));
FDCE #(
.INIT(1\'b0))
\\count_reg[3]
(.C(clk),
.CE(I4),
.CLR(Q),
.D(\
_4_count_reg[3]_i_1 ),
.Q(O1[3]));
CARRY4 \\count_reg[3]_i_1
(.CI(1\'b0),
.CO({\
_0_count_reg[3]_i_1 ,\
_1_count_reg[3]_i_1 ,\
_2_count_reg[3]_i_1 ,\
_3_count_reg[3]_i_1 }),
.CYINIT(1\'b0),
.DI({O1[2],DI,O1[0]}),
.O({\
_4_count_reg[3]_i_1 ,\
_5_count_reg[3]_i_1 ,\
_6_count_reg[3]_i_1 ,\
_7_count_reg[3]_i_1 }),
.S({\
_0_count[3]_i_4 ,S,\
_0_count[3]_i_7 }));
FDCE #(
.INIT(1\'b0))
\\count_reg[4]
(.C(clk),
.CE(I4),
.CLR(Q),
.D(\
_7_count_reg[7]_i_1 ),
.Q(O1[4]));
FDCE #(
.INIT(1\'b0))
\\count_reg[5]
(.C(clk),
.CE(I4),
.CLR(Q),
.D(\
_6_count_reg[7]_i_1 ),
.Q(O1[5]));
FDCE #(
.INIT(1\'b0))
\\count_reg[6]
(.C(clk),
.CE(I4),
.CLR(Q),
.D(\
_5_count_reg[7]_i_1 ),
.Q(O1[6]));
FDCE #(
.INIT(1\'b0))
\\count_reg[7]
(.C(clk),
.CE(I4),
.CLR(Q),
.D(\
_4_count_reg[7]_i_1 ),
.Q(O1[7]));
CARRY4 \\count_reg[7]_i_1
(.CI(\
_0_count_reg[3]_i_1 ),
.CO({\
_0_count_reg[7]_i_1 ,\
_1_count_reg[7]_i_1 ,\
_2_count_reg[7]_i_1 ,\
_3_count_reg[7]_i_1 }),
.CYINIT(1\'b0),
.DI(O1[6:3]),
.O({\
_4_count_reg[7]_i_1 ,\
_5_count_reg[7]_i_1 ,\
_6_count_reg[7]_i_1 ,\
_7_count_reg[7]_i_1 }),
.S({\
_0_count[7]_i_2 ,\
_0_count[7]_i_3 ,\
_0_count[7]_i_4 ,\
_0_count[7]_i_5 }));
FDCE #(
.INIT(1\'b0))
\\count_reg[8]
(.C(clk),
.CE(I4),
.CLR(Q),
.D(\
_7_count_reg[8]_i_2 ),
.Q(O1[8]));
CARRY4 \\count_reg[8]_i_2
(.CI(\
_0_count_reg[7]_i_1 ),
.CO(\\NLW_count_reg[8]_i_2_CO_UNCONNECTED [3:0]),
.CYINIT(1\'b0),
.DI({1\'b0,1\'b0,1\'b0,1\'b0}),
.O({\\NLW_count_reg[8]_i_2_O_UNCONNECTED [3:1],\
_7_count_reg[8]_i_2 }),
.S({1\'b0,1\'b0,1\'b0,\
_0_count[8]_i_3 }));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module Fifo8xWidthRows_wr_bin_cntr
(O1,
Q,
O2,
O3,
O5,
O6,
O7,
O8,
O9,
O10,
O11,
O12,
O13,
O14,
O15,
O16,
O17,
O18,
O19,
O20,
O21,
O22,
O23,
O24,
O25,
O26,
O27,
O28,
O29,
O30,
O31,
O32,
O33,
O34,
O35,
O36,
ram_full_comb,
O37,
v1_reg,
O4,
wr_en,
I1,
comp0,
rst_full_gen_i,
comp1,
E,
I2,
I3,
clk,
AR);
output O1;
output [8:0]Q;
output O2;
output O3;
output O5;
output O6;
output O7;
output O8;
output O9;
output O10;
output O11;
output O12;
output O13;
output O14;
output O15;
output O16;
output O17;
output O18;
output O19;
output O20;
output O21;
output O22;
output O23;
output O24;
output O25;
output O26;
output O27;
output O28;
output O29;
output O30;
output O31;
output O32;
output O33;
output O34;
output O35;
output O36;
output ram_full_comb;
output [7:0]O37;
output [3:0]v1_reg;
input [0:0]O4;
input wr_en;
input I1;
input comp0;
input rst_full_gen_i;
input comp1;
input [0:0]E;
input [7:0]I2;
input [0:0]I3;
input clk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire I1;
wire [7:0]I2;
wire [0:0]I3;
wire O1;
wire O10;
wire O11;
wire O12;
wire O13;
wire O14;
wire O15;
wire O16;
wire O17;
wire O18;
wire O19;
wire O2;
wire O20;
wire O21;
wire O22;
wire O23;
wire O24;
wire O25;
wire O26;
wire O27;
wire O28;
wire O29;
wire O3;
wire O30;
wire O31;
wire O32;
wire O33;
wire O34;
wire O35;
wire O36;
wire [7:0]O37;
wire [0:0]O4;
wire O5;
wire O6;
wire O7;
wire O8;
wire O9;
wire [8:0]Q;
wire clk;
wire comp0;
wire comp1;
wire \
_0_gcc0.gc0.count[8]_i_2 ;
wire [8:8]p_9_out;
wire [8:0]plusOp__0;
wire ram_full_comb;
wire rst_full_gen_i;
wire [3:0]v1_reg;
wire wr_en;
LUT5 #(
.INIT(32\'h00000100))
RAM_reg_0_63_0_2_i_1
(.I0(Q[7]),
.I1(Q[6]),
.I2(Q[8]),
.I3(wr_en),
.I4(I1),
.O(O20));
LUT5 #(
.INIT(32\'h00000100))
RAM_reg_0_63_3_5_i_1
(.I0(Q[7]),
.I1(Q[6]),
.I2(Q[8]),
.I3(wr_en),
.I4(I1),
.O(O16));
LUT5 #(
.INIT(32\'h00000100))
RAM_reg_0_63_6_6_i_1
(.I0(Q[7]),
.I1(Q[6]),
.I2(Q[8]),
.I3(wr_en),
.I4(I1),
.O(O12));
LUT5 #(
.INIT(32\'h00000100))
RAM_reg_0_63_7_7_i_1
(.I0(Q[7]),
.I1(Q[6]),
.I2(Q[8]),
.I3(wr_en),
.I4(I1),
.O(O11));
LUT5 #(
.INIT(32\'h00040000))
RAM_reg_128_191_0_2_i_1
(.I0(Q[8]),
.I1(wr_en),
.I2(I1),
.I3(Q[6]),
.I4(Q[7]),
.O(O18));
LUT5 #(
.INIT(32\'h00040000))
RAM_reg_128_191_3_5_i_1
(.I0(Q[8]),
.I1(wr_en),
.I2(I1),
.I3(Q[6]),
.I4(Q[7]),
.O(O14));
LUT5 #(
.INIT(32\'h00040000))
RAM_reg_128_191_6_6_i_1
(.I0(Q[8]),
.I1(wr_en),
.I2(I1),
.I3(Q[6]),
.I4(Q[7]),
.O(O8));
LUT5 #(
.INIT(32\'h00040000))
RAM_reg_128_191_7_7_i_1
(.I0(Q[8]),
.I1(wr_en),
.I2(I1),
.I3(Q[6]),
.I4(Q[7]),
.O(O7));
LUT5 #(
.INIT(32\'h04000000))
RAM_reg_192_255_0_2_i_1
(.I0(Q[8]),
.I1(wr_en),
.I2(I1),
.I3(Q[7]),
.I4(Q[6]),
.O(O17));
LUT5 #(
.INIT(32\'h04000000))
RAM_reg_192_255_3_5_i_1
(.I0(Q[8]),
.I1(wr_en),
.I2(I1),
.I3(Q[7]),
.I4(Q[6]),
.O(O13));
LUT5 #(
.INIT(32\'h04000000))
RAM_reg_192_255_6_6_i_1
(.I0(Q[8]),
.I1(wr_en),
.I2(I1),
.I3(Q[7]),
.I4(Q[6]),
.O(O6));
LUT5 #(
.INIT(32\'h04000000))
RAM_reg_192_255_7_7_i_1
(.I0(Q[8]),
.I1(wr_en),
.I2(I1),
.I3(Q[7]),
.I4(Q[6]),
.O(O5));
LUT5 #(
.INIT(32\'h00100000))
RAM_reg_256_319_0_2_i_1
(.I0(Q[7]),
.I1(Q[6]),
.I2(wr_en),
.I3(I1),
.I4(Q[8]),
.O(O24));
LUT5 #(
.INIT(32\'h00100000))
RAM_reg_256_319_3_5_i_1
(.I0(Q[7]),
.I1(Q[6]),
.I2(wr_en),
.I3(I1),
.I4(Q[8]),
.O(O23));
LUT5 #(
.INIT(32\'h00100000))
RAM_reg_256_319_6_6_i_1
(.I0(Q[7]),
.I1(Q[6]),
.I2(wr_en),
.I3(I1),
.I4(Q[8]),
.O(O22));
LUT5 #(
.INIT(32\'h00100000))
RAM_reg_256_319_7_7_i_1
(.I0(Q[7]),
.I1(Q[6]),
.I2(wr_en),
.I3(I1),
.I4(Q[8]),
.O(O21));
LUT5 #(
.INIT(32\'h00400000))
RAM_reg_320_383_0_2_i_1
(.I0(Q[7]),
.I1(Q[6]),
.I2(wr_en),
.I3(I1),
.I4(Q[8]),
.O(O28));
LUT5 #(
.INIT(32\'h00400000))
RAM_reg_320_383_3_5_i_1
(.I0(Q[7]),
.I1(Q[6]),
.I2(wr_en),
.I3(I1),
.I4(Q[8]),
.O(O27));
LUT5 #(
.INIT(32\'h00400000))
RAM_reg_320_383_6_6_i_1
(.I0(Q[7]),
.I1(Q[6]),
.I2(wr_en),
.I3(I1),
.I4(Q[8]),
.O(O26));
LUT5 #(
.INIT(32\'h00400000))
RAM_reg_320_383_7_7_i_1
(.I0(Q[7]),
.I1(Q[6]),
.I2(wr_en),
.I3(I1),
.I4(Q[8]),
.O(O25));
LUT5 #(
.INIT(32\'h00400000))
RAM_reg_384_447_0_2_i_1
(.I0(Q[6]),
.I1(Q[7]),
.I2(wr_en),
.I3(I1),
.I4(Q[8]),
.O(O32));
LUT5 #(
.INIT(32\'h00400000))
RAM_reg_384_447_3_5_i_1
(.I0(Q[6]),
.I1(Q[7]),
.I2(wr_en),
.I3(I1),
.I4(Q[8]),
.O(O31));
LUT5 #(
.INIT(32\'h00400000))
RAM_reg_384_447_6_6_i_1
(.I0(Q[6]),
.I1(Q[7]),
.I2(wr_en),
.I3(I1),
.I4(Q[8]),
.O(O30));
LUT5 #(
.INIT(32\'h00400000))
RAM_reg_384_447_7_7_i_1
(.I0(Q[6]),
.I1(Q[7]),
.I2(wr_en),
.I3(I1),
.I4(Q[8]),
.O(O29));
LUT5 #(
.INIT(32\'h00800000))
RAM_reg_448_511_0_2_i_1
(.I0(Q[7]),
.I1(Q[6]),
.I2(wr_en),
.I3(I1),
.I4(Q[8]),
.O(O36));
LUT5 #(
.INIT(32\'h00800000))
RAM_reg_448_511_3_5_i_1
(.I0(Q[7]),
.I1(Q[6]),
.I2(wr_en),
.I3(I1),
.I4(Q[8]),
.O(O35));
LUT5 #(
.INIT(32\'h00800000))
RAM_reg_448_511_6_6_i_1
(.I0(Q[7]),
.I1(Q[6]),
.I2(wr_en),
.I3(I1),
.I4(Q[8]),
.O(O34));
LUT5 #(
.INIT(32\'h00800000))
RAM_reg_448_511_7_7_i_1
(.I0(Q[7]),
.I1(Q[6]),
.I2(wr_en),
.I3(I1),
.I4(Q[8]),
.O(O33));
LUT5 #(
.INIT(32\'h00040000))
RAM_reg_64_127_0_2_i_1
(.I0(Q[8]),
.I1(wr_en),
.I2(I1),
.I3(Q[7]),
.I4(Q[6]),
.O(O19));
LUT5 #(
.INIT(32\'h00040000))
RAM_reg_64_127_3_5_i_1
(.I0(Q[8]),
.I1(wr_en),
.I2(I1),
.I3(Q[7]),
.I4(Q[6]),
.O(O15));
LUT5 #(
.INIT(32\'h00040000))
RAM_reg_64_127_6_6_i_1
(.I0(Q[8]),
.I1(wr_en),
.I2(I1),
.I3(Q[7]),
.I4(Q[6]),
.O(O10));
LUT5 #(
.INIT(32\'h00040000))
RAM_reg_64_127_7_7_i_1
(.I0(Q[8]),
.I1(wr_en),
.I2(I1),
.I3(Q[7]),
.I4(Q[6]),
.O(O9));
LUT1 #(
.INIT(2\'h1))
\\gcc0.gc0.count[0]_i_1
(.I0(O37[0]),
.O(plusOp__0[0]));
LUT2 #(
.INIT(4\'h6))
\\gcc0.gc0.count[1]_i_1
(.I0(O37[0]),
.I1(O37[1]),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8\'h6A))
\\gcc0.gc0.count[2]_i_1
(.I0(O37[2]),
.I1(O37[0]),
.I2(O37[1]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16\'h7F80))
\\gcc0.gc0.count[3]_i_1
(.I0(O37[1]),
.I1(O37[0]),
.I2(O37[2]),
.I3(O37[3]),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32\'h6AAAAAAA))
\\gcc0.gc0.count[4]_i_1
(.I0(O37[4]),
.I1(O37[1]),
.I2(O37[0]),
.I3(O37[2]),
.I4(O37[3]),
.O(plusOp__0[4]));
LUT6 #(
.INIT(64\'h6AAAAAAAAAAAAAAA))
\\gcc0.gc0.count[5]_i_1
(.I0(O37[5]),
.I1(O37[3]),
.I2(O37[2]),
.I3(O37[0]),
.I4(O37[1]),
.I5(O37[4]),
.O(plusOp__0[5]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16\'h6AAA))
\\gcc0.gc0.count[6]_i_1
(.I0(O37[6]),
.I1(O37[4]),
.I2(\
_0_gcc0.gc0.count[8]_i_2 ),
.I3(O37[5]),
.O(plusOp__0[6]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32\'h6AAAAAAA))
\\gcc0.gc0.count[7]_i_1
(.I0(O37[7]),
.I1(O37[5]),
.I2(\
_0_gcc0.gc0.count[8]_i_2 ),
.I3(O37[4]),
.I4(O37[6]),
.O(plusOp__0[7]));
LUT6 #(
.INIT(64\'h6AAAAAAAAAAAAAAA))
\\gcc0.gc0.count[8]_i_1
(.I0(p_9_out),
.I1(O37[6]),
.I2(O37[4]),
.I3(\
_0_gcc0.gc0.count[8]_i_2 ),
.I4(O37[5]),
.I5(O37[7]),
.O(plusOp__0[8]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16\'h8000))
\\gcc0.gc0.count[8]_i_2
(.I0(O37[3]),
.I1(O37[2]),
.I2(O37[0]),
.I3(O37[1]),
.O(\
_0_gcc0.gc0.count[8]_i_2 ));
FDCE #(
.INIT(1\'b0))
\\gcc0.gc0.count_d1_reg[0]
(.C(clk),
.CE(I3),
.CLR(AR),
.D(O37[0]),
.Q(Q[0]));
FDCE #(
.INIT(1\'b0))
\\gcc0.gc0.count_d1_reg[1]
(.C(clk),
.CE(I3),
.CLR(AR),
.D(O37[1]),
.Q(Q[1]));
FDCE #(
.INIT(1\'b0))
\\gcc0.gc0.count_d1_reg[2]
(.C(clk),
.CE(I3),
.CLR(AR),
.D(O37[2]),
.Q(Q[2]));
FDCE #(
.INIT(1\'b0))
\\gcc0.gc0.count_d1_reg[3]
(.C(clk),
.CE(I3),
.CLR(AR),
.D(O37[3]),
.Q(Q[3]));
FDCE #(
.INIT(1\'b0))
\\gcc0.gc0.count_d1_reg[4]
(.C(clk),
.CE(I3),
.CLR(AR),
.D(O37[4]),
.Q(Q[4]));
FDCE #(
.INIT(1\'b0))
\\gcc0.gc0.count_d1_reg[5]
(.C(clk),
.CE(I3),
.CLR(AR),
.D(O37[5]),
.Q(Q[5]));
FDCE #(
.INIT(1\'b0))
\\gcc0.gc0.count_d1_reg[6]
(.C(clk),
.CE(I3),
.CLR(AR),
.D(O37[6]),
.Q(Q[6]));
FDCE #(
.INIT(1\'b0))
\\gcc0.gc0.count_d1_reg[7]
(.C(clk),
.CE(I3),
.CLR(AR),
.D(O37[7]),
.Q(Q[7]));
FDCE #(
.INIT(1\'b0))
\\gcc0.gc0.count_d1_reg[8]
(.C(clk),
.CE(I3),
.CLR(AR),
.D(p_9_out),
.Q(Q[8]));
FDPE #(
.INIT(1\'b1))
\\gcc0.gc0.count_reg[0]
(.C(clk),
.CE(I3),
.D(plusOp__0[0]),
.PRE(AR),
.Q(O37[0]));
FDCE #(
.INIT(1\'b0))
\\gcc0.gc0.count_reg[1]
(.C(clk),
.CE(I3),
.CLR(AR),
.D(plusOp__0[1]),
.Q(O37[1]));
FDCE #(
.INIT(1\'b0))
\\gcc0.gc0.count_reg[2]
(.C(clk),
.CE(I3),
.CLR(AR),
.D(plusOp__0[2]),
.Q(O37[2]));
FDCE #(
.INIT(1\'b0))
\\gcc0.gc0.count_reg[3]
(.C(clk),
.CE(I3),
.CLR(AR),
.D(plusOp__0[3]),
.Q(O37[3]));
FDCE #(
.INIT(1\'b0))
\\gcc0.gc0.count_reg[4]
(.C(clk),
.CE(I3),
.CLR(AR),
.D(plusOp__0[4]),
.Q(O37[4]));
FDCE #(
.INIT(1\'b0))
\\gcc0.gc0.count_reg[5]
(.C(clk),
.CE(I3),
.CLR(AR),
.D(plusOp__0[5]),
.Q(O37[5]));
FDCE #(
.INIT(1\'b0))
\\gcc0.gc0.count_reg[6]
(.C(clk),
.CE(I3),
.CLR(AR),
.D(plusOp__0[6]),
.Q(O37[6]));
FDCE #(
.INIT(1\'b0))
\\gcc0.gc0.count_reg[7]
(.C(clk),
.CE(I3),
.CLR(AR),
.D(plusOp__0[7]),
.Q(O37[7]));
FDCE #(
.INIT(1\'b0))
\\gcc0.gc0.count_reg[8]
(.C(clk),
.CE(I3),
.CLR(AR),
.D(plusOp__0[8]),
.Q(p_9_out));
LUT4 #(
.INIT(16\'h9009))
\\gmux.gm[0].gm1.m1_i_1__1
(.I0(Q[1]),
.I1(I2[1]),
.I2(Q[0]),
.I3(I2[0]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16\'h9009))
\\gmux.gm[1].gms.ms_i_1__1
(.I0(Q[3]),
.I1(I2[3]),
.I2(Q[2]),
.I3(I2[2]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16\'h9009))
\\gmux.gm[2].gms.ms_i_1__1
(.I0(Q[5]),
.I1(I2[5]),
.I2(Q[4]),
.I3(I2[4]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16\'h9009))
\\gmux.gm[3].gms.ms_i_1__1
(.I0(Q[7]),
.I1(I2[7]),
.I2(Q[6]),
.I3(I2[6]),
.O(v1_reg[3]));
LUT2 #(
.INIT(4\'h9))
\\gmux.gm[4].gms.ms_i_1
(.I0(Q[8]),
.I1(O4),
.O(O1));
LUT2 #(
.INIT(4\'h9))
\\gmux.gm[4].gms.ms_i_1__1
(.I0(Q[8]),
.I1(O4),
.O(O2));
LUT2 #(
.INIT(4\'h9))
\\gmux.gm[4].gms.ms_i_1__2
(.I0(p_9_out),
.I1(O4),
.O(O3));
LUT6 #(
.INIT(64\'h040404043F0C0C0C))
ram_full_i_i_1
(.I0(comp0),
.I1(I1),
.I2(rst_full_gen_i),
.I3(comp1),
.I4(wr_en),
.I5(E),
.O(ram_full_comb));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module Fifo8xWidthRows_wr_logic
(p_1_out,
full,
Q,
O1,
O2,
O3,
O5,
O6,
O7,
O8,
O9,
O10,
O11,
O12,
O13,
O14,
O15,
O16,
O17,
O18,
O19,
O20,
O21,
O22,
O23,
O24,
O25,
O26,
O27,
O28,
O29,
O30,
O31,
O32,
O33,
O34,
O35,
I4,
v1_reg,
v1_reg_0,
v1_reg_1,
clk,
rst_d2,
O4,
wr_en,
rst_full_gen_i,
E,
p_18_out,
rd_en,
I1,
AR);
output p_1_out;
output full;
output [8:0]Q;
output O1;
output [7:0]O2;
output O3;
output O5;
output O6;
output O7;
output O8;
output O9;
output O10;
output O11;
output O12;
output O13;
output O14;
output O15;
output O16;
output O17;
output O18;
output O19;
output O20;
output O21;
output O22;
output O23;
output O24;
output O25;
output O26;
output O27;
output O28;
output O29;
output O30;
output O31;
output O32;
output O33;
output O34;
output O35;
output [0:0]I4;
output [3:0]v1_reg;
input [3:0]v1_reg_0;
input [3:0]v1_reg_1;
input clk;
input rst_d2;
input [0:0]O4;
input wr_en;
input rst_full_gen_i;
input [0:0]E;
input p_18_out;
input rd_en;
input [7:0]I1;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [7:0]I1;
wire [0:0]I4;
wire O1;
wire O10;
wire O11;
wire O12;
wire O13;
wire O14;
wire O15;
wire O16;
wire O17;
wire O18;
wire O19;
wire [7:0]O2;
wire O20;
wire O21;
wire O22;
wire O23;
wire O24;
wire O25;
wire O26;
wire O27;
wire O28;
wire O29;
wire O3;
wire O30;
wire O31;
wire O32;
wire O33;
wire O34;
wire O35;
wire [0:0]O4;
wire O5;
wire O6;
wire O7;
wire O8;
wire O9;
wire [8:0]Q;
wire clk;
wire comp0;
wire comp1;
wire full;
wire n_0_wpntr;
wire n_11_wpntr;
wire p_18_out;
wire p_1_out;
wire p_4_out;
wire ram_full_comb;
wire rd_en;
wire rst_d2;
wire rst_full_gen_i;
wire [3:0]v1_reg;
wire [3:0]v1_reg_0;
wire [3:0]v1_reg_1;
wire wr_en;
Fifo8xWidthRows_wr_status_flags_ss \\gwss.wsts
(.E(p_4_out),
.I1(n_0_wpntr),
.I2(n_11_wpntr),
.I4(I4),
.O1(p_1_out),
.clk(clk),
.comp0(comp0),
.comp1(comp1),
.full(full),
.p_18_out(p_18_out),
.ram_full_comb(ram_full_comb),
.rd_en(rd_en),
.rst_d2(rst_d2),
.v1_reg_0(v1_reg_0),
.v1_reg_1(v1_reg_1),
.wr_en(wr_en));
Fifo8xWidthRows_wr_bin_cntr wpntr
(.AR(AR),
.E(E),
.I1(p_1_out),
.I2(I1),
.I3(p_4_out),
.O1(n_0_wpntr),
.O10(O9),
.O11(O10),
.O12(O11),
.O13(O12),
.O14(O13),
.O15(O14),
.O16(O15),
.O17(O16),
.O18(O17),
.O19(O18),
.O2(O1),
.O20(O19),
.O21(O20),
.O22(O21),
.O23(O22),
.O24(O23),
.O25(O24),
.O26(O25),
.O27(O26),
.O28(O27),
.O29(O28),
.O3(n_11_wpntr),
.O30(O29),
.O31(O30),
.O32(O31),
.O33(O32),
.O34(O33),
.O35(O34),
.O36(O35),
.O37(O2),
.O4(O4),
.O5(O3),
.O6(O5),
.O7(O6),
.O8(O7),
.O9(O8),
.Q(Q),
.clk(clk),
.comp0(comp0),
.comp1(comp1),
.ram_full_comb(ram_full_comb),
.rst_full_gen_i(rst_full_gen_i),
.v1_reg(v1_reg),
.wr_en(wr_en));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_ss" *)
module Fifo8xWidthRows_wr_status_flags_ss
(comp0,
comp1,
O1,
full,
I4,
E,
v1_reg_0,
I1,
v1_reg_1,
I2,
ram_full_comb,
clk,
rst_d2,
wr_en,
p_18_out,
rd_en);
output comp0;
output comp1;
output O1;
output full;
output [0:0]I4;
output [0:0]E;
input [3:0]v1_reg_0;
input I1;
input [3:0]v1_reg_1;
input I2;
input ram_full_comb;
input clk;
input rst_d2;
input wr_en;
input p_18_out;
input rd_en;
wire [0:0]E;
wire I1;
wire I2;
wire [0:0]I4;
wire O1;
wire clk;
wire comp0;
wire comp1;
wire full;
wire p_18_out;
wire ram_full_comb;
wire rd_en;
wire rst_d2;
wire [3:0]v1_reg_0;
wire [3:0]v1_reg_1;
wire wr_en;
Fifo8xWidthRows_compare c0
(.I1(I1),
.comp0(comp0),
.v1_reg_0(v1_reg_0));
Fifo8xWidthRows_compare_0 c1
(.I2(I2),
.comp1(comp1),
.v1_reg_1(v1_reg_1));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16\'h4B44))
\\count[8]_i_1
(.I0(O1),
.I1(wr_en),
.I2(p_18_out),
.I3(rd_en),
.O(I4));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4\'h2))
\\gcc0.gc0.count_d1[8]_i_1
(.I0(wr_en),
.I1(O1),
.O(E));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1\'b1))
ram_full_fb_i_reg
(.C(clk),
.CE(1\'b1),
.D(ram_full_comb),
.PRE(rst_d2),
.Q(O1));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1\'b1))
ram_full_i_reg
(.C(clk),
.CE(1\'b1),
.D(ram_full_comb),
.PRE(rst_d2),
.Q(full));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1\'bz;
reg JTAG_USER_TDO2_GLBL = 1\'bz;
reg JTAG_USER_TDO3_GLBL = 1\'bz;
reg JTAG_USER_TDO4_GLBL = 1\'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1\'b1;
\tPRLD_int = 1\'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1\'b0;
\tPRLD_int = 1\'b0;
end
initial begin
\tGTS_int = 1\'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1\'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: None
// Engineer: Dai Tianyu (dtysky)
//
// Create Date: 2015/04/07 18:01:07
// Design Name:
// Module Name: Mux2
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependenrgb24es:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Mux2(sel, i0, i1, o);
\tparameter data_width = 8;
\tinput sel;
\tinput[data_width - 1 : 0] i0;
\tinput[data_width - 1 : 0] i1;
\toutput[data_width - 1 : 0] o;
\tassign o = sel == 0 ? i0 : i1;
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
// Date : Mon May 25 17:58:01 2015
// Host : Dtysky running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// b:/Complex_Mind/FPGA-Imaging-Library/Master/Generator/FrameController2/HDL/FrameController2.srcs/sources_1/ip/Multiplier12x12FR2/Multiplier12x12FR2_funcsim.v
// Design : Multiplier12x12FR2
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "mult_gen_v12_0,Vivado 2014.4" *) (* CHECK_LICENSE_TYPE = "Multiplier12x12FR2,mult_gen_v12_0,{}" *)
(* core_generation_info = "Multiplier12x12FR2,mult_gen_v12_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=zynq,C_HAS_CE=0,C_HAS_SCLR=1,C_LATENCY=3,C_A_WIDTH=12,C_A_TYPE=1,C_B_WIDTH=12,C_B_TYPE=1,C_OUT_HIGH=23,C_OUT_LOW=0,C_MULT_TYPE=1,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}" *)
(* NotValidForBitStream *)
module Multiplier12x12FR2
(CLK,
A,
B,
SCLR,
P);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) input CLK;
input [11:0]A;
input [11:0]B;
(* x_interface_info = "xilinx.com:signal:reset:1.0 sclr_intf RST" *) input SCLR;
output [23:0]P;
wire [11:0]A;
wire [11:0]B;
wire CLK;
wire [23:0]P;
wire SCLR;
wire [47:0]NLW_U0_PCASC_UNCONNECTED;
wire [1:0]NLW_U0_ZERO_DETECT_UNCONNECTED;
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "12" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "12" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "3" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "1" *)
(* C_OPTIMIZE_GOAL = "1" *)
(* C_OUT_HIGH = "23" *)
(* C_OUT_LOW = "0" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* DONT_TOUCH *)
(* downgradeipidentifiedwarnings = "yes" *)
Multiplier12x12FR2_mult_gen_v12_0__parameterized0 U0
(.A(A),
.B(B),
.CE(1\'b1),
.CLK(CLK),
.P(P),
.PCASC(NLW_U0_PCASC_UNCONNECTED[47:0]),
.SCLR(SCLR),
.ZERO_DETECT(NLW_U0_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule
(* ORIG_REF_NAME = "mult_gen_v12_0" *) (* C_VERBOSITY = "0" *) (* C_MODEL_TYPE = "0" *)
(* C_OPTIMIZE_GOAL = "1" *) (* C_XDEVICEFAMILY = "zynq" *) (* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *) (* C_LATENCY = "3" *) (* C_A_WIDTH = "12" *)
(* C_A_TYPE = "1" *) (* C_B_WIDTH = "12" *) (* C_B_TYPE = "1" *)
(* C_OUT_HIGH = "23" *) (* C_OUT_LOW = "0" *) (* C_MULT_TYPE = "1" *)
(* C_CE_OVERRIDES_SCLR = "0" *) (* C_CCM_IMP = "0" *) (* C_B_VALUE = "10000001" *)
(* C_HAS_ZERO_DETECT = "0" *) (* C_ROUND_OUTPUT = "0" *) (* C_ROUND_PT = "0" *)
(* downgradeipidentifiedwarnings = "yes" *)
module Multiplier12x12FR2_mult_gen_v12_0__parameterized0
(CLK,
A,
B,
CE,
SCLR,
ZERO_DETECT,
P,
PCASC);
input CLK;
input [11:0]A;
input [11:0]B;
input CE;
input SCLR;
output [1:0]ZERO_DETECT;
output [23:0]P;
output [47:0]PCASC;
wire [11:0]A;
wire [11:0]B;
wire CE;
wire CLK;
wire [23:0]P;
wire [47:0]PCASC;
wire SCLR;
wire [1:0]ZERO_DETECT;
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "12" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "12" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "3" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "1" *)
(* C_OPTIMIZE_GOAL = "1" *)
(* C_OUT_HIGH = "23" *)
(* C_OUT_LOW = "0" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* downgradeipidentifiedwarnings = "yes" *)
Multiplier12x12FR2_mult_gen_v12_0_viv__parameterized0 i_mult
(.A(A),
.B(B),
.CE(CE),
.CLK(CLK),
.P(P),
.PCASC(PCASC),
.SCLR(SCLR),
.ZERO_DETECT(ZERO_DETECT));
endmodule
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`pragma protect key_block
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7328)
`pragma protect data_block
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`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: None
// Engineer: Dai Tianyu (dtysky)
//
// Create Date: 2015/04/07 18:01:07
// Design Name: DataDelay
// Module Name: DataDelay
// Project Name: Image processing project
// Target Devices:
// Tool Versions:
// Description:
//
// Dependenrgb24es:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DataDelay(clk, in_data, out_data);
\tparameter data_width = 8;
\tparameter delay = 1;
\tinput clk;
\tinput[data_width - 1 : 0] in_data;
\toutput[data_width - 1 : 0] out_data;
\tgenvar i;
\tgenerate
\t\tfor (i = 0; i < delay; i = i + 1) begin : pip
\t\t\treg[data_width - 1 : 0] tmp;
\t\t\tif(i == 0) begin
\t\t\t\talways @(posedge clk)
\t\t\t\t\ttmp <= in_data;
\t\t\tend else begin
\t\t\t\talways @(posedge clk)
\t\t\t\t\ttmp <= pip[i - 1].tmp;
\t\t\tend
\t\tend
\t\tassign out_data = pip[delay - 1].tmp;
\tendgenerate
\t
endmodule
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
Shear
:Function
Shearing an image by your given sh.
Give the first output after 1 cycle while the frame input ready.
:Module
Main module
:Version
1.0
:Modified
2015-05-28
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module Shear(
\tclk,
\trst_n,
\tsh_u,
\tsh_v,
\tin_enable,
\tframe_in_ready,
\tframe_in_data,
\tframe_enable,
\tframe_out_count_x,
\tframe_out_count_y,
\tout_ready,
\tout_data);
\t/*
\t::description
\tThis module\'s working mode.
\t::range
\t0 for Pipline, 1 for Req-ack
\t*/
\tparameter work_mode = 0;
\t/*
\t::description
\tData bit width.
\t*/
\tparameter data_width = 8;
\t/*
\t::description
\tWidth of image.
\t::range
\t1 - 4096
\t*/
\tparameter im_width = 320;
\t/*
\t::description
\tHeight of image.
\t::range
\t1 - 4096
\t*/
\tparameter im_height = 240;
\t/*
\t::description
\tThe bits of width of image.
\t::range
\tDepend on width of image
\t*/
\tparameter im_width_bits = 9;
\t/*
\t::description
\tDelay for multiplier.
\t::range
\tDepend on your multilpliers\' configurations, 1 - 14
\t*/
\tparameter mul_delay = 3;
\t/*
\t::description
\tDelay for FrameController.
\t::range
\tDepend on your FrameController
\t*/
\tparameter ram_RL = 7;
\t/*
\t::description
\tClock.
\t*/
\tinput clk;
\t/*
\t::description
\tReset, active low.
\t*/
\tinput rst_n;
\t/*
\t::description
\tSh for horizontal.
\t::range
\tFixed number, 13bits.12bits
\t*/
\tinput signed[24 : 0] sh_u;
\t/*
\t::description
\tSh for vertical.
\t::range
\tFixed number, 13bits.12bits
\t*/
\tinput signed[24 : 0] sh_v;
\t/*
\t::description
\tInput data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
\t*/
\tinput in_enable;
\t/*
\t::description
\tConnect to out_ready in FrameController.
\t*/
\tinput frame_in_ready;
\t/*
\t::description
\tConnect to out_data in FrameController.
\t*/
\tinput[data_width - 1 : 0] frame_in_data;
\t/*
\t::description
\tConnect to in_enable in FrameController.
\t*/
\toutput frame_enable;
\t/*
\t::description
\tConnect to in_count_u in FrameController.
\t*/
\toutput[im_width_bits - 1 : 0] frame_out_count_x;
\t/*
\t::description
\tConnect to in_count_v in FrameController.
\t*/
\toutput[im_width_bits - 1 : 0] frame_out_count_y;
\t/*
\t::description
\tOutput data ready, in both two mode, it will be high while the out_data can be read.
\t*/
\toutput out_ready;
\t/*
\t::description
\tOutput data, it will be synchronous with out_ready.
\t*/
\toutput[data_width - 1 : 0] out_data;
\treg reg_out_ready;
\treg in_range_t, in_range_b, in_range_l, in_range_r;
\twire signed[36 : 0] mul_u_p, mul_v_p;
\twire signed[im_width_bits : 0] mul_u_r, mul_v_r;
\treg signed[im_width_bits + 1 : 0] reg_frame_out_count_x, reg_frame_out_count_y;
\treg[3 : 0] con_mul_enable;
\treg[data_width - 1 : 0] reg_out_data;
\twire[im_width_bits - 1 : 0] count_u, count_v;
\tgenerate
\t\tif(work_mode == 0) begin
\t\t\treg [im_width_bits - 1 : 0] reg_count_u, reg_count_v;
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\treg_count_u <= 0;
\t\t\t\telse if(reg_count_u == im_width - 1)
\t\t\t\t\treg_count_u <= 0;
\t\t\t\telse
\t\t\t\t\treg_count_u <= reg_count_u + 1;
\t\t\tend
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\treg_count_v <= 0;
\t\t\t\telse if(reg_count_u == im_width - 1 && reg_count_v == im_height - 1)
\t\t\t\t\treg_count_v <= 0;
\t\t\t\telse if(reg_count_u == im_width - 1)
\t\t\t\t\treg_count_v <= reg_count_v + 1;
\t\t\t\telse
\t\t\t\t\treg_count_v <= reg_count_v;
\t\t\tend
\t\t\tassign count_u = reg_count_u;
\t\t\tassign count_v = reg_count_v;
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\tcon_mul_enable <= 0;
\t\t\t\telse if(con_mul_enable == mul_delay + 4)
\t\t\t\t\tcon_mul_enable <= con_mul_enable;
\t\t\t\telse
\t\t\t\t\tcon_mul_enable <= con_mul_enable + 1;
\t\t\tend
\t\t\tassign frame_enable = con_mul_enable == mul_delay + 4 ? 1 : 0;
\t\tend else begin
\t\t\treg signed [im_width_bits : 0] reg_count_u, reg_count_v;
\t\t\treg in_enable_last;
\t\t\talways @(posedge clk)
\t\t\t\tin_enable_last <= in_enable;
\t\t\talways @(posedge clk or negedge rst_n) begin
\t\t\t\tif(~rst_n)
\t\t\t\t\treg_count_u <= -1;
\t\t\t\telse if(~in_enable_last & in_enable) begin
\t\t\t\t\tif(reg_count_u == im_width - 1)
\t\t\t\t\t\treg_count_u <= 0;
\t\t\t\t\telse
\t\t\t\t\t\treg_count_u <= reg_count_u + 1;
\t\t\t\tend else
\t\t\t\t\treg_count_u <= reg_count_u;
\t\t\tend
\t\t\talways @(posedge clk or negedge rst_n) begin
\t\t\t\tif(~rst_n)
\t\t\t\t\treg_count_v <= 0;
\t\t\t\telse if(~in_enable_last & in_enable) begin
\t\t\t\t\tif(reg_count_u == im_width - 1 && reg_count_v == im_height - 1)
\t\t\t\t\t\treg_count_v <= 0;
\t\t\t\t\telse if(reg_count_u == im_width - 1)
\t\t\t\t\t\treg_count_v <= reg_count_v + 1;
\t\t\t\t\telse
\t\t\t\t\t\treg_count_v <= reg_count_v;
\t\t\t\tend\telse
\t\t\t\t\treg_count_v <= reg_count_v;
\t\t\tend
\t\t\tassign count_u = reg_count_u[im_width_bits - 1 : 0];
\t\t\tassign count_v = reg_count_v[im_width_bits - 1 : 0];
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\tcon_mul_enable <= 0;
\t\t\t\telse if(con_mul_enable == mul_delay + 5)
\t\t\t\t\tcon_mul_enable <= con_mul_enable;
\t\t\t\telse
\t\t\t\t\tcon_mul_enable <= con_mul_enable + 1;
\t\t\tend
\t\t\tassign frame_enable = con_mul_enable == mul_delay + 5 ? 1 : 0;
\t\tend
\t\t/*
\t\t::description
\t\tMultiplier for Unsigned 12bits x Signed 25bits, used for fixed multiplication.
\t\tYou can configure the multiplier by yourself, then change the "mul_delay".
\t\tAll Multiplier\'s pipeline stage must be same, you can not change the ports\' configurations!
\t\t*/
\t\tMultiplier12x25SSHR MulU(.CLK(clk), .A({{12 - im_width_bits{1\'b0}}, count_u}), .B(sh_u), .SCLR(~rst_n), .P(mul_u_p));
\t\t/*
\t\t::description
\t\tMultiplier for Unsigned 12bits x Signed 25bits, used for fixed multiplication.
\t\tYou can configure the multiplier by yourself, then change the "mul_delay".
\t\tAll Multiplier\'s pipeline stage must be same, you can not change the ports\' configurations!
\t\t*/
\t\tMultiplier12x25SSHR MulV(.CLK(clk), .A({{12 - im_width_bits{1\'b0}}, count_v}), .B(sh_v), .SCLR(~rst_n), .P(mul_v_p));
\t\twire overflow_u0, overflow_v0;
\t\t/*
\t\t::description
\t\tFor rounding signed fixed number.
\t\t*/
\t\tFixedRoundSigned1 #(37, 18, im_width_bits) FRSU(clk, mul_u_p, mul_u_r, overflow_u0);
\t\t/*
\t\t::description
\t\tFor rounding signed fixed number.
\t\t*/
\t\tFixedRoundSigned1 #(37, 18, im_width_bits) FRSV(clk, mul_v_p, mul_v_r, overflow_v0);
\t\tif(work_mode == 0) begin
\t\t\tgenvar i;
\t\t\tfor (i = 0; i < mul_delay + 3; i = i + 1) begin : count_buffer
\t\t\t\treg signed [im_width_bits : 0] u, v;
\t\t\t\tif(i == 0) begin
\t\t\t\t\talways @(posedge clk) begin
\t\t\t\t\t\tu <= {1\'b0, count_u};
\t\t\t\t\t\tv <= {1\'b0, count_v};
\t\t\t\t\tend
\t\t\t\tend else begin
\t\t\t\t\talways @(posedge clk) begin
\t\t\t\t\t\tu <= count_buffer[i - 1].u;
\t\t\t\t\t\tv <= count_buffer[i - 1].v;
\t\t\t\t\tend
\t\t\t\tend
\t\t\tend
\t\t\treg not_overflow_u, not_overflow_v;
\t\t\talways @(posedge clk) begin
\t\t\t\treg_frame_out_count_x <= count_buffer[mul_delay + 2].u + mul_v_r;
\t\t\t\treg_frame_out_count_y <= count_buffer[mul_delay + 2].v + mul_u_r;
\t\t\t\tnot_overflow_u <= ~overflow_u0;
\t\t\t\tnot_overflow_v <= ~overflow_v0;
\t\t\tend
\t\t\tfor (i = 0; i < ram_RL - 1; i = i + 1) begin : buffer
\t\t\t\treg tmp_t, tmp_b, tmp_l, tmp_r, overflow_u, overflow_v;
\t\t\t\tif(i == 0) begin
\t\t\t\t\talways @(posedge clk) begin
\t\t\t\t\t\ttmp_t <= reg_frame_out_count_x[im_width_bits + 1] == 0 ? 1 : 0;
\t\t\t\t\t\ttmp_b <= reg_frame_out_count_x < im_width ? 1 : 0;
\t\t\t\t\t\ttmp_l <= reg_frame_out_count_y[im_width_bits + 1] == 0 ? 1 : 0;
\t\t\t\t\t\ttmp_r <= reg_frame_out_count_y < im_height ? 1 : 0;
\t\t\t\t\t\toverflow_u <= not_overflow_u;
\t\t\t\t\t\toverflow_v <= not_overflow_v;
\t\t\t\t\tend
\t\t\t\tend else begin
\t\t\t\t\talways @(posedge clk) begin
\t\t\t\t\t\ttmp_t <= buffer[i - 1].tmp_t;
\t\t\t\t\t\ttmp_b <= buffer[i - 1].tmp_b;
\t\t\t\t\t\ttmp_l <= buffer[i - 1].tmp_l;
\t\t\t\t\t\ttmp_r <= buffer[i - 1].tmp_r;
\t\t\t\t\t\toverflow_u <= buffer[i - 1].overflow_u;
\t\t\t\t\t\toverflow_v <= buffer[i - 1].overflow_v;
\t\t\t\t\tend
\t\t\t\tend
\t\t\tend
\t\t\talways @(posedge clk or negedge rst_n or negedge frame_in_ready) begin
\t\t\t\tif(~rst_n || ~frame_in_ready) begin
\t\t\t\t\treg_out_ready <= 0;
\t\t\t\t\tin_range_t <= 0;
\t\t\t\t\tin_range_b <= 0;
\t\t\t\t\tin_range_l <= 0;
\t\t\t\t\tin_range_r <= 0;
\t\t\t\t\treg_out_data <= 0;
\t\t\t\tend else begin
\t\t\t\t\treg_out_ready <= 1;
\t\t\t\t\tin_range_t <= buffer[ram_RL - 2].tmp_t;
\t\t\t\t\tin_range_b <= buffer[ram_RL - 2].tmp_b & buffer[ram_RL - 2].overflow_v;
\t\t\t\t\tin_range_l <= buffer[ram_RL - 2].tmp_l;
\t\t\t\t\tin_range_r <= buffer[ram_RL - 2].tmp_r & buffer[ram_RL - 2].overflow_u;
\t\t\t\t\treg_out_data <= frame_in_data;
\t\t\t\tend
\t\t\tend
\t\tend else begin
\t\t\talways @(posedge clk) begin
\t\t\t\treg_frame_out_count_x <= $signed({1\'b0, count_u}) + mul_v_r;
\t\t\t\treg_frame_out_count_y <= $signed({1\'b0, count_v}) + mul_u_r;
\t\t\tend
\t\t\treg tmp_t, tmp_b, tmp_l, tmp_r;
\t\t\treg not_overflow_u, not_overflow_v;
\t\t\talways @(posedge clk) begin
\t\t\t\ttmp_t <= reg_frame_out_count_x[im_width_bits + 1] == 0 ? 1 : 0;
\t\t\t\ttmp_b <= reg_frame_out_count_x < im_width ? 1 : 0;
\t\t\t\ttmp_l <= reg_frame_out_count_y[im_width_bits + 1] == 0 ? 1 : 0;
\t\t\t\ttmp_r <= reg_frame_out_count_y < im_height ? 1 : 0;
\t\t\t\tnot_overflow_u <= ~overflow_u0;
\t\t\t\tnot_overflow_v <= ~overflow_v0;
\t\t\tend
\t\t\talways @(posedge clk or negedge rst_n or negedge frame_in_ready) begin
\t\t\t\tif(~rst_n || ~frame_in_ready) begin
\t\t\t\t\treg_out_ready <= 0;
\t\t\t\t\treg_out_data <= 0;
\t\t\t\t\tin_range_t <= 0;
\t\t\t\t\tin_range_b <= 0;
\t\t\t\t\tin_range_l <= 0;
\t\t\t\t\tin_range_r <= 0;
\t\t\t\tend else begin
\t\t\t\t\treg_out_ready <= 1;
\t\t\t\t\treg_out_data <= frame_in_data;
\t\t\t\t\tin_range_t <= tmp_t;
\t\t\t\t\tin_range_b <= tmp_b & not_overflow_v;
\t\t\t\t\tin_range_l <= tmp_l;
\t\t\t\t\tin_range_r <= tmp_r & not_overflow_u;
\t\t\t\tend
\t\t\tend
\t\tend
\t\tassign frame_out_count_x = reg_frame_out_count_x[im_width_bits - 1 : 0];
\t\tassign frame_out_count_y = reg_frame_out_count_y[im_width_bits - 1 : 0];
\t\tassign out_ready = reg_out_ready;
\t\tassign out_data = out_ready & in_range_t & in_range_b & in_range_l & in_range_r ? reg_out_data : 0;
\tendgenerate
endmodule
|
`timescale 1 ps / 1 ps
module BRam8x512x512(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb);
input clka;
input [0:0]wea;
input [17:0]addra;
input [7:0]dina;
input clkb;
input [17:0]addrb;
output reg [7:0]doutb;
reg[7 : 0] mem[0 : 2 ** 18 - 1];
always @(posedge clka) begin
if(wea)
mem[addra] <= dina;
else
mem[addra] <= mem[addra];
end
always @(posedge clkb)
doutb <= mem[addrb];
endmodule
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
Rotate
:Function
Function: Rotating an image by your given angle.
Give the first output after 1 cycle while the frame input ready.
:Module
Main module
:Version
1.0
:Modified
2015-05-28
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
`define im_width_half im_width / 2
`define im_height_half im_height / 2
module Rotate(
\tclk,
\trst_n,
\tangle,
\tin_enable,
\tframe_in_ready,
\tframe_in_data,
\tframe_enable,
\tframe_out_count_x,
\tframe_out_count_y,
\tout_ready,
\tout_data);
\t/*
\t::description
\tThis module\'s working mode.
\t::range
\t0 for Pipline, 1 for Req-ack
\t*/
\tparameter work_mode = 0;
\t/*
\t::description
\tData bit width.
\t*/
\tparameter data_width = 8;
\t/*
\t::description
\tWidth of image.
\t::range
\t1 - 4096
\t*/
\tparameter signed[11 : 0] im_width = 320;
\t/*
\t::description
\tHeight of image.
\t::range
\t1 - 4096
\t*/
\tparameter signed[11 : 0] im_height = 240;
\t/*
\t::description
\tThe bits of width of image.
\t::range
\tDepend on width of image
\t*/
\tparameter im_width_bits = 9;
\t/*
\t::description
\tDelay for multiplier.
\t::range
\tDepend on your multilpliers\' configurations, 1 - 14
\t*/
\tparameter mul_delay = 3;
\t/*
\t::description
\tDelay for FrameController.
\t::range
\tDepend on your FrameController
\t*/
\tparameter ram_RL = 7;
\t/*
\t::description
\tClock.
\t*/
\tinput clk;
\t/*
\t::description
\tReset, active low.
\t*/
\tinput rst_n;
\t/*
\t::description
\tAngle.
\t::range
\t0 - 359
\t*/
\tinput[8 : 0] angle;
\t/*
\t::description
\tInput data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
\t*/
\tinput in_enable;
\t/*
\t::description
\tConnect to out_ready in FrameController.
\t*/
\tinput frame_in_ready;
\t/*
\t::description
\tConnect to out_data in FrameController.
\t*/
\tinput[data_width - 1 : 0] frame_in_data;
\t/*
\t::description
\tConnect to in_enable in FrameController.
\t*/
\toutput frame_enable;
\t/*
\t::description
\tConnect to in_count_u in FrameController.
\t*/
\toutput[im_width_bits - 1 : 0] frame_out_count_x;
\t/*
\t::description
\tConnect to in_count_v in FrameController.
\t*/
\toutput[im_width_bits - 1 : 0] frame_out_count_y;
\t/*
\t::description
\tOutput data ready, in both two mode, it will be high while the out_data can be read.
\t*/
\toutput out_ready;
\t/*
\t::description
\tOutput data, it will be synchronous with out_ready.
\t*/
\toutput[data_width - 1 : 0] out_data;
\twire signed[19 : 0] sina, cosa;
\treg signed[im_width_bits : 0] count_u, count_v;
\treg in_range_t, in_range_b, in_range_l, in_range_r;
\twire signed [32 : 0] mul_x_p1, mul_x_p2, mul_y_p1, mul_y_p2;
\treg signed [12 : 0] mul_x_a1, mul_x_a2, mul_y_a1, mul_y_a2;
\twire signed [im_width_bits : 0] mul_x_r1, mul_x_r2, mul_y_r1, mul_y_r2;
\treg signed [im_width_bits + 1 : 0] add_x, add_y;
\treg signed[im_width_bits + 1 : 0] reg_frame_out_count_x, reg_frame_out_count_y;
\treg[3 : 0] con_mul_enable;
\treg reg_out_ready;
\treg[data_width - 1 : 0] reg_out_data;
\tgenerate
\t\tif(work_mode == 0) begin
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\tcount_u <= 0;
\t\t\t\telse if(count_u == im_width - 1)
\t\t\t\t\tcount_u <= 0;
\t\t\t\telse
\t\t\t\t\tcount_u <= count_u + 1;
\t\t\tend
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\tcount_v <= 0;
\t\t\t\telse if(count_u == im_width - 1 && count_v == im_height - 1)
\t\t\t\t\tcount_v <= 0;
\t\t\t\telse if(count_u == im_width - 1)
\t\t\t\t\tcount_v <= count_v + 1;
\t\t\t\telse
\t\t\t\t\tcount_v <= count_v;
\t\t\tend
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\tcon_mul_enable <= 0;
\t\t\t\telse if(con_mul_enable == mul_delay + 6)
\t\t\t\t\tcon_mul_enable <= con_mul_enable;
\t\t\t\telse
\t\t\t\t\tcon_mul_enable <= con_mul_enable + 1;
\t\t\tend
\t\t\tassign frame_enable = con_mul_enable == mul_delay + 6 ? 1 : 0;
\t\tend else begin
\t\t\treg in_enable_last;
\t\t\talways @(posedge clk)
\t\t\t\tin_enable_last <= in_enable;
\t\t\talways @(posedge clk or negedge rst_n) begin
\t\t\t\tif(~rst_n)
\t\t\t\t\tcount_u <= -1;
\t\t\t\telse if(~in_enable_last & in_enable) begin
\t\t\t\t\tif(count_u == im_width - 1)
\t\t\t\t\t\tcount_u <= 0;
\t\t\t\t\telse
\t\t\t\t\t\tcount_u <= count_u + 1;
\t\t\t\tend else
\t\t\t\t\tcount_u <= count_u;
\t\t\tend
\t\t\talways @(posedge clk or negedge rst_n) begin
\t\t\t\tif(~rst_n)
\t\t\t\t\tcount_v <= 0;
\t\t\t\telse if(~in_enable_last & in_enable) begin
\t\t\t\t\tif(count_u == im_width - 1 && count_v == im_height - 1)
\t\t\t\t\t\tcount_v <= 0;
\t\t\t\t\telse if(count_u == im_width - 1)
\t\t\t\t\t\tcount_v <= count_v + 1;
\t\t\t\t\telse
\t\t\t\t\t\tcount_v <= count_v;
\t\t\t\tend\telse
\t\t\t\t\tcount_v <= count_v;
\t\t\tend
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\tcon_mul_enable <= 0;
\t\t\t\telse if(con_mul_enable == mul_delay + 7)
\t\t\t\t\tcon_mul_enable <= con_mul_enable;
\t\t\t\telse
\t\t\t\t\tcon_mul_enable <= con_mul_enable + 1;
\t\t\tend
\t\t\tassign frame_enable = con_mul_enable == mul_delay + 7 ? 1 : 0;
\t\tend
\t\t/*
\t\t::description
\t\tGetting sine of angle.
\t\t*/
\t\tSinLUT Sin(angle, sina);
\t\t/*
\t\t::description
\t\tGetting cosine of angle.
\t\t*/
\t\tCosLUT Cos(angle, cosa);
\t\talways @(posedge clk) begin
\t\t\tmul_x_a1 <= count_u - `im_width_half;
\t\t\tmul_x_a2 <= count_v - `im_height_half;
\t\t\tmul_y_a1 <= `im_width_half - count_u;
\t\t\tmul_y_a2 <= count_v - `im_height_half;
\t\tend
\t\t/*
\t\t::description
\t\tMultiplier for Unsigned 12bits x Signed 25bits, used for fixed multiplication.
\t\tYou can configure the multiplier by yourself, then change the "mul_delay".
\t\tAll Multiplier\'s pipeline stage must be same, you can not change the ports\' configurations!
\t\t*/
\t\tMultiplier13Sx20SRTT MulX1(.CLK(clk), .A(mul_x_a1), .B(cosa), .SCLR(~rst_n), .P(mul_x_p1));
\t\t/*
\t\t::description
\t\tMultiplier for Unsigned 12bits x Signed 25bits, used for fixed multiplication.
\t\tYou can configure the multiplier by yourself, then change the "mul_delay".
\t\tAll Multiplier\'s pipeline stage must be same, you can not change the ports\' configurations!
\t\t*/
\t\tMultiplier13Sx20SRTT MulX2(.CLK(clk), .A(mul_x_a2), .B(sina), .SCLR(~rst_n), .P(mul_x_p2));
\t\t/*
\t\t::description
\t\tMultiplier for Unsigned 12bits x Signed 25bits, used for fixed multiplication.
\t\tYou can configure the multiplier by yourself, then change the "mul_delay".
\t\tAll Multiplier\'s pipeline stage must be same, you can not change the ports\' configurations!
\t\t*/
\t\tMultiplier13Sx20SRTT MulY1(.CLK(clk), .A(mul_y_a1), .B(sina), .SCLR(~rst_n), .P(mul_y_p1));
\t\t/*
\t\t::description
\t\tMultiplier for Unsigned 12bits x Signed 25bits, used for fixed multiplication.
\t\tYou can configure the multiplier by yourself, then change the "mul_delay".
\t\tAll Multiplier\'s pipeline stage must be same, you can not change the ports\' configurations!
\t\t*/
\t\tMultiplier13Sx20SRTT MulY2(.CLK(clk), .A(mul_y_a2), .B(cosa), .SCLR(~rst_n), .P(mul_y_p2));
\t\t/*
\t\t::description
\t\tFor rounding signed fixed number.
\t\t*/
\t\tFixedRoundSigned2 #(33, 18, im_width_bits) FRSX1(clk, mul_x_p1, mul_x_r1);
\t\t/*
\t\t::description
\t\tFor rounding signed fixed number.
\t\t*/
\t\tFixedRoundSigned2 #(33, 18, im_width_bits) FRSX2(clk, mul_x_p2, mul_x_r2);
\t\t/*
\t\t::description
\t\tFor rounding signed fixed number.
\t\t*/
\t\tFixedRoundSigned2 #(33, 18, im_width_bits) FRSY1(clk, mul_y_p1, mul_y_r1);
\t\t/*
\t\t::description
\t\tFor rounding signed fixed number.
\t\t*/
\t\tFixedRoundSigned2 #(33, 18, im_width_bits) FRSY2(clk, mul_y_p2, mul_y_r2);
\t\talways @(posedge clk) begin
\t\t\tadd_x <= mul_x_r1 + mul_x_r2;
\t\t\tadd_y <= mul_y_r1 + mul_y_r2;
\t\t\treg_frame_out_count_x <= add_x + `im_width_half;
\t\t\treg_frame_out_count_y <= add_y + `im_height_half;
\t\tend
\t\tassign frame_out_count_x = reg_frame_out_count_x[im_width_bits - 1 : 0];
\t\tassign frame_out_count_y = reg_frame_out_count_y[im_width_bits - 1 : 0];
\t\tif(work_mode == 0) begin
\t\t\tgenvar i;
\t\t\tfor (i = 0; i < ram_RL - 1; i = i + 1) begin : buffer
\t\t\t\treg tmp_t, tmp_b, tmp_l, tmp_r;
\t\t\t\tif(i == 0) begin
\t\t\t\t\talways @(posedge clk) begin
\t\t\t\t\t\ttmp_t <= reg_frame_out_count_x[im_width_bits + 1] == 0 ? 1 : 0;
\t\t\t\t\t\ttmp_b <= reg_frame_out_count_x < im_width ? 1 : 0;
\t\t\t\t\t\ttmp_l <= reg_frame_out_count_y[im_width_bits + 1] == 0 ? 1 : 0;
\t\t\t\t\t\ttmp_r <= reg_frame_out_count_y < im_height ? 1 : 0;
\t\t\t\t\tend
\t\t\t\tend else begin
\t\t\t\t\talways @(posedge clk) begin
\t\t\t\t\t\ttmp_t <= buffer[i - 1].tmp_t;
\t\t\t\t\t\ttmp_b <= buffer[i - 1].tmp_b;
\t\t\t\t\t\ttmp_l <= buffer[i - 1].tmp_l;
\t\t\t\t\t\ttmp_r <= buffer[i - 1].tmp_r;
\t\t\t\t\tend
\t\t\t\tend
\t\t\tend
\t\t\talways @(posedge clk or negedge rst_n or negedge frame_in_ready) begin
\t\t\t\tif(~rst_n || ~frame_in_ready) begin
\t\t\t\t\treg_out_ready <= 0;
\t\t\t\t\tin_range_t <= 0;
\t\t\t\t\tin_range_b <= 0;
\t\t\t\t\tin_range_l <= 0;
\t\t\t\t\tin_range_r <= 0;
\t\t\t\t\treg_out_data <= 0;
\t\t\t\tend else begin
\t\t\t\t\treg_out_ready <= 1;
\t\t\t\t\tin_range_t <= buffer[ram_RL - 2].tmp_t;
\t\t\t\t\tin_range_b <= buffer[ram_RL - 2].tmp_b;
\t\t\t\t\tin_range_l <= buffer[ram_RL - 2].tmp_l;
\t\t\t\t\tin_range_r <= buffer[ram_RL - 2].tmp_r;
\t\t\t\t\treg_out_data <= frame_in_data;
\t\t\t\tend
\t\t\tend
\t\tend else begin
\t\t\treg tmp_t, tmp_b, tmp_l, tmp_r;
\t\t\talways @(posedge clk) begin
\t\t\t\ttmp_t <= reg_frame_out_count_x[im_width_bits + 1] == 0 ? 1 : 0;
\t\t\t\ttmp_b <= reg_frame_out_count_x < im_width ? 1 : 0;
\t\t\t\ttmp_l <= reg_frame_out_count_y[im_width_bits + 1] == 0 ? 1 : 0;
\t\t\t\ttmp_r <= reg_frame_out_count_y < im_height ? 1 : 0;
\t\t\tend
\t\t\talways @(posedge clk or negedge rst_n or negedge frame_in_ready) begin
\t\t\t\tif(~rst_n || ~frame_in_ready) begin
\t\t\t\t\treg_out_ready <= 0;
\t\t\t\t\treg_out_data <= 0;
\t\t\t\t\tin_range_t <= 0;
\t\t\t\t\tin_range_b <= 0;
\t\t\t\t\tin_range_l <= 0;
\t\t\t\t\tin_range_r <= 0;
\t\t\t\tend else begin
\t\t\t\t\treg_out_ready <= 1;
\t\t\t\t\treg_out_data <= frame_in_data;
\t\t\t\t\tin_range_t <= tmp_t;
\t\t\t\t\tin_range_b <= tmp_b;
\t\t\t\t\tin_range_l <= tmp_l;
\t\t\t\t\tin_range_r <= tmp_r;
\t\t\t\tend
\t\t\tend
\t\tend
\t\tassign out_ready = reg_out_ready;
\t\tassign out_data = out_ready & in_range_t & in_range_b & in_range_l & in_range_r ? reg_out_data : 0;
\tendgenerate
endmodule
`undef im_width_half
`undef im_height_half
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
Scale
:Function
Scaling an image by your given scale.
Give the first output after 1 cycle while the frame input ready.
:Module
Main module
:Version
1.0
:Modified
2015-05-28
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module Scale(
\tclk,
\trst_n,
\tscale_x,
\tscale_y,
\tin_enable,
\tframe_in_ready,
\tframe_in_data,
\tframe_enable,
\tframe_out_count_x,
\tframe_out_count_y,
\tout_ready,
\tout_data);
\t/*
\t::description
\tThis module\'s working mode.
\t::range
\t0 for Pipline, 1 for Req-ack
\t*/
\tparameter work_mode = 0;
\t/*
\t::description
\tData bit width.
\t*/
\tparameter data_width = 8;
\t/*
\t::description
\tWidth of image.
\t::range
\t1 - 4096
\t*/
\tparameter im_width = 320;
\t/*
\t::description
\tHeight of image.
\t::range
\t1 - 4096
\t*/
\tparameter im_height = 240;
\t/*
\t::description
\tThe bits of width of image.
\t::range
\tDepend on width of image
\t*/
\tparameter im_width_bits = 9;
\t/*
\t::description
\tDelay for multiplier.
\t::range
\tDepend on your multilpliers\' configurations, 1 - 14
\t*/
\tparameter mul_delay = 3;
\t/*
\t::description
\tDelay for FrameController.
\t::range
\tDepend on your FrameController
\t*/
\tparameter ram_RL = 7;
\t/*
\t::description
\tClock.
\t*/
\tinput clk;
\t/*
\t::description
\tReset, active low.
\t*/
\tinput rst_n;
\t/*
\t::description
\tScale for horizontal, must be reciprocal of real scale.
\t::range
\tFixed number, 6bits.18bits
\t*/
\tinput [23 : 0] scale_x;
\t/*
\t::description
\tScale for vertical, must be reciprocal of real scale.
\t::range
\tFixed number, 6bits.18bits
\t*/
\tinput [23 : 0] scale_y;
\t/*
\t::description
\tInput data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
\t*/
\tinput in_enable;
\t/*
\t::description
\tConnect to out_ready in FrameController.
\t*/
\tinput frame_in_ready;
\t/*
\t::description
\tConnect to out_data in FrameController.
\t*/
\tinput[data_width - 1 : 0] frame_in_data;
\t/*
\t::description
\tConnect to in_enable in FrameController.
\t*/
\toutput frame_enable;
\t/*
\t::description
\tConnect to in_count_x in FrameController.
\t*/
\toutput[im_width_bits - 1 : 0] frame_out_count_x;
\t/*
\t::description
\tConnect to in_count_y in FrameController.
\t*/
\toutput[im_width_bits - 1 : 0] frame_out_count_y;
\t/*
\t::description
\tOutput data ready, in both two mode, it will be high while the out_data can be read.
\t*/
\toutput out_ready;
\t/*
\t::description
\tOutput data, it will be synchronous with out_ready.
\t*/
\toutput[data_width - 1 : 0] out_data;
\treg reg_out_ready;
\treg in_range_h, in_range_v;
\twire[18 : 0] mul_x_p, mul_y_p;
\twire[17 : 0] mul_x_r, mul_y_r;
\treg[3 : 0] con_mul_enable;
\treg[data_width - 1 : 0] reg_out_data;
\twire[im_width_bits - 1 : 0] count_x, count_y;
\tgenerate
\t\tif(work_mode == 0) begin
\t\t\treg [im_width_bits - 1 : 0] reg_count_x, reg_count_y;
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\treg_count_x <= 0;
\t\t\t\telse if(reg_count_x == im_width - 1)
\t\t\t\t\treg_count_x <= 0;
\t\t\t\telse
\t\t\t\t\treg_count_x <= reg_count_x + 1;
\t\t\tend
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\treg_count_y <= 0;
\t\t\t\telse if(reg_count_x == im_width - 1 && reg_count_y == im_height - 1)
\t\t\t\t\treg_count_y <= 0;
\t\t\t\telse if(reg_count_x == im_width - 1)
\t\t\t\t\treg_count_y <= reg_count_y + 1;
\t\t\t\telse
\t\t\t\t\treg_count_y <= reg_count_y;
\t\t\tend
\t\t\tassign count_x = reg_count_x;
\t\t\tassign count_y = reg_count_y;
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\tcon_mul_enable <= 0;
\t\t\t\telse if(con_mul_enable == mul_delay + 1)
\t\t\t\t\tcon_mul_enable <= con_mul_enable;
\t\t\t\telse
\t\t\t\t\tcon_mul_enable <= con_mul_enable + 1;
\t\t\tend
\t\t\tassign frame_enable = con_mul_enable == mul_delay + 1 ? 1 : 0;
\t\tend else begin
\t\t\treg signed [im_width_bits : 0] reg_count_x, reg_count_y;
\t\t\treg in_enable_last;
\t\t\talways @(posedge clk)
\t\t\t\tin_enable_last <= in_enable;
\t\t\talways @(posedge clk or negedge rst_n) begin
\t\t\t\tif(~rst_n)
\t\t\t\t\treg_count_x <= -1;
\t\t\t\telse if(~in_enable_last & in_enable) begin
\t\t\t\t\tif(reg_count_x == im_width - 1)
\t\t\t\t\t\treg_count_x <= 0;
\t\t\t\t\telse
\t\t\t\t\t\treg_count_x <= reg_count_x + 1;
\t\t\t\tend else
\t\t\t\t\treg_count_x <= reg_count_x;
\t\t\tend
\t\t\talways @(posedge clk or negedge rst_n) begin
\t\t\t\tif(~rst_n)
\t\t\t\t\treg_count_y <= 0;
\t\t\t\telse if(~in_enable_last & in_enable) begin
\t\t\t\t\tif(reg_count_x == im_width - 1 && reg_count_y == im_height - 1)
\t\t\t\t\t\treg_count_y <= 0;
\t\t\t\t\telse if(reg_count_x == im_width - 1)
\t\t\t\t\t\treg_count_y <= reg_count_y + 1;
\t\t\t\t\telse
\t\t\t\t\t\treg_count_y <= reg_count_y;
\t\t\t\tend\telse
\t\t\t\t\treg_count_y <= reg_count_y;
\t\t\tend
\t\t\tassign count_x = reg_count_x[im_width_bits - 1 : 0];
\t\t\tassign count_y = reg_count_y[im_width_bits - 1 : 0];
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\tcon_mul_enable <= 0;
\t\t\t\telse if(con_mul_enable == mul_delay + 2)
\t\t\t\t\tcon_mul_enable <= con_mul_enable;
\t\t\t\telse
\t\t\t\t\tcon_mul_enable <= con_mul_enable + 1;
\t\t\tend
\t\t\tassign frame_enable = con_mul_enable == mul_delay + 2 ? 1 : 0;
\t\tend
\t\t/*
\t\t::description
\t\tMultiplier for Unsigned 12bits x Unsigned 24bits, used for fixed multiplication.
\t\tYou can configure the multiplier by yourself, then change the "mul_delay".
\t\tAll Multiplier\'s pipeline stage must be same, you can not change the ports\' configurations!
\t\t*/
\t\tMultiplier12x24SCL MulX(.CLK(clk), .A({{12 - im_width_bits{1\'b0}}, count_x[im_width_bits - 1 : 0]}), .B(scale_x), .SCLR(~rst_n), .P(mul_x_p));
\t\t/*
\t\t::description
\t\tMultiplier for Unsigned 12bits x Unsigned 24bits, used for fixed multiplication.
\t\tYou can configure the multiplier by yourself, then change the "mul_delay".
\t\tAll Multiplier\'s pipeline stage must be same, you can not change the ports\' configurations!
\t\t*/
\t\tMultiplier12x24SCL MulY(.CLK(clk), .A({{12 - im_width_bits{1\'b0}}, count_y[im_width_bits - 1 : 0]}), .B(scale_y), .SCLR(~rst_n), .P(mul_y_p));
\t\t/*
\t\t::description
\t\tFor rounding fixed number.
\t\t*/
\t\tFixedRoundUnsigned #(19, 1) FRUX(clk, mul_x_p, mul_x_r);
\t\t/*
\t\t::description
\t\tFor rounding fixed number.
\t\t*/
\t\tFixedRoundUnsigned #(19, 1) FRUY(clk, mul_y_p, mul_y_r);
\t\tassign frame_out_count_x = mul_x_r[im_width_bits - 1 : 0];
\t\tassign frame_out_count_y = mul_y_r[im_width_bits - 1 : 0];
\t\tif(work_mode == 0) begin
\t\t\tgenvar i;
\t\t\tfor (i = 0; i < ram_RL - 1; i = i + 1) begin : buffer
\t\t\t\treg in_range_h, in_range_v;
\t\t\t\tif(i == 0) begin
\t\t\t\t\talways @(posedge clk) begin
\t\t\t\t\t\tin_range_h <= mul_x_r < im_width ? 1 : 0;
\t\t\t\t\t\tin_range_v <= mul_y_r < im_height ? 1 : 0;
\t\t\t\t\tend
\t\t\t\tend else begin
\t\t\t\t\talways @(posedge clk) begin
\t\t\t\t\t\tin_range_h <= buffer[i - 1].in_range_h;
\t\t\t\t\t\tin_range_v <= buffer[i - 1].in_range_v;
\t\t\t\t\tend
\t\t\t\tend
\t\t\tend
\t\t\talways @(posedge clk or negedge rst_n or negedge frame_in_ready) begin
\t\t\t\tif(~rst_n || ~frame_in_ready) begin
\t\t\t\t\treg_out_ready <= 0;
\t\t\t\t\tin_range_h <= 0;
\t\t\t\t\tin_range_v <= 0;
\t\t\t\t\treg_out_data <= 0;
\t\t\t\tend else begin
\t\t\t\t\treg_out_ready <= 1;
\t\t\t\t\tin_range_h <= buffer[ram_RL - 2].in_range_h;
\t\t\t\t\tin_range_v <= buffer[ram_RL - 2].in_range_v;
\t\t\t\t\treg_out_data <= frame_in_data;
\t\t\t\tend
\t\t\tend
\t\tend else begin
\t\t\treg tmp_h, tmp_v;
\t\t\talways @(posedge clk or negedge rst_n or negedge frame_in_ready) begin
\t\t\t\tif(~rst_n || ~frame_in_ready) begin
\t\t\t\t\treg_out_ready <= 0;
\t\t\t\t\treg_out_data <= 0;
\t\t\t\t\tin_range_h <= 0;
\t\t\t\t\tin_range_v <= 0;
\t\t\t\tend else begin
\t\t\t\t\treg_out_ready <= 1;
\t\t\t\t\treg_out_data <= frame_in_data;
\t\t\t\t\tin_range_h <= tmp_h;
\t\t\t\t\tin_range_v <= tmp_v;
\t\t\t\tend
\t\t\tend
\t\t\talways @(posedge clk) begin
\t\t\t\ttmp_h <= mul_x_r < im_width ? 1 : 0;
\t\t\t\ttmp_v <= mul_y_r < im_height ? 1 : 0;
\t\t\tend
\t\tend
\t\tassign out_ready = reg_out_ready;
\t\tassign out_data = out_ready & in_range_h & in_range_v ? reg_out_data : 0;
\tendgenerate
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
// Date : Fri May 29 20:15:13 2015
// Host : Dtysky running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// b:/Complex_Mind/FPGA-Imaging-Library/Master/Geometry/Rotate/HDL/Rotate.srcs/sources_1/ip/Multiplier13Sx20SRTT/Multiplier13Sx20SRTT_funcsim.v
// Design : Multiplier13Sx20SRTT
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "mult_gen_v12_0,Vivado 2014.4" *) (* CHECK_LICENSE_TYPE = "Multiplier13Sx20SRTT,mult_gen_v12_0,{}" *)
(* core_generation_info = "Multiplier13Sx20SRTT,mult_gen_v12_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=zynq,C_HAS_CE=0,C_HAS_SCLR=1,C_LATENCY=3,C_A_WIDTH=13,C_A_TYPE=0,C_B_WIDTH=20,C_B_TYPE=0,C_OUT_HIGH=32,C_OUT_LOW=0,C_MULT_TYPE=1,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}" *)
(* NotValidForBitStream *)
module Multiplier13Sx20SRTT
(CLK,
A,
B,
SCLR,
P);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) input CLK;
input [12:0]A;
input [19:0]B;
(* x_interface_info = "xilinx.com:signal:reset:1.0 sclr_intf RST" *) input SCLR;
output [32:0]P;
wire [12:0]A;
wire [19:0]B;
wire CLK;
wire [32:0]P;
wire SCLR;
wire [47:0]NLW_U0_PCASC_UNCONNECTED;
wire [1:0]NLW_U0_ZERO_DETECT_UNCONNECTED;
(* C_A_TYPE = "0" *)
(* C_A_WIDTH = "13" *)
(* C_B_TYPE = "0" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "20" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "3" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "1" *)
(* C_OPTIMIZE_GOAL = "1" *)
(* C_OUT_HIGH = "32" *)
(* C_OUT_LOW = "0" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* DONT_TOUCH *)
(* downgradeipidentifiedwarnings = "yes" *)
Multiplier13Sx20SRTT_mult_gen_v12_0__parameterized0 U0
(.A(A),
.B(B),
.CE(1\'b1),
.CLK(CLK),
.P(P),
.PCASC(NLW_U0_PCASC_UNCONNECTED[47:0]),
.SCLR(SCLR),
.ZERO_DETECT(NLW_U0_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule
(* ORIG_REF_NAME = "mult_gen_v12_0" *) (* C_VERBOSITY = "0" *) (* C_MODEL_TYPE = "0" *)
(* C_OPTIMIZE_GOAL = "1" *) (* C_XDEVICEFAMILY = "zynq" *) (* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *) (* C_LATENCY = "3" *) (* C_A_WIDTH = "13" *)
(* C_A_TYPE = "0" *) (* C_B_WIDTH = "20" *) (* C_B_TYPE = "0" *)
(* C_OUT_HIGH = "32" *) (* C_OUT_LOW = "0" *) (* C_MULT_TYPE = "1" *)
(* C_CE_OVERRIDES_SCLR = "0" *) (* C_CCM_IMP = "0" *) (* C_B_VALUE = "10000001" *)
(* C_HAS_ZERO_DETECT = "0" *) (* C_ROUND_OUTPUT = "0" *) (* C_ROUND_PT = "0" *)
(* downgradeipidentifiedwarnings = "yes" *)
module Multiplier13Sx20SRTT_mult_gen_v12_0__parameterized0
(CLK,
A,
B,
CE,
SCLR,
ZERO_DETECT,
P,
PCASC);
input CLK;
input [12:0]A;
input [19:0]B;
input CE;
input SCLR;
output [1:0]ZERO_DETECT;
output [32:0]P;
output [47:0]PCASC;
wire [12:0]A;
wire [19:0]B;
wire CE;
wire CLK;
wire [32:0]P;
wire [47:0]PCASC;
wire SCLR;
wire [1:0]ZERO_DETECT;
(* C_A_TYPE = "0" *)
(* C_A_WIDTH = "13" *)
(* C_B_TYPE = "0" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "20" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "3" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "1" *)
(* C_OPTIMIZE_GOAL = "1" *)
(* C_OUT_HIGH = "32" *)
(* C_OUT_LOW = "0" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* downgradeipidentifiedwarnings = "yes" *)
Multiplier13Sx20SRTT_mult_gen_v12_0_viv__parameterized0 i_mult
(.A(A),
.B(B),
.CE(CE),
.CLK(CLK),
.P(P),
.PCASC(PCASC),
.SCLR(SCLR),
.ZERO_DETECT(ZERO_DETECT));
endmodule
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`pragma protect key_block
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uVMi7GoGag==
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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gnO5lAmOjOXrf+28RyOfxhyCRgHKh6mRiH0tlgZUxbFCb24jFd8F2ON6eZARrIbx4Vu5v/7L6X5o
oTd41gw6CHpypaHAd88=
`pragma protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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FbcTbpApf4PkFyRzckA+yzqct0XOkXLsuWu6dE34gxuaUw9BCMtj5rnbQ0G0Xote0ldMp+AIN/vj
bJafuR2HkqxTvqwCTed3PqEy4xVdmr/ecywIlw==
`pragma protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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`pragma protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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pV+7oyzvQjUyYpAt0GiJuzwTVRTBCgpo3qFmbw==
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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26noQnHG8HzI3/cC/ctd9i6kgkDw4XwetJZQTQ==
`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7296)
`pragma protect data_block
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`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Xilinx
// Engineer: dtysky
//
// Create Date: 2015/02/05 18:01:07
// Design Name:
// Module Name: Or8
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependenrgb24es:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Or8(i0, i1, i2, i3, i4, i5, i6, i7, o);
\t
\tinput i0;
\tinput i1;
\tinput i2;
\tinput i3;
\tinput i4;
\tinput i5;
\tinput i6;
\tinput i7;
\toutput o;
\tassign o = {i0, i1, i2, i3, i4, i5, i6, i7} == 0 ? 0 : 1;
endmodule
|
/*
:Project
FPGA-Imaging-Library
:Design
ColorBin2Channels
:Function
Covert Bin to more channels.
:Module
Main module
:Version
1.0
:Modified
2015-05-12
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module ColorBin2Channels(
\tb,
\tchannels
);
\tparameter color_width = 8;
\tparameter color_channels = 3;
\tinput b;
\toutput[color_channels * color_width - 1 : 0] channels;
\tgenvar i;
\tgenerate
\t\t`define h (i + 1) * color_width - 1
\t\t`define l i * color_width
\t\tfor (i = 0; i < color_channels; i = i + 1) begin: channel
\t\t\tassign channels[`h : `l] = b ? {color_width{1'b1}} : {color_width{1'b0}};
\t\tend
\t\t`undef h
\t\t`undef l
\tendgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: None
// Engineer: Dai Tianyu (dtysky)
//
// Create Date: 2015/04/07 18:01:07
// Design Name:
// Module Name: DataCombin2
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependenrgb24es:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DataCombin2(i0, i1, o);
\tparameter data_width = 1;
\tinput[data_width - 1 : 0] i0, i1;
\toutput[2 * data_width - 1 : 0] o;
\tassign o = {i1, i0};
endmodule
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
ErosionDilationBin
:Function
Erosion or Dilation for binary images.
It will give the first output after pipe_stage cycles while in_enable enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-24
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
`define full_win_width window_width * window_width
module ErosionDilationBin(
\tclk,
\trst_n,
\tmode,
\ttemplate,
\tin_enable,
\tin_data,
\tout_ready,
\tout_data);
\t/*
\t::description
\tThis module's working mode.
\t::range
\t0 for Pipeline, 1 for Req-ack
\t*/
\tparameter[0 : 0] work_mode = 0;
\t/*
\t::description
\tThe width(and height) of window.
\t::range
\t2 - 15
\t*/
\tparameter[3 : 0] window_width = 3;
\t/*
\t::description
\tStage of pipe.
\t::range
\tDepend on width of window, log2(window_width^2)
\t*/
\tparameter pipe_stage = 3;
\t/*
\t::description
\tClock.
\t*/
\tinput clk;
\t/*
\t::description
\tReset, active low.
\t*/
\tinput rst_n;
\t/*
\t::description
\tOperation's mode.
\t::range
\t0 for Erosion, 1 for Dilation.
\t*/
\tinput mode;
\t/*
\t::description
\tTemplate for operation.
\t*/
\tinput[window_width * window_width - 1 : 0] template;
\t/*
\t::description
\tInput data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
\t*/
\tinput in_enable;
\t/*
\t::description
\tInput data, it must be synchronous with in_enable.
\t*/
\tinput [window_width * window_width - 1 : 0] in_data;
\t/*
\t::description
\tOutput data ready, in both two mode, it will be high while the out_data can be read.
\t*/
\toutput out_ready;
\t/*
\t::description
\tOutput data, it will be synchronous with out_ready.
\t*/
\toutput out_data;
\treg[`full_win_width - 1 : 0] reg_in_data;
\treg[3 : 0] con_enable;
\tfunction pre_now_pix(input pix, mode, template);
\t\tpre_now_pix = pix ^ mode | ~template;
\tendfunction
\tgenvar i, j;
\tgenerate
\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\tif(~rst_n || ~in_enable)
\t\t\t\tcon_enable <= 0;
\t\t\telse if(con_enable == pipe_stage)
\t\t\t\tcon_enable <= con_enable;
\t\t\telse
\t\t\t\tcon_enable <= con_enable + 1;
\t\tend
\t\tassign out_ready = con_enable == pipe_stage? 1 : 0;
\t\tfor (i = 0; i < `full_win_width; i = i + 1) begin
\t\t\tif(work_mode == 0) begin
\t\t\t\talways @(*)
\t\t\t\t\treg_in_data[i] = in_data[i];
\t\t\tend else begin
\t\t\t\talways @(posedge in_enable)
\t\t\t\t\treg_in_data[i] = in_data[i];
\t\t\tend
\t\tend
\t\tfor (i = 0; i < pipe_stage; i = i + 1) begin : pipe
\t\t\treg[(`full_win_width >> i + 1) - 1 : 0] res;
\t\t\tfor (j = 0; j < `full_win_width >> i + 1; j = j + 1) begin
\t\t\t\tif(i == 0) begin
\t\t\t\t\tif(j == 0 && ((`full_win_width >> i) % 2 != 0)) begin
\t\t\t\t\t\talways @(posedge clk)
\t\t\t\t\t\t\tres[j] <=
\t\t\t\t\t\t\t\tpre_now_pix(reg_in_data[`full_win_width - 1], mode, template[`full_win_width - 1]) &
\t\t\t\t\t\t\t\tpre_now_pix(reg_in_data[2 * j], mode, template[2 * j]) &
\t\t\t\t\t\t\t\tpre_now_pix(reg_in_data[2 * j + 1], mode, template[2 * j + 1]);
\t\t\t\t\tend else begin
\t\t\t\t\t\talways @(posedge clk)
\t\t\t\t\t\t\tres[j] <=
\t\t\t\t\t\t\t\tpre_now_pix(reg_in_data[2 * j], mode, template[2 * j]) &
\t\t\t\t\t\t\t\tpre_now_pix(reg_in_data[2 * j + 1], mode, template[2 * j + 1]);
\t\t\t\t\tend
\t\t\t\tend else begin
\t\t\t\t\tif(j == 0 && ((`full_win_width >> i) % 2 != 0)) begin
\t\t\t\t\t\talways @(posedge clk)
\t\t\t\t\t\t\tres[j] <= pipe[i - 1].res[(`full_win_width >> i) - 1] & pipe[i - 1].res[2 * j] & pipe[i - 1].res[2 * j + 1];
\t\t\t\t\tend else begin
\t\t\t\t\t\talways @(posedge clk)
\t\t\t\t\t\t\tres[j] <= pipe[i - 1].res[2 * j] & pipe[i - 1].res[2 * j + 1];
\t\t\t\t\tend
\t\t\t\tend
\t\t\tend
\t\tend
\t\tassign out_data = out_ready ? pipe[pipe_stage - 1].res[0] ^ mode : 0;
\tendgenerate
endmodule
`undef full_win_width
|
module I2C_Controller
(
\tinput\t\t\t\tiCLK,\t\t
\tinput\t\t\t\tiRST_N,\t\t
\tinput\t\t\t\tI2C_CLK,\t
\tinput\t\t\t\tI2C_EN,\t\t
\tinput\t\t[23:0]\tI2C_WDATA,\t
\toutput\t\t\t\tI2C_SCLK,\t
\tinout\t\t\t\tI2C_SDAT,\t
\tinput\t\t\t\tWR, \t
\tinput\t\t\t\tGO, \t
\toutput\t\t\t\tACK, \t
\toutput\treg\t\t\tEND, \t
\toutput\treg\t[7:0]\tI2C_RDATA\t
);
reg\t\tI2C_BIT;
reg \tSCLK;\t
reg\t[5:0]\tSD_COUNTER;
wire \tI2C_SCLK1 = \t(GO == 1 &&
\t\t\t\t\t\t((SD_COUNTER >= 5 && SD_COUNTER <=12 || SD_COUNTER == 14) ||\t
\t\t\t\t\t\t(SD_COUNTER >= 16 && SD_COUNTER <=23 || SD_COUNTER == 25) ||
\t\t\t\t\t\t(SD_COUNTER >= 27 && SD_COUNTER <=34 || SD_COUNTER == 36))) ? I2C_CLK : SCLK;\t\t\t\t\t
wire \tI2C_SCLK2 = \t(GO == 1 &&
\t\t\t\t\t\t((SD_COUNTER >= 5 && SD_COUNTER <=12 || SD_COUNTER == 14) ||
\t\t\t\t\t\t(SD_COUNTER >= 16 && SD_COUNTER <=23 || SD_COUNTER == 25) ||
\t\t\t\t\t\t(SD_COUNTER >= 33 && SD_COUNTER <=40 || SD_COUNTER == 42) ||
\t\t\t\t\t\t(SD_COUNTER >= 45 && SD_COUNTER <=52 || SD_COUNTER == 54))) ? I2C_CLK : SCLK;\t\t\t\t\t\t
assign\tI2C_SCLK = WR ? I2C_SCLK1 : I2C_SCLK2;\t
wire\tSDO1\t=\t\t((SD_COUNTER == 13 || SD_COUNTER == 14)||
\t\t\t\t\t\t(SD_COUNTER == 24 || SD_COUNTER == 25) ||
\t\t\t\t\t\t(SD_COUNTER == 35 || SD_COUNTER == 36)) ? 1'b0 : 1'b1;\t\t\t\t\t\t\t\t
wire\tSDO2\t=\t\t((SD_COUNTER == 13 || SD_COUNTER == 14)||
\t\t\t\t\t\t(SD_COUNTER == 24 || SD_COUNTER == 25) ||
\t\t\t\t\t\t(SD_COUNTER == 41 || SD_COUNTER == 42) ||
\t\t\t\t\t\t(SD_COUNTER >= 44 && SD_COUNTER <= 52)) ? 1'b0 : 1'b1;\t\t
wire\tSDO = WR ? SDO1 : SDO2;
assign\tI2C_SDAT = SDO ? I2C_BIT : 1'bz;
reg\t\tACKW1, ACKW2, ACKW3;\t\t
reg \tACKR1, ACKR2, ACKR3;\t\t
assign\tACK = WR ? (ACKW1 | ACKW2 | ACKW3) : (ACKR1 | ACKR2 | ACKR3);
always @(posedge iCLK or negedge iRST_N)
begin
\tif (!iRST_N)
\t\tSD_COUNTER <= 6'b0;
\telse if(I2C_EN)
\t\tbegin
\t\tif (GO == 0 || END == 1)
\t\t\tSD_COUNTER <= 6'b0;
\t\telse if (SD_COUNTER < 6'd63)
\t\t\tSD_COUNTER <= SD_COUNTER + 6'd1;\t
\t\tend
\telse
\t\tSD_COUNTER <= SD_COUNTER;
end
always @(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
\t\tbegin
\t\tSCLK <= 1;
\t\tI2C_BIT <= 1;
\t\tACKW1 <= 1; ACKW2 <= 1; ACKW3 <= 1;
\t\tACKR1 <= 1; ACKR2 <= 1; ACKR3 <= 1;
\t\tEND <= 0;
\t\tI2C_RDATA <= 8'h0;\t
\t\tend
\telse if(I2C_EN)\t\t
\t\tbegin
\t\tif(GO)
\t\t\tbegin
\t\t\tif(WR)\t\t
\t\t\t\tbegin
\t\t\t\tcase(SD_COUNTER)
\t\t\t\t6'd0 :\tbegin
\t\t\t\t\t\tSCLK <= 1;
\t\t\t\t\t\tI2C_BIT <= 1;
\t\t\t\t\t\tACKW1 <= 1; ACKW2 <= 1; ACKW3 <= 1;
\t\t\t\t\t\tACKR1 <= 1; ACKR2 <= 1; ACKR3 <= 1;
\t\t\t\t\t\tEND <= 0;
\t\t\t\t\t\tend
\t\t\t\t6'd1 :\tbegin
\t\t\t\t\t\tSCLK <= 1;
\t\t\t\t\t\tI2C_BIT <= 1;
\t\t\t\t\t\tACKW1 <= 1; ACKW2 <= 1; ACKW3 <= 1;
\t\t\t\t\t\tEND <= 0;
\t\t\t\t\t\tend
\t\t\t\t6'd2 : I2C_BIT <= 0;\t\t
\t\t\t\t6'd3 : SCLK <= 0;\t\t\t
\t\t\t\t6'd4 : I2C_BIT <= I2C_WDATA[23];\t
\t\t\t\t6'd5 : I2C_BIT <= I2C_WDATA[22];\t
\t\t\t\t6'd6 : I2C_BIT <= I2C_WDATA[21];\t
\t\t\t\t6'd7 : I2C_BIT <= I2C_WDATA[20];\t
\t\t\t\t6'd8 : I2C_BIT <= I2C_WDATA[19];\t
\t\t\t\t6'd9 : I2C_BIT <= I2C_WDATA[18];\t
\t\t\t\t6'd10 : I2C_BIT <= I2C_WDATA[17];\t
\t\t\t\t6'd11 : I2C_BIT <= I2C_WDATA[16];\t
\t\t\t\t6'd12 : I2C_BIT <= 0;\t\t\t\t
\t\t\t\t6'd13 : ACKW1 \t<= I2C_SDAT;\t\t
\t\t\t\t6'd14 : I2C_BIT <= 0;\t\t\t\t
\t\t\t\t6'd15 : I2C_BIT <= I2C_WDATA[15];\t
\t\t\t\t6'd16 : I2C_BIT <= I2C_WDATA[14];\t
\t\t\t\t6'd17 : I2C_BIT <= I2C_WDATA[13];\t
\t\t\t\t6'd18 : I2C_BIT <= I2C_WDATA[12];\t
\t\t\t\t6'd19 : I2C_BIT <= I2C_WDATA[11];\t
\t\t\t\t6'd20 : I2C_BIT <= I2C_WDATA[10];\t
\t\t\t\t6'd21 : I2C_BIT <= I2C_WDATA[9];
\t\t\t\t6'd22 : I2C_BIT <= I2C_WDATA[8];\t
\t\t\t\t6'd23 : I2C_BIT <= 0;\t\t\t\t
\t\t\t\t6'd24 : ACKW2 \t<= I2C_SDAT;\t\t
\t\t\t\t6'd25 : I2C_BIT <= 0;\t\t\t\t
\t\t\t\t6'd26 : I2C_BIT <= I2C_WDATA[7];\t
\t\t\t\t6'd27 : I2C_BIT <= I2C_WDATA[6];\t
\t\t\t\t6'd28 : I2C_BIT <= I2C_WDATA[5];\t
\t\t\t\t6'd29 : I2C_BIT <= I2C_WDATA[4];\t
\t\t\t\t6'd30 : I2C_BIT <= I2C_WDATA[3];\t
\t\t\t\t6'd31 : I2C_BIT <= I2C_WDATA[2];\t
\t\t\t\t6'd32 : I2C_BIT <= I2C_WDATA[1];\t
\t\t\t\t6'd33 : I2C_BIT <= I2C_WDATA[0];\t
\t\t\t\t6'd34 : I2C_BIT <= 0;\t\t\t\t
\t\t\t\t6'd35 : ACKW3 \t<= I2C_SDAT;\t\t
\t\t\t\t6'd36 : I2C_BIT <= 0;\t\t\t\t
\t\t\t\t6'd37 : begin\tSCLK <= 0; I2C_BIT <= 0; end
\t\t\t\t6'd38 : SCLK <= 1;\t
\t\t\t\t6'd39 : begin I2C_BIT <= 1; END <= 1; end
\t\t\t\tdefault : begin I2C_BIT <= 1; SCLK <= 1; end
\t\t\t\tendcase
\t\t\t\tend
\t\t\telse\t\t
\t\t\t\tbegin
\t\t\t\tcase(SD_COUNTER)
\t\t\t\t6'd0 :\tbegin
\t\t\t\t\t\tSCLK <= 1;
\t\t\t\t\t\tI2C_BIT <= 1;
\t\t\t\t\t\tACKW1 <= 1; ACKW2 <= 1; ACKW3 <= 1;
\t\t\t\t\t\tACKR1 <= 1; ACKR2 <= 1; ACKR3 <= 1;
\t\t\t\t\t\tEND <= 0;
\t\t\t\t\t\tend
\t\t\t\t6'd1 :\tbegin
\t\t\t\t\t\tSCLK <= 1;
\t\t\t\t\t\tI2C_BIT <= 1;
\t\t\t\t\t\tACKR1 <= 1; ACKR2 <= 1; ACKR3 <= 1;
\t\t\t\t\t\tEND <= 0;
\t\t\t\t\t\tend
\t\t\t\t6'd2 : I2C_BIT <= 0;\t\t
\t\t\t\t6'd3 : SCLK <= 0;\t\t\t
\t\t\t\t6'd4 : I2C_BIT <= I2C_WDATA[23];\t
\t\t\t\t6'd5 : I2C_BIT <= I2C_WDATA[22];\t
\t\t\t\t6'd6 : I2C_BIT <= I2C_WDATA[21];\t
\t\t\t\t6'd7 : I2C_BIT <= I2C_WDATA[20];\t
\t\t\t\t6'd8 : I2C_BIT <= I2C_WDATA[19];
\t\t\t\t6'd9 : I2C_BIT <= I2C_WDATA[18];\t
\t\t\t\t6'd10 : I2C_BIT <= I2C_WDATA[17];\t
\t\t\t\t6'd11 : I2C_BIT <= I2C_WDATA[16];\t
\t\t\t\t6'd12 : I2C_BIT <= 0;\t\t\t\t
\t\t\t\t6'd13 : ACKR1 \t<= I2C_SDAT;\t\t
\t\t\t\t6'd14 : I2C_BIT <= 0;\t\t\t\t
\t\t\t\t6'd15 : I2C_BIT <= I2C_WDATA[15];\t
\t\t\t\t6'd16 : I2C_BIT <= I2C_WDATA[14];\t
\t\t\t\t6'd17 : I2C_BIT <= I2C_WDATA[13];\t
\t\t\t\t6'd18 : I2C_BIT <= I2C_WDATA[12];\t
\t\t\t\t6'd19 : I2C_BIT <= I2C_WDATA[11];\t
\t\t\t\t6'd20 : I2C_BIT <= I2C_WDATA[10];\t
\t\t\t\t6'd21 : I2C_BIT <= I2C_WDATA[9];
\t\t\t\t6'd22 : I2C_BIT <= I2C_WDATA[8];\t
\t\t\t\t6'd23 : I2C_BIT <= 0;\t\t\t\t
\t\t\t\t6'd24 : ACKR2 \t<= I2C_SDAT;\t\t
\t\t\t\t6'd25 : I2C_BIT <= 0;\t\t\t\t
\t\t\t\t6'd26 : begin\tSCLK <= 0; I2C_BIT <= 0; end
\t\t\t\t6'd27 : SCLK <= 1;\t
\t\t\t\t6'd28 : begin I2C_BIT <= 1; end
\t\t\t\t6'd29 :\tbegin
\t\t\t\t\t\tSCLK <= 1;
\t\t\t\t\t\tI2C_BIT <= 1;
\t\t\t\t\t\tend
\t\t\t\t6'd30 : I2C_BIT <= 0;\t\t
\t\t\t\t6'd31 : SCLK <= 0;\t\t\t
\t\t\t\t6'd32 : I2C_BIT <= I2C_WDATA[23];\t
\t\t\t\t6'd33 : I2C_BIT <= I2C_WDATA[22];\t
\t\t\t\t6'd34 : I2C_BIT <= I2C_WDATA[21];\t
\t\t\t\t6'd35 : I2C_BIT <= I2C_WDATA[20];\t
\t\t\t\t6'd36 : I2C_BIT <= I2C_WDATA[19];\t
\t\t\t\t6'd37 : I2C_BIT <= I2C_WDATA[18];\t
\t\t\t\t6'd38 : I2C_BIT <= I2C_WDATA[17];\t
\t\t\t\t6'd39 : I2C_BIT <= 1'b1;\t\t\t
\t\t\t\t6'd40 : I2C_BIT <= 0;\t\t\t\t
\t\t\t\t6'd41 : ACKR3 \t<= I2C_SDAT;\t\t
\t\t\t\t6'd42 : I2C_BIT <= 0;\t\t\t\t
\t\t\t\t6'd43 : I2C_BIT \t<= 0;\t\t\t
\t\t\t\t6'd44 : I2C_BIT \t<= 0;\t\t\t
\t\t\t\t6'd45 : I2C_RDATA[7] <= I2C_SDAT;\t
\t\t\t\t6'd46 : I2C_RDATA[6] <= I2C_SDAT;\t
\t\t\t\t6'd47 : I2C_RDATA[5] <= I2C_SDAT;\t
\t\t\t\t6'd48 : I2C_RDATA[4] <= I2C_SDAT;\t
\t\t\t\t6'd49 : I2C_RDATA[3] <= I2C_SDAT;\t
\t\t\t\t6'd50 : I2C_RDATA[2] <= I2C_SDAT;\t
\t\t\t\t6'd51 : I2C_RDATA[1] <= I2C_SDAT;\t
\t\t\t\t6'd52 : I2C_RDATA[0] <= I2C_SDAT;\t \t
\t\t\t\t6'd53 : I2C_BIT \t<= 1;\t\t\t
\t\t\t\t6'd54 : I2C_BIT \t<= 0;\t\t\t
\t\t\t\t6'd55 : begin\tSCLK <= 0; I2C_BIT <= 0; end
\t\t\t\t6'd56 : SCLK <= 1;\t
\t\t\t\t6'd57 : begin I2C_BIT <= 1; END <= 1; end
\t\t\t\tdefault : begin I2C_BIT <= 1; SCLK <= 1; end
\t\t\t\tendcase
\t\t\t\tend
\t\t\tend
\t\telse
\t\t\tbegin
\t\t\tSCLK <= 1;
\t\t\tI2C_BIT <= 1;
\t\t\tACKW1 <= 1; ACKW2 <= 1; ACKW3 <= 1;
\t\t\tACKR1 <= 1; ACKR2 <= 1; ACKR3 <= 1;
\t\t\tEND <= 0;
\t\t\tI2C_RDATA <= I2C_RDATA;
\t\t\tend
\t\tend
end
\t\t
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
// Date : Mon May 25 17:58:01 2015
// Host : Dtysky running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// b:/Complex_Mind/FPGA-Imaging-Library/Master/Generator/FrameController2/HDL/FrameController2.srcs/sources_1/ip/Multiplier12x12FR2/Multiplier12x12FR2_funcsim.v
// Design : Multiplier12x12FR2
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "mult_gen_v12_0,Vivado 2014.4" *) (* CHECK_LICENSE_TYPE = "Multiplier12x12FR2,mult_gen_v12_0,{}" *)
(* core_generation_info = "Multiplier12x12FR2,mult_gen_v12_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=zynq,C_HAS_CE=0,C_HAS_SCLR=1,C_LATENCY=3,C_A_WIDTH=12,C_A_TYPE=1,C_B_WIDTH=12,C_B_TYPE=1,C_OUT_HIGH=23,C_OUT_LOW=0,C_MULT_TYPE=1,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}" *)
(* NotValidForBitStream *)
module Multiplier12x12FR2
(CLK,
A,
B,
SCLR,
P);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) input CLK;
input [11:0]A;
input [11:0]B;
(* x_interface_info = "xilinx.com:signal:reset:1.0 sclr_intf RST" *) input SCLR;
output [23:0]P;
wire [11:0]A;
wire [11:0]B;
wire CLK;
wire [23:0]P;
wire SCLR;
wire [47:0]NLW_U0_PCASC_UNCONNECTED;
wire [1:0]NLW_U0_ZERO_DETECT_UNCONNECTED;
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "12" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "12" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "3" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "1" *)
(* C_OPTIMIZE_GOAL = "1" *)
(* C_OUT_HIGH = "23" *)
(* C_OUT_LOW = "0" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* DONT_TOUCH *)
(* downgradeipidentifiedwarnings = "yes" *)
Multiplier12x12FR2_mult_gen_v12_0__parameterized0 U0
(.A(A),
.B(B),
.CE(1\'b1),
.CLK(CLK),
.P(P),
.PCASC(NLW_U0_PCASC_UNCONNECTED[47:0]),
.SCLR(SCLR),
.ZERO_DETECT(NLW_U0_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule
(* ORIG_REF_NAME = "mult_gen_v12_0" *) (* C_VERBOSITY = "0" *) (* C_MODEL_TYPE = "0" *)
(* C_OPTIMIZE_GOAL = "1" *) (* C_XDEVICEFAMILY = "zynq" *) (* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *) (* C_LATENCY = "3" *) (* C_A_WIDTH = "12" *)
(* C_A_TYPE = "1" *) (* C_B_WIDTH = "12" *) (* C_B_TYPE = "1" *)
(* C_OUT_HIGH = "23" *) (* C_OUT_LOW = "0" *) (* C_MULT_TYPE = "1" *)
(* C_CE_OVERRIDES_SCLR = "0" *) (* C_CCM_IMP = "0" *) (* C_B_VALUE = "10000001" *)
(* C_HAS_ZERO_DETECT = "0" *) (* C_ROUND_OUTPUT = "0" *) (* C_ROUND_PT = "0" *)
(* downgradeipidentifiedwarnings = "yes" *)
module Multiplier12x12FR2_mult_gen_v12_0__parameterized0
(CLK,
A,
B,
CE,
SCLR,
ZERO_DETECT,
P,
PCASC);
input CLK;
input [11:0]A;
input [11:0]B;
input CE;
input SCLR;
output [1:0]ZERO_DETECT;
output [23:0]P;
output [47:0]PCASC;
wire [11:0]A;
wire [11:0]B;
wire CE;
wire CLK;
wire [23:0]P;
wire [47:0]PCASC;
wire SCLR;
wire [1:0]ZERO_DETECT;
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "12" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "12" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "3" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "1" *)
(* C_OPTIMIZE_GOAL = "1" *)
(* C_OUT_HIGH = "23" *)
(* C_OUT_LOW = "0" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* downgradeipidentifiedwarnings = "yes" *)
Multiplier12x12FR2_mult_gen_v12_0_viv__parameterized0 i_mult
(.A(A),
.B(B),
.CE(CE),
.CLK(CLK),
.P(P),
.PCASC(PCASC),
.SCLR(SCLR),
.ZERO_DETECT(ZERO_DETECT));
endmodule
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`pragma protect key_block
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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gnO5lAmOjOXrf+28RyOfxhyCRgHKh6mRiH0tlgZUxbFCb24jFd8F2ON6eZARrIbx4Vu5v/7L6X5o
oTd41gw6CHpypaHAd88=
`pragma protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
d4UDVzST4F/GIUQK7Q/mgyckJ8hrUJmJYmR7IrVlH2X6hv2uAAk4gpmfB6E2dVAnuOOE4STY1OeO
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bJafuR2HkqxTvqwCTed3PqEy4xVdmr/ecywIlw==
`pragma protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
ZzJe3CosxBQtdtXIXPjUB1PIjPHRzRe+TcPVuazVXoOV6QQ4DY8D8TRP6/DZEeIUzxe5gMRXz2yf
RclEq20zSfPMaB3h6L9uECxIUPiPZJ03aglicg+QjHFDLo1XgOo1ItxSaGSam80SUko6TFrRjWV7
DlVH8SFB0gTLxJpXLeU=
`pragma protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
k0pB4lrRLLpdtNnVRXv7qxU15dyKF9BuJVYUlIA955FRzEtgaMMCmzDybCNTUJh5QGLsvLYdRVSK
VcBOlgtImwe2FJEsDE/buKE8+W7HPOSiP0Elo4jDRWfwpueOq6VQ4zL5XMAGi+70gMxxGQr7Z5E8
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
CvrdHJXWnQfXzzSiWw0jNoEt7+BoZ/LZtdbDFXaSiWMDQ2Vk6puIc6EOqYAUQkDOk2e0tjeVPbuy
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`pragma protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
OdvspRxAZYkQaAxKKdA1LsFAsM56hWSeApR5vUpKpxX6pSTf+1FKT4VsjLCFBqzGqve0MQBjmS3V
qyRHXgiuBp9jz5c7CcarmZSThSGxGNBblhKNJeYgXCu0ip6BtkoDBwXW++32tF/sf/FnJ1XuyAA3
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wuxy68DKLNCFR0gHKmnUESZyscn0Y+ZfyohQEQ==
`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7328)
`pragma protect data_block
VkGLvYoQ7nNwZ5ihhIO8WVUnCfeOd+Ac0yOFd71E533xQvvXqi7dcMP2EVC3ypJuXpWEKSHoM0UX
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`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1 ns / 1 ps
\tmodule BoardInit_AXI_v1_0_S00_AXI #
\t(
\t\t// Users to add parameters here
\t\tparameter integer im_bits_width = 9,
\t\tparameter integer color_width = 8,
\t\tparameter integer window_width = 8,
\t\t// User parameters ends
\t\t// Do not modify the parameters beyond this line
\t\t// Width of S_AXI data bus
\t\tparameter integer C_S_AXI_DATA_WIDTH\t= 32,
\t\t// Width of S_AXI address bus
\t\tparameter integer C_S_AXI_ADDR_WIDTH\t= 7
\t)
\t(
\t\t// Users to add ports here
\t\tinput wire rst_n,
\t\tinput wire pll_locked,
\t\toutput wire rst_all_n,
\t\toutput wire th_mode,
\t\toutput wire[color_width - 1 : 0] th1,
\t\toutput wire[color_width - 1 : 0] th2,
\t\toutput wire[23 : 0] ct_scale,
\t\toutput wire signed[color_width : 0] lm_gain,
\t\toutput wire[3 : 0] rank,
\t\toutput wire ed_mode,
\t\toutput wire[window_width * window_width - 1 : 0] ed_template,
\t\toutput wire[window_width * window_width - 1 : 0] mt_template,
\t\toutput wire[im_bits_width - 1 : 0] crop_top,crop_bottom,crop_left,crop_right,
\t\toutput wire[1 : 0] mirror_mode,
\t\toutput wire signed[im_bits_width : 0] offset_x, offset_y,
\t\toutput wire [23 : 0] scale_x, scale_y,
\t\toutput wire signed[24 : 0] sh_u, sh_v,
\t\toutput wire[8 : 0] angle,
\t\toutput wire[31 : 0] sels,
\t\t// User ports ends
\t\t// Do not modify the ports beyond this line
\t\t// Global Clock Signal
\t\tinput wire S_AXI_ACLK,
\t\t// Global Reset Signal. This Signal is Active LOW
\t\tinput wire S_AXI_ARESETN,
\t\t// Write address (issued by master, acceped by Slave)
\t\tinput wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
\t\t// Write channel Protection type. This signal indicates the
\t\t// privilege and security level of the transaction, and whether
\t\t// the transaction is a data access or an instruction access.
\t\tinput wire [2 : 0] S_AXI_AWPROT,
\t\t// Write address valid. This signal indicates that the master signaling
\t\t// valid write address and control information.
\t\tinput wire S_AXI_AWVALID,
\t\t// Write address ready. This signal indicates that the slave is ready
\t\t// to accept an address and associated control signals.
\t\toutput wire S_AXI_AWREADY,
\t\t// Write data (issued by master, acceped by Slave)
\t\tinput wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
\t\t// Write strobes. This signal indicates which byte lanes hold
\t\t// valid data. There is one write strobe bit for each eight
\t\t// bits of the write data bus.
\t\tinput wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
\t\t// Write valid. This signal indicates that valid write
\t\t// data and strobes are available.
\t\tinput wire S_AXI_WVALID,
\t\t// Write ready. This signal indicates that the slave
\t\t// can accept the write data.
\t\toutput wire S_AXI_WREADY,
\t\t// Write response. This signal indicates the status
\t\t// of the write transaction.
\t\toutput wire [1 : 0] S_AXI_BRESP,
\t\t// Write response valid. This signal indicates that the channel
\t\t// is signaling a valid write response.
\t\toutput wire S_AXI_BVALID,
\t\t// Response ready. This signal indicates that the master
\t\t// can accept a write response.
\t\tinput wire S_AXI_BREADY,
\t\t// Read address (issued by master, acceped by Slave)
\t\tinput wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
\t\t// Protection type. This signal indicates the privilege
\t\t// and security level of the transaction, and whether the
\t\t// transaction is a data access or an instruction access.
\t\tinput wire [2 : 0] S_AXI_ARPROT,
\t\t// Read address valid. This signal indicates that the channel
\t\t// is signaling valid read address and control information.
\t\tinput wire S_AXI_ARVALID,
\t\t// Read address ready. This signal indicates that the slave is
\t\t// ready to accept an address and associated control signals.
\t\toutput wire S_AXI_ARREADY,
\t\t// Read data (issued by slave)
\t\toutput wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
\t\t// Read response. This signal indicates the status of the
\t\t// read transfer.
\t\toutput wire [1 : 0] S_AXI_RRESP,
\t\t// Read valid. This signal indicates that the channel is
\t\t// signaling the required read data.
\t\toutput wire S_AXI_RVALID,
\t\t// Read ready. This signal indicates that the master can
\t\t// accept the read data and response information.
\t\tinput wire S_AXI_RREADY
\t);
\t// AXI4LITE signals
\treg [C_S_AXI_ADDR_WIDTH-1 : 0] \taxi_awaddr;
\treg \taxi_awready;
\treg \taxi_wready;
\treg [1 : 0] \taxi_bresp;
\treg \taxi_bvalid;
\treg [C_S_AXI_ADDR_WIDTH-1 : 0] \taxi_araddr;
\treg \taxi_arready;
\treg [C_S_AXI_DATA_WIDTH-1 : 0] \taxi_rdata;
\treg [1 : 0] \taxi_rresp;
\treg \taxi_rvalid;
\t// Example-specific design signals
\t// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
\t// ADDR_LSB is used for addressing 32/64 bit registers/memories
\t// ADDR_LSB = 2 for 32 bits (n downto 2)
\t// ADDR_LSB = 3 for 64 bits (n downto 3)
\tlocalparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
\tlocalparam integer OPT_MEM_ADDR_BITS = 4;
\t//----------------------------------------------
\t//-- Signals for user logic register space example
\t//------------------------------------------------
\t//-- Number of Slave Registers 32
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg0;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg1;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg2;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg3;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg4;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg5;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg6;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg7;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg8;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg9;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg10;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg11;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg12;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg13;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg14;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg15;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg16;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg17;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg18;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg19;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg20;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg21;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg22;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg23;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg24;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg25;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg26;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg27;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg28;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg29;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg30;
\treg [C_S_AXI_DATA_WIDTH-1:0]\tslv_reg31;
\twire\t slv_reg_rden;
\twire\t slv_reg_wren;
\treg [C_S_AXI_DATA_WIDTH-1:0]\t reg_data_out;
\tinteger\t byte_index;
\t// I/O Connections assignments
\tassign S_AXI_AWREADY\t= axi_awready;
\tassign S_AXI_WREADY\t= axi_wready;
\tassign S_AXI_BRESP\t= axi_bresp;
\tassign S_AXI_BVALID\t= axi_bvalid;
\tassign S_AXI_ARREADY\t= axi_arready;
\tassign S_AXI_RDATA\t= axi_rdata;
\tassign S_AXI_RRESP\t= axi_rresp;
\tassign S_AXI_RVALID\t= axi_rvalid;
\t// Implement axi_awready generation
\t// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
\t// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
\t// de-asserted when reset is low.
\talways @( posedge S_AXI_ACLK )
\tbegin
\t if ( S_AXI_ARESETN == 1'b0 )
\t begin
\t axi_awready <= 1'b0;
\t end
\t else
\t begin
\t if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
\t begin
\t // slave is ready to accept write address when
\t // there is a valid write address and write data
\t // on the write address and data bus. This design
\t // expects no outstanding transactions.
\t axi_awready <= 1'b1;
\t end
\t else
\t begin
\t axi_awready <= 1'b0;
\t end
\t end
\tend
\t// Implement axi_awaddr latching
\t// This process is used to latch the address when both
\t// S_AXI_AWVALID and S_AXI_WVALID are valid.
\talways @( posedge S_AXI_ACLK )
\tbegin
\t if ( S_AXI_ARESETN == 1'b0 )
\t begin
\t axi_awaddr <= 0;
\t end
\t else
\t begin
\t if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
\t begin
\t // Write Address latching
\t axi_awaddr <= S_AXI_AWADDR;
\t end
\t end
\tend
\t// Implement axi_wready generation
\t// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
\t// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
\t// de-asserted when reset is low.
\talways @( posedge S_AXI_ACLK )
\tbegin
\t if ( S_AXI_ARESETN == 1'b0 )
\t begin
\t axi_wready <= 1'b0;
\t end
\t else
\t begin
\t if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
\t begin
\t // slave is ready to accept write data when
\t // there is a valid write address and write data
\t // on the write address and data bus. This design
\t // expects no outstanding transactions.
\t axi_wready <= 1'b1;
\t end
\t else
\t begin
\t axi_wready <= 1'b0;
\t end
\t end
\tend
\t// Implement memory mapped register select and write logic generation
\t// The write data is accepted and written to memory mapped registers when
\t// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
\t// select byte enables of slave registers while writing.
\t// These registers are cleared when reset (active low) is applied.
\t// Slave register write enable is asserted when valid address and data are available
\t// and the slave is ready to accept the write address and write data.
\tassign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
\talways @( posedge S_AXI_ACLK )
\tbegin
\t if ( S_AXI_ARESETN == 1'b0 )
\t begin
\t slv_reg0 <= 0;
\t slv_reg1 <= 0;
\t slv_reg2 <= 0;
\t slv_reg3 <= 0;
\t slv_reg4 <= 0;
\t slv_reg5 <= 0;
\t slv_reg6 <= 0;
\t slv_reg7 <= 0;
\t slv_reg8 <= 0;
\t slv_reg9 <= 0;
\t slv_reg10 <= 0;
\t slv_reg11 <= 0;
\t slv_reg12 <= 0;
\t slv_reg13 <= 0;
\t slv_reg14 <= 0;
\t slv_reg15 <= 0;
\t slv_reg16 <= 0;
\t slv_reg17 <= 0;
\t slv_reg18 <= 0;
\t slv_reg19 <= 0;
\t slv_reg20 <= 0;
\t slv_reg21 <= 0;
\t slv_reg22 <= 0;
\t slv_reg23 <= 0;
\t slv_reg24 <= 0;
\t slv_reg25 <= 0;
\t slv_reg26 <= 0;
\t slv_reg27 <= 0;
\t slv_reg28 <= 0;
\t slv_reg29 <= 0;
\t slv_reg30 <= 0;
\t slv_reg31 <= 0;
\t end
\t else begin
\t if (slv_reg_wren)
\t begin
\t case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
\t 5'h00:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 0
\t slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h01:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 1
\t slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h02:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 2
\t slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h03:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 3
\t slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h04:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 4
\t slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h05:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 5
\t slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h06:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 6
\t slv_reg6[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h07:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 7
\t slv_reg7[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h08:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 8
\t slv_reg8[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h09:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 9
\t slv_reg9[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h0A:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 10
\t slv_reg10[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h0B:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 11
\t slv_reg11[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h0C:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 12
\t slv_reg12[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h0D:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 13
\t slv_reg13[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h0E:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 14
\t slv_reg14[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h0F:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 15
\t slv_reg15[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h10:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 16
\t slv_reg16[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h11:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 17
\t slv_reg17[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h12:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 18
\t slv_reg18[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h13:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 19
\t slv_reg19[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h14:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 20
\t slv_reg20[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h15:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 21
\t slv_reg21[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h16:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 22
\t slv_reg22[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h17:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 23
\t slv_reg23[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h18:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 24
\t slv_reg24[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h19:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 25
\t slv_reg25[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h1A:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 26
\t slv_reg26[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h1B:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 27
\t slv_reg27[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h1C:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 28
\t slv_reg28[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h1D:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 29
\t slv_reg29[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h1E:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 30
\t slv_reg30[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t 5'h1F:
\t for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
\t if ( S_AXI_WSTRB[byte_index] == 1 ) begin
\t // Respective byte enables are asserted as per write strobes
\t // Slave register 31
\t slv_reg31[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
\t end
\t default : begin
\t slv_reg0 <= slv_reg0;
\t slv_reg1 <= slv_reg1;
\t slv_reg2 <= slv_reg2;
\t slv_reg3 <= slv_reg3;
\t slv_reg4 <= slv_reg4;
\t slv_reg5 <= slv_reg5;
\t slv_reg6 <= slv_reg6;
\t slv_reg7 <= slv_reg7;
\t slv_reg8 <= slv_reg8;
\t slv_reg9 <= slv_reg9;
\t slv_reg10 <= slv_reg10;
\t slv_reg11 <= slv_reg11;
\t slv_reg12 <= slv_reg12;
\t slv_reg13 <= slv_reg13;
\t slv_reg14 <= slv_reg14;
\t slv_reg15 <= slv_reg15;
\t slv_reg16 <= slv_reg16;
\t slv_reg17 <= slv_reg17;
\t slv_reg18 <= slv_reg18;
\t slv_reg19 <= slv_reg19;
\t slv_reg20 <= slv_reg20;
\t slv_reg21 <= slv_reg21;
\t slv_reg22 <= slv_reg22;
\t slv_reg23 <= slv_reg23;
\t slv_reg24 <= slv_reg24;
\t slv_reg25 <= slv_reg25;
\t slv_reg26 <= slv_reg26;
\t slv_reg27 <= slv_reg27;
\t slv_reg28 <= slv_reg28;
\t slv_reg29 <= slv_reg29;
\t slv_reg30 <= slv_reg30;
\t slv_reg31 <= slv_reg31;
\t end
\t endcase
\t end
\t end
\tend
\t// Implement write response logic generation
\t// The write response and response valid signals are asserted by the slave
\t// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
\t// This marks the acceptance of address and indicates the status of
\t// write transaction.
\talways @( posedge S_AXI_ACLK )
\tbegin
\t if ( S_AXI_ARESETN == 1'b0 )
\t begin
\t axi_bvalid <= 0;
\t axi_bresp <= 2'b0;
\t end
\t else
\t begin
\t if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
\t begin
\t // indicates a valid write response is available
\t axi_bvalid <= 1'b1;
\t axi_bresp <= 2'b0; // 'OKAY' response
\t end // work error responses in future
\t else
\t begin
\t if (S_AXI_BREADY && axi_bvalid)
\t //check if bready is asserted while bvalid is high)
\t //(there is a possibility that bready is always asserted high)
\t begin
\t axi_bvalid <= 1'b0;
\t end
\t end
\t end
\tend
\t// Implement axi_arready generation
\t// axi_arready is asserted for one S_AXI_ACLK clock cycle when
\t// S_AXI_ARVALID is asserted. axi_awready is
\t// de-asserted when reset (active low) is asserted.
\t// The read address is also latched when S_AXI_ARVALID is
\t// asserted. axi_araddr is reset to zero on reset assertion.
\talways @( posedge S_AXI_ACLK )
\tbegin
\t if ( S_AXI_ARESETN == 1'b0 )
\t begin
\t axi_arready <= 1'b0;
\t axi_araddr <= 32'b0;
\t end
\t else
\t begin
\t if (~axi_arready && S_AXI_ARVALID)
\t begin
\t // indicates that the slave has acceped the valid read address
\t axi_arready <= 1'b1;
\t // Read address latching
\t axi_araddr <= S_AXI_ARADDR;
\t end
\t else
\t begin
\t axi_arready <= 1'b0;
\t end
\t end
\tend
\t// Implement axi_arvalid generation
\t// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
\t// S_AXI_ARVALID and axi_arready are asserted. The slave registers
\t// data are available on the axi_rdata bus at this instance. The
\t// assertion of axi_rvalid marks the validity of read data on the
\t// bus and axi_rresp indicates the status of read transaction.axi_rvalid
\t// is deasserted on reset (active low). axi_rresp and axi_rdata are
\t// cleared to zero on reset (active low).
\talways @( posedge S_AXI_ACLK )
\tbegin
\t if ( S_AXI_ARESETN == 1'b0 )
\t begin
\t axi_rvalid <= 0;
\t axi_rresp <= 0;
\t end
\t else
\t begin
\t if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
\t begin
\t // Valid read data is available at the read data bus
\t axi_rvalid <= 1'b1;
\t axi_rresp <= 2'b0; // 'OKAY' response
\t end
\t else if (axi_rvalid && S_AXI_RREADY)
\t begin
\t // Read data is accepted by the master
\t axi_rvalid <= 1'b0;
\t end
\t end
\tend
\t// Implement memory mapped register select and read logic generation
\t// Slave register read enable is asserted when valid address is available
\t// and the slave is ready to accept the read address.
\tassign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
\talways @(*)
\tbegin
\t // Address decoding for reading registers
\t case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
\t 5'h00 : reg_data_out <= slv_reg0;
\t 5'h01 : reg_data_out <= slv_reg1;
\t 5'h02 : reg_data_out <= slv_reg2;
\t 5'h03 : reg_data_out <= slv_reg3;
\t 5'h04 : reg_data_out <= slv_reg4;
\t 5'h05 : reg_data_out <= slv_reg5;
\t 5'h06 : reg_data_out <= slv_reg6;
\t 5'h07 : reg_data_out <= slv_reg7;
\t 5'h08 : reg_data_out <= slv_reg8;
\t 5'h09 : reg_data_out <= slv_reg9;
\t 5'h0A : reg_data_out <= slv_reg10;
\t 5'h0B : reg_data_out <= slv_reg11;
\t 5'h0C : reg_data_out <= slv_reg12;
\t 5'h0D : reg_data_out <= slv_reg13;
\t 5'h0E : reg_data_out <= slv_reg14;
\t 5'h0F : reg_data_out <= slv_reg15;
\t 5'h10 : reg_data_out <= slv_reg16;
\t 5'h11 : reg_data_out <= slv_reg17;
\t 5'h12 : reg_data_out <= slv_reg18;
\t 5'h13 : reg_data_out <= slv_reg19;
\t 5'h14 : reg_data_out <= slv_reg20;
\t 5'h15 : reg_data_out <= slv_reg21;
\t 5'h16 : reg_data_out <= slv_reg22;
\t 5'h17 : reg_data_out <= slv_reg23;
\t 5'h18 : reg_data_out <= slv_reg24;
\t 5'h19 : reg_data_out <= slv_reg25;
\t 5'h1A : reg_data_out <= slv_reg26;
\t 5'h1B : reg_data_out <= slv_reg27;
\t 5'h1C : reg_data_out <= slv_reg28;
\t 5'h1D : reg_data_out <= slv_reg29;
\t 5'h1E : reg_data_out <= slv_reg30;
\t 5'h1F : reg_data_out <= slv_reg31;
\t default : reg_data_out <= 0;
\t endcase
\tend
\t// Output register or memory read data
\talways @( posedge S_AXI_ACLK )
\tbegin
\t if ( S_AXI_ARESETN == 1'b0 )
\t begin
\t axi_rdata <= 0;
\t end
\t else
\t begin
\t // When there is a valid read address (S_AXI_ARVALID) with
\t // acceptance of read address by the slave (axi_arready),
\t // output the read dada
\t if (slv_reg_rden)
\t begin
\t axi_rdata <= reg_data_out; // register read data
\t end
\t end
\tend
\t// Add user logic here
\tassign th_mode = slv_reg1;
\tassign th1 = slv_reg2;
\tassign th2 = slv_reg3;
\tassign ct_scale = slv_reg4;
\tassign lm_gain = slv_reg5;
\tassign rank = slv_reg6;
\tassign ed_mode = slv_reg7;
\tassign ed_template = slv_reg8;
\tassign mt_template = slv_reg9;
\tassign crop_top = slv_reg10;
\tassign crop_bottom = slv_reg11;
\tassign crop_left = slv_reg12;
\tassign crop_right = slv_reg13;
\tassign mirror_mode = slv_reg14;
\tassign offset_x = slv_reg15;
\tassign offset_y = slv_reg16;
\tassign scale_x = slv_reg17;
\tassign scale_y = slv_reg18;
\tassign sh_u = slv_reg19;
\tassign sh_v = slv_reg20;
\tassign angle = slv_reg21;
\tassign sels = slv_reg31;
\treg[15 : 0] con_init;
\tinitial con_init = 0;
\talways @(posedge S_AXI_ACLK or negedge S_AXI_ARESETN or negedge rst_n or negedge pll_locked) begin
\t\tif(~rst_n || ~pll_locked || ~S_AXI_ARESETN)
\t\t\tcon_init <= 0;
\t\telse if(con_init == slv_reg0)
\t\t\tcon_init <= con_init;
\t\telse
\t\t\tcon_init <= con_init + 1;
\tend
\tassign rst_all_n = con_init == slv_reg0 ? 1 : 0;
\t// User logic ends
\tendmodule
|
/*
:Project
FPGA-Imaging-Library
:Design
FixedRoundSigned
:Function
Round for signed fixed number.
Give the first output after 3 cycles.
:Module
Main module
:Version
1.0
:Modified
2015-05-16
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module FixedRoundSigned2(
\tclk,
\tfixed_num,
\tround
\t);
\tparameter num_width = 42;
\tparameter fixed_pos = 16;
\tparameter res_width = 12;
\tinput clk;
\tinput signed [num_width - 1 : 0] fixed_num;
\toutput reg signed [res_width : 0] round;
\treg signed [num_width - 1 : 0] num_orig;
\treg num_orig_sflag, num_orig_rflag;
\treg signed [res_width : 0] num_comp;
\talways @(posedge clk) begin
\t\tnum_orig <= fixed_num[num_width - 1] == 0 ? fixed_num :
\t\t\t{fixed_num[num_width - 1], ~(fixed_num[num_width - 2 : 0] - 1)};
\t\tnum_comp <= num_orig[num_width - 1] == 0 ?
\t\t\t{num_orig[num_width - 1], num_orig[res_width + fixed_pos - 1 : fixed_pos]} :
\t\t\t{num_orig[num_width - 1], ~num_orig[res_width + fixed_pos - 1 : fixed_pos] + 1};
\t\tnum_orig_sflag <= num_orig[num_width - 1];
\t\tnum_orig_rflag <= num_orig[fixed_pos - 1];
\t\t//Why not use num_comp[25] to judge? : if 0
\t\tcase(num_orig_sflag)
\t\t\t0 : round <= num_orig_rflag == 0 ? num_comp : num_comp + 1;
\t\t\t1 : round <= num_orig_rflag == 0 ? num_comp : num_comp - 1;
\t\t\tdefault : /* default */;
\t\tendcase
\tend
endmodule
|
/*
Image processing project : Rotate.
Function: Rotating an image by your given angle.
LUT for cos(angle).
Copyright (C) 2015 Dai Tianyu (dtysky)
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://ifl.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module CosLUT(angle, value);
\tinput[8 : 0] angle;
\toutput[19 : 0] value;
\treg[19 : 0] reg_value;
\tassign value = reg_value;
\talways@(*) begin
\t\tcase(angle)
\t\t\t0 : reg_value <= 20'b01000000000000000000;
\t\t\t1 : reg_value <= 20'b00111111111111011000;
\t\t\t2 : reg_value <= 20'b00111111111101100000;
\t\t\t3 : reg_value <= 20'b00111111111010011000;
\t\t\t4 : reg_value <= 20'b00111111110110000001;
\t\t\t5 : reg_value <= 20'b00111111110000011010;
\t\t\t6 : reg_value <= 20'b00111111101001100011;
\t\t\t7 : reg_value <= 20'b00111111100001011101;
\t\t\t8 : reg_value <= 20'b00111111011000001000;
\t\t\t9 : reg_value <= 20'b00111111001101100100;
\t\t\t10 : reg_value <= 20'b00111111000001110001;
\t\t\t11 : reg_value <= 20'b00111110110100101111;
\t\t\t12 : reg_value <= 20'b00111110100110011111;
\t\t\t13 : reg_value <= 20'b00111110010111000001;
\t\t\t14 : reg_value <= 20'b00111110000110010101;
\t\t\t15 : reg_value <= 20'b00111101110100011011;
\t\t\t16 : reg_value <= 20'b00111101100001010101;
\t\t\t17 : reg_value <= 20'b00111101001101000001;
\t\t\t18 : reg_value <= 20'b00111100110111100001;
\t\t\t19 : reg_value <= 20'b00111100100000110110;
\t\t\t20 : reg_value <= 20'b00111100001000111110;
\t\t\t21 : reg_value <= 20'b00111011101111111100;
\t\t\t22 : reg_value <= 20'b00111011010101101111;
\t\t\t23 : reg_value <= 20'b00111010111010011000;
\t\t\t24 : reg_value <= 20'b00111010011101111000;
\t\t\t25 : reg_value <= 20'b00111010000000001111;
\t\t\t26 : reg_value <= 20'b00111001100001011101;
\t\t\t27 : reg_value <= 20'b00111001000001100100;
\t\t\t28 : reg_value <= 20'b00111000100000100011;
\t\t\t29 : reg_value <= 20'b00110111111110011100;
\t\t\t30 : reg_value <= 20'b00110111011011001111;
\t\t\t31 : reg_value <= 20'b00110110110110111101;
\t\t\t32 : reg_value <= 20'b00110110010001100110;
\t\t\t33 : reg_value <= 20'b00110101101011001100;
\t\t\t34 : reg_value <= 20'b00110101000011101111;
\t\t\t35 : reg_value <= 20'b00110100011011001111;
\t\t\t36 : reg_value <= 20'b00110011110001101110;
\t\t\t37 : reg_value <= 20'b00110011000111001101;
\t\t\t38 : reg_value <= 20'b00110010011011101100;
\t\t\t39 : reg_value <= 20'b00110001101111001100;
\t\t\t40 : reg_value <= 20'b00110001000001101101;
\t\t\t41 : reg_value <= 20'b00110000010011010010;
\t\t\t42 : reg_value <= 20'b00101111100011111011;
\t\t\t43 : reg_value <= 20'b00101110110011101000;
\t\t\t44 : reg_value <= 20'b00101110000010011010;
\t\t\t45 : reg_value <= 20'b00101101010000010011;
\t\t\t46 : reg_value <= 20'b00101100011101010100;
\t\t\t47 : reg_value <= 20'b00101011101001011101;
\t\t\t48 : reg_value <= 20'b00101010110100110000;
\t\t\t49 : reg_value <= 20'b00101001111111001101;
\t\t\t50 : reg_value <= 20'b00101001001000110111;
\t\t\t51 : reg_value <= 20'b00101000010001101100;
\t\t\t52 : reg_value <= 20'b00100111011001101111;
\t\t\t53 : reg_value <= 20'b00100110100001000010;
\t\t\t54 : reg_value <= 20'b00100101100111100100;
\t\t\t55 : reg_value <= 20'b00100100101101010111;
\t\t\t56 : reg_value <= 20'b00100011110010011101;
\t\t\t57 : reg_value <= 20'b00100010110110110101;
\t\t\t58 : reg_value <= 20'b00100001111010100011;
\t\t\t59 : reg_value <= 20'b00100000111101100110;
\t\t\t60 : reg_value <= 20'b00100000000000000000;
\t\t\t61 : reg_value <= 20'b00011111000001110010;
\t\t\t62 : reg_value <= 20'b00011110000010111101;
\t\t\t63 : reg_value <= 20'b00011101000011100010;
\t\t\t64 : reg_value <= 20'b00011100000011100100;
\t\t\t65 : reg_value <= 20'b00011011000011000010;
\t\t\t66 : reg_value <= 20'b00011010000001111111;
\t\t\t67 : reg_value <= 20'b00011001000000011011;
\t\t\t68 : reg_value <= 20'b00010111111110011000;
\t\t\t69 : reg_value <= 20'b00010110111011111000;
\t\t\t70 : reg_value <= 20'b00010101111000111010;
\t\t\t71 : reg_value <= 20'b00010100110101100001;
\t\t\t72 : reg_value <= 20'b00010011110001101110;
\t\t\t73 : reg_value <= 20'b00010010101101100011;
\t\t\t74 : reg_value <= 20'b00010001101001000000;
\t\t\t75 : reg_value <= 20'b00010000100100000111;
\t\t\t76 : reg_value <= 20'b00001111011110111010;
\t\t\t77 : reg_value <= 20'b00001110011001011001;
\t\t\t78 : reg_value <= 20'b00001101010011100110;
\t\t\t79 : reg_value <= 20'b00001100001101100011;
\t\t\t80 : reg_value <= 20'b00001011000111010000;
\t\t\t81 : reg_value <= 20'b00001010000000110000;
\t\t\t82 : reg_value <= 20'b00001000111010000011;
\t\t\t83 : reg_value <= 20'b00000111110011001011;
\t\t\t84 : reg_value <= 20'b00000110101100001001;
\t\t\t85 : reg_value <= 20'b00000101100100111111;
\t\t\t86 : reg_value <= 20'b00000100011101101110;
\t\t\t87 : reg_value <= 20'b00000011010110010111;
\t\t\t88 : reg_value <= 20'b00000010001110111100;
\t\t\t89 : reg_value <= 20'b00000001000111011110;
\t\t\t90 : reg_value <= 20'b00000000000000000000;
\t\t\t91 : reg_value <= 20'b11111110111000100010;
\t\t\t92 : reg_value <= 20'b11111101110001000100;
\t\t\t93 : reg_value <= 20'b11111100101001101001;
\t\t\t94 : reg_value <= 20'b11111011100010010010;
\t\t\t95 : reg_value <= 20'b11111010011011000001;
\t\t\t96 : reg_value <= 20'b11111001010011110111;
\t\t\t97 : reg_value <= 20'b11111000001100110101;
\t\t\t98 : reg_value <= 20'b11110111000101111101;
\t\t\t99 : reg_value <= 20'b11110101111111010000;
\t\t\t100 : reg_value <= 20'b11110100111000110000;
\t\t\t101 : reg_value <= 20'b11110011110010011101;
\t\t\t102 : reg_value <= 20'b11110010101100011010;
\t\t\t103 : reg_value <= 20'b11110001100110100111;
\t\t\t104 : reg_value <= 20'b11110000100001000110;
\t\t\t105 : reg_value <= 20'b11101111011011111001;
\t\t\t106 : reg_value <= 20'b11101110010111000000;
\t\t\t107 : reg_value <= 20'b11101101010010011101;
\t\t\t108 : reg_value <= 20'b11101100001110010010;
\t\t\t109 : reg_value <= 20'b11101011001010011111;
\t\t\t110 : reg_value <= 20'b11101010000111000110;
\t\t\t111 : reg_value <= 20'b11101001000100001000;
\t\t\t112 : reg_value <= 20'b11101000000001101000;
\t\t\t113 : reg_value <= 20'b11100110111111100101;
\t\t\t114 : reg_value <= 20'b11100101111110000001;
\t\t\t115 : reg_value <= 20'b11100100111100111110;
\t\t\t116 : reg_value <= 20'b11100011111100011100;
\t\t\t117 : reg_value <= 20'b11100010111100011110;
\t\t\t118 : reg_value <= 20'b11100001111101000011;
\t\t\t119 : reg_value <= 20'b11100000111110001110;
\t\t\t120 : reg_value <= 20'b11100000000000000000;
\t\t\t121 : reg_value <= 20'b11011111000010011010;
\t\t\t122 : reg_value <= 20'b11011110000101011101;
\t\t\t123 : reg_value <= 20'b11011101001001001011;
\t\t\t124 : reg_value <= 20'b11011100001101100011;
\t\t\t125 : reg_value <= 20'b11011011010010101001;
\t\t\t126 : reg_value <= 20'b11011010011000011100;
\t\t\t127 : reg_value <= 20'b11011001011110111110;
\t\t\t128 : reg_value <= 20'b11011000100110010001;
\t\t\t129 : reg_value <= 20'b11010111101110010100;
\t\t\t130 : reg_value <= 20'b11010110110111001001;
\t\t\t131 : reg_value <= 20'b11010110000000110011;
\t\t\t132 : reg_value <= 20'b11010101001011010000;
\t\t\t133 : reg_value <= 20'b11010100010110100011;
\t\t\t134 : reg_value <= 20'b11010011100010101100;
\t\t\t135 : reg_value <= 20'b11010010101111101101;
\t\t\t136 : reg_value <= 20'b11010001111101100110;
\t\t\t137 : reg_value <= 20'b11010001001100011000;
\t\t\t138 : reg_value <= 20'b11010000011100000101;
\t\t\t139 : reg_value <= 20'b11001111101100101110;
\t\t\t140 : reg_value <= 20'b11001110111110010011;
\t\t\t141 : reg_value <= 20'b11001110010000110100;
\t\t\t142 : reg_value <= 20'b11001101100100010100;
\t\t\t143 : reg_value <= 20'b11001100111000110011;
\t\t\t144 : reg_value <= 20'b11001100001110010010;
\t\t\t145 : reg_value <= 20'b11001011100100110001;
\t\t\t146 : reg_value <= 20'b11001010111100010001;
\t\t\t147 : reg_value <= 20'b11001010010100110100;
\t\t\t148 : reg_value <= 20'b11001001101110011010;
\t\t\t149 : reg_value <= 20'b11001001001001000011;
\t\t\t150 : reg_value <= 20'b11001000100100110001;
\t\t\t151 : reg_value <= 20'b11001000000001100100;
\t\t\t152 : reg_value <= 20'b11000111011111011101;
\t\t\t153 : reg_value <= 20'b11000110111110011100;
\t\t\t154 : reg_value <= 20'b11000110011110100011;
\t\t\t155 : reg_value <= 20'b11000101111111110001;
\t\t\t156 : reg_value <= 20'b11000101100010001000;
\t\t\t157 : reg_value <= 20'b11000101000101101000;
\t\t\t158 : reg_value <= 20'b11000100101010010001;
\t\t\t159 : reg_value <= 20'b11000100010000000100;
\t\t\t160 : reg_value <= 20'b11000011110111000010;
\t\t\t161 : reg_value <= 20'b11000011011111001010;
\t\t\t162 : reg_value <= 20'b11000011001000011111;
\t\t\t163 : reg_value <= 20'b11000010110010111111;
\t\t\t164 : reg_value <= 20'b11000010011110101011;
\t\t\t165 : reg_value <= 20'b11000010001011100101;
\t\t\t166 : reg_value <= 20'b11000001111001101011;
\t\t\t167 : reg_value <= 20'b11000001101000111111;
\t\t\t168 : reg_value <= 20'b11000001011001100001;
\t\t\t169 : reg_value <= 20'b11000001001011010001;
\t\t\t170 : reg_value <= 20'b11000000111110001111;
\t\t\t171 : reg_value <= 20'b11000000110010011100;
\t\t\t172 : reg_value <= 20'b11000000100111111000;
\t\t\t173 : reg_value <= 20'b11000000011110100011;
\t\t\t174 : reg_value <= 20'b11000000010110011101;
\t\t\t175 : reg_value <= 20'b11000000001111100110;
\t\t\t176 : reg_value <= 20'b11000000001001111111;
\t\t\t177 : reg_value <= 20'b11000000000101101000;
\t\t\t178 : reg_value <= 20'b11000000000010100000;
\t\t\t179 : reg_value <= 20'b11000000000000101000;
\t\t\t180 : reg_value <= 20'b11000000000000000000;
\t\t\t181 : reg_value <= 20'b11000000000000101000;
\t\t\t182 : reg_value <= 20'b11000000000010100000;
\t\t\t183 : reg_value <= 20'b11000000000101101000;
\t\t\t184 : reg_value <= 20'b11000000001001111111;
\t\t\t185 : reg_value <= 20'b11000000001111100110;
\t\t\t186 : reg_value <= 20'b11000000010110011101;
\t\t\t187 : reg_value <= 20'b11000000011110100011;
\t\t\t188 : reg_value <= 20'b11000000100111111000;
\t\t\t189 : reg_value <= 20'b11000000110010011100;
\t\t\t190 : reg_value <= 20'b11000000111110001111;
\t\t\t191 : reg_value <= 20'b11000001001011010001;
\t\t\t192 : reg_value <= 20'b11000001011001100001;
\t\t\t193 : reg_value <= 20'b11000001101000111111;
\t\t\t194 : reg_value <= 20'b11000001111001101011;
\t\t\t195 : reg_value <= 20'b11000010001011100101;
\t\t\t196 : reg_value <= 20'b11000010011110101011;
\t\t\t197 : reg_value <= 20'b11000010110010111111;
\t\t\t198 : reg_value <= 20'b11000011001000011111;
\t\t\t199 : reg_value <= 20'b11000011011111001010;
\t\t\t200 : reg_value <= 20'b11000011110111000010;
\t\t\t201 : reg_value <= 20'b11000100010000000100;
\t\t\t202 : reg_value <= 20'b11000100101010010001;
\t\t\t203 : reg_value <= 20'b11000101000101101000;
\t\t\t204 : reg_value <= 20'b11000101100010001000;
\t\t\t205 : reg_value <= 20'b11000101111111110001;
\t\t\t206 : reg_value <= 20'b11000110011110100011;
\t\t\t207 : reg_value <= 20'b11000110111110011100;
\t\t\t208 : reg_value <= 20'b11000111011111011101;
\t\t\t209 : reg_value <= 20'b11001000000001100100;
\t\t\t210 : reg_value <= 20'b11001000100100110001;
\t\t\t211 : reg_value <= 20'b11001001001001000011;
\t\t\t212 : reg_value <= 20'b11001001101110011010;
\t\t\t213 : reg_value <= 20'b11001010010100110100;
\t\t\t214 : reg_value <= 20'b11001010111100010001;
\t\t\t215 : reg_value <= 20'b11001011100100110001;
\t\t\t216 : reg_value <= 20'b11001100001110010010;
\t\t\t217 : reg_value <= 20'b11001100111000110011;
\t\t\t218 : reg_value <= 20'b11001101100100010100;
\t\t\t219 : reg_value <= 20'b11001110010000110100;
\t\t\t220 : reg_value <= 20'b11001110111110010011;
\t\t\t221 : reg_value <= 20'b11001111101100101110;
\t\t\t222 : reg_value <= 20'b11010000011100000101;
\t\t\t223 : reg_value <= 20'b11010001001100011000;
\t\t\t224 : reg_value <= 20'b11010001111101100110;
\t\t\t225 : reg_value <= 20'b11010010101111101101;
\t\t\t226 : reg_value <= 20'b11010011100010101100;
\t\t\t227 : reg_value <= 20'b11010100010110100011;
\t\t\t228 : reg_value <= 20'b11010101001011010000;
\t\t\t229 : reg_value <= 20'b11010110000000110011;
\t\t\t230 : reg_value <= 20'b11010110110111001001;
\t\t\t231 : reg_value <= 20'b11010111101110010100;
\t\t\t232 : reg_value <= 20'b11011000100110010001;
\t\t\t233 : reg_value <= 20'b11011001011110111110;
\t\t\t234 : reg_value <= 20'b11011010011000011100;
\t\t\t235 : reg_value <= 20'b11011011010010101001;
\t\t\t236 : reg_value <= 20'b11011100001101100011;
\t\t\t237 : reg_value <= 20'b11011101001001001011;
\t\t\t238 : reg_value <= 20'b11011110000101011101;
\t\t\t239 : reg_value <= 20'b11011111000010011010;
\t\t\t240 : reg_value <= 20'b11100000000000000000;
\t\t\t241 : reg_value <= 20'b11100000111110001110;
\t\t\t242 : reg_value <= 20'b11100001111101000011;
\t\t\t243 : reg_value <= 20'b11100010111100011110;
\t\t\t244 : reg_value <= 20'b11100011111100011100;
\t\t\t245 : reg_value <= 20'b11100100111100111110;
\t\t\t246 : reg_value <= 20'b11100101111110000001;
\t\t\t247 : reg_value <= 20'b11100110111111100101;
\t\t\t248 : reg_value <= 20'b11101000000001101000;
\t\t\t249 : reg_value <= 20'b11101001000100001000;
\t\t\t250 : reg_value <= 20'b11101010000111000110;
\t\t\t251 : reg_value <= 20'b11101011001010011111;
\t\t\t252 : reg_value <= 20'b11101100001110010010;
\t\t\t253 : reg_value <= 20'b11101101010010011101;
\t\t\t254 : reg_value <= 20'b11101110010111000000;
\t\t\t255 : reg_value <= 20'b11101111011011111001;
\t\t\t256 : reg_value <= 20'b11110000100001000110;
\t\t\t257 : reg_value <= 20'b11110001100110100111;
\t\t\t258 : reg_value <= 20'b11110010101100011010;
\t\t\t259 : reg_value <= 20'b11110011110010011101;
\t\t\t260 : reg_value <= 20'b11110100111000110000;
\t\t\t261 : reg_value <= 20'b11110101111111010000;
\t\t\t262 : reg_value <= 20'b11110111000101111101;
\t\t\t263 : reg_value <= 20'b11111000001100110101;
\t\t\t264 : reg_value <= 20'b11111001010011110111;
\t\t\t265 : reg_value <= 20'b11111010011011000001;
\t\t\t266 : reg_value <= 20'b11111011100010010010;
\t\t\t267 : reg_value <= 20'b11111100101001101001;
\t\t\t268 : reg_value <= 20'b11111101110001000100;
\t\t\t269 : reg_value <= 20'b11111110111000100010;
\t\t\t270 : reg_value <= 20'b00000000000000000000;
\t\t\t271 : reg_value <= 20'b00000001000111011110;
\t\t\t272 : reg_value <= 20'b00000010001110111100;
\t\t\t273 : reg_value <= 20'b00000011010110010111;
\t\t\t274 : reg_value <= 20'b00000100011101101110;
\t\t\t275 : reg_value <= 20'b00000101100100111111;
\t\t\t276 : reg_value <= 20'b00000110101100001001;
\t\t\t277 : reg_value <= 20'b00000111110011001011;
\t\t\t278 : reg_value <= 20'b00001000111010000011;
\t\t\t279 : reg_value <= 20'b00001010000000110000;
\t\t\t280 : reg_value <= 20'b00001011000111010000;
\t\t\t281 : reg_value <= 20'b00001100001101100011;
\t\t\t282 : reg_value <= 20'b00001101010011100110;
\t\t\t283 : reg_value <= 20'b00001110011001011001;
\t\t\t284 : reg_value <= 20'b00001111011110111010;
\t\t\t285 : reg_value <= 20'b00010000100100000111;
\t\t\t286 : reg_value <= 20'b00010001101001000000;
\t\t\t287 : reg_value <= 20'b00010010101101100011;
\t\t\t288 : reg_value <= 20'b00010011110001101110;
\t\t\t289 : reg_value <= 20'b00010100110101100001;
\t\t\t290 : reg_value <= 20'b00010101111000111010;
\t\t\t291 : reg_value <= 20'b00010110111011111000;
\t\t\t292 : reg_value <= 20'b00010111111110011000;
\t\t\t293 : reg_value <= 20'b00011001000000011011;
\t\t\t294 : reg_value <= 20'b00011010000001111111;
\t\t\t295 : reg_value <= 20'b00011011000011000010;
\t\t\t296 : reg_value <= 20'b00011100000011100100;
\t\t\t297 : reg_value <= 20'b00011101000011100010;
\t\t\t298 : reg_value <= 20'b00011110000010111101;
\t\t\t299 : reg_value <= 20'b00011111000001110010;
\t\t\t300 : reg_value <= 20'b00100000000000000000;
\t\t\t301 : reg_value <= 20'b00100000111101100110;
\t\t\t302 : reg_value <= 20'b00100001111010100011;
\t\t\t303 : reg_value <= 20'b00100010110110110101;
\t\t\t304 : reg_value <= 20'b00100011110010011101;
\t\t\t305 : reg_value <= 20'b00100100101101010111;
\t\t\t306 : reg_value <= 20'b00100101100111100100;
\t\t\t307 : reg_value <= 20'b00100110100001000010;
\t\t\t308 : reg_value <= 20'b00100111011001101111;
\t\t\t309 : reg_value <= 20'b00101000010001101100;
\t\t\t310 : reg_value <= 20'b00101001001000110111;
\t\t\t311 : reg_value <= 20'b00101001111111001101;
\t\t\t312 : reg_value <= 20'b00101010110100110000;
\t\t\t313 : reg_value <= 20'b00101011101001011101;
\t\t\t314 : reg_value <= 20'b00101100011101010100;
\t\t\t315 : reg_value <= 20'b00101101010000010011;
\t\t\t316 : reg_value <= 20'b00101110000010011010;
\t\t\t317 : reg_value <= 20'b00101110110011101000;
\t\t\t318 : reg_value <= 20'b00101111100011111011;
\t\t\t319 : reg_value <= 20'b00110000010011010010;
\t\t\t320 : reg_value <= 20'b00110001000001101101;
\t\t\t321 : reg_value <= 20'b00110001101111001100;
\t\t\t322 : reg_value <= 20'b00110010011011101100;
\t\t\t323 : reg_value <= 20'b00110011000111001101;
\t\t\t324 : reg_value <= 20'b00110011110001101110;
\t\t\t325 : reg_value <= 20'b00110100011011001111;
\t\t\t326 : reg_value <= 20'b00110101000011101111;
\t\t\t327 : reg_value <= 20'b00110101101011001100;
\t\t\t328 : reg_value <= 20'b00110110010001100110;
\t\t\t329 : reg_value <= 20'b00110110110110111101;
\t\t\t330 : reg_value <= 20'b00110111011011001111;
\t\t\t331 : reg_value <= 20'b00110111111110011100;
\t\t\t332 : reg_value <= 20'b00111000100000100011;
\t\t\t333 : reg_value <= 20'b00111001000001100100;
\t\t\t334 : reg_value <= 20'b00111001100001011101;
\t\t\t335 : reg_value <= 20'b00111010000000001111;
\t\t\t336 : reg_value <= 20'b00111010011101111000;
\t\t\t337 : reg_value <= 20'b00111010111010011000;
\t\t\t338 : reg_value <= 20'b00111011010101101111;
\t\t\t339 : reg_value <= 20'b00111011101111111100;
\t\t\t340 : reg_value <= 20'b00111100001000111110;
\t\t\t341 : reg_value <= 20'b00111100100000110110;
\t\t\t342 : reg_value <= 20'b00111100110111100001;
\t\t\t343 : reg_value <= 20'b00111101001101000001;
\t\t\t344 : reg_value <= 20'b00111101100001010101;
\t\t\t345 : reg_value <= 20'b00111101110100011011;
\t\t\t346 : reg_value <= 20'b00111110000110010101;
\t\t\t347 : reg_value <= 20'b00111110010111000001;
\t\t\t348 : reg_value <= 20'b00111110100110011111;
\t\t\t349 : reg_value <= 20'b00111110110100101111;
\t\t\t350 : reg_value <= 20'b00111111000001110001;
\t\t\t351 : reg_value <= 20'b00111111001101100100;
\t\t\t352 : reg_value <= 20'b00111111011000001000;
\t\t\t353 : reg_value <= 20'b00111111100001011101;
\t\t\t354 : reg_value <= 20'b00111111101001100011;
\t\t\t355 : reg_value <= 20'b00111111110000011010;
\t\t\t356 : reg_value <= 20'b00111111110110000001;
\t\t\t357 : reg_value <= 20'b00111111111010011000;
\t\t\t358 : reg_value <= 20'b00111111111101100000;
\t\t\t359 : reg_value <= 20'b00111111111111011000;
\t\t\tdefault: reg_value <= 0;
\t\tendcase
\tend
endmodule
|
/*
:Project
FPGA-Imaging-Library
:Design
ColorRGB24toVGA
:Function
Covert 24bits-RGB to VGA.
:Module
Main module
:Version
1.0
:Modified
2015-05-12
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module ColorRGB24toVGA(
\tinput[23:0] rgb24,
\toutput[15:0] vga
);
\tassign vga[15:11] = rgb24[23:19];
\tassign vga[10:5] = rgb24[15:10];
\tassign vga[4:0] = rgb24[7:3];
endmodule
|
module Encoder(index, value);
\tparameter window_width = 3;
\tparameter full_win_bits = 4;
\tinput[window_width * window_width - 1 : 0] index;
\toutput[full_win_bits - 1 : 0] value;
\treg[full_win_bits - 1 : 0] reg_value;
\tassign value = reg_value;
\tgenerate
\t\tcase(window_width)
\t\t\t2 :
\t\t\t\talways@(*) begin
\t\t\t\t\tcase(index)
\t\t\t\t\t\t1 : reg_value <= 0;
\t\t\t\t\t\t2 : reg_value <= 1;
\t\t\t\t\t\t4 : reg_value <= 2;
\t\t\t\t\t\t8 : reg_value <= 3;
\t\t\t\t\t\tdefault: reg_value <= 0;
\t\t\t\t\tendcase
\t\t\t\tend
\t\t\t3 :
\t\t\t\talways@(*) begin
\t\t\t\t\tcase(index)
\t\t\t\t\t\t1 : reg_value <= 0;
\t\t\t\t\t\t2 : reg_value <= 1;
\t\t\t\t\t\t4 : reg_value <= 2;
\t\t\t\t\t\t8 : reg_value <= 3;
\t\t\t\t\t\t16 : reg_value <= 4;
\t\t\t\t\t\t32 : reg_value <= 5;
\t\t\t\t\t\t64 : reg_value <= 6;
\t\t\t\t\t\t128 : reg_value <= 7;
\t\t\t\t\t\t256 : reg_value <= 8;
\t\t\t\t\t\tdefault: reg_value <= 0;
\t\t\t\t\tendcase
\t\t\t\tend
\t\t\t4 :
\t\t\t\talways@(*) begin
\t\t\t\t\tcase(index)
\t\t\t\t\t\t1 : reg_value <= 0;
\t\t\t\t\t\t2 : reg_value <= 1;
\t\t\t\t\t\t4 : reg_value <= 2;
\t\t\t\t\t\t8 : reg_value <= 3;
\t\t\t\t\t\t16 : reg_value <= 4;
\t\t\t\t\t\t32 : reg_value <= 5;
\t\t\t\t\t\t64 : reg_value <= 6;
\t\t\t\t\t\t128 : reg_value <= 7;
\t\t\t\t\t\t256 : reg_value <= 8;
\t\t\t\t\t\t512 : reg_value <= 9;
\t\t\t\t\t\t1024 : reg_value <= 10;
\t\t\t\t\t\t2048 : reg_value <= 11;
\t\t\t\t\t\t4096 : reg_value <= 12;
\t\t\t\t\t\t8192 : reg_value <= 13;
\t\t\t\t\t\t16384 : reg_value <= 14;
\t\t\t\t\t\t32768 : reg_value <= 15;
\t\t\t\t\t\tdefault: reg_value <= 0;
\t\t\t\t\tendcase
\t\t\t\tend
\t\t\t5 :
\t\t\t\talways@(*) begin
\t\t\t\t\tcase(index)
\t\t\t\t\t\t1 : reg_value <= 0;
\t\t\t\t\t\t2 : reg_value <= 1;
\t\t\t\t\t\t4 : reg_value <= 2;
\t\t\t\t\t\t8 : reg_value <= 3;
\t\t\t\t\t\t16 : reg_value <= 4;
\t\t\t\t\t\t32 : reg_value <= 5;
\t\t\t\t\t\t64 : reg_value <= 6;
\t\t\t\t\t\t128 : reg_value <= 7;
\t\t\t\t\t\t256 : reg_value <= 8;
\t\t\t\t\t\t512 : reg_value <= 9;
\t\t\t\t\t\t1024 : reg_value <= 10;
\t\t\t\t\t\t2048 : reg_value <= 11;
\t\t\t\t\t\t4096 : reg_value <= 12;
\t\t\t\t\t\t8192 : reg_value <= 13;
\t\t\t\t\t\t16384 : reg_value <= 14;
\t\t\t\t\t\t32768 : reg_value <= 15;
\t\t\t\t\t\t65536 : reg_value <= 16;
\t\t\t\t\t\t131072 : reg_value <= 17;
\t\t\t\t\t\t262144 : reg_value <= 18;
\t\t\t\t\t\t524288 : reg_value <= 19;
\t\t\t\t\t\t1048576 : reg_value <= 20;
\t\t\t\t\t\t2097152 : reg_value <= 21;
\t\t\t\t\t\t4194304 : reg_value <= 22;
\t\t\t\t\t\t8388608 : reg_value <= 23;
\t\t\t\t\t\t16777216 : reg_value <= 24;
\t\t\t\t\t\tdefault: reg_value <= 0;
\t\t\t\t\tendcase
\t\t\t\tend
\t\t\tdefault : ;
\t\tendcase
\tendgenerate
endmodule\t
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
Crop
:Function
Cropping images, depending on your top, bottom, left and right coordinate.
Give the first output after 1 cycle while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-25
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module Crop(
\tclk,
\trst_n,
\ttop,
\tbottom,
\tleft,
\tright,
\tin_enable,
\tin_data,
\tin_count_x,
\tin_count_y,
\tout_ready,
\tout_data,
\tout_count_x,
\tout_count_y);
\t/*
\t::description
\tThis module's working mode.
\t::range
\t0 for Pipline, 1 for Req-ack
\t*/
\tparameter work_mode = 0;
\t/*
\t::description
\tData bit width.
\t*/
\tparameter data_width = 8;
\t/*
\t::description
\tWidth of image.
\t::range
\t1 - 4096
\t*/
\tparameter im_width = 320;
\t/*
\t::description
\tHeight of image.
\t::range
\t1 - 4096
\t*/
\tparameter im_height = 240;
\t/*
\t::description
\tThe bits of width of image.
\t::range
\tDepend on width of image
\t*/
\tparameter im_width_bits = 9;
\t/*
\t::description
\tClock.
\t*/
\tinput clk;
\t/*
\t::description
\tReset, active low.
\t*/
\tinput rst_n;
\t/*
\t::description
\tTop of the rang you want to crop.
\t::range
\tDepend on height of image, 0 - im_height-1.
\t*/
\tinput[im_width_bits - 1 : 0] top;
\t/*
\t::description
\tBottom of the rang you want to crop.
\t::range
\tDepend on height of image, 0 - im_height-1.
\t*/
\tinput[im_width_bits - 1 : 0] bottom;
\t/*
\t::description
\tLeft of the rang you want to crop.
\t::range
\tDepend on height of image, 0 - im_width-1.
\t*/
\tinput[im_width_bits - 1 : 0] left;
\t/*
\t::description
\tRight of the rang you want to crop.
\t::range
\tDepend on height of image, 0 - im_width-1.
\t*/
\tinput[im_width_bits - 1 : 0] right;
\t/*
\t::description
\tInput data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
\t*/
\tinput in_enable;
\t/*
\t::description
\tInput data, it must be synchronous with in_enable.
\t*/
\tinput [data_width - 1 : 0] in_data;
\t/*
\t::description
\tInput pixel count for width.
\t*/
\tinput[im_width_bits - 1 : 0] in_count_x;
\t/*
\t::description
\tInput pixel count for height.
\t*/
\tinput[im_width_bits - 1 : 0] in_count_y;
\t/*
\t::description
\tOutput data ready, in both two mode, it will be high while the out_data can be read.
\t*/
\toutput out_ready;
\t/*
\t::description
\tOutput data, it will be synchronous with out_ready.
\t*/
\toutput[data_width - 1 : 0] out_data;
\t/*
\t::description
\tOutput pixel count for height.
\t*/
\toutput[im_width_bits - 1 : 0] out_count_x;
\t/*
\t::description
\tOutput pixel count for height.
\t*/
\toutput[im_width_bits - 1 : 0] out_count_y;
\tgenerate
\t\treg[im_width_bits - 1 : 0] reg_out_count_x;
\t\treg[im_width_bits - 1 : 0] reg_out_count_y;
\t\treg[data_width - 1 : 0] reg_out_data;
\t\treg reg_out_ready;
\t\treg in_range_t, in_range_b, in_range_l, in_range_r;
\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\tif(~rst_n || ~in_enable)
\t\t\t\treg_out_ready <= 0;
\t\t\telse
\t\t\t\treg_out_ready <= 1;
\t\tend
\t\tassign out_ready = reg_out_ready;
\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\tif(~rst_n || ~in_enable) begin
\t\t\t\tin_range_t <= 0;
\t\t\t\tin_range_b <= 0;
\t\t\t\tin_range_l <= 0;
\t\t\t\tin_range_r <= 0;
\t\t\tend else begin
\t\t\t\tin_range_t <= in_count_y >= top ? 1 : 0;
\t\t\t\tin_range_b <= in_count_y <= bottom ? 1 : 0;
\t\t\t\tin_range_l <= in_count_x >= left ? 1 : 0;
\t\t\t\tin_range_r <= in_count_x <= right ? 1 : 0;
\t\t\tend
\t\tend
\t\tif(work_mode == 0) begin
\t\t\talways @(posedge clk) begin
\t\t\t\treg_out_count_x <= in_count_x;
\t\t\t\treg_out_count_y <= in_count_y;
\t\t\t\treg_out_data <= in_data;
\t\t\tend
\t\tend else begin
\t\t\talways @(posedge in_enable) begin
\t\t\t\treg_out_count_x <= in_count_x;
\t\t\t\treg_out_count_y <= in_count_y;
\t\t\t\treg_out_data <= in_data;
\t\t\tend
\t\tend
\t\tassign out_count_x = reg_out_count_x;
\t\tassign out_count_y = reg_out_count_y;
\t\tassign out_data = out_ready & in_range_t & in_range_b & in_range_l & in_range_r ? reg_out_data : 0;
\tendgenerate
\t
endmodule
|
/*
:Project
FPGA-Imaging-Library
:Design
ColorRGB16toRGB24
:Function
Covert 16bits-RGB to 24bits-RGB.
:Module
Main module
:Version
1.0
:Modified
2015-05-12
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module ColorRGB16toRGB24(
\tinput[15 : 0] rgb16,
\toutput[23 : 0] rgb24
);
\tassign rgb24[23 : 16] = {rgb16[15 : 11], rgb16[15 : 13]};
\tassign rgb24[15:8] = {rgb16[10 : 5], rgb16[10 : 9]};
\tassign rgb24[7:0] = {rgb16[4 : 0], rgb16[4 : 2]};
endmodule
|
/*
Image processing project : Rotate.
Function: Rotating an image by your given angle.
LUT for sin(angle).
Copyright (C) 2015 Dai Tianyu (dtysky)
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://ifl.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module SinLUT(angle, value);
\tinput[8 : 0] angle;
\toutput[19 : 0] value;
\treg[19 : 0] reg_value;
\tassign value = reg_value;
\talways@(*) begin
\t\tcase(angle)
\t\t\t0 : reg_value <= 20'b00000000000000000000;
\t\t\t1 : reg_value <= 20'b00000001000111011110;
\t\t\t2 : reg_value <= 20'b00000010001110111100;
\t\t\t3 : reg_value <= 20'b00000011010110010111;
\t\t\t4 : reg_value <= 20'b00000100011101101110;
\t\t\t5 : reg_value <= 20'b00000101100100111111;
\t\t\t6 : reg_value <= 20'b00000110101100001001;
\t\t\t7 : reg_value <= 20'b00000111110011001011;
\t\t\t8 : reg_value <= 20'b00001000111010000011;
\t\t\t9 : reg_value <= 20'b00001010000000110000;
\t\t\t10 : reg_value <= 20'b00001011000111010000;
\t\t\t11 : reg_value <= 20'b00001100001101100011;
\t\t\t12 : reg_value <= 20'b00001101010011100110;
\t\t\t13 : reg_value <= 20'b00001110011001011001;
\t\t\t14 : reg_value <= 20'b00001111011110111010;
\t\t\t15 : reg_value <= 20'b00010000100100000111;
\t\t\t16 : reg_value <= 20'b00010001101001000000;
\t\t\t17 : reg_value <= 20'b00010010101101100011;
\t\t\t18 : reg_value <= 20'b00010011110001101110;
\t\t\t19 : reg_value <= 20'b00010100110101100001;
\t\t\t20 : reg_value <= 20'b00010101111000111010;
\t\t\t21 : reg_value <= 20'b00010110111011111000;
\t\t\t22 : reg_value <= 20'b00010111111110011000;
\t\t\t23 : reg_value <= 20'b00011001000000011011;
\t\t\t24 : reg_value <= 20'b00011010000001111111;
\t\t\t25 : reg_value <= 20'b00011011000011000010;
\t\t\t26 : reg_value <= 20'b00011100000011100100;
\t\t\t27 : reg_value <= 20'b00011101000011100010;
\t\t\t28 : reg_value <= 20'b00011110000010111101;
\t\t\t29 : reg_value <= 20'b00011111000001110010;
\t\t\t30 : reg_value <= 20'b00100000000000000000;
\t\t\t31 : reg_value <= 20'b00100000111101100110;
\t\t\t32 : reg_value <= 20'b00100001111010100011;
\t\t\t33 : reg_value <= 20'b00100010110110110101;
\t\t\t34 : reg_value <= 20'b00100011110010011101;
\t\t\t35 : reg_value <= 20'b00100100101101010111;
\t\t\t36 : reg_value <= 20'b00100101100111100100;
\t\t\t37 : reg_value <= 20'b00100110100001000010;
\t\t\t38 : reg_value <= 20'b00100111011001101111;
\t\t\t39 : reg_value <= 20'b00101000010001101100;
\t\t\t40 : reg_value <= 20'b00101001001000110111;
\t\t\t41 : reg_value <= 20'b00101001111111001101;
\t\t\t42 : reg_value <= 20'b00101010110100110000;
\t\t\t43 : reg_value <= 20'b00101011101001011101;
\t\t\t44 : reg_value <= 20'b00101100011101010100;
\t\t\t45 : reg_value <= 20'b00101101010000010011;
\t\t\t46 : reg_value <= 20'b00101110000010011010;
\t\t\t47 : reg_value <= 20'b00101110110011101000;
\t\t\t48 : reg_value <= 20'b00101111100011111011;
\t\t\t49 : reg_value <= 20'b00110000010011010010;
\t\t\t50 : reg_value <= 20'b00110001000001101101;
\t\t\t51 : reg_value <= 20'b00110001101111001100;
\t\t\t52 : reg_value <= 20'b00110010011011101100;
\t\t\t53 : reg_value <= 20'b00110011000111001101;
\t\t\t54 : reg_value <= 20'b00110011110001101110;
\t\t\t55 : reg_value <= 20'b00110100011011001111;
\t\t\t56 : reg_value <= 20'b00110101000011101111;
\t\t\t57 : reg_value <= 20'b00110101101011001100;
\t\t\t58 : reg_value <= 20'b00110110010001100110;
\t\t\t59 : reg_value <= 20'b00110110110110111101;
\t\t\t60 : reg_value <= 20'b00110111011011001111;
\t\t\t61 : reg_value <= 20'b00110111111110011100;
\t\t\t62 : reg_value <= 20'b00111000100000100011;
\t\t\t63 : reg_value <= 20'b00111001000001100100;
\t\t\t64 : reg_value <= 20'b00111001100001011101;
\t\t\t65 : reg_value <= 20'b00111010000000001111;
\t\t\t66 : reg_value <= 20'b00111010011101111000;
\t\t\t67 : reg_value <= 20'b00111010111010011000;
\t\t\t68 : reg_value <= 20'b00111011010101101111;
\t\t\t69 : reg_value <= 20'b00111011101111111100;
\t\t\t70 : reg_value <= 20'b00111100001000111110;
\t\t\t71 : reg_value <= 20'b00111100100000110110;
\t\t\t72 : reg_value <= 20'b00111100110111100001;
\t\t\t73 : reg_value <= 20'b00111101001101000001;
\t\t\t74 : reg_value <= 20'b00111101100001010101;
\t\t\t75 : reg_value <= 20'b00111101110100011011;
\t\t\t76 : reg_value <= 20'b00111110000110010101;
\t\t\t77 : reg_value <= 20'b00111110010111000001;
\t\t\t78 : reg_value <= 20'b00111110100110011111;
\t\t\t79 : reg_value <= 20'b00111110110100101111;
\t\t\t80 : reg_value <= 20'b00111111000001110001;
\t\t\t81 : reg_value <= 20'b00111111001101100100;
\t\t\t82 : reg_value <= 20'b00111111011000001000;
\t\t\t83 : reg_value <= 20'b00111111100001011101;
\t\t\t84 : reg_value <= 20'b00111111101001100011;
\t\t\t85 : reg_value <= 20'b00111111110000011010;
\t\t\t86 : reg_value <= 20'b00111111110110000001;
\t\t\t87 : reg_value <= 20'b00111111111010011000;
\t\t\t88 : reg_value <= 20'b00111111111101100000;
\t\t\t89 : reg_value <= 20'b00111111111111011000;
\t\t\t90 : reg_value <= 20'b01000000000000000000;
\t\t\t91 : reg_value <= 20'b00111111111111011000;
\t\t\t92 : reg_value <= 20'b00111111111101100000;
\t\t\t93 : reg_value <= 20'b00111111111010011000;
\t\t\t94 : reg_value <= 20'b00111111110110000001;
\t\t\t95 : reg_value <= 20'b00111111110000011010;
\t\t\t96 : reg_value <= 20'b00111111101001100011;
\t\t\t97 : reg_value <= 20'b00111111100001011101;
\t\t\t98 : reg_value <= 20'b00111111011000001000;
\t\t\t99 : reg_value <= 20'b00111111001101100100;
\t\t\t100 : reg_value <= 20'b00111111000001110001;
\t\t\t101 : reg_value <= 20'b00111110110100101111;
\t\t\t102 : reg_value <= 20'b00111110100110011111;
\t\t\t103 : reg_value <= 20'b00111110010111000001;
\t\t\t104 : reg_value <= 20'b00111110000110010101;
\t\t\t105 : reg_value <= 20'b00111101110100011011;
\t\t\t106 : reg_value <= 20'b00111101100001010101;
\t\t\t107 : reg_value <= 20'b00111101001101000001;
\t\t\t108 : reg_value <= 20'b00111100110111100001;
\t\t\t109 : reg_value <= 20'b00111100100000110110;
\t\t\t110 : reg_value <= 20'b00111100001000111110;
\t\t\t111 : reg_value <= 20'b00111011101111111100;
\t\t\t112 : reg_value <= 20'b00111011010101101111;
\t\t\t113 : reg_value <= 20'b00111010111010011000;
\t\t\t114 : reg_value <= 20'b00111010011101111000;
\t\t\t115 : reg_value <= 20'b00111010000000001111;
\t\t\t116 : reg_value <= 20'b00111001100001011101;
\t\t\t117 : reg_value <= 20'b00111001000001100100;
\t\t\t118 : reg_value <= 20'b00111000100000100011;
\t\t\t119 : reg_value <= 20'b00110111111110011100;
\t\t\t120 : reg_value <= 20'b00110111011011001111;
\t\t\t121 : reg_value <= 20'b00110110110110111101;
\t\t\t122 : reg_value <= 20'b00110110010001100110;
\t\t\t123 : reg_value <= 20'b00110101101011001100;
\t\t\t124 : reg_value <= 20'b00110101000011101111;
\t\t\t125 : reg_value <= 20'b00110100011011001111;
\t\t\t126 : reg_value <= 20'b00110011110001101110;
\t\t\t127 : reg_value <= 20'b00110011000111001101;
\t\t\t128 : reg_value <= 20'b00110010011011101100;
\t\t\t129 : reg_value <= 20'b00110001101111001100;
\t\t\t130 : reg_value <= 20'b00110001000001101101;
\t\t\t131 : reg_value <= 20'b00110000010011010010;
\t\t\t132 : reg_value <= 20'b00101111100011111011;
\t\t\t133 : reg_value <= 20'b00101110110011101000;
\t\t\t134 : reg_value <= 20'b00101110000010011010;
\t\t\t135 : reg_value <= 20'b00101101010000010011;
\t\t\t136 : reg_value <= 20'b00101100011101010100;
\t\t\t137 : reg_value <= 20'b00101011101001011101;
\t\t\t138 : reg_value <= 20'b00101010110100110000;
\t\t\t139 : reg_value <= 20'b00101001111111001101;
\t\t\t140 : reg_value <= 20'b00101001001000110111;
\t\t\t141 : reg_value <= 20'b00101000010001101100;
\t\t\t142 : reg_value <= 20'b00100111011001101111;
\t\t\t143 : reg_value <= 20'b00100110100001000010;
\t\t\t144 : reg_value <= 20'b00100101100111100100;
\t\t\t145 : reg_value <= 20'b00100100101101010111;
\t\t\t146 : reg_value <= 20'b00100011110010011101;
\t\t\t147 : reg_value <= 20'b00100010110110110101;
\t\t\t148 : reg_value <= 20'b00100001111010100011;
\t\t\t149 : reg_value <= 20'b00100000111101100110;
\t\t\t150 : reg_value <= 20'b00100000000000000000;
\t\t\t151 : reg_value <= 20'b00011111000001110010;
\t\t\t152 : reg_value <= 20'b00011110000010111101;
\t\t\t153 : reg_value <= 20'b00011101000011100010;
\t\t\t154 : reg_value <= 20'b00011100000011100100;
\t\t\t155 : reg_value <= 20'b00011011000011000010;
\t\t\t156 : reg_value <= 20'b00011010000001111111;
\t\t\t157 : reg_value <= 20'b00011001000000011011;
\t\t\t158 : reg_value <= 20'b00010111111110011000;
\t\t\t159 : reg_value <= 20'b00010110111011111000;
\t\t\t160 : reg_value <= 20'b00010101111000111010;
\t\t\t161 : reg_value <= 20'b00010100110101100001;
\t\t\t162 : reg_value <= 20'b00010011110001101110;
\t\t\t163 : reg_value <= 20'b00010010101101100011;
\t\t\t164 : reg_value <= 20'b00010001101001000000;
\t\t\t165 : reg_value <= 20'b00010000100100000111;
\t\t\t166 : reg_value <= 20'b00001111011110111010;
\t\t\t167 : reg_value <= 20'b00001110011001011001;
\t\t\t168 : reg_value <= 20'b00001101010011100110;
\t\t\t169 : reg_value <= 20'b00001100001101100011;
\t\t\t170 : reg_value <= 20'b00001011000111010000;
\t\t\t171 : reg_value <= 20'b00001010000000110000;
\t\t\t172 : reg_value <= 20'b00001000111010000011;
\t\t\t173 : reg_value <= 20'b00000111110011001011;
\t\t\t174 : reg_value <= 20'b00000110101100001001;
\t\t\t175 : reg_value <= 20'b00000101100100111111;
\t\t\t176 : reg_value <= 20'b00000100011101101110;
\t\t\t177 : reg_value <= 20'b00000011010110010111;
\t\t\t178 : reg_value <= 20'b00000010001110111100;
\t\t\t179 : reg_value <= 20'b00000001000111011110;
\t\t\t180 : reg_value <= 20'b00000000000000000000;
\t\t\t181 : reg_value <= 20'b11111110111000100010;
\t\t\t182 : reg_value <= 20'b11111101110001000100;
\t\t\t183 : reg_value <= 20'b11111100101001101001;
\t\t\t184 : reg_value <= 20'b11111011100010010010;
\t\t\t185 : reg_value <= 20'b11111010011011000001;
\t\t\t186 : reg_value <= 20'b11111001010011110111;
\t\t\t187 : reg_value <= 20'b11111000001100110101;
\t\t\t188 : reg_value <= 20'b11110111000101111101;
\t\t\t189 : reg_value <= 20'b11110101111111010000;
\t\t\t190 : reg_value <= 20'b11110100111000110000;
\t\t\t191 : reg_value <= 20'b11110011110010011101;
\t\t\t192 : reg_value <= 20'b11110010101100011010;
\t\t\t193 : reg_value <= 20'b11110001100110100111;
\t\t\t194 : reg_value <= 20'b11110000100001000110;
\t\t\t195 : reg_value <= 20'b11101111011011111001;
\t\t\t196 : reg_value <= 20'b11101110010111000000;
\t\t\t197 : reg_value <= 20'b11101101010010011101;
\t\t\t198 : reg_value <= 20'b11101100001110010010;
\t\t\t199 : reg_value <= 20'b11101011001010011111;
\t\t\t200 : reg_value <= 20'b11101010000111000110;
\t\t\t201 : reg_value <= 20'b11101001000100001000;
\t\t\t202 : reg_value <= 20'b11101000000001101000;
\t\t\t203 : reg_value <= 20'b11100110111111100101;
\t\t\t204 : reg_value <= 20'b11100101111110000001;
\t\t\t205 : reg_value <= 20'b11100100111100111110;
\t\t\t206 : reg_value <= 20'b11100011111100011100;
\t\t\t207 : reg_value <= 20'b11100010111100011110;
\t\t\t208 : reg_value <= 20'b11100001111101000011;
\t\t\t209 : reg_value <= 20'b11100000111110001110;
\t\t\t210 : reg_value <= 20'b11100000000000000000;
\t\t\t211 : reg_value <= 20'b11011111000010011010;
\t\t\t212 : reg_value <= 20'b11011110000101011101;
\t\t\t213 : reg_value <= 20'b11011101001001001011;
\t\t\t214 : reg_value <= 20'b11011100001101100011;
\t\t\t215 : reg_value <= 20'b11011011010010101001;
\t\t\t216 : reg_value <= 20'b11011010011000011100;
\t\t\t217 : reg_value <= 20'b11011001011110111110;
\t\t\t218 : reg_value <= 20'b11011000100110010001;
\t\t\t219 : reg_value <= 20'b11010111101110010100;
\t\t\t220 : reg_value <= 20'b11010110110111001001;
\t\t\t221 : reg_value <= 20'b11010110000000110011;
\t\t\t222 : reg_value <= 20'b11010101001011010000;
\t\t\t223 : reg_value <= 20'b11010100010110100011;
\t\t\t224 : reg_value <= 20'b11010011100010101100;
\t\t\t225 : reg_value <= 20'b11010010101111101101;
\t\t\t226 : reg_value <= 20'b11010001111101100110;
\t\t\t227 : reg_value <= 20'b11010001001100011000;
\t\t\t228 : reg_value <= 20'b11010000011100000101;
\t\t\t229 : reg_value <= 20'b11001111101100101110;
\t\t\t230 : reg_value <= 20'b11001110111110010011;
\t\t\t231 : reg_value <= 20'b11001110010000110100;
\t\t\t232 : reg_value <= 20'b11001101100100010100;
\t\t\t233 : reg_value <= 20'b11001100111000110011;
\t\t\t234 : reg_value <= 20'b11001100001110010010;
\t\t\t235 : reg_value <= 20'b11001011100100110001;
\t\t\t236 : reg_value <= 20'b11001010111100010001;
\t\t\t237 : reg_value <= 20'b11001010010100110100;
\t\t\t238 : reg_value <= 20'b11001001101110011010;
\t\t\t239 : reg_value <= 20'b11001001001001000011;
\t\t\t240 : reg_value <= 20'b11001000100100110001;
\t\t\t241 : reg_value <= 20'b11001000000001100100;
\t\t\t242 : reg_value <= 20'b11000111011111011101;
\t\t\t243 : reg_value <= 20'b11000110111110011100;
\t\t\t244 : reg_value <= 20'b11000110011110100011;
\t\t\t245 : reg_value <= 20'b11000101111111110001;
\t\t\t246 : reg_value <= 20'b11000101100010001000;
\t\t\t247 : reg_value <= 20'b11000101000101101000;
\t\t\t248 : reg_value <= 20'b11000100101010010001;
\t\t\t249 : reg_value <= 20'b11000100010000000100;
\t\t\t250 : reg_value <= 20'b11000011110111000010;
\t\t\t251 : reg_value <= 20'b11000011011111001010;
\t\t\t252 : reg_value <= 20'b11000011001000011111;
\t\t\t253 : reg_value <= 20'b11000010110010111111;
\t\t\t254 : reg_value <= 20'b11000010011110101011;
\t\t\t255 : reg_value <= 20'b11000010001011100101;
\t\t\t256 : reg_value <= 20'b11000001111001101011;
\t\t\t257 : reg_value <= 20'b11000001101000111111;
\t\t\t258 : reg_value <= 20'b11000001011001100001;
\t\t\t259 : reg_value <= 20'b11000001001011010001;
\t\t\t260 : reg_value <= 20'b11000000111110001111;
\t\t\t261 : reg_value <= 20'b11000000110010011100;
\t\t\t262 : reg_value <= 20'b11000000100111111000;
\t\t\t263 : reg_value <= 20'b11000000011110100011;
\t\t\t264 : reg_value <= 20'b11000000010110011101;
\t\t\t265 : reg_value <= 20'b11000000001111100110;
\t\t\t266 : reg_value <= 20'b11000000001001111111;
\t\t\t267 : reg_value <= 20'b11000000000101101000;
\t\t\t268 : reg_value <= 20'b11000000000010100000;
\t\t\t269 : reg_value <= 20'b11000000000000101000;
\t\t\t270 : reg_value <= 20'b11000000000000000000;
\t\t\t271 : reg_value <= 20'b11000000000000101000;
\t\t\t272 : reg_value <= 20'b11000000000010100000;
\t\t\t273 : reg_value <= 20'b11000000000101101000;
\t\t\t274 : reg_value <= 20'b11000000001001111111;
\t\t\t275 : reg_value <= 20'b11000000001111100110;
\t\t\t276 : reg_value <= 20'b11000000010110011101;
\t\t\t277 : reg_value <= 20'b11000000011110100011;
\t\t\t278 : reg_value <= 20'b11000000100111111000;
\t\t\t279 : reg_value <= 20'b11000000110010011100;
\t\t\t280 : reg_value <= 20'b11000000111110001111;
\t\t\t281 : reg_value <= 20'b11000001001011010001;
\t\t\t282 : reg_value <= 20'b11000001011001100001;
\t\t\t283 : reg_value <= 20'b11000001101000111111;
\t\t\t284 : reg_value <= 20'b11000001111001101011;
\t\t\t285 : reg_value <= 20'b11000010001011100101;
\t\t\t286 : reg_value <= 20'b11000010011110101011;
\t\t\t287 : reg_value <= 20'b11000010110010111111;
\t\t\t288 : reg_value <= 20'b11000011001000011111;
\t\t\t289 : reg_value <= 20'b11000011011111001010;
\t\t\t290 : reg_value <= 20'b11000011110111000010;
\t\t\t291 : reg_value <= 20'b11000100010000000100;
\t\t\t292 : reg_value <= 20'b11000100101010010001;
\t\t\t293 : reg_value <= 20'b11000101000101101000;
\t\t\t294 : reg_value <= 20'b11000101100010001000;
\t\t\t295 : reg_value <= 20'b11000101111111110001;
\t\t\t296 : reg_value <= 20'b11000110011110100011;
\t\t\t297 : reg_value <= 20'b11000110111110011100;
\t\t\t298 : reg_value <= 20'b11000111011111011101;
\t\t\t299 : reg_value <= 20'b11001000000001100100;
\t\t\t300 : reg_value <= 20'b11001000100100110001;
\t\t\t301 : reg_value <= 20'b11001001001001000011;
\t\t\t302 : reg_value <= 20'b11001001101110011010;
\t\t\t303 : reg_value <= 20'b11001010010100110100;
\t\t\t304 : reg_value <= 20'b11001010111100010001;
\t\t\t305 : reg_value <= 20'b11001011100100110001;
\t\t\t306 : reg_value <= 20'b11001100001110010010;
\t\t\t307 : reg_value <= 20'b11001100111000110011;
\t\t\t308 : reg_value <= 20'b11001101100100010100;
\t\t\t309 : reg_value <= 20'b11001110010000110100;
\t\t\t310 : reg_value <= 20'b11001110111110010011;
\t\t\t311 : reg_value <= 20'b11001111101100101110;
\t\t\t312 : reg_value <= 20'b11010000011100000101;
\t\t\t313 : reg_value <= 20'b11010001001100011000;
\t\t\t314 : reg_value <= 20'b11010001111101100110;
\t\t\t315 : reg_value <= 20'b11010010101111101101;
\t\t\t316 : reg_value <= 20'b11010011100010101100;
\t\t\t317 : reg_value <= 20'b11010100010110100011;
\t\t\t318 : reg_value <= 20'b11010101001011010000;
\t\t\t319 : reg_value <= 20'b11010110000000110011;
\t\t\t320 : reg_value <= 20'b11010110110111001001;
\t\t\t321 : reg_value <= 20'b11010111101110010100;
\t\t\t322 : reg_value <= 20'b11011000100110010001;
\t\t\t323 : reg_value <= 20'b11011001011110111110;
\t\t\t324 : reg_value <= 20'b11011010011000011100;
\t\t\t325 : reg_value <= 20'b11011011010010101001;
\t\t\t326 : reg_value <= 20'b11011100001101100011;
\t\t\t327 : reg_value <= 20'b11011101001001001011;
\t\t\t328 : reg_value <= 20'b11011110000101011101;
\t\t\t329 : reg_value <= 20'b11011111000010011010;
\t\t\t330 : reg_value <= 20'b11100000000000000000;
\t\t\t331 : reg_value <= 20'b11100000111110001110;
\t\t\t332 : reg_value <= 20'b11100001111101000011;
\t\t\t333 : reg_value <= 20'b11100010111100011110;
\t\t\t334 : reg_value <= 20'b11100011111100011100;
\t\t\t335 : reg_value <= 20'b11100100111100111110;
\t\t\t336 : reg_value <= 20'b11100101111110000001;
\t\t\t337 : reg_value <= 20'b11100110111111100101;
\t\t\t338 : reg_value <= 20'b11101000000001101000;
\t\t\t339 : reg_value <= 20'b11101001000100001000;
\t\t\t340 : reg_value <= 20'b11101010000111000110;
\t\t\t341 : reg_value <= 20'b11101011001010011111;
\t\t\t342 : reg_value <= 20'b11101100001110010010;
\t\t\t343 : reg_value <= 20'b11101101010010011101;
\t\t\t344 : reg_value <= 20'b11101110010111000000;
\t\t\t345 : reg_value <= 20'b11101111011011111001;
\t\t\t346 : reg_value <= 20'b11110000100001000110;
\t\t\t347 : reg_value <= 20'b11110001100110100111;
\t\t\t348 : reg_value <= 20'b11110010101100011010;
\t\t\t349 : reg_value <= 20'b11110011110010011101;
\t\t\t350 : reg_value <= 20'b11110100111000110000;
\t\t\t351 : reg_value <= 20'b11110101111111010000;
\t\t\t352 : reg_value <= 20'b11110111000101111101;
\t\t\t353 : reg_value <= 20'b11111000001100110101;
\t\t\t354 : reg_value <= 20'b11111001010011110111;
\t\t\t355 : reg_value <= 20'b11111010011011000001;
\t\t\t356 : reg_value <= 20'b11111011100010010010;
\t\t\t357 : reg_value <= 20'b11111100101001101001;
\t\t\t358 : reg_value <= 20'b11111101110001000100;
\t\t\t359 : reg_value <= 20'b11111110111000100010;
\t\t\tdefault: reg_value <= 0;
\t\tendcase
\tend
endmodule
|
module top (reset, clk1, clk2, x, y);
\tinput reset, clk1, clk2, x;
\toutput y;
\tDFF ff1 (clk1, reset, x, n1);
\tDFF ff2 (clk1, reset, n1, n2);
\tNOT u1 (n2_inv, n2);
\tDFF ff3 (clk2, reset, n2_inv, n3);
\tDFF ff4 (clk2, reset, n3, n4);
\tDFF ff5 (clk2, reset, n4, y);
endmodule
|
`ifndef _inc_fifo_
`define _inc_fifo_
module fifo2 (clk, reset, full, empty, item_in, item_out, write, read);
\tparameter SIZE = 2;
\tparameter DEPTH_LOG2 = 1;
\tlocalparam DEPTH = 2 ** DEPTH_LOG2;
\tinput clk, reset, write, read;
\tinput [SIZE-1:0] item_in;
\toutput [SIZE-1:0] item_out;
\toutput full, empty;
\treg full, empty;
\treg [SIZE-1:0] memory [DEPTH-1:0];
\treg [DEPTH_LOG2-1:0] read_ptr;
\treg [DEPTH_LOG2-1:0] write_ptr;
\twire [DEPTH_LOG2-1:0] read_ptr_p1 = read_ptr + 1;
\twire [DEPTH_LOG2-1:0] write_ptr_p1 = write_ptr + 1;
\tassign item_out = memory[read_ptr];
\tinteger i;
\twire do_read = read & !empty;
\twire do_write = write & !full;
\talways @(posedge clk or posedge reset) begin
\t\tif (reset) begin
\t\t\tread_ptr <= 0;
\t\t\twrite_ptr <= 0;
\t\t\tempty <= 1;
\t\t\tfull <= 0;
\t\t\tfor (i=0; i<DEPTH; i=i+1) memory[i] <= 0;
\t\tend else begin
\t\t\tif (do_read & do_write) begin
\t\t\t\tread_ptr <= read_ptr_p1;
\t\t\t\twrite_ptr <= write_ptr_p1;
\t\t\t\tmemory[write_ptr] <= item_in;
\t\t\tend else if (do_read) begin
\t\t\t\tfull <= 0;
\t\t\t\tread_ptr <= read_ptr_p1;
\t\t\t\tempty <= (read_ptr_p1 == write_ptr);
\t\t\tend else if (do_write) begin
\t\t\t\tmemory[write_ptr] <= item_in;
\t\t\t\tempty <= 0;
\t\t\t\twrite_ptr <= write_ptr_p1;
\t\t\t\tfull <= (read_ptr == write_ptr_p1);
\t\t\tend
\t\tend
\tend
endmodule
`endif
|
module top (clk, rst, a, b, c, d, count);
\tinput a, b;
\tinput clk, rst;
\toutput c, d;
\treg c, d;
\toutput [3:0] count;
\treg [3:0] count;
\talways @(posedge clk or posedge rst) begin
\t\tif (rst) begin
\t\t\tc <= 0;
\t\t\td <= 0;
\t\t\tcount <= 0;
\t\tend else begin
\t\t\tc <= a;
\t\t\td <= b;
\t\t\tcount <= count + a;
\t\tend
\tend
endmodule
|
`define DATA_BITS 8
// Setting 1:
// (uncomment to implement a 2-FF synchronizer on the receiver's end)
`define USE_RECEIVER_SYNCHRONIZER
// Setting 2:
// (uncomment to implement a 2-FF synchronizer on the sender's end)
`define USE_SENDER_SYNCHRONIZER
// Setting 3:
// use multiple synchronizer points assuming the synchronized signals are equal:
//`define USE_TWO_RECEIVERS_DIVERGE_HAZARD
// use multiple synchronization points without assuming synchronizer signals are equal:
//`define USE_TWO_RECEIVERS_DIVERGE_SAFE
// or uncomment both to use a single receiver
module topunit (clk1, clk2, rst, busy, send, data_in, data_out, valid);
\tinput clk1, clk2, rst, send;
\tinput [`DATA_BITS-1:0] data_in;
\toutput [`DATA_BITS-1:0] data_out;
\toutput busy, valid;
\t// data, stb and ack are the crossover signals
\twire [`DATA_BITS-1:0] data;
\twire stb, ack;
\t// module instantiations
\tsender u1 (clk1, rst, busy, send, data_in, data, stb, ack);
\t`ifdef USE_TWO_RECEIVERS_DIVERGE_HAZARD
\t\ttwo_receivers_hazard u2 (clk2, rst, data, stb, data_out, ack, valid);
\t`elsif USE_TWO_RECEIVERS_DIVERGE_SAFE
\t\treceiver_multiple_synchronization_safe u2 (clk2, rst, data, stb, data_out, ack, valid);
\t`else
\t\treceiver u2 (clk2, rst, data, stb, data_out, ack, valid);
\t`endif
endmodule
module sender (clk, rst, busy, send, data_in, data, stb, ack);
\tinput clk, rst, send, ack;
\tinput [`DATA_BITS-1:0] data_in;
\toutput [`DATA_BITS-1:0] data;
\toutput stb, busy;
\treg stb;
\twire ack_selected;
\t`ifdef USE_SENDER_SYNCHRONIZER
\t\tsynchronizer sync1 (clk, rst, ack, ack_sync);
\t\tassign ack_selected = ack_sync;
\t`else
\t\tassign ack_selected = ack;
\t`endif
\tassign busy = stb || ack_selected;
\tmyregister reg1 (clk, rst, data_in, data, send);
\talways @(posedge clk or posedge rst) begin
\t\tif (rst == 1) begin
\t\t\tstb <= 0;
\t\tend else if (send && !busy) begin
\t\t\tstb <= 1;
\t\tend else if (stb && ack_selected) begin
\t\t\tstb <= 0;
\t\tend
\tend
endmodule
module receiver (clk, rst, data, stb, data_out, ack, valid);
\tinput clk, rst, stb;
\tinput [`DATA_BITS-1:0] data;
\toutput [`DATA_BITS-1:0] data_out;
\toutput ack, valid;
\twire [`DATA_BITS-1:0] data_rec;
\twire stb_selected;
\t`ifdef USE_RECEIVER_SYNCHRONIZER
\t\tsynchronizer sync1 (clk, rst, stb, stb_sync);
\t\tassign stb_selected = stb_sync;
\t`else
\t\tassign stb_selected = stb;
\t`endif
//\tassign ack = valid | stb;
\t/*
\treg ack;
\talways @(posedge clk or posedge rst) begin
\t\tif (rst == 1) begin
\t\t\tack <= 0;
\t\tend else if (!ack & stb_selected) begin
\t\t\tack <= 1;
\t\tend else if (ack & !stb_selected) begin
\t\t\tack <= 0;
\t\tend
\tend
\t*/
\t//assign ack = stb_selected;
\tmyflop reg5 (clk, rst, stb_selected, ack, 1'b1);
\t// copy `data` to `data_rec` when stb_selected=1
\tmyregister reg1 (clk, rst, data, data_rec, newdata);
\t// copy `data_rec` to `data_out`
\t//myregister reg2 (clk, rst, data_rec, data_out, 1'b1);
\tassign data_out = data_rec;
\t// receive is high for one cycle following assertion of stb_selected
\t//myflop reg3 (clk, rst, stb_selected && !receive, receive, 1'b1);
\tmyflop reg3 (clk, rst, stb_selected, stb_latched, 1'b1);
\t// valid bit
\t//myflop reg4 (clk, rst, receive, valid, 1'b1);
\tassign newdata = stb_selected & !stb_latched;
\tmyflop reg4 (clk, rst, newdata, valid, 1'b1);
endmodule
module two_receivers_hazard (clk, rst, data, stb, data_out, ack, valid);
\tinput clk, rst, stb;
\tinput [`DATA_BITS-1:0] data;
\toutput [`DATA_BITS-1:0] data_out;
\toutput ack, valid;
\treceiver u2 (clk, rst, data, stb, , ack, valid1);
\treceiver u3 (clk, rst, data, stb, data_out, , valid2);
\tassign valid = valid1;
endmodule
module receiver_multiple_synchronization_safe (clk, rst, data, stb, data_out, ack, valid);
\tinput clk, rst, stb;
\tinput [`DATA_BITS-1:0] data;
\toutput [`DATA_BITS-1:0] data_out;
\toutput ack, valid;
\treceiver u1 (clk, rst, data, sync_stb, data_out, ack, valid);
\tdivg_synchronizer u2 (clk, rst, stb, sync_stb);
endmodule
module myflop (clk, rst, d, q, ena);
\tinput clk, rst, ena;
\toutput q;
\treg q;
\tinput d;
\talways @(posedge clk or posedge rst) begin
\t\tif (rst == 1) begin
\t\t\tq <= 0;
\t\tend else if (ena) begin
\t\t\tq <= d;
\t\tend
\tend
endmodule
module myregister (clk, rst, d, q, ena);
\tinput clk, rst, ena;
\toutput [`DATA_BITS-1:0] q;
\treg [`DATA_BITS-1:0] q;
\tinput [`DATA_BITS-1:0] d;
\talways @(posedge clk or posedge rst) begin
\t\tif (rst == 1) begin
\t\t\tq <= 0;
\t\tend else if (ena) begin
\t\t\tq <= d;
\t\tend
\tend
endmodule
module forgetfulregister (clk, rst, d, q, ena);
\t// behaves the sameway as a typical register
\t// except it resets the data when ena is 0
\t// this module simplifes some synthesized design
\t// because it doesn't require instantiating a feedback
\t// loop to retain the register state
\tparameter BITS = 1;
\tinput clk, rst, ena;
\toutput [BITS-1:0] q;
\treg [BITS-1:0] q;
\tinput [BITS-1:0] d;
\talways @(posedge clk or posedge rst) begin
\t\tif (rst == 1) begin
\t\t\tq <= 0;
\t\tend else if (ena) begin
\t\t\tq <= d;
\t\tend else begin
\t\t\tq <= 0;
\t\tend
\tend
endmodule
module synchronizer (clk, rst, x, sync_x);
\tinput clk, rst, x;
\toutput sync_x;
\treg f1, f2;
\tassign sync_x = f2;
\talways @(posedge clk or posedge rst) begin
\t\tif (rst) begin
\t\t\tf1 <= 0;
\t\t\tf2 <= 0;
\t\tend else begin
\t\t\tf1 <= x;
\t\t\tf2 <= f1;
\t\tend
\tend
endmodule
module divg_synchronizer (clk, rst, x, sync_x);
\tinput clk, rst, x;
\toutput sync_x;
\tsynchronizer u1 (clk, rst, x, sync_x_1);
\tsynchronizer u2 (clk, rst, x, sync_x_2);
\tassign sync_x = sync_x_1 | sync_x_2;
endmodule
|
module async_counter(clk, reset, active, count);
\tparameter N = 10;
\tinput clk, reset;
\tinput [5:0] active; // enough bits for (3*N)
\treg [N-1:0] n5;
\treg [N-1:0] n7;
\treg [N-1:0] n9;
\toutput [N-1:0] count = n7;
\twire [N-1:0] n7_prev;
\twire [N-1:0] n5_next;
\tgenerate
\t\tgenvar i;
\t\tfor (i=0; i<N; i=i+1) begin
\t\t\tif (i>0)
\t\t\t\tassign n7_prev[i] = n7[i-1];
\t\t\telse
\t\t\t\tassign n7_prev[i] = ~n5[0];
\t\t\tif (i<N-1)
\t\t\t\tassign n5_next[i] = n5[i+1];
\t\t\telse
\t\t\t\tassign n5_next[i] = n7[i];
\t\t\talways @(posedge clk or posedge reset)
\t\t\t\tif (reset) begin
\t\t\t\t\tn5[i] <= 0;
\t\t\t\t\tn7[i] <= 0;
\t\t\t\t\tn9[i] <= 1;
\t\t\t\tend else begin
\t\t\t\t\tn5[i] <= (active == (i*3 + 0)) ? (n7[i] & n9[i] | ~n7[i] & ~n9[i]) : n5[i];
\t\t\t\t\tn7[i] <= (active == (i*3 + 1)) ? (n7[i] & ~n7_prev[i] | n7_prev[i] & n9[i]) : n7[i];
\t\t\t\t\tn9[i] <= (active == (i*3 + 2)) ? (n7_prev[i] & n9[i] | ~n7_prev[i] & ~n5_next[i]) : n9[i];
\t\t\t\tend
\t\tend
\tendgenerate
endmodule
|
module pipeline1 (clk, rst, ena, data_in, data_out, valid, busy);
\tparameter SIZE = 8;
\tinput clk, rst, ena;
\tinput [SIZE-1:0] data_in;
\toutput [SIZE-1:0] data_out = stage2;
\toutput valid = valid2;
\toutput busy = valid1;
\treg [SIZE-1:0] stage1;
\treg [SIZE-1:0] stage2;
\treg valid1;
\treg valid2;
\talways @(posedge clk or posedge rst) begin
\t\tif (rst) begin
\t\t\tstage1 <= 0;
\t\t\tstage2 <= 0;
\t\t\tvalid1 <= 0;
\t\t\tvalid2 <= 0;
\t\tend else if (ena) begin
\t\t\tstage1 <= data_in;
\t\t\tstage2 <= stage1;
\t\t\tvalid1 <= valid1 | ena;
\t\t\tvalid2 <= valid1;
\t\tend
\tend
endmodule
|
// This is a simple design to test $eventually().
// The input `a` propagates through three FFs: r1, r2 and r3. Between r1 and
// r2, the value gets XOR'ed with b allowing `b` to mask the propagating value
// of `a`. Thus, the assertion $eventually(a, y) is false.
module top (clk, rst, a, b, y);
\tinput clk, rst, a, b;
\toutput y;
\treg r1, r2, r3;
\talways @(posedge clk or posedge rst) begin
\t\tif (rst) begin
\t\t\tr1 <= 0;
\t\t\tr2 <= 0;
\t\t\tr3 <= 0;
\t\tend else begin
\t\t\tr1 <= a;
\t\t\tr2 <= r1 ^ b;
\t\t\tr3 <= r2;
\t\tend
\tend
\tassign y = r3;
endmodule
|
module top (reset, clk1, clk2, x, y);
\tinput reset, clk1, clk2, x;
\toutput y;
\tDFF ff1 (clk1, reset, x, n1);
\tDFF ff2 (clk1, reset, n1, n2);
\tAND u1 (n2_inv, n2, y);
\tDFF ff3 (clk2, reset, n2_inv, n3);
\tDFF ff4 (clk2, reset, n3, n4);
\tDFF ff5 (clk2, reset, n4, y);
endmodule
|
// finding a state for which valid=0 in the design below takes 9.55 second on ifv:
module assert1 (count, count2, valid);
\tinput [11:0] count;
\tinput [11:0] count2;
\t
\toutput valid;
\tassign valid = (count != 12'hfff) | (count2 != 12'hfff);
\t
endmodule
module top (clk, rst, ena1, ena2, count, valid);
\tinput clk, rst, ena1, ena2;
\t
\toutput [11:0] count;
\t
\toutput valid;
\t
\treg [11:0] count;
\treg [11:0] count2;
\t
\twire valid;
\t
\talways @(posedge clk or posedge rst) begin
\t
\t\tif (rst) begin
\t\t
\t\t\tcount <= 0;
\t\t\t
\t\tend else if (ena1) begin
\t\t
\t\t\tcount <= count + 1;
\t\t\t
\t\tend
\t
\tend
\t
\talways @(posedge clk or posedge rst) begin
\t
\t\tif (rst) begin
\t\t
\t\t\tcount2 <= 0;
\t\t\t
\t\tend else if (ena2) begin
\t\t
\t\t\tcount2 <= count2 + 1;
\t\t\t
\t\tend
\t
\tend
\t
\tassert1 u1 (count, count2, valid);\t\t
\t
endmodule
|
module graycounter2 (clk, rst, ena1, ena2, count);
\tinput clk, rst, ena1, ena2;
\toutput [1:0] count;
\treg [1:0] count;
\talways @(posedge clk or posedge rst) begin
\t\tif (rst) begin
\t\t\tcount <= 0;
\t\tend else if (ena1 ^ ena2) begin
\t\t\tif (count == 0) begin
\t\t\t\tcount <= 1;
\t\t\tend else if (count == 1) begin
\t\t\t\tcount <= 3;
\t\t\tend else if (count == 3) begin
\t\t\t\tcount <= 2;
\t\t\tend else if (count == 2) begin
\t\t\t\tcount <= 0;
\t\t\tend
\t\tend
\tend
endmodule
|
module top (reset, clk1, clk2, x, y);
\tinput reset, clk1, clk2, x;
\toutput y;
\tDFF ff1 ( .CK(clk1), .RS(reset), .D(x), .Q(n1) );
\tDFF ff2 (. CK(clk1), .RS(reset), .D(n1), .Q(n2) );
\tDFF ff3 (. CK(clk2), .RS(reset), .D(n2), .Q(n3) );
\tDFF ff4 (. CK(clk2), .RS(reset), .D(n3), .Q(n4) );
\tDFF ff5 ( .CK(clk2), .RS(reset), .D(n4), .Q(y) );
endmodule
|
module top (clk, rst, x, count, valid, assume);
\tinput clk, rst, x;
\toutput [7:0] count;
\toutput valid, assume;
\twire ena;
\tassign ena = x == ^count;
\tassign valid = (count != 25);
\tassign assume = (count < 50);
\tcounter u1 (clk, rst, ena, count);
endmodule
module counter (clk, rst, ena, count);
\tinput clk, rst, ena;
\toutput [7:0] count;
\treg [7:0] count;
\talways @(posedge rst or posedge clk) begin
\t\tif (rst) begin
\t\t\tcount <= 0;
\t\tend else begin
\t\t\tcount <= count + ena;
\t\tend
\tend
endmodule
|
module Test (p1, p2, p3, p4, p5);
\tinput p1, p2;
\toutput p3, p4, p5;
\tAND a1 (p3, p1, p2);
\tOR o1 (p4, p1, p2);
\tXOR x1 (p5, p3, p4);
endmodule
|
module graycounter (clk, rst, ena, count);
\tinput clk, rst, ena;
\toutput [1:0] count;
\treg [1:0] count;
\talways @(posedge clk or posedge rst) begin
\t\tif (rst) begin
\t\t\tcount <= 0;
\t\tend else if (ena) begin
\t\t\tif (count == 0) begin
\t\t\t\tcount <= 1;
\t\t\tend else if (count == 1) begin
\t\t\t\tcount <= 3;
\t\t\tend else if (count == 3) begin
\t\t\t\tcount <= 2;
\t\t\tend else if (count == 2) begin
\t\t\t\tcount <= 0;
\t\t\tend
\t\tend
\tend
endmodule
|
module DFFx (CK, RS, D, Q, T, M, V, rD, rV);
\tinput CK, RS, D, V, rD, rV;
\toutput Q, T, M;
\tTIEX tiex1 (.y(x)); // when M or T
\tMUX2 mux1 (.y(inpD), .a(D), .b(rD), .s(isV)); // when V
\tMUX2 mux2 (.y(M), .a(Q), .b(x), .s(isM)); // when M
\tMUX2 mux3 (.y(T), .a(Q), .b(x), .s(isT)); // when T
\tDFF d (.CK(CK), .RS(RS), .D(inpD), .Q(Q)); // always
\tDFF m (.CK(CK), .RS(RS), .D(inpM), .Q(isM)); // when M
\tDFF t (.CK(CK), .RS(RS), .D(inpT), .Q(isT)); // when T
\t// note: M -> V
\tX2H x2h (.y(isV), .a(V)); // when V
\tAND and1 (.y(inpM), .a(isV), .b(rV)); // when M
\tXOR xor1 (.y(inpT), .a(inpD), .b(Q)); // when T
endmodule
|
module counter (clk, rst, ena, count);
\tinput clk, rst, ena;
\toutput [7:0] count;
\treg [7:0] count;
\talways @(posedge clk or posedge rst) begin
\t\tif (rst) begin
\t\t\tcount <= 0;
\t\tend else if (ena) begin
\t\t\tcount <= count + 1;
\t\tend
\tend
endmodule
|
module top (clk, rst, ena1, ena2, count, valid);
\tinput clk, rst, ena1, ena2;
\t
\toutput [3:0] count;
\t
\toutput valid;
\t
\treg [3:0] count;
\t
\twire a1, a2;
\t
\tassign a1 = ena1 && (count<2);
\tassign a2 = ena2 && (count>=2);
\t
\talways @(posedge clk or posedge rst) begin
\t
\t\tif (rst) begin
\t\t
\t\t\tcount <= 0;
\t\t\t
\t\tend else if (ena1) begin
\t\t
\t\t\tcount <= count + 1;
\t\t\t
\t\tend
\t
\tend
\t
\t// assertion logic
\t
\treg ena1_old;
\t
\talways @(posedge clk or posedge rst) begin
\t\tif (rst) begin
\t\t\tena1_old <= 0;
\t\tend else begin
\t\t\tena1_old <= ena1;
\t\tend
\tend
\t
\t// (x -> y) == (~x V y)
\t
\tassign valid = (ena1_old == 0) || (count<5);
\t
endmodule
|
module top (a, b, c, y);
\tinput a, b, c;
\toutput [2:0] y;
\tassign y = {a, b,c};
endmodule
|
// finding a state for which err=0 in the design below takes 9.55 second on ifv:
module top (clk, rst, ena1, ena2, count, err);
\tinput clk, rst, ena1, ena2;
\t
\toutput [11:0] count;
\t
\toutput err;
\t
\treg [11:0] count;
\treg [11:0] count2;
\t
\talways @(posedge clk or posedge rst) begin
\t
\t\tif (rst) begin
\t\t
\t\t\tcount <= 0;
\t\t\t
\t\tend else if (ena1) begin
\t\t
\t\t\tcount <= count + 1;
\t\t\t
\t\tend
\t
\tend
\t
\talways @(posedge clk or posedge rst) begin
\t
\t\tif (rst) begin
\t\t
\t\t\tcount2 <= 0;
\t\t\t
\t\tend else if (ena2) begin
\t\t
\t\t\tcount2 <= count2 + 1;
\t\t\t
\t\tend
\t
\tend\t
\t
\tassign err = (count == 12'hfff) | (count2 == 12'hfff);
\t
endmodule
|
module top (a , b);
\tinput a;
\toutput [1:0] b;
\tassign b[0] = a;
\tNOT n1 ( b [1] , a);
endmodule
|
`define SIZE 2
`define FIFO_DEPTH_LOG2 2
`define FIFO_DEPTH (1<<`FIFO_DEPTH_LOG2)
module fifo(clk, reset, full, empty, item_in, item_out, write, read);
parameter routerid=-1;
input clk, reset, write, read;
output full, empty;
reg [`SIZE-1:0] mem [`FIFO_DEPTH-1:0];
reg [`FIFO_DEPTH_LOG2-1:0] read_ptr;
reg [`FIFO_DEPTH_LOG2-1:0] write_ptr;
wire [`FIFO_DEPTH_LOG2-1:0] read_ptr_p1; assign read_ptr_p1 = read_ptr + 1;
wire [`FIFO_DEPTH_LOG2-1:0] write_ptr_p1; assign write_ptr_p1 = write_ptr + 1;
reg [`FIFO_DEPTH_LOG2:0] count;
input [`SIZE-1:0] item_in;
output [`SIZE-1:0] item_out;
reg full, empty;
integer i;
always @(posedge clk or posedge reset) begin
if (reset) begin
read_ptr <= 0;
write_ptr <= 0;
empty <= 1;
full <= 0;
count <= 0;
for (i=0; i<`FIFO_DEPTH; i=i+1) begin
mem[i] <= 0;
end
end else begin
if (read & !empty) begin
full <= 0;
read_ptr <= read_ptr_p1;
if (read_ptr_p1 == write_ptr) empty <= 1;
//if (routerid > -1) $display("router %d fifo pop : %d", routerid, item_out);
end
if (write & !full) begin
mem [write_ptr] <= item_in;
//if (routerid > -1) $display("router %d fifo push : %d", routerid, item_in);
empty <= 0;
write_ptr <= write_ptr_p1;
if (read_ptr == write_ptr_p1) full <= 1;
end
if (actual_read & !actual_write)
count <= count-1;
else if (actual_write & !actual_read)
count <= count+1;
end
end
assign item_out = mem [read_ptr];
wire actual_read = read & !empty;
wire actual_write = write & !full;
endmodule
|
module design1 (in1, in2, out1, out2, out3);
\tinput in1, in2;
\toutput out1, out2, out3;
\tTest t1 (in1, in2, out1, out2, out3);
endmodule
|
module top (reset, clk1, clk2, x, y);
\tinput reset, clk1, clk2, x;
\toutput y;
\tDFF ff1 ( .CK(clk1), .RS(reset), .D(x), .Q(n1) );
\tDFF ff2 ( .CK(clk1), .RS(reset), .D(n1), .Q(n2) );
\tAND u1 (nx, n2, y);
\tDFF ff3 ( .CK(clk2), .RS(reset), .D(nx), .Q(n3) );
\tDFF ff4 ( .CK(clk2), .RS(reset), .D(n3), .Q(n4) );
\tDFF ff5 ( .CK(clk2), .RS(reset), .D(n4), .Q(y) );
\tDFF ff6 ( .CK(clk1), .RS(reset), .D(nx), .Q(n5) );
endmodule
|
// state transitions:
// 0 -> 1 (a=0)
// 0 -> 2 (a=1)
// 1 -> 3 (a=0)
// 1 -> 4 (a=1)
// 4 -> 5 (a=0)
// 4 -> 6 (a=1)
// 2 -> 6
// 5 -> 0
module statemach1(clk, rst, a, state);
\tinput clk, rst, a;
\toutput [2:0] state;
\treg [2:0] state;
\talways @(posedge clk or posedge rst) begin
\t\tif (rst) begin
\t\t\tstate <= 0;
\t\tend else begin
\t\t\tif (state == 0)
\t\t\t\tstate <= 1 + a;
\t\t\telse if (state == 1)
\t\t\t\tstate <= 3 + a;
\t\t\telse if (state == 4)
\t\t\t\tstate <= 5 + a;
\t\t\telse if (state == 2)
\t\t\t\tstate <= 6;
\t\t\telse if (state == 5)
\t\t\t\tstate <= 0;
\t\tend
\tend
endmodule
|
module AND (y, a, b);
\tinput a, b;
\toutput y;
endmodule
module NAND (y, a, b);
\tinput a, b;
\toutput y;
endmodule
module OR (y, a, b);
\tinput a, b;
\toutput y;
endmodule
module NOR (y, a, b);
\tinput a, b;
\toutput y;
endmodule
module BUF (y, a);
\tinput a;
\toutput y;
endmodule
module NOT (y, a);
\tinput a;
\toutput y;
endmodule
module XOR (y, a, b);
\tinput a, b;
\toutput y;
endmodule
module DFF (CK, RS, ST, D, Q);
\tinput CK, RS, ST, D;
\toutput Q;
endmodule
module DFFx (CK, RS, ST, D, Q, M, V, T, rD, rV);
\tinput CK, RS, ST, D;
\toutput Q;
\tinput V;
\toutput M, T;
\tinput rD, rV;
endmodule
module TIE0(y);
\toutput y;
endmodule
module TIE1(y);
\toutput y;
endmodule
module TIEX(y);
\toutput y;
endmodule
module MUX2 (y, a, b, s);
\tinput a, b, s;
\toutput y;
endmodule
module X2H (y, a);
\tinput a;
\toutput y;
endmodule
module H2X (y, a);
\tinput a;
\toutput y;
endmodule
module Test (p1, p2, p3, p4, p5);
\tinput p1, p2;
\toutput p3, p4, p5;
endmodule
|
// finding a state for which valid=0 in the design below takes 26.5 second on ifv:
module lfsr15(clk, rst, ena, state);
\t// period = 32767
\tinput clk, rst, ena;
\toutput [14:0] state;
\treg [14:0] state;
\talways @(posedge rst or posedge clk) begin
\t\tif (rst == 1) begin
\t\t\tstate <= 1;
\t\tend else if (ena) begin
\t\t\tstate[14:1] <= state[13:0];
\t\t\tstate[0] <= state[13] ^ state[14];
\t\tend
\tend
endmodule
module lfsr13(clk, rst, ena, state);
\t// period = 8191
\tinput clk, rst, ena;
\toutput [12:0] state;
\treg [12:0] state;
\talways @(posedge rst or posedge clk) begin
\t\tif (rst == 1) begin
\t\t\tstate <= 1;
\t\tend else if (ena) begin
\t\t\tstate[12:1] <= state[11:0];
\t\t\tstate[0] <= state[7] ^ state[10] ^ state[11] ^ state[12];
\t\tend
\tend
endmodule
module lfsr12(clk, rst, ena, state);
\t// period = 4095
\tinput clk, rst, ena;
\toutput [11:0] state;
\treg [11:0] state;
\talways @(posedge rst or posedge clk) begin
\t\tif (rst == 1) begin
\t\t\tstate <= 1;
\t\tend else if (ena) begin
\t\t\tstate[11:1] <= state[10:0];
\t\t\tstate[0] <= state[3] ^ state[9] ^ state[10] ^ state[11];
\t\tend
\tend
endmodule
module lfsr4(clk, rst, ena, state);
\t// period = 15
\tinput clk, rst, ena;
\toutput [3:0] state;
\treg [3:0] state;
\talways @(posedge rst or posedge clk) begin
\t\tif (rst == 1) begin
\t\t\tstate <= 1;
\t\tend else if (ena) begin
\t\t\tstate[3:1] <= state[2:0];
\t\t\tstate[0] <= state[2] ^ state[3];
\t\tend
\tend
endmodule
module top (clk, rst, code, err, secret, state);
\tinput clk, rst;
\toutput err;
\tinput [14:0] code;
\toutput [11:0] state;
\tlfsr12 u1 (clk, rst, ena, state);
\toutput [14:0] secret;
\t//lfsr13 u2 (clk, rst, ena, secret);
\tlfsr15 u2 (clk, rst, ena, secret);
\twire ena;
\tassign ena = (code == secret);
\tassign err = state != 'b100000000000;
endmodule
|
///2016/8/6
///ShaoMin Zhai
///module function: used to debug core
`include "define.v"
module top_level(
clk,
rst
);
input clk;
input rst;
wire [31:0] pc;
wire [31:0] mem_data;
wire [31:0] mem_addr;
wire [3:0] mem_head;
wire v_mem;
wire v_pc;
wire [31:0] data;
wire v_data;
wire [31:0] inst;
wire v_inst;
core core_du(//input
.clk(clk),
.rst(rst),
.v_inst(v_inst),
.inst(inst),
.v_data(v_data),
.data(data),
//output
.pc(pc),
.v_pc(v_pc),
.v_mem(v_mem),
.mem_head(mem_head),
.mem_addr(mem_addr),
.mem_data(mem_data)
);
instmem instmem_du(
.clk(clk),
.rst(rst),
.pc(pc),
.read(v_pc),
.inst(inst),
.v_inst(v_inst)
);
datamem datamem_du(
.clk(clk),
.rst(rst),
.addr(mem_addr),
.data_in(mem_data),
.r_w(mem_head[3]),
.v_cmd(v_mem),
.data_out(data),
.v_data_out(v_data)
);
endmodule
|
/// date:2016/3/5
/// engineer :ZhaiShaoMin 3/6 am: 10:57 done!
/// module function :because accesses come from three different sources:cpu,IN_req/rep(at one time ,only req or rep),mem
/// so here we need a arbiter to determine who can access data cache finally.
module arbiter_for_dcache(//input
clk,
rst,
dcache_done_access,
v_dc_download,
dc_download_flits,
v_cpu,
cpu_access_flits,
v_m_d_areg,
m_d_areg_flits,
//output
flits_dc,
v_flits_dc,
re_dc_download_flits,
re_cpu_access_flits,
re_m_d_areg_flits,
cpu_done_access,
dc_download_done_access,
m_d_areg_done_access
);
//input
input clk;
input rst;
input dcache_done_access;
input v_dc_download;
input [143:0] dc_download_flits;
input v_cpu;
input [67:0] cpu_access_flits;
input v_m_d_areg;
input [143:0] m_d_areg_flits;
//output
output [143:0] flits_dc;
output v_flits_dc;
output re_dc_download_flits;
output re_cpu_access_flits;
output re_m_d_areg_flits;
output cpu_done_access;
output dc_download_done_access;
output m_d_areg_done_access;
// parameter for fsm state
parameter idle=4'b0001;
parameter cpu_busy=4'b0010;
parameter dc_busy=4'b0100;
parameter mem_busy=4'b1000;
reg [2:0] select;
reg update_priority_3;
reg update_priority_2;
reg [3:0] nstate;
reg [3:0] state;
reg re_cpu_access_flits;
reg re_dc_download_flits;
reg re_m_d_areg_flits;
reg cpu_done_access;
reg dc_download_done_access;
reg m_d_areg_done_access;
reg [143:0] flits_dc;
reg v_flits_dc;
wire [2:0] v_vector;
reg [2:0] priority_3;
reg [1:0] priority_2;
assign v_vector={v_dc_download,v_cpu,v_m_d_areg};
always@(*)
begin
select=3'b000;
update_priority_3=1'b0;
update_priority_2=1'b0;
nstate=state;
re_cpu_access_flits=1'b0;
re_dc_download_flits=1'b0;
re_m_d_areg_flits=1'b0;
cpu_done_access=1'b0;
dc_download_done_access=1'b0;
m_d_areg_done_access=1'b0;
flits_dc=144'h0000;
v_flits_dc=1'b0;
case(state)
idle:
begin
if(v_vector==3'b111)
begin
select=priority_3;
update_priority_3=1'b1;
end
else if(v_vector==3'b011)
begin
select={1'b0,priority_2};
update_priority_2=1'b1;
end
else if(v_vector==3'b101)
begin
select={priority_2[0],1'b0,priority_2[1]};
update_priority_2=1'b1;
end
else if(v_vector==3'b110)
begin
select={priority_2,1'b0};
update_priority_2=1'b1;
end
else if(v_vector==3'b001||v_vector==3'b010||v_vector==3'b100)
begin
select=v_vector;
end
if(select==3'b001)
nstate=mem_busy;
else if(select==3'b010)
nstate=dc_busy;
else if(select==3'b100)
nstate=cpu_busy;
end
cpu_busy:
begin
re_cpu_access_flits=1'b1;
flits_dc={cpu_access_flits,76'h0000};
v_flits_dc=1'b1;
if(dcache_done_access)
begin
nstate=idle;
cpu_done_access=1'b1;
end
end
dc_busy:
begin
re_dc_download_flits=1'b1;
flits_dc=dc_download_flits;
v_flits_dc=1'b1;
if(dcache_done_access)
begin
nstate=idle;
dc_download_done_access=1'b1;
end
end
mem_busy:
begin
re_m_d_areg_flits=1'b1;
flits_dc=m_d_areg_flits;
v_flits_dc=1'b1;
if(dcache_done_access)
begin
nstate=idle;
m_d_areg_done_access=1'b1;
end
end
endcase
end
/// fsm state
always@(posedge clk)
begin
if(rst)
state<=4'b0001;
else
state<=nstate;
end
/// priority state
always@(posedge clk)
begin
if(rst)
priority_3<=3'b001;
else if(update_priority_3)
priority_3<={priority_3[1:0],priority_3[2]};
end
always@(posedge clk)
begin
if(rst)
priority_2<=2'b01;
else if(update_priority_2)
priority_2<={priority_2[0],priority_2[1]};
end
endmodule
|
/// date:2016/3/9
/// engineer: ZhaiShaoMin
module m_req_upload(//input
clk,
rst,
v_flits_in,
out_req_fifo_rdy_in,
en_inv_ids,
inv_ids_in,
flits_max_in,
head_flit,
addrhi,
addrlo,
// datahi1,
// datalo1,
// datahi2,
// datalo2,
// datahi3,
// datalo3,
// datahi4,
// datalo4,
//output
ctrl_out,
flit_out,
fsm_state,
v_flit_to_req_fifo
);
// input
input clk;
input rst;
input v_flits_in;
input out_req_fifo_rdy_in;
input en_inv_ids;
input [3:0] inv_ids_in;
input [3:0] flits_max_in;
input [15:0] head_flit;
input [15:0] addrhi;
input [15:0] addrlo;
/*input [15:0] datahi1;
//input [15:0] datalo1;
input [15:0] datahi2;
input [15:0] datalo2;
input [15:0] datahi3;
input [15:0] datalo3;
input [15:0] datahi4;
input [15:0] datalo4;
*/
//output
output [1:0] ctrl_out;
output [15:0] flit_out;
output [1:0] fsm_state;
output v_flit_to_req_fifo;
wire [3:0] inv_ids_reg_net;
wire [1:0] sel_cnt_invs_net;
wire [15:0] flit_out_net;
wire cnt_eq_max_net;
wire cnt_invs_eq_3_net;
wire cnt_eq_0_net;
wire dest_sel_net;
wire clr_max_net;
wire clr_inv_ids_net;
wire clr_sel_cnt_inv_net;
wire clr_sel_cnt_net;
wire inc_sel_cnt_net;
wire inc_sel_cnt_inv_net;
wire en_flit_max_in_net;
wire en_inv_ids_net;
FSM_upload_flit req_fsm_dut (// input
.clk(clk),
.rst(rst),
.en_for_reg(v_flits_in),
.out_req_fifo_rdy(out_req_fifo_rdy_in),
.cnt_invs_eq_3(cnt_invs_eq_3_net),
.cnt_eq_max(cnt_eq_max_net),
.head_flit(head_flit),
.inv_ids_reg(inv_ids_reg_net),
.sel_cnt_invs(sel_cnt_invs_net),
.sel_cnt_eq_0(cnt_eq_0_net),
// output
.en_inv_ids(en_inv_ids_net),
.en_flit_max_in(en_flit_max_in_net),
.inc_sel_cnt_invs(inc_sel_cnt_inv_net),
.inc_sel_cnt(inc_sel_cnt_net),
.ctrl(ctrl_out),
.clr_max(clr_max_net),
.clr_inv_ids(clr_inv_ids_net),
.clr_sel_cnt_inv(clr_sel_cnt_inv_net),
.clr_sel_cnt(clr_sel_cnt_net),
.dest_sel(dest_sel_net),
.fsm_state_out(fsm_state),
.en_flit_out(v_flit_to_req_fifo)
);
upload_datapath req_datapath_dut(// input
.clk(clk),
.rst(rst),
.clr_max(clr_max_net),
.clr_inv_ids(clr_inv_ids_net),
.clr_sel_cnt_inv(clr_sel_cnt_inv_net),
.clr_sel_cnt(clr_sel_cnt_net),
.inc_sel_cnt(inc_sel_cnt_net),
.inc_sel_cnt_inv(inc_sel_cnt_inv_net),
.en_flit_max_in(en_flit_max_in_net),
.en_for_reg(v_flits_in),
.en_inv_ids(en_inv_ids),
.inv_ids_in(inv_ids_in),
.dest_sel(dest_sel_net),
.flit_max_in(flits_max_in),
.head_flit(head_flit),
.addrhi(addrhi),
.addrlo(addrlo),
/* .datahi1(datahi1),
.datalo1(datalo1),
.datahi2(datahi2),
.datalo2(datalo2),
.datahi3(datahi3),
.datalo3(datalo3),
.datahi4(datahi4),
.datalo4(datalo4), */
//output
.flit_out(flit_out),
.cnt_eq_max(cnt_eq_max_net),
.cnt_invs_eq_3(cnt_invs_eq_3_net),
.cnt_eq_0(cnt_eq_0_net),
.inv_ids_reg_out(inv_ids_reg_net),
.sel_cnt_invs_out(sel_cnt_invs_net)
);
endmodule
/*//input
clk,
rst,
m_flits_req,
v_m_flits_req,
req_fifo_rdy,
//output
m_flit_out,
v_m_flit_out,
m_req_upload_state
);
//input
input clk;
input rst;
input [47:0] m_flits_req;
input v_m_flits_req;
input req_fifo_rdy;
//output
output [15:0] m_flit_out;
output v_m_flit_out;
output m_req_upload_state;
//parameter
parameter m_req_upload_idle=1'b0;
parameter m_req_upload_busy=1'b1;
//reg m_req_nstate;
reg m_req_state;
reg [47:0] m_req_flits;
reg [1:0] sel_cnt;
reg v_m_flit_out;
reg fsm_rst;
reg next;
reg en_flits_in;
reg inc_cnt;
assign m_req_upload_state=m_req_state;
always@(*)
begin
//default value
// ic_req_nstate=ic_req_state;
v_m_flit_out=1'b0;
inc_cnt=1'b0;
fsm_rst=1'b0;
en_flits_in=1'b0;
next=1'b0;
case(m_req_state)
m_req_upload_idle:
begin
if(v_m_flits_req)
begin
en_flits_in=1'b1;
next=1'b1;
end
end
m_req_upload_busy:
begin
if(req_fifo_rdy)
begin
if(sel_cnt==2'b10)
fsm_rst=1'b1;
inc_cnt=1'b1;
v_m_flit_out=1'b1;
end
end
endcase
end
// fsm state
always@(posedge clk)
begin
if(rst||fsm_rst)
m_req_state<=1'b0;
else if(next)
m_req_state<=1'b1;
end
// flits regs
always@(posedge clk)
begin
if(rst||fsm_rst)
m_req_flits<=48'h0000;
else if(en_flits_in)
m_req_flits<=m_flits_req;
end
reg [15:0] m_flit_out;
always@(*)
begin
case(sel_cnt)
2'b00:m_flit_out=m_req_flits[47:32];
2'b01:m_flit_out=m_req_flits[31:16];
2'b10:m_flit_out=m_req_flits[15:0];
default:m_flit_out=m_req_flits[47:32];
endcase
end
///sel_counter
always@(posedge clk)
begin
if(rst||fsm_rst)
sel_cnt<=2'b00;
else if(inc_cnt)
sel_cnt<=sel_cnt+1;
end
endmodule */
|
/// date :2016/3/4
/// engineer :ZhaiShaoMin
/// module name :memory_state_data_ram
/// module function : here is placed the ram of state and data
/// because of design division
/// note: state[3:0] is directory
/// state[5:4] is home directory state .00 :R(dir),01 :W(id),10 TR(dir),11 TW(id).
/// every home memeory has 2KB
module memory_state_data_ram(// input
clk,
state_we_in,
state_re_in,
addr_in,
state_in,
data_we_in,
data_re_in,
data_in,
// output
state_out,
data_out);
input clk;
input state_we_in;
input state_re_in;
input [31:0] addr_in;
input [5:0] state_in;
input data_we_in;
input data_re_in;
input [127:0] data_in;
//output
output [5:0] state_out;
output [127:0] data_out;
/*wire [31:0] seled_addr;
wire [5:0] m_state_out;
wire [127:0] seled_data;
wire [127:0] data_read; */
/////////////////////////////////////////////////////////////////////////
////////////// directory_ram and data_ram////////////////////////////////////
////////////////////////////////////////////////////////////////////////
SP_BRAM_SRd #(128,6,7) tag_ram(.clk(clk), .we(state_we_in), .re(state_re_in), .a(addr_in[10:4]), .di(state_in), .dout(state_out));
SP_BRAM_SRd #(128,128,7) data_ram(.clk(clk), .we(data_we_in), .re(data_re_in), .a(addr_in[10:4]), .di(data_in), .dout(data_out));
endmodule
|
// date:2016/2/19 11:00 done!
// engineer:ZhaiShaoMin
// module name:arbiter_4_enq
// module function:decide which fifo should receive coming flit according to the head flit of msg
// since arbiter dequeue has done most of the selction work , this part seems much easier!
module arbiter_4_enq ( // input
flit,
ctrl,
en_dest_fifo,
dest_fifo,
// output
flit2pass_req, // seled flit output to pass req
ctrl2pass_req, // seled ctrl output to pass req
flit2pass_rep, // seled flit output to pass rep
ctrl2pass_rep, // seled ctrl output to pass rep
flit2local_in_req, // seled flit output to local in req
ctrl2local_in_req, // seled ctrl output to local in req
flit2local_in_rep, // seled flit output to local in rep
ctrl2local_in_rep, // seled ctrl output to local in rep
en_pass_req,
en_pass_rep,
en_local_in_req,
en_local_in_rep
);
//INPUT
input [15:0] flit;
input [1:0] ctrl;
input en_dest_fifo; // enable selection between 4 fifos
input [1:0] dest_fifo;// used to decide write flit to pass fifos or In_local fifos
// 00:write to pass req fifo; 01:write to pass rep fifo;
// 10:write to IN_local req fifo; 11:write to IN_local rep fifo;
//output
//output [1:0] enq_select; // 00:enq for pass fifo req;
// 01:enq for pass fifo rep; 10:enq for local fifo req;
// 11:enq for local fifo rep.
output [15:0] flit2pass_req; // seled flit output to pass req
output [1:0] ctrl2pass_req; // seled ctrl output to pass req
output [15:0] flit2pass_rep; // seled flit output to pass req
output [1:0] ctrl2pass_rep; // seled ctrl output to pass req
output [15:0] flit2local_in_req; // seled flit output to pass req
output [1:0] ctrl2local_in_req; // seled ctrl output to pass req
output [15:0] flit2local_in_rep; // seled flit output to pass req
output [1:0] ctrl2local_in_rep; // seled ctrl output to pass req
output en_pass_req; // enable for pass req fifo to write data to tail
output en_pass_rep; // enable for pass rep fifo to write data to tail
output en_local_in_req; // enable for local in req fifo to write data to tail
output en_local_in_rep; // enable for local in rep fifo to write data to tail
reg [15:0] flit2pass_req; // seled flit output to pass req
reg [1:0] ctrl2pass_req; // seled ctrl output to pass req
reg [15:0] flit2pass_rep; // seled flit output to pass req
reg [1:0] ctrl2pass_rep; // seled ctrl output to pass req
reg [15:0] flit2local_in_req; // seled flit output to pass req
reg [1:0] ctrl2local_in_req; // seled ctrl output to pass req
reg [15:0] flit2local_in_rep; // seled flit output to pass req
reg [1:0] ctrl2local_in_rep; // seled ctrl output to pass req
reg en_pass_req;
reg en_pass_rep;
reg en_local_in_req;
reg en_local_in_rep;
always@(*)
begin
{en_pass_req,flit2pass_req,ctrl2pass_req}={1'b0,flit,ctrl};
{en_pass_rep,flit2pass_rep,ctrl2pass_rep}={1'b0,flit,ctrl};
{en_local_in_req,flit2local_in_req,ctrl2local_in_req}={1'b0,flit,ctrl};
{en_local_in_rep,flit2local_in_rep,ctrl2local_in_rep}={1'b0,flit,ctrl};
if(en_dest_fifo)
begin
case(dest_fifo)
2'b00:{en_pass_req,flit2pass_req,ctrl2pass_req}={1'b1,flit,ctrl};
2'b01:{en_pass_rep,flit2pass_rep,ctrl2pass_rep}={1'b1,flit,ctrl};
2'b10:{en_local_in_req,flit2local_in_req,ctrl2local_in_req}={1'b1,flit,ctrl};
2'b11:{en_local_in_rep,flit2local_in_rep,ctrl2local_in_rep}={1'b1,flit,ctrl};
// default:{en_pass_req,flit2pass_req,ctrl2pass_req}={1'b1,flit,ctrl};
endcase
end
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////////////////////////////////
/// network_interface include: pass fifo, which is used to pass non_local messages to next node ///////////
/// IN_local req fifo and rep fifo,which is used to buffers msgs to local node//
/// OUT_local req fifo and rep fifo ,which is used to buffers msgs leave local//
/// and some other FSMs to help manage these fifos! ////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////
module network_interface(
//input
clk, //global clock
rst, //global reset
ctrl_in, //[2:0] for guiding flit flowing ; 00:nothing, 01:head flit, 10:body flit, 11:tail flit
//ctrl[2] 1:next_node; 0:not_next_node;
flit_in,
dest_fifo_in,
en_IN_req_deq, // from arbiter_for_IN_node in commu_assist
en_IN_rep_deq,
enq_req_data, // from arbiter_for_OUT_req fifo in commu_assist (include ctrl)
enq_rep_data, // from arbiter_for_OUT_rep fifo in commu_assist (include ctrl)
en_OUT_req_enq, // from arbiter_for_OUT_req fifo in commu_assist
en_OUT_rep_enq, // from arbiter_for_OUT_rep fifo in commu_assist
en_local_req_in,
en_local_rep_in,
en_pass_req_in,
en_pass_rep_in,
used_slots_pass_req_in,
used_slots_pass_rep_in, //the pass req fifo of next node says it can receive a flit
//output
deq_req_data, //[17:0]cache or memory dequeue a flit from IN_local req fifo
deq_rep_data, //[17:0]cache or memory dequeue a flit from IN_local rep fifo
req_rdy,
rep_rdy,
en_local_req, // to previous node refer to below notes
en_local_rep,
en_pass_req, // from next node //local_in_req fifo in next node says that it can receive
en_pass_rep, // refer to notes below
used_slots_pass_req,
used_slots_pass_rep,
flit_out,
ctrl_out,
dest_fifo_out,
OUT_req_rdy,
OUT_rep_rdy
);
/////// parameter for reply cmd
parameter wbrep_cmd=5'b10000;
parameter C2Hinvrep_cmd=5'b10001;
parameter flushrep_cmd=5'b10010;
parameter ATflurep_cmd=5'b10011;
parameter shrep_cmd=5'b11000;
parameter exrep_cmd=5'b11001;
parameter SH_exrep_cmd=5'b11010;
parameter SCflurep_cmd=5'b11100;
parameter instrep_cmd=5'b10100;
parameter C2Cinvrep_cmd=5'b11011;
parameter nackrep_cmd=5'b10101;
parameter flushfail_rep_cmd=5'b10110;
parameter wbfail_rep_cmd=5'b10111;
parameter local_id=2'b00;
parameter next_id=local_id+1;
//input
input clk;
input rst;
input [2:0] ctrl_in;
input [15:0] flit_in;
input [1:0] dest_fifo_in;
input en_IN_req_deq; // from arbiter_for_IN_node in commu_assist
input en_IN_rep_deq;
input [17:0] enq_req_data; // from arbiter_for_OUT_req fifo in commu_assist (include ctrl)
input [17:0] enq_rep_data; // from arbiter_for_OUT_rep fifo in commu_assist (include ctrl)
input en_OUT_req_enq; // from arbiter_for_OUT_req fifo in commu_assist
input en_OUT_rep_enq; // from arbiter_for_OUT_rep fifo in commu_assist
input en_local_req_in; // from next node //local_in_req fifo in next node says that it can receive
input en_local_rep_in; //local_in_req fifo in next node says that it can receive
input en_pass_req_in; //pass_req fifo in next node says that it can receive
input en_pass_rep_in; //pass_req fifo in next node says that it can receive
input [3:0] used_slots_pass_req_in; //pass_req fifo in next node says how many used slots
input [3:0] used_slots_pass_rep_in; //pass_req fifo in next node says how many used slots
//output
output [2:0] ctrl_out;
output [15:0] flit_out;
output [1:0] dest_fifo_out; // used for arbiter_enq to select which fifo to write in
output OUT_req_rdy; // it's ready for ic_req_upload,dc_req_upload or mem_req_upload to enq their req flit
output OUT_rep_rdy; // it's ready for dc_rep_upload or mem_rep_upload to enq their rep flit
output [17:0] deq_req_data; // from IN_req fifo (include ctrl)
output [17:0] deq_rep_data; // from IN_rep fifo (include ctrl)
output req_rdy; // it's ready for arbiter_IN_node to dequeue flit from In req fifo
output rep_rdy; // it's ready for arbiter_IN_node to dequeue flit from In rep fifo
output en_local_req; // to previous node refer to above notes
output en_local_rep;
output en_pass_req;
output en_pass_rep;
output [3:0] used_slots_pass_req;
output [3:0] used_slots_pass_rep;
// output from pass fifos and OUT_local fifos
wire [17:0] pass_rep_dout;
wire [17:0] out_local_rep_dout;
wire [17:0] pass_req_dout;
wire [17:0] out_local_req_dout;
//full state of fifos
wire pass_req_full;
wire pass_rep_full;
wire in_req_full;
wire in_rep_full;
wire out_req_full;
wire out_rep_full;
//empty state of fifos
wire pass_req_empty;
wire pass_rep_empty;
wire IN_local_req_empty;
wire IN_local_rep_empty;
wire OUT_local_req_empty;
wire OUT_local_rep_empty;
//// mux 4 kinds of flits to output to next node
reg [17:0] temp_flit_out;
// arbietr for deq
wire [3:0] select;
wire next_pass_req;
wire next_pass_rep;
wire next_local_req;
wire next_local_rep;
//arbiter for enq
wire [15:0] flit2pass_req; // seled flit output to pass req
wire [1:0] ctrl2pass_req; // seled ctrl output to pass req
wire [15:0] flit2pass_rep; // seled flit output to pass req
wire [1:0] ctrl2pass_rep; // seled ctrl output to pass req
wire [15:0] flit2local_in_req; // seled flit output to pass req
wire [1:0] ctrl2local_in_req; // seled ctrl output to pass req
wire [15:0] flit2local_in_rep; // seled flit output to pass req
wire [1:0] ctrl2local_in_rep; // seled ctrl output to pass req
wire en_pass_req; // enable for pass req fifo to write data to tail
wire en_pass_rep; // enable for pass rep fifo to write data to tail
wire en_local_in_req; // enable for local in req fifo to write data to tail
wire en_local_in_rep; // enable for local in rep fifo to write data to tail
// output to uploads saying it's ready for them to receive flits from uploads
assign OUT_req_rdy=!out_req_full;
assign OUT_rep_rdy=!out_rep_full;
// to previous node refer to below notes
assign en_local_req=!in_req_full;
assign en_local_rep=!in_rep_full;
//assign en_pass_req=!pass_req_full; // from next node //local_in_req fifo in next node says that it can receive
//assign en_pass_rep=!pass_rep_full; // refer to notes below
// output to arbiter_IN_node to tell it it's ready for them to deq flit from IN_local fifos
assign req_rdy=!IN_local_req_empty;
assign rep_rdy=!IN_local_rep_empty;
//wires just for convenience
assign flit_out=temp_flit_out[15:0];
assign ctrl_out=temp_flit_out[17:16];
wire next_or_not;
assign next_or_not=(flit_out[15:14]==next_id)?1'b1:1'b0;
assign dest_fifo_out={next_or_not,flit_out[9]};
// figure out which fifo output its flit to next node
always@(*)
begin
case(select)
4'b0001:temp_flit_out=pass_rep_dout;
4'b0010:temp_flit_out=out_local_rep_dout;
4'b0100:temp_flit_out=pass_req_dout;
4'b1000:temp_flit_out=out_local_req_dout;
default:temp_flit_out=pass_rep_dout;
endcase
end
reg [1:0] OUT_rep_length_code;
// use hesd flit of every msg at the head of OUT_local_rep fifo
// to produce OUT_rep_length_code ,which is usefull to avoid deadlock
always@(*)
begin
if(out_local_rep_dout[17:16]==2'b01&&(out_local_rep_dout[9:5]==ATflurep_cmd||out_local_rep_dout[9:5]==wbrep_cmd))
OUT_rep_length_code=2'b11;//msg has 11 flits
else if(out_local_rep_dout[17:16]==2'b01&&(out_local_rep_dout[9:5]==exrep_cmd||out_local_rep_dout[9:5]==shrep_cmd||out_local_rep_dout[9:5]==instrep_cmd||out_local_rep_dout[9:5]==SH_exrep_cmd))
OUT_rep_length_code=2'b10; //msg has 9 flits
else if(out_local_rep_dout[17:16]==2'b01&&(out_local_rep_dout[9:5]==nackrep_cmd||out_local_rep_dout[9:5]==flushrep_cmd||out_local_rep_dout[9:5]==C2Hinvrep_cmd||out_local_rep_dout[9:5]==flushfail_rep_cmd||out_local_rep_dout[9:5]==wbfail_rep_cmd))
OUT_rep_length_code=2'b01; //msg has 3 flits
else if(out_local_rep_dout[17:16]==2'b01&&(out_local_rep_dout[9:5]==C2Cinvrep_cmd||out_local_rep_dout[9:5]==nackrep_cmd))
OUT_rep_length_code=2'b00; // msg has only 1 flit
else //default valus
OUT_rep_length_code=2'b00; // msg has only 1 flit
end
my_scfifo pass_req_fifo(
\t .aclr(rst),
\t .clock(clk),
\t .data({ctrl2pass_req,flit2pass_req}),
\t .rdreq(select[2]),
\t .wrreq(en_pass_req),
\t .empty(pass_req_empty),
\t .full(pass_req_full),
\t .q(pass_req_dout),
\t .usedw(used_slots_pass_req)
\t );
my_scfifo pass_rep_fifo(
\t .aclr(rst),
\t .clock(clk),
\t .data({ctrl2pass_rep,flit2pass_rep}),
\t .rdreq(select[0]),
\t .wrreq(en_pass_rep),
\t .empty(pass_rep_empty),
\t .full(pass_rep_full),
\t .q(pass_rep_dout),
\t .usedw(used_slots_pass_rep)
\t );
my_scfifo IN_req_fifo(
\t .aclr(rst),
\t .clock(clk),
\t .data({ctrl2local_in_req,flit2local_in_req}),
\t .rdreq(en_IN_req_deq),
\t .wrreq(en_local_in_req),
\t .empty(IN_local_req_empty),
\t .full(in_req_full),
\t .q({deq_req_data}),
\t .usedw()
\t );
my_scfifo IN_rep_fifo(
\t .aclr(rst),
\t .clock(clk),
\t .data({ctrl2local_in_rep,flit2local_in_rep}),
\t .rdreq(en_IN_rep_deq),
\t .wrreq(en_local_in_rep),
\t .empty(IN_local_rep_empty),
\t .full(in_rep_full),
\t .q({deq_rep_data}),
\t .usedw()
\t );
\t
my_scfifo OUT_req_fifo(
\t .aclr(rst),
\t .clock(clk),
\t .data({enq_req_data}),
\t .rdreq(select[3]),
\t .wrreq(en_OUT_req_enq),
\t .empty(OUT_local_req_empty),
\t .full(out_req_full),
\t .q(out_local_req_dout),
\t .usedw()
\t );
\t
my_scfifo OUT_rep_fifo(
\t .aclr(rst),
\t .clock(clk),
\t .data({enq_rep_data}),
\t .rdreq(select[1]),
\t .wrreq(en_OUT_rep_enq),
\t .empty(OUT_local_rep_empty),
\t .full(out_rep_full),
\t .q(out_local_rep_dout),
\t .usedw()
\t );
///////////////////////////////////////////////////////////////////////////////////////////
////////////////////Here need a arbiter to decide which flit to select to send out/////////
////////////////////from pass rep/req fifo, OUT_local rep/req fifo ////////////////
///////////////////////////////////////////////////////////////////////////////////////////
arbiter_4_deq my_arbiter_4_deq(
//input
.clk(clk),
.rst(rst),
.pass_req_empty(pass_req_empty),
.pass_rep_empty(pass_rep_empty),
.OUT_local_req_empty(OUT_local_req_empty),
.OUT_local_rep_empty(OUT_local_rep_empty),
.OUT_rep_length_code(OUT_rep_length_code),
.en_local_req(en_local_req_in),
.en_local_rep(en_local_rep_in),
.en_pass_req(en_pass_req_in),
.en_pass_rep(en_pass_rep_in),
.used_slots_pass_req(used_slots_pass_req_in),
.used_slots_pass_rep(used_slots_pass_rep_in),
.next_pass_req(next_pass_req),
.next_pass_rep(next_pass_rep),
.next_local_req(next_local_req),
.next_local_rep(next_local_rep),
//output
.select(select)
);
///////////////////////////////////////////////////////////////////////////////////////////
////////////////////Here need a arbiter to decide which fifo to select to write flit in////
////////////////////write to pass rep/req fifo ,IN_local rep/req fifo ///////////////
///////////////////////////////////////////////////////////////////////////////////////////
arbiter_4_enq my_arbiter_4_enq( // input
.flit(flit_in),
.ctrl(ctrl_in),
.en_dest_fifo(|ctrl_in),
.dest_fifo(dest_fifo_in),
// output
.flit2pass_req(flit2pass_req), // seled flit output to pass req
.ctrl2pass_req(ctrl2pass_req), // seled ctrl output to pass req
.flit2pass_rep(flit2pass_rep), // seled flit output to pass rep
.ctrl2pass_rep(ctrl2pass_rep), // seled ctrl output to pass rep
.flit2local_in_req(flit2local_in_req), // seled flit output to local in req
.ctrl2local_in_req(ctrl2local_in_req), // seled ctrl output to local in req
.flit2local_in_rep(flit2local_in_rep), // seled flit output to local in rep
.ctrl2local_in_rep(ctrl2local_in_rep), // seled ctrl output to local in rep
.en_pass_req(en_pass_req),
.en_pass_rep(en_pass_rep),
.en_local_in_req(en_local_in_req),
.en_local_in_rep(en_local_in_rep)
);
endmodule
///////////////////////////////////////////////////////////////////////////////////////////
////////////here we process cache request or memory request for dequeuing IN_local fifo////
///////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////
////////////here we process cache reply or memory reply for dequeuing OUT_local fifo///////
////////////////////////////////////////////////////////////////////////////////////////////
|
/// date:2016/3/9
/// engineer :ZhaiShaoMin
/// module name: communication assist
/// module function: put many components,such as arbiter and download_flit_fsm and
/// upload_flit_fsm,together, then we can get a bigger module which named communication assist.
/// this module is responsible for handling flits from IN fifos and flits to OUT fifos ,as well as
/// providing firendly interfaces to inst cache ,data cache and memory
////////////////////////////////////////////////////////////////////////////////
/// submoddules: arbiter_IN_node, // guiding flits from IN_fifos to the right places with high efficiency
/// arbiter_for_dc, // select source flits from cpu_access,IN_fifos msg and local memory access
/// arbiter_for_mem, // select source flits from local inst cache or local data cache or IN_fifos
/// arbiter_for_OUT_rep,// select src flit from dc_rep_upload and m_rep_upload
/// arbiter_for_OUT_req,// select flit from ic_req_upload or dc_req_upload or m_req_upload
/// ic_download, // receive rep from IN_rep or local mem
/// dc_download, // receive rep from IN_rep or req from IN_req
/// m_download, // receive rep from IN_rep or req from IN_req
/// m_d_areg, // receive rep or req from local mem
/// d_m_areg, // receive req or rep fromlocal data cache
/// i_m_areg, // receive req from local inst cache
/// ic_req_upload, //upload flits from ic(inst cache) to OUT_req
/// dc_rep_upload, //upload flits from dc to OUT_req
/// m_rep_upload, //upload flits from mem to OUT_req
/// dc_req_upload, //upload flits from dc to OUT_rep
/// m_req_upload //upload flits from mem to OUT_req
////////////////////////////////////////////////////////////////////////////////
module commu_assist(//input
clk,
rst,
// I/O between arbiter and IN fifos
// input
req_flit_in, //flit from IN req fifo
req_rdy, // it's ready for arbiter_IN_node to dequeue flit from In req fifo
req_ctrl_in, //control signals from In fifo indicate what kind of flit under transfering
rep_flit_in,
rep_rdy,
rep_ctrl_in,
// output
ack_rep, // arbiter tell IN rep fifo that it's ready to receive flit,
// as well as been used by IN rep fifo as a deq rdy signal
ack_req, //req_rep and req_req are better!
/// I/O about OUT_req/rep fifo
//input
OUT_req_rdy, // arbiter_OUT_req tell OUT req fifo to be ready to receive flit from commu_assist
OUT_rep_rdy, // arbiter_OUT_rep ......
// output
OUT_req_ctrl, // used to tell the frame of msg. 00 means nothing 01 means head flit,
// 10 means body flit,11 means tail flit, exception is invrep which has only one flit.
OUT_req_flit, // flit outputed to OUT req fifo
OUT_req_ack, // same as rdy signal saying now I'm a valid flit, also a enq signal for OUT req fifo
OUT_rep_ctrl, // similar function as above
OUT_rep_flit,
OUT_rep_ack,
/// I/O about inst cache
// input
// v_req_inst, // indicate that's a valid inst request from pc
// pc_addr, // addr of pc used to look up inst cache to find intended inst
// to OUT_req
v_flits_2_ic_req, // saying I'm a valid req flits to OUT req fifo
flits_2_ic_req, // req flits output to OUT req fifo
// to local mem
v_req_i_m_areg, // saying I'm a valid req flits to local home(memory)
req_i_m_areg, // req flits output to local home
// output
v_inst_rep, // saying that is a valid rep data back to pipeline
inst_data, // rep data (inst word) back to inst cache.
/// I/O about data cache
// input
dcache_done_access, // data cache tell arbiter_for_dcache previous access had done via this signal
// output
flits_dcache, // arbiter select a flits to dcache
v_flits_dcache, // means it's a valid flits to dcache
/// I/O about cpu_req_cache about ll/ld/st/sc
// input
v_cpu_access, // means it's a valid access from pipeline
cpu_head, // this part include access ctrl info such as ll or ld ,sc or st ,wr or rd
cpu_addr, //addr of mem ops
cpu_data, // data of store or store-condition
/// I/O about memory
// input
ack_m_donwload, // response to m_download saying i'm now reading flits
ack_d_m_donwload, // similar as above
ack_i_m_donwload, //similar as above
mem_access_done,
mem_ic_download, // flits from mem to ic_download
v_mem_ic_download, // flit above is valid
mem_m_d_areg, // flits from mem to m_d_areg
v_mem_m_d_areg, // it's a valid flits to m_d_areg
mem_m_req, // similar as above
v_mem_m_req,
mem_m_rep,
v_mem_m_rep, //similar as above
en_m_flits_max_rep,
m_flits_max_rep,
en_m_flits_max_req,
m_flits_max_req,
en_inv_ids,
inv_ids_in,
// output
v_m_download, // valic flits from m_download to mem
m_donwload, //flits from m_download to mem
v_d_m_areg, // valid flits from d_m_areg to mem
d_m_areg, // flits from d_m_areg to mem
v_i_m_areg,
i_m_areg,
ic_download_fsm_state, //here are some fsm state indicating whether some state elements is idle or busy
m_d_areg_fsm_state, // which is useful to decide whether or not to output flits from mem to these elements
m_rep_fsm_state,
m_req_fsm_state,
/// I/O about data cache
//input
dcache_d_m_areg, //access via flits from data cache to local mem
v_dcache_d_m_areg, // means it's avalid access
dcache_dc_req, // access via flits to OUT_req_upload corresponding to dcache
v_dcache_dc_req, // means it's avalid access
dcache_dc_rep,
v_dcache_dc_rep,
en_dc_flits_max_rep,
dc_flits_max_rep,
/// output
d_m_areg_fsm_state, // fsm state outputed from commu_assist intended to tell dcache if it's able
// to send flits to these units
dc_req_fsm_state,
dc_rep_fsm_state
);
// I/O between arbiter and IN fifos
// input
input clk;
input rst;
input [15:0] req_flit_in;
input req_rdy;
input [1:0] req_ctrl_in;
input [15:0] rep_flit_in;
input rep_rdy;
input [1:0] rep_ctrl_in;
// output
output ack_rep;
output ack_req;
input OUT_req_rdy;
input OUT_rep_rdy;
// output
output [1:0] OUT_req_ctrl;
output [15:0] OUT_req_flit;
output OUT_req_ack;
output [1:0] OUT_rep_ctrl;
output [15:0] OUT_rep_flit;
output OUT_rep_ack;
// input
// input v_req_inst;
// input [31:0] pc_addr;
input v_flits_2_ic_req;
input [47:0] flits_2_ic_req;
// to local mem
input v_req_i_m_areg;
input [31:0] req_i_m_areg;
// output
output v_inst_rep;
output [127:0] inst_data;
/// I/O about data cache
// input
input dcache_done_access;
// output
output [143:0] flits_dcache;
output v_flits_dcache;
/// I/O about cpu_req_cache about ll/ld/st/sc
// input
input v_cpu_access;
input [3:0] cpu_head;
input [31:0] cpu_addr;
input [31:0] cpu_data;
/// I/O about memory
// input
input ack_m_donwload;
input ack_d_m_donwload;
input ack_i_m_donwload;
input mem_access_done;
input [127:0] mem_ic_download;
input v_mem_ic_download;
input [143:0] mem_m_d_areg;
input v_mem_m_d_areg;
input [47:0] mem_m_req;
input v_mem_m_req;
input [143:0] mem_m_rep;
input v_mem_m_rep;
input en_m_flits_max_rep;
input [3:0] m_flits_max_rep;
input en_m_flits_max_req;
input [1:0] m_flits_max_req;
input en_inv_ids; //from mem
input inv_ids_in;
// output
output v_m_download;
output [175:0] m_donwload;
output v_d_m_areg;
output [175:0] d_m_areg;
output v_i_m_areg;
output [47:0] i_m_areg;
output [1:0] ic_download_fsm_state;
output m_d_areg_fsm_state;
output m_rep_fsm_state;
output [1:0] m_req_fsm_state;
/// I/O about data cache
//input
input [175:0] dcache_d_m_areg;
input v_dcache_d_m_areg;
input [47:0] dcache_dc_req;
input v_dcache_dc_req;
input [175:0] dcache_dc_rep;
input v_dcache_dc_rep;
input en_dc_flits_max_rep;
input [3:0] dc_flits_max_rep;
/// output
output d_m_areg_fsm_state;
output dc_req_fsm_state;
output dc_rep_fsm_state;
///////////////////////////////////////////////
///////////// submodules//////////////////////
//////////////////////////////////////////////
//output of arbiter_IN_node
wire ack_req;
wire ack_rep;
wire v_ic_net;
wire [15:0] flit_ic_net;
wire [1:0] ctrl_ic_net;
wire v_dc_net;
wire [15:0] flit_dc_net;
wire [1:0] ctrl_dc_net;
wire v_mem_net;
wire [15:0] flit_mem_net;
wire [1:0] ctrl_mem_net;
//output of arbiter_for_dcache
wire [143:0] flits_dcache_abter;
wire v_flits_dcache_abter;
wire re_dc_download_flits;
wire re_cpu_access_flits;
wire re_m_d_areg_flits;
wire cpu_done_access;
wire dc_download_done_access;
wire m_d_areg_done_access;
// output of arbiter_for_mem
wire ack_m_download_net;
wire ack_d_m_areg_net;
wire ack_i_m_areg_net;
wire v_m_download_m_net;
wire v_d_m_areg_m_net;
wire v_i_m_areg_m_net;
//output of arbiter_for_OUT_rep
wire OUT_rep_ack;
wire ack_dc_rep_net;
wire ack_mem_rep_net;
wire [1:0] select2_net;
//output of arbiter_for_OUT_req
wire OUT_req_ack;
wire ack_ic_req_net;
wire ack_dc_req_net;
wire ack_mem_req_net;
wire [1:0] select3_net ;
//output of ic_download
wire [1:0] ic_download_state_net;
//wire [127:0] inst_data;
wire v_inst_rep;
//output of dc_download
wire v_flits_dcache;
wire [143:0] flits_dcache;
wire [1:0] dc_download_state_net;
//output of m_download
wire v_m_download;
wire [175:0] m_donwload;
wire [1:0] mem_download_state_net;
//output of m_d_areg
wire [143:0] m_d_areg_flits_net;
wire v_m_d_areg_flits_net;
wire m_d_areg_fsm_state;
//ooutput of d_m_areg
wire [175:0] d_m_areg;
wire v_d_m_areg;
wire d_m_areg_fsm_state;
//output of i_m_areg
wire [47:0] i_m_areg;
wire v_i_m_areg;
//output of m_rep_upload
wire [15:0] m_rep_flit_net;
wire v_m_rep_flit_net;
wire m_rep_fsm_state;
wire [1:0] m_rep_ctrl_net;
//output of dc_rep_upload
wire [15:0] dc_rep_flit_net;
wire v_dc_rep_flit_net;
wire dc_rep_fsm_state;
wire [1:0] dc_rep_ctrl_net;
//output of ic_req_upload
wire [15:0] ic_req_flit_net;
wire v_ic_req_flit_net;
wire [1:0] ic_download_fsm_state;
wire [1:0] ic_req_ctrl_net;
//output of m_req_upload
wire [1:0] m_req_ctrl_net;
wire [15:0] m_req_flit_net;
wire [1:0] m_req_fsm_state;
wire v_m_req_flit_net;
//output of dc_req_upload
wire [15:0] dc_req_flit_net;
wire v_dc_req_flit_net;
wire dc_req_fsm_state;
wire [1:0] dc_req_ctrl_net;
reg [15:0] OUT_req_flit;
reg [1:0] OUT_req_ctrl;
//mux OUT_req_ctrl and OUT_req_flit
always@(*)
begin
case(select3_net)
3'b001:
begin
\t OUT_req_ctrl=m_req_ctrl_net;
\t OUT_req_flit=m_req_flit_net;
\t end
3'b010:
begin
\t OUT_req_ctrl=dc_req_ctrl_net;
OUT_req_flit=dc_req_flit_net;
\t end
3'b100:
begin
\t OUT_req_ctrl=ic_req_ctrl_net;
OUT_req_flit=ic_req_flit_net;
\t end
\tdefault:
begin
\t OUT_req_ctrl=2'b00;
OUT_req_flit=ic_req_ctrl_net;
\t end
\tendcase
end
reg [15:0] OUT_rep_flit;
reg [1:0] OUT_rep_ctrl;
//mux OUT_req_ctrl and OUT_req_flit
always@(*)
begin
case(select2_net)
2'b01:
begin
\t OUT_rep_ctrl=dc_rep_ctrl_net;
OUT_rep_flit=dc_rep_flit_net;
\t end
2'b10:
begin
\t OUT_rep_ctrl=m_rep_ctrl_net;
OUT_rep_flit=m_rep_flit_net;
\t end
\tdefault:
begin
\t OUT_rep_ctrl=2'b00;
OUT_rep_flit=m_rep_flit_net;
\t end
\tendcase
end
arbiter_IN_node arbiter_IN_node_dut(
//input
.clk(clk),
.rst(rst),
.in_req_rdy(req_rdy),
.in_rep_rdy(rep_rdy),
.req_ctrl_in(req_ctrl_in),
.rep_ctrl_in(rep_ctrl_in),
.req_flit_in(req_flit_in),
.rep_flit_in(rep_flit_in),
.ic_download_state_in(ic_download_state_net), // (net)from ic_downlaod
.dc_download_state_in(dc_download_state_net), // from dc_download
.mem_download_state_in(mem_download_state_net), // from mem_downlaod
//output
.ack_req(ack_req), // to IN_req fifo
.ack_rep(ack_rep), // to IN_rep fifo
.v_ic(v_ic_net), // to ic_download
.flit_ic(flit_ic_net),
.ctrl_ic(ctrl_ic_net),
.v_dc(v_dc_net), // to dc_download
.flit_dc(flit_dc_net),
.ctrl_dc(ctrl_dc_net),
.v_mem(v_mem_net), // to mem_download
.flit_mem(flit_mem_net),
.ctrl_mem(ctrl_mem_net)
); // guiding flits from IN_fifos to the right places with high efficiency
arbiter_for_dcache arbiter_for_dcache_dut (
//input
.clk(clk),
.rst(rst),
.dcache_done_access(dcache_done_access), // from data cache
.v_dc_download(v_flits_dcache), // from dc_downlaod
.dc_download_flits(flits_dcache),
.v_cpu(v_cpu_access), // from cpu mem stage
.cpu_access_flits({cpu_head,cpu_addr,cpu_data}),
.v_m_d_areg(v_m_d_areg_flits_net), // from local mem
.m_d_areg_flits(m_d_areg_flits_net),
//output
.flits_dc(flits_dcache_abter), // selected flits to data cache
.v_flits_dc(v_flits_dcache_abter),
.re_dc_download_flits(re_dc_download_flits), // to dc_donwlaod
.re_cpu_access_flits(re_cpu_access_flits), // to cpu mem stage
.re_m_d_areg_flits(re_m_d_areg_flits), // to local mem
.cpu_done_access(cpu_done_access),
.dc_download_done_access(dc_download_done_access),
.m_d_areg_done_access(m_d_areg_done_access)
); // select source flits from cpu_access,IN_fifos msg and local memory access
arbiter_for_mem arbiter_for_mem_dut(
//input
.clk(clk),
.rst(rst),
.v_mem_download(v_m_download), // from mem_downlaod
.v_d_m_areg(v_d_m_areg), // from local data cache
.v_i_m_areg(v_i_m_areg), // from local inst cache
.mem_access_done(mem_access_done), // from local mem
//output
.ack_m_download(ack_m_download_net), // to m_download
.ack_d_m_areg(ack_d_m_areg_net), // to data cache via d_m_areg
.ack_i_m_areg(ack_i_m_areg_net),
.v_m_download_m(v_m_download_m_net), // to mem syaing these flits is valid
.v_d_m_areg_m(v_d_m_areg_m_net),
.v_i_m_areg_m(v_i_m_areg_m_net)
); // select source flits from local inst cache or local data cache or IN_fifos
\t\t\t\t\t\t\t\t\t
arbiter_for_OUT_rep arbiter_for_OUT_rep_dut(
//input
.clk(clk),
.rst(rst),
.OUT_rep_rdy(OUT_rep_rdy), // from OUT_rep fifo
.v_dc_rep(v_dc_rep_flit_net), // from dc_upload
.v_mem_rep(v_m_rep_flit_net), // from mem_upload
.dc_rep_flit(dc_rep_flit_net),
.mem_rep_flit(m_rep_flit_net),
.dc_rep_ctrl(dc_rep_ctrl_net),
.mem_rep_ctrl(m_rep_ctrl_net),
//output
.ack_OUT_rep(OUT_rep_ack), // to OUT_rep fifo
.ack_dc_rep(ack_dc_rep_net), // to dc_upload
.ack_mem_rep(ack_mem_rep_net), //to mem_upload
.select(select2_net) // select 1/2
);// select src flit from dc_rep_upload and m_rep_upload
arbiter_for_OUT_req arbiter_for_OUT_req_dut(
//input
.clk(clk),
.rst(rst),
.OUT_req_rdy(OUT_req_rdy), // from OUT_req fifo
.v_ic_req(v_ic_req_flit_net), // from ic_upload_req
.v_dc_req(v_dc_req_flit_net), // from dc_upload_req
.v_mem_req(v_m_req_flit_net), // from mem_upload_req
.ic_req_ctrl(ic_req_ctrl_net),
.dc_req_ctrl(dc_req_ctrl_net),
.mem_req_ctrl(m_req_ctrl_net),
//output
.ack_OUT_req(OUT_req_ack), // to OUT_req
.ack_ic_req(ack_ic_req_net), // to ic_upload_req
.ack_dc_req(ack_dc_req_net), // to dc_
.ack_mem_req(ack_mem_req_net), // to mem_
.select(select3_net)// select one from three
);// select flit from ic_req_upload or dc_req_upload or m_req_upload
ic_download ic_download_dut(
//input
.clk(clk),
.rst(rst),
.rep_flit_ic(flit_ic_net), //from arbiter_for_IN_node
.v_rep_flit_ic(v_ic_net),
.rep_ctrl_ic(ctrl_ic_net),
.mem_flits_ic(mem_ic_download), // from local mem
.v_mem_flits_ic(v_mem_ic_download),
//output
.ic_download_state(ic_download_state_net), // to local mem and arbiter_IN_node
.inst_word_ic(inst_data), // to front of cpu
.v_inst_word(v_inst_rep)
); // receive rep from IN_rep or local mem
\t\t\t\t\t\t
dc_download dc_download_dut(
//input
.clk(clk),
.rst(rst),
.IN_flit_dc(flit_dc_net), // from arrbiter_IN_node
.v_IN_flit_dc(v_dc_net),
.In_flit_ctrl_dc(ctrl_dc_net),
.dc_done_access(dcache_done_access), // from data cache
//output
.v_dc_download(v_flits_dcache), // to data cache
.dc_download_flits(flits_dcache),
.dc_download_state(dc_download_state_net) // to arbiter_IN_node
); // receive rep from IN_rep or req from IN_req
m_download m_download_dut(
//input
.clk(clk),
.rst(rst),
.IN_flit_mem(flit_mem_net), // from arrbiter_IN_node
.v_IN_flit_mem(v_mem_net),
.In_flit_ctrl(ctrl_mem_net),
.mem_done_access(mem_access_done), // from mem
//output
.v_m_download(v_m_download), // to arbiter_for_mem
.m_download_flits(m_donwload),
.m_download_state(mem_download_state_net) // to arbiter_IN_node
); // receive rep from IN_rep or req from IN_req
m_d_areg m_d_areg_dut(
//input
.clk(clk),
.rst(rst),
.m_flits_d(mem_m_d_areg), // from local mem
.v_m_flits_d(v_mem_m_d_areg),
.dc_done_access(dcache_done_access), // from data cache
//output
.m_d_areg_flits(m_d_areg_flits_net), // to data cache
.v_m_d_areg_flits(v_m_d_areg_flits_net),
.m_d_areg_state( m_d_areg_fsm_state) // to local mem
); // receive rep or req from local mem
d_m_areg d_m_areg_dut(
//input
.clk(clk), ////////////////////////////note :here local mem or data cache equals mem or data cache
.rst(rst),
.d_flits_m(dcache_d_m_areg), // from data cache
.v_d_flits_m(v_dcache_d_m_areg),
.mem_done_access(mem_access_done), // from local mem
///output
.d_m_areg_flits(d_m_areg), // to local mem
.v_d_m_areg_flits(v_d_m_areg),
.d_m_areg_state(d_m_areg_fsm_state) // to data cache
); // receive req or rep fromlocal data cache
i_m_areg i_m_areg_dut(
//input
.clk(clk),
.rst(rst),
.i_flits_m(req_i_m_areg), // from inst cache
.v_i_flits_m(v_req_i_m_areg),
.mem_done_access(mem_access_done), // from mem
//output
.i_m_areg_flits(i_m_areg), // to mem
.v_i_areg_m_flits(v_i_m_areg)
); // receive req from local inst cache
//note : here we need a ctrl output
m_rep_upload m_rep_upload_dut (
//input
.clk(clk),
.rst(rst),
.m_flits_rep(mem_m_rep), // from mem
.v_m_flits_rep(v_mem_m_rep),
.flits_max(m_flits_max_rep),
.en_flits_max(en_m_flits_max_rep),
.rep_fifo_rdy(ack_mem_rep_net), // from OUT_rep fifo
//output
.m_flit_out(m_rep_flit_net), // to arbiter_OUT_rep
.v_m_flit_out(v_m_rep_flit_net),
\t\t\t\t\t\t\t\t.m_ctrl_out(m_rep_ctrl_net),
.m_rep_upload_state(m_rep_fsm_state) // to mem
); //upload flits from mem to OUT_req
\t\t\t\t\t\t\t\t
//note : here we need a ctrl output
dc_rep_upload dc_rep_upload_dut(
//input
.clk(clk),
.rst(rst),
.dc_flits_rep(dcache_dc_rep), // from dc
.v_dc_flits_rep(v_dcache_dc_rep),
.flits_max(dc_flits_max_rep),
.en_flits_max(en_dc_flits_max_rep),
.rep_fifo_rdy(ack_dc_rep_net), // from OUT_rep fifo
//output
.dc_flit_out(dc_rep_flit_net), // to arbiter_OUT_rep
.v_dc_flit_out(v_dc_rep_flit_net),
\t\t\t\t\t\t\t\t .dc_ctrl_out(dc_rep_ctrl_net),
.dc_rep_upload_state(dc_rep_fsm_state) //to dc
); //upload flits from dc to OUT_req
//note : here we need a ctrl output
ic_req_upload ic_req_upload_dut(
//input
.clk(clk),
.rst(rst),
.ic_flits_req(flits_2_ic_req),// from ic
.v_ic_flits_req(v_flits_2_ic_req),
//here need a ctrl .req_fifo_rdy(ack_ic_req_net),
//output
.ic_flit_out(ic_req_flit_net), // to arbiter_OUT_req
.v_ic_flit_out(v_ic_req_flit_net),
\t\t\t\t\t\t\t\t .ic_ctrl_out(ic_req_ctrl_net),
.ic_req_upload_state(ic_download_fsm_state) // to inst cache
); //upload flits from ic(inst cache) to OUT_req
//note : here we need a ctrl output
m_req_upload m_req_upload_dut(
//input
.clk(clk),
.rst(rst),
.v_flits_in(v_mem_m_req), // from mem
.out_req_fifo_rdy_in(ack_mem_req_net), //from OUT_req_fifo
.en_inv_ids(en_inv_ids), //from mem
.inv_ids_in(inv_ids_in),
.flits_max_in(m_flits_max_req),
.head_flit(mem_m_req[47:32]),
.addrhi(mem_m_req[31:16]),
.addrlo(mem_m_req[15:0]),
//output
.ctrl_out(m_req_ctrl_net), // to OUT_req_fifo
.flit_out(m_req_flit_net),
.fsm_state(m_req_fsm_state), // to mem
.v_flit_to_req_fifo(v_m_req_flit_net)
); //upload flits from mem to OUT_req
//note : here we need a ctrl output
dc_req_upload dc_req_upload_dut(
//input
.clk(clk),
.rst(rst),
.dc_flits_req(dcache_dc_req), // from dc
.v_dc_flits_req(v_dcache_dc_req),
.req_fifo_rdy(ack_dc_req_net), // from OUT_req_fifo
//output
.dc_flit_out(dc_req_flit_net), // to OUT_req_fifo
.v_dc_flit_out(v_dc_req_flit_net),
\t\t\t\t\t\t\t\t .dc_ctrl_out(dc_req_ctrl_net),
.dc_req_upload_state(dc_req_fsm_state) // to dc
); //upload flits from dc to OUT_rep
endmodule
|
// Block RAM initialization
//
//
module BLOCK_RAM_INIT (data_out, ADDR, data_in, CLK, WE);
output[3:0] data_out;
input [2:0] ADDR;
input [3:0] data_in;
input CLK, WE;
reg [3:0] mem [7:0];
reg [3:0] read_addr;
initial
begin
$readmemb("data.dat", mem); //?data.dat? contains initial RAM
//contents, it gets put into the bitfile
end //and loaded at configuration time.
//(Remake bits to change contents)
always@(posedge CLK)
read_addr <= ADDR;
assign data_out = mem[read_addr];
always @(posedge CLK)
if (WE) mem[ADDR] = data_in;
endmodule
|
//date:2016/3/13
//engineer:ZhaiShaoMin
//module name: it includes all pipeline stages and has interfaces with inst cache and data cache
// and all necessary instances are refered here!
module core(//input
clk,
rst,
v_inst,
inst,
v_data,
data,
//output
pc,
v_pc,
v_mem,
mem_head,
mem_addr,
mem_data
);
parameter jal_btb_type=2'b10;
parameter jr_btb_type=2'b11;
//input
input clk;
input rst;
input v_inst;
input [31:0] inst;
input v_data;
input [31:0] data;
//output
output [31:0] pc;
output v_pc;
output v_mem;
output [3:0] mem_head;
output [31:0] mem_addr;
output [31:0] mem_data;
// I/O about pc
wire v_pc;
wire [31:0] pc;
wire [31:0] pc_plus4;
// I/O about btb
//wire if_flush;
//wire [31:0] pc_plus4_reg;
//wire [31:0] inst_reg;
wire [1:0] btb_type_out;
wire [31:0] btb_target_out;
wire btb_v;
wire en_btb_pred;
// output of PHT
wire pred_out;
wire [2:0] BHR_rd;
wire [1:0] PHT_out;
//output of RAS
wire [31:0] ret_addr_out;
//output of if_id_reg
wire [31:0] if_id_pred_target_out;
wire [1:0] if_id_delayed_PHT_out;
wire [2:0] if_id_delayed_BHR_out;
wire [1:0] if_id_btb_type_out;
wire if_id_btb_v_out;
//wire [31:0] pred_target;
wire [31:0] pc_out;
wire [31:0] pc_plus_4_out;
wire [31:0] inst_word_out;
//output of id
wire stall_pipeline_alu;
wire stall_pipeline_br;
wire [31:0] id_btb_target_out;
wire update_btb_target_out;
wire [1:0] id_btb_type_out;
wire update_BP_out;
wire pred_right_out;
wire taken;
wire [1:0] delayed_PHT_out;
wire [2:0] delayed_BHR_out;
wire recover_push;
wire [31:0] recover_push_addr;
wire recover_pop;
wire wb_regwrite;
wire wb_memtoreg;
//wire mem_branch;
wire mem_memread;
wire mem_memwrite;
wire [3:0] ex_aluop;
wire [1:0] ex_alusrc;
wire ex_regdst;
wire [31:0] regread1;
wire [31:0] regread2;
wire [4:0] if_id_regrs;
wire [4:0] if_id_regrd;
wire [4:0] if_id_regrt;
wire if_flush;
wire [1:0] pc_src;
wire ll_mem;
wire sc_mem;
wire [31:0] sign_extend;
//output of id_ex_reg
wire ex_wb_reg_write;
wire ex_wb_memtoreg;
wire ex_mem_memread;
wire ex_mem_memwrite;
wire ex_mem_ll_mem;
wire ex_mem_sc_mem;
wire ex_regdst_reg;
wire [1:0] ex_aluop_reg;
wire ex_alusrc_reg;
wire [31:0] ex_regread1;
wire [31:0] ex_regread2;
wire [31:0] ex_sign_extend;
wire [4:0] ex_reg_rs;
wire [4:0] ex_reg_rt;
wire [4:0] ex_reg_rd;
//output of ex
wire [31:0] alu_result;
wire [31:0] data_to_mem;
wire [4:0] ex_dest_rd;
wire zero;
//output of ex_mem
//wire mem_branch_reg;
wire mem_mem_read;
wire mem_mem_write;
wire mem_ll_mem;
wire mem_sc_mem;
wire mem_reg_write;
wire mem_memtoreg;
wire mem_alu_zero;
wire [31:0] mem_addr;
wire [31:0] mem_data;
wire [4:0] mem_dest_reg;
// output of mem_wb
wire wb_regwrite_reg;
wire wb_memtoreg_reg;
wire [31:0] wb_aluresult;
wire [31:0] wb_read_memdata;
wire [4:0] wb_dest_reg;
//input to pc
wire pc_go;
wire stall;
core_pc pc_dut(//input
.clk(clk),
.rst(rst),
.btb_target(btb_target_out),
.ras_target(ret_addr_out),
.pc_go(v_inst),
.stall(stall),
.good_target(id_btb_target_out),
.id_pc_src(update_btb_target_out),
.btb_v(en_btb_pred),
.btb_type(btb_type_out),
//output
.pc_out(pc),
.v_pc_out(v_pc),
.pc_plus4(pc_plus4)
);
core_btb btb_dut(//input
.clk(clk),
.rst(rst),
.pc(pc),
.update_btb_tag(update_btb_target_out),
.update_btb_target(update_btb_target_out),
.btb_target_in(id_btb_target_out),
.btb_type_in(id_btb_type_out),
.PHT_pred_taken(pred_out),
//output
.btb_type_out(btb_type_out),
.btb_target_out(btb_target_out),
.btb_v(btb_v),
.en_btb_pred(en_btb_pred) // only valid when both btb_v and PHT_pred_taken valid are vallid
);
core_pht pht_dut(//input
.clk(clk),
.rst(rst),
.if_pc(pc[10:5]), // pc[10:5]
.id_pc(pc_out[10:5]), // pc[10:5]
.update_BP(update_BP_out),
.pred_right(pred_right_out),
.taken(taken),
.BHR_in(delayed_BHR_out),
//delayed PHT_out from previous stage , useful to avoid reading PHT when update PHT
.delayed_PHT(delayed_PHT_out),
//output
.pred_out(pred_out),
.BHR_rd(BHR_rd),
.PHT_out(PHT_out)
);
core_ras ras_dut(
.clk(clk),
.rst(rst),
//inst fetch stage prediction
.en_call_in((btb_v&&(btb_type_out==jal_btb_type))), //in my previous version ,it equals en_ret_addr_in
.en_ret_in((btb_v&&(btb_type_out==jr_btb_type))),//in my previous version ,it equals en_ret_addr_out
.ret_addr_in(pc_plus4[31:2]),// which is gened by call inst
// decode stage recover something wrong,which caused by misprediction in btb, in RAS.
.recover_push(recover_push),//previous inst was preded as a JR inst incorrectly.
.recover_push_addr(recover_push_addr[31:2]),//push back the top return addr to RAs
.recover_pop(recover_pop),// previous inst was preded as a jal inst incorrectly.
////output
//inst fetch stage poping top addr
.ret_addr_out(ret_addr_out)
);
wire [31:0] pred_target;
assign pred_target=(btb_type_out==jr_btb_type)? ret_addr_out:btb_target_out;
core_if_id if_id_reg(//input
.clk(clk),
.rst(rst),
// stall,
.if_id_we(stall),
.if_flush(if_flush),
.pc_plus_4(pc_plus4),
.inst_word(inst),
//used for update Branch predictor
.pc(pc),
.pred_target(pred_target),
.delayed_PHT(PHT_out),
.delayed_BHR(BHR_rd),
.btb_type(btb_type_out),
.btb_v(btb_v),
//output
.pc_plus_4_out(pc_plus_4_out),
.inst_word_out(inst_word_out),
.pc_out(pc_out),
.pred_target_out(if_id_pred_target_out),
.delayed_PHT_out(if_id_delayed_PHT_out),
.delayed_BHR_out(if_id_delayed_BHR_out),
.btb_type_out(if_id_btb_type_out),
.btb_v_out(if_id_btb_v_out)
);
// from wb stage
wire [31:0] wb_mux_regdata;
core_id id_dut (//input
.clk(clk),
.rst(rst),
//btb banch predict
.btb_v(if_id_btb_v_out),
.btb_type(if_id_btb_type_out),
.pred_target(if_id_pred_target_out),
.delayed_PHT(if_id_delayed_PHT_out),
.delayed_BHR(if_id_delayed_BHR_out),
.if_id_inst_word(inst_word_out),
//hazard_detection_for_alu
.id_ex_memread(ex_mem_memread),
.id_ex_regrt(ex_reg_rt),
//branch target
.if_id_plus_4(pc_plus_4_out),
//hazard_detection_for_branch
.id_ex_wb_regwrite(ex_wb_reg_write),
.mem_mem_read(mem_mem_read),
.ex_dest_reg(ex_dest_rd),
.mem_dest_reg(mem_dest_reg),
//forwarding_unit_id
.ex_mem_regwrite(mem_reg_write),
.mem_wb_regwrite(wb_regwrite_reg),
.ex_mem_regrd(mem_dest_reg),
.mem_wb_regrd(wb_dest_reg),
.ex_mem_regdata(mem_addr),
.mem_wb_regdata(wb_mux_regdata),
//output
//output to if stage
.stall_pipeline_alu(stall_pipeline_alu),
.stall_pipeline_br(stall_pipeline_br),
.update_btb_target_out(update_btb_target_out),
.btb_target_out(id_btb_target_out),
.btb_type_out(id_btb_type_out),
.update_BP_out(update_BP_out),
.pred_right_out(pred_right_out),
.taken(taken),
.delayed_PHT_out(delayed_PHT_out),
.delayed_BHR_out(delayed_BHR_out),
.recover_push(recover_push),
.recover_push_addr(recover_push_addr),
.recover_pop(recover_pop),
//output to next stage
.wb_regwrite(wb_regwrite),
.wb_memtoreg(wb_memtoreg),
// .mem_branch(mem_branch),
.mem_memread(mem_memread),
.mem_memwrite(mem_memwrite),
// ex_reg_dest,
.ex_aluop(ex_aluop),
.ex_alusrc(ex_alusrc),
.ex_regdst(ex_regdst),
.regread1(regread1),
.regread2(regread2),
.reg_rs(if_id_regrs),
.reg_rt(if_id_regrt),
.reg_rd(if_id_regrd),
.if_flush(if_flush),
.pc_src(pc_src),
.ll_mem(ll_mem),
.sc_mem(sc_mem),
.sign_extend(sign_extend)
// .id_inst_lo(id_inst_lo)
);
assign stall=stall_pipeline_alu||stall_pipeline_br;
core_id_ex id_ex_reg_dut(//input
.clk(clk),
.rst(rst),
// .inst_lo(id_inst_lo),
.wb_reg_write(wb_regwrite),
.wb_memtoreg(wb_memtoreg),
.mem_memread(mem_memread),
.mem_memwrite(mem_memwrite),
.mem_ll_mem(ll_mem),
.mem_sc_mem(sc_mem),
.regdst(ex_regdst),
.aluop(ex_aluop),
.alusrc(ex_alusrc),
.regread1(regread1),
.regread2(regread2),
.sign_extend(sign_extend),
.reg_rs(if_id_regrs),
.reg_rt(if_id_regrt),
.reg_rd(if_id_regrd),
//output
// .ex_inst_lo(ex_inst_lo),
.ex_wb_reg_write(ex_wb_reg_write),
.ex_wb_memtoreg(ex_wb_memtoreg),
.ex_mem_memread(ex_mem_memread),
.ex_mem_memwrite(ex_mem_memwrite),
.ex_mem_ll_mem(ex_mem_ll_mem),
.ex_mem_sc_mem(ex_mem_sc_mem),
.ex_regdst(ex_regdst_reg),
.ex_aluop(ex_aluop_reg),
.ex_alusrc(ex_alusrc_reg),
.ex_regread1(ex_regread1),
.ex_regread2(ex_regread2),
.ex_sign_extend(ex_sign_extend),
.ex_reg_rs(ex_reg_rs),
.ex_reg_rt(ex_reg_rt),
.ex_reg_rd(ex_reg_rd)
);
core_ex ex_dut (//input
.alusrc_a(ex_regread1),
.alusrc_b(ex_regread2),
.aluop(ex_aluop),
// .inst_lo(ex_inst_lo),
.regdst(ex_regdst),
.alusrc(ex_alusrc),
.id_ex_rs(ex_reg_rs),
.id_ex_rt(ex_reg_rt),
.id_ex_rd(ex_reg_rd),
.mem_regwrite(mem_reg_write),
.wb_regwrite(wb_regwrite_reg),
.mem_regrd(mem_dest_reg),
.wb_regrd(wb_dest_reg),
.mem_reg_data(mem_addr),
.wb_reg_data(wb_aluresult),
.id_ex_sign_extend(ex_sign_extend),
//output
.alu_result(alu_result),
.data_to_mem(data_to_mem),
.ex_dest_rd(ex_dest_rd),
.zero(zero)
);
core_ex_mem ex_mem_reg_dut(//input
.clk(clk),
.rst(rst),
// .branch(branch),
.mem_read(ex_mem_memread),
.mem_write(ex_mem_memwrite),
.ll_mem(ex_mem_ll_mem),
.sc_mem(ex_mem_sc_mem),
.reg_write(ex_wb_reg_write),
.memtoreg(ex_wb_memtoreg),
.alu_zero(zero),
.alu_result(alu_result),
.reg_read2(data_to_mem),
.dest_reg(ex_dest_rd),
//output
// .mem_branch(mem_branch),
.mem_mem_read(mem_mem_read),
.mem_mem_write(mem_mem_write),
.mem_ll_mem(mem_ll_mem),
.mem_sc_mem(mem_sc_mem),
.mem_reg_write(mem_reg_write),
.mem_memtoreg(mem_memtoreg),
.mem_alu_zero(mem_alu_zero),
.mem_alu_result(mem_addr),
.mem_reg_read2(mem_data),
.mem_dest_reg(mem_dest_reg)
);
assign mem_head[3]=mem_mem_write?1'b1:1'b0;
assign mem_head[2]=mem_mem_read||mem_mem_write;
assign mem_head[1:0]={!mem_ll_mem,!mem_sc_mem};
assign v_mem=mem_mem_read||mem_mem_write; // a waste of logic ,but it's necessary for data cache
core_mem_wb mem_wb_dut(//input
.clk(clk),
.rst(rst),
.regwrite(mem_reg_write),
.memtoreg(mem_memtoreg),
.aluresult(mem_addr),
.read_memdata(data),
.valid_read_memdata(v_data),
.dest_reg(mem_dest_reg),
//output
.wb_regwrite(wb_regwrite_reg),
.wb_memtoreg(wb_memtoreg_reg),
.wb_aluresult(wb_aluresult),
.wb_read_memdata(wb_read_memdata),
.wb_dest_reg(wb_dest_reg)
);
assign wb_mux_regdata=wb_memtoreg?wb_read_memdata:wb_aluresult;
endmodule
|
/// date:2016/3/4
/// engineer: ZhaiShaoMin
/// module function : just combine memory_fsm and memory_state_data_ram
module memory (//input
clk,
rst,
//fsm state of rep paralle-serial port corresponding to mem
m_rep_fsm_state,
//fsm state of req paralle-serial port corresponding to mem
m_req_fsm_state,
// fsm state of req paralle-serial port corresponding to data cache
d_fsm_state,
// input from local d cache
v_d_req,
v_d_rep,
local_d_head_in,
local_d_addr_in,
local_d_data_in,
// input from local i cache
v_i_rep,
// local_i_head, // no need for local i cache miss
local_i_addr_in,
// input form INfifos
v_INfifos,
infifos_head_in,
infifos_addr_in,
infifos_data_in,
// output to local d cache
v_req_d,
v_rep_d,
head_out_local_d,
addr_out_local_d,
data_out_local_d,
// output to local i cahce
v_rep_i,
data_out_local_i,
// output to OUT req fifo
en_inv_ids,
inv_ids_in,
flit_max_req,
en_flit_max_req,
v_req_out,
head_out_req_out,
addr_out_req_out,
// data_out_req_out,
// output to OUT rep fifo
flit_max_rep,
en_flit_max_rep,
v_rep_out,
head_out_rep_out,
addr_out_rep_out,
data_out_rep_out,
mem_access_done
);
// input
input clk;
input rst;
//fsm state of rep paralle-serial port corresponding to mem
input [1:0] m_rep_fsm_state;
//fsm state of req paralle-serial port corresponding to mem
input [1:0] m_req_fsm_state;
// fsm state of req paralle-serial port corresponding to data cache
input [1:0] d_fsm_state;
// input from local d cache
input v_d_req;
input v_d_rep;
input [15:0] local_d_head_in;
input [31:0] local_d_addr_in;
input [127:0] local_d_data_in;
// input from local i cache
input v_i_rep;
// local_i_head, // no need for local i cache miss
input [31:0] local_i_addr_in;
// input form INfifos
input v_INfifos;
input [15:0] infifos_head_in;
input [31:0] infifos_addr_in;
input [127:0] infifos_data_in;
// output
// output to local d cache
output v_req_d;
output v_rep_d;
output [15:0] head_out_local_d;
output [31:0] addr_out_local_d;
output [127:0] data_out_local_d;
// output to local i cahce
output v_rep_i;
output [127:0] data_out_local_i;
// output to OUT req fifo
output en_inv_ids;
output [3:0] inv_ids_in;
output [1:0] flit_max_req;
output en_flit_max_req;
output v_req_out;
output [15:0] head_out_req_out;
output [31:0] addr_out_req_out;
//output [127:0] data_out_req_out;
// output to OUT rep fifo
output [3:0] flit_max_rep;
output en_flit_max_rep;
output v_rep_out;
output [15:0] head_out_rep_out;
output [31:0] addr_out_rep_out;
output [127:0] data_out_rep_out;
output mem_access_done;
wire state_we_net;
wire state_re_net;
wire data_we_net;
wire data_re_net;
wire [31:0] addr_net;
wire [127:0] data_in_net;
wire [127:0] data_out_net;
wire [5:0] state_in_net;
wire [5:0] state_out_net;
memory_state_data_ram mem_ram(// input
.clk(clk),
.state_we_in(state_we_net),
.state_re_in(state_re_net),
.addr_in(addr_net),
.state_in(state_in_net),
.data_we_in(data_we_net),
.data_re_in(data_re_net),
.data_in(data_in_net),
// output
.state_out(state_out_net),
.data_out(data_out_net));
memory_fsm mem_fsm(// global signals
.clk(clk),
.rst(rst),
//fsm state of rep paralle-serial port corresponding to mem
.m_rep_fsm_state(m_rep_fsm_state),
//fsm state of req paralle-serial port corresponding to mem
.m_req_fsm_state(m_req_fsm_state),
// fsm state of req paralle-serial port corresponding to data cache
.d_fsm_state(d_fsm_state),
// input from mem_ram
.mem_state_out(state_out_net),
.mem_data_in(data_out_net),
// input from local d cache
.v_d_req(v_d_req),
.v_d_rep(v_d_rep),
.local_d_head_in(local_d_head_in),
.local_d_addr_in(local_d_addr_in),
.local_d_data_in(local_d_data_in),
// input from local i cache
.v_i_rep(v_i_rep),
// local_i_head, // no need for local i cache miss
.local_i_addr_in(),
// input form INfifos
.v_INfifos(v_INfifos),
.infifos_head_in(infifos_head_in),
.infifos_addr_in(infifos_addr_in),
.infifos_data_in(infifos_data_in),
//output to mem_ram
.data_out_mem_ram(data_in_net),
.state_out_mem_ram(state_in_net),
.addr_out_mem_ram(addr_net),
.state_we_out(state_we_net),
.state_re_out(state_re_net),
.data_we_out(data_we_net),
.data_re_out(data_re_net),
// output to local d cache
.v_req_d(v_req_d),
.v_rep_d(v_rep_d),
.head_out_local_d(head_out_local_d),
.addr_out_local_d(addr_out_local_d),
.data_out_local_d(data_out_local_d),
// output to local i cahce
.v_rep_Icache(v_rep_i),
.data_out_local_i(data_out_local_i),
// output to OUT req fifo
.en_inv_ids(en_inv_ids),
.inv_ids_in(inv_ids_in),
.flit_max_req(flit_max_req),
.en_flit_max_req(en_flit_max_req),
.v_req_out(v_req_out),
.head_out_req_out(head_out_req_out),
.addr_out_req_out(addr_out_req_out),
//.data_out_req_out(data_out_req_out),
// output to OUT rep fifo
.flit_max_rep(flit_max_rep),
.en_flit_max_rep(en_flit_max_rep),
.v_rep_out(v_rep_out),
.head_out_rep_out(head_out_rep_out),
.addr_out_rep_out(addr_out_rep_out),
.data_out_rep_out(data_out_rep_out),
.mem_access_done(mem_access_done)
);
endmodule
|
//date:2016/3/12
//engineer:ZhaiShaoMin
//module name:inst decode stage of core
//module function:including all issues excuted necessarily in id stage
// they are hazard_detection_for_alu ,hazard_detection_for_branch,
// decoder,regfile,br_addr_adder ect.
module core_id(//input
clk,
rst,
//btb banch predict
btb_v,
btb_type,
pred_target,
delayed_PHT,
delayed_BHR,
if_id_inst_word,
//h_d_f_alu
id_ex_memread,
id_ex_regrt,
//branch target
if_id_plus_4,
//h_d_f_br
id_ex_wb_regwrite,
mem_mem_read,
ex_dest_reg,
mem_dest_reg,
//frowarding_unit_id
ex_mem_regwrite,
mem_wb_regwrite,
ex_mem_regrd,
mem_wb_regrd,
ex_mem_regdata,
mem_wb_regdata,
///////////////output
// output to if stage
stall_pipeline_alu,
stall_pipeline_br,
update_btb_target_out,
btb_target_out,
btb_type_out,
update_BP_out,
pred_right_out,
taken,
delayed_PHT_out,
delayed_BHR_out,
recover_push,
recover_push_addr,
recover_pop,
//output to next stage
wb_regwrite,
wb_memtoreg,
// mem_branch,
mem_memread,
mem_memwrite,
ex_aluop,
ex_alusrc,
ex_regdst,
regread1,
regread2,
reg_rs,
reg_rt,
reg_rd,
if_flush,
pc_src,
ll_mem,
sc_mem,
sign_extend
// id_inst_lo
);
//parameter
parameter R_type=6'b000000;
parameter lw_type=6'b100011;
parameter sw_type=6'b101011;
parameter beq_type=6'b000100;
parameter jump_type=6'b000010;
parameter ll_type=6'b110000;
parameter sc_type=6'b111000;
parameter bne_type=6'b000101;
parameter blez_type=6'b000110;
parameter bgtz_type=6'b000111;
parameter bltz_type=6'b000001;
parameter bgez_type=6'b000001;
parameter jal_type=6'b000011;
parameter addiu_type=6'b001001;
parameter slti_type=6'b001010;
parameter sltiu_type=6'b001011;
parameter andi_type=6'b001100;
parameter ori_type=6'b001101;
parameter xori_type=6'b001110;
parameter lui_type=6'b001111;
// parameter
parameter br_btb_type=2'b00;
parameter j_btb_type=2'b01;
parameter jal_btb_type=2'b10;
parameter jr_btb_type=2'b11;
//input
input clk;
input rst;
input btb_v;
input [1:0] btb_type;
input [31:0] pred_target;
input [1:0] delayed_PHT;
input [2:0] delayed_BHR;
input [31:0] if_id_inst_word;
//h_d_f_alu
input id_ex_memread;
input [4:0] id_ex_regrt;
//branch target
input [31:0] if_id_plus_4;
//h_d_f_br
input id_ex_wb_regwrite;
input mem_mem_read;
input [4:0] ex_dest_reg;
input [4:0] mem_dest_reg;
//mem forwarding
input ex_mem_regwrite;
input [4:0] ex_mem_regrd;
input [31:0] ex_mem_regdata;
//wb forwarding
input mem_wb_regwrite;
input [4:0] mem_wb_regrd;
input [31:0] mem_wb_regdata;
//output
output stall_pipeline_alu;
output stall_pipeline_br;
output [31:0] btb_target_out;
output update_btb_target_out;
output [1:0] btb_type_out;
output update_BP_out;
output pred_right_out;
output taken;
output [1:0] delayed_PHT_out;
output [2:0] delayed_BHR_out;
output recover_push;
output [31:0] recover_push_addr;
output recover_pop;
output wb_regwrite;
output wb_memtoreg;
//output mem_branch;
output mem_memread;
output mem_memwrite;
output [3:0] ex_aluop;
output [1:0] ex_alusrc;
output ex_regdst;
output [31:0] regread1;
output [31:0] regread2;
output [4:0] reg_rs;
output [4:0] reg_rd;
output [4:0] reg_rt;
output if_flush;
output [1:0] pc_src;
output ll_mem;
output sc_mem;
output [31:0] sign_extend;
//output [15:0] id_inst_lo;
wire blez_taken;
wire bgtz_taken;
wire bltz_taken;
wire bgez_taken;
wire src1_eq_src2;
wire br_taken;
assign br_taken=blez_taken||bgtz_taken||bltz_taken||bgez_taken;
// froword delayed PHT and delayed BHR to if stage
assign delayed_BHR_out=delayed_BHR;
assign delayed_PHT_out=delayed_PHT;
//hazard detection for alu
assign stall_pipeline_alu=(id_ex_memread&&(id_ex_regrt==if_id_inst_word[25:21])||(id_ex_regrt==if_id_inst_word[20:16]))?1'b1:1'b0;
//hazard detection for branch target
assign stall_pipeline_br=( (id_ex_wb_regwrite&&( (ex_dest_reg==if_id_inst_word[25:21]) || (ex_dest_reg==if_id_inst_word[20:16]) ) ) ||
(mem_mem_read&&((mem_dest_reg==if_id_inst_word[25:21])||(mem_dest_reg==if_id_inst_word[20:16]))) )?1'b1:1'b0;
//sign-extend
wire [31:0] sign_extend;
wire [15:0] temp_sign;
assign temp_sign=if_id_inst_word[15]?16'hffff:16'h0000;
assign sign_extend={temp_sign,if_id_inst_word[15:0]};
//shift_left_2
wire [31:0] shift_left_2;
wire [31:0] br_target;
wire [31:0] j_target;
wire [31:0] jal_target;
wire [31:0] jr_target;
assign shift_left_2={sign_extend[31],sign_extend[28:0],2'b00};
//branch target
assign br_target=if_id_plus_4+shift_left_2;
assign j_target={if_id_plus_4[31:28],if_id_inst_word[25:0],2'b00};
assign jal_target={if_id_plus_4[31:28],if_id_inst_word[25:0],2'b00};
assign jr_target=regread1;
// inst_fun
//assign id_inst_lo=if_id_inst_word[15:0];
reg ex_regdst;
reg jump;
reg branch;
reg memread;
reg memtoreg;
reg [3:0] ex_aluop;
reg memwrite;
reg [1:0] ex_alusrc;
reg regwrite;
reg ll_mem;
reg sc_mem;
reg jal;
reg jr;
//reg jalr;
assign wb_memtoreg=memtoreg;
assign wb_regwrite=regwrite;
assign mem_memread=memread;
assign mem_memwrite=memwrite;
assign reg_rs=if_id_inst_word[25:21];
assign reg_rt=if_id_inst_word[20:16];
assign reg_rd=if_id_inst_word[15:11];
//decode block
always@(*)
begin
//default value
ex_regdst=1'b0;
jump=1'b0;
branch=1'b0;
memread=1'b0;
memtoreg=1'b0;
ex_aluop=4'b0000;
memwrite=1'b0;
ex_alusrc=2'b00;
regwrite=1'b0;
ll_mem=1'b0;
sc_mem=1'b0;
jal=1'b0;
jr=1'b0;
// jalr=1'b0;
case(if_id_inst_word[31:26])
R_type:
begin
if(if_id_inst_word[5:0]==6'b001000)
begin
jr=1'b1;
end
// else if(if_id_inst_word[5:0]==6'b001001)
// begin
// jalr=1'b1;
// end
ex_regdst=1'b1;
regwrite=1'b1;
ex_aluop=4'b0010;
end
lw_type:
begin
ex_alusrc=2'b01;
memtoreg=1'b1;
regwrite=1'b1;
memread=1'b1;
end
ll_type:
begin
ex_alusrc=2'b01;
memtoreg=1'b1;
regwrite=1'b1;
memread=1'b1;
ll_mem=1'b1;
end
sw_type:
begin
ex_alusrc=2'b01;
memwrite=1'b1;
end
sc_type:
begin
ex_alusrc=2'b01;
memwrite=1'b1;
sc_mem=1'b1;
end
//branch_type
beq_type:
begin
branch=1'b1;
ex_alusrc=2'b01;
ex_aluop=4'b0001;
end
bne_type:
begin
branch=1'b1;
ex_alusrc=2'b01;
ex_aluop=4'b1110;
end
blez_type:
begin
branch=1'b1;
ex_alusrc=2'b01;
ex_aluop=4'b1010;
end
bgtz_type:
begin
branch=1'b1;
ex_alusrc=2'b01;
ex_aluop=4'b1011;
end
bltz_type:
\t begin
\t //bltz
\t if(if_id_inst_word[20:16]==5'b00000)
begin
branch=1'b1;
ex_alusrc=2'b01;
ex_aluop=4'b1100;
end
// bgez if_id_inst_word[20:16]==5'b00001
\t else
begin
branch=1'b1;
ex_alusrc=2'b01;
ex_aluop=4'b1101;
end
\t end
//j_type
jump_type:
begin
jump=1'b1;
ex_aluop=4'b1001;
end
jal_type:
begin
jal=1'b1;
ex_aluop=4'b1001;
end
///I-type
addiu_type:
begin
ex_aluop=4'b0000;
ex_alusrc=2'b01;
regwrite=1'b1;
end
slti_type:
begin
ex_aluop=4'b0011;
ex_alusrc=2'b01;
regwrite=1'b1;
end
sltiu_type:
begin
ex_aluop=4'b0100;
ex_alusrc=2'b01;
regwrite=1'b1;
end
andi_type:
begin
ex_aluop=4'b0101;
ex_alusrc=2'b10;
regwrite=1'b1;
end
ori_type:
begin
ex_aluop=4'b0110;
ex_alusrc=2'b10;
regwrite=1'b1;
end
xori_type:
begin
ex_aluop=4'b0111;
ex_alusrc=2'b10;
regwrite=1'b1;
end
lui_type:
begin
ex_aluop=4'b1000;
regwrite=1'b1;
end
//
endcase
end
//forwarding_unit_id
reg [1:0] forward_a;
reg [1:0] forward_b;
always@(*)
begin
//forward_a
if(mem_wb_regwrite&&(mem_wb_regrd!=5'b00000)&& !(ex_mem_regwrite&&(ex_mem_regrd!=5'b00000)&&(ex_mem_regrd!=reg_rs)) &&(mem_wb_regrd==reg_rs))
forward_a=2'b01;
else if(ex_mem_regwrite&&(ex_mem_regrd!=5'b00000)&&(ex_mem_regrd==reg_rs))
forward_a=2'b10;
else
forward_a=2'b00;
//fotward_b
if(mem_wb_regwrite&&(mem_wb_regrd!=5'b00000)&& !(ex_mem_regwrite&&(ex_mem_regrd!=5'b00000)&&(ex_mem_regrd!=reg_rt)) &&(mem_wb_regrd==reg_rt))
forward_b=2'b01;
else if(ex_mem_regwrite&&(ex_mem_regrd!=5'b00000)&&(ex_mem_regrd==reg_rt))
forward_b=2'b10;
else
forward_b=2'b00;
end
// regfile
core_id_regfile regfile(//input
.clk(clk),
.rst(rst),
.raddr1(if_id_inst_word[25:21]),
.raddr2(if_id_inst_word[20:16]),
.rf_write(mem_wb_regwrite),
.waddr(mem_wb_regrd),
.data(mem_wb_regdata),
//output
.rd_data1(regread1),
.rd_data2(regread2)
);
//beq compare src
reg [31:0] cmp_src1;
reg [31:0] cmp_src2;
always@(*)
begin
case(forward_a)
2'b00:cmp_src1=regread1;
2'b01:cmp_src1=mem_wb_regdata;
2'b10:cmp_src1=ex_mem_regdata;
default:cmp_src1=regread1;
endcase
end
always@(*)
begin
case(forward_b)
2'b00:cmp_src2=regread2;
2'b01:cmp_src2=mem_wb_regdata;
2'b10:cmp_src2=ex_mem_regdata;
default:cmp_src2=regread2;
endcase
end
//function for generating update infos to btb ,pht and ras of if stage
wire jr_valid;
assign jr_valid=(!(id_ex_memread&&id_ex_regrt==reg_rs))&&(!(mem_mem_read&&mem_dest_reg==reg_rs))?1'b1:1'b0;
reg update_btb_target_out;
reg [31:0] btb_target_out;
reg [1:0] btb_type_out;
reg update_BP_out;
reg pred_right_out;
reg taken;
always@(*)
begin
//default values
taken=1'b0;
update_btb_target_out=1'b0;
btb_target_out=br_target;
btb_type_out=br_btb_type;
update_BP_out=1'b0;
pred_right_out=1'b0;
//when decode find the inst is a jr
if(jr&&jr_valid&&(btb_type==jr_btb_type&&pred_target!=jr_target&&btb_v||btb_type!=jr_btb_type||btb_v==1'b0))
begin
update_btb_target_out=1'b1;
btb_target_out=jr_target;
btb_type_out=jr_btb_type;
update_BP_out=1'b1;
taken=1'b1;
if(delayed_PHT[1]==1'b1)
pred_right_out=1'b1;
else
pred_right_out=1'b0;
end
//when decode find the inst is a j
else if(jump&&(btb_type==j_btb_type&&pred_target!=j_target&&btb_v||btb_type!=j_btb_type||btb_v==1'b0))
begin
update_btb_target_out=1'b1;
btb_target_out=j_target;
btb_type_out=j_btb_type;
update_BP_out=1'b1;
taken=1'b1;
if(delayed_PHT[1]==1'b1)
pred_right_out=1'b1;
else
pred_right_out=1'b0;
end
//when decode find the inst is a jal
else if(jal&&(btb_type==jal_btb_type&&pred_target!=jal_target&&btb_v||btb_type!=jal_btb_type||btb_v==1'b0))
begin
update_btb_target_out=1'b1;
btb_target_out=jal_target;
btb_type_out=jal_btb_type;
update_BP_out=1'b1;
taken=1'b1;
if(delayed_PHT[1]==1'b1)
pred_right_out=1'b1;
else
pred_right_out=1'b0;
end
//when decode find the inst is a br
else if(br_taken&&(btb_type==br_btb_type&&pred_target!=br_target&&btb_v||btb_type!=br_btb_type||btb_v==1'b0))
begin
update_btb_target_out=1'b1;
btb_target_out=br_target;
btb_type_out=br_btb_type;
update_BP_out=1'b1;
taken=1'b1;
if(delayed_PHT[1]==1'b1)
pred_right_out=1'b1;
else
pred_right_out=1'b0;
end
//when decode find the inst is not a branch or jump
else if(!jump&&btb_type!=j_btb_type||!jal&&btb_type!=jal_btb_type
||!jr&&btb_type!=jr_btb_type||!branch&&btb_type!=br_btb_type)
begin
update_BP_out=1'b1;
pred_right_out=1'b0;
end
end
// function of recovering something wrong happened in RAS
reg recover_push;
reg [31:0] recover_push_addr;
reg recover_pop;
always@(*)
begin
//defalut values
recover_pop=1'b0;
recover_push=1'b0;
recover_push_addr=pred_target;
if(!jal&&btb_type==jal_btb_type&&btb_v)
begin
recover_pop=1'b1;
end
else if(!jr&&btb_type==jr_btb_type&&btb_v)
begin
recover_push=1'b1;
recover_push_addr=pred_target;
end
end
assign blez_taken=(branch&&(cmp_src1<=32'h00000000)&&(ex_aluop==4'b1010));
assign bgtz_taken=(branch&&(cmp_src1>32'h00000000)&&(ex_aluop==4'b1011));
assign bltz_taken=(branch&&(cmp_src1<32'h00000000)&&(ex_aluop==4'b1100));
assign bgez_taken=(branch&&(cmp_src1>=32'h00000000)&&(ex_aluop==4'b1101));
assign src1_eq_src2=cmp_src1==cmp_src2?1'b1:1'b0;
assign pc_src=(src1_eq_src2&&branch==1'b1)?2'b01:jump?2'b10:2'b00;
assign if_flush=|pc_src;
endmodule
|
//A Small MIPSv2 Instruction Set
// LW rt, offset(rs)
// SW rt, offset(rs)
//I-Type Computational Instructions
// ADDIU rt, rs, signed-imm.
// SLTI rt, rs, signed-imm.
// SLTIU rt, rs, signed-imm.
// ANDI rt, rs, zero-ext-imm.
// ORI rt, rs, zero-ext-imm.
// XORI rt, rs, zero-ext-imm.
// LUI rt, zero-ext-imm.
//R-Type Computational Instructions
// SLL rd, rt, shamt
// SRL rd, rt, shamt
// SRA rd, rt, shamt
// SLLV rd, rt, rs
// SRLV rd, rt, rs
// SRAV rd, rt, rs
// ADDU rd, rs, rt
// SUBU rd, rs, rt
// AND rd, rs, rt
// OR rd, rs, rt
// XOR rd, rs, rt
// NOR rd, rs, rt
// SLT rd, rs, rt
// SLTU rd, rs, rt
//Jump and Branch Instructions
// J target
// JAL target
// JR rs
// JALR rd, rs
// BEQ rs, rt, offset
// BNE rs, rt, offset
// BLEZ rs, offset
// BGTZ rs, offset
// BLTZ rs, offset
// BGEZ rs, offset
//System Coprocessor (COP0) Instructions
// MFC0 rt, rd
// MTC0 rt, rd
|
// date:2016/3/11
// engineer:ZhaiShaoMin
// module name program counter module
module core_pc(//input
clk,
rst,
btb_target,
ras_target,
pc_go,
stall,
// from id module
good_target, // target from decode stage, correct target
id_pc_src, // if 1 ,meaning pc scoure is from decode ,0,otherwise
// from BTB module
btb_v,
btb_type,
//output
pc_out,
v_pc_out,
pc_plus4
);
//parameter
parameter initial_addr=32'h00040000;
// para used in btb
parameter br_type=2'b00;
parameter j_type=2'b01;
parameter jal_type=2'b10;
parameter jr_type=2'b11;
//input
input clk;
input rst;
input [31:0] btb_target;
input [31:0] ras_target;
input id_pc_src;
input stall;
input pc_go;
input [31:0] good_target;
input [1:0] btb_type;
input btb_v;
//output
output [31:0] pc_out;
output v_pc_out;
output [31:0] pc_plus4;
//figure out pc src sel
wire [1:0] pc_src;
wire [1:0] pc_src1;
assign pc_src1=(btb_v&&(btb_type==br_type||btb_type==j_type||btb_type==jal_type))?2'b11:(btb_v&&btb_type==jr_type)?2'b10:2'b01;
assign pc_src=(id_pc_src==1'b1)?2'b00:pc_src1;
reg [31:0] pc_temp;
always@(*)
begin
case(pc_src)
\t2'b00:pc_temp=good_target;
\t2'b01:pc_temp=pc_plus4;
\t2'b10:pc_temp=ras_target;
\t2'b11:pc_temp=btb_target;
\tdefault:pc_temp=pc_plus4;
\tendcase
end
//reg
reg [31:0] pc;
always@(posedge clk)
begin
if(rst)
pc<=32'h00040000;
else if(pc_go&&!stall)
begin
pc<=pc_temp;
end
end
assign pc_plus4=pc+4;
assign v_pc_out=(pc_go&&!stall);//?1'b0:1'b1;
assign pc_out=pc;
endmodule
|
/// date:2016/3/5 3/6 am: 10:57 done!
/// engineer:ZhaiShaoMIn
/// module function:because there are three kinds of uploadregs to
/// OUT_req: inst_cache ,data_cache and memory, so we need to determine which can be writed into OUT_req.
module arbiter_for_OUT_req(//input
clk,
rst,
OUT_req_rdy,
v_ic_req,
v_dc_req,
v_mem_req,
ic_req_ctrl,
dc_req_ctrl,
mem_req_ctrl,
//output
ack_OUT_req,
ack_ic_req,
ack_dc_req,
ack_mem_req,
select
);
//input
input clk;
input rst;
input OUT_req_rdy;
input v_ic_req;
input v_dc_req;
input v_mem_req;
input [1:0] ic_req_ctrl;
input [1:0] dc_req_ctrl;
input [1:0] mem_req_ctrl;
//output
output ack_OUT_req;
output ack_ic_req;
output ack_dc_req;
output ack_mem_req;
output [2:0] select; // select 1/3
/// parameter for fsm state
parameter arbiter_idle=4'b0001;
parameter ic_uploading=4'b0010;
parameter dc_uploading=4'b0100;
parameter mem_uploading=4'b1000;
reg [3:0] nstate;
reg [3:0] state;
reg [1:0] priority_2;
reg ack_ic_req;
reg ack_dc_req;
reg ack_mem_req;
reg [2:0] select;
reg ack_OUT_req;
reg update_priority;
wire [2:0] arbiter_vector;
assign arbiter_vector={v_ic_req,v_dc_req,v_mem_req};
// next state and output function
always@(*)
begin
ack_ic_req=1'b0;
ack_dc_req=1'b0;
ack_mem_req=1'b0;
select=3'b000;
ack_OUT_req=1'b0;
nstate=state;
update_priority=1'b0;
case(state)
arbiter_idle:
begin
if(OUT_req_rdy)
begin
if(arbiter_vector[2]==1'b1)
begin
ack_ic_req=1'b1;
select=3'b100;
nstate=ic_uploading;
ack_OUT_req=1'b1;
end
else
begin
if(arbiter_vector[1:0]==2'b11)
begin
update_priority=1'b1;
begin
if(priority_2[1]==1'b1)
begin
ack_dc_req=1'b1;
select=3'b010;
nstate=dc_uploading;
ack_OUT_req=1'b1;
end
else
begin
ack_mem_req=1'b1;
select=3'b001;
nstate=mem_uploading;
ack_OUT_req=1'b1;
end
end
end
else if(arbiter_vector[1:0]==2'b10)
begin
ack_dc_req=1'b1;
select=3'b010;
nstate=dc_uploading;
ack_OUT_req=1'b1;
end
else if(arbiter_vector[1:0]==2'b01)
begin
ack_mem_req=1'b1;
select=3'b001;
nstate=mem_uploading;
ack_OUT_req=1'b1;
end
end
end
end
ic_uploading:
begin
if(OUT_req_rdy)
begin
if(ic_req_ctrl==2'b11)
nstate=arbiter_idle;
ack_ic_req=1'b1;
select=3'b100;
ack_OUT_req=1'b1;
end
end
dc_uploading:
begin
if(OUT_req_rdy)
begin
if(dc_req_ctrl==2'b11)
nstate=arbiter_idle;
ack_dc_req=1'b1;
select=3'b010;
ack_OUT_req=1'b1;
end
end
mem_uploading:
begin
if(OUT_req_rdy)
begin
if(mem_req_ctrl==2'b11)
nstate=arbiter_idle;
ack_mem_req=1'b1;
select=3'b001;
ack_OUT_req=1'b1;
end
end
endcase
end
/// fsm reg
always@(posedge clk)
begin
if(rst)
state<=4'b0001;
else
state<=nstate;
end
// reg for priority_2
always@(posedge clk)
begin
if(rst)
priority_2<=2'b01;
else if(update_priority)
priority_2<={priority_2[0],priority_2[1]};
end
endmodule
|
// date:2016/8/10
// engineer:ZhaiShaoMin
// module name:tb_arbiter_4_enq
// module func: find out the bugs and prove that this part canworks well;
// module function:decide which fifo should receive coming flit according to the head flit of msg
// since arbiter dequeue has done most of the selction work , this part seems much easier!
`timescale 1ns/1ps
module tb_arbiter_4_enq();
//INPUT
reg [15:0] flit;
reg [1:0] ctrl;
reg en_dest_fifo; // enable selection between 4 fifos
reg [1:0] dest_fifo;// used to decide write flit to pass fifos or In_local fifos
// 00:write to pass req fifo; 01:write to pass rep fifo;
// 10:write to IN_local req fifo; 11:write to IN_local rep fifo;
//output
//output [1:0] enq_select; // 00:enq for pass fifo req;
// 01:enq for pass fifo rep; 10:enq for local fifo req;
// 11:enq for local fifo rep.
wire [15:0] flit2pass_req; // seled flit output to pass req
wire [1:0] ctrl2pass_req; // seled ctrl output to pass req
wire [15:0] flit2pass_rep; // seled flit output to pass req
wire [1:0] ctrl2pass_rep; // seled ctrl output to pass req
wire [15:0] flit2local_in_req; // seled flit output to pass req
wire [1:0] ctrl2local_in_req; // seled ctrl output to pass req
wire [15:0] flit2local_in_rep; // seled flit output to pass req
wire [1:0] ctrl2local_in_rep; // seled ctrl output to pass req
wire en_pass_req; // enable for pass req fifo to write data to tail
wire en_pass_rep; // enable for pass rep fifo to write data to tail
wire en_local_in_req; // enable for local in req fifo to write data to tail
wire en_local_in_rep; // enable for local in rep fifo to write data to tail
arbiter_4_enq duv( // input
.flit(flit),
.ctrl(ctrl),
.en_dest_fifo(en_dest_fifo),
.dest_fifo(dest_fifo),
// output
.flit2pass_req(flit2pass_req), // seled flit output to pass req
.ctrl2pass_req(ctrl2pass_req), // seled ctrl output to pass req
.flit2pass_rep(flit2pass_rep), // seled flit output to pass rep
.ctrl2pass_rep(ctrl2pass_rep), // seled ctrl output to pass rep
.flit2local_in_req(flit2local_in_req), // seled flit output to local in req
.ctrl2local_in_req(ctrl2local_in_req), // seled ctrl output to local in req
.flit2local_in_rep(flit2local_in_rep), // seled flit output to local in rep
.ctrl2local_in_rep(ctrl2local_in_rep), // seled ctrl output to local in rep
.en_pass_req(en_pass_req),
.en_pass_rep(en_pass_rep),
.en_local_in_req(en_local_in_req),
.en_local_in_rep(en_local_in_rep)
);
initial begin
flit = 16'h0000;
ctrl = 2'b00;
en_dest_fifo = 1'b0;
dest_fifo = 2'b00;
end
`define clk_step #10;
///////////////////////////////////////////begin test/////////////////////////////////////////
initial begin
`clk_step
flit = 16'h0001;
ctrl = 2'b01;
en_dest_fifo = 1'b0;
dest_fifo = 2'b00;
`clk_step
flit = 16'h0001;
ctrl = 2'b01;
en_dest_fifo = 1'b1;
dest_fifo = 2'b00;
`clk_step
flit = 16'h0002;
ctrl = 2'b01;
en_dest_fifo = 1'b1;
dest_fifo = 2'b01;
`clk_step
flit = 16'h0003;
ctrl = 2'b01;
en_dest_fifo = 1'b1;
dest_fifo = 2'b10;
`clk_step
flit = 16'h0004;
ctrl = 2'b01;
en_dest_fifo = 1'b1;
dest_fifo = 2'b11;
`clk_step
flit = 16'h1234;
ctrl = 2'b01;
en_dest_fifo = 1'b1;
dest_fifo = 2'b10;
`clk_step
flit = 16'h4321;
ctrl = 2'b01;
en_dest_fifo = 1'b1;
dest_fifo = 2'b01;
`clk_step
$stop;
end
endmodule
|
/// date:2016/3/9
/// engineer: ZhaiShaoMin
module dc_req_upload(//input
clk,
rst,
dc_flits_req,
v_dc_flits_req,
req_fifo_rdy,
//output
dc_flit_out,
v_dc_flit_out,
\t\t\t\t\t\t\t\t dc_ctrl_out,
dc_req_upload_state
);
//input
input clk;
input rst;
input [47:0] dc_flits_req;
input v_dc_flits_req;
input req_fifo_rdy;
//output
output [15:0] dc_flit_out;
output v_dc_flit_out;
output [1:0] dc_ctrl_out;
output dc_req_upload_state;
//parameter
parameter dc_req_upload_idle=1'b0;
parameter dc_req_upload_busy=1'b1;
//reg dc_req_nstate;
reg dc_req_state;
reg [47:0] dc_req_flits;
reg [1:0] sel_cnt;
reg v_dc_flit_out;
reg fsm_rst;
reg next;
reg en_flits_in;
reg inc_cnt;
assign dc_req_upload_state=dc_req_state;
always@(*)
begin
//default value
// dc_req_nstate=dc_req_state;
v_dc_flit_out=1'b0;
inc_cnt=1'b0;
fsm_rst=1'b0;
en_flits_in=1'b0;
next=1'b0;
case(dc_req_state)
dc_req_upload_idle:
begin
if(v_dc_flits_req)
begin
en_flits_in=1'b1;
next=1'b1;
end
end
dc_req_upload_busy:
begin
if(req_fifo_rdy)
begin
if(sel_cnt==2'b10)
fsm_rst=1'b1;
inc_cnt=1'b1;
v_dc_flit_out=1'b1;
end
end
endcase
end
// fsm state
always@(posedge clk)
begin
if(rst||fsm_rst)
dc_req_state<=1'b0;
else if(next)
dc_req_state<=1'b1;
end
// flits regs
always@(posedge clk)
begin
if(rst||fsm_rst)
dc_req_flits<=48'h0000;
else if(en_flits_in)
dc_req_flits<=dc_flits_req;
end
reg [15:0] dc_flit_out;
reg [1:0] dc_ctrl_out;
always@(*)
begin
case(sel_cnt)
2'b00:
\t begin
\t dc_flit_out=dc_req_flits[47:32];
\t\tdc_ctrl_out=2'b01;
\t\tend
2'b01:
\t begin
\t dc_flit_out=dc_req_flits[31:16];
\t\tdc_ctrl_out=2'b10;
\t\tend
2'b10:
\t begin
\t dc_flit_out=dc_req_flits[15:0];
\t\tdc_ctrl_out=2'b11;
\t\tend
default:begin
\t dc_flit_out=dc_req_flits[47:32];
\t\t\t\t dc_ctrl_out=2'b00;
\t\t\t\tend
endcase
end
///sel_counter
always@(posedge clk)
begin
if(rst||fsm_rst)
sel_cnt<=2'b00;
else if(inc_cnt)
sel_cnt<=sel_cnt+2'b01;
end
endmodule
|
//
// Multiple-Port RAM Descriptions
//
module MP_rf_LUT_RAM (
clk,
we,
wa,
ra1,
ra2,
di,
do1,
do2);
parameter depth=31;
parameter width=31;
parameter addr_width=5;
input clk;
input we;
input [addr_width-1:0] wa;
input [addr_width-1:0] ra1;
input [addr_width-1:0] ra2;
input [width-1:0] di;
output [width-1:0] do1;
output [width-1:0] do2;
reg [width-1:0] ram [depth-1:0];
always @(posedge clk)
begin
if (we)
ram[wa] <= di;
end
assign do1 = ram[ra1]; //Multiple reference to
assign do2 = ram[ra2]; //same array.
endmodule
//
// single-Port RAM Descriptions
//
module SP_rf_LUT_RAM (
clk,
we,
wa,
// ra2,
di,
re,
do0,
do1,
do2,
do3,
do4,
do5,
do6,
do7,
do8,
do9,
do10
// do2
);
parameter depth=11;
parameter width=16;
parameter addr_width=4;
input clk;
input we;
input [addr_width-1:0] wa;
input [width-1:0] di;
input re;
output [width-1:0] do0;
output [width-1:0] do1;
output [width-1:0] do2;
output [width-1:0] do3;
output [width-1:0] do4;
output [width-1:0] do5;
output [width-1:0] do6;
output [width-1:0] do7;
output [width-1:0] do8;
output [width-1:0] do9;
output [width-1:0] do10;
reg [width-1:0] ram [depth-1:0];
always @(posedge clk)
begin
if (we)
ram[wa] <= di;
end
assign do0 = re?ram[0]:16'hxxxx;
assign do1 = re?ram[1]:16'hxxxx;
assign do2 = re?ram[2]:16'hxxxx;
assign do3 = re?ram[3]:16'hxxxx;
assign do4 = re?ram[4]:16'hxxxx;
assign do5 = re?ram[5]:16'hxxxx;
assign do6 = re?ram[6]:16'hxxxx;
assign do7 = re?ram[7]:16'hxxxx;
assign do8 = re?ram[8]:16'hxxxx;
assign do9 = re?ram[9]:16'hxxxx;
assign do10= re?ram[10]:16'hxxxx;
endmodule
|
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