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/// date:2016/3/5 3/6 am: 10:57 done!
/// engineer:ZhaiShaoMIn
/// module function:because there are two kinds of uploadregs to
/// OUT_rep: inst_cache ,data_cache and memory, so we need to determine which can be writed into OUT_rep.
module arbiter_for_OUT_rep(//input
clk,
rst,
OUT_rep_rdy,
v_dc_rep,
v_mem_rep,
dc_rep_flit,
mem_rep_flit,
dc_rep_ctrl,
mem_rep_ctrl,
//output
ack_OUT_rep,
ack_dc_rep,
ack_mem_rep,
select // select 1/2
);
//input
input clk;
input rst;
input OUT_rep_rdy;
input v_dc_rep;
input v_mem_rep;
input [15:0] dc_rep_flit;
input [15:0] mem_rep_flit;
input [1:0] dc_rep_ctrl;
input [1:0] mem_rep_ctrl;
//output
output ack_OUT_rep;
output ack_dc_rep;
output ack_mem_rep;
output [1:0] select; // select 1/2
//parameter for fsm state
parameter arbiter_idle=3'b001;
parameter dc_uploading=3'b010;
parameter mem_uploading=3'b100;
//parameter of cmd
parameter nackrep_cmd=5'b10101;
parameter SCflurep_cmd=5'b11100;
reg [2:0] nstate;
reg [2:0] state;
reg priority1;
reg ack_OUT_rep;
reg ack_dc_rep;
reg ack_mem_rep;
reg update_priority;
reg [1:0] select;
/// nstate and output function
always@(*)
begin
nstate=state;
ack_OUT_rep=1'b0;
ack_dc_rep=1'b0;
ack_mem_rep=1'b0;
update_priority=1'b0;
select=2'b00;
case(state)
arbiter_idle:
begin
if({v_dc_rep,v_mem_rep}==2'b11)
begin
update_priority=1'b1;
if(priority1)
begin
nstate=dc_uploading;
end
else
begin
nstate=mem_uploading;
end
end
else if({v_dc_rep,v_mem_rep}==2'b01)
begin
nstate=mem_uploading;
end
else if({v_dc_rep,v_mem_rep}==2'b10)
begin
nstate=dc_uploading;
end
end
dc_uploading:
begin
if(OUT_rep_rdy)
begin
ack_OUT_rep=1'b1;
ack_dc_rep=1'b1;
\t\t\t\tselect=2'b01;
if(dc_rep_ctrl==2'b11||dc_rep_ctrl==2'b01&&(dc_rep_flit[9:5]==SCflurep_cmd||dc_rep_flit[9:5]==nackrep_cmd))
begin
nstate=arbiter_idle;
end
end
end
mem_uploading:
begin
if(OUT_rep_rdy)
begin
ack_OUT_rep=1'b1;
ack_mem_rep=1'b1;
\t\t\t\tselect=2'b10;
if(mem_rep_ctrl==2'b11||mem_rep_ctrl==2'b01&&(mem_rep_flit[9:5]==SCflurep_cmd||mem_rep_flit[9:5]==nackrep_cmd))
begin
nstate=arbiter_idle;
end
end
end
endcase
end
// fsm state reg
always@(posedge clk)
begin
if(rst)
state<=3'b001;
else
state<=nstate;
end
always@(posedge clk)
begin
if(rst)
priority1<=1'b0;
else if(update_priority)
priority1<=~priority1;
end
endmodule
|
/**********************************************************************
date:2016/3/30
designer:ZhaiShaoMin
module name:tb_arbiter_for_mem
module function: find out errors in this module if any
***********************************************************************/
`timescale 1ns/1ps
module tb_arbiter_for_mem();
//input
reg clk;
reg rst;
reg v_mem_download;
reg v_d_m_areg;
reg v_i_m_areg;
reg mem_access_done;
//output
wire ack_m_download;
wire ack_d_m_areg;
wire ack_i_m_areg;
wire v_m_download_m;
wire v_d_m_areg_m;
wire v_i_m_areg_m;
arbiter_for_mem uut (//input
.clk(clk),
.rst(rst),
.v_mem_download(v_mem_download),
.v_d_m_areg(v_d_m_areg),
.v_i_m_areg(v_i_m_areg),
.mem_access_done(mem_access_done),
//output
.ack_m_download(ack_m_download),
.ack_d_m_areg(ack_d_m_areg),
.ack_i_m_areg(ack_i_m_areg),
.v_m_download_m(v_m_download_m),
.v_d_m_areg_m(v_d_m_areg_m),
.v_i_m_areg_m(v_i_m_areg_m)
);
initial begin
clk=1'b0;
rst=1'b1;
v_mem_download=1'b0;
v_d_m_areg=1'b0;
v_i_m_areg=1'b0;
mem_access_done=1'b0;
end
`define clk_step # 14;
always #7 clk=~clk;
/////////////////////////////////////////////////////
/////////////////BEGIN TEST//////////////////////////
initial begin
`clk_step
rst=1'b0;
`clk_step
///////////////////////////////////////////////////
/////////1st case mem ic and dc all are valid//////
v_mem_download=1'b1;
v_d_m_areg=1'b1;
v_i_m_areg=1'b1;
mem_access_done=1'b0;
`clk_step
v_mem_download=1'b1;
v_d_m_areg=1'b1;
v_i_m_areg=1'b1;
mem_access_done=1'b0;
`clk_step
v_mem_download=1'b1;
v_d_m_areg=1'b1;
v_i_m_areg=1'b1;
mem_access_done=1'b0;
`clk_step
//mem done access in this cycle
v_mem_download=1'b1;
v_d_m_areg=1'b1;
v_i_m_areg=1'b1;
mem_access_done=1'b1;
`clk_step
//////////////////////////////////////////
//////////2nd case: dc and mem are valid//
v_mem_download=1'b1;
v_d_m_areg=1'b1;
v_i_m_areg=1'b0;
mem_access_done=1'b0;
`clk_step
v_mem_download=1'b1;
v_d_m_areg=1'b1;
v_i_m_areg=1'b0;
mem_access_done=1'b0;
`clk_step
v_mem_download=1'b1;
v_d_m_areg=1'b1;
v_i_m_areg=1'b0;
mem_access_done=1'b0;
`clk_step
//mem done access in this cycle
v_mem_download=1'b1;
v_d_m_areg=1'b1;
v_i_m_areg=1'b0;
mem_access_done=1'b1;
`clk_step
////////////////////////////////////////////////
////////3rd case: only mem valid ///////////////
v_mem_download=1'b1;
v_d_m_areg=1'b0;
v_i_m_areg=1'b0;
mem_access_done=1'b0;
`clk_step
v_mem_download=1'b1;
v_d_m_areg=1'b0;
v_i_m_areg=1'b0;
mem_access_done=1'b0;
`clk_step
v_mem_download=1'b1;
v_d_m_areg=1'b0;
v_i_m_areg=1'b0;
mem_access_done=1'b0;
`clk_step
//mem done access in this cycle
v_mem_download=1'b1;
v_d_m_areg=1'b0;
v_i_m_areg=1'b0;
mem_access_done=1'b1;
`clk_step
$stop;
end
endmodule
|
//date:2016/3/13
//engineer:ZhaiShaoMin
//module name:pipeline register between mem and wb
module core_mem_wb(//input
clk,
rst,
regwrite,
memtoreg,
aluresult,
read_memdata,
valid_read_memdata,
dest_reg,
//output
wb_regwrite,
wb_memtoreg,
wb_aluresult,
wb_read_memdata,
wb_dest_reg
);
//input
input clk;
input rst;
input regwrite;
input memtoreg;
input [31:0] aluresult;
input [31:0] read_memdata;
input valid_read_memdata;
input [4:0] dest_reg;
//output
output wb_regwrite;
output wb_memtoreg;
output [31:0] wb_aluresult;
output [31:0] wb_read_memdata;
output [4:0] wb_dest_reg;
reg wb_regwrite;
reg wb_memtoreg;
reg [31:0] wb_aluresult;
reg [31:0] wb_read_memdata;
reg [4:0] wb_dest_reg;
always@(posedge clk)
begin
if(rst)
begin
wb_regwrite<=1'b0;
wb_memtoreg<=1'b0;
wb_aluresult<=32'h0000;
wb_read_memdata<=32'h0000;
wb_dest_reg<=5'b00000;
end
else if(valid_read_memdata)
begin
wb_regwrite<=regwrite;
wb_memtoreg<=memtoreg;
wb_aluresult<=aluresult;
wb_read_memdata<=read_memdata;
wb_dest_reg<=dest_reg;
end
end
endmodule
|
//date:2016/3/16
//engineer: zhaishaomin
//module function :test whether dc_download will behave as what i want it to do ,such as handling coming flit correctly
/*
// test examples
//wbrep 11 flits long
flits_d_m_areg={flits_in[140:139],1\'b1,local_id,1\'b0,wbrep_cmd,5\'b00000,seled_addr,data_read};
//ATflurep 11 flits long
flits_d_m_areg={state_tag_out[3:2],1\'b0,local_id,1\'b1,ATflurep_cmd,5\'b00000,
seled_addr[31:13],delayed_state_tag,seled_addr[8:0],data_read};
//shrep 9 flits long
msg={temp_rep_head_flit,data_read,32\'h00000000};
//SHexrep 9 flits long
msg={temp_rep_head_flit,data_read,32\'h00000000};
//exrep 9 flits long
msg={temp_rep_head_flit,data_read,32\'h00000000};
//wbreq 3 flits long
msg={temp_rep_head_flit,seled_addr,128\'h0000};
//flushreq 3 flits long
msg={temp_req_head_flit,seled_addr,128\'h0000};
//SCinvreq or invreq 3 flits long
msg={temp_req_head_flit,seled_addr,128\'h0000};
//shreq 3 flits long
flits_d_m_areg={seled_addr[12:11],1\'b0,local_id,1\'b1,shreq_cmd,5\'b00000,seled_addr,128\'hzzzz};
//exreq 3 flits long
flits_d_m_areg={state_tag_out[3:2],1\'b0,local_id,1\'b1,exreq_cmd,5\'b00000,seled_addr,128\'hzzzz};
//C2Hinvrep 3 flits long
flits_d_m_areg={state_tag_out[3:2],1\'b0,local_id,1\'b1,C2Hinvrep_cmd,5\'b00000,
seled_addr[31:13],delayed_state_tag,seled_addr[8:0],128\'hzzzz};
//flushrep 3 flits long
flits_d_m_areg={flits_in[140:139],1\'b1,local_id,1\'b0,flushrep_cmd,5\'b00000,seled_addr,128\'h0000};
//flushfail_rep 3 flits long
flits_d_m_areg={flits_in[140:139],1\'b1,flits_in[132:131],1\'b0,flushfail_rep_cmd,5\'b00000,seled_addr,128\'h0000};
//wbfail_rep 3 flits long
flits_d_m_areg={flits_in[140:139],1\'b1,flits_in[132:131],1\'b0,wbfail_rep_cmd,5\'b00000,seled_addr,128\'h0000};
//nackrep 1 flit long
msg={temp_rep_head_flit,data_read,32\'h00000000};
//C2Cinvrep 1 flit long
flits_d_m_areg={state_tag_out[3:2],1\'b0,local_id,1\'b1,C2Hinvrep_cmd,5\'b00000,
seled_addr[31:13],delayed_state_tag,seled_addr[8:0],128\'hzzzz};
//SCflushrep 1 flit long
msg={temp_rep_head_flit,data_read,32\'h00000000};
*/
`timescale 1ns/1ps
module tb_dc_download();
//inputs
reg clk;
reg rst;
reg [15:0] IN_flit_dc;
reg v_IN_flit_dc;
reg [1:0] In_flit_ctrl_dc;
reg dc_done_access;
//output
wire v_dc_download;
wire [1:0] dc_downlaod_state;
wire [143:0]dc_download_flits;
//instantiate the uut
dc_download uut(//input
.clk(clk),
.rst(rst),
.IN_flit_dc(IN_flit_dc),
.v_IN_flit_dc(v_IN_flit_dc),
.In_flit_ctrl_dc(In_flit_ctrl_dc),
.dc_done_access(dc_done_access),
//output
.v_dc_download(v_dc_download),
.dc_download_flits(dc_download_flits),
.dc_download_state(dc_download_state)
);
// store the simulation log into log_file
integer logfile;
// Initialize Inputs
initial begin
clk = 1\'b0;
rst = 1\'b0;
IN_flit_dc=16\'h1234;
v_IN_flit_dc=1\'b0;
In_flit_ctrl_dc=2\'b00;
dc_done_access=1\'b0;
end
always #20 clk=~clk;
`define step #40;
initial begin
/////// mem_download test /////////
// First reset all //
$display("(%t) Initializing...", $time);
$fdisplay(log_file, "(%t) Initializing...", $time);
rst=1;
`step
rst=0;
`step
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////REP MSG FROM IN_REP_FIFO//////////////////////////////////////////////////////////////////////
//after a few cycles ,a rep msg from IN_local_rep fifo come and dc_download should be ready to receive the flits
// note :here are three kinds of reps and reqs totally,
// including :9 flits long msg : exrep , shrep, sh->exrep
// 3 flits long msg : invreq, wbreq, flushreq, scflushreq,
// 1 flit long msg : C2Cinvrep so far.
/////////////////////////////////////////////////////////////
/////////////FIRST TEST 9 FLITS LONG MSG
//first flit
IN_flit_dc=16\'h1234;
v_IN_flit_dc=1\'b1;
In_flit_ctrl_dc=2\'b01;
`step
// second flit comes and is usefull for dc_download
IN_flit_dc=16\'h1234;
v_IN_flit_dc=1\'b1;
In_flit_ctrl_dc=2\'b10;
`step
// 3rd flit comes and is usefull for dc_download
IN_flit_dc=16\'h1234;
v_IN_flit_dc=1\'b1;
In_flit_ctrl_dc=2\'b10;
`step
// 4th flit comes and is usefull for dc_download
IN_flit_dc=16\'h1234;
v_IN_flit_dc=1\'b1;
In_flit_ctrl_dc=2\'b10;
// JUST a test that whether ic_download only output inst word to inst cache when it has receiverd all flits taht required!
$display("(%t)TEST ERROR msg to data cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
$fdisplay(logfile,"(%t) TEST ERROR msg to data cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
`step
// 5th flit comes and is usefull for dc_download
IN_flit_dc=16\'h1234;
v_IN_flit_dc=1\'b1;
In_flit_ctrl_dc=2\'b10;
`step
// 6th flit comes and is usefull for dc_download
IN_flit_dc=16\'h1234;
v_IN_flit_dc=1\'b1;
In_flit_ctrl_dc=2\'b10;
// just test that whether ic_download only output inst word to inst cache when it has receiverd all flits taht required!
`step
// 7th flit comes and is usefull for dc_download
IN_flit_dc=16\'h1234;
v_IN_flit_dc=1\'b1;
In_flit_ctrl_dc=2\'b10;
`step
// 8th flit comes and is usefull for dc_download
IN_flit_dc=16\'h1234;
v_IN_flit_dc=1\'b1;
In_flit_ctrl_dc=2\'b10;
`step
// 9th flit comes and is usefull for dc_download
IN_flit_dc=16\'h1234;
v_IN_flit_dc=1\'b1;
In_flit_ctrl_dc=2\'b11;
`step
//at this time, inst cache is ready to receive inst word and all inst words have been recceived by ic_download
$display("(%t) msg to data cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
$fdisplay(logfile,"(%t) msg todata cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
/////////////////////////////////////////////////////////////
/////////////FIRST TEST 3 FLITS LONG MSG
//first flit
IN_flit_dc=16\'h1234;
v_IN_flit_dc=1\'b1;
In_flit_ctrl_dc=2\'b01;
`step
// second flit comes and is usefull for dc_download
IN_flit_dc=16\'h1234;
v_IN_flit_dc=1\'b1;
In_flit_ctrl_dc=2\'b10;
// JUST a test that whether ic_download only output inst word to inst cache when it has receiverd all flits taht required!
$display("(%t)TEST ERROR msg to data cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
$fdisplay(logfile,"(%t) TEST ERROR msg to data cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
`step
// 3rd flit comes and is usefull for dc_download
IN_flit_dc=16\'h1234;
v_IN_flit_dc=1\'b1;
In_flit_ctrl_dc=2\'b11;
`step
//at this time, inst cache is ready to receive inst word and all inst words have been recceived by ic_download
$display("(%t) msg to data cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
$fdisplay(logfile,"(%t) msg to data cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
/////////////////////////////////////////////////////////////
/////////////FIRST TEST 1 FLITS LONG MSG
//first flit
IN_flit_dc=16\'h1234; // condition: IN_flit_dc[9:5]==nackrep_cmd||IN_flit_dc[9:5]==SCflurep_cmd||IN_flit_dc[9:5]==C2Cinvrep_cmd
v_IN_flit_dc=1\'b1;
In_flit_ctrl_dc=2\'b01;
`step
//at this time, inst cache is ready to receive inst word and all inst words have been recceived by ic_download
$display("(%t) msg to data cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
$fdisplay(logfile,"(%t) msg to data cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
$stop;
end
endmodule
|
/**************************************************************
date:2016/3/30
designer:ZhaiShaoMin
module name :tb_arbiter_for_IN_node
module function : check out errors about arbiter_for_IN_node
**************************************************************/
`timescale 1ns/1ps
module tb_arbiter_IN_node();
//input
reg clk;
reg rst;
reg in_req_rdy;
reg in_rep_rdy;
reg [1:0] req_ctrl_in;
reg [1:0] rep_ctrl_in;
reg [15:0] req_flit_in;
reg [15:0] rep_flit_in;
reg [1:0] ic_download_state_in;
reg [1:0] dc_download_state_in;
reg [1:0] mem_download_state_in;
//output
wire ack_req;
wire ack_rep;
wire v_ic;
wire [15:0] flit_ic;
wire [1:0] ctrl_ic;
wire v_dc;
wire [15:0] flit_dc;
wire [1:0] ctrl_dc;
wire v_mem;
wire [15:0] flit_mem;
wire [1:0] ctrl_mem;
//instante the design unit
arbiter_IN_node uut (//input
.clk(clk),
.rst(rst),
.in_req_rdy(in_req_rdy),
.in_rep_rdy(in_rep_rdy),
.req_ctrl_in(req_ctrl_in),
.rep_ctrl_in(rep_ctrl_in),
.req_flit_in(req_flit_in),
.rep_flit_in(rep_flit_in),
.ic_download_state_in(ic_download_state_in),
.dc_download_state_in(dc_download_state_in),
.mem_download_state_in(mem_download_state_in),
//output
.ack_req(ack_req),
.ack_rep(ack_rep),
.v_ic(v_ic),
.flit_ic(flit_ic),
.ctrl_ic(ctrl_ic),
.v_dc(v_dc),
.flit_dc(flit_dc),
.ctrl_dc(ctrl_dc),
.v_mem(v_mem),
.flit_mem(flit_mem),
.ctrl_mem(ctrl_mem)
);
integer log_file;
//initial inputs
initial
begin
clk=1\'b0;
rst=1\'b1;
in_req_rdy=1\'b0;
in_rep_rdy=1\'b0;
req_ctrl_in=2\'b00;
rep_ctrl_in=2\'b00;
req_flit_in=16\'h0000;
rep_flit_in=16\'h0000;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b00;//mem_idle
log_file=$fopen("log_arbiter_IN_node");
end
`define clk_step #14;
always #7 clk=~clk;
/////////////////////////////////////////////////////////////////
/////////////BEGIN TEST!/////////////////////////////////////////
initial begin
`clk_step
$display("BEGIN TEST!");
$fdisplay(log_file,"BEGIN TEST!");
rst=1\'b0;
/////////////////////////////////////////////////////////////
///////////first case : ic rep flit and dc req come////////
////first flit come anad both ic_download and dc_download are ready
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hc0de;
rep_flit_in=16\'hc280;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b00;//mem_idle
///second flits ,both ready
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b10;
rep_ctrl_in=2\'b10;
req_flit_in=16\'hc1de;
rep_flit_in=16\'hc380;
ic_download_state_in=2\'b01;//ic_busy
dc_download_state_in=2\'b01;//dc_busy
mem_download_state_in=2\'b00;//mem_idle
///3rd flits ,both ready
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b10;
rep_ctrl_in=2\'b10;
req_flit_in=16\'hc2de;
rep_flit_in=16\'hc480;
ic_download_state_in=2\'b01;//ic_busy
dc_download_state_in=2\'b01;//dc_busy
mem_download_state_in=2\'b00;//mem_idle
////after a while ,last flits both come
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b11;
rep_ctrl_in=2\'b11;
req_flit_in=16\'hc3de;
rep_flit_in=16\'hc580;
ic_download_state_in=2\'b01;//ic_busy
dc_download_state_in=2\'b01;//dc_busy
mem_download_state_in=2\'b00;//mem_idle
///this time make ic busy for a moment
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hc0de;
rep_flit_in=16\'hc280;
ic_download_state_in=2\'b10;//ic_busy
dc_download_state_in=2\'b00;
mem_download_state_in=2\'b00;
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b10;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hc1de;
rep_flit_in=16\'hc280;
ic_download_state_in=2\'b10;//ic_busy
dc_download_state_in=2\'b01;
mem_download_state_in=2\'b00;
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b10;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hc2de;
rep_flit_in=16\'hc280;
ic_download_state_in=2\'b10;//ic_busy
dc_download_state_in=2\'b01;
mem_download_state_in=2\'b00;
////now ic_donwload is idle
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b11;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hc3de;
rep_flit_in=16\'hc280;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b01;
mem_download_state_in=2\'b00;
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b10;
req_flit_in=16\'hc0df;
rep_flit_in=16\'hc0de;
ic_download_state_in=2\'b01;//ic_busy
dc_download_state_in=2\'b10;//dc_rdy
mem_download_state_in=2\'b00;
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b10;
req_flit_in=16\'hc0df;
rep_flit_in=16\'hc1de;
ic_download_state_in=2\'b01;//ic_busy
dc_download_state_in=2\'b10;//dc_rdy
mem_download_state_in=2\'b00;
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b11;
req_flit_in=16\'hc0df;
rep_flit_in=16\'hc2de;
ic_download_state_in=2\'b01;//ic_busy
dc_download_state_in=2\'b10;//dc_rdy
mem_download_state_in=2\'b00;
`clk_step
////////////////////////////////////////////////////////////
////////////second case :ic rep flit and mem req come ///////
///both mem and ic idle
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hfed0;
rep_flit_in=16\'hc280;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b00;//mem_idle
///second flits ,both ready
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b10;
rep_ctrl_in=2\'b10;
req_flit_in=16\'h1234;
rep_flit_in=16\'hc380;
ic_download_state_in=2\'b01;//ic_busy
dc_download_state_in=2\'b01;//dc_busy
mem_download_state_in=2\'b00;//mem_idle
///3rd flits ,both ready
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b10;
rep_ctrl_in=2\'b10;
req_flit_in=16\'habcd;
rep_flit_in=16\'hc480;
ic_download_state_in=2\'b01;//ic_busy
dc_download_state_in=2\'b01;//dc_busy
mem_download_state_in=2\'b00;//mem_idle
////after a while ,last flits both come
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b11;
rep_ctrl_in=2\'b11;
req_flit_in=16\'hfed8;
rep_flit_in=16\'hc580;
ic_download_state_in=2\'b01;//ic_busy
dc_download_state_in=2\'b01;//dc_busy
mem_download_state_in=2\'b00;//mem_idle
///this time make mem rdy for a moment
//first flit to ic and mem download is ready for mem now
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hfed0;
rep_flit_in=16\'hc280;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b10;//mem_rdy
//second flit to ic and mem is still rdy for m_dl
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b10;
req_flit_in=16\'hfed0;
rep_flit_in=16\'hc380;
ic_download_state_in=2\'b01;//ic_busy
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b10;//mem_rdy
//third flit to ic and first flit to mem
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b10;
req_flit_in=16\'hfed0;
rep_flit_in=16\'hc480;
ic_download_state_in=2\'b01;//ic_busy
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b00;//mem_idle
//4th to ic and 2nd to mem
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b10;
rep_ctrl_in=2\'b10;
req_flit_in=16\'h1234;
rep_flit_in=16\'hc580;
ic_download_state_in=2\'b01;//ic_busy
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b01;//mem_busy
//last to ic and 7th to mem
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b10;
rep_ctrl_in=2\'b11;
req_flit_in=16\'habcd;
rep_flit_in=16\'hc980;
ic_download_state_in=2\'b01;//ic_busy
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b01;//mem_busy
//no flit to ic and last to mem
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b0;
req_ctrl_in=2\'b11;
rep_ctrl_in=2\'b00;
req_flit_in=16\'h1357;
rep_flit_in=16\'hc980;
ic_download_state_in=2\'b10;//ic_rdy
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b01;//mem_busy
////////////////////////////////////////////////////////////
///////////third case: only ic comes !//////////////////////
`clk_step
in_req_rdy=1\'b0;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b00;
rep_ctrl_in=2\'b01;
req_flit_in=16\'h1234;
rep_flit_in=16\'hc280;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b00;//mem_idle
`clk_step
in_req_rdy=1\'b0;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b00;
rep_ctrl_in=2\'b10;
req_flit_in=16\'h1234;
rep_flit_in=16\'hc380;
ic_download_state_in=2\'b01;//ic_idle
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b00;//mem_idle
`clk_step
in_req_rdy=1\'b0;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b00;
rep_ctrl_in=2\'b10;
req_flit_in=16\'h1234;
rep_flit_in=16\'hc480;
ic_download_state_in=2\'b01;//ic_idle
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b00;//mem_idle
`clk_step
in_req_rdy=1\'b0;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b00;
rep_ctrl_in=2\'b11;
req_flit_in=16\'h1234;
rep_flit_in=16\'hc580;
ic_download_state_in=2\'b01;//ic_idle
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b00;//mem_idle
////////////////////////////////////////////////////////////
///////////4th case: dc rep and mem req come////////////////
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hfed0;
rep_flit_in=16\'hc0de;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b00;//mem_idle
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b10;
rep_ctrl_in=2\'b10;
req_flit_in=16\'hfed1;
rep_flit_in=16\'hc1de;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b01;//dc_busy
mem_download_state_in=2\'b01;//mem_busy
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b10;
rep_ctrl_in=2\'b10;
req_flit_in=16\'hfed2;
rep_flit_in=16\'hc2de;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b01;//dc_busy
mem_download_state_in=2\'b01;//mem_busy
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b10;
rep_ctrl_in=2\'b10;
req_flit_in=16\'hfed3;
rep_flit_in=16\'hc3de;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b01;//dc_busy
mem_download_state_in=2\'b01;//mem_busy
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b10;
rep_ctrl_in=2\'b11;
req_flit_in=16\'hfed4;
rep_flit_in=16\'hc4de;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b01;//dc_busy
mem_download_state_in=2\'b01;//mem_busy
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b10;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hfed5;
rep_flit_in=16\'hc5de;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b10;//dc_rdy
mem_download_state_in=2\'b01;//mem_busy
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b11;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hfed4;
rep_flit_in=16\'hc4de;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b10;//dc_rdy
mem_download_state_in=2\'b01;//mem_busy
////////////////////////////////////////////////////////////
///////////5th case: mem rep and dc req come/////////////////
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hc0de;
rep_flit_in=16\'hfed0;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b00;//mem_idle
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b10;
rep_ctrl_in=2\'b10;
req_flit_in=16\'hc1de;
rep_flit_in=16\'hfed1;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b01;//dc_busy
mem_download_state_in=2\'b01;//mem_busy
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b10;
rep_ctrl_in=2\'b10;
req_flit_in=16\'hc2de;
rep_flit_in=16\'hfed2;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b01;//dc_busy
mem_download_state_in=2\'b01;//mem_busy
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b11;
rep_ctrl_in=2\'b10;
req_flit_in=16\'hc3de;
rep_flit_in=16\'hfed3;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b01;//dc_busy
mem_download_state_in=2\'b01;//mem_busy
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b11;
req_flit_in=16\'hc0de;
rep_flit_in=16\'hfed4;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b10;//dc_rdy
mem_download_state_in=2\'b01;//mem_busy
////////////////////////////////////////////////////////////
///////////6th case:dc rep and dc req come!/////////////////
// both come and dc rep win
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hc0de;
rep_flit_in=16\'hc0ef;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b00;//mem_idle
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b10;
req_flit_in=16\'hc0de;
rep_flit_in=16\'hc1ef;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b01;//dc_busy
mem_download_state_in=2\'b01;//mem_idle
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b10;
req_flit_in=16\'hc0de;
rep_flit_in=16\'hc2ef;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b01;//dc_busy
mem_download_state_in=2\'b01;//mem_idle
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b11;
req_flit_in=16\'hc0de;
rep_flit_in=16\'hc3ef;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b01;//dc_busy
mem_download_state_in=2\'b01;//mem_idle
`clk_step
`clk_step
`clk_step
`clk_step
/////////////////////////////
//it\'s turn of dc req////////
in_req_rdy=1\'b1;
in_rep_rdy=1\'b0;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hc0de;
rep_flit_in=16\'hc3ef;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b00;//mem_idle
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b0;
req_ctrl_in=2\'b10;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hc1de;
rep_flit_in=16\'hc3ef;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b01;//dc_busy
mem_download_state_in=2\'b01;//mem_idle
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b0;
req_ctrl_in=2\'b10;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hc2de;
rep_flit_in=16\'hc3ef;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b01;//dc_busy
mem_download_state_in=2\'b01;//mem_idle
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b0;
req_ctrl_in=2\'b11;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hc2de;
rep_flit_in=16\'hc4ef;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b01;//dc_busy
mem_download_state_in=2\'b01;//mem_idle
//next cycle dc_rdy
////////////////////////////////////////////////////////////
///////////7th case:mem rep and mem req come////////////////
// both come and mem rep win
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hfed0;
rep_flit_in=16\'hfeb0;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b00;//mem_idle
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b10;
req_flit_in=16\'hfed0;
rep_flit_in=16\'hfeb1;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_busy
mem_download_state_in=2\'b01;//mem_idle
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b10;
req_flit_in=16\'hfed0;
rep_flit_in=16\'hfeb2;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_busy
mem_download_state_in=2\'b01;//mem_idle
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b11;
req_flit_in=16\'hfed0;
rep_flit_in=16\'hfeb3;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b01;//mem_busy
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hfed0;
rep_flit_in=16\'hfeb3;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b01;//mem_busy
`clk_step
`clk_step
`clk_step
/////////////////////////////
//it\'s turn of dc req////////
in_req_rdy=1\'b1;
in_rep_rdy=1\'b0;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hfed0;
rep_flit_in=16\'hfeb3;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b00;//mem_idle
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b0;
req_ctrl_in=2\'b10;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hfed1;
rep_flit_in=16\'hfeb3;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b01;//mem_busy
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b0;
req_ctrl_in=2\'b10;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hfed2;
rep_flit_in=16\'hfeb3;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b01;//dc_idle
mem_download_state_in=2\'b01;//mem_busy
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b0;
req_ctrl_in=2\'b11;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hfed3;
rep_flit_in=16\'hfeb0;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_busy
mem_download_state_in=2\'b01;//mem_busy
//mem will reject coming flit whatever kind
////////////////////////////////////////////////////////////
//////////8th case:only dc rep comes////////////////////////
`clk_step
in_req_rdy=1\'b0;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hc0de;
rep_flit_in=16\'hc0ef;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b00;//mem_idle
`clk_step
in_req_rdy=1\'b0;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b10;
req_flit_in=16\'hc0de;
rep_flit_in=16\'hc1ef;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b01;//dc_busy
mem_download_state_in=2\'b01;//mem_idle
`clk_step
in_req_rdy=1\'b0;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b10;
req_flit_in=16\'hc0de;
rep_flit_in=16\'hc2ef;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b01;//dc_busy
mem_download_state_in=2\'b01;//mem_idle
`clk_step
in_req_rdy=1\'b0;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b11;
req_flit_in=16\'hc0de;
rep_flit_in=16\'hc3ef;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b01;//dc_busy
mem_download_state_in=2\'b01;//mem_idle
////////////////////////////////////////////////////////////
///////////9th case:only dc req come////////////////////////
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b0;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hc0de;
rep_flit_in=16\'hc0ef;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b00;//mem_idle
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b0;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b10;
req_flit_in=16\'hc0de;
rep_flit_in=16\'hc1ef;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b01;//dc_busy
mem_download_state_in=2\'b01;//mem_idle
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b0;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b10;
req_flit_in=16\'hc0de;
rep_flit_in=16\'hc2ef;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b01;//dc_busy
mem_download_state_in=2\'b01;//mem_idle
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b0;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b11;
req_flit_in=16\'hc0de;
rep_flit_in=16\'hc3ef;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b01;//dc_busy
mem_download_state_in=2\'b01;//mem_idle
////////////////////////////////////////////////////////////
///////////10th case:only mem rep comes/////////////////////
`clk_step
in_req_rdy=1\'b0;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hfed0;
rep_flit_in=16\'hfeb0;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b00;//mem_idle
`clk_step
in_req_rdy=1\'b0;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b10;
req_flit_in=16\'hfed0;
rep_flit_in=16\'hfeb1;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_busy
mem_download_state_in=2\'b01;//mem_idle
`clk_step
in_req_rdy=1\'b0;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b10;
req_flit_in=16\'hfed0;
rep_flit_in=16\'hfeb2;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_busy
mem_download_state_in=2\'b01;//mem_idle
`clk_step
in_req_rdy=1\'b0;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b11;
req_flit_in=16\'hfed0;
rep_flit_in=16\'hfeb3;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b01;//mem_busy
`clk_step
in_req_rdy=1\'b0;
in_rep_rdy=1\'b1;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hfed0;
rep_flit_in=16\'hfeb3;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b01;//mem_busy
////////////////////////////////////////////////////////////
////////////11th case: only mem req comes //////////////////
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b0;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hfed0;
rep_flit_in=16\'hfeb0;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b00;//mem_idle
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b0;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b10;
req_flit_in=16\'hfed0;
rep_flit_in=16\'hfeb1;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_busy
mem_download_state_in=2\'b01;//mem_idle
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b0;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b10;
req_flit_in=16\'hfed0;
rep_flit_in=16\'hfeb2;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_busy
mem_download_state_in=2\'b01;//mem_idle
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b0;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b11;
req_flit_in=16\'hfed0;
rep_flit_in=16\'hfeb3;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b01;//mem_busy
`clk_step
in_req_rdy=1\'b1;
in_rep_rdy=1\'b0;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hfed0;
rep_flit_in=16\'hfeb3;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b01;//mem_busy
////////////////////////////////////////////////////////////
/////////////12th case: nothing comes///////////////////////
`clk_step
in_req_rdy=1\'b0;
in_rep_rdy=1\'b0;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hfed0;
rep_flit_in=16\'hfeb0;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b00;//mem_idle
`clk_step
in_req_rdy=1\'b0;
in_rep_rdy=1\'b0;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b10;
req_flit_in=16\'hfed0;
rep_flit_in=16\'hfeb1;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_busy
mem_download_state_in=2\'b01;//mem_idle
`clk_step
in_req_rdy=1\'b0;
in_rep_rdy=1\'b0;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b10;
req_flit_in=16\'hfed0;
rep_flit_in=16\'hfeb2;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_busy
mem_download_state_in=2\'b01;//mem_idle
`clk_step
in_req_rdy=1\'b0;
in_rep_rdy=1\'b0;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b11;
req_flit_in=16\'hfed0;
rep_flit_in=16\'hfeb3;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b01;//mem_busy
`clk_step
in_req_rdy=1\'b0;
in_rep_rdy=1\'b0;
req_ctrl_in=2\'b01;
rep_ctrl_in=2\'b01;
req_flit_in=16\'hfed0;
rep_flit_in=16\'hfeb3;
ic_download_state_in=2\'b00;//ic_idle
dc_download_state_in=2\'b00;//dc_idle
mem_download_state_in=2\'b01;//mem_busy
`clk_step
$display("FINISH TEST!");
$fdisplay(log_file,"FINISH TEST!");
$stop;
end
endmodule
|
//date:2016/3/13
//engineer:ZhaiShaoMin
//module name: pipeline register between id and ex
module core_id_ex(//input
clk,
rst,
// inst_lo,
wb_reg_write,
wb_memtoreg,
mem_memread,
mem_memwrite,
mem_ll_mem,
mem_sc_mem,
regdst,
aluop,
alusrc,
regread1,
regread2,
sign_extend,
reg_rs,
reg_rt,
reg_rd,
//output
// ex_inst_lo,
ex_wb_reg_write,
ex_wb_memtoreg,
ex_mem_memread,
ex_mem_memwrite,
ex_mem_ll_mem,
ex_mem_sc_mem,
ex_regdst,
ex_aluop,
ex_alusrc,
ex_regread1,
ex_regread2,
ex_sign_extend,
ex_reg_rs,
ex_reg_rt,
ex_reg_rd);
//input
input clk;
input rst;
//input [15:0] inst_lo;
input wb_reg_write;
input wb_memtoreg;
input mem_memread;
input mem_memwrite;
input mem_ll_mem;
input mem_sc_mem;
input regdst;
input [1:0] aluop;
input alusrc;
input [31:0] regread1;
input [31:0] regread2;
input [31:0] sign_extend;
input [4:0] reg_rs;
input [4:0] reg_rt;
input [4:0] reg_rd;
//outpu
//output [15:0] ex_inst_lo;
output ex_wb_reg_write;
output ex_wb_memtoreg;
output ex_mem_memread;
output ex_mem_memwrite;
output ex_mem_ll_mem;
output ex_mem_sc_mem;
output ex_regdst;
output [1:0] ex_aluop;
output ex_alusrc;
output [31:0] ex_regread1;
output [31:0] ex_regread2;
output [31:0] ex_sign_extend;
output [4:0] ex_reg_rs;
output [4:0] ex_reg_rt;
output [4:0] ex_reg_rd;
//define regs
//reg [15:0] ex_inst_lo;
reg ex_wb_reg_write;
reg ex_wb_memtoreg;
reg ex_mem_memread;
reg ex_mem_memwrite;
reg ex_mem_ll_mem;
reg ex_mem_sc_mem;
reg ex_regdst;
reg [1:0] ex_aluop;
reg ex_alusrc;
reg [31:0] ex_regread1;
reg [31:0] ex_regread2;
reg [31:0] ex_sign_extend;
reg [4:0] ex_reg_rs;
reg [4:0] ex_reg_rt;
reg [4:0] ex_reg_rd;
always@(posedge clk)
begin
if(rst)
begin
// ex_inst_lo<=15'b000000000000000;
ex_wb_reg_write<=1'b0;
ex_wb_memtoreg<=1'b0;
ex_mem_memread<=1'b0;
ex_mem_memwrite<=1'b0;
ex_mem_ll_mem<=1'b0;
ex_mem_sc_mem<=1'b0;
ex_regdst<=1'b0;
ex_aluop<=2'b00;
ex_alusrc<=1'b0;
ex_regread1<=32'h0000;
ex_regread2<=32'h0000;
ex_sign_extend<=32'h0000;
ex_reg_rs<=5'b00000;
ex_reg_rt<=5'b00000;
ex_reg_rd<=5'b00000;
end
else
begin
// ex_inst_lo<=inst_lo;
ex_wb_reg_write<=wb_reg_write;
ex_wb_memtoreg<=wb_memtoreg;
ex_mem_memread<=mem_memread;
ex_mem_memwrite<=mem_memwrite;
ex_mem_ll_mem<=mem_ll_mem;
ex_mem_sc_mem<=mem_sc_mem;
ex_regdst<=regdst;
ex_aluop<=aluop;
ex_alusrc<=alusrc;
ex_regread1<=regread1;
ex_regread2<=regread2;
ex_sign_extend<=sign_extend;
ex_reg_rs<=reg_rs;
ex_reg_rt<=reg_rt;
ex_reg_rd<=reg_rd;
end
end
endmodule
|
/**********************************************************************
date:2016/3/26
designer:ZhaiShaoMin
project:ring network multicore
module name:tb_arbiter_OUT_rep
module function: figure out what\'s wrong with it
***********************************************************************/
`timescale 1ns/1ps
module tb_arbiter_for_OUT_req();
//input
reg clk;
reg rst;
reg OUT_req_rdy;
reg v_ic_req;
reg v_dc_req;
reg v_mem_req;
reg [1:0] ic_req_ctrl;
reg [1:0] dc_req_ctrl;
reg [1:0] mem_req_ctrl;
//output
wire ack_OUT_req;
wire ack_ic_req;
wire ack_dc_req;
wire ack_mem_req;
wire [2:0] select; // select 1/3
arbiter_for_OUT_req uut(//input
.clk(clk),
.rst(rst),
.OUT_req_rdy(OUT_req_rdy),
.v_ic_req(v_ic_req),
.v_dc_req(v_dc_req),
.v_mem_req(v_mem_req),
.ic_req_ctrl(ic_req_ctrl),
.dc_req_ctrl(dc_req_ctrl),
.mem_req_ctrl(mem_req_ctrl),
//output
.ack_OUT_req(ack_OUT_req),
.ack_ic_req(ack_ic_req),
.ack_dc_req(ack_dc_req),
.ack_mem_req(ack_mem_req),
.select(select)
);
integer log_file;
//define task for compare expected outputs with actural outputs
task cmp_outputs;
input exp_ack_OUT_req;
input exp_ack_ic_req;
input exp_ack_dc_req;
input exp_ack_mem_req;
input [2:0] exp_select;
begin
$display("Time:%t\
",$time);
$fdisplay (log_file, "Time: %t\
", $time);
if (ack_OUT_req != exp_ack_OUT_req)
begin
$display("ERROR: Invalid ack_OUT_req\
\\t Expected: 0x%x \
\\t Acutal: 0x%x", exp_ack_OUT_req,ack_OUT_req);
$fdisplay(log_file,"ERROR: Invalid ack_OUT_req\
\\t Expected: 0x%x \
\\t Acutal: 0x%x", exp_ack_OUT_req,ack_OUT_req);
end
if (ack_ic_req != exp_ack_ic_req)
begin
$display("ERROR: Invalid ack_ic_req\
\\t Expected: 0x%x \
\\t Acutal: 0x%x", exp_ack_ic_req,ack_ic_req);
$fdisplay(log_file,"ERROR: Invalid ack_ic_req\
\\t Expected: 0x%x \
\\t Acutal: 0x%x", exp_ack_ic_req,ack_ic_req);
end
if (ack_dc_req != exp_ack_dc_req)
begin
$display("ERROR: Invalid ack_dc_req\
\\t Expected: 0x%x \
\\t Acutal: 0x%x", exp_ack_dc_req,ack_dc_req);
$fdisplay(log_file,"ERROR: Invalid ack_dc_req\
\\t Expected: 0x%x \
\\t Acutal: 0x%x", exp_ack_dc_req,ack_dc_req);
end
if (ack_mem_req != exp_ack_mem_req)
begin
$display("ERROR: Invalid ack_mem_req\
\\t Expected: 0x%x \
\\t Acutal: 0x%x", exp_ack_mem_req,ack_mem_req);
$fdisplay(log_file,"ERROR: Invalid ack_mem_req\
\\t Expected: 0x%x \
\\t Acutal: 0x%x", exp_ack_mem_req,ack_mem_req);
end
if (select != exp_select)
begin
$display("ERROR: Invalid select\
\\t Expected: 0x%x \
\\t Acutal: 0x%x", exp_select,select);
$fdisplay(log_file,"ERROR: Invalid select\
\\t Expected: 0x%x \
\\t Acutal: 0x%x", exp_select,select);
end
if((ack_OUT_req != exp_ack_OUT_req)&&
(ack_ic_req != exp_ack_ic_req)&&
(ack_dc_req != exp_ack_dc_req)&&
(ack_mem_req != exp_ack_mem_req)&&
(select != exp_select))
begin
$display("passed test!");
$fdisplay(log_file,"passed test!");
end
end
endtask
//initial inputs
initial begin
clk=1\'b0;
rst=1\'b1;
OUT_req_rdy=1\'b0;
v_ic_req=1\'b0;
v_dc_req=1\'b0;
v_mem_req=1\'b0;
ic_req_ctrl=2\'b00;
dc_req_ctrl=2\'b00;
mem_req_ctrl=2\'b00;
log_file=$fopen("log_arbiter_for_OUT_req.txt");
end
`define clk_step #14;
always #7 clk=~clk;
//////////////////////////////////////////////////////////
///////////initial actural test : arbiter_for_OUT_req ////
initial begin
`clk_step
$display("TEST BEGIN.......");
$fdisplay(log_file,"TEST BEGIN.......");
rst=1\'b0;
`clk_step
///////////////////////////////////////////////////////////////
//First case: v_ic_req ,v_dc_req and v_mem_req are all valid///
$display("First case: v_ic_req ,v_dc_req and v_mem_req are all valid");
$fdisplay(log_file,"First case: v_ic_req ,v_dc_req and v_mem_req are all valid");
$display("First try");
$fdisplay(log_file,"First try");
OUT_req_rdy=1\'b0;
v_ic_req=1\'b1;
v_dc_req=1\'b1;
v_mem_req=1\'b1;
ic_req_ctrl=2\'b01;
dc_req_ctrl=2\'b01;
mem_req_ctrl=2\'b01;
cmp_outputs(1\'b0, //exp_ack_OUT_req;
1\'b0, //exp_ack_ic_req;
1\'b0, //exp_ack_dc_req;
1\'b0, //exp_ack_mem_req;
3\'b000 //exp_select;
);
`clk_step
$display("2nd try : ic should win! ");
$fdisplay(log_file,"2nd try : ic should win!");
OUT_req_rdy=1\'b1;
v_ic_req=1\'b1;
v_dc_req=1\'b1;
v_mem_req=1\'b1;
ic_req_ctrl=2\'b01;
dc_req_ctrl=2\'b01;
mem_req_ctrl=2\'b01;
cmp_outputs(1\'b1, //exp_ack_OUT_req;
1\'b1, //exp_ack_ic_req;
1\'b0, //exp_ack_dc_req;
1\'b0, //exp_ack_mem_req;
3\'b100 //exp_select;
);
`clk_step
$display("3rd try : ic should win! ");
$fdisplay(log_file,"3rd try : ic should win!");
OUT_req_rdy=1\'b1;
v_ic_req=1\'b1;
v_dc_req=1\'b1;
v_mem_req=1\'b1;
ic_req_ctrl=2\'b10;
dc_req_ctrl=2\'b01;
mem_req_ctrl=2\'b01;
cmp_outputs(1\'b1, //exp_ack_OUT_req;
1\'b1, //exp_ack_ic_req;
1\'b0, //exp_ack_dc_req;
1\'b0, //exp_ack_mem_req;
3\'b100 //exp_select;
);
`clk_step
$display("last try : ic should finish ! ");
$fdisplay(log_file,"last try : ic should finish !");
OUT_req_rdy=1\'b1;
v_ic_req=1\'b1;
v_dc_req=1\'b1;
v_mem_req=1\'b1;
ic_req_ctrl=2\'b11;
dc_req_ctrl=2\'b01;
mem_req_ctrl=2\'b01;
cmp_outputs(1\'b1, //exp_ack_OUT_req;
1\'b1, //exp_ack_ic_req;
1\'b0, //exp_ack_dc_req;
1\'b0, //exp_ack_mem_req;
3\'b100 //exp_select;
);
/* `clk_step
$display("last try :just test if ic has finish and mem win ! ");
$fdisplay(log_file,"last try : if ic has finish and mem win !");
OUT_req_rdy=1\'b1;
v_ic_req=1\'b0;
v_dc_req=1\'b1;
v_mem_req=1\'b1;
ic_req_ctrl=2\'b00;
dc_req_ctrl=2\'b01;
mem_req_ctrl=2\'b01;
cmp_outputs(1\'b1, //exp_ack_OUT_req;
1\'b0, //exp_ack_ic_req;
1\'b0, //exp_ack_dc_req;
1\'b1, //exp_ack_mem_req;
3\'b001 //exp_select;
);
*/
/////////////////////////////////////////////////////////////////
///////2nd case :both mem and dc are valid! and mem will win!////
/////////////////////////////////////////////////////////////////
rst=1\'b1;
#7;
rst=1\'b0;
#7;
//clk_step
$display("2nd case: v_dc_req and v_mem_req are valid");
$fdisplay(log_file,"2nd case: v_dc_req and v_mem_req are valid");
$display("First try");
$fdisplay(log_file,"First try");
OUT_req_rdy=1\'b1;
v_ic_req=1\'b0;
v_dc_req=1\'b1;
v_mem_req=1\'b1;
ic_req_ctrl=2\'b00;
dc_req_ctrl=2\'b01;
mem_req_ctrl=2\'b01;
cmp_outputs(1\'b1, //exp_ack_OUT_req;
1\'b0, //exp_ack_ic_req;
1\'b0, //exp_ack_dc_req;
1\'b1, //exp_ack_mem_req;
3\'b001 //exp_select;
);
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
OUT_req_rdy=1\'b1;
v_ic_req=1\'b0;
v_dc_req=1\'b1;
v_mem_req=1\'b1;
ic_req_ctrl=2\'b00;
dc_req_ctrl=2\'b01;
mem_req_ctrl=2\'b10;
cmp_outputs(1\'b1, //exp_ack_OUT_req;
1\'b0, //exp_ack_ic_req;
1\'b0, //exp_ack_dc_req;
1\'b1, //exp_ack_mem_req;
3\'b001 //exp_select;
);
`clk_step
$display("3rd try");
$fdisplay(log_file,"3rd try");
OUT_req_rdy=1\'b1;
v_ic_req=1\'b0;
v_dc_req=1\'b1;
v_mem_req=1\'b1;
ic_req_ctrl=2\'b00;
dc_req_ctrl=2\'b01;
mem_req_ctrl=2\'b10;
cmp_outputs(1\'b1, //exp_ack_OUT_req;
1\'b0, //exp_ack_ic_req;
1\'b0, //exp_ack_dc_req;
1\'b1, //exp_ack_mem_req;
3\'b001 //exp_select;
);
`clk_step
$display("last try");
$fdisplay(log_file,"last try");
OUT_req_rdy=1\'b1;
v_ic_req=1\'b0;
v_dc_req=1\'b1;
v_mem_req=1\'b1;
ic_req_ctrl=2\'b00;
dc_req_ctrl=2\'b01;
mem_req_ctrl=2\'b11;
cmp_outputs(1\'b1, //exp_ack_OUT_req;
1\'b0, //exp_ack_ic_req;
1\'b0, //exp_ack_dc_req;
1\'b1, //exp_ack_mem_req;
3\'b001 //exp_select;
);
/////////////////////////////////////////////////////////////////////////////
////3rd case: both mem and dc are valid but it\'s dc\'s turn to transfer msg///
`clk_step
$display("3rd case: both mem and dc are valid but it\'s dc\'s turn to transfer msg\
also test for last try error");
$fdisplay(log_file,"3rd case: both mem and dc are valid but it\'s dc\'s turn to transfer msg\
also test for last try error");
$display("First try");
$fdisplay(log_file,"First try");
OUT_req_rdy=1\'b1;
v_ic_req=1\'b0;
v_dc_req=1\'b1;
v_mem_req=1\'b1;
ic_req_ctrl=2\'b00;
dc_req_ctrl=2\'b01;
mem_req_ctrl=2\'b01;
cmp_outputs(1\'b1, //exp_ack_OUT_req;
1\'b0, //exp_ack_ic_req;
1\'b1, //exp_ack_dc_req;
1\'b0, //exp_ack_mem_req;
3\'b010 //exp_select;
);
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
OUT_req_rdy=1\'b1;
v_ic_req=1\'b0;
v_dc_req=1\'b1;
v_mem_req=1\'b1;
ic_req_ctrl=2\'b00;
dc_req_ctrl=2\'b10;
mem_req_ctrl=2\'b01;
cmp_outputs(1\'b1, //exp_ack_OUT_req;
1\'b0, //exp_ack_ic_req;
1\'b1, //exp_ack_dc_req;
1\'b0, //exp_ack_mem_req;
3\'b010 //exp_select;
);
`clk_step
$display("3rd try");
$fdisplay(log_file,"3rd try");
OUT_req_rdy=1\'b1;
v_ic_req=1\'b0;
v_dc_req=1\'b1;
v_mem_req=1\'b1;
ic_req_ctrl=2\'b00;
dc_req_ctrl=2\'b10;
mem_req_ctrl=2\'b01;
cmp_outputs(1\'b1, //exp_ack_OUT_req;
1\'b0, //exp_ack_ic_req;
1\'b1, //exp_ack_dc_req;
1\'b0, //exp_ack_mem_req;
3\'b010 //exp_select;
);
// req fifo is not ready
`clk_step
$display("last try");
$fdisplay(log_file,"last try");
OUT_req_rdy=1\'b0;
v_ic_req=1\'b0;
v_dc_req=1\'b1;
v_mem_req=1\'b1;
ic_req_ctrl=2\'b00;
dc_req_ctrl=2\'b11;
mem_req_ctrl=2\'b01;
cmp_outputs(1\'b0, //exp_ack_OUT_req;
1\'b0, //exp_ack_ic_req;
1\'b0, //exp_ack_dc_req;
1\'b0, //exp_ack_mem_req;
3\'b000 //exp_select;
);
`clk_step
$display("last try");
$fdisplay(log_file,"last try");
OUT_req_rdy=1\'b1;
v_ic_req=1\'b0;
v_dc_req=1\'b1;
v_mem_req=1\'b1;
ic_req_ctrl=2\'b00;
dc_req_ctrl=2\'b11;
mem_req_ctrl=2\'b01;
cmp_outputs(1\'b1, //exp_ack_OUT_req;
1\'b0, //exp_ack_ic_req;
1\'b1, //exp_ack_dc_req;
1\'b0, //exp_ack_mem_req;
3\'b010 //exp_select;
);
///////////////////////////////////////////////////////////////
////4th case : only dc is valid! /////
`clk_step
$display("4th case : only dc is valid!\
also test for last try error");
$fdisplay(log_file,"4th case : only dc is valid!\
also test for last try error");
$display("First try");
$fdisplay(log_file,"First try");
OUT_req_rdy=1\'b1;
v_ic_req=1\'b0;
v_dc_req=1\'b1;
v_mem_req=1\'b0;
ic_req_ctrl=2\'b00;
dc_req_ctrl=2\'b01;
mem_req_ctrl=2\'b00;
cmp_outputs(1\'b1, //exp_ack_OUT_req;
1\'b0, //exp_ack_ic_req;
1\'b1, //exp_ack_dc_req;
1\'b0, //exp_ack_mem_req;
3\'b010 //exp_select;
);
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
OUT_req_rdy=1\'b1;
v_ic_req=1\'b0;
v_dc_req=1\'b1;
v_mem_req=1\'b0;
ic_req_ctrl=2\'b00;
dc_req_ctrl=2\'b10;
mem_req_ctrl=2\'b01;
cmp_outputs(1\'b1, //exp_ack_OUT_req;
1\'b0, //exp_ack_ic_req;
1\'b1, //exp_ack_dc_req;
1\'b0, //exp_ack_mem_req;
3\'b010 //exp_select;
);
//req fifo is not ready
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
OUT_req_rdy=1\'b0;
v_ic_req=1\'b0;
v_dc_req=1\'b1;
v_mem_req=1\'b0;
ic_req_ctrl=2\'b00;
dc_req_ctrl=2\'b10;
mem_req_ctrl=2\'b01;
cmp_outputs(1\'b0, //exp_ack_OUT_req;
1\'b0, //exp_ack_ic_req;
1\'b0, //exp_ack_dc_req;
1\'b0, //exp_ack_mem_req;
3\'b000 //exp_select;
);
`clk_step
$display("last try");
$fdisplay(log_file,"last try");
OUT_req_rdy=1\'b1;
v_ic_req=1\'b0;
v_dc_req=1\'b1;
v_mem_req=1\'b0;
ic_req_ctrl=2\'b00;
dc_req_ctrl=2\'b11;
mem_req_ctrl=2\'b01;
cmp_outputs(1\'b1, //exp_ack_OUT_req;
1\'b0, //exp_ack_ic_req;
1\'b1, //exp_ack_dc_req;
1\'b0, //exp_ack_mem_req;
3\'b010 //exp_select;
);
////////////////////////////////////////////////////////////
////5th case: only mem is valid !///////////////////////////
`clk_step
$display("1st try");
$fdisplay(log_file,"1st try");
OUT_req_rdy=1\'b1; //doesn\'t matter
v_ic_req=1\'b0;
v_dc_req=1\'b0;
v_mem_req=1\'b1;
ic_req_ctrl=2\'b01;
dc_req_ctrl=2\'b01;
mem_req_ctrl=2\'b01;
cmp_outputs(1\'b1, //exp_ack_OUT_req;
1\'b0, //exp_ack_ic_req;
1\'b0, //exp_ack_dc_req;
1\'b1, //exp_ack_mem_req;
3\'b001 //exp_select;
);
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
OUT_req_rdy=1\'b1; //doesn\'t matter
v_ic_req=1\'b0;
v_dc_req=1\'b0;
v_mem_req=1\'b1;
ic_req_ctrl=2\'b01;
dc_req_ctrl=2\'b01;
mem_req_ctrl=2\'b10;
cmp_outputs(1\'b1, //exp_ack_OUT_req;
1\'b0, //exp_ack_ic_req;
1\'b0, //exp_ack_dc_req;
1\'b1, //exp_ack_mem_req;
3\'b001 //exp_select;
);
/// req fifo is not ready!
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
OUT_req_rdy=1\'b0; //doesn\'t matter
v_ic_req=1\'b0;
v_dc_req=1\'b0;
v_mem_req=1\'b1;
ic_req_ctrl=2\'b01;
dc_req_ctrl=2\'b01;
mem_req_ctrl=2\'b10;
cmp_outputs(1\'b0, //exp_ack_OUT_req;
1\'b0, //exp_ack_ic_req;
1\'b0, //exp_ack_dc_req;
1\'b0, //exp_ack_mem_req;
3\'b000 //exp_select;
);
`clk_step
$display("3rd try");
$fdisplay(log_file,"3rd try");
OUT_req_rdy=1\'b1; //doesn\'t matter
v_ic_req=1\'b0;
v_dc_req=1\'b0;
v_mem_req=1\'b1;
ic_req_ctrl=2\'b01;
dc_req_ctrl=2\'b01;
mem_req_ctrl=2\'b11;
cmp_outputs(1\'b1, //exp_ack_OUT_req;
1\'b0, //exp_ack_ic_req;
1\'b0, //exp_ack_dc_req;
1\'b1, //exp_ack_mem_req;
3\'b001 //exp_select;
);
/////////////////////////////////////////////////
////both mem and ic are valid ///////////////////
`clk_step
$display("1st try");
$fdisplay(log_file,"1st try");
OUT_req_rdy=1\'b1; //doesn\'t matter
v_ic_req=1\'b1;
v_dc_req=1\'b0;
v_mem_req=1\'b1;
ic_req_ctrl=2\'b01;
dc_req_ctrl=2\'b01;
mem_req_ctrl=2\'b01;
cmp_outputs(1\'b1, //exp_ack_OUT_req;
1\'b1, //exp_ack_ic_req;
1\'b0, //exp_ack_dc_req;
1\'b0, //exp_ack_mem_req;
3\'b100 //exp_select;
);
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
OUT_req_rdy=1\'b1; //doesn\'t matter
v_ic_req=1\'b1;
v_dc_req=1\'b0;
v_mem_req=1\'b1;
ic_req_ctrl=2\'b10;
dc_req_ctrl=2\'b01;
mem_req_ctrl=2\'b01;
cmp_outputs(1\'b1, //exp_ack_OUT_req;
1\'b1, //exp_ack_ic_req;
1\'b0, //exp_ack_dc_req;
1\'b0, //exp_ack_mem_req;
3\'b100 //exp_select;
);
/// req fifo is not ready!
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
OUT_req_rdy=1\'b0; //doesn\'t matter
v_ic_req=1\'b1;
v_dc_req=1\'b0;
v_mem_req=1\'b1;
ic_req_ctrl=2\'b10;
dc_req_ctrl=2\'b01;
mem_req_ctrl=2\'b01;
cmp_outputs(1\'b0, //exp_ack_OUT_req;
1\'b0, //exp_ack_ic_req;
1\'b0, //exp_ack_dc_req;
1\'b0, //exp_ack_mem_req;
3\'b000 //exp_select;
);
`clk_step
$display("3rd try");
$fdisplay(log_file,"3rd try");
OUT_req_rdy=1\'b1; //doesn\'t matter
v_ic_req=1\'b1;
v_dc_req=1\'b0;
v_mem_req=1\'b1;
ic_req_ctrl=2\'b11;
dc_req_ctrl=2\'b01;
mem_req_ctrl=2\'b01;
cmp_outputs(1\'b1, //exp_ack_OUT_req;
1\'b1, //exp_ack_ic_req;
1\'b0, //exp_ack_dc_req;
1\'b0, //exp_ack_mem_req;
3\'b100 //exp_select;
);
`clk_step
$display("FINISH TEST!");
$fdisplay(log_file,"FINISH TEST!");
$stop;
end
endmodule
|
// date:2016/8/1
// engineer:ZhaiShaoMin
// module name:BTB testbench module used to cache recent target of jumps and branches
// module implementation(also useful for testbench code):
// case 0: all of the btb entries should be invalid, if system is just powered on, rst is set to 1
// case 1: except for rst==1, btb should only be updated by inst decode stage, either only update btb_type or btb_target, or both
// case 2: btb should only be read in inst fetch stage, which can generate btb target or type.
// here I just want to figure out if btb has a corret function,
// especially read behavior: btb data output right away, or after a cycle when pc is ready.
////////////////////////////////////////////////////////////////////
/////////////////////////////TEST PLAN//////////////////////////////
//following is the test enviorment code from book <<digital design and computer architecture>>
/* RECURSIVE PROCEDURE CALL
0x90 factorial: addi $sp, $sp, -8 # make room on stack
0x94 sw $a0, 4($sp) # store $a0
0x98 sw $ra, 0($sp) # store $ra
0x9C addi $t0, $0, 2 # $t0 = 2
0xA0 slt $t0, $a0, $t0 # a <= 1 ?
0xA4 beq $t0, $0, else # no: goto else
0xA8 addi $v0, $0, 1 # yes: return 1
0xAC addi $sp, $sp, 8 # restore $sp
0xB0 jr $ra # return
0xB4 else: addi $a0, $a0, -1 # n = n - 1
0xB8 jal factorial # recursive call
0xBC lw $ra, 0($sp) # restore $ra
0xC0 lw $a0, 4($sp) # restore $a0
0xC4 addi $sp, $sp, 8 # restore $sp
0xC8 mul $v0, $a0, $v0 # n * factorial (n-1)
0xCC jr $ra # return
Now I assume n=3, then I figure out the inst stream is following pattern
-----> if there are some behaviors related to BTB ,they will be underline in bracket!
////first time/////
10 jal from OS,
40 jal from main ,
90\xef\xbc\x8c 94, 98, 9c, a0,
a4 beq(branch taken, write target and br_type to BTB),
b4,
b8 jal(branch taken, write jal_type and its target to BTB),
90,94,98,9c,a0,
a4 beq(branch taken, predict target via BTB and get right target pc),
b4,
b8 jal(branch taken, get target pc from BTB),
90,94,98,9c,a0,
a4 beq(branch not taken, but may be predicted to take),
a8,ac,
b0 jr(jump taken, not recorded in BTB yet, so we need to update btb in decode stage),
bc, c0, c4, c8,
cc jr(jump taken, not recorded in BTB yet, so we need to update btb in decode stage),
bc, c0, c4, c8,
cc jr(jump taken, get no target pc from RAS).//return to main 44
...
54 jr(jump to OS) 14
////second time, and assume no other branch inst affect the above entries in BTB //////
10 jal from OS (branch taken, get right target pc from btb and also push ret_pc to RAS),
40 jal from main (branch taken, get right target pc from btb and also push ret_pc to RAS),
90\xef\xbc\x8c 94, 98, 9c, a0,
a4 beq(branch taken, predict target via BTB and get right target pc),
b4,
b8 jal(branch taken, get right target pc from btb and also push ret_pc to RAS),
90,94,98,9c,a0,
a4 beq(branch taken, predict target via BTB and get right target pc),
b4,
b8 jal(branch taken, get target pc from BTB and also push ret_pc to RAS),
90,94,98,9c,a0,
a4 beq(branch not taken, but may be predicted to take),
a8,ac,
b0 jr(jump taken, recorded in BTB yet, so we can find it is ret, so get target from RAS),
bc, c0, c4, c8,
cc jr(jump taken, recorded in BTB yet, so we can find it is ret, so get target from RAS),
bc, c0, c4, c8,
cc jr(jump taken, recorded in BTB yet, so we can find it is ret, so get target from RAS).//return to main 44
...
54 jr(jump to OS, recorded in BTB yet, so we can find it is ret, so get target from RAS) 14
*/
`timescale 1ns/1ps
`include "define.v"
module tb_core_btb();
//input
reg clk;
reg rst;
reg [31:0] id_pc;
reg [31:0] if_pc;
reg [31:0] btb_target_in;
reg update_btb_target;
reg update_btb_tag;
reg [1:0] btb_type_in;
reg PHT_pred_taken;
//output
wire btb_v;
wire [31:0] btb_target_out;
wire [1:0] btb_type_out;
wire en_btb_pred;
core_btb duv(//input
.clk(clk),
.rst(rst),
.if_pc(if_pc),
\t\t\t\t\t\t .id_pc(id_pc),
.update_btb_tag(update_btb_tag),
.update_btb_target(update_btb_target),
.btb_target_in(btb_target_in),
.btb_type_in(btb_type_in),
.PHT_pred_taken(PHT_pred_taken),
//output
.btb_type_out(btb_type_out),
.btb_target_out(btb_target_out),
.btb_v(btb_v),
.en_btb_pred(en_btb_pred) // only valid when both btb_v and PHT_pred_taken valid are both 1
);
\tinteger log_file;
\t\t\t\t\t\t
\tinitial begin
\t
\t clk=1\'b0;
\t rst=1\'b1;
\t if_pc=32\'h40001110;
\t id_pc=32\'h40001100;
btb_target_in=32\'h40002220;
update_btb_target=1\'b0;
update_btb_tag=1\'b0;
btb_type_in=2\'b00;
PHT_pred_taken=1\'b0;
\t log_file=$fopen("tb_core_btb.txt");
\t end
\t
\t
\t always #5 clk=~clk;
`define clk_step #8;
\t
\tinteger i=0;
integer j=0;
\tinitial begin
\t
\t////////////////test begin///////////////////
\t
\t// case 0: all of the btb entries should be invalid, if system is just powered on, rst is set to 1
\t
\trst=1\'b1;
\t
\t#2;
\t`clk_step
\t
\trst=1\'b0;
\t/*
\trepeat(128)
\t begin
\t
\t $display("(%t)btb entry[%d] should be %b", $time, i, duv.btb_entry_valid[i]);
\t $fdisplay(log_file,"(%t)btb entry[%d] should be %b", $time, i, duv.btb_entry_valid[i]);
\t `clk_step
\t i=i+1;
\t end
\t*/
\t//case 1: except for rst==1, btb should only be updated by inst decode stage, either only update btb_type or update btb_target, or both
\t#2;
\t`clk_step
\t
\trst=1\'b0;
\t
\t
\trepeat(16) begin
\t
\t if_pc=i;
\t\t PHT_pred_taken=0;
\t\t $display("(%t) btb_v: %b; btb_type_out:%b, btb_target_out:%h", $time, btb_v, btb_type_out, btb_target_out);
\t $fdisplay(log_file,"(%t)btb_v: %b; btb_type_out:%b, btb_target_out:%h ", $time, btb_v, btb_type_out, btb_target_out);
\t\t
\t\t #2;
\t\t `clk_step
\t i=i+8;
\t\t
\t\t end
\t\t
//10 jal from OS,
if_pc=32\'h40001010;
\t\t\t id_pc=32\'h4000100c;
\t\t\t update_btb_tag=0;
update_btb_target=0;
btb_type_in=`jal_type;
btb_target_in=32\'h40001010;
#2;
\t\t\t $display("(%t) btb_v: %b; btb_type_out:%b, btb_target_out:%h", $time, btb_v, btb_type_out, btb_target_out);
\t $fdisplay(log_file,"(%t)btb_v: %b; btb_type_out:%b, btb_target_out:%h ", $time, btb_v, btb_type_out, btb_target_out);
\t\t\t `clk_step
//we miss jal target ,decode stage updateing the target into btb
if_pc=32\'h40001014;
\t\t\t id_pc=32\'h40101010;
\t\t\t update_btb_tag=1;
update_btb_target=1;
btb_type_in=`jal_type;
btb_target_in=32\'h40001240;
#2;
\t\t\t $display("writing btb now");
\t\t\t $fdisplay(log_file,"writing btb now");
\t\t\t `clk_step
//4c jal from main ,
\t\t\t if_pc=32\'h40001240;
\t\t\t id_pc=32\'h40101014;
\t\t\t update_btb_tag=0;
update_btb_target=0;
btb_type_in=`jal_type;
btb_target_in=32\'h40001018;
\t\t\t #2;
\t\t\t $display("(%t) btb_v: %b; btb_type_out:%b, btb_target_out:%h", $time, btb_v, btb_type_out, btb_target_out);
\t $fdisplay(log_file,"(%t)btb_v: %b; btb_type_out:%b, btb_target_out:%h ", $time, btb_v, btb_type_out, btb_target_out);
\t\t\t `clk_step
\t\t\t
\t\t\t if_pc=32\'h40001244;
\t\t\t id_pc=32\'h40101240;
\t\t\t #2;
\t\t\t $display("(%t) btb_v: %b; btb_type_out:%b, btb_target_out:%h", $time, btb_v, btb_type_out, btb_target_out);
\t $fdisplay(log_file,"(%t)btb_v: %b; btb_type_out:%b, btb_target_out:%h ", $time, btb_v, btb_type_out, btb_target_out);
\t\t\t `clk_step
\t\t\t
\t\t\t if_pc=32\'h40001248;
\t\t\t id_pc=32\'h40101244;
\t\t\t #2;
\t\t\t $display("(%t) btb_v: %b; btb_type_out:%b, btb_target_out:%h", $time, btb_v, btb_type_out, btb_target_out);
\t $fdisplay(log_file,"(%t)btb_v: %b; btb_type_out:%b, btb_target_out:%h ", $time, btb_v, btb_type_out, btb_target_out);
\t\t\t `clk_step
\t\t\t
\t\t\t //this inst is jal from main
\t\t\t if_pc=32\'h4000124c;
\t\t\t id_pc=32\'h40101248;
\t\t\t #2;
\t\t\t $display("(%t) btb_v: %b; btb_type_out:%b, btb_target_out:%h", $time, btb_v, btb_type_out, btb_target_out);
\t $fdisplay(log_file,"(%t)btb_v: %b; btb_type_out:%b, btb_target_out:%h ", $time, btb_v, btb_type_out, btb_target_out);
\t\t\t `clk_step
\t\t\t //we can find target from btb, so we have to go ahead
\t\t\t if_pc=32\'h40001250;
\t\t\t id_pc=32\'h4000124c;
\t\t\t //decode find it is a jal, so need to record it in the btb
\t\t\t update_btb_tag=1;
update_btb_target=1;
btb_type_in=`jal_type;
btb_target_in=32\'h40001290;
#2;
$display("writing btb now");
$fdisplay(log_file,"writing btb now");
$display("(%t) btb_v: %b; btb_type_out:%b, btb_target_out:%h", $time, btb_v, btb_type_out, btb_target_out);
\t $fdisplay(log_file,"(%t)btb_v: %b; btb_type_out:%b, btb_target_out:%h ", $time, btb_v, btb_type_out, btb_target_out);
\t `clk_step
//90\xef\xbc\x8c 94, 98, 9c, a0,
if_pc=32\'h40001290;
\t\t\t id_pc=32\'h40101250;
\t\t\t update_btb_tag=0;
update_btb_target=0;
btb_type_in=`jal_type;
btb_target_in=32\'h40001250;
\t\t\t #2;
\t\t\t $display("(%t) btb_v: %b; btb_type_out:%b, btb_target_out:%h", $time, btb_v, btb_type_out, btb_target_out);
\t $fdisplay(log_file,"(%t)btb_v: %b; btb_type_out:%b, btb_target_out:%h ", $time, btb_v, btb_type_out, btb_target_out);
\t\t\t `clk_step
\t\t\t
\t\t\t if_pc=32\'h40001294;
\t\t\t id_pc=32\'h40101290;
\t\t\t
\t\t\t // `clk_step//98
\t\t\t // `clk_step//9c
\t\t\t
\t\t\t// `clk_step
\t\t\t
\t\t\t if_pc=32\'h400012a0;
\t\t\t id_pc=32\'h40101250;
\t\t\t #2;
\t\t\t `clk_step
\t\t\t
\t\t\t
//a4 beq(branch taken, write target and br_type to BTB),
if_pc=32\'h400012a4;
\t\t\t id_pc=32\'h401012a0;
\t\t\t update_btb_tag=0;
update_btb_target=0;
btb_type_in=`br_type;
btb_target_in=32\'h400012a4;
\t\t\t #2;
\t\t\t $display("(%t) btb_v: %b; btb_type_out:%b, btb_target_out:%h", $time, btb_v, btb_type_out, btb_target_out);
\t $fdisplay(log_file,"(%t)btb_v: %b; btb_type_out:%b, btb_target_out:%h ", $time, btb_v, btb_type_out, btb_target_out);
\t\t\t `clk_step
\t\t\t
\t\t\t if_pc=32\'h400012a8;
\t\t\t id_pc=32\'h401012a4;
\t\t\t update_btb_tag=1;
update_btb_target=1;
btb_type_in=`br_type;
btb_target_in=32\'h400012b4;
#2;
$display("writing btb now");
$fdisplay(log_file,"writing btb now");
\t\t\t $display("(%t) btb_v: %b; btb_type_out:%b, btb_target_out:%h", $time, btb_v, btb_type_out, btb_target_out);
\t $fdisplay(log_file,"(%t)btb_v: %b; btb_type_out:%b, btb_target_out:%h ", $time, btb_v, btb_type_out, btb_target_out);
\t\t\t `clk_step
//b4,
if_pc=32\'h400012b4;
\t\t\t id_pc=32\'h401012a8;
\t\t\t update_btb_tag=0;
update_btb_target=0;
btb_type_in=`jal_type;
btb_target_in=32\'h400012b4;
#2;
\t\t\t $display("(%t) btb_v: %b; btb_type_out:%b, btb_target_out:%h", $time, btb_v, btb_type_out, btb_target_out);
\t $fdisplay(log_file,"(%t)btb_v: %b; btb_type_out:%b, btb_target_out:%h ", $time, btb_v, btb_type_out, btb_target_out);
\t\t\t `clk_step
\t\t\t
//b8 jal(branch taken, write jal_type and its target to BTB),
if_pc=32\'h400012b8;
\t\t\t id_pc=32\'h401012b4;
\t\t\t update_btb_tag=0;
update_btb_target=0;
btb_type_in=`jal_type;
btb_target_in=32\'h400012b8;
\t\t\t
\t\t\t #2;
\t\t\t $display("(%t) btb_v: %b; btb_type_out:%b, btb_target_out:%h", $time, btb_v, btb_type_out, btb_target_out);
\t $fdisplay(log_file,"(%t)btb_v: %b; btb_type_out:%b, btb_target_out:%h ", $time, btb_v, btb_type_out, btb_target_out);
\t\t\t `clk_step
\t\t\t
\t\t\t if_pc=32\'h400012bc;
\t\t\t id_pc=32\'h401012b8;
\t\t\t update_btb_tag=1;
update_btb_target=1;
btb_type_in=`br_type;
btb_target_in=32\'h40001290;
\t\t\t #2;
\t\t\t $display("writing btb now");
\t\t\t $fdisplay(log_file,"writing btb now");
\t\t\t $display("(%t) btb_v: %b; btb_type_out:%b, btb_target_out:%h", $time, btb_v, btb_type_out, btb_target_out);
\t $fdisplay(log_file,"(%t)btb_v: %b; btb_type_out:%b, btb_target_out:%h ", $time, btb_v, btb_type_out, btb_target_out);
\t\t\t `clk_step
//90,94,98,9c,a0,
if_pc=32\'h40001290;
\t\t\t id_pc=32\'h401012bc;
\t\t\t update_btb_tag=0;
update_btb_target=0;
btb_type_in=`jal_type;
btb_target_in=32\'h400012b4;
\t\t\t #2;
\t\t\t `clk_step
\t\t\t// `clk_step
\t\t\t// `clk_step
\t\t\t// `clk_step
\t\t\t
\t\t\t if_pc=32\'h400012a0;
\t\t\t #2;
\t\t\t `clk_step
//a4 beq(branch taken, predict target via BTB and get right target pc),
if_pc=32\'h400012a4;
\t\t\t id_pc=32\'h401012a0;
\t\t\t update_btb_tag=0;
update_btb_target=0;
btb_type_in=`jal_type;
btb_target_in=32\'h400012a4;
\t\t\t #2;
\t\t\t $display("we should get target 32\'h400012b4 from btb");
\t\t\t $fdisplay(log_file,"we should get target 32\'h400012b4 from btb");
\t\t\t $display("(%t) btb_v: %b; btb_type_out:%b, btb_target_out:%h", $time, btb_v, btb_type_out, btb_target_out);
\t $fdisplay(log_file,"(%t)btb_v: %b; btb_type_out:%b, btb_target_out:%h ", $time, btb_v, btb_type_out, btb_target_out);
\t\t\t `clk_step
//b4\t\t\t
\t\t\t if_pc=32\'h400012b4;
\t\t\t id_pc=32\'h401012a4;
\t\t\t update_btb_tag=0;
update_btb_target=0;
btb_type_in=`jal_type;
btb_target_in=32\'h400012b8;
\t\t\t #2;
\t\t\t $display("(%t) btb_v: %b; btb_type_out:%b, btb_target_out:%h", $time, btb_v, btb_type_out, btb_target_out);
\t $fdisplay(log_file,"(%t)btb_v: %b; btb_type_out:%b, btb_target_out:%h ", $time, btb_v, btb_type_out, btb_target_out);
\t\t\t `clk_step
//b8 jal(branch taken, get target pc from BTB),
if_pc=32\'h400012b8;
\t\t\t id_pc=32\'h401012b4;
\t\t\t update_btb_tag=0;
update_btb_target=0;
btb_type_in=`jal_type;
btb_target_in=32\'h400012b8;
#2;
\t\t\t $display("we should get target 32\'h40001290 from btb");
\t\t\t $fdisplay(log_file,"we should get target 32\'h40001290 from btb");
\t\t\t $display("(%t) btb_v: %b; btb_type_out:%b, btb_target_out:%h", $time, btb_v, btb_type_out, btb_target_out);
\t $fdisplay(log_file,"(%t)btb_v: %b; btb_type_out:%b, btb_target_out:%h ", $time, btb_v, btb_type_out, btb_target_out);
\t\t\t `clk_step
//90,94,98,9c,a0,
if_pc=32\'h40001290;
\t\t\t id_pc=32\'h401012b8;
\t\t\t #2;
\t\t\t `clk_step
\t\t\t
\t\t\t if_pc=32\'h40001294;
\t\t\t id_pc=32\'h40101290;
\t\t//\t `clk_step
\t\t\t
\t\t\t if_pc=32\'h40001298;
\t\t\t id_pc=32\'h40101294;
\t\t//\t `clk_step
\t\t\t
\t\t\t
\t\t\t if_pc=32\'h4000129c;
\t\t\t id_pc=32\'h40101298;
\t//\t\t `clk_step
\t\t\t
\t\t\t if_pc=32\'h400012a0;
\t\t\t id_pc=32\'h4010129c;
\t\t\t #2;
\t\t\t `clk_step
\t\t\t
//a4 beq(branch not taken, but may be predicted to take),
if_pc=32\'h400012a4;
\t\t\t id_pc=32\'h401012a0;
\t\t\t #2;
\t\t\t $display("we should get target 32\'h400012b4 from btb");
\t\t\t $fdisplay(log_file,"we should get target 32\'h400012b4 from btb");
\t\t\t $display("(%t) btb_v: %b; btb_type_out:%b, btb_target_out:%h", $time, btb_v, btb_type_out, btb_target_out);
\t $fdisplay(log_file,"(%t)btb_v: %b; btb_type_out:%b, btb_target_out:%h ", $time, btb_v, btb_type_out, btb_target_out);
\t\t\t `clk_step
//a8,ac,
if_pc=32\'h400012a8;
\t\t\t id_pc=32\'h401012a4;
\t\t\t #2;
\t\t\t `clk_step
\t\t\t
\t\t\t if_pc=32\'h400012ac;
\t\t\t id_pc=32\'h401012a8;
\t\t\t #2;
\t\t\t `clk_step
//b0 jr(jump taken, not recorded in BTB yet, so we need to update btb in decode stage),
//bc, c0, c4, c8,
//cc jr(jump taken, not recorded in BTB yet, so we need to update btb in decode stage),
//bc, c0, c4, c8,
//cc jr(jump taken, get no target pc from RAS).//return to main 44
//54 jr(jump to OS) 14
////second time, and assume no other branch inst affect the above entries in BTB //////
//10 jal from OS (branch taken, get right target pc from btb and also push ret_pc to RAS),
if_pc=32\'h40001010;
\t\t\t id_pc=32\'h4000100c;
\t\t\t update_btb_tag=0;
update_btb_target=0;
btb_type_in=`jal_type;
btb_target_in=32\'h40001010;
#2;
\t\t\t $display("we should get target 32\'h40001240 from btb");
\t\t\t $fdisplay(log_file,"we should get target 32\'h40001240 from btb");
\t\t\t $display("(%t) btb_v: %b; btb_type_out:%b, btb_target_out:%h", $time, btb_v, btb_type_out, btb_target_out);
\t $fdisplay(log_file,"(%t)btb_v: %b; btb_type_out:%b, btb_target_out:%h ", $time, btb_v, btb_type_out, btb_target_out);
\t\t\t `clk_step
\t\t\t
//40 jal from main (branch taken, get right target pc from btb and also push ret_pc to RAS),
if_pc=32\'h40001240;
\t\t\t id_pc=32\'h40101014;
\t\t\t update_btb_tag=0;
update_btb_target=0;
btb_type_in=`jal_type;
btb_target_in=32\'h40001018;
\t\t\t #2;
\t\t\t `clk_step
\t\t\t #2;
\t\t\t `clk_step
\t\t\t #2;
\t\t\t `clk_step
\t\t\t
\t\t\t if_pc=32\'h4000124c;
\t\t\t id_pc=32\'h40101040;
\t\t\t #2;
\t\t\t $display("we should get target 32\'h40001290 from btb");
\t\t\t $fdisplay(log_file,"we should get target 32\'h40001290 from btb");
\t\t\t $display("(%t) btb_v: %b; btb_type_out:%b, btb_target_out:%h", $time, btb_v, btb_type_out, btb_target_out);
\t $fdisplay(log_file,"(%t)btb_v: %b; btb_type_out:%b, btb_target_out:%h ", $time, btb_v, btb_type_out, btb_target_out);
\t\t\t `clk_step
//90\xef\xbc\x8c 94, 98, 9c, a0,
if_pc=32\'h40001290;
\t\t\t id_pc=32\'h4010104c;
\t\t\t #2;
\t\t\t `clk_step
//a4 beq(branch taken, predict target via BTB and get right target pc),
if_pc=32\'h400012a4;
\t\t\t id_pc=32\'h401012a0;
\t\t\t #2;
\t\t\t $display("we should get target 32\'h400012b4 from btb");
\t\t\t $fdisplay(log_file,"we should get target 32\'h400012b4 from btb");
\t\t\t $display("(%t) btb_v: %b; btb_type_out:%b, btb_target_out:%h", $time, btb_v, btb_type_out, btb_target_out);
\t $fdisplay(log_file,"(%t)btb_v: %b; btb_type_out:%b, btb_target_out:%h ", $time, btb_v, btb_type_out, btb_target_out);
\t\t\t `clk_step
//b4,
if_pc=32\'h400012b4;
\t\t\t id_pc=32\'h401012a4;
\t\t\t #2;
\t\t\t `clk_step
//b8 jal(branch taken, get right target pc from btb and also push ret_pc to RAS),
if_pc=32\'h400012b8;
\t\t\t id_pc=32\'h401012b4;
\t\t\t update_btb_tag=0;
update_btb_target=0;
btb_type_in=`jal_type;
btb_target_in=32\'h400012b8;
#2;
\t\t\t $display("we should get target 32\'h40001290 from btb");
\t\t\t $fdisplay(log_file,"we should get target 32\'h40001290 from btb");
\t\t\t $display("(%t) btb_v: %b; btb_type_out:%b, btb_target_out:%h", $time, btb_v, btb_type_out, btb_target_out);
\t $fdisplay(log_file,"(%t)btb_v: %b; btb_type_out:%b, btb_target_out:%h ", $time, btb_v, btb_type_out, btb_target_out);
\t\t\t `clk_step
//90,94,98,9c,a0,
if_pc=32\'h40001290;
\t\t\t id_pc=32\'h401012b8;
\t\t\t update_btb_tag=0;
update_btb_target=0;
btb_type_in=`jal_type;
btb_target_in=32\'h400012b4;
\t\t\t #2;
\t\t\t `clk_step
\t\t\t
\t\t\t if_pc=32\'h40001294;
\t\t\t id_pc=32\'h40101290;
\t\t\t #2;
\t\t\t `clk_step
\t\t\t
\t\t\t if_pc=32\'h40001298;
\t\t\t id_pc=32\'h40101294;
\t\t\t #2;
\t\t\t `clk_step
\t\t\t
\t\t\t if_pc=32\'h4000129c;
\t\t\t id_pc=32\'h40101298;
\t\t\t #2;
\t\t\t `clk_step
\t\t\t
\t\t\t if_pc=32\'h400012a0;
\t\t\t id_pc=32\'h4010129c;
\t\t\t #2;
\t\t\t `clk_step
//a4 beq(branch taken, predict target via BTB and get right target pc),
if_pc=32\'h400012a4;
\t\t\t id_pc=32\'h401012a0;
\t\t\t update_btb_tag=0;
update_btb_target=0;
btb_type_in=`jal_type;
btb_target_in=32\'h400012a4;
#2;
\t\t\t $display("we should get target 32\'h400012b4 from btb");
\t\t\t $fdisplay(log_file,"we should get target 32\'h400012b4 from btb");
\t\t\t $display("(%t) btb_v: %b; btb_type_out:%b, btb_target_out:%h", $time, btb_v, btb_type_out, btb_target_out);
\t $fdisplay(log_file,"(%t)btb_v: %b; btb_type_out:%b, btb_target_out:%h ", $time, btb_v, btb_type_out, btb_target_out);
\t\t\t `clk_step
//b4,
if_pc=32\'h400012b4;
\t\t\t id_pc=32\'h401012a4;
\t\t\t update_btb_tag=0;
update_btb_target=0;
btb_type_in=`jal_type;
btb_target_in=32\'h400012b8;
\t\t\t #2;
\t\t\t `clk_step
//b8 jal(branch taken, get target pc from BTB and also push ret_pc to RAS),
if_pc=32\'h400012b8;
\t\t\t id_pc=32\'h401012b4;
\t\t\t update_btb_tag=0;
update_btb_target=0;
btb_type_in=`jal_type;
btb_target_in=32\'h400012b8;
#2;
\t\t\t $display("we should get target 32\'h40001290 from btb");
\t\t\t $fdisplay(log_file,"we should get target 32\'h40001290 from btb");
\t\t\t $display("(%t) btb_v: %b; btb_type_out:%b, btb_target_out:%h", $time, btb_v, btb_type_out, btb_target_out);
\t $fdisplay(log_file,"(%t)btb_v: %b; btb_type_out:%b, btb_target_out:%h ", $time, btb_v, btb_type_out, btb_target_out);
\t\t\t `clk_step
//90,94,98,9c,a0,
if_pc=32\'h40001290;
\t\t\t id_pc=32\'h401012b8;
\t\t\t update_btb_tag=0;
update_btb_target=0;
btb_type_in=`jal_type;
btb_target_in=32\'h400012b4;
\t\t\t #2;
\t\t\t `clk_step
\t\t\t
\t\t\t if_pc=32\'h40001294;
\t\t\t id_pc=32\'h40101290;
\t\t\t #2;
\t\t\t `clk_step
\t\t\t
\t\t\t if_pc=32\'h40001298;
\t\t\t id_pc=32\'h40101294;
\t\t\t #2;
\t\t\t `clk_step
\t\t\t
\t\t\t if_pc=32\'h4000129c;
\t\t\t id_pc=32\'h40101298;
\t\t\t #2;
\t\t\t `clk_step
\t\t\t
\t\t\t if_pc=32\'h400012a0;
\t\t\t id_pc=32\'h4010129c;
\t\t\t #2;
\t\t\t `clk_step
//a4 beq(branch not taken, but may be predicted to take),
if_pc=32\'h400012a4;
\t\t\t id_pc=32\'h401012a0;
\t\t\t #2;
\t\t\t $display("we should get target 32\'h400012b4 from btb");
\t\t\t $fdisplay(log_file,"we should get target 32\'h400012b4 from btb");
\t\t\t $display("(%t) btb_v: %b; btb_type_out:%b, btb_target_out:%h", $time, btb_v, btb_type_out, btb_target_out);
\t $fdisplay(log_file,"(%t)btb_v: %b; btb_type_out:%b, btb_target_out:%h ", $time, btb_v, btb_type_out, btb_target_out);
\t\t\t `clk_step
//a8,ac,
//b0 jr(jump taken, recorded in BTB yet, so we can find it is ret, so get target from RAS),
//bc, c0, c4, c8,
//cc jr(jump taken, recorded in BTB yet, so we can find it is ret, so get target from RAS),
//bc, c0, c4, c8,
//cc jr(jump taken, recorded in BTB yet, so we can find it is ret, so get target from RAS).//return to main 44
//54 jr(jump to OS, recorded in BTB yet, so we can find it is ret, so get target from RAS) 14
\t $stop;
end
endmodule
\t
|
/// date: 2016/8/10
/// engineer: ZhaiShaoMin
/// module name: tb_arbiter_4_deq
/// module function: decide which fifo among pass fifos and OUT_local fifos can
/// really deq flit,ctrl and next_node infos;
`timescale 1ns/1ps
module tb_arbiter_4_deq();
//input
reg clk;
reg rst;
reg pass_req_empty; //local node: pass req fifo is empty
reg pass_rep_empty; //local node: pass rep fifo is empty
reg OUT_local_req_empty; //local node: OUT_local req fifo is empty
reg OUT_local_rep_empty; //local node: OUT_local rep fifo is empty
reg [1:0] pass_req_ctrl; //local node: tell whether current flit is over.
reg [1:0] pass_rep_ctrl; //local node: tell whether current flit is over.
reg [1:0] out_req_ctrl; //local node: tell whether current flit is over.
reg [1:0] out_rep_ctrl; //local node: tell whether current flit is over.
reg en_local_req; //IN_local_req_fifo of next node says I can receive a flit
reg en_local_rep; //IN_local_rep_fifo of next node says I can receive a flit
reg en_pass_req; //pass req fifo of next node says i can receive a flit now
reg en_pass_rep; //pass rep fifo of next node says i can receive a flit now
reg [3:0] used_slots_pass_req; //pass req fifo of next node says how many slots I have used ,avoiding deadlock
reg [3:0] used_slots_pass_rep; //pass rep fifo of next node says how many slots I have used ,avoiding deadlock
reg next_pass_req; //local node: flit in the head of pass req fifo says I am a flit to next node if it\'s 1;
reg next_pass_rep; //local node: flit in the head of pass rep fifo says I am a flit to next node if it\'s 1;
reg next_local_req; //local node: flit in the head of OUT_local req fifo says I am a flit to next node if it\'s 1;
reg next_local_rep; //local node: flit in the head of OUT_local rep fifo says I am a flit to next node if it\'s 1;
reg [1:0] OUT_rep_length_code;
//output
wire [3:0] select; // one-hot encode select 4\'b0001 : pass_rep
// 4\'b0010 : local_rep
// 4\'b0100 ? pass_req
// 4\'b1000 ? local_req
arbiter_4_deq duv(
//input
.clk(clk),
.rst(rst),
.pass_req_empty(pass_req_empty),
.pass_rep_empty(pass_rep_empty),
.OUT_local_req_empty(OUT_local_req_empty),
.OUT_local_rep_empty(OUT_local_rep_empty),
.pass_req_ctrl(pass_req_ctrl),
.pass_rep_ctrl(pass_rep_ctrl),
.out_req_ctrl(out_req_ctrl),
.out_rep_ctrl(out_rep_ctrl),
.OUT_rep_length_code(OUT_rep_length_code),
.en_local_req(en_local_req),
.en_local_rep(en_local_rep),
.en_pass_req(en_pass_req),
.en_pass_rep(en_pass_rep),
.used_slots_pass_req(used_slots_pass_req),
.used_slots_pass_rep(used_slots_pass_rep),
.next_pass_req(next_pass_req),
.next_pass_rep(next_pass_rep),
.next_local_req(next_local_req),
.next_local_rep(next_local_rep),
//output
.select(select)
);
integer log_file;
initial begin
clk = 1\'b0;
rst = 1\'b1;
pass_req_empty = 1\'b0;
pass_rep_empty = 1\'b0;
OUT_local_req_empty = 1\'b0;
OUT_local_rep_empty = 1\'b0;
pass_req_ctrl = 2\'b00;
pass_rep_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
out_rep_ctrl = 2\'b00;
OUT_rep_length_code = 2\'b00;
en_local_req = 1\'b0;
en_local_rep = 1\'b0;
en_pass_req = 1\'b0;
en_pass_rep = 1\'b0;
used_slots_pass_req = 4\'b0000;
used_slots_pass_rep = 4\'b0000;
next_pass_req = 1\'b0;
next_pass_rep = 1\'b0;
next_local_req = 1\'b0;
next_local_rep = 1\'b0;
log_file=$fopen("tb_arbiter_4_deq.txt");
end
`define clk_step #10;
always #5 clk=~clk;
////////////////////////////////////////////////////////////////////
////////////////////begin test//////////////////////////////////////
initial begin
#6;
rst=1\'b0;
#4;
//////////////////////////////////////////////////////////////////////////////////////
// the case order is pass_rep 11, pass_req 10, out_rep 01, out_req 00 to next node////
// ex: 11,10,01,00 means local fifos go to respective fifo of next node///////////////
////case 1: 11,10,01,00 ;
pass_req_empty = 1\'b0;
pass_rep_empty = 1\'b0;
OUT_local_req_empty = 1\'b0;
OUT_local_rep_empty = 1\'b0;
OUT_rep_length_code = 2\'b00;
en_local_req = 1\'b1;
en_local_rep = 1\'b1;
en_pass_req = 1\'b1;
en_pass_rep = 1\'b1;
next_pass_req = 1\'b0;
next_pass_rep = 1\'b0;
next_local_req = 1\'b1;
next_local_rep = 1\'b1;
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
pass_req_ctrl = 2\'b11;
pass_rep_ctrl = 2\'b11;
out_req_ctrl = 2\'b11;
out_rep_ctrl = 2\'b11;
`clk_step
pass_req_ctrl = 2\'b00;
pass_rep_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
out_rep_ctrl = 2\'b00;
////case 2: -11,10,11,00 ;
pass_req_empty = 1\'b0;
pass_rep_empty = 1\'b0;
OUT_local_req_empty = 1\'b0;
OUT_local_rep_empty = 1\'b0;
OUT_rep_length_code = 2\'b00;
en_local_req = 1\'b1;
en_local_rep = 1\'b1;
en_pass_req = 1\'b1;
en_pass_rep = 1\'b1;
next_pass_req = 1\'b0;
next_pass_rep = 1\'b0;
next_local_req = 1\'b1;
next_local_rep = 1\'b0;
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
pass_req_ctrl = 2\'b11;
pass_rep_ctrl = 2\'b11;
out_req_ctrl = 2\'b11;
out_rep_ctrl = 2\'b11;
`clk_step
pass_req_ctrl = 2\'b00;
pass_rep_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
out_rep_ctrl = 2\'b00;
////case 3: 01,10,11,00 ;
pass_req_empty = 1\'b0;
pass_rep_empty = 1\'b0;
OUT_local_req_empty = 1\'b0;
OUT_local_rep_empty = 1\'b0;
OUT_rep_length_code = 2\'b00;
en_local_req = 1\'b1;
en_local_rep = 1\'b1;
en_pass_req = 1\'b1;
en_pass_rep = 1\'b1;
next_pass_req = 1\'b0;
next_pass_rep = 1\'b1;
next_local_req = 1\'b1;
next_local_rep = 1\'b0;
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
pass_req_ctrl = 2\'b11;
pass_rep_ctrl = 2\'b11;
out_req_ctrl = 2\'b11;
out_rep_ctrl = 2\'b11;
`clk_step
pass_req_ctrl = 2\'b00;
pass_rep_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
out_rep_ctrl = 2\'b00;
\r
\r
////case 4: 01,-10,11,10 ;
pass_req_empty = 1\'b0;
pass_rep_empty = 1\'b0;
OUT_local_req_empty = 1\'b0;
OUT_local_rep_empty = 1\'b0;
OUT_rep_length_code = 2\'b00;
en_local_req = 1\'b1;
en_local_rep = 1\'b1;
en_pass_req = 1\'b1;
en_pass_rep = 1\'b1;
next_pass_req = 1\'b0;
next_pass_rep = 1\'b1;
next_local_req = 1\'b0;
next_local_rep = 1\'b0;
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
pass_req_ctrl = 2\'b11;
pass_rep_ctrl = 2\'b11;
out_req_ctrl = 2\'b11;
out_rep_ctrl = 2\'b11;
`clk_step
pass_req_ctrl = 2\'b00;
pass_rep_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
out_rep_ctrl = 2\'b00;
////case 5: 01,00,11,10 ;
/////////////////////////////////////////////////////////////////////////
//////// also useful to test length code cases for OUT rep fifo /////////
/// case 5.1 origin case
pass_req_empty = 1\'b0;
pass_rep_empty = 1\'b0;
OUT_local_req_empty = 1\'b0;
OUT_local_rep_empty = 1\'b0;
OUT_rep_length_code = 2\'b00;
en_local_req = 1\'b1;
en_local_rep = 1\'b1;
en_pass_req = 1\'b1;
en_pass_rep = 1\'b1;
next_pass_req = 1\'b1;
next_pass_rep = 1\'b1;
next_local_req = 1\'b0;
next_local_rep = 1\'b0;
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
pass_req_ctrl = 2\'b11;
pass_rep_ctrl = 2\'b11;
out_req_ctrl = 2\'b11;
out_rep_ctrl = 2\'b11;
`clk_step
pass_req_ctrl = 2\'b00;
pass_rep_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
out_rep_ctrl = 2\'b00;
/// case 5.2 length_code is 11 and used_slots_pass_rep = 4\'b0100;
// out_rep go is one
pass_req_empty = 1\'b0;
pass_rep_empty = 1\'b0;
OUT_local_req_empty = 1\'b0;
OUT_local_rep_empty = 1\'b0;
OUT_rep_length_code = 2\'b11;
used_slots_pass_rep = 4\'b0100;
en_local_req = 1\'b1;
en_local_rep = 1\'b1;
en_pass_req = 1\'b1;
en_pass_rep = 1\'b1;
next_pass_req = 1\'b1;
next_pass_rep = 1\'b1;
next_local_req = 1\'b0;
next_local_rep = 1\'b0;
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
pass_req_ctrl = 2\'b11;
pass_rep_ctrl = 2\'b11;
out_req_ctrl = 2\'b11;
out_rep_ctrl = 2\'b11;
`clk_step
pass_req_ctrl = 2\'b00;
pass_rep_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
out_rep_ctrl = 2\'b00;
/// case 5.3 length_code is 11 and used_slots_pass_rep = 4\'b0101;
// out_rep go is zero
pass_req_empty = 1\'b0;
pass_rep_empty = 1\'b0;
OUT_local_req_empty = 1\'b0;
OUT_local_rep_empty = 1\'b0;
OUT_rep_length_code = 2\'b11;
used_slots_pass_rep = 4\'b0101;
en_local_req = 1\'b1;
en_local_rep = 1\'b1;
en_pass_req = 1\'b1;
en_pass_rep = 1\'b1;
next_pass_req = 1\'b1;
next_pass_rep = 1\'b1;
next_local_req = 1\'b0;
next_local_rep = 1\'b0;
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
pass_req_ctrl = 2\'b11;
pass_rep_ctrl = 2\'b11;
out_req_ctrl = 2\'b11;
out_rep_ctrl = 2\'b11;
`clk_step
pass_req_ctrl = 2\'b00;
pass_rep_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
out_rep_ctrl = 2\'b00;
/// case 5.4 length_code is 10 and used_slots_pass_rep = 4\'b0110;
// out_rep go is one
pass_req_empty = 1\'b0;
pass_rep_empty = 1\'b0;
OUT_local_req_empty = 1\'b0;
OUT_local_rep_empty = 1\'b0;
OUT_rep_length_code = 2\'b10;
used_slots_pass_rep = 4\'b0110;
en_local_req = 1\'b1;
en_local_rep = 1\'b1;
en_pass_req = 1\'b1;
en_pass_rep = 1\'b1;
next_pass_req = 1\'b1;
next_pass_rep = 1\'b1;
next_local_req = 1\'b0;
next_local_rep = 1\'b0;
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
pass_req_ctrl = 2\'b11;
pass_rep_ctrl = 2\'b11;
out_req_ctrl = 2\'b11;
out_rep_ctrl = 2\'b11;
`clk_step
pass_req_ctrl = 2\'b00;
pass_rep_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
out_rep_ctrl = 2\'b00;
/// case 5.5 length_code is 10 and used_slots_pass_rep = 4\'b0111;
// out_rep go is zero
pass_req_empty = 1\'b0;
pass_rep_empty = 1\'b0;
OUT_local_req_empty = 1\'b0;
OUT_local_rep_empty = 1\'b0;
OUT_rep_length_code = 2\'b10;
used_slots_pass_rep = 4\'b0111;
en_local_req = 1\'b1;
en_local_rep = 1\'b1;
en_pass_req = 1\'b1;
en_pass_rep = 1\'b1;
next_pass_req = 1\'b1;
next_pass_rep = 1\'b1;
next_local_req = 1\'b0;
next_local_rep = 1\'b0;
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
pass_req_ctrl = 2\'b11;
pass_rep_ctrl = 2\'b11;
out_req_ctrl = 2\'b11;
out_rep_ctrl = 2\'b11;
`clk_step
pass_req_ctrl = 2\'b00;
pass_rep_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
out_rep_ctrl = 2\'b00;
/// case 5.6 length_code is 01 and used_slots_pass_rep = 4\'b1100;
// out_rep go is one
pass_req_empty = 1\'b0;
pass_rep_empty = 1\'b0;
OUT_local_req_empty = 1\'b0;
OUT_local_rep_empty = 1\'b0;
OUT_rep_length_code = 2\'b01;
used_slots_pass_rep = 4\'b1100;
en_local_req = 1\'b1;
en_local_rep = 1\'b1;
en_pass_req = 1\'b1;
en_pass_rep = 1\'b1;
next_pass_req = 1\'b1;
next_pass_rep = 1\'b1;
next_local_req = 1\'b0;
next_local_rep = 1\'b0;
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
pass_req_ctrl = 2\'b11;
pass_rep_ctrl = 2\'b11;
out_req_ctrl = 2\'b11;
out_rep_ctrl = 2\'b11;
`clk_step
pass_req_ctrl = 2\'b00;
pass_rep_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
out_rep_ctrl = 2\'b00;
/// case 5.7 length_code is 01 and used_slots_pass_rep = 4\'b1101;
// out_rep go is zero
pass_req_empty = 1\'b0;
pass_rep_empty = 1\'b0;
OUT_local_req_empty = 1\'b0;
OUT_local_rep_empty = 1\'b0;
OUT_rep_length_code = 2\'b01;
used_slots_pass_rep = 4\'b1101;
en_local_req = 1\'b1;
en_local_rep = 1\'b1;
en_pass_req = 1\'b1;
en_pass_rep = 1\'b1;
next_pass_req = 1\'b1;
next_pass_rep = 1\'b1;
next_local_req = 1\'b0;
next_local_rep = 1\'b0;
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
pass_req_ctrl = 2\'b11;
pass_rep_ctrl = 2\'b11;
out_req_ctrl = 2\'b11;
out_rep_ctrl = 2\'b11;
`clk_step
pass_req_ctrl = 2\'b00;
pass_rep_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
out_rep_ctrl = 2\'b00;
/// case 5.8 length_code is 00 and used_slots_pass_rep = 4\'b1110;
// out_rep go is one
pass_req_empty = 1\'b0;
pass_rep_empty = 1\'b0;
OUT_local_req_empty = 1\'b0;
OUT_local_rep_empty = 1\'b0;
OUT_rep_length_code = 2\'b00;
used_slots_pass_rep = 4\'b1110;
en_local_req = 1\'b1;
en_local_rep = 1\'b1;
en_pass_req = 1\'b1;
en_pass_rep = 1\'b1;
next_pass_req = 1\'b1;
next_pass_rep = 1\'b1;
next_local_req = 1\'b0;
next_local_rep = 1\'b0;
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
pass_req_ctrl = 2\'b11;
pass_rep_ctrl = 2\'b11;
out_req_ctrl = 2\'b11;
out_rep_ctrl = 2\'b11;
`clk_step
pass_req_ctrl = 2\'b00;
pass_rep_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
out_rep_ctrl = 2\'b00;
/// case 5.9 length_code is 00 and used_slots_pass_rep = 4\'b1111;
// out_rep go is zero
pass_req_empty = 1\'b0;
pass_rep_empty = 1\'b0;
OUT_local_req_empty = 1\'b0;
OUT_local_rep_empty = 1\'b0;
OUT_rep_length_code = 2\'b01;
used_slots_pass_rep = 4\'b1111;
en_local_req = 1\'b1;
en_local_rep = 1\'b1;
en_pass_req = 1\'b1;
en_pass_rep = 1\'b1;
next_pass_req = 1\'b1;
next_pass_rep = 1\'b1;
next_local_req = 1\'b0;
next_local_rep = 1\'b0;
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
pass_req_ctrl = 2\'b11;
pass_rep_ctrl = 2\'b11;
out_req_ctrl = 2\'b11;
out_rep_ctrl = 2\'b11;
`clk_step
pass_req_ctrl = 2\'b00;
pass_rep_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
out_rep_ctrl = 2\'b00;
////case 6: -11,00,11,10 ;
pass_req_empty = 1\'b0;
pass_rep_empty = 1\'b0;
OUT_local_req_empty = 1\'b0;
OUT_local_rep_empty = 1\'b0;
OUT_rep_length_code = 2\'b00;
used_slots_pass_rep = 4\'b0000;
en_local_req = 1\'b1;
en_local_rep = 1\'b1;
en_pass_req = 1\'b1;
en_pass_rep = 1\'b1;
next_pass_req = 1\'b1;
next_pass_rep = 1\'b0;
next_local_req = 1\'b0;
next_local_rep = 1\'b0;
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
pass_req_ctrl = 2\'b11;
pass_rep_ctrl = 2\'b11;
out_req_ctrl = 2\'b11;
out_rep_ctrl = 2\'b11;
`clk_step
pass_req_ctrl = 2\'b00;
pass_rep_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
out_rep_ctrl = 2\'b00;
////case 7: 01,00\\,11,00\\ ;
pass_req_empty = 1\'b0;
pass_rep_empty = 1\'b0;
OUT_local_req_empty = 1\'b0;
OUT_local_rep_empty = 1\'b0;
OUT_rep_length_code = 2\'b00;
en_local_req = 1\'b1;
en_local_rep = 1\'b1;
en_pass_req = 1\'b1;
en_pass_rep = 1\'b1;
next_pass_req = 1\'b1;
next_pass_rep = 1\'b1;
next_local_req = 1\'b1;
next_local_rep = 1\'b0;
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
pass_req_ctrl = 2\'b11;
pass_rep_ctrl = 2\'b11;
out_req_ctrl = 2\'b11;
out_rep_ctrl = 2\'b11;
`clk_step
pass_req_ctrl = 2\'b00;
pass_rep_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
out_rep_ctrl = 2\'b00;
////case 8: 01\\,00\\,01\\,00\\ ;
pass_req_empty = 1\'b0;
pass_rep_empty = 1\'b0;
OUT_local_req_empty = 1\'b0;
OUT_local_rep_empty = 1\'b0;
OUT_rep_length_code = 2\'b00;
en_local_req = 1\'b1;
en_local_rep = 1\'b1;
en_pass_req = 1\'b1;
en_pass_rep = 1\'b1;
next_pass_req = 1\'b1;
next_pass_rep = 1\'b1;
next_local_req = 1\'b1;
next_local_rep = 1\'b1;
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
pass_req_ctrl = 2\'b11;
pass_rep_ctrl = 2\'b11;
out_req_ctrl = 2\'b11;
out_rep_ctrl = 2\'b11;
`clk_step
pass_req_ctrl = 2\'b00;
pass_rep_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
out_rep_ctrl = 2\'b00;
////case 9: 11,00\\,01,00\\ ;
pass_req_empty = 1\'b0;
pass_rep_empty = 1\'b0;
OUT_local_req_empty = 1\'b0;
OUT_local_rep_empty = 1\'b0;
OUT_rep_length_code = 2\'b00;
en_local_req = 1\'b1;
en_local_rep = 1\'b1;
en_pass_req = 1\'b1;
en_pass_rep = 1\'b1;
next_pass_req = 1\'b1;
next_pass_rep = 1\'b0;
next_local_req = 1\'b1;
next_local_rep = 1\'b1;
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
pass_req_ctrl = 2\'b11;
pass_rep_ctrl = 2\'b11;
out_req_ctrl = 2\'b11;
out_rep_ctrl = 2\'b11;
`clk_step
pass_req_ctrl = 2\'b00;
pass_rep_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
out_rep_ctrl = 2\'b00;
////case 10: 01\\,-10,01\\,10\\ ;
pass_req_empty = 1\'b0;
pass_rep_empty = 1\'b0;
OUT_local_req_empty = 1\'b0;
OUT_local_rep_empty = 1\'b0;
OUT_rep_length_code = 2\'b00;
en_local_req = 1\'b1;
en_local_rep = 1\'b1;
en_pass_req = 1\'b1;
en_pass_rep = 1\'b1;
next_pass_req = 1\'b0;
next_pass_rep = 1\'b1;
next_local_req = 1\'b0;
next_local_rep = 1\'b1;
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
pass_req_ctrl = 2\'b11;
pass_rep_ctrl = 2\'b11;
out_req_ctrl = 2\'b11;
out_rep_ctrl = 2\'b11;
`clk_step
pass_req_ctrl = 2\'b00;
pass_rep_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
out_rep_ctrl = 2\'b00;
///////////////////////////////////////////////////////////////////////
//////////test whether the arbiter_4_deq can avoid deadlock////////////
used_slots_pass_req = 4\'b0000;
used_slots_pass_rep = 4\'b0000;
pass_req_empty = 1\'b0;
pass_rep_empty = 1\'b0;
OUT_local_req_empty = 1\'b0;
OUT_local_rep_empty = 1\'b0;
OUT_rep_length_code = 2\'b00;
en_local_req = 1\'b1;
en_local_rep = 1\'b1;
en_pass_req = 1\'b1;
en_pass_rep = 1\'b1;
next_pass_req = 1\'b0;
next_pass_rep = 1\'b0;
next_local_req = 1\'b1;
next_local_rep = 1\'b1;
`clk_step
pass_rep_ctrl = 2\'b11;
`clk_step
pass_rep_ctrl = 2\'b00;
`clk_step
pass_req_ctrl = 2\'b11;
out_req_ctrl = 2\'b11;
out_rep_ctrl = 2\'b11;
`clk_step
pass_req_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
out_rep_ctrl = 2\'b00;
\r
\r`clk_step
\r
\rpass_rep_ctrl = 2\'b11;
\r\rout_rep_ctrl = 2\'b11;
\r\r
\r\r`clk_step
\r\r
\r\r\rpass_rep_ctrl = 2\'b00;
\r\rout_rep_ctrl = 2\'b00;
\r\rpass_req_ctrl = 2\'b11;
out_req_ctrl = 2\'b11;
`clk_step
pass_req_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
`clk_step
`clk_step
pass_req_ctrl = 2\'b11;
out_req_ctrl = 2\'b11;
\r\r`clk_step
pass_req_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
`clk_step
`clk_step
pass_req_ctrl = 2\'b11;
out_req_ctrl = 2\'b11;
\r\r`clk_step
pass_req_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
`clk_step
pass_rep_ctrl = 2\'b11;
`clk_step
pass_rep_ctrl = 2\'b00;
pass_req_ctrl = 2\'b11;
out_req_ctrl = 2\'b11;
\r\r`clk_step
pass_req_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
\r\rout_rep_ctrl = 2\'b11;
`clk_step
out_rep_ctrl = 2\'b00;
`clk_step
pass_req_ctrl = 2\'b11;
out_req_ctrl = 2\'b11;
\r\r`clk_step
pass_req_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
`clk_step
`clk_step
pass_req_ctrl = 2\'b11;
out_req_ctrl = 2\'b11;
\r\r`clk_step
pass_req_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
`clk_step
`clk_step
pass_req_ctrl = 2\'b11;
out_req_ctrl = 2\'b11;
\r\r`clk_step
pass_req_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
pass_rep_ctrl=2\'b11;
out_rep_ctrl = 2\'b11;
`clk_step
pass_rep_ctrl=2\'b00;
out_rep_ctrl = 2\'b00;
`clk_step
pass_req_ctrl = 2\'b11;
out_req_ctrl = 2\'b11;
\r\r`clk_step
pass_req_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
`clk_step
`clk_step
pass_req_ctrl = 2\'b11;
out_req_ctrl = 2\'b11;
\r\r`clk_step
pass_req_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
`clk_step
`clk_step
pass_req_ctrl = 2\'b11;
out_req_ctrl = 2\'b11;
pass_rep_ctrl = 2\'b11;
`clk_step
pass_req_ctrl = 2\'b00;
out_req_ctrl = 2\'b00;
pass_rep_ctrl = 2\'b00;
`clk_step
`clk_step
out_rep_ctrl= 2\'b11;
`clk_step
out_rep_ctrl = 2\'b00;
\r`clk_step
$stop;
end
endmodule
|
/*************************************************************************************
date:2016/7/25
designer:ZhaiShaoMin
module name:tb_core_ras
module function:find out errors in the core_RAS
*************************************************************************************/
`timescale 1ns/1ps
`include"define.v"
module tb_core_pc();
//input
reg clk;
reg rst;
reg [31:0] btb_target;
reg [31:0] ras_target;
reg id_pc_src;
reg stall;
reg pc_go;
reg [31:0] good_target;
reg [1:0] btb_type;
reg btb_v;
//output
wire [31:0] pc_out;
wire v_pc_out;
wire [31:0] pc_plus4;
core_pc duv(//input
.clk(clk),
.rst(rst),
.btb_target(btb_target),
.ras_target(ras_target),
.pc_go(pc_go),//pipeline is not stall
.stall(stall),
// from id module
.good_target(good_target), // target from decode stage, correct target
.id_pc_src(id_pc_src), // if 1 ,meaning pc scoure is from decode ,0,otherwise
// from BTB module
.btb_v(btb_v),
.btb_type(btb_type),
//output
.pc_out(pc_out),
.v_pc_out(v_pc_out),
.pc_plus4(pc_plus4)
);
\t\t\t\t\t
//initial inputs
initial begin
clk=1\'b0;
rst=1\'b1;
btb_target=32\'hffffffff;
\t\tras_target=32\'h11111111;
\t\tpc_go=1\'b0;
\t\tstall=1\'b0;
\t\tgood_target=32\'h88888888;
\t\tid_pc_src=1\'b0;
\t\tbtb_v=1\'b0;
\t\tbtb_type=2\'b11;
\t\t
\t\tend
\t\t
\t\t// para used in btb
parameter br_type=2\'b00;
parameter j_type=2\'b01;
parameter jal_type=2\'b10;
parameter jr_type=2\'b11;
\talways #5 clk=~clk;
\tinteger log_file;
`define clk_step #10;
`define record_log 1
\tinitial begin
log_file = $fopen("core_pc_tf.txt");
////////////////////////begin test//////////////////////////
`clk_step
rst=1\'b0;
`clk_step
/////case 1: if rst is set to 1, then pc should be set to 32\'h00040000;
rst=1\'b1;
`clk_step
`ifdef record_log
$display( "(%t) we should get rst_pc. Got 0x%x. Expected 32\'h00040000", $time, pc_out);
$fdisplay(log_file, "(%t) we should get rst_pc. Got 0x%x. Expected 32\'h00040000", $time, pc_out);
`endif
/////// case 2.1: if rst==0&& pc_go stall pc_go&&!stall what it means
/////// 0 0 0 inst cache not hits, pipeline is busy.
rst=1\'b0;
pc_go=1\'b0;
stall=1\'b0;
`clk_step
`ifdef record_log
$display( "(%t) pc_out should not be changed. Got 0x%x. Expected 32\'h00040000", $time, pc_out);
$fdisplay(log_file, "(%t) pc_out should not be changed. Got 0x%x. Expected 32\'h00040000", $time, pc_out);
`endif
/////// case 2.2: if rst==0&& pc_go stall pc_go&&!stall what it means
///////// 0 1 0 inst cache not hits, pipeline is stall.
rst=1\'b0;
pc_go=1\'b0;
stall=1\'b1;
`clk_step
`ifdef record_log
$display( "(%t) pc_out should not be changed. Got 0x%x. Expected 32\'h00040000", $time, pc_out);
$fdisplay(log_file, "(%t) pc_out should not be changed. Got 0x%x. Expected 32\'h00040000", $time, pc_out);
`endif
/////// case 2.3: if rst==0&& pc_go stall pc_go&&!stall what it means
///////// 1 1 0 inst cache hits, pipeline is busy.
rst=1\'b0;
pc_go=1\'b1;
stall=1\'b1;
`clk_step
`ifdef record_log
$display( "(%t) pc_out should not be changed. Got 0x%x. Expected 32\'h00040000", $time, pc_out);
$fdisplay(log_file, "(%t) pc_out should not be changed. Got 0x%x. Expected 32\'h00040000", $time, pc_out);
`endif
/////// case 2.4: if rst==0&& pc_go stall pc_go&&!stall what it means
/////// 1 0 1 inst cache hits, pipeline is busy.
//
// case 2-1-0: if id_pc_src==1,then pc is set to good_target;
rst=1\'b0;
pc_go=1\'b1;
stall=1\'b0;
id_pc_src=1\'b1;
good_target=32\'h20168010;
`clk_step
`ifdef record_log
$display( "(%t) pc_out should be changed . Got 0x%x. Expected 32\'h20168010", $time, pc_out);
$fdisplay(log_file, "(%t) pc_out should be changed. Got 0x%x. Expected 32\'h20168010", $time, pc_out);
`endif
// case 2-1-1: if btb_v==0&&id_pc_src==0, then pc is set to pc_plus4;
rst=1\'b0;
pc_go=1\'b1;
stall=1\'b0;
id_pc_src=1\'b0;
good_target=32\'h20168010;
btb_v=1\'b0;
`clk_step
`ifdef record_log
$display( "(%t) pc_out should be changed . Got 0x%x. Expected 32\'h20168014", $time, pc_out);
$fdisplay(log_file, "(%t) pc_out should be changed. Got 0x%x. Expected 32\'h20168014", $time, pc_out);
`endif
// case 2-1-2: if btb_v==1&&id_pc_src==0&&btb_type==jr_type, then pc is set to RAS_target;
rst=1\'b0;
pc_go=1\'b1;
stall=1\'b0;
id_pc_src=1\'b0;
good_target=32\'h20168010;
ras_target=32\'h24241010;
btb_v=1\'b1;
btb_type=`jr_type;
`clk_step
`ifdef record_log
$display( "(%t) pc_out should be changed . Got 0x%x. Expected 32\'h24241010", $time, pc_out);
$fdisplay(log_file, "(%t) pc_out should be changed. Got 0x%x. Expected 32\'h24241010", $time, pc_out);
`endif
// case 2-1-3: if btb_v==1&&id_pc_src==0&&(btb_type==br_type||
// btb_type==j_type||
// btb_type==jal_type),then pc is set to btb_target.
//////btb_type==j_type
rst=1\'b0;
pc_go=1\'b1;
stall=1\'b0;
id_pc_src=1\'b0;
good_target=32\'h20168010;
ras_target=32\'h24241010;
btb_target=32\'h22228888;
btb_v=1\'b1;
btb_type=`j_type;
`clk_step
`ifdef record_log
$display( "(%t) pc_out should be changed . Got 0x%x. Expected 32\'h22228888", $time, pc_out);
$fdisplay(log_file, "(%t) pc_out should be changed. Got 0x%x. Expected 32\'h22228888", $time, pc_out);
`endif
/////btb_type==jal_type
rst=1\'b0;
pc_go=1\'b1;
stall=1\'b0;
id_pc_src=1\'b0;
good_target=32\'h20168010;
ras_target=32\'h24241010;
btb_target=32\'h22448888;
btb_v=1\'b1;
btb_type=`jal_type;
`clk_step
`ifdef record_log
$display( "(%t) pc_out should be changed . Got 0x%x. Expected 32\'h22448888", $time, pc_out);
$fdisplay(log_file, "(%t) pc_out should be changed. Got 0x%x. Expected 32\'h22448888", $time, pc_out);
`endif
/////btb_type==br_type
rst=1\'b0;
pc_go=1\'b1;
stall=1\'b0;
id_pc_src=1\'b0;
good_target=32\'h20168010;
ras_target=32\'h24241010;
btb_target=32\'h22446688;
btb_v=1\'b1;
btb_type=`br_type;
`clk_step
`ifdef record_log
$display( "(%t) pc_out should be changed . Got 0x%x. Expected 32\'h22446688", $time, pc_out);
$fdisplay(log_file, "(%t) pc_out should be changed. Got 0x%x. Expected 32\'h22446688", $time, pc_out);
`endif
$stop;
end
endmodule
|
/// date:2016/3/9
/// engineer: ZhaiShaoMin
module dc_download(//input
clk,
rst,
IN_flit_dc,
v_IN_flit_dc,
In_flit_ctrl_dc,
dc_done_access,
//output
v_dc_download,
dc_download_flits,
dc_download_state
);
/////// reply cmd
parameter wbrep_cmd=5'b10000;
parameter C2Hinvrep_cmd=5'b10001;
parameter flushrep_cmd=5'b10010;
parameter ATflurep_cmd=5'b10011;
parameter shrep_cmd=5'b11000;
parameter exrep_cmd=5'b11001;
parameter SH_exrep_cmd=5'b11010;
parameter SCflurep_cmd=5'b11100;
parameter instrep_cmd=5'b10100;
parameter C2Cinvrep_cmd=5'b11011;
parameter nackrep_cmd=5'b10101;
parameter flushfail_rep_cmd=5'b10110;
parameter wbfail_rep_cmd=5'b10111;
//input
input clk;
input rst;
input [15:0] IN_flit_dc; //from IN fifos
input v_IN_flit_dc;
input [1:0] In_flit_ctrl_dc;
input dc_done_access; // from data cache
//output
output v_dc_download; // to data cache
output [143:0] dc_download_flits;
output [1:0] dc_download_state; // to arbiter_IN_node
//
reg [1:0] dc_download_nstate;
reg [1:0] dc_download_cstate;
parameter dc_download_idle=2'b00;
parameter dc_download_busy=2'b01;
parameter dc_download_rdy=2'b10;
reg [15:0] flit_reg1;
reg [15:0] flit_reg2;
reg [15:0] flit_reg3;
reg [15:0] flit_reg4;
reg [15:0] flit_reg5;
reg [15:0] flit_reg6;
reg [15:0] flit_reg7;
reg [15:0] flit_reg8;
reg [15:0] flit_reg9;
assign dc_download_state=dc_download_cstate;
assign dc_download_flits={flit_reg9,flit_reg8,flit_reg7,flit_reg6,flit_reg5,flit_reg4,flit_reg3,flit_reg2,flit_reg1};
reg v_dc_download;
reg en_flit_dc;
reg inc_cnt;
reg fsm_rst;
/// fsm of ic_download
always@(*)
begin
//default values
dc_download_nstate=dc_download_cstate;
v_dc_download=1'b0;
en_flit_dc=1'b0;
inc_cnt=1'b0;
fsm_rst=1'b0;
case(dc_download_cstate)
dc_download_idle:
begin
if(v_IN_flit_dc)
begin
if(IN_flit_dc[9:5]==nackrep_cmd||IN_flit_dc[9:5]==SCflurep_cmd||IN_flit_dc[9:5]==C2Cinvrep_cmd)
dc_download_nstate=dc_download_rdy;
else
dc_download_nstate=dc_download_busy;
en_flit_dc=1'b1;
inc_cnt=1'b1;
end
end
dc_download_busy:
begin
if(v_IN_flit_dc)
begin
if(In_flit_ctrl_dc==2'b11)
begin
// en_flit_dc=1'b1;
dc_download_nstate=dc_download_rdy;
end
en_flit_dc=1'b1;
inc_cnt=1'b1;
end
end
dc_download_rdy:
begin
v_dc_download=1'b1;
if(dc_done_access)
begin
dc_download_nstate=dc_download_idle;
fsm_rst=1'b1;
end
end
endcase
end
reg [3:0] cnt;
reg [8:0] en_flits;
// select right inst_word_in
always@(*)
begin
case(cnt)
4'b0000:en_flits=9'b000000001;
4'b0001:en_flits=9'b000000010;
4'b0010:en_flits=9'b000000100;
4'b0011:en_flits=9'b000001000;
4'b0100:en_flits=9'b000010000;
4'b0101:en_flits=9'b000100000;
4'b0110:en_flits=9'b001000000;
4'b0111:en_flits=9'b010000000;
4'b1000:en_flits=9'b100000000;
default:en_flits=9'b000000000;
endcase
end
// 1st flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg1<=16'h0000;
else if(en_flits[0]&&en_flit_dc)
flit_reg1<=IN_flit_dc;
end
//2ed flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg2<=16'h0000;
else if(en_flits[1]&&en_flit_dc)
flit_reg2<=IN_flit_dc;
end
// 3rd flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg3<=16'h0000;
else if(en_flits[2]&&en_flit_dc)
flit_reg3<=IN_flit_dc;
end
//4th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg4<=16'h0000;
else if(en_flits[3]&&en_flit_dc)
flit_reg4<=IN_flit_dc;
end
//5th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg5<=16'h0000;
else if(en_flits[4]&&en_flit_dc)
flit_reg5<=IN_flit_dc;
end
//6th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg6<=16'h0000;
else if(en_flits[5]&&en_flit_dc)
flit_reg6<=IN_flit_dc;
end
//7th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg7<=16'h0000;
else if(en_flits[6]&&en_flit_dc)
flit_reg7<=IN_flit_dc;
end
//8th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg8<=16'h0000;
else if(en_flits[7]&&en_flit_dc)
flit_reg8<=IN_flit_dc;
end
//9th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg9<=16'h0000;
else if(en_flits[8]&&en_flit_dc)
flit_reg9<=IN_flit_dc;
end
// fsm regs
always@(posedge clk)
begin
if(rst)
dc_download_cstate<=2'b00;
else
dc_download_cstate<=dc_download_nstate;
end
//counter reg
always@(posedge clk)
begin
if(rst||fsm_rst)
cnt<=4'b0000;
else if(inc_cnt)
cnt<=cnt+4'b0001;
end
endmodule
|
/// date :2016/2/27
/// engineer
/// module name mem controler
/// module function : include direcotory ram and data ram
module memory_fsm(// global signals
clk,
rst,
//fsm state of rep paralle-serial port corresponding to mem
m_rep_fsm_state,
//fsm state of req paralle-serial port corresponding to mem
m_req_fsm_state,
// fsm state of req/rep regs to data cache
d_fsm_state,
// fsm state of input reg to inst cache
i_fsm_state,
// input from mem_ram
mem_state_out,
mem_data_in,
// input from local d cache
v_d_req,
v_d_rep,
local_d_head_in,
local_d_addr_in,
local_d_data_in,
// input from local i cache
v_i_rep,
// local_i_head, // no need for local i cache miss
local_i_addr_in,
// input form INfifos
v_INfifos,
infifos_head_in,
infifos_addr_in,
infifos_data_in,
//output to mem_ram
data_out_mem_ram,
state_out_mem_ram,
addr_out_mem_ram,
//output to mem_ram
state_we_out,
state_re_out,
data_we_out,
data_re_out,
// output to local d cache
v_req_d,
v_rep_d,
head_out_local_d,
addr_out_local_d,
data_out_local_d,
// output to local i cahce
v_rep_Icache,
data_out_local_i,
// output to OUT req fifo
en_inv_ids,
inv_ids_in,
flit_max_req,
en_flit_max_req,
v_req_out,
head_out_req_out,
addr_out_req_out,
// data_out_req_out,
// output to OUT rep fifo
flit_max_rep,
en_flit_max_rep,
v_rep_out,
head_out_rep_out,
addr_out_rep_out,
data_out_rep_out,
mem_access_done
);
// parameters of msg type used for temp reg
parameter shrep_type=4'b0001;
parameter wbreq_type=4'b0010;
parameter exrep_type=4'b0011;
parameter SHexrep_type=4'b0100;
parameter invreq_type=4'b0101;
parameter SCinvreq_type=4'b0110;
parameter flushreq_type=4'b0111;
parameter SCflurep_type=4'b1000;
parameter instrep_type=4'b1001;
parameter nackrep_type=4'b1010;
parameter local_id=2'b00;
/// parameter of msg cmd
/////// request cmd
parameter shreq_cmd=5'b00000;
parameter exreq_cmd=5'b00001;
parameter SCexreq_cmd=5'b00010;
parameter instreq_cmd=5'b00110;
parameter wbreq_cmd=5'b00011;
parameter invreq_cmd=5'b00100;
parameter flushreq_cmd=5'b00101;
parameter SCinvreq_cmd=5'b00110;
/////// reply cmd
parameter wbrep_cmd=5'b10000;
parameter C2Hinvrep_cmd=5'b10001;
parameter flushrep_cmd=5'b10010;
parameter ATflurep_cmd=5'b10011;
parameter shrep_cmd=5'b11000;
parameter exrep_cmd=5'b11001;
parameter SH_exrep_cmd=5'b11010;
parameter SCflurep_cmd=5'b11100;
parameter instrep_cmd=5'b10100;
parameter C2Cinvrep_cmd=5'b11011;
parameter nackrep_cmd=5'b10101;
parameter flushfail_rep_cmd=5'b10110;
parameter wbfail_rep_cmd=5'b10111;
///
parameter i_idle=2'b00;
parameter d_idle=1'b0;
parameter m_rep_idle=1'b0;
parameter m_req_idle=1'b0;
input clk;
input rst;
input [1:0] i_fsm_state;
input d_fsm_state;
input m_rep_fsm_state;
input m_req_fsm_state;
// input from mem_ram
input [5:0] mem_state_out;
input [127:0] mem_data_in;
// input from local d cache
input v_d_req;
input v_d_rep;
input [15:0] local_d_head_in;
input [31:0] local_d_addr_in;
input [127:0] local_d_data_in;
// input from local i cache
input v_i_rep;
// local_i_head, // no need for local i cache miss
input [31:0] local_i_addr_in;
// input form INfifos
input v_INfifos;
input [15:0] infifos_head_in;
input [31:0] infifos_addr_in;
input [127:0] infifos_data_in;
// output to mem_ram
output [127:0] data_out_mem_ram;
output [5:0] state_out_mem_ram;
output [31:0] addr_out_mem_ram;
//output to mem_ram
output state_we_out;
output state_re_out;
output data_we_out;
output data_re_out;
// output to local d cache
output v_req_d;
output v_rep_d;
output [15:0] head_out_local_d;
output [31:0] addr_out_local_d;
output [127:0] data_out_local_d;
// output to local i cahce
output v_rep_Icache;
output [127:0] data_out_local_i;
// output to OUT req fifo
output en_inv_ids;
output [3:0] inv_ids_in;
output [3:0] flit_max_req;
output en_flit_max_req;
output v_req_out;
output [15:0] head_out_req_out;
output [31:0] addr_out_req_out;
// output [127:0] data_out_req_out;
// output to OUT rep fifo
output [3:0] flit_max_rep;
output en_flit_max_rep;
output v_rep_out;
output [15:0] head_out_rep_out;
output [31:0] addr_out_rep_out;
output [127:0] data_out_rep_out;
output mem_access_done;
wire [5:0] m_state_out;
assign m_state_out=mem_state_out;
reg [15:0] temp_req_head_flit;
reg [15:0] temp_rep_head_flit;
wire [15:0] temp_req_head_flit_in1;
wire [15:0] temp_rep_head_flit_in1;
///////////////////////////////////////////////////////////////////////////
//////////////////////MEMORY FSM///////////////////////////////////////////
reg state_re_out;
reg mem_access_done;
reg data_re_out;
reg [1:0] addr_sel;
reg [1:0] data_sel;
reg req_done;
reg rep_done;
reg has_only_id;
reg [5:0] m_state_in;
reg en_rep_type;
reg [3:0] rep_type;
reg [3:0] rep_type_reg;
reg en_req_type;
reg [3:0] req_type;
reg [3:0] req_type_reg;
reg en_m_state_in;
reg oneORmore;
reg en_inv_ids;
reg [3:0] inv_ids_in;
reg [3:0] src_id_dir;
reg [3:0] requester_id_dir;
reg en_m_data_in;
reg [175:0] msg;
reg v_rep_d;
reg v_rep_out;
reg v_req_d;
reg v_req_out;
reg v_rep_Icache;
//reg [4:0] thead;
///////////// I have forget what function it is ,soI think I should take enough notes to some strange things
reg en_temp_rep_head_flit;
reg [15:0] temp_rep_head_flit_in;
reg en_temp_req_head_flit;
reg [15:0] temp_req_head_flit_in;
//reg [3:0] flit_max;
//reg en_flit_max;
reg [3:0] flit_max_rep;
reg en_flit_max_rep;
reg [3:0] flit_max_req;
reg en_flit_max_req;
reg t_req_head_sel;
reg t_rep_head_sel;
reg id_sel_out;
reg rep_local_remote;
reg req_local_remote;
reg [4:0] cmd_type;
reg set_req_done;
reg set_rep_done;
reg rst_rep_type;
reg rst_req_type;
////////fsm
parameter m_idle=2'b00;
parameter m_compare_tag=2'b01;
parameter m_gen_shrep=2'b10;
parameter m_gen_exrep=2'b11;
reg [1:0] nstate;
reg [1:0] rstate;
wire [15:0] seled_head;
wire [31:0] seled_addr;
wire [127:0] seled_data;
wire [127:0] data_read;
assign data_read=mem_data_in;
assign seled_head=addr_sel?infifos_head_in:local_d_head_in;
assign seled_addr=addr_sel?infifos_addr_in:local_d_addr_in;
assign addr_out_mem_ram=seled_addr;
always@(*)
begin
// default signal values
// en_temp_head_flit=1'b0;
mem_access_done=1'b0;
state_re_out=1'b0;
data_re_out=1'b0;
cmd_type=5'b00000;
rep_local_remote=1'b0;
req_local_remote=1'b0;
addr_sel=1'b0;
data_sel=1'b0;
nstate=rstate;
has_only_id=1'b0;
m_state_in=6'b000000;
en_rep_type=1'b0;
rep_type=4'b0000;
en_req_type=1'b0;
req_type=4'b0000;
en_m_state_in=1'b0;
oneORmore=1'b0;
en_inv_ids=1'b0;
inv_ids_in=4'b0000;
src_id_dir=4'b0000;
requester_id_dir=4'b0000;
en_m_data_in=1'b0;
msg=176'h0000;
v_rep_d=1'b0;
v_rep_out=1'b0;
v_req_d=1'b0;
v_req_out=1'b0;
v_rep_Icache=1'b0;
// thead=5'b00000;
t_req_head_sel=1'b0;
t_rep_head_sel=1'b0;
en_temp_rep_head_flit=1'b0;
temp_rep_head_flit_in =16'h0000;
en_temp_req_head_flit=1'b0;
temp_req_head_flit_in=16'h0000;
// flit_max=4'b0000;
// en_flit_max=1'b0;
flit_max_req=4'b0000;
en_flit_max_req=1'b0;
\t flit_max_rep=4'b0000;
en_flit_max_rep=1'b0;
id_sel_out=1'b0;
set_req_done=1'b0;
set_rep_done=1'b0;
\t rst_rep_type=1'b0;
\t rst_req_type=1'b0;
case(rstate)
m_idle:
begin
if(v_d_req==1'b1||v_d_rep==1'b1)
begin
addr_sel=1'b0;
data_sel=1'b0;
nstate=m_compare_tag;
// en_temp_head_flit=1'b1;
t_req_head_sel=1'b0;
t_rep_head_sel=1'b0;
en_temp_rep_head_flit=1'b1;
en_temp_req_head_flit=1'b1;
end
else if(v_INfifos==1'b1)
begin
addr_sel=1'b1;
data_sel=1'b1;
nstate=m_compare_tag;
// en_temp_head_flit=1'b1;
t_req_head_sel=1'b0;
t_rep_head_sel=1'b0;
en_temp_rep_head_flit=1'b1;
en_temp_req_head_flit=1'b1;
end
end
m_compare_tag:
begin
state_re_out=1'b1;
// has_only_id function
case(seled_head[12:11])
2'b00:has_only_id=m_state_out[3:0]==4'b0001;
2'b01:has_only_id=m_state_out[3:0]==4'b0010;
2'b10:has_only_id=m_state_out[3:0]==4'b0100;
2'b11:has_only_id=m_state_out[3:0]==4'b1000;
// default:has_only_id=m_state_out[3:0]==4'b0001;
endcase
//id_sel_out
case(seled_head[12:11])
2'b00:id_sel_out=m_state_out[0];
2'b01:id_sel_out=m_state_out[1];
2'b10:id_sel_out=m_state_out[2];
2'b11:id_sel_out=m_state_out[3];
endcase
// default:id_sel_out=m_state_out[0];
//////////////////////////////////
// check req /rep type////////////
//////////////////////////////////
//////////////////////////////////
// fsm will gen shreps
if((seled_head[9:5]==shreq_cmd||seled_head[9:5]==wbfail_rep_cmd)&&m_state_out[5:4]==2'b00&&id_sel_out==1'b0)
begin
if(seled_addr[12:11]==local_id)
rep_local_remote=1'b0;
else
rep_local_remote=1'b1;
en_m_state_in=1'b1;
case(seled_head[12:11])
2'b00:m_state_in={m_state_out[5:1],1'b0};
2'b01:m_state_in={m_state_out[5:2],1'b0,m_state_out[0]};
2'b10:m_state_in={m_state_out[5:3],1'b0,m_state_out[1:0]};
2'b11:m_state_in={m_state_out[5:4],1'b0,m_state_out[2:0]};
default:m_state_in=m_state_out;
endcase
rep_type=shrep_type;
en_rep_type=1'b1;
// oneORmore=1'b0;
nstate=m_gen_shrep;
// t_req_head_sel=1'b0;
t_rep_head_sel=1'b1;
en_temp_rep_head_flit=1'b1;
temp_rep_head_flit_in={temp_rep_head_flit[12:11],1'b0,temp_rep_head_flit[15:14],1'b1,shrep_cmd,5'b00000};
end
////////////////////////////////////
// fsm will gen NACKreply
if(seled_head[9:5]==shreq_cmd&&m_state_out[5]==1'b1)
begin
if(seled_addr[12:11]==local_id)
rep_local_remote=1'b0;
else
rep_local_remote=1'b1;
/// since the addr being accessed is busy doing other thing,home should just NACK this request ,
/// (via sending back a simple reply tell the requester the addr now is busy ,please retry again(here just for simplicity))
/// and no need to do something to m_state!
rep_type=nackrep_type;
en_rep_type=1'b1;
/* en_m_state_in=1'b1;
case(seled_head[12:11])
2'b00:m_state_in={m_state_out[5:1],1'b0};
2'b01:m_state_in={m_state_out[5:2],1'b0,m_state_out[0]};
2'b01:m_state_in={m_state_out[5:3],1'b0,m_state_out[1:0]};
2'b01:m_state_in={m_state_out[5:4],1'b0,m_state_out[2:0]};
default:m_state_in=m_state_out;
endcase */
// oneORmore=1'b0;
nstate=m_gen_shrep;
// t_req_head_sel=1'b0;
t_rep_head_sel=1'b1;
en_temp_rep_head_flit=1'b1;
temp_rep_head_flit_in={temp_rep_head_flit[12:11],1'b0,temp_rep_head_flit[15:14],1'b1,nackrep_cmd,5'b00000};
end
//////////////////////
// fsm will gen wbreq
if(seled_head[9:5]==shreq_cmd&&m_state_out[5:4]==2'b01&&id_sel_out==1'b0)
begin
if(seled_addr[12:11]==local_id)
req_local_remote=1'b0;
else
req_local_remote=1'b1;
en_m_state_in=1'b1;
m_state_in={2'b11,m_state_out[3:0]};
en_req_type=1'b1;
req_type=wbreq_type;
// oneORmore=1'b0;
t_req_head_sel=1'b1;
// t_rep_head_sel=1'b0;
nstate=m_gen_shrep;
en_temp_req_head_flit=1'b1;
temp_req_head_flit_in={2'b00,1'b0,temp_req_head_flit[15:14],1'b1,wbreq_cmd,temp_req_head_flit[12:11],3'b000};
end
////////////////////////
// fsm will gen exrep
if((seled_head[9:5]==exreq_cmd||seled_head[9:5]==flushfail_rep_cmd||seled_head[9:5]==SCexreq_cmd)&&m_state_out[5:4]==2'b00&&(|m_state_out[3:0]==1'b0||has_only_id))
begin
if(seled_addr[12:11]==local_id)
rep_local_remote=1'b0;
else
rep_local_remote=1'b1;
en_m_state_in=1'b1;
case(seled_head[12:11])
2'b00:m_state_in=6'b100001;
2'b01:m_state_in=6'b100010;
2'b10:m_state_in=6'b100100;
2'b11:m_state_in=6'b101000;
default:m_state_in=6'b100001;
endcase
rep_type=exrep_type;
en_rep_type=1'b1;
oneORmore=1'b0;
nstate=m_gen_exrep;
// t_req_head_sel=1'b0;
t_rep_head_sel=1'b1;
en_temp_rep_head_flit=1'b1;
temp_rep_head_flit_in={temp_rep_head_flit[12:11],1'b0,temp_rep_head_flit[15:14],1'b1,exrep_cmd,5'b00000};
end
////////////////////////
// fsm will gen NACKrep
if((seled_head[9:5]==exreq_cmd||seled_head[9:5]==SCexreq_cmd)&&m_state_out[5]==1'b1)
begin
if(seled_addr[12:11]==local_id)
rep_local_remote=1'b0;
else
rep_local_remote=1'b1;
/// since the addr being accessed is busy doing other thing,home should just NACK this request ,
/// (via sending back a simple reply tell the requester the addr now is busy ,please retry again(here just for simplicity))
/// and no need to do something to m_state!
rep_type=nackrep_type;
en_rep_type=1'b1;
oneORmore=1'b0;
/* en_m_state_in=1'b1;
case(seled_head[12:11])
2'b00:m_state_in=6'b100001;
2'b01:m_state_in=6'b100010;
2'b01:m_state_in=6'b100100;
2'b01:m_state_in=6'b101000;
default:m_state_in=6'b100001;
endcase */
nstate=m_gen_exrep;
// t_req_head_sel=1'b0;
t_rep_head_sel=1'b1;
en_temp_rep_head_flit=1'b1;
temp_rep_head_flit_in={temp_rep_head_flit[12:11],1'b0,temp_rep_head_flit[15:14],1'b1,nackrep_cmd,5'b00000};
end
//////////////////////////////////
//// fsm will gen invreq /SCinvreq
if((seled_head[9:5]==exreq_cmd||seled_head[9:5]==SCexreq_cmd)&&m_state_out[5:4]==2'b00&&!(|m_state_out[3:0]==1'b0||has_only_id))
begin
// check whether the original dir include src_id
if(id_sel_out==1'b1)
begin
case(seled_head[12:11])
2'b00:m_state_in={2'b10,m_state_out[3:1],1'b0};
2'b01:m_state_in={2'b10,m_state_out[3:2],1'b0,m_state_out[0]};
2'b10:m_state_in={2'b10,m_state_out[3],1'b0,m_state_out[1:0]};
2'b11:m_state_in={2'b10,1'b0,m_state_out[2:0]};
default:m_state_in={2'b10,m_state_out[3:1],1'b0};
endcase
end
else
begin
m_state_in={2'b10,m_state_out[3:0]};
end
//check whether invreq or SCinvreq
if(seled_head[9:5]==exreq_cmd)
begin
req_type=invreq_type;
cmd_type=invreq_cmd;
end
else
begin
req_type=SCinvreq_type;
cmd_type=SCinvreq_cmd;
end
if(seled_addr[12:11]==local_id)
req_local_remote=1'b0;
else
req_local_remote=1'b1;
// commen signals
en_m_state_in=1'b1;
en_req_type=1'b1;
oneORmore=1'b1;
rep_type=SHexrep_type;
en_rep_type=1'b1;
// reg the invreq vectors!
en_inv_ids=1'b1;
inv_ids_in=m_state_out[3:0];
nstate=m_gen_exrep;
t_req_head_sel=1'b1;
t_rep_head_sel=1'b1;
en_temp_rep_head_flit=1'b1;
temp_rep_head_flit_in={temp_rep_head_flit[12:11],1'b0,temp_rep_head_flit[15:14],1'b1,exrep_cmd,1'b0,m_state_out[3:0]};
en_temp_req_head_flit=1'b1;
temp_req_head_flit_in={2'b00,1'b0,temp_rep_head_flit[15:14],1'b1,cmd_type,temp_rep_head_flit[12:11],3'b000};
end
//////////////////
// gen flushreq
if(seled_head[9:5]==exreq_cmd&&m_state_out[5:4]==2'b10&&id_sel_out==1'b0)
begin
if(seled_addr[12:11]==local_id)
req_local_remote=1'b0;
else
req_local_remote=1'b1;
oneORmore=1'b0;
en_m_state_in=1'b1;
m_state_in={2'b11,m_state_out[3:0]};
en_req_type=1'b1;
req_type=flushreq_type;
nstate=m_gen_exrep;
t_req_head_sel=1'b1;
// t_rep_head_sel=1'b0;
en_temp_req_head_flit=1'b1;
temp_req_head_flit_in={2'b00,1'b0,temp_req_head_flit[15:14],1'b1,flushreq_cmd,temp_req_head_flit[12:11],3'b000};
end
/////////////////
// gen SCflushrep
if(seled_head[9:5]==SCexreq_cmd&&m_state_out[5:4]==2'b10&&id_sel_out==1'b0)
begin
if(seled_addr[12:11]==local_id)
rep_local_remote=1'b0;
else
rep_local_remote=1'b1;
oneORmore=1'b0;
en_rep_type=1'b1;
rep_type=SCflurep_type;
// t_req_head_sel=1'b0;
nstate=m_gen_exrep;
t_rep_head_sel=1'b1;
en_temp_rep_head_flit=1'b1;
temp_rep_head_flit_in={temp_rep_head_flit[12:11],1'b0,temp_rep_head_flit[15:14],1'b1,SCflurep_cmd,5'b00000};
end
/////////////////
/// gen instrep!
if(seled_head[9:5]==instreq_cmd)
begin
if(seled_addr[12:11]==local_id)
rep_local_remote=1'b0;
else
rep_local_remote=1'b1;
en_rep_type=1'b1;
rep_type=instrep_type;
// oneORmore=1'b0;
nstate=m_gen_shrep;
// t_req_head_sel=1'b0;
t_rep_head_sel=1'b1;
en_temp_rep_head_flit=1'b1;
temp_rep_head_flit_in={temp_rep_head_flit[12:11],1'b0,temp_rep_head_flit[15:14],1'b1,instrep_cmd,5'b00000};
end
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
///////////fsm will process the rep from network or local D$ or I$///////
//process invreps
if(seled_head[9:5]==C2Cinvrep_cmd&&(m_state_out[5:4]==2'b10))
begin
\t\t rst_rep_type=1'b1;
\t\t\t rst_req_type=1'b1;
nstate=m_idle;
mem_access_done=1'b1;
// some invreps haven't come
if(m_state_out[3:0]!=src_id_dir)
begin
en_m_state_in=1'b1;
case(seled_head[12:11])
2'b00:m_state_in={2'b10,m_state_out[3:1],1'b0};
2'b01:m_state_in={2'b10,m_state_out[3:2],1'b0,m_state_out[0]};
2'b10:m_state_in={2'b10,m_state_out[3],1'b0,m_state_out[1:0]};
2'b11:m_state_in={2'b10,1'b0,m_state_out[2:0]};
default:m_state_in={2'b10,m_state_out[3:1],1'b0};
endcase
end
// all the necessary invreps have come
else
begin
m_state_in={2'b01,requester_id_dir};
en_m_state_in=1'b1;
end
//src_id_dir :convert src_id to dir style
case(seled_head[12:11])
2'b00:src_id_dir=4'b0001;
2'b01:src_id_dir=4'b0010;
2'b10:src_id_dir=4'b0100;
2'b11:src_id_dir=4'b1000;
default:src_id_dir=4'b0001;
endcase
//requester_id_dir: convert requester id into dir stylr
case(seled_head[4:3])
2'b00:requester_id_dir=4'b0001;
2'b01:requester_id_dir=4'b0010;
2'b10:requester_id_dir=4'b0100;
2'b11:requester_id_dir=4'b1000;
default:requester_id_dir=4'b0001;
endcase
end
////////////////////////////////////
/// process (auto)invreps
if(seled_head[9:5]==C2Hinvrep_cmd&&(m_state_out[5:4]==2'b00))
begin
\t\t rst_rep_type=1'b1;
\t\t\t rst_req_type=1'b1;
nstate=m_idle;
mem_access_done=1'b1;
en_m_state_in=1'b1;
case(seled_head[12:11])
2'b00:m_state_in={2'b00,m_state_out[3:1],1'b0};
2'b01:m_state_in={2'b00,m_state_out[3:2],1'b0,m_state_out[0]};
2'b10:m_state_in={2'b00,m_state_out[3],1'b0,m_state_out[1:0]};
2'b11:m_state_in={2'b00,1'b0,m_state_out[2:0]};
default:m_state_in={2'b00,m_state_out[3:1],1'b0};
endcase
end
//////////////////////////////////////
/// process wbrep
if(seled_head[9:5]==wbrep_cmd&&(m_state_out[5:4]==2'b11))
begin
\t\t rst_rep_type=1'b1;
\t\t\t rst_req_type=1'b1;
nstate=m_idle;
mem_access_done=1'b1;
en_m_state_in=1'b1;
en_m_data_in=1'b1;
case(seled_head[12:11])
2'b00:m_state_in={2'b00,m_state_out[3:1],1'b1};
2'b01:m_state_in={2'b00,m_state_out[3:2],1'b1,m_state_out[0]};
2'b10:m_state_in={2'b00,m_state_out[3],1'b1,m_state_out[1:0]};
2'b11:m_state_in={2'b00,1'b1,m_state_out[2:0]};
default:m_state_in={2'b00,m_state_out[3:1],1'b1};
endcase
end
/////////////////////////////////////////
/// process AUTOflushrep
if(seled_head[9:5]==ATflurep_cmd&&(m_state_out[5:4]==2'b01))
begin
\t\t rst_rep_type=1'b1;
\t\t\t rst_req_type=1'b1;
nstate=m_idle;
mem_access_done=1'b1;
en_m_state_in=1'b1;
en_m_data_in=1'b1;
m_state_in=6'b000000;
end
/////////////////////////////////////////
/// process flushrep
if(seled_head[9:5]==flushrep_cmd&&(m_state_out[5:4]==2'b11))
begin
\t\t rst_rep_type=1'b1;
\t\t\t rst_req_type=1'b1;
nstate=m_idle;
mem_access_done=1'b1;
en_m_state_in=1'b1;
case(seled_head[4:3])
2'b00:m_state_in=6'b010001;
2'b01:m_state_in=6'b010010;
2'b10:m_state_in=6'b010100;
2'b11:m_state_in=6'b011000;
default:m_state_in=6'b010001;
endcase
end
end
m_gen_shrep:
begin
data_re_out=1'b1;
/////////////////////////////////////
/// gen shrep
if(rep_type_reg==shrep_type&&~rep_local_remote&&d_fsm_state==d_idle)
begin
v_rep_d=1'b1;
// flit_max_rep=4'b1000;
// en_flit_max_rep=1'b1;
msg={temp_rep_head_flit,data_read,32'h00000000};
nstate=m_idle;
mem_access_done=1'b1;
\t\t\t\t rst_rep_type=1'b1;
\t\t\t\t rst_req_type=1'b1;
end
if(rep_type_reg==shrep_type&&rep_local_remote&&m_rep_fsm_state==m_rep_idle)
begin
v_rep_out=1'b1;
flit_max_rep=4'b1000;
en_flit_max_rep=1'b1;
msg={temp_rep_head_flit,data_read,32'h00000000};
nstate=m_idle;
mem_access_done=1'b1;
\t\t\t\t rst_rep_type=1'b1;
\t\t\t\t rst_req_type=1'b1;
end
/////////////////////////////////////
/// gen nackrep
if(rep_type_reg==nackrep_type&&~rep_local_remote&&d_fsm_state==d_idle)
begin
v_rep_d=1'b1;
// flit_max_rep=4'b0000;
// en_flit_max_rep=1'b1;
msg={temp_rep_head_flit,data_read,32'h00000000};
nstate=m_idle;
mem_access_done=1'b1;
\t\t\t\t rst_rep_type=1'b1;
\t\t\t\t rst_req_type=1'b1;
end
if(rep_type_reg==nackrep_type&&rep_local_remote&&m_rep_fsm_state==m_rep_idle)
begin
v_rep_out=1'b1;
flit_max_rep=4'b0000;
en_flit_max_rep=1'b1;
msg={temp_rep_head_flit,data_read,32'h00000000};
nstate=m_idle;
mem_access_done=1'b1;
\t\t rst_rep_type=1'b1;
\t\t\t\t rst_req_type=1'b1;
end
//////////////////////////////////////
/// gen wbreq
if(req_type_reg==wbreq_type&&~req_local_remote&&d_fsm_state==d_idle)
begin
v_req_d=1'b1;
// flit_max_req=4'b0010;
// en_flit_max_req=1'b1;
msg={temp_rep_head_flit,seled_addr,128'h0000};
nstate=m_idle;
mem_access_done=1'b1;
\t\t\t\t rst_rep_type=1'b1;
\t\t\t\t rst_req_type=1'b1;
end
if(req_type_reg==wbreq_type&&req_local_remote&&m_req_fsm_state==m_req_idle)
begin
v_req_out=1'b1;
flit_max_req=4'b0010;
en_flit_max_req=1'b1;
msg={temp_req_head_flit,seled_addr,128'h0000};
nstate=m_idle;
mem_access_done=1'b1;
\t\t\t\t rst_rep_type=1'b1;
\t\t\t\t rst_req_type=1'b1;
end
///////////////////////////////////////
/// gen instrep
if(rep_type_reg==instrep_type&&~rep_local_remote&&i_fsm_state==i_idle)
begin
v_rep_Icache=1'b1;
// flit_max_rep=4'b1000;
// en_flit_max_rep=1'b1;
msg={temp_rep_head_flit,data_read,32'h00000000};
nstate=m_idle;
mem_access_done=1'b1;
\t\t\t\t rst_rep_type=1'b1;
\t\t\t\t rst_req_type=1'b1;
end
if(rep_type_reg==instrep_type&&rep_local_remote&&m_rep_fsm_state==m_rep_idle)
begin
v_rep_out=1'b1;
flit_max_rep=4'b1000;
en_flit_max_rep=1'b1;
msg={temp_rep_head_flit,data_read,32'h00000000};
nstate=m_idle;
mem_access_done=1'b1;
\t\t\t\t rst_rep_type=1'b1;
\t\t\t rst_req_type=1'b1;
end
end
m_gen_exrep:
begin
//////////////////////////////////////////
//// gen exrep
if(oneORmore==1'b0)
begin
if(rep_type_reg==exrep_type&&~rep_local_remote&&d_fsm_state==d_idle)
begin
v_rep_d=1'b1;
// flit_max_rep=4'b1000;
// en_flit_max_rep=1'b1;
msg={temp_rep_head_flit,data_read,32'h00000000};
nstate=m_idle;
mem_access_done=1'b1;
\t\t\t\t\t rst_rep_type=1'b1;
\t\t\t\t\t rst_req_type=1'b1;
end
if(rep_type_reg==exrep_type&&rep_local_remote&&m_rep_fsm_state==m_rep_idle)
begin
v_rep_out=1'b1;
flit_max_rep=4'b1000;
en_flit_max_rep=1'b1;
msg={temp_rep_head_flit,data_read,32'h00000000};
nstate=m_idle;
mem_access_done=1'b1;
\t\t\t\t\t rst_rep_type=1'b1;
\t\t\t\t\t rst_req_type=1'b1;
end
/////////////////////////////////////
/// gen nackrep
if(rep_type_reg==nackrep_type&&~rep_local_remote&&d_fsm_state==d_idle)
begin
v_rep_d=1'b1;
// flit_max_rep=4'b0000;
// en_flit_max_rep=1'b1;
msg={temp_rep_head_flit,data_read,32'h00000000};
nstate=m_idle;
mem_access_done=1'b1;
\t\t\t\t rst_rep_type=1'b1;
\t\t\t rst_req_type=1'b1;
end
if(rep_type_reg==nackrep_type&&rep_local_remote&&m_rep_fsm_state==m_rep_idle)
begin
v_rep_out=1'b1;
flit_max_rep=4'b0000;
en_flit_max_rep=1'b1;
msg={temp_rep_head_flit,data_read,32'h00000000};
nstate=m_idle;
mem_access_done=1'b1;
\t\t\t\t rst_rep_type=1'b1;
\t\t\t\t rst_req_type=1'b1;
end
////////////////////////////////////////////////
/// gen flushreq
if(req_type_reg==flushreq_type&&~req_local_remote&&d_fsm_state==d_idle)
begin
v_req_d=1'b1;
// flit_max_req=4'b0010;
// en_flit_max_req=1'b1;
msg={temp_req_head_flit,seled_addr,128'h0000};
nstate=m_idle;
mem_access_done=1'b1;
\t\t\t\t\t rst_rep_type=1'b1;
\t\t\t\t\t rst_req_type=1'b1;
end
if(req_type_reg==flushreq_type&&req_local_remote&&m_req_fsm_state==m_req_idle)
begin
v_req_out=1'b1;
flit_max_req=4'b0010;
en_flit_max_req=1'b1;
msg={temp_req_head_flit,seled_addr,128'h0000};
nstate=m_idle;
mem_access_done=1'b1;
\t\t\t\t\t rst_rep_type=1'b1;
\t\t\t\t\t rst_req_type=1'b1;
end
//////////////////////////////////////////////////
/// gen SCflushrep
if(rep_type_reg==SCflurep_type&&~rep_local_remote&&d_fsm_state==d_idle)
begin
v_rep_d=1'b1;
// flit_max_rep=4'b0000;
// en_flit_max_rep=1'b1;
msg={temp_rep_head_flit,data_read,32'h00000000};
nstate=m_idle;
mem_access_done=1'b1;
\t\t\t\t\t rst_rep_type=1'b1;
\t\t\t\t\t rst_req_type=1'b1;
end
if(rep_type_reg==SCflurep_type&&rep_local_remote&&m_rep_fsm_state==m_rep_idle)
begin
v_rep_out=1'b1;
flit_max_rep=4'b0000;
en_flit_max_rep=1'b1;
msg={temp_rep_head_flit,data_read,32'h00000000};
nstate=m_idle;
mem_access_done=1'b1;
\t\t\t\t\t rst_rep_type=1'b1;
\t\t\t\t\t rst_req_type=1'b1;
end
end
if(oneORmore==1'b1)
begin
//////////////////////////////////////////////////
/// gen SHexrep
if(rep_type_reg==SHexrep_type&&~rep_local_remote&&d_fsm_state==d_idle)
begin
v_rep_d=1'b1;
// flit_max_rep=4'b1000;
// en_flit_max_rep=1'b1;
msg={temp_rep_head_flit,data_read,32'h00000000};
set_rep_done=1'b1;
end
if(rep_type_reg==SHexrep_type&&rep_local_remote&&m_rep_fsm_state==m_rep_idle)
begin
v_rep_out=1'b1;
flit_max_rep=4'b1000;
en_flit_max_rep=1'b1;
msg={temp_rep_head_flit,data_read,32'h00000000};
set_rep_done=1'b1;
end
////////////////////////////////////////////////////
/// gen SCinvreq or invreq
if((req_type_reg==invreq_type||req_type_reg==SCinvreq_type)&&~req_local_remote&&d_fsm_state==d_idle)
begin
/* if(req_type==invreq_type)
thead[4:0]=invreq_cmd;
else
thead[4:0]=SCinvreq_cmd;
*/ ///
// flit_max=4'b0010;
// en_flit_max=1'b1;
v_req_d=1'b1;
msg={temp_req_head_flit,seled_addr,128'h0000};
set_req_done=1'b1;
end
if((req_type_reg==invreq_type||req_type_reg==SCinvreq_type)&&req_local_remote&&m_req_fsm_state==m_req_idle)
begin
/* if(req_type==invreq_type)
thead[4:0]=invreq_cmd;
else
thead[4:0]=SCinvreq_cmd;
*/ ///
flit_max_req=4'b0010;
en_flit_max_req=1'b1;
v_req_out=1'b1;
msg={temp_req_head_flit,seled_addr,128'h0000};
set_req_done=1'b1;
end
if(rep_done&&req_done||set_rep_done&&req_done||rep_done&&set_req_done)
begin
nstate=m_idle;
mem_access_done=1'b1;
\t\t\t\t\t rst_rep_type=1'b1;
\t\t\t\t\t rst_req_type=1'b1;
end
end
end
endcase
end
// fsm_memory_ctrl
always@(posedge clk)
begin
if(rst)
rstate<=m_idle;
else
\trstate<=nstate;
end
always@(posedge clk)
begin
if(rst)
req_done<=1'b0;
else if(set_req_done)
req_done<=1'b1;
end
always@(posedge clk)
begin
if(rst)
rep_done<=1'b0;
else if(set_rep_done)
rep_done<=1'b1;
end
always@(posedge clk)
begin
if(rst||rst_rep_type)
rep_type_reg<=4'b0000;
else if(en_rep_type)
rep_type_reg<=rep_type;
end
always@(posedge clk)
begin
if(rst||rst_req_type)
req_type_reg<=4'b0000;
else if(en_req_type)
req_type_reg<=req_type;
end
assign temp_req_head_flit_in1=t_req_head_sel?temp_req_head_flit_in:seled_head;
assign temp_rep_head_flit_in1=t_rep_head_sel?temp_rep_head_flit_in:seled_head;
always@(posedge clk)
begin
if(rst)
temp_req_head_flit<=16'h0000;
else if(en_temp_req_head_flit)
temp_req_head_flit<=temp_req_head_flit_in1;
end
always@(posedge clk)
begin
if(rst)
temp_rep_head_flit<=16'h0000;
else if(en_temp_rep_head_flit)
temp_rep_head_flit<=temp_rep_head_flit_in1;
end
assign seled_data=data_sel?infifos_data_in:local_d_data_in;
wire [127:0] data_out_mem_ram;
wire [5:0] state_out_mem_ram;
assign state_we_out=en_m_state_in;
assign data_we_out=en_m_data_in;
assign state_out_mem_ram=m_state_in;
assign data_out_mem_ram=seled_data;
// assign output to local inst cache or local data cache or mem_rep_out fifo or mem_rep_out fifo
// output to local data cache
assign {head_out_local_d,addr_out_local_d,data_out_local_d}=msg;
// output to local inst cache
assign data_out_local_i=msg[159:32];
// output to mem_OUT rep fifo
assign {head_out_rep_out,addr_out_rep_out,data_out_rep_out}=msg;
// output to mem_OUT req fifo
assign {head_out_req_out,addr_out_req_out}=msg[175:128]; // msg[127:0] is useless for req msg
endmodule
|
/// date:2016/3/9
/// engineer: ZhaiShaoMin
module m_download(//input
clk,
rst,
IN_flit_mem,
v_IN_flit_mem,
In_flit_ctrl,
mem_done_access,
//output
v_m_download,
m_download_flits,
m_download_state
);
//input
input clk;
input rst;
input [15:0] IN_flit_mem;
input v_IN_flit_mem;
input [1:0] In_flit_ctrl;
input mem_done_access;
//output
output v_m_download;
output [175:0] m_download_flits;
output [1:0] m_download_state;
//
reg [1:0] m_download_nstate;
reg [1:0] m_download_cstate;
parameter m_download_idle=2'b00;
parameter m_download_busy=2'b01;
parameter m_download_rdy=2'b10;
reg [15:0] flit_reg1;
reg [15:0] flit_reg2;
reg [15:0] flit_reg3;
reg [15:0] flit_reg4;
reg [15:0] flit_reg5;
reg [15:0] flit_reg6;
reg [15:0] flit_reg7;
reg [15:0] flit_reg8;
reg [15:0] flit_reg9;
reg [15:0] flit_reg10;
reg [15:0] flit_reg11;
assign m_download_state=m_download_cstate;
assign m_download_flits={flit_reg11,flit_reg10,flit_reg9,flit_reg8,flit_reg7,flit_reg6,flit_reg5,flit_reg4,flit_reg3,flit_reg2,flit_reg1};
reg v_m_download;
reg en_flit_m;
reg inc_cnt;
reg fsm_rst;
/// fsm of ic_download
always@(*)
begin
//default values
m_download_nstate=m_download_cstate;
v_m_download=1'b0;
en_flit_m=1'b0;
inc_cnt=1'b0;
fsm_rst=1'b0;
case(m_download_cstate)
m_download_idle:
begin
if(v_IN_flit_mem)
begin
m_download_nstate=m_download_busy;
en_flit_m=1'b1;
end
end
m_download_busy:
begin
if(v_IN_flit_mem)
begin
if(In_flit_ctrl==2'b11)
begin
en_flit_m=1'b1;
m_download_nstate=m_download_rdy;
end
en_flit_m=1'b1;
inc_cnt=1'b1;
end
end
m_download_rdy:
begin
v_m_download=1'b1;
if(mem_done_access)
begin
m_download_nstate=m_download_idle;
fsm_rst=1'b1;
end
end
endcase
end
reg [3:0] cnt;
reg [10:0] en_flits;
// select right inst_word_in
always@(*)
begin
case(cnt)
4'b0000:en_flits=11'b00000000001;
4'b0001:en_flits=11'b00000000010;
4'b0010:en_flits=11'b00000000100;
4'b0011:en_flits=11'b00000001000;
4'b0100:en_flits=11'b00000010000;
4'b0101:en_flits=11'b00000100000;
4'b0110:en_flits=11'b00001000000;
4'b0111:en_flits=11'b00010000000;
4'b1000:en_flits=11'b00100000000;
4'b1001:en_flits=11'b01000000000;
4'b1010:en_flits=11'b10000000000;
default:en_flits=11'b00000000000;
endcase
end
// 1st flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg1<=16'h0000;
else if(en_flits[0]&&en_flit_m)
flit_reg1<=IN_flit_mem;
end
//2ed flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg2<=16'h0000;
else if(en_flits[1]&&en_flit_m)
flit_reg2<=IN_flit_mem;
end
// 3rd flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg3<=16'h0000;
else if(en_flits[2]&&en_flit_m)
flit_reg3<=IN_flit_mem;
end
//4th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg4<=16'h0000;
else if(en_flits[3]&&en_flit_m)
flit_reg4<=IN_flit_mem;
end
//5th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg5<=16'h0000;
else if(en_flits[4]&&en_flit_m)
flit_reg5<=IN_flit_mem;
end
//6th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg6<=16'h0000;
else if(en_flits[5]&&en_flit_m)
flit_reg6<=IN_flit_mem;
end
//7th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg7<=16'h0000;
else if(en_flits[6]&&en_flit_m)
flit_reg7<=IN_flit_mem;
end
//8th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg8<=16'h0000;
else if(en_flits[7]&&en_flit_m)
flit_reg8<=IN_flit_mem;
end
//9th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg9<=16'h0000;
else if(en_flits[8]&&en_flit_m)
flit_reg9<=IN_flit_mem;
end
//10th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg10<=16'h0000;
else if(en_flits[9]&&en_flit_m)
flit_reg10<=IN_flit_mem;
end
//11th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg11<=16'h0000;
else if(en_flits[10]&&en_flit_m)
flit_reg11<=IN_flit_mem;
end
// fsm regs
always@(posedge clk)
begin
if(rst)
m_download_cstate<=2'b00;
else
m_download_cstate<=m_download_nstate;
end
//counter reg
always@(posedge clk)
begin
if(rst||fsm_rst)
cnt<=3'b000;
else if(inc_cnt)
cnt<=cnt+3'b001;
end
endmodule
|
/// date:2016/3/5 3/6 am: 10:57 done!
/// engineer:ZhaiShaoMin
/// module function: determine where head flits of req/rep go?
/// inst cache or data cache or memory according to
/// the fsm states of three kinds of downloadregs.
/// if ic_fsm_state is idle, then rep to inst cache is
/// free to go,same way for dc_downloadregs and mem_downloadregs
module arbiter_IN_node(//input
clk,
rst,
in_req_rdy,
in_rep_rdy,
req_ctrl_in,
rep_ctrl_in,
req_flit_in,
rep_flit_in,
ic_download_state_in,
dc_download_state_in,
mem_download_state_in,
//output
ack_req,
ack_rep,
v_ic,
flit_ic,
ctrl_ic,
v_dc,
flit_dc,
ctrl_dc,
v_mem,
flit_mem,
ctrl_mem
);
//input
input clk;
input rst;
input in_req_rdy;
input in_rep_rdy;
input [1:0] req_ctrl_in;
input [1:0] rep_ctrl_in;
input [15:0] req_flit_in;
input [15:0] rep_flit_in;
input [1:0] ic_download_state_in;
input [1:0] dc_download_state_in;
input [1:0] mem_download_state_in;
//output
output ack_req;
output ack_rep;
output v_ic;
output [15:0] flit_ic;
output [1:0] ctrl_ic;
output v_dc;
output [15:0] flit_dc;
output [1:0] ctrl_dc;
output v_mem;
output [15:0] flit_mem;
output [1:0] ctrl_mem;
reg [3:0] rep_nstate;
reg [2:0] req_nstate;
reg [3:0] rep_state;
reg [2:0] req_state;
// rep_cmd parameter
parameter instrep_cmd=5'b10100;
// rep fsm state parameter
parameter rep_idle=4'b0001;
parameter rep_ic_downloading=4'b0010;
parameter rep_dc_downloading=4'b0100;
parameter rep_mem_downloading=4'b1000;
// req fsm state parameter
parameter req_idle=3'b001;
parameter req_dc_downloading=3'b010;
parameter req_mem_downloading=3'b100;
// state parameter of donwload
parameter ic_idle=2'b00;
parameter dc_idle=2'b00;
parameter mem_idle=2'b00;
reg ack_req;
reg ack_rep;
reg v_ic;
reg v_dc_req;
reg v_mem_req;
reg v_dc_rep;
reg v_mem_rep;
reg [15:0] flit_ic;
reg [1:0] ctrl_ic;
reg [15:0] flit_dc_rep;
reg [1:0] ctrl_dc_rep;
reg [15:0] flit_mem_rep;
reg [1:0] ctrl_mem_rep;
reg [15:0] flit_dc_req;
reg [1:0] ctrl_dc_req;
reg [15:0] flit_mem_req;
reg [1:0] ctrl_mem_req;
reg rep_win;
/// fsm of arbiter_for_rep
always@(*)
begin
ack_rep=1'b0;
v_ic=1'b0;
v_dc_rep=1'b0;
v_mem_rep=1'b0;
flit_ic=16'h0000;
ctrl_ic=2'b00;
flit_dc_rep=16'h0000;
ctrl_dc_rep=2'b00;
flit_mem_rep=16'h0000;
ctrl_mem_rep=2'b00;
rep_nstate=rep_state;
rep_win=1'b0;
case(rep_state)
rep_idle:
begin
if(rep_flit_in[9:5]==instrep_cmd&&rep_ctrl_in==2'b01&&in_rep_rdy&&ic_download_state_in==ic_idle)
begin
ack_rep=1'b1;
v_ic=1'b1;
flit_ic=rep_flit_in;
ctrl_ic=rep_ctrl_in;
rep_nstate=rep_ic_downloading;
end
else if(rep_flit_in[13]==1'b0&&rep_ctrl_in==2'b01&&in_rep_rdy&&dc_download_state_in==dc_idle)
begin
ack_rep=1'b1;
v_dc_rep=1'b1;
flit_dc_rep=rep_flit_in;
ctrl_dc_rep=rep_ctrl_in;
rep_nstate=rep_dc_downloading;
rep_win=1'b1;
end
else if(rep_flit_in[13]==1'b1&&rep_ctrl_in==2'b01&&in_rep_rdy&&mem_download_state_in==mem_idle)
begin
ack_rep=1'b1;
v_mem_rep=1'b1;
flit_mem_rep=rep_flit_in;
ctrl_mem_rep=rep_ctrl_in;
rep_nstate=rep_mem_downloading;
rep_win=1'b1;
end
end
rep_ic_downloading:
begin
if(in_rep_rdy==1'b1)
begin
if(rep_ctrl_in==2'b11)
begin
rep_nstate=rep_idle;
end
ack_rep=1'b1;
v_ic=1'b1;
flit_ic=rep_flit_in;
ctrl_ic=rep_ctrl_in;
end
end
rep_dc_downloading:
begin
if(in_rep_rdy==1'b1)
begin
if(rep_ctrl_in==2'b11)
begin
rep_nstate=rep_idle;
end
ack_rep=1'b1;
v_dc_rep=1'b1;
flit_dc_rep=rep_flit_in;
ctrl_dc_rep=rep_ctrl_in;
end
end
rep_mem_downloading:
begin
if(in_rep_rdy==1'b1)
begin
if(rep_ctrl_in==2'b11)
begin
rep_nstate=rep_idle;
end
ack_rep=1'b1;
v_mem_rep=1'b1;
flit_mem_rep=rep_flit_in;
ctrl_mem_rep=rep_ctrl_in;
end
end
endcase
end
/// fsm of arbiter_for_req
always@(*)
begin
ack_req=1'b0;
v_dc_req=1'b0;
v_mem_req=1'b0;
flit_dc_req=req_flit_in;
ctrl_dc_req=req_ctrl_in;
flit_mem_req=req_flit_in;
ctrl_mem_req=req_ctrl_in;
req_nstate=req_state;
case(req_state)
req_idle:
begin
if(rep_win==1'b0&&req_ctrl_in==2'b01&&in_req_rdy)
begin
if(req_flit_in[13]==1'b0&&dc_download_state_in==dc_idle)
begin
ack_req=1'b1;
v_dc_req=1'b1;
flit_dc_req=req_flit_in;
ctrl_dc_req=req_ctrl_in;
req_nstate=req_dc_downloading;
end
else if(req_flit_in[13]==1'b1&&mem_download_state_in==mem_idle)
begin
ack_req=1'b1;
v_mem_req=1'b1;
flit_mem_req=req_flit_in;
ctrl_mem_req=req_ctrl_in;
req_nstate=req_mem_downloading;
end
end
end
req_dc_downloading:
begin
if(in_rep_rdy==1'b1)
begin
if(rep_ctrl_in==2'b11)
begin
req_nstate=req_idle;
end
ack_req=1'b1;
v_dc_req=1'b1;
flit_dc_req=rep_flit_in;
ctrl_dc_req=rep_ctrl_in;
end
end
req_mem_downloading:
begin
if(in_req_rdy)
begin
if(req_ctrl_in==2'b11)
begin
req_nstate=req_idle;
end
ack_req=1'b1;
v_mem_req=1'b1;
flit_mem_req=req_flit_in;
ctrl_mem_req=req_ctrl_in;
end
end
endcase
end
// fsm regs
always@(posedge clk)
begin
if(rst)
rep_state<=4'b0001;
else
rep_state<=rep_nstate;
end
always@(posedge clk)
begin
if(rst)
req_state<=3'b001;
else
req_state<=req_nstate;
end
// it will be valid ,either req or rep valid
assign v_dc=v_dc_req||v_dc_rep;
// it will be valid ,either req or rep valid
assign v_mem=v_mem_req||v_mem_rep;
assign flit_dc=v_dc_req?flit_dc_req:flit_dc_rep;
assign ctrl_dc=v_dc_req?ctrl_dc_req:ctrl_dc_rep;
assign flit_mem=v_mem_req?flit_mem_req:flit_mem_rep;
assign ctrl_mem=v_mem_req?ctrl_mem_req:ctrl_mem_rep;
endmodule
|
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
University of Illinois/NCSA
Open Source License
Copyright(C) 2004, The Board of Trustees of the
University of Illinois. All rights reserved
IVM 1.0
Developed by:
Advanced Computing Systems Group
Center for Reliable and High-Performance Computing
University of Illinois at Urbana-Champaign
http://www.crhc.uiuc.edu/ACS
-- with support from --
Center for Circuits and Systems Solutions (C2S2)
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the Software), to
deal with the Software without restriction, including without limitation the
rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
sell copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimers.
Redistributions in binary, gate-level, layout-level, or physical form must
reproduce the above copyright notice, this list of conditions and the
following disclaimers in the documentation and/or other materials provided
with the distribution.
Neither the names of Advanced Computing Systems Group, Center for Reliable
and High-Performance Computing, Center for Circuits and Systems Solution
(C2S2), University of Illinois at Urbana-Champaign, nor the names of its
contributors may be used to endorse or promote products derived from this
Software without specific prior written permission.
THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
WITH THE SOFTWARE.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
/*******************************************************************************
File: REGn.v
Description: This file contains the definition of a n-bit register
******************************************************************************/
`timescale 1ns/100ps
/*
* FUNC_NAME: REGn
*
* DESCRIPTION:
*\tDefinition for a n-bit register, asynch. reset
*
* INPUT:
*\treg_in - the value to be stored in the register on the next clock edge
*\tclk - the system clock
*
* OUTPUT:
*\treg_out - the current value of the register
*
* ASSUMPTIONS:
*
* AUTHOR:
*\tJustin Quek
* DATE:
*\t17-Apr-03
* LAST MODIFICATION:
*\tCreated modules
*/
module REGn(reg_out, clk, reset, reg_in);
parameter RegLen = 63;
// outputs
output [RegLen:0] reg_out;
// inouts
// special inputs
input clk;
input reset;
// inputs
input [RegLen:0] reg_in;
// internal vars
reg [RegLen:0] reg_val;
// assign vars
// assign outputs
assign reg_out = reg_val;
// instantiate other modules
// change the value of the register on every rising clock edge
always @(posedge clk)
begin
reg_val <= reg_in;
end
// async. reset
always @(posedge reset)
begin
reg_val = 'b0;
end
endmodule // REGn
/*
* FUNC_NAME: REGfn
*
* DESCRIPTION:
*\tDefinition for a n-bit register, with synchronous AND asynchronous reset signal
*
* INPUT:
*\treg_in - the value to be stored in the register on the next clock edge
*\tclk - the system clock
* flush - synchronous reset
*
* OUTPUT:
*\treg_out - the current value of the register
*
* ASSUMPTIONS:
*
* AUTHOR:
*\tJustin Quek
* DATE:
*\t19-Apr-03
* LAST MODIFICATION:
*\tCreated modules
*/
module REGfn(reg_out, clk, reset, flush, reg_in);
parameter RegLen = 63;
// outputs
output [RegLen:0] reg_out;
// inouts
// special inputs
input clk;
input reset;
input flush;
// inputs
input [RegLen:0] reg_in;
// internal vars
reg [RegLen:0] reg_val;
// assign vars
// assign outputs
assign reg_out = reg_val;
// instantiate other modules
// change the value of the register on every rising clock edge if the flush signal is low
always @(posedge clk)
begin
if (flush == 1'b1)
begin
reg_val <= 'b0;
end
else
begin
reg_val <= reg_in;
end
end
// async. reset
always @(posedge reset)
begin
reg_val = 'b0;
end
endmodule // REGfn
/*
* FUNC_NAME: REGln
*
* DESCRIPTION:
*\tDefinition for a n-bit register, with load signal and synchronous reset
*
* INPUT:
*\treg_in - the value to be stored in the register on the next clock edge
*\tclk - the system clock
* load - if we should store on the next clock edge
*
* OUTPUT:
*\treg_out - the current value of the register
*
* ASSUMPTIONS:
*
* AUTHOR:
*\tJustin Quek
* DATE:
*\t10-Apr-03
* LAST MODIFICATION:
*\tCreated modules
*/
module REGln(reg_out, clk, load, reset, reg_in);
parameter RegLen = 63;
// outputs
output [RegLen:0] reg_out;
// inouts
// special inputs
input clk;
input load;
input reset;
// inputs
input [RegLen:0] reg_in;
// internal vars
reg [RegLen:0] reg_val;
// assign vars
// assign outputs
assign reg_out = reg_val;
// instantiate other modules
// change the value of the register on every rising clock edge if the load signal is high
always @(posedge clk)
begin
if (reset == 1'b1)
begin
reg_val <= 'b0;
end
else if (load == 1'b1)
begin
reg_val <= reg_in;
end
end
endmodule // REGln
/*
* FUNC_NAME: REGan
*
* DESCRIPTION:
*\tDefinition for a n-bit register, with load signal and asynchronous reset
*
* INPUT:
*\treg_in - the value to be stored in the register on the next clock edge
*\tclk - the system clock
* load - if we should store on the next clock edge
*
* OUTPUT:
*\treg_out - the current value of the register
*
* ASSUMPTIONS:
*
* AUTHOR:
*\tJustin Quek
* DATE:
*\t10-Apr-03
* LAST MODIFICATION:
*\tCreated modules
*/
module REGan(reg_out, clk, load, reset, reg_in);
parameter RegLen = 63;
// outputs
output [RegLen:0] reg_out;
// inouts
// special inputs
input clk;
input load;
input reset;
// inputs
input [RegLen:0] reg_in;
// internal vars
reg [RegLen:0] reg_val;
// assign vars
// assign outputs
assign reg_out = reg_val;
// instantiate other modules
// change the value of the register on every rising clock edge if the load signal is high
always @(posedge clk)
begin
if (load == 1'b1)
begin
reg_val <= reg_in;
end
end
// async. reset
always @(posedge reset)
begin
reg_val = 'b0;
end
endmodule // REGan
|
//datae:2016/3/20
//engineer:zhaoshaomin
//module name: return address stack which is used to predict indirect branch target ,
// in MIPS such as JR or JALR(which i didn't implemente)
module core_ras(//input
clk,
rst,
//inst fetch stage prediction
en_call_in, //in my previous version ,it equals en_ret_addr_in
en_ret_in,//in my previous version ,it equals en_ret_addr_out
ret_addr_in,// which is gened by call inst
// decode stage recover something wrong,which caused by misprediction in btb, in RAS.
recover_push,//previous inst was preded as a JR inst incorrectly.
recover_push_addr,//push back the top return addr to RAs
recover_pop,// previous inst was preded as a jal inst incorrectly.
////output
//inst fetch stage poping top addr
ret_addr_out
);
//parameter
parameter ps2=2'b00;
parameter ps1=2'b01;
parameter pp1=2'b10;
parameter pp2=2'b11;
//input
input clk;
input rst;
input en_call_in;
input en_ret_in;
input [29:0] ret_addr_in;
input recover_push;
input [29:0] recover_push_addr;
input recover_pop;
//output
output [31:0] ret_addr_out;
reg en_RAS_ret;
reg en_RAS_rec;
reg en_pointer;
reg [1:0] ret_addr_out_src;
//reg of RAS
reg [29:0] RAS_1;
reg [29:0] RAS_2;
reg [29:0] RAS_3;
reg [29:0] RAS_4;
reg [29:0] RAS_5;
reg [29:0] RAS_6;
reg [29:0] RAS_7;
reg [29:0] RAS_8;
reg [2:0] pointer;
reg [1:0] pointer_src;
always@(posedge clk)
begin
if(rst)
pointer<=3'b000;
else if(en_pointer&&(pointer_src==ps2))
pointer<=pointer-3'b010;
else if(en_pointer&&(pointer_src==ps1))
pointer<=pointer-3'b001;
else if(en_pointer&&(pointer_src==pp1))
pointer<=pointer+3'b001;
else if(en_pointer&&(pointer_src==pp2))
pointer<=pointer+3'b010;
end
// reg of en vector
reg [7:0] en_pointer_P0;
reg [7:0] en_pointer_P1;
reg [7:0] en_pointer_P2;
//en vector functions
always@(*)
begin
//en_pointer_p0 means enable of pinter
case(pointer)
3'b000:en_pointer_P0=8'b00000001;
3'b001:en_pointer_P0=8'b00000010;
3'b010:en_pointer_P0=8'b00000100;
3'b011:en_pointer_P0=8'b00001000;
3'b100:en_pointer_P0=8'b00010000;
3'b101:en_pointer_P0=8'b00100000;
3'b110:en_pointer_P0=8'b01000000;
3'b111:en_pointer_P0=8'b10000000;
default:en_pointer_P0=8'b00000000;
endcase
//en_pointer_p1 means enable of pinter+1
case(pointer)
3'b111:en_pointer_P1=8'b00000001;
3'b000:en_pointer_P1=8'b00000010;
3'b001:en_pointer_P1=8'b00000100;
3'b010:en_pointer_P1=8'b00001000;
3'b011:en_pointer_P1=8'b00010000;
3'b100:en_pointer_P1=8'b00100000;
3'b101:en_pointer_P1=8'b01000000;
3'b110:en_pointer_P1=8'b10000000;
default:en_pointer_P1=8'b00000000;
endcase
//en_pointer_p2 means enable of pinter+2
case(pointer)
3'b111:en_pointer_P2=8'b00000010;
3'b000:en_pointer_P2=8'b00000100;
3'b001:en_pointer_P2=8'b00001000;
3'b010:en_pointer_P2=8'b00010000;
3'b011:en_pointer_P2=8'b00100000;
3'b100:en_pointer_P2=8'b01000000;
3'b101:en_pointer_P2=8'b10000000;
3'b110:en_pointer_P2=8'b00000001;
default:en_pointer_P2=8'b00000000;
endcase
end
//control signals for RAS
//reg of en_RAS_ret and en_RAS_rec
always@(*)
begin
//default values
en_RAS_ret=1'b0;
en_RAS_rec=1'b0;
pointer_src=pp2;
en_pointer=1'b0;
ret_addr_out_src=2'b11;
//////////////////////////////////
// when call_in meets recover_push
if(en_call_in&&recover_push)
begin
en_RAS_ret=1'b1;
en_RAS_rec=1'b1;
pointer_src=pp2;
en_pointer=1'b1;
end
else if(en_call_in&&!recover_push&&!recover_pop) //i'm not sure there is nothing wrong
begin
en_RAS_ret=1'b1;
pointer_src=pp1;
en_pointer=1'b1;
end
else if(!en_ret_in&&!en_call_in&&recover_push)
begin
en_RAS_rec=1'b1;
pointer_src=pp1;
en_pointer=1'b1;
end
///////////////////////////////////
//when ret_in meets recover_push
if(en_ret_in&&recover_push)
begin
ret_addr_out_src=2'b00;
end
else if(en_ret_in&&!recover_push&&!recover_pop)
begin
pointer_src=ps1;
en_pointer=1'b1;
ret_addr_out_src=2'b10;
end
////////////////////////////////////
///when call_in meets recover_pop
if(en_call_in&&recover_pop)
begin
en_RAS_ret=1'b1;
end
else if(!en_ret_in&&!en_call_in&&recover_pop)
begin
pointer_src=ps1;
en_pointer=1'b1;
end
////////////////////////////////////
//when ret_in meets recover_pop
if(en_ret_in&&recover_pop)
begin
ret_addr_out_src=2'b01;
pointer_src=ps2;
en_pointer=1'b1;
end
end
///////////////////////////////////
//write RAS_num
//RAS_1
always@(posedge clk)
begin
if(rst)
RAS_1<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[0]||en_pointer_P1[0]||en_pointer_P2[0]))
RAS_1<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[0]||en_pointer_P1[0]))
RAS_1<=recover_push_addr;
end
//RAS_2
always@(posedge clk)
begin
if(rst)
RAS_2<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[1]||en_pointer_P1[1]||en_pointer_P2[1]))
RAS_2<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[1]||en_pointer_P1[1]))
RAS_2<=recover_push_addr;
end
//RAS_3
always@(posedge clk)
begin
if(rst)
RAS_3<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[2]||en_pointer_P1[2]||en_pointer_P2[2]))
RAS_3<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[2]||en_pointer_P1[2]))
RAS_3<=recover_push_addr;
end
//RAS_4
always@(posedge clk)
begin
if(rst)
RAS_4<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[3]||en_pointer_P1[3]||en_pointer_P2[3]))
RAS_4<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[3]||en_pointer_P1[3]))
RAS_4<=recover_push_addr;
end
//RAS_5
always@(posedge clk)
begin
if(rst)
RAS_5<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[4]||en_pointer_P1[4]||en_pointer_P2[4]))
RAS_5<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[4]||en_pointer_P1[4]))
RAS_5<=recover_push_addr;
end
//RAS_6
always@(posedge clk)
begin
if(rst)
RAS_6<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[5]||en_pointer_P1[5]||en_pointer_P2[5]))
RAS_6<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[5]||en_pointer_P1[5]))
RAS_6<=recover_push_addr;
end
//RAS_7
always@(posedge clk)
begin
if(rst)
RAS_7<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[6]||en_pointer_P1[6]||en_pointer_P2[6]))
RAS_7<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[6]||en_pointer_P1[6]))
RAS_7<=recover_push_addr;
end
//RAS_8
always@(posedge clk)
begin
if(rst)
RAS_8<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[7]||en_pointer_P1[7]||en_pointer_P2[7]))
RAS_8<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[7]||en_pointer_P1[7]))
RAS_8<=recover_push_addr;
end
//read RAS port of pointer
reg [29:0] pointer_rd_ras;
always@(*)
begin
case(pointer)
3'b000:pointer_rd_ras=RAS_1;
3'b001:pointer_rd_ras=RAS_2;
3'b010:pointer_rd_ras=RAS_3;
3'b011:pointer_rd_ras=RAS_4;
3'b100:pointer_rd_ras=RAS_5;
3'b101:pointer_rd_ras=RAS_6;
3'b110:pointer_rd_ras=RAS_7;
3'b111:pointer_rd_ras=RAS_8;
default:pointer_rd_ras=30'hzzzzzzzz;
endcase
end
//read RAS port of pointere+1
reg [29:0] pointerP1_rd_ras;
always@(*)
begin
case(pointer)
3'b000:pointerP1_rd_ras=RAS_2;
3'b001:pointerP1_rd_ras=RAS_3;
3'b010:pointerP1_rd_ras=RAS_4;
3'b011:pointerP1_rd_ras=RAS_5;
3'b100:pointerP1_rd_ras=RAS_6;
3'b101:pointerP1_rd_ras=RAS_7;
3'b110:pointerP1_rd_ras=RAS_8;
3'b111:pointerP1_rd_ras=RAS_1;
default:pointerP1_rd_ras=30'hzzzzzzzz;
endcase
end
wire [29:0] ret_addr_out_temp;
assign ret_addr_out_temp=(ret_addr_out_src==2'b00)?recover_push_addr:
(ret_addr_out_src==2'b01)?pointer_rd_ras:
(ret_addr_out_src==2'b10)?pointerP1_rd_ras:30'hzzzzzzzz;
assign ret_addr_out={ret_addr_out_temp,2'b00};
endmodule
|
/// date:2016/3/9
/// engineer: ZhaiShaoMin
module dc_rep_upload(//input
clk,
rst,
dc_flits_rep,
v_dc_flits_rep,
flits_max,
en_flits_max,
rep_fifo_rdy,
//output
dc_flit_out,
v_dc_flit_out,
\t\t\t\t\t\t\t\t dc_ctrl_out,
dc_rep_upload_state
);
//input
input clk;
input rst;
input [175:0] dc_flits_rep;
input v_dc_flits_rep;
input [3:0] flits_max;
input en_flits_max;
input rep_fifo_rdy;
//output
output [15:0] dc_flit_out;
output v_dc_flit_out;
output [1:0] dc_ctrl_out;
output dc_rep_upload_state;
//parameter
parameter dc_rep_upload_idle=1'b0;
parameter dc_rep_upload_busy=1'b1;
//reg dc_req_nstate;
reg dc_rep_state;
reg [175:0] dc_rep_flits;
reg [3:0] sel_cnt;
reg v_dc_flit_out;
reg fsm_rst;
reg next;
reg en_flits_in;
reg inc_cnt;
reg [3:0] flits_max_reg;
reg [1:0] dc_ctrl_out;
assign dc_rep_upload_state=dc_rep_state;
always@(*)
begin
//default value
// dc_req_nstate=dc_req_state;
v_dc_flit_out=1'b0;
inc_cnt=1'b0;
fsm_rst=1'b0;
en_flits_in=1'b0;
next=1'b0;
dc_ctrl_out=2'b00;
case(dc_rep_state)
dc_rep_upload_idle:
begin
if(v_dc_flits_rep)
begin
en_flits_in=1'b1;
next=1'b1;
end
end
dc_rep_upload_busy:
begin
if(rep_fifo_rdy)
begin
if(sel_cnt==flits_max_reg)
\t\t\t\t begin
fsm_rst=1'b1;
\t\t\t\t\tdc_ctrl_out=2'b11;
\t\t\t\t\tend
\t\t\t\telse if(sel_cnt==3'b000)
\t\t\t\t dc_ctrl_out=2'b01;
\t\t\t\telse \t
\t\t\t\t dc_ctrl_out=2'b10;
inc_cnt=1'b1;
v_dc_flit_out=1'b1;
end
end
endcase
end
// fsm state
always@(posedge clk)
begin
if(rst||fsm_rst)
dc_rep_state<=1'b0;
else if(next)
dc_rep_state<=1'b1;
end
// flits regs
always@(posedge clk)
begin
if(rst||fsm_rst)
dc_rep_flits<=176'h0000;
else if(en_flits_in)
dc_rep_flits<=dc_flits_rep;
end
reg [15:0] dc_flit_out;
always@(*)
begin
case(sel_cnt)
4'b0000:dc_flit_out=dc_rep_flits[175:160];
4'b0001:dc_flit_out=dc_rep_flits[159:144];
4'b0010:dc_flit_out=dc_rep_flits[143:128];
4'b0011:dc_flit_out=dc_rep_flits[127:112];
4'b0100:dc_flit_out=dc_rep_flits[111:96];
4'b0101:dc_flit_out=dc_rep_flits[95:80];
4'b0110:dc_flit_out=dc_rep_flits[79:64];
4'b0111:dc_flit_out=dc_rep_flits[63:48];
4'b1000:dc_flit_out=dc_rep_flits[47:32];
4'b1001:dc_flit_out=dc_rep_flits[31:16];
4'b1010:dc_flit_out=dc_rep_flits[15:0];
default:dc_flit_out=dc_rep_flits[175:160];
endcase
end
// flits_max
always@(posedge clk)
begin
if(rst||fsm_rst)
flits_max_reg<=4'b0000;
else if(en_flits_max)
flits_max_reg<=flits_max;
end
///sel_counter
always@(posedge clk)
begin
if(rst||fsm_rst)
sel_cnt<=4'b0000;
else if(inc_cnt)
sel_cnt<=sel_cnt+4'b0001;
end
endmodule
|
/// date :2016/3/3
/// engineer :ZhaiShaoMin
/// module name: data path of FSM_upload_flit
/// module function : combination of needed state elment,which are controled by FSM_upload_flit
module upload_datapath(// input
clk,
rst,
clr_max,
clr_inv_ids,
clr_sel_cnt_inv,
clr_sel_cnt,
inc_sel_cnt,
inc_sel_cnt_inv,
en_flit_max_in,
en_for_reg,
en_inv_ids,
inv_ids_in,
dest_sel,
flit_max_in,
head_flit,
addrhi,
addrlo,
/* datahi1,
datalo1,
datahi2,
datalo2,
datahi3,
datalo3,
datahi4,
datalo4, */
//output
flit_out,
cnt_eq_max,
cnt_invs_eq_3,
cnt_eq_0,
inv_ids_reg_out,
sel_cnt_invs_out
);
///////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////
///////////////////Datapath Unit///////////////////////////////////////////////////
input clk;
input rst;
// input [3:0] inv_ids_in; // invreq vector used for generating every invreqs
// input en_for_reg; // enable for all kinds of flits regs
input [15:0] head_flit;
input [15:0] addrhi;
input [15:0] addrlo;
/* input [15:0] datahi1;
input [15:0] datalo1;
input [15:0] datahi2;
input [15:0] datalo2;
input [15:0] datahi3;
input [15:0] datalo3;
input [15:0] datahi4;
input [15:0] datalo4; */
input clr_max;
input clr_inv_ids;
input clr_sel_cnt_inv;
input clr_sel_cnt;
input inc_sel_cnt;
input inc_sel_cnt_inv;
input en_for_reg;
input en_inv_ids;
input [3:0] inv_ids_in;
input [3:0] flit_max_in;
input en_flit_max_in;
input dest_sel;
// output
output [15:0] flit_out;
output cnt_eq_max;
output cnt_invs_eq_3;
output cnt_eq_0;
output [3:0] inv_ids_reg_out;
output [1:0] sel_cnt_invs_out;
// register max_number of flits of a message
reg [3:0] flits_max;
always@(posedge clk)
begin
if(rst||clr_max)
flits_max<=4'b0000;
else if(en_flit_max_in)
flits_max<=flit_max_in;
end
// register current needed invreqs vector
reg [3:0] inv_ids_reg;
always@(posedge clk)
begin
if(rst||clr_inv_ids)
inv_ids_reg<=4'b0000;
else if(en_inv_ids)
inv_ids_reg<=inv_ids_in;
end
wire [3:0] inv_ids_reg_out;
assign inv_ids_reg_out=inv_ids_reg;
// selection counter for mux flit among 11 flit regs
reg [3:0] sel_cnt;
always@(posedge clk)
begin
if(rst||clr_sel_cnt)
sel_cnt<=4'b0000;
else if(inc_sel_cnt)
sel_cnt<=sel_cnt+4'b0001;
end
// selection counter for invreqs_vector generating different invreqs with different dest id
reg [1:0] sel_cnt_invs;
always@(posedge clk)
begin
if(rst||clr_sel_cnt_inv)
sel_cnt_invs<=2'b00;
else if(inc_sel_cnt_inv)
sel_cnt_invs<=sel_cnt_invs+2'b01;
end
wire [1:0] sel_cnt_invs_out;
assign sel_cnt_invs_out=sel_cnt_invs;
wire cnt_eq_0;
assign cnt_eq_0=(sel_cnt==4'b0000);
wire cnt_eq_max;
assign cnt_eq_max=(sel_cnt==flits_max);
wire cnt_invs_eq_3;
assign cnt_invs_eq_3=(sel_cnt_invs==2'b11);
reg [15:0] head_flit_reg;
reg [15:0] addrhi_reg;
reg [15:0] addrlo_reg;
/*reg [15:0] datahi1_reg;
reg [15:0] datalo1_reg;
reg [15:0] datahi2_reg;
reg [15:0] datalo2_reg;
reg [15:0] datahi3_reg;
reg [15:0] datalo3_reg;
reg [15:0] datahi4_reg;
reg [15:0] datalo4_reg; */
always@(posedge clk)
begin
if(rst)
begin
head_flit_reg<=16'h0000;
addrhi_reg<=16'h0000;
addrlo_reg<=16'h0000;
/* datahi1_reg<=16'h0000;
datalo1_reg<=16'h0000;
datahi2_reg<=16'h0000;
datalo2_reg<=16'h0000;
datahi3_reg<=16'h0000;
datalo3_reg<=16'h0000;
datahi4_reg<=16'h0000;
datalo4_reg<=16'h0000; */
end
else if(en_for_reg)
begin
head_flit_reg<=head_flit;
addrhi_reg<=addrhi;
addrlo_reg<=addrlo;
/* datahi1_reg<=datahi1;
datalo1_reg<=datahi1;
datahi2_reg<=datahi1;
datalo2_reg<=datalo2;
datahi3_reg<=datahi3;
datalo3_reg<=datalo3;
datahi4_reg<=datahi4;
datalo4_reg<=datalo4; */
end
end
// dest selection if 0 :scORinvreqs ;1 :wbORflushreqs
wire [1:0] dest_seled_id;
assign dest_seled_id=dest_sel?head_flit_reg[15:14]:sel_cnt_invs;
// select flit outputting to req fifo
reg [15:0] flit_seled_out;
always@(*)
begin
// if(en_sel)
// begin
case(sel_cnt)
4'b0000:flit_seled_out={dest_seled_id,head_flit_reg[13:0]};
4'b0001:flit_seled_out=addrhi_reg;
4'b0010:flit_seled_out=addrlo_reg;
/* 4'b0011:flit_seled_out=datahi1_reg;
4'b0100:flit_seled_out=datalo1_reg;
4'b0101:flit_seled_out=datahi2_reg;
4'b0110:flit_seled_out=datalo2_reg;
4'b0111:flit_seled_out=datahi3_reg;
4'b1000:flit_seled_out=datalo3_reg;
4'b1001:flit_seled_out=datahi4_reg;
4'b1010:flit_seled_out=datalo4_reg; */
default:flit_seled_out=head_flit_reg;
endcase
// end
end
assign flit_out=flit_seled_out;
endmodule
|
/************************************************************
date:2016/3/16
engineer:ZhaiShaoMin
module function: find out errors in the module
revision date:2016/3/31
*************************************************************/
`timescale 1ns/1ps
module tb_dc_req_upload();
//input
reg clk;
reg rst;
reg [47:0] dc_flits_req;
reg v_dc_flits_req;
reg req_fifo_rdy;
//output
wire [15:0] dc_flit_out;
wire v_dc_flit_out;
wire dc_req_upload_state;
//instantiate the uut
dc_req_upload uut (//input
.clk(clk),
.rst(rst),
.dc_flits_req(dc_flits_req),
.v_dc_flits_req(v_dc_flits_req),
.req_fifo_rdy(req_fifo_rdy),
//output
.dc_flit_out(dc_flit_out),
.v_dc_flit_out(v_dc_flit_out),
.dc_req_upload_state(dc_req_upload_state)
);
// store the simulation log into log_file
integer log_file;
// Initialize Inputs
initial begin
clk=1\'b0;
rst=1\'b0;
dc_flits_req=48\'h000000000000;
v_dc_flits_req=1\'b0;
req_fifo_rdy=1\'b0;
log_file=$fopen("log_tb_arbiter_req_upload");
end
always #20 clk=~clk;
`define clk_step #40;
initial begin
/////// dc_req_upload test /////////
// First reset all //
$display("(%t) Initializing...", $time);
$fdisplay(log_file, "(%t) Initializing...", $time);
rst=1;
`clk_step
rst=0;
`clk_step
///////////////////////////////////////////////////////////////////////////////////////
//////////////////////only need to test shreq or exreq both 3 flits long///////////////
dc_flits_req=48\'h123456789abc;
v_dc_flits_req=1\'b1;
`clk_step
//inter regs should have hold the flits
req_fifo_rdy=1\'b0;
$display("(%t),the flit from dc_req_upload is %h and v_dc_flit_out is %b ",$time,dc_flit_out,v_dc_flit_out);
$fdisplay(log_file,"(%t),the flit from dc_req_upload is %h and v_dc_flit_out is %b ",$time,dc_flit_out,v_dc_flit_out);
`clk_step
v_dc_flits_req=1\'b0;
//since last cycle req fifo rdy is not valid , v_dc_flit_out will be not valid
req_fifo_rdy=1\'b1;
$display("(%t),the flit from dc_req_upload is %h and v_dc_flit_out is %b ",$time,dc_flit_out,v_dc_flit_out);
$fdisplay(log_file,"(%t),the flit from dc_req_upload is %h and v_dc_flit_out is %b ",$time,dc_flit_out,v_dc_flit_out);
`clk_step
//since last cycle req fifo rdy is not valid , v_dc_flit_out will be valid
req_fifo_rdy=1\'b1;
$display("(%t),the flit from dc_req_upload is %h and v_dc_flit_out is %b ",$time,dc_flit_out,v_dc_flit_out);
$fdisplay(log_file,"(%t),the flit from dc_req_upload is %h and v_dc_flit_out is %b ",$time,dc_flit_out,v_dc_flit_out);
`clk_step
//since last cycle req fifo rdy is not valid , v_dc_flit_out will be valid
dc_flits_req=48\'h2016c0de0330;
v_dc_flits_req=1\'b1;
req_fifo_rdy=1\'b0;
$display("(%t),the flit from dc_req_upload is %h and v_dc_flit_out is %b ",$time,dc_flit_out,v_dc_flit_out);
$fdisplay(log_file,"(%t),the flit from dc_req_upload is %h and v_dc_flit_out is %b ",$time,dc_flit_out,v_dc_flit_out);
`clk_step
//since last cycle req fifo rdy is not valid , v_dc_flit_out will be not valid
req_fifo_rdy=1\'b1;
$display("(%t),the flit from dc_req_upload is %h and v_dc_flit_out is %b ",$time,dc_flit_out,v_dc_flit_out);
$fdisplay(log_file,"(%t),the flit from dc_req_upload is %h and v_dc_flit_out is %b ",$time,dc_flit_out,v_dc_flit_out);
`clk_step
//since last cycle req fifo rdy is not valid , v_dc_flit_out will be valid
`clk_step
//till now dc_req_upload has been empty,so flits will be push into ic_upload ,but it\'s not the to pop one flit to req fifo!
req_fifo_rdy=1\'b1;
`clk_step
//this cycle head flit will be poped to req fifo
req_fifo_rdy=1\'b1;
`clk_step
//due to not being valid ,second flit won\'t be poped to req fifo
req_fifo_rdy=1\'b0;
`clk_step
//this cycle second flit will be poped to req fifo
req_fifo_rdy=1\'b1;
`clk_step
//this cycle third flit will be poped to req fifo
req_fifo_rdy=1\'b1;
`clk_step
//this time upload_rs(=>upload_reserve station) should become empty!
`clk_step
$stop;
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////GENERIC COUNTER////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//Generic n-bit incrementable counter
module counter (CLK, //input assert posedge to increment/decrement counter
EN, //input enable signal (assert to allow counter to count)
RST, //input assert to reset counter
DONE, //output asserted if count is reached
COUNT); //output [n:0] current count
//////////MODULE PARAMETERS//////////
parameter n=4, //width of counter
start=0, //starting value of counter
final=8, //ending value of counter
step=1; //step to increment by (set to -1 for decrementing)
//////////SIGNALS ///////////////////
input CLK;
input EN;
input RST;
output DONE;
output [n-1:0] COUNT;
///////////IMPLEMENTATION//////////////////////
reg [n-1:0] COUNT;
always @ (posedge CLK or posedge RST)
begin
if (RST)
#5 COUNT = start;
else if (EN)
#5 COUNT = COUNT + step;
end
assign DONE = (COUNT == final);
endmodule
|
/// date: 2016/2/19 11:00-17:50
/// engineer: ZhaiShaoMin
/// module name: arbiter_4_deq
/// module function: decide which fifo among pass fifos and OUT_local fifos can really deq flit,ctrl and next_node infos;
module arbiter_4_deq (
//input
clk,
rst,
pass_req_empty,
pass_rep_empty,
OUT_local_req_empty,
OUT_local_rep_empty,
OUT_rep_length_code,
en_local_req,
en_local_rep,
en_pass_req,
en_pass_rep,
used_slots_pass_req,
used_slots_pass_rep,
next_pass_req,
next_pass_rep,
next_local_req,
next_local_rep,
//output
select
);
//input
input clk;
input rst;
input pass_req_empty; //local node: pass req fifo is empty
input pass_rep_empty; //local node: pass rep fifo is empty
input OUT_local_req_empty; //local node: OUT_local req fifo is empty
input OUT_local_rep_empty; //local node: OUT_local rep fifo is empty
input en_local_req; //IN_local_req_fifo of next node says I can receive a flit
input en_local_rep; //IN_local_rep_fifo of next node says I can receive a flit
input en_pass_req; //pass req fifo of next node says i can receive a flit now
input en_pass_rep; //pass rep fifo of next node says i can receive a flit now
input [3:0] used_slots_pass_req; //pass req fifo of next node says how many slots I have used ,avoiding deadlock
input [3:0] used_slots_pass_rep; //pass rep fifo of next node says how many slots I have used ,avoiding deadlock
input next_pass_req; //local node: flit in the head of pass req fifo says I am a flit to next node if it's 1;
input next_pass_rep; //local node: flit in the head of pass rep fifo says I am a flit to next node if it's 1;
input next_local_req; //local node: flit in the head of OUT_local req fifo says I am a flit to next node if it's 1;
input next_local_rep; //local node: flit in the head of OUT_local rep fifo says I am a flit to next node if it's 1;
input [1:0] OUT_rep_length_code;
//output
output [3:0] select; // one-hot encode select 4'b0001 : pass_rep
reg [3:0] select; // 4'b0010 : local_rep
// 4'b0100 ? pass_req
// 4'b1000 ? local_req
//local fifos busy flag
reg local_pass_req_busy;
reg local_pass_rep_busy;
reg OUT_req_busy;
reg OUT_rep_busy;
reg set_local_pass_req_busy;
reg set_local_pass_rep_busy;
reg set_OUT_req_busy;
reg set_OUT_rep_busy;
// set pass_req_busy
always@(posedge clk)
begin
if(rst==1'b0)
local_pass_req_busy<=1'b0;
else if(set_local_pass_req_busy==1'b1)
local_pass_req_busy<=1'b1;
end
// set pass_rep_busy
always@(posedge clk)
begin
if(rst==1'b0)
local_pass_rep_busy<=1'b0;
else if(set_local_pass_rep_busy==1'b1)
local_pass_rep_busy<=1'b1;
end
// set OUT_req_busy
always@(posedge clk)
begin
if(rst==1'b0)
OUT_req_busy<=1'b0;
else if(set_OUT_req_busy==1'b1)
OUT_req_busy<=1'b1;
end
// set OUT_rep_busy
always@(posedge clk)
begin
if(rst==1'b0)
OUT_rep_busy<=1'b0;
else if(set_OUT_rep_busy==1'b1)
OUT_rep_busy<=1'b1;
end
// temp dest fifo id of local fifos
reg [1:0] pass_req_temp_dest_id;
reg [1:0] pass_rep_temp_dest_id;
reg [1:0] OUT_req_temp_dest_id;
reg [1:0] OUT_rep_temp_dest_id;
reg [1:0] set_OUT_rep_dest_id_in;
reg [1:0] set_OUT_req_dest_id_in;
reg [1:0] set_pass_rep_dest_id_in;
reg [1:0] set_pass_req_dest_id_in;
reg set_OUT_rep_dest_id;
reg set_OUT_req_dest_id;
reg set_pass_rep_dest_id;
reg set_pass_req_dest_id;
// set_pass_req_dest_id
always@(posedge clk)
begin
if(rst)
pass_req_temp_dest_id<=2'b00;
else if(set_pass_req_dest_id)
pass_req_temp_dest_id<=set_pass_req_dest_id_in;
end
// set_pass_rep_dest_id
always@(posedge clk)
begin
if(rst)
pass_rep_temp_dest_id<=2'b00;
else if(set_pass_rep_dest_id)
pass_rep_temp_dest_id<=set_pass_rep_dest_id_in;
end
// set_OUT_req_dest_id
always@(posedge clk)
begin
if(rst)
OUT_req_temp_dest_id<=2'b00;
else if(set_OUT_req_dest_id)
OUT_req_temp_dest_id<=set_OUT_req_dest_id_in;
end
// set_OUT_rep_dest_id
always@(posedge clk)
begin
if(rst)
OUT_rep_temp_dest_id<=2'b00;
else if(set_OUT_rep_dest_id)
OUT_rep_temp_dest_id<=set_OUT_rep_dest_id_in;
end
wire local_pass_req_dest_seled_rdy;
wire local_pass_rep_dest_seled_rdy;
wire OUT_req_dest_seled_rdy;
wire OUT_rep_dest_seled_rdy;
///////////////////////////////////////////////////////////////////////////////////////////////////////////
/////select every src fifo's ready signal of dest fifo to avoiding overflow in the fifos of next node ////
MUXn_4_1 #(0) local_pass_req_dest_seled_rdy_dut(.mux_in0(en_local_req),
.mux_in1(en_local_rep),
.mux_in2(en_pass_req),
.mux_in3(en_pass_rep),
.mux_sel(pass_req_temp_dest_id),
.mux_out(local_pass_req_dest_seled_rdy));
MUXn_4_1 #(0) local_pass_rep_dest_seled_rdy_dut(.mux_in0(en_local_req),
.mux_in1(en_local_rep),
.mux_in2(en_pass_req),
.mux_in3(en_pass_rep),
.mux_sel(pass_rep_temp_dest_id),
.mux_out(local_pass_rep_dest_seled_rdy));
MUXn_4_1 #(0) OUT_req_dest_seled_rdy_dut (.mux_in0(en_local_req),
.mux_in1(en_local_rep),
.mux_in2(en_pass_req),
.mux_in3(en_pass_rep),
.mux_sel(OUT_req_temp_dest_id),
.mux_out(OUT_req_dest_seled_rdy));
MUXn_4_1 #(0) OUT_rep_dest_seled_rdy_dut (.mux_in0(en_local_req),
.mux_in1(en_local_rep),
.mux_in2(en_pass_req),
.mux_in3(en_pass_rep),
.mux_sel(OUT_rep_temp_dest_id),
.mux_out(OUT_rep_dest_seled_rdy));
// busy flag of next node
reg next_pass_req_busy;
reg next_pass_rep_busy;
reg next_in_req_busy;
reg next_in_rep_busy;
reg set_next_pass_req_busy;
reg set_next_pass_rep_busy;
reg set_next_in_req_busy;
reg set_next_in_rep_busy;
// set next_pass_req_busy
always@(posedge clk)
begin
if(rst==1'b0)
next_pass_req_busy<=1'b0;
else if(set_next_pass_req_busy==1'b1)
next_pass_req_busy<=1'b1;
end
// set next_pass_rep_busy
always@(posedge clk)
begin
if(rst==1'b0)
next_pass_rep_busy<=1'b0;
else if(set_next_pass_rep_busy==1'b1)
next_pass_rep_busy<=1'b1;
end
// set next_in_req_busy
always@(posedge clk)
begin
if(rst==1'b0)
next_in_req_busy<=1'b0;
else if(set_next_in_req_busy==1'b1)
next_in_req_busy<=1'b1;
end
// set next_in_rep_busy
always@(posedge clk)
begin
if(rst==1'b0)
next_in_rep_busy<=1'b0;
else if(set_next_in_rep_busy==1'b1)
next_in_rep_busy<=1'b1;
end
reg pass_rep_go;
reg local_rep_go;
reg pass_req_go;
reg local_req_go;
//priority reg
reg [3:0] priority_1;
reg [2:0] priority_2;
reg [1:0] priority_3;
// fake en_priority
reg en_priority_1;
reg en_priority_2;
reg en_priority_3;
//reg en_priority_4;
wire [3:0] en;
//assign
wire [3:0] temp_priority_1;
wire [2:0] temp_priority_2;
wire [1:0] temp_priority_3;
//assign
assign temp_priority_1=priority_1;
assign temp_priority_2=priority_2;
assign temp_priority_3=priority_3;
//////////////////////////////////////////////////////////////////////////////////
///// here need some revision/////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////
// from unused to used
always@( * )
begin
local_req_go=1'b0;
\t local_rep_go=1'b0;
\t pass_req_go=1'b0;
\t pass_rep_go=1'b0;
if(next_local_rep==1'b0&&~next_pass_rep_busy&&~OUT_rep_busy&&(!OUT_local_rep_empty))
begin
if(used_slots_pass_rep<=4'b0100&&OUT_rep_length_code==2'b11)
// out local rep not empty, unused slots in pass rep of next node more than 11
local_rep_go=1'b1;
if(used_slots_pass_rep<=4'b0110&&OUT_rep_length_code==2'b10)
// out local rep not empty, unused slots in pass rep of next node more than 9
local_rep_go=1'b1;
if(used_slots_pass_rep<=4'b1100&&OUT_rep_length_code==2'b01)
// out local rep not empty, unused slots in pass rep of next node more than 3
local_rep_go=1'b1;
if(used_slots_pass_rep<=4'b1110&&OUT_rep_length_code==2'b00)
// out local rep not empty, unused slots in pass rep of next node more than 1
local_rep_go=1'b1;
end
\t\t
if(!OUT_local_rep_empty&&next_local_rep&&~next_in_rep_busy&&~OUT_rep_busy)
local_rep_go=1'b1;
if(!OUT_local_req_empty&&~next_local_req&&~next_pass_req_busy&&~OUT_req_busy)
//
//
// i'm afraid of some revision here i made causing problems
//
//
local_req_go=1'b1;
if(!OUT_local_req_empty&&next_local_req&&~next_in_req_busy&&~OUT_req_busy)
local_req_go=1'b1;
if(!pass_rep_empty&&~next_pass_rep&&~next_pass_rep_busy&&~local_pass_rep_busy)
pass_rep_go=1'b1;
if(!pass_rep_empty&&next_pass_rep&&~next_in_rep_busy&&~local_pass_rep_busy)
pass_rep_go=1'b1;
if(!pass_req_empty&&~next_pass_req&&~next_pass_req_busy&&~local_pass_req_busy)
pass_req_go=1'b1;
if(!pass_req_empty&&~next_pass_req&&~next_in_req_busy&&~local_pass_req_busy)
pass_req_go=1'b1;
end
// arbitrate dest fifos for ready and safe source fifos
reg priority_arbiter1;
reg priority_arbiter2;
reg update_arbiter1;
reg update_arbiter2;
always@(posedge clk)
begin
if(rst)
priority_arbiter1<=1'b0;
else if(update_arbiter1)
priority_arbiter1<=~priority_arbiter1;
end
always@(posedge clk)
begin
if(rst)
priority_arbiter2<=1'b0;
else if(update_arbiter2)
priority_arbiter2<=~priority_arbiter2;
end
/// arbitrate local rep fifo and pass rep fifo
always@(*)
begin
//default values
set_next_pass_rep_busy=1'b0;
set_local_pass_rep_busy=1'b0;
set_pass_rep_dest_id_in=2'b00;
set_pass_rep_dest_id=1'b0;
set_next_in_rep_busy=1'b0;
set_OUT_rep_busy=1'b0;
set_OUT_rep_dest_id_in=2'b00;
set_OUT_rep_dest_id=1'b0;
update_arbiter1=1'b0;
/////////////////////////////////////////////////////////////////////////////////
///////NOTE: the order if block looks like 4 bits ////////////
////// {local_rep_go,pass_rep_go,next_local_rep,next_pass_rep} ///////////
////// order 0000,0001,0010... //////////
/////////////////////////////////////////////////////////////////////////////////
// if (00xx) // 4 case
// if local rep can't go anywhere ,then pass can go anywhere it want!
if(~local_rep_go&&pass_rep_go&&~next_pass_rep) // 2 case 01x0
begin
set_next_pass_rep_busy=1'b1;
set_local_pass_rep_busy=1'b1;
set_pass_rep_dest_id_in=2'b11;
set_pass_rep_dest_id=1'b1;
end
// if local rep can't go anywhere ,then pass can go anywhere it want!
if(~local_rep_go&&pass_rep_go&&next_pass_rep) // 2 case 01x1
begin
set_next_in_rep_busy=1'b1;
set_local_pass_rep_busy=1'b1;
set_pass_rep_dest_id_in=2'b01;
set_pass_rep_dest_id=1'b1;
end
// if local rep want and can go to next pass rep fifo,then he will be allowed to go on.
if(local_rep_go&&~pass_rep_go&&~next_local_rep) //2 case 100x
begin
set_next_pass_rep_busy=1'b1;
set_OUT_rep_busy=1'b1;
set_OUT_rep_dest_id_in=2'b11;
set_OUT_rep_dest_id=1'b1;
end
// if local rep want and can go to next local rep fifo,then he will be allowed to go on.
if(local_rep_go&&~pass_rep_go&&next_local_rep) //2 case 101x
begin
set_next_in_rep_busy=1'b1;
set_OUT_rep_busy=1'b1;
set_OUT_rep_dest_id_in=2'b01;
set_OUT_rep_dest_id=1'b1;
end
// if local rep want to go to pass rep of next,it will go
if(local_rep_go&&pass_rep_go&&~next_local_rep) //2 case 110x
begin
set_next_pass_rep_busy=1'b1;
set_OUT_rep_busy=1'b1;
set_OUT_rep_dest_id_in=2'b11;
set_OUT_rep_dest_id=1'b1;
end
// if local rep and pass rep want go to differrent fifo of next node, they both succeed go on.
if(local_rep_go&&pass_rep_go&&next_local_rep&&~next_pass_rep) //1 case 1110
begin
set_next_in_rep_busy=1'b1;
set_OUT_rep_busy=1'b1;
set_OUT_rep_dest_id_in=2'b01;
set_OUT_rep_dest_id=1'b1;
set_next_pass_rep_busy=1'b1;
set_local_pass_rep_busy=1'b1;
set_pass_rep_dest_id_in=2'b11;
set_pass_rep_dest_id=1'b1;
end
// if local rep and pass rep both want to go to local rep of next node ,priority_arbiter1 will decide who win!
if(local_rep_go&&pass_rep_go&&next_local_rep&&next_pass_rep) // 1 case 1111
begin
update_arbiter1=1'b1;
if(priority_arbiter1)
begin
set_next_in_rep_busy=1'b1;
set_OUT_rep_busy=1'b1;
set_OUT_rep_dest_id_in=2'b01;
set_OUT_rep_dest_id=1'b1;
end
else
begin
set_next_in_rep_busy=1'b1;
set_local_pass_rep_busy=1'b1;
set_pass_rep_dest_id_in=2'b01;
set_pass_rep_dest_id=1'b1;
end
end
end
//// arbitrate local req fifo and pass req fifo
always@(*)
begin
//default values
set_next_in_req_busy=1'b0;
set_OUT_req_busy=1'b0;
set_OUT_req_dest_id_in=2'b00;
set_OUT_req_dest_id=1'b0;
set_next_pass_req_busy=1'b0;
set_local_pass_req_busy=1'b0;
set_pass_req_dest_id_in=2'b00;
set_pass_req_dest_id=1'b0;
\t\tupdate_arbiter2=1'b0;
/////////////////////////////////////////////////////////////////////////////////
///////NOTE: the order if block looks like 4 bits ////////////
////// {local_req_go,pass_req_go,next_local_req,next_pass_req} ///////////
////// order 0000,0001,0010... //////////
/////////////////////////////////////////////////////////////////////////////////
// if (00xx) // 4 case
// if local req can't go anywhere ,then pass can go anywhere it want!
if(~local_req_go&&pass_req_go&&~next_pass_req) // 2 case 01x0
begin
set_next_pass_req_busy=1'b1;
set_local_pass_req_busy=1'b1;
set_pass_req_dest_id_in=2'b10;
set_pass_req_dest_id=1'b1;
end
// if local req can't go anywhere ,then pass can go anywhere it want!
if(~local_req_go&&pass_req_go&&next_pass_req) // 2 case 01x1
begin
set_next_in_req_busy=1'b1;
set_local_pass_req_busy=1'b1;
set_pass_req_dest_id_in=2'b00;
set_pass_req_dest_id=1'b1;
end
// if local req want and can go to next pass req fifo,then he will be allowed to go on.
if(local_req_go&&~pass_req_go&&~next_local_req) //2 case 100x
begin
set_next_pass_req_busy=1'b1;
set_OUT_req_busy=1'b1;
set_OUT_req_dest_id_in=2'b10;
set_OUT_req_dest_id=1'b1;
end
// if local req want and can go to next local req fifo,then he will be allowed to go on.
if(local_req_go&&~pass_req_go&&next_local_req) //2 case 101x
begin
set_next_in_req_busy=1'b1;
set_OUT_req_busy=1'b1;
set_OUT_req_dest_id_in=2'b00;
set_OUT_req_dest_id=1'b1;
end
// if local req want to go to pass req of next,it will go
if(local_req_go&&pass_req_go&&~next_local_req) //2 case 110x
begin
set_next_pass_req_busy=1'b1;
set_OUT_req_busy=1'b1;
set_OUT_req_dest_id_in=2'b10;
set_OUT_req_dest_id=1'b1;
end
// if local req and pass req want go to differrent fifo of next node, they both succeed go on.
if(local_req_go&&pass_req_go&&next_local_req&&~next_pass_req) //1 case 1110
begin
set_next_in_req_busy=1'b1;
set_OUT_req_busy=1'b1;
set_OUT_req_dest_id_in=2'b00;
set_OUT_req_dest_id=1'b1;
set_next_pass_req_busy=1'b1;
set_local_pass_req_busy=1'b1;
set_pass_req_dest_id_in=2'b10;
set_pass_req_dest_id=1'b1;
end
// if local req and pass req both want to go to local req of next node ,priority_arbiter1 will decide who win!
if(local_req_go&&pass_req_go&&next_local_req&&next_pass_req) // 1 case 1111
begin
update_arbiter2=1'b1;
if(priority_arbiter2)
begin
set_next_in_req_busy=1'b1;
set_OUT_req_busy=1'b1;
set_OUT_req_dest_id_in=2'b00;
set_OUT_req_dest_id=1'b1;
end
else
begin
set_next_in_req_busy=1'b1;
set_local_pass_req_busy=1'b1;
set_pass_req_dest_id_in=2'b00;
set_pass_req_dest_id=1'b1;
end
end
end
assign en[3:0]={OUT_req_busy&&OUT_req_dest_seled_rdy,local_pass_req_busy&&local_pass_req_dest_seled_rdy,
OUT_rep_busy&&OUT_rep_dest_seled_rdy,local_pass_rep_busy&&local_pass_rep_dest_seled_rdy};
always@(en[3:0] or temp_priority_1 or temp_priority_2 or temp_priority_3)
begin
//init
en_priority_1=0;
en_priority_2=0;
en_priority_3=0;
// en_priority_4=0;
select=4'b0000;
//behave logic judgement
if(en[3:0]==4'b1111)
begin
select=temp_priority_1;
en_priority_1=1;
end
else if(en[3:0]==4'b1110)
begin
select={temp_priority_2,1'b0};
en_priority_2=1;
end
else if(en[3:0]==4'b1101)
begin
select={temp_priority_2[1:0],1'b0,temp_priority_2[2]};
en_priority_2=1;
end
else if(en[3:0]==4'b1011)
begin
select={temp_priority_2[0],1'b0,temp_priority_2[2:1]};
en_priority_2=1;
end
else if(en[3:0]==4'b0111)
begin
select={1'b0,temp_priority_2};
en_priority_2=1;
end
else if(en[3:0]==4'b1100)
begin
select={temp_priority_3,1'b0,1'b0};
en_priority_3=1;
end
else if(en[3:0]==4'b1001)
begin
select={temp_priority_3[0],1'b0,1'b0,temp_priority_3[1]};
en_priority_3=1;
end
else if(en[3:0]==4'b0011)
begin
select={1'b0,1'b0,temp_priority_3};
en_priority_3=1;
end
else if(en[3:0]==4'b0110)
begin
select={1'b0,temp_priority_3,1'b0};
en_priority_3=1;
end
else if(en[3:0]==4'b1010)
begin
select={temp_priority_3[1],1'b0,temp_priority_3[0],1'b0};
en_priority_3=1;
end
else if(en[3:0]==4'b0101)
begin
select={1'b0,temp_priority_3[1],1'b0,temp_priority_3[0]};
en_priority_3=1;
end
else
begin
select=en;
end
end
//priority_1 reg
always@(posedge clk or posedge rst)
begin
if(rst)
priority_1=0001;
else if(en_priority_1)
priority_1={priority_1[2:0],priority_1[3]};
end
//priority_2 reg
always@(posedge clk or posedge rst)
begin
if(rst)
priority_2=3'b001;
else if(en_priority_2)
priority_2={priority_2[1:0],priority_2[2]};
end
//priority_3 reg
always@(posedge clk or posedge rst)
begin
if(rst)
priority_3=2'b01;
else if(en_priority_3)
priority_3={priority_3[0],priority_3[1]};
end
endmodule
|
//date:2016/3/19
// engineer:ZhaiShaoMin
//module name:BTB module used to cache recent target of jumps and branches
module core_btb(//input
clk,
rst,
pc,
update_btb_tag,
update_btb_target,
btb_target_in,
btb_type_in,
PHT_pred_taken,
//output
btb_type_out,
btb_target_out,
btb_v,
en_btb_pred // only valid when both btb_v and PHT_pred_taken valid are vallid
);
//parameter
parameter pc_tag_width=11;
parameter btb_target_width=32;
parameter btb_depth=64;
parameter BTB_TARGET_INIT=32'h00000000;
parameter BTB_TAG_INIT=11'b00000000000;
//input
input clk;
input rst;
input [31:0] pc;
input [31:0] btb_target_in;
input update_btb_target;
input update_btb_tag;
input [1:0] btb_type_in;
input PHT_pred_taken;
//output
output btb_v;
output [31:0] btb_target_out;
output [1:0] btb_type_out;
output en_btb_pred;
//ram of btb
reg [pc_tag_width-1:0] btb_tag [btb_depth-1:0];
reg [btb_target_width-1:0] btb_target [btb_depth-1:0];
// gen btb_tag_in
wire [5:0] pc_index;
assign pc_index=pc[7:2];
wire [10:0] btb_tag_in;
assign btb_tag_in={pc[29]^pc[28],pc[27]^pc[26],pc[25]^pc[24],pc[23]^pc[22],
pc[21]^pc[20],pc[19]^pc[18],pc[17]^pc[16],pc[15]^pc[14],
pc[13]^pc[12],pc[11]^pc[10],pc[9]^pc[8]};
// write btb tag
always@(posedge clk)
begin
// if(rst)
// begin:tagblock
// integer i;
// for (i=0 ; i<btb_depth; i=i+1)
// begin
// btb_target[pc_index]<=BTB_TARGET_INIT;
// end
// end
//else
if(update_btb_target)
begin
btb_target[pc_index]<={btb_target_in[31:2],btb_type_in};
end
end
//write btb target btb
always@(posedge clk)
begin
// if(rst)
// begin:targetblock
// integer j;
// for (j=0 ; j<btb_depth; j=j+1)
// begin
// btb_tag[pc_index]<=BTB_TAG_INIT;
// end
// end
// else
if(update_btb_tag)
begin
btb_tag[pc_index]<=btb_tag_in;
end
end
reg [31:0] btb_temp;
always@(*)
begin
btb_temp=btb_target[pc_index];
end
reg [10:0] btb_tag_out;
always@(*)
begin
btb_tag_out=btb_tag[pc_index];
end
//read btb
//wire [31:0] btb_temp;
//wire [31:0] btb_target_out;
//wire [1:0] btb_type_out;
//wire [10:0] btb_tag_out;
wire btb_hit;
//assign btb_temp=btb_target[pc_index];
assign btb_target_out={btb_temp[31:2],2'b00};
assign btb_type_out=btb_temp[1:0];
//assign btb_tag_out=btb_tag[pc_index];
assign btb_hit=(btb_tag_out==btb_tag_in);//?1'b1:1'b0;
assign btb_v=btb_hit;
assign en_btb_pred=btb_v&&PHT_pred_taken;
endmodule
|
/// date:2016/3/5 3/6 am: 10:57 done!
/// engineer:ZhaiShaoMin
/// module function:because there are three kinds of accesses to mem ,
/// we need to determine which will be allowed to access mem finally.
module arbiter_for_mem(//input
clk,
rst,
v_mem_download,
v_d_m_areg,
v_i_m_areg,
mem_access_done,
//output
ack_m_download,
ack_d_m_areg,
ack_i_m_areg,
v_m_download_m,
v_d_m_areg_m,
v_i_m_areg_m
);
//input
input clk;
input rst;
input v_mem_download;
input v_d_m_areg;
input v_i_m_areg;
input mem_access_done;
//output
output ack_m_download;
output ack_d_m_areg;
output ack_i_m_areg;
output v_m_download_m;
output v_d_m_areg_m;
output v_i_m_areg_m;
/// parameter for fsm state
parameter arbiter_idle=2'b00;
parameter i_m_areg_busy=2'b01;
parameter d_m_areg_busy=2'b10;
parameter m_download_busy=2'b11;
reg [1:0] nstate;
reg [1:0] state;
// wire [2:0] v_vector;
// assign v_vector={v_i_m_areg,v_d_m_areg,v_mem_download};
wire [2:0] seled_v;
reg ack_m_download;
reg ack_d_m_areg;
reg ack_i_m_areg;
reg v_m_download_m;
reg v_d_m_areg_m;
reg v_i_m_areg_m;
assign seled_v=(v_i_m_areg==1'b1)?3'b100:(v_d_m_areg==1'b1)?3'b010:(v_mem_download==1'b1)?3'b001:3'b000;
always@(*)
begin
//default values
\t{ack_i_m_areg,ack_d_m_areg,ack_m_download}=3'b000;
\t{v_i_m_areg_m,v_d_m_areg_m,v_m_download_m}=3'b000;
\tnstate=state;
case(state)
arbiter_idle:
begin
{ack_i_m_areg,ack_d_m_areg,ack_m_download}=seled_v;
{v_i_m_areg_m,v_d_m_areg_m,v_m_download_m}=seled_v;
if(seled_v==3'b100)
nstate=i_m_areg_busy;
else
if(seled_v==3'b010)
nstate=d_m_areg_busy;
else
if(seled_v==3'b001)
nstate=m_download_busy;
end
i_m_areg_busy:
begin
if(mem_access_done)
begin
nstate=arbiter_idle;
end
{ack_i_m_areg,ack_d_m_areg,ack_m_download}=3'b100;
{v_i_m_areg_m,v_d_m_areg_m,v_m_download_m}=3'b100;
end
d_m_areg_busy:
begin
if(mem_access_done)
begin
nstate=arbiter_idle;
end
{ack_i_m_areg,ack_d_m_areg,ack_m_download}=3'b010;
{v_i_m_areg_m,v_d_m_areg_m,v_m_download_m}=3'b010;
end
m_download_busy:
begin
if(mem_access_done)
begin
nstate=arbiter_idle;
end
{ack_i_m_areg,ack_d_m_areg,ack_m_download}=3'b001;
{v_i_m_areg_m,v_d_m_areg_m,v_m_download_m}=3'b001;
end
endcase
end
/// state reg
always@(posedge clk)
begin
if(rst)
state<=2'b00;
else
state<=nstate;
end
endmodule
|
/// date:2016/3/9
/// engineer: ZhaiShaoMin
module m_rep_upload(//input
clk,
rst,
m_flits_rep,
v_m_flits_rep,
flits_max,
en_flits_max,
rep_fifo_rdy,
//output
m_flit_out,
v_m_flit_out,
\t\t\t\t\t\t\t\tm_ctrl_out,
m_rep_upload_state
);
//input
input clk;
input rst;
input [175:0] m_flits_rep;
input v_m_flits_rep;
input [3:0] flits_max;
input en_flits_max;
input rep_fifo_rdy;
//output
output [15:0] m_flit_out;
output v_m_flit_out;
output [1:0] m_ctrl_out;
output m_rep_upload_state;
//parameter
parameter m_rep_upload_idle=1'b0;
parameter m_rep_upload_busy=1'b1;
//reg m_req_nstate;
reg m_rep_state;
reg [143:0] m_rep_flits;
reg [3:0] sel_cnt;
reg v_m_flit_out;
reg fsm_rst;
reg next;
reg en_flits_in;
reg inc_cnt;
reg [3:0] flits_max_reg;
reg [1:0] m_ctrl_out;
assign m_rep_upload_state=m_rep_state;
always@(*)
begin
//default value
// dc_req_nstate=dc_req_state;
v_m_flit_out=1'b0;
inc_cnt=1'b0;
fsm_rst=1'b0;
en_flits_in=1'b0;
next=1'b0;
m_ctrl_out=2'b00;
case(m_rep_state)
m_rep_upload_idle:
begin
if(v_m_flits_rep)
begin
en_flits_in=1'b1;
next=1'b1;
end
end
m_rep_upload_busy:
begin
if(rep_fifo_rdy)
begin
if(sel_cnt==flits_max_reg)
\t\t\t\t begin
fsm_rst=1'b1;
\t\t\t\t\tm_ctrl_out=2'b11;
\t\t\t\t\tend
\t\t\t\t else if(sel_cnt==3'b000)
\t\t\t\t m_ctrl_out=2'b01;
\t\t\t\t m_ctrl_out=2'b10;
inc_cnt=1'b1;
v_m_flit_out=1'b1;
end
end
endcase
end
// fsm state
always@(posedge clk)
begin
if(rst||fsm_rst)
m_rep_state<=1'b0;
else if(next)
m_rep_state<=1'b1;
end
// flits regs
always@(posedge clk)
begin
if(rst||fsm_rst)
m_rep_flits<=143'h0000;
else if(en_flits_in)
m_rep_flits<=m_flits_rep[175:32];
end
reg [15:0] m_flit_out;
always@(*)
begin
case(sel_cnt)
4'b0000:m_flit_out=m_rep_flits[143:128];
4'b0001:m_flit_out=m_rep_flits[127:112];
4'b0010:m_flit_out=m_rep_flits[111:96];
4'b0011:m_flit_out=m_rep_flits[95:80];
4'b0100:m_flit_out=m_rep_flits[79:64];
4'b0101:m_flit_out=m_rep_flits[63:48];
4'b0110:m_flit_out=m_rep_flits[47:32];
4'b0111:m_flit_out=m_rep_flits[31:16];
4'b1000:m_flit_out=m_rep_flits[15:0];
default:m_flit_out=m_rep_flits[143:128];
endcase
end
// flits_max
always@(posedge clk)
begin
if(rst||fsm_rst)
flits_max_reg<=4'b0000;
else if(en_flits_max)
flits_max_reg<=flits_max;
end
///sel_counter
always@(posedge clk)
begin
if(rst||fsm_rst)
sel_cnt<=4'b0000;
else if(inc_cnt)
sel_cnt<=sel_cnt+4'b0001;
end
endmodule
|
// BLOCK RAM
// Simple dual-Port RAM with Synchronous Read
// mainly used for fifo
module SDP_BRAM_SRd(clk, wren,rden, wa, ra, di, do);
parameter ram_width=19;
parameter ram_dipth=16;
parameter addr_width=5;
input clk;
input wren;
input rden;
input [addr_width-1:0] ra;
input [addr_width-1:0] wa;
input [ram_width-1:0] di;
output [ram_width-1:0] do;
reg [ram_width-1:0] ram [ram_dipth-1:0];
reg [addr_width-1:0] read_a;
always @(posedge clk) begin
if (wren)
ram[wa] <= di;
if (rden)
read_a <= ra;
end
assign do = ram[read_a];
endmodule
//
// Single-Port RAM with Synchronous Read
//
module SP_BRAM_SRd(clk, we, re, a, di, do);
parameter ram_depth=16;
parameter ram_width=6;
parameter ram_addr_width=4;
input clk;
input we;
input re;
input [ram_addr_width-1:0] a;
input [ram_width-1:0] di;
output [ram_width-1:0] do;
reg [ram_width-1:0] ram [ram_depth-1:0];
reg [ram_addr_width-1:0] read_a;
always @(posedge clk) begin
if (we)
ram[a] <= di;
read_a <= a;
end
assign do = re?ram[read_a]:'z;
endmodule
|
/****************************************************************************************
date:2016/3/28
designer:ZhaiShaoMin
module name:tb_ic_req_upload
project:ring network multicore
module function: test the behavior of ic_req_upload
****************************************************************************************/
`timescale 1ns/100ps
module tb_ic_req_upload();
//inputs
reg clk;
reg rst;
reg [47:0] ic_flits_req;
reg v_ic_flits_req;
reg req_fifo_rdy;
//output
wire [15:0] ic_flit_out;
wire v_ic_flit_out;
wire [1:0] ic_ctrl_out;
wire ic_req_upload_state;
ic_req_upload uut (//input
.clk(clk),
.rst(rst),
.ic_flits_req(ic_flits_req),
.v_ic_flits_req(v_ic_flits_req),
.req_fifo_rdy(req_fifo_rdy),
//output
.ic_flit_out(ic_flit_out),
.v_ic_flit_out(v_ic_flit_out),
\t\t\t\t\t\t\t\t .ic_ctrl_out(ic_ctrl_out),
.ic_req_upload_state(ic_req_upload_state)
);
integer log_file;
//define task for cmp actual output and expected outputs
task cmp_outputs;
input [15:0] exp_ic_flit_out;
input exp_v_ic_flit_out;
input [1:0] exp_ic_ctrl_out;
input exp_ic_req_upload_state;
begin
$display ("Time: %t", $time);
$fdisplay (log_file, "Time: %t", $time);
if (ic_flit_out != exp_ic_flit_out)
begin
$display("ERROR: Invalid ic_flit_out\
\\t Expected: 0x%x \
\\t Acutal: 0x%x", exp_ic_flit_out,ic_flit_out);
$fdisplay(log_file,"ERROR: Invalid ic_flit_out\
\\t Expected: 0x%x \
\\t Acutal: 0x%x", exp_ic_flit_out,ic_flit_out);
end
if (v_ic_flit_out != exp_v_ic_flit_out)
begin
$display("ERROR: Invalid v_ic_flit_out\
\\t Expected: 0x%x \
\\t Acutal: 0x%x", exp_v_ic_flit_out,v_ic_flit_out);
$fdisplay(log_file,"ERROR: Invalid v_ic_flit_out\
\\t Expected: 0x%x \
\\t Acutal: 0x%x", exp_v_ic_flit_out,v_ic_flit_out);
end
if (ic_ctrl_out != exp_ic_ctrl_out)
begin
$display("ERROR: Invalid ic_ctrl_out\
\\t Expected: 0x%x \
\\t Acutal: 0x%x", exp_ic_ctrl_out,ic_ctrl_out);
$fdisplay(log_file,"ERROR: Invalid ic_ctrl_out\
\\t Expected: 0x%x \
\\t Acutal: 0x%x", exp_ic_ctrl_out,ic_ctrl_out);
end
if (ic_req_upload_state != exp_ic_req_upload_state)
begin
$display("ERROR: Invalid ic_req_upload_state\
\\t Expected: 0x%x \
\\t Acutal: 0x%x",exp_ic_req_upload_state,ic_req_upload_state);
$fdisplay(log_file,"ERROR: Invalid ic_req_upload_state\
\\t Expected: 0x%x \
\\t Acutal: 0x%x", exp_ic_req_upload_state,ic_req_upload_state);
end
if((ic_flit_out == exp_ic_flit_out)&&
(v_ic_flit_out == exp_v_ic_flit_out)&&
(ic_ctrl_out == exp_ic_ctrl_out)&&
(ic_req_upload_state == exp_ic_req_upload_state))
begin
$display("passed,test");
$fdisplay(log_file,"passed,test");
end
end
endtask
//initial inputs
initial begin
clk=1\'b0;
rst=1\'b1;
v_ic_flits_req=1\'b0;
req_fifo_rdy=1\'b0;
ic_flits_req=48\'h000000000000;
log_file=$fopen("log_IC_REQ_UPLOAD.txt");
end
`define clk_step #14;
always #7 clk=~clk;
initial
begin
// IC_REQ_UPLOAD TEST//
`clk_step
$display("TEST BEGIN.......");
$fdisplay(log_file,"TEST BEGIN.......");
rst=1\'b0;
`clk_step
$display("1st try \
no valid flit from ic_req_upload,assuming that req_fifo is not full");
$fdisplay(log_file,"1st try \
no valid flit from ic_req_upload,assuming that req_fifo is not full");
v_ic_flits_req=1\'b0;
req_fifo_rdy=1\'b1;
ic_flits_req=48\'h12345678abcd;
//Now,let\'s test whether ic_req_up work well,note: there should be passed,test!
cmp_outputs(16\'h0000,/*ic_flit_out*/
1\'b0, /*v_ic_flit_out*/
2\'b01, /*ic_ctrl_out*/
1\'b0 /*ic_req_upload_state */
);
`clk_step
// till now, ic_req_upload has nothing valid
$display("2nd try\
no valid flit from ic_req_upload,assuming that req_fifo is not full");
$fdisplay(log_file,"2nd try\
no valid flit from ic_req_upload,assuming that req_fifo is not full");
v_ic_flits_req=1\'b1;
req_fifo_rdy=1\'b1;
ic_flits_req=48\'h12345678abcd;
//a valid flits comes in !
//Now,let\'s test whether ic_req_up work well,note: there should be passed,test!
cmp_outputs(16\'h0000,/*ic_flit_out*/
1\'b0, /*v_ic_flit_out*/
2\'b01, /*ic_ctrl_out*/
1\'b0 /*ic_req_upload_state */
);
`clk_step
$display("3rd try\
1st valid flit from ic_req_upload,assuming that req_fifo is not full");
$fdisplay(log_file,"3rd try\
1st valid flit from ic_req_upload,assuming that req_fifo is not full");
v_ic_flits_req=1\'b0;
req_fifo_rdy=1\'b1;
ic_flits_req=48\'h12345678abcd;
//Now,let\'s test whether ic_req_up work well,note: there should be passed,test!
// this is a case where coming flits and req_fifo_rdy both are valid
cmp_outputs(16\'h1234,/*ic_flit_out*/
1\'b1, /*v_ic_flit_out*/
2\'b01, /*ic_ctrl_out*/
1\'b1 /*ic_req_upload_state */
);
// cpm above should be right ,since there was a valid req fifo rdy!
`clk_step
$display("4th try\
no valid flit from ic_req_upload,assuming that req_fifo is full");
$fdisplay(log_file,"4th try\
no valid flit from ic_req_upload,assuming that req_fifo is full");
v_ic_flits_req=1\'b0;
req_fifo_rdy=1\'b0;
ic_flits_req=48\'h12345678abcd;
//Now,let\'s test whether ic_req_up work well,note: there should be passed,test!
cmp_outputs(16\'h5678,/*ic_flit_out*/
1\'b0, /*v_ic_flit_out*/
2\'b10, /*ic_ctrl_out*/
1\'b1 /*ic_req_upload_state */
);
`clk_step
$display("5th try\
2nd valid flit from ic_req_upload,assuming that req_fifo is not full");
$fdisplay(log_file,"5th try\
2nd valid flit from ic_req_upload,assuming that req_fifo is not full");
// second flit will get out of ic_req_upload
v_ic_flits_req=1\'b0;
req_fifo_rdy=1\'b1;
ic_flits_req=48\'h12345678abcd;
cmp_outputs(16\'h5678,/*ic_flit_out*/
1\'b1, /*v_ic_flit_out*/
2\'b10, /*ic_ctrl_out*/
1\'b1 /*ic_req_upload_state */
);
`clk_step
//third flit get out of ic_req_upload
$display("6th try\
3rd valid flit from ic_req_upload,assuming that req_fifo is not full");
$fdisplay(log_file,"6th try\
3rd valid flit from ic_req_upload,assuming that req_fifo is not full");
v_ic_flits_req=1\'b0;
req_fifo_rdy=1\'b1;
ic_flits_req=48\'h12345678abcd;
cmp_outputs(16\'habcd,/*ic_flit_out*/
1\'b1, /*v_ic_flit_out*/
2\'b11, /*ic_ctrl_out*/
1\'b1 /*ic_req_upload_state */
);
`clk_step
// now let\'s try a case where coming flits is valid but req_fifo_rdy is invalid
$display("7th try \
now let\'s try a case where coming flits is valid but req_fifo_rdy is invalid\
a valid flits comes in");
$fdisplay(log_file,"7th try \
now let\'s try a case where coming flits is valid but req_fifo_rdy is invalid\
a valid flits comes in");
v_ic_flits_req=1\'b1;
req_fifo_rdy=1\'b0;
ic_flits_req=48\'hc0de2016c0de;
//this time v_ic_flit_out should be invalid because req_fifo_rdy==1\'b0
cmp_outputs(16\'h0000,/*ic_flit_out*/
1\'b0, /*v_ic_flit_out*/
2\'b01, /*ic_ctrl_out*/
1\'b0 /*ic_req_upload_state */
);
`clk_step
$display("8th try \
1st flit from ic_req_upload,assuming that req_fifo is not full");
$fdisplay(log_file,"8th try \
1st flit from ic_req_upload,assuming that req_fifo is not full");
v_ic_flits_req=1\'b0;
req_fifo_rdy=1\'b1;
ic_flits_req=48\'hc0de2016c0de;
cmp_outputs(16\'hc0de,/*ic_flit_out*/
1\'b1, /*v_ic_flit_out*/
2\'b01, /*ic_ctrl_out*/
1\'b1 /*ic_req_upload_state */
);
`clk_step
//assuming that req_fifo is full
$display("9th try \
2nd flit from ic_req_upload,assuming that req_fifo is full");
$fdisplay(log_file,"9th try \
2nd flit from ic_req_upload,assuming that req_fifo is full");
v_ic_flits_req=1\'b0;
req_fifo_rdy=1\'b0;
ic_flits_req=48\'hc0de2016c0de;
//this time v_ic_flit_out should be invalid because req_fifo_rdy==1\'b0
cmp_outputs(16\'h2016,/*ic_flit_out*/
1\'b0, /*v_ic_flit_out*/
2\'b10, /*ic_ctrl_out*/
1\'b1 /*ic_req_upload_state */
);
`clk_step
//2th flit from ic_req_upload
//assuming that req_fifo is not full
$display("10th try \
2th flit from ic_req_upload,assuming that req_fifo is not full");
$fdisplay(log_file,"10th try \
2th flit from ic_req_upload,assuming that req_fifo is not full");
v_ic_flits_req=1\'b0;
req_fifo_rdy=1\'b1;
ic_flits_req=48\'hc0de2016c0de;
//this time v_ic_flit_out should be invalid because req_fifo_rdy==1\'b0
cmp_outputs(16\'h2016,/*ic_flit_out*/
1\'b1, /*v_ic_flit_out*/
2\'b10, /*ic_ctrl_out*/
1\'b1 /*ic_req_upload_state */
);
`clk_step
//3rd flit from ic_req_upload
//assuming that req_fifo is full
$display("11th try \
3rd flit from ic_req_upload,assuming that req_fifo is not full");
$fdisplay(log_file,"11th try \
3rd flit from ic_req_upload,assuming that req_fifo is full");
v_ic_flits_req=1\'b0;
req_fifo_rdy=1\'b1;
ic_flits_req=48\'hc0de2016c0de;
//this time v_ic_flit_out should be invalid because req_fifo_rdy==1\'b0
cmp_outputs(16\'hc0de,/*ic_flit_out*/
1\'b0, /*v_ic_flit_out*/
2\'b11, /*ic_ctrl_out*/
1\'b1 /*ic_req_upload_state */
);
`clk_step
//3rd flit from ic_req_upload
//assuming that req_fifo is not full
$display("12th try \
3rd flit from ic_req_upload,assuming that req_fifo is not full");
$fdisplay(log_file,"12th try \
3rd flit from ic_req_upload,assuming that req_fifo is not full");
v_ic_flits_req=1\'b0;
req_fifo_rdy=1\'b1;
ic_flits_req=48\'hc0de2016c0de;
//this time v_ic_flit_out should be invalid because req_fifo_rdy==1\'b0
cmp_outputs(16\'hc0de,/*ic_flit_out*/
1\'b1, /*v_ic_flit_out*/
2\'b11, /*ic_ctrl_out*/
1\'b1 /*ic_req_upload_state */
);
$display("FINISH test of ic_req_upload !");
$fdisplay(log_file,"FINISH test of ic_req_upload !");
$stop;
end
endmodule
|
//date:2016/3/14
//engineer :ZhaiShaoMin
// module function :unite all four ring_node together
module whole_system(//input
clk,
rst
);
input clk;
input rst;
wire en_local_req_1; // to previous node refer to below notes
wire en_local_rep_1;
wire en_pass_req_1; // from next node //local_in_req fifo in next node says that it can receive
wire en_pass_rep_1; // refer to notes below
wire [3:0] used_slots_pass_req_1;
wire [3:0] used_slots_pass_rep_1;
wire [15:0] flit_out_1;
wire [1:0] ctrl_out_1;
wire [1:0] dest_fifo_out_1;
wire en_local_req_2; // to previous node refer to below notes
wire en_local_rep_2;
wire en_pass_req_2; // from next node //local_in_req fifo in next node says that it can receive
wire en_pass_rep_2; // refer to notes below
wire [3:0] used_slots_pass_req_2;
wire [3:0] used_slots_pass_rep_2;
wire [15:0] flit_out_2;
wire [1:0] ctrl_out_2;
wire [1:0] dest_fifo_out_2;
wire en_local_req_3; // to previous node refer to below notes
wire en_local_rep_3;
wire en_pass_req_3; // from next node //local_in_req fifo in next node says that it can receive
wire en_pass_rep_3; // refer to notes below
wire [3:0] used_slots_pass_req_3;
wire [3:0] used_slots_pass_rep_3;
wire [15:0] flit_out_3;
wire [1:0] ctrl_out_3;
wire [1:0] dest_fifo_out_3;
wire en_local_req_4; // to previous node refer to below notes
wire en_local_rep_4;
wire en_pass_req_4; // from next node //local_in_req fifo in next node says that it can receive
wire en_pass_rep_4; // refer to notes below
wire [3:0] used_slots_pass_req_4;
wire [3:0] used_slots_pass_rep_4;
wire [15:0] flit_out_4;
wire [1:0] ctrl_out_4;
wire [1:0] dest_fifo_out_4;
// instance of node1
ring_node node1(//input
.clk(clk),
.rst(rst),
.ctrl_in(ctrl_out_4), //[1:0] for guiding flit flowing ; 00:nothing, 01:head flit, 10:body flit, 11:tail flit
.flit_in(flit_out_4),
.dest_fifo_in(dest_fifo_out_4),
.en_local_req_in(en_local_req_4),
.en_local_rep_in(en_local_rep_4),
.en_pass_req_in(en_pass_req_4),
.en_pass_rep_in(en_pass_rep_4),
.used_slots_pass_req_in(used_slots_pass_req_4),
.used_slots_pass_rep_in(used_slots_pass_rep_4),
//output
.en_local_req(en_local_req_1), // to previous node refer to below notes
.en_local_rep(en_local_rep_1),
.en_pass_req(en_pass_req_1), // from next node //local_in_req fifo in next node says that it can receive
.en_pass_rep(en_pass_rep_1), // refer to notes below
.used_slots_pass_req(used_slots_pass_req_1),
.used_slots_pass_rep(used_slots_pass_rep_1),
.flit_out(flit_out_1),
.ctrl_out(ctrl_out_1),
.dest_fifo_out(dest_fifo_out_1)
);
// instance of node2
ring_node node2(//input
.clk(clk),
.rst(rst),
.ctrl_in(ctrl_out_1), //[1:0] for guiding flit flowing ; 00:nothing, 01:head flit, 10:body flit, 11:tail flit
.flit_in(flit_out_1),
.dest_fifo_in(dest_fifo_out_1),
.en_local_req_in(en_local_req_1),
.en_local_rep_in(en_local_rep_1),
.en_pass_req_in(en_pass_req_1),
.en_pass_rep_in(en_pass_rep_1),
.used_slots_pass_req_in(used_slots_pass_req_1),
.used_slots_pass_rep_in(used_slots_pass_rep_1),
//output
.en_local_req(en_local_req_2), // to previous node refer to below notes
.en_local_rep(en_local_rep_2),
.en_pass_req(en_pass_req_2), // from next node //local_in_req fifo in next node says that it can receive
.en_pass_rep(en_pass_rep_2), // refer to notes below
.used_slots_pass_req(used_slots_pass_req_2),
.used_slots_pass_rep(used_slots_pass_rep_2),
.flit_out(flit_out_2),
.ctrl_out(ctrl_out_2),
.dest_fifo_out(dest_fifo_out_2)
);
// instance of node3
ring_node node3(//input
.clk(clk),
.rst(rst),
.ctrl_in(ctrl_out_2), //[1:0] for guiding flit flowing ; 00:nothing, 01:head flit, 10:body flit, 11:tail flit
.flit_in(flit_out_2),
.dest_fifo_in(dest_fifo_out_2),
.en_local_req_in(en_local_req_2),
.en_local_rep_in(en_local_rep_2),
.en_pass_req_in(en_pass_req_2),
.en_pass_rep_in(en_pass_rep_2),
.used_slots_pass_req_in(used_slots_pass_req_2),
.used_slots_pass_rep_in(used_slots_pass_rep_2),
//output
.en_local_req(en_local_req_3), // to previous node refer to below notes
.en_local_rep(en_local_rep_3),
.en_pass_req(en_pass_req_3), // from next node //local_in_req fifo in next node says that it can receive
.en_pass_rep(en_pass_rep_3), // refer to notes below
.used_slots_pass_req(used_slots_pass_req_3),
.used_slots_pass_rep(used_slots_pass_rep_3),
.flit_out(flit_out_3),
.ctrl_out(ctrl_out_3),
.dest_fifo_out(dest_fifo_out_3)
);
// instance of node4
ring_node node4(//input
.clk(clk),
.rst(rst),
.ctrl_in(ctrl_out_3), //[1:0] for guiding flit flowing ; 00:nothing, 01:head flit, 10:body flit, 11:tail flit
.flit_in(flit_out_3),
.dest_fifo_in(dest_fifo_out_3),
.en_local_req_in(en_local_req_3),
.en_local_rep_in(en_local_rep_3),
.en_pass_req_in(en_pass_req_3),
.en_pass_rep_in(en_pass_rep_3),
.used_slots_pass_req_in(used_slots_pass_req_3),
.used_slots_pass_rep_in(used_slots_pass_rep_3),
//output
.en_local_req(en_local_req_4), // to previous node refer to below notes
.en_local_rep(en_local_rep_4),
.en_pass_req(en_pass_req_4), // from next node //local_in_req fifo in next node says that it can receive
.en_pass_rep(en_pass_rep_4), // refer to notes below
.used_slots_pass_req(used_slots_pass_req_4),
.used_slots_pass_rep(used_slots_pass_rep_4),
.flit_out(flit_out_4),
.ctrl_out(ctrl_out_4),
.dest_fifo_out(dest_fifo_out_4)
);
endmodule
|
/*******************************************************************
date:2016/3/31
designer:ZhaiShaoMin
module name:tb_dc_rep_upload
module function:find out errors in the design unit
********************************************************************/
`timescale 1ns/1ps
module tb_dc_rep_upload();
//input
reg clk;
reg rst;
reg [175:0] dc_flits_rep;
reg v_dc_flits_rep;
reg [3:0] flits_max;
reg en_flits_max;
reg rep_fifo_rdy;
//output
wire [15:0] dc_flit_out;
wire v_dc_flit_out;
wire [1:0] dc_ctrl_out;
wire dc_rep_upload_state;
//instante
dc_rep_upload uut(//input
.clk(clk),
.rst(rst),
.dc_flits_rep(dc_flits_rep),
.v_dc_flits_rep(v_dc_flits_rep),
.flits_max(flits_max),
.en_flits_max(en_flits_max),
.rep_fifo_rdy(rep_fifo_rdy),
//output
.dc_flit_out(dc_flit_out),
.v_dc_flit_out(v_dc_flit_out),
\t\t\t\t\t\t\t\t .dc_ctrl_out(dc_ctrl_out),
.dc_rep_upload_state(dc_rep_upload_state)
);
//initial inputs
initial begin
clk=1'b0;
rst=1'b1;
dc_flits_rep=176'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000;
v_dc_flits_rep=1'b0;
en_flits_max=1'b0;
flits_max=4'b0000;
rep_fifo_rdy=1'b0;
end
`define clk_step #14;
always #7 clk=~clk;
//////////////////////////////////////////////////////////////////
////////////BEGIN TEST////////////////////////////////////////////
initial begin
`clk_step
rst=1'b0;
`clk_step
////////////////////////////////////////////////////////////////
//////////////1st case:one flit long msg such as C2Cinvrep//////
///this time dc_flits_rep is not ready
dc_flits_rep=176'h2011_2010_2009_2008_2007_2006_2005_2004_2003_2002_2001;
v_dc_flits_rep=1'b0;
en_flits_max=1'b1;
flits_max=4'b0001;
rep_fifo_rdy=1'b1;
`clk_step
///this cycle dc_flits_rep is ready !
dc_flits_rep=176'h2011_2010_2009_2008_2007_2006_2005_2004_2003_2002_2001;
v_dc_flits_rep=1'b1;
en_flits_max=1'b0;
flits_max=4'b0000;
rep_fifo_rdy=1'b1;
`clk_step
///by the end of this cycle ,the upload will be empty for that's a one-flit msg
dc_flits_rep=176'h2016_2015_2014_2013_2012_2011_2010_2009_2008_2007_2006; v_dc_flits_rep=1'b1;
en_flits_max=1'b0;
flits_max=4'b0000;
rep_fifo_rdy=1'b1;
`clk_step
///next six cycles there is no valid msg coming!
v_dc_flits_rep=1'b0;
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
////////////////////////////////////////////////////////////////////////////////
/////////2nd case: 9-flits msg is coming!///////////////////////////////////////
en_flits_max=1'b1;
flits_max=4'b1000;
`clk_step
v_dc_flits_rep=1'b1;
dc_flits_rep=176'hc0de_c1de_c2de_c3de_c4de_c5de_c6de_c7de_c8de_c9de_cade;
`clk_step
v_dc_flits_rep=1'b0;
en_flits_max=1'b0;
//first flit is poped to rep fifo
`clk_step
//second flit is poped to rep fifo
`clk_step
// 3rd flit is poped to rep fifo
`clk_step
///now assume that rep fifo is full
rep_fifo_rdy=1'b0;
`clk_step
///now assume that rep fifo is full
`clk_step
///now assume that rep fifo is full
`clk_step
///now assume that rep fifo is full
`clk_step
///now assume that rep fifo is not full! And 4th flit is poped to rep fifo
`clk_step
rep_fifo_rdy=1'b1;
`clk_step
///5th flit is poped to rep fifo
`clk_step
///6th flit is poped to rep fifo
`clk_step
///7th flit is poped to rep fifo
`clk_step
///now assume rep fifo become full once again!
rep_fifo_rdy=1'b0;
`clk_step
///still full
`clk_step
///still full
`clk_step
///rep fifo is not full now! So the 8th flit is poped to rep fifo
rep_fifo_rdy=1'b1;
`clk_step
/// the last flit is poped to rep fifo!
`clk_step
///dc_rep_upload will be idle
en_flits_max=1'b1;
flits_max=4'b1010;
rep_fifo_rdy=1'b0;
`clk_step
////////////////////////////////////////////////////////////////////////////
//////////////3rd case: 11-flits msg is coming!/////////////////////////////
v_dc_flits_rep=1'b1;
dc_flits_rep=176'h0331_0401_0402_0403_0404_0405_0406_0407_0408_0409_040a;
`clk_step
//due to rep fifo being full,no flit poped to rep fifo
`clk_step
`clk_step
`clk_step
//now rep fifo become not full and first flit is poped to rep fifo
`clk_step
//due to fifo being full ,second flit still sit in dc_rep_upload
`clk_step
//now rep fifo become not full , second flit is poped to rep fifo
`clk_step
//3rd flit to rep fifo
`clk_step
//4th flit to rep fifo
`clk_step
//5th flit to reo fifo
`clk_step
//6th flit ro rep fifo
`clk_step
///// rep fifo become full again!
rep_fifo_rdy=1'b0;
`clk_step
`clk_step
`clk_step
///rep fifo changes to be not full, and 7th flit to rep fifo
rep_fifo_rdy=1'b1;
`clk_step
//8th flit to rep fifo
`clk_step
//9th flit to rep fifo
`clk_step
//10th flit to rep fifo
`clk_step
//11th flit to rep fifo
`clk_step
//////dc_rep_upload become idle!
`clk_step
$stop;
end
endmodule
|
//date:2016/3/11
//engineer:ZhaiShaoMin
//module name:inter registers between inst fetch stage and inst decode stage
module core_if_id(//input
clk,
rst,
// stall,
if_id_we,
if_flush,
pc_plus_4,
inst_word,
//used for update Branch predictor
pc,
pred_target,
delayed_PHT,
delayed_BHR,
btb_type,
btb_v,
//output
pc_plus_4_out,
inst_word_out,
pc_out,
pred_target_out,
delayed_PHT_out,
delayed_BHR_out,
btb_type_out,
btb_v_out
);
//input
input clk;
input rst;
input [31:0] pc_plus_4;
input [31:0] inst_word;
input [31:0] pc;
input [31:0] pred_target;
input [1:0] delayed_PHT;
input [2:0] delayed_BHR;
input [1:0] btb_type;
input btb_v;
//input stall;
input if_id_we;
input if_flush;
//output
output [31:0] pc_plus_4_out;
output [31:0] inst_word_out;
output [31:0] pc_out;
output [31:0] pred_target_out;
output [1:0] delayed_PHT_out;
output [2:0] delayed_BHR_out;
output [1:0] btb_type_out;
output btb_v_out;
//reg
reg [31:0] inst_word_out;
reg [31:0] pc_plus_4_out;
reg [31:0] pc_out;
reg [31:0] pred_target_out;
reg [1:0] delayed_PHT_out;
reg [2:0] delayed_BHR_out;
reg [1:0] btb_type_out;
reg btb_v_out;
always@(posedge clk)
begin
if(rst||if_flush)
begin
pc_plus_4_out<=32'h0000;
inst_word_out<=32'h0000;
pc_out<=32'h0000;
pred_target_out<=32'h0000;
delayed_PHT_out<=2'b00;
delayed_BHR_out<=3'b000;
btb_type_out<=2'b00;
btb_v_out<=1'b0;
end
else if(if_id_we)
begin
pc_plus_4_out<=pc_plus_4;
inst_word_out<=inst_word;
pc_out<=pc;
pred_target_out<=pred_target;
delayed_PHT_out<=delayed_PHT;
delayed_BHR_out<=delayed_BHR;
btb_type_out<=btb_type;
btb_v_out<=btb_v;
end
end
endmodule
|
/// date:2016/3/9
/// engineer: ZhaiShaoMin
module ic_req_upload(//input
clk,
rst,
ic_flits_req,
v_ic_flits_req,
req_fifo_rdy,
//output
ic_flit_out,
v_ic_flit_out,
\t\t\t\t\t\t\t\t ic_ctrl_out,
ic_req_upload_state
);
//input
input clk;
input rst;
input [47:0] ic_flits_req;
input v_ic_flits_req;
input req_fifo_rdy;
//output
output [15:0] ic_flit_out;
output v_ic_flit_out;
output [1:0] ic_ctrl_out;
output ic_req_upload_state;
//parameter
parameter ic_req_upload_idle=1'b0;
parameter ic_req_upload_busy=1'b1;
//reg ic_req_nstate;
reg ic_req_state;
reg [47:0] ic_req_flits;
reg [1:0] sel_cnt;
reg v_ic_flit_out;
reg fsm_rst;
reg next;
reg en_flits_in;
reg inc_cnt;
assign ic_req_upload_state=ic_req_state;
always@(*)
begin
//default value
// ic_req_nstate=ic_req_state;
v_ic_flit_out=1'b0;
inc_cnt=1'b0;
fsm_rst=1'b0;
en_flits_in=1'b0;
next=1'b0;
case(ic_req_state)
ic_req_upload_idle:
begin
if(v_ic_flits_req)
begin
en_flits_in=1'b1;
next=1'b1;
end
end
ic_req_upload_busy:
begin
if(req_fifo_rdy)
begin
if(sel_cnt==2'b10)
fsm_rst=1'b1;
inc_cnt=1'b1;
v_ic_flit_out=1'b1;
end
end
endcase
end
// fsm state
always@(posedge clk)
begin
if(rst||fsm_rst)
ic_req_state<=1'b0;
else if(next)
ic_req_state<=1'b1;
end
// flits regs
always@(posedge clk)
begin
if(rst||fsm_rst)
ic_req_flits<=48'h0000;
else if(en_flits_in)
ic_req_flits<=ic_flits_req;
end
reg [15:0] ic_flit_out;
reg [1:0] ic_ctrl_out;
always@(*)
begin
case(sel_cnt)
2'b00:
\t begin
\t ic_flit_out=ic_req_flits[47:32];
\t ic_ctrl_out=2'b01;
\t end
2'b01:
\t begin
\t ic_flit_out=ic_req_flits[31:16];
\t\t ic_ctrl_out=2'b10;
\t\tend
2'b10:
\t begin
\t ic_flit_out=ic_req_flits[15:0];
\t\t ic_ctrl_out=2'b11;
\t\tend
default:
\t begin
\t ic_flit_out=ic_req_flits[47:32];
\t\t ic_ctrl_out=2'b00;
\t end
endcase
end
///sel_counter
always@(posedge clk)
begin
if(rst||fsm_rst)
sel_cnt<=2'b00;
else if(inc_cnt)
sel_cnt<=sel_cnt+2'b01;
end
endmodule
|
//date:2016/3/11
//engineer:ZhaiShaoMin
//module name :regflie
module core_id_regfile(//input
clk,
rst,
raddr1,
raddr2,
rf_write,
waddr,
data,
//output
rd_data1,
rd_data2
);
//input
input clk;
input rst;
input [4:0] raddr1;
input [4:0] raddr2;
input rf_write;
input [4:0] waddr;
input [31:0] data;
//output
output [31:0] rd_data1;
output [31:0] rd_data2;
reg [31:0] regfile [31:0];
always @ (posedge clk) begin
\t\tif (rst==1'b1) begin
\t\t\tif((rf_write==1'b1) && (waddr!=32'h0000))
\t\t\t begin
\t\t\t\tregfile[waddr] <= data;
\t\t\t end
\t\tend
\tend
\treg [31:0] rd_data1;
\treg [31:0] rd_data2;
\talways @ (*) begin
\t\tif(rst==1'b1)
\t\t begin
\t\t\t rd_data1 <=32'h0000;
\t\t\tend
\t else if(raddr1==32'h0000)
\t begin
\t \t\t rd_data1 <= 32'h0000;
\t end
\t else if((raddr1== waddr) && (rf_write ==1'b1))
\t begin
\t \t rd_data1 <= data;
\t end
\t else
\t begin
\t rd_data1 <= regfile[raddr1];
end
\tend
\talways @ (*) begin
\t\tif(rst==1'b1)
\t\t begin
\t\t\t rd_data2 <=32'h0000;
\t\t\tend
\t else if(raddr2==32'h0000)
\t begin
\t \t\t rd_data2 <= 32'h0000;
\t end
\t else if((raddr2== waddr) && (rf_write ==1'b1))
\t begin
\t \t rd_data2 <= data;
\t end
\t else
\t begin
\t rd_data2 <= regfile[raddr2];
end
\tend
endmodule
|
//date:2016/8/02
//engineer:ZhaiShaoMin
//module name :regflie
//version: test bench
module tb_core_rf();
//input
reg clk;
reg rst;
reg [4:0] raddr1;
reg [4:0] raddr2;
reg rf_write;
reg [4:0] waddr;
reg [31:0] data;
//output
wire [31:0] rd_data1;
wire [31:0] rd_data2;
core_id_regfile duv(//input
.clk(clk),
.rst(rst),
.raddr1(raddr1),
.raddr2(raddr2),
.rf_write(rf_write),
.waddr(waddr),
.data(data),
//output
.rd_data1(rd_data1),
.rd_data2(rd_data2)
);
\t\t\t\t\t\t\t\t
\t\talways #5 clk=~clk;
\t\t
\t\tinteger log_file;
\t\tinteger i;
\t\t
\t\t
\t\t
\t\t`define clk_step #10;
\t\t
\t\tinitial begin
\t\t
\t\tclk=1\'b0;
\t\trst=1\'b1;
\t\traddr1=5\'h00;
\t\traddr2=5\'h00;
\t\trf_write=1\'b0;
\t\twaddr=5\'h01;
\t\tdata=32\'h11112222;
\t\tlog_file=$fopen("core_rf_log.txt");
\t\tend
\t\t
\t\t////////////////////////////////////////////////////////////////////////////
\t\t/////////////BEGIN TEST/////////////////////////////////////////////////////
\t\tinitial begin
\t\t
\t\t////////case 1: write the regfile then we should see what I want to see////////
\t\t///////here just write th rf/////////////
\t\t`clk_step
\t\trst=1\'b0;
\t\t
\t\tfor(i=0;i<32;i=i+1)
\t\tbegin
\t\t rf_write=1\'b1;
\t\t waddr=i;
\t\t data=i+1;
\t\t
\t\t $display( "(%t) writing %d. to %d ", $time, data, waddr);
$fdisplay(log_file, "(%t) writing %d. to %d ", $time, data, waddr);
\t\t
\t\t`clk_step
\t\tend
\t\t
\t\t////////case 2: read out the content in regfile /////////////////
\t\t`clk_step
\t\trf_write=1\'b0;
\t\t
\t\tfor(i=0;i<32;i=i+1)
\t\t begin
\t\t\t raddr1=i;
\t\t raddr2=i;
\t\t\t
\t\t\t $display( "(%t) get %d. from %d and get %d from %d", $time, rd_data1, raddr1 ,rd_data2, raddr2);
$fdisplay(log_file, "(%t) get %d. from %d and get %d from %d", $time, rd_data1, raddr1 ,rd_data2, raddr2);
\t\t\t
\t\t\t `clk_step
\t\t\t
\t\t\tend
\t\t\t
\t\t////////case 3: when read a reg same as being written one, it should get it direct from write data////////////
\t\t
\t\t////read port 1
\t for(i=0;i<32;i=i+1)
\t begin
\t\t raddr1=i;
\t\t\t rf_write=1\'b1;
\t\t waddr=i;
\t\t data=i+32;
\t\t\t
\t\t\t $display( "(%t) get %d. from %d and write %d to %d", $time, rd_data1, raddr1 ,data, waddr);
$fdisplay(log_file, "(%t) get %d. from %d and write %d to %d", $time, rd_data1, raddr1 ,data, waddr);
\t\t\t
\t\t\t`clk_step
\t\t\t
\t end
\t\t////read port 2
\t for(i=0;i<32;i=i+1)
\t begin
\t\t raddr2=i;
\t\t\t rf_write=1\'b1;
\t\t waddr=i;
\t\t data=i+64;
\t\t\t
\t\t\t $display( "(%t) get %d. from %d and write %d to %d", $time, rd_data1, raddr1 ,data, waddr);
$fdisplay(log_file, "(%t) get %d. from %d and write %d to %d", $time, rd_data1, raddr1 ,data, waddr);
\t\t\t
\t\t\t`clk_step
\t\t\t
\t end\t
\t $stop;
\t\tend
\tendmodule\t
\t\t
|
/*******************************************************************
date:2016/3/31
designer:ZhaiShaoMin
module name:tb_m_rep_upload
module function :find out bugs in m_rep_upload
********************************************************************/
`timescale 1ns/1ps
module tb_m_rep_upload();
//input
reg clk;
reg rst;
reg [175:0] m_flits_rep;
reg v_m_flits_rep;
reg [3:0] flits_max;
reg en_flits_max;
reg rep_fifo_rdy;
//output
wire [15:0] m_flit_out;
wire v_m_flit_out;
wire [1:0] m_ctrl_out;
wire m_rep_upload_state;
m_rep_upload uut(//input
.clk(clk),
.rst(rst),
.m_flits_rep(m_flits_rep),
.v_m_flits_rep(v_m_flits_rep),
.flits_max(flits_max),
.en_flits_max(en_flits_max),
.rep_fifo_rdy(rep_fifo_rdy),
//output
.m_flit_out(m_flit_out),
.v_m_flit_out(v_m_flit_out),
\t\t\t\t\t\t\t\t .m_ctrl_out(m_ctrl_out),
.m_rep_upload_state(m_rep_upload_state)
);
//initial inputs
initial begin
clk=1'b0;
rst=1'b1;
m_flits_rep=144'h0000_0000_0000_0000_0000_0000_0000_0000_0000;
v_m_flits_rep=1'b0;
en_flits_max=1'b0;
flits_max=1'b1;
rep_fifo_rdy=1'b0;
end
`define clk_step # 14;
always #7 clk=~clk;
/////////////////////////////////////////////////////////////
////////////////////////////BEGIN TEST!//////////////////////
initial begin
`clk_step
rst=1'b0;
`clk_step
/////////////////////////////////////////////////////////////
//////////1st case: a msg which is only one flit long////////
en_flits_max=1'b1;
flits_max=4'b0000;
rep_fifo_rdy=1'b1;
`clk_step
en_flits_max=1'b0;
m_flits_rep=144'hc0de_c1de_c2de_c3de_c4de_c5de_c6de_c7de_c8de;
v_m_flits_rep=1'b1;
`clk_step
//since rey fifo is ready to receive flit ,so the only flit is poped to rep fifo
v_m_flits_rep=1'b0;
`clk_step
//this cycle m_rep_upload is idle
//in the meantime, preparing for next msg
en_flits_max=1'b1;
flits_max=4'b0010;
/////////////////////////////////////////////////////////////
/////////////2nd case: a msg with 3 flits is coming!/////////
`clk_step
v_m_flits_rep=1'b1;
m_flits_rep=144'habc1_abc2_abc3_abc4_abc5_abc6_abc7_abc8_abc9;
`clk_step
///the 1st flit is transfered to rep fifo
`clk_step
///this cycle rep fifo become full ,so 2nd flit still sit in the regs of m_upload
rep_fifo_rdy=1'b0;
`clk_step
//still full
`clk_step
//still full
`clk_step
//rep fifo become not full! And 2nd flit can be transfered to rep fifo
rep_fifo_rdy=1'b1;
`clk_step
///3rd flit also last flit to rep fifo
`clk_step
/// m_rep_upload become idle
//////////////////////////////////////////////////////////////////
//////////// 3rd case: a msg with 9 flits is coming!//////////////
`clk_step
en_flits_max=1'b1;
flits_max=4'b1000;
`clk_step
m_flits_rep=144'h0123_1234_2345_3456_4567_5678_6789_7890_8901;
v_m_flits_rep=1'b1;
`clk_step
//since rep fifo is ready to receive flit, first flit will get out of m_rep_upload!
`clk_step
//2nd flit get out
`clk_step
//3rd flit get out
`clk_step
////rep fifo become full
rep_fifo_rdy=1'b0;
`clk_step
//still full
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
//rep fifo has empty slots now! And 4th flit get to rep fifo
rep_fifo_rdy=1'b1;
`clk_step
//5th flit get out
`clk_step
//full again!
rep_fifo_rdy=1'b0;
`clk_step
//rep fifo has empty slots now! And 6th flit get to rep fifo
rep_fifo_rdy=1'b1;
`clk_step
//7th get out
`clk_step
//8th get out
`clk_step
//9th get out
`clk_step
//////m_rep_upload become idle now !
`clk_step
$stop;
end
endmodule
|
/*************************************************************************************
date:2016/4/4
designer:ZhaiShaoMin
module name:tb_core_ras
module function:find out errors in the core_RAS
*************************************************************************************/
`timescale 1ns/1ps
module tb_core_ras();
//input
reg clk;
reg rst;
reg en_call_in;// a ret inst isn coming!
reg en_ret_in; // a call inst is coming!
reg [29:0] ret_addr_in;
reg recover_push;
reg [29:0] recover_push_addr;
reg recover_pop;
//output
wire [31:0] ret_addr_out;
core_ras uut(//input
.clk(clk),
.rst(rst),
//inst fetch stage prediction
.en_call_in(en_call_in), //in my previous version ,it equals en_ret_addr_in
.en_ret_in(en_ret_in),//in my previous version ,it equals en_ret_addr_out
.ret_addr_in(ret_addr_in),// which is gened by call inst
// decode stage recover something wrong,which caused by misprediction in btb, in RAS.
.recover_push(recover_push),//previous inst was preded as a JR inst incorrectly.
.recover_push_addr(recover_push_addr),//push back the top return addr to RAs
.recover_pop(recover_pop),// previous inst was preded as a jal inst incorrectly.
////output
//inst fetch stage poping top addr
.ret_addr_out(ret_addr_out)
);
integer log_file;
//initial inputs
initial begin
clk=1\'b0;
rst=1\'b1;
en_call_in=1\'b0;
en_ret_in=1\'b0;
ret_addr_in=30\'h00000000;
recover_push=1\'b0;
recover_push_addr=30\'h00000000;
recover_pop=1\'b0;
log_file=$fopen("tb_core_ras_logfile.txt");
end
always #5 clk=~clk;
`define clk_step #10;
initial begin
//////////////////////////////////////////////////////////////
////////////////BEGIN RAS TEST!///////////////////////////////
//////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
///////////1st case: normal case which pred right& no mispred//////////
///////////////////////////////////////////////////////////////////////
`clk_step
rst=1\'b0;
`clk_step
///////////////////////////////////////////////////////////
////////furst we should push 8 addrs into ras one by one
///push 1st addr into ras
en_call_in=1\'b1;
ret_addr_in=30\'h12340000;
$display("%t, push 1st addr: %h into ras",$time,ret_addr_in);
$fdisplay(log_file,"%t, push 1st addr: %h into ras",$time,ret_addr_in);
`clk_step
///push 2nd addr into ras
en_call_in=1\'b1;
ret_addr_in=30\'h12340001;
$display("%time, push 2nd addr: %h into ras",$time,ret_addr_in);
$fdisplay(log_file,"%time, push 2nd addr: %h into ras",$time,ret_addr_in);
`clk_step
///push 3rd addr into ras
en_call_in=1\'b1;
ret_addr_in=30\'h12340002;
$display("%time, push 3nd addr: %h into ras",$time,ret_addr_in);
$fdisplay(log_file,"%time, push 3nd addr: %h into ras",$time,ret_addr_in);
`clk_step
///push 4th addr into ras
en_call_in=1\'b1;
ret_addr_in=30\'h12340003;
$display("%time, push 4nd addr: %h into ras",$time,ret_addr_in);
$fdisplay(log_file,"%time, push 4nd addr: %h into ras",$time,ret_addr_in);
`clk_step
///push 5th addr into ras
en_call_in=1\'b1;
ret_addr_in=30\'h12340004;
$display("%time, push 5nd addr: %h into ras",$time,ret_addr_in);
$fdisplay(log_file,"%time, push 5nd addr: %h into ras",$time,ret_addr_in);
`clk_step
///push 6th addr into ras
en_call_in=1\'b1;
ret_addr_in=30\'h12340005;
$display("%time, push 6nd addr: %h into ras",$time,ret_addr_in);
$fdisplay(log_file,"%time, push 6nd addr: %h into ras",$time,ret_addr_in);
`clk_step
///push 7th addr into ras
en_call_in=1\'b1;
ret_addr_in=30\'h12340006;
$display("%time, push 7nd addr: %h into ras",$time,ret_addr_in);
$fdisplay(log_file,"%time, push 7nd addr: %h into ras",$time,ret_addr_in);
`clk_step
///push 8th addr into ras
en_call_in=1\'b1;
ret_addr_in=30\'h12340007;
$display("%time, push 8nd addr: %h into ras",$time,ret_addr_in);
$fdisplay(log_file,"%time, push 8nd addr: %h into ras",$time,ret_addr_in);
//////////////////////////////////////////////////////
///////then we can pop the pushed addrs one by one ///
`clk_step
en_call_in=1\'b0;
///pop 8th addr 30\'h12340007;
en_ret_in=1\'b1;
`clk_step
$display("%time, pop 8st addr: %h pop 8th addr 30\'h12340007;",$time,ret_addr_out);
$fdisplay(log_file,"%time, pop 8st addr: %h pop 8th addr 30\'h12340007;",$time,ret_addr_out);
///pop 7th addr 30\'h12340006;
`clk_step
$display("%time, pop 7st addr: %h pop 7th addr 30\'h12340006;",$time,ret_addr_out);
$fdisplay(log_file,"%time, pop 7st addr: %h pop 7th addr 30\'h12340006;",$time,ret_addr_out);
///pop 6th addr 30\'h12340005;
`clk_step
$display("%time, pop 6st addr: %h pop 6th addr 30\'h12340005;",$time,ret_addr_out);
$fdisplay(log_file,"%time, pop 6st addr: %h pop 6th addr 30\'h12340005;",$time,ret_addr_out);
///pop 5th addr 30\'h12340004;
`clk_step
$display("%time, pop 5st addr: %h pop 5th addr 30\'h12340004;",$time,ret_addr_out);
$fdisplay(log_file,"%time, pop 5st addr: %h pop 5th addr 30\'h12340004;",$time,ret_addr_out);
///pop 4th addr 30\'h12340003;
`clk_step
$display("%time, pop 4st addr: %h pop 4th addr 30\'h12340003;",$time,ret_addr_out);
$fdisplay(log_file,"%time, pop 4st addr: %h pop 4th addr 30\'h12340003;",$time,ret_addr_out);
///pop 3th addr 30\'h12340002;
`clk_step
$display("%time, pop 3st addr: %h pop 3th addr 30\'h12340002;",$time,ret_addr_out);
$fdisplay(log_file,"%time, pop 3st addr: %h pop 3th addr 30\'h12340002;",$time,ret_addr_out);
///pop 2th addr 30\'h12340001;
`clk_step
$display("%time, pop 2st addr: %h pop 2th addr 30\'h12340001;",$time,ret_addr_out);
$fdisplay(log_file,"%time, pop 2st addr: %h pop 2th addr 30\'h12340001;",$time,ret_addr_out);
///pop 1st addr 30\'h12340000;
`clk_step
$display("%time, pop 1st addr: %h pop 1st addr 30\'h12340000;",$time,ret_addr_out);
$fdisplay(log_file,"%time, pop 1st addr: %h pop 1st addr 30\'h12340000;",$time,ret_addr_out);
`clk_step
en_ret_in=1\'b0;
`clk_step
`clk_step
////////////////////////////////////////////////////////////////
///////////2nd case: pred non-ret inst as a ret inst////////////
////////////////////////////////////////////////////////////////
//////note : en_call_in pop addr of ras ,while en_ret_in push ret_addr_in into ras!
`clk_step
///first push a addr 12340078
en_call_in=1\'b1;
ret_addr_in=30\'h12340078;
$display("%time, push addr: %h into ras",$time,ret_addr_in);
$fdisplay(log_file,"%time, push addr: %h into ras",$time,ret_addr_in);
`clk_step
///second push a addr 12340077
ret_addr_in=30\'h12340077;
$display("%time, push addr: %h into ras",$time,ret_addr_in);
$fdisplay(log_file,"%time, push addr: %h into ras",$time,ret_addr_in);
`clk_step
en_call_in=1\'b0;
en_ret_in=1\'b1;///this is a non-ret inst!
$display("%time, pop addr: %h ",$time,ret_addr_out);
$fdisplay(log_file,"%time, pop addr: %h ",$time,ret_addr_out);
`clk_step
en_ret_in=1\'b0;
//////////////////////////////////////////////////////////////////
/////1st case : there is not another operations concurrently /////
//////////////////////////////////////////////////////////////////
///here is a recover to push poped addr which is incorrectly poped
recover_push=1\'b1;
recover_push_addr=30\'h12340077;
$display("%time, recover_push_addr=30\'h12340077;",$time);
$fdisplay(log_file,"%time,recover_push_addr=30\'h12340077;",$time);
`clk_step
recover_push=1\'b0;
`clk_step
`clk_step
///this cycle a addr is pushed correctly into ras
en_call_in=1\'b1;
ret_addr_in=30\'h12340076;
$display("%time, push addr: %h into ras",$time,ret_addr_in);
$fdisplay(log_file,"%time, push addr: %h into ras",$time,ret_addr_in);
`clk_step
////note :there are three addrs in the ras! 12340078 and 12340077 12340076
en_call_in=1\'b0;
`clk_step
///here is a fake ret
en_ret_in=1\'b1;
$display("%time, pop addr: %h ",$time,ret_addr_out);
$fdisplay(log_file,"%time, pop addr: %h ",$time,ret_addr_out);
`clk_step
en_ret_in=1\'b0;
///////////////////////////////////////////////////////////////////////
//////2nd case: there is concurrent ret when a recover_push comes/////
///////////////////////////////////////////////////////////////////////
///the fake inst is found not a ret in decode stage ,so it is recovered from decode
recover_push=1\'b1;
recover_push_addr=30\'h12340076;
///at the same time ,the real ret is calling the addr in the head of ras, then the ret_addr_out should be 30\'h12340076;
en_ret_in=1\'b1;
$display("%time, pop addr: %h ret_addr_out should be 30\'h12340076;",$time,ret_addr_out);
$fdisplay(log_file,"%time, pop addr: %h ret_addr_out should be 30\'h12340076;",$time,ret_addr_out);
`clk_step
recover_push=1\'b0;
en_ret_in=1\'b0;
`clk_step
`clk_step
/// a fake ret pop the addr in the head of ras 30\'h12340077
en_ret_in=1\'b1;
$display("%time, pop addr: %h ret_addr_out should be 30\'h12340077;",$time,ret_addr_out);
$fdisplay(log_file,"%time, pop addr: %h ret_addr_out should be 30\'h12340077;",$time,ret_addr_out);
`clk_step
////////////////////////////////////////////////////////////////////////
///////3rd case:there is concurrent push when a recover comes!//////////
////////////////////////////////////////////////////////////////////////
en_ret_in=1\'b0;
recover_push=1\'b1;
recover_push_addr=30\'h12340077;
en_call_in=1\'b1;
ret_addr_in=30\'h12340075;
//after this cycle, the stack should be 30\'h12340075; 30\'h12340077; 12340078 from top to root.
`clk_step
en_call_in=1\'b0;
recover_push=1\'b0;
`clk_step
en_ret_in=1\'b1; // ret_addr_out is 30\'h12340075;
$display("%time, pop addr: %h ret_addr_out is 30\'h12340075;",$time,ret_addr_out);
$fdisplay(log_file,"%time, pop addr: %h ret_addr_out is 30\'h12340075;",$time,ret_addr_out);
`clk_step
en_ret_in=1\'b0;
`clk_step
en_ret_in=1\'b1; // ret_addr_out is 30\'h12340077;
$display("%time, pop addr: %h ret_addr_out is 30\'h12340077;",$time,ret_addr_out);
$fdisplay(log_file,"%time, pop addr: %h ret_addr_out is 30\'h12340077;",$time,ret_addr_out);
`clk_step
en_ret_in=1\'b0;
`clk_step
en_ret_in=1\'b1; // ret_addr_out is 30\'h12340078;
$display("%time, pop addr: %h ret_addr_out is 30\'h12340078;",$time,ret_addr_out);
$fdisplay(log_file,"%time, pop addr: %h ret_addr_out is 30\'h12340078;",$time,ret_addr_out);
////////////////////////////////////////////////////////////////
///////////3rd case: pred non-call as a call////////////////////
////////////////////////////////////////////////////////////////
`clk_step
///first push a addr 20160405
en_ret_in=1\'b0;
en_call_in=1\'b1;
ret_addr_in=30\'h20160405;
$display("%time, push addr: %h into ras",$time,ret_addr_in);
$fdisplay(log_file,"%time, push addr: %h into ras",$time,ret_addr_in);
`clk_step
///push a addr 20160404
ret_addr_in=30\'h20160404;
$display("%time, push addr: %h into ras",$time,ret_addr_in);
$fdisplay(log_file,"%time, push addr: %h into ras",$time,ret_addr_in);
`clk_step
en_call_in=1\'b1;///this is a non-call inst!
ret_addr_in=30\'h20000406;
$display("%time, push addr: %h into ras ;this is a non-call inst!",$time,ret_addr_in);
$fdisplay(log_file,"%time, push addr: %h into ras ;this is a non-call inst!",$time,ret_addr_in);
`clk_step
en_call_in=1\'b0;
/////////////////////////////////////////////////////////////
/////////1st case :there is no another operations ///////////
/////////////////////////////////////////////////////////////
/// I want to pop the wrong pred target pushed on the head of ras in the previous cycle
/// just revise the tail pointer!
recover_pop=1\'b1;
////now 20160405 and 20160404 are in the ras
`clk_step
recover_pop=1\'b0;
en_call_in=1\'b1;
ret_addr_in=30\'h20160403;// 3 4 5 from top to root
`clk_step
`clk_step
en_call_in=1\'b1;
ret_addr_in=30\'h20000404;/// a wrong ret addr, then 4 3 4 5 from top to root
`clk_step
en_call_in=1\'b0;
`clk_step
/////////////////////////////////////////////////////////////
////////2nd case:there is a ret when a recover_pop///////////
/////////////////////////////////////////////////////////////
recover_pop=1\'b1;
en_ret_in=1\'b1; // the ret_addr_out should be 30\'h20160403;
`clk_step
recover_pop=1\'b0;
en_ret_in=1\'b0;
`clk_step
`clk_step
en_call_in=1\'b1;
ret_addr_in=30\'h20000403; // the stack should be 30\'h20000403; 20160404 20160405 from top to root
`clk_step
en_call_in=1\'b0;
`clk_step
//////////////////////////////////////////////////////////////
////////3rd case: there is call when a recover_pop////////////
//////////////////////////////////////////////////////////////
recover_pop=1\'b1;
en_call_in=1\'b1;
ret_addr_in=30\'h20160403; //the stack should be 20160403; 20160404 20160405 from top to root
`clk_step
recover_pop=1\'b0;
en_call_in=1\'b0;
`clk_step
///now there are 3 addrs in the ras :30\'h20160403 30\'h20160404 30\'h20160405
/// and we now pop them one by one to check the behavior of ras
en_ret_in=1\'b1;//ret_addr_out should be 20160403;
`clk_step
en_ret_in=1\'b0;
`clk_step
en_ret_in=1\'b1;//ret_addr_out should be 20160404;
`clk_step
en_ret_in=1\'b0;
`clk_step
en_ret_in=1\'b1;//ret_addr_out should be 20160405;
`clk_step
en_ret_in=1\'b0;
`clk_step
$stop;
end
endmodule
|
/// date:2016/3/9
/// engineer: ZhaiShaoMin
/// module name ic_download
/// module function: receiving rep flits from local memory or IN_rep fifo
module ic_download(//input
clk,
rst,
rep_flit_ic,
v_rep_flit_ic,
rep_ctrl_ic,
mem_flits_ic,
v_mem_flits_ic,
//output
ic_download_state,
inst_word_ic,
v_inst_word
);
//input
input clk;
input rst;
input [15:0] rep_flit_ic;
input v_rep_flit_ic;
input [1:0] rep_ctrl_ic;
input [127:0] mem_flits_ic;
input v_mem_flits_ic;
//output
output [1:0] ic_download_state;
output [127:0] inst_word_ic;
output v_inst_word;
//reg for inst word
reg [127:0] inst_word ;
reg [1:0] ic_download_nstate;
reg [1:0] ic_download_cstate;
parameter ic_download_idle=2'b00;
parameter ic_download_busy=2'b01;
parameter ic_download_rdy=2'b10;
assign ic_download_state=ic_download_cstate;
assign inst_word_ic=inst_word;
//assign inst_word_ic={inst_word[127:112],inst_word[111:96],inst_word[95:80],inst_word[79:64],inst_word[63:48],inst_word[47:32],inst_word[31:16],inst_word[15:0]};
reg v_inst_word;
reg en_mem_flits_ic;
reg en_rep_flit_ic;
reg inc_cnt;
reg fsm_rst;
reg [127:0] inst_word_in;
/// fsm of ic_download
always@(*)
begin
//default values
ic_download_nstate=ic_download_cstate;
v_inst_word=1'b0;
en_mem_flits_ic=1'b0;
en_rep_flit_ic=1'b0;
inc_cnt=1'b0;
fsm_rst=1'b0;
inst_word_in=128'h0000;
case(ic_download_cstate)
ic_download_idle:
begin
if(v_mem_flits_ic)
begin
ic_download_nstate=ic_download_rdy;
inst_word_in=mem_flits_ic;
en_mem_flits_ic=1'b1;
end
else if(v_rep_flit_ic)
begin
ic_download_nstate=ic_download_busy;
en_rep_flit_ic=1'b1;
end
end
ic_download_busy:
begin
if(rep_ctrl_ic==2'b11)
begin
en_rep_flit_ic=1'b1;
// inc_cnt=1'b1;
ic_download_nstate=ic_download_rdy;
end
else if(rep_ctrl_ic==2'b10)
begin
en_rep_flit_ic=1'b1;
inc_cnt=1'b1;
end
end
ic_download_rdy:
begin
v_inst_word=1'b1;
ic_download_nstate=ic_download_idle;
fsm_rst=1'b1;
end
endcase
end
reg [2:0] cnt;
reg [7:0] en_instword;
// select right inst_word_in
always@(*)
begin
case(cnt)
3'b000:en_instword=8'b00000001;
3'b001:en_instword=8'b00000010;
3'b010:en_instword=8'b00000100;
3'b011:en_instword=8'b00001000;
3'b100:en_instword=8'b00010000;
3'b101:en_instword=8'b00100001;
3'b110:en_instword=8'b01000001;
3'b111:en_instword=8'b10000001;
default:en_instword=8'b00000000;
endcase
end
// 1th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
begin
inst_word[15:0]<=16'h0000;
end
else if(en_mem_flits_ic)
inst_word[15:0]<=inst_word_in[15:0];
else if(en_rep_flit_ic&&en_instword[0])
inst_word[15:0]<=inst_word_in[15:0];
end
// 2ed flit
always@(posedge clk)
begin
if(rst||fsm_rst)
begin
inst_word[31:16]<=16'h0000;
end
else if(en_mem_flits_ic)
inst_word[31:16]<=inst_word_in[31:16];
else if(en_rep_flit_ic&&en_instword[1])
inst_word[31:16]<=inst_word_in[31:16];
end
//3rd flit
always@(posedge clk)
begin
if(rst||fsm_rst)
begin
inst_word[47:32]<=16'h0000;
end
else if(en_mem_flits_ic)
inst_word[47:32]<=inst_word_in[47:32];
else if(en_rep_flit_ic&&en_instword[2])
inst_word[47:32]<=inst_word_in[47:32];
end
//4th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
begin
inst_word[63:48]<=16'h0000;
end
else if(en_mem_flits_ic)
inst_word[63:48]<=inst_word_in[63:48];
else if(en_rep_flit_ic&&en_instword[3])
inst_word[63:48]<=inst_word_in[63:48];
end
// 5th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
begin
inst_word[79:64]<=16'h0000;
end
else if(en_mem_flits_ic)
inst_word[79:64]<=inst_word_in[79:64];
else if(en_rep_flit_ic&&en_instword[4])
inst_word[79:64]<=inst_word_in[79:64];
end
//6th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
begin
inst_word[95:80]<=16'h0000;
end
else if(en_mem_flits_ic)
inst_word[95:80]<=inst_word_in[95:80];
else if(en_rep_flit_ic&&en_instword[5])
inst_word[95:80]<=inst_word_in[95:80];
end
//7th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
begin
inst_word[111:96]<=16'h0000;
end
else if(en_mem_flits_ic)
inst_word[111:96]<=inst_word_in[111:96];
else if(en_rep_flit_ic&&en_instword[6])
inst_word[111:96]<=inst_word_in[111:96];
end
//8th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
begin
inst_word[127:112]<=16'h0000;
end
else if(en_mem_flits_ic)
inst_word[127:112]<=inst_word_in[127:112];
else if(en_rep_flit_ic&&en_instword[7])
inst_word[127:112]<=inst_word_in[127:112];
end
always@(posedge clk)
begin
if(rst)
ic_download_cstate<=2'b00;
else
ic_download_cstate<=ic_download_nstate;
end
always@(posedge clk)
begin
if(rst||fsm_rst)
cnt<=3'b000;
else if(inc_cnt)
cnt<=cnt+3'b001;
end
endmodule
|
/******2016/7/25 AM 10:36**************
A.core
B.memory system
C.interconnection network
A-1 reg1 of PC should be moved to reg2 of branch predicter, both reg1 and reg2 save PC here to obey cycle behavior.
A-2 submodule net link, I think it should be maintained in a easy way, good style naming.
A-3 optimize the ALU unit to implement multiple ALU ops via an addr.
A-4 same as A-1, I should move reg of pipeline to input register of SRAM blocks, such as INST cache SRAM, and DATA cache SRAM.
A-5 I should implement regfile with a style: register input & non_reg for output.
B-1 rethink the cpusidecache ctrler and memsidecache ctrler, refer to hardware design pattern(HDP).
B-2 since we implement inst cache with sram, we need to rethink the microarchitecture of them.
B-3 check out if there is any deadlock or livelock inside memory system, refer to HDP.
C-1 we should consider multiple clock domain to improve performance, refer to some books.
C-2 how should I implement a deadlock free interconnecton network, rethink the algorithm, refer to computer network.
I should add core and memory document to project introduction.
******************************************/
|
//date: 2016/3/13
//engineer :ZhaiShaoMin
//module name :ring_node
//module function: It includes network_interface , commu_assist ,core ,inst cache ,data cache and memory.
module ring_node(//input
clk,
rst,
ctrl_in, //[1:0] for guiding flit flowing ; 00:nothing, 01:head flit, 10:body flit, 11:tail flit
flit_in,
dest_fifo_in,
en_local_req_in,
en_local_rep_in,
en_pass_req_in,
en_pass_rep_in,
used_slots_pass_req_in,
used_slots_pass_rep_in,
//output
en_local_req, // to previous node refer to below notes
en_local_rep,
en_pass_req, // from next node //local_in_req fifo in next node says that it can receive
en_pass_rep, // refer to notes below
used_slots_pass_req,
used_slots_pass_rep,
flit_out,
ctrl_out,
dest_fifo_out
);
//input
input clk;
input rst;
input [1:0] ctrl_in; //[1:0] for guiding flit flowing ; 00:nothing, 01:head flit, 10:body flit, 11:tail flit
input [15:0] flit_in;
input [1:0] dest_fifo_in;
input en_local_req_in;
input en_local_rep_in;
input en_pass_req_in;
input en_pass_rep_in;
input [3:0] used_slots_pass_req_in;
input [3:0] used_slots_pass_rep_in;
//output
output en_local_req; // to previous node refer to below notes
output en_local_rep;
output en_pass_req; // from next node //local_in_req fifo in next node says that it can receive
output en_pass_rep; // refer to notes below
output [3:0] used_slots_pass_req;
output [3:0] used_slots_pass_rep;
output [15:0] flit_out;
output [1:0] ctrl_out;
output [1:0] dest_fifo_out;
// top- down
// network interface output
wire [17:0] deq_req_data; //[17:0]cache or memory dequeue a flit from IN_local req fifo
wire [17:0] deq_rep_data; //[17:0]cache or memory dequeue a flit from IN_local rep fifo
wire en_local_req; // to previous node refer to below notes
wire en_local_rep;
wire en_pass_req; // from next node //local_in_req fifo in next node says that it can receive
wire en_pass_rep; // refer to notes below
wire [3:0] used_slots_pass_req;
wire [3:0] used_slots_pass_rep;
wire [15:0] flit_out;
wire [1:0] ctrl_out;
wire [1:0] dest_fifo_out;
wire req_rdy;
wire rep_rdy;
wire OUT_req_rdy;
wire OUT_rep_rdy;
//commu assist output
// output
wire ack_rep; // arbiter tell IN rep fifo that it's ready to receive flit,
// as well as been used by IN rep fifo as a deq rdy signal
wire ack_req; //req_rep and req_req are better!
// output
wire [1:0] OUT_req_ctrl; // used to tell the frame of msg. 00 means nothing 01 means head flit,
// 10 means body flit,11 means tail flit, exception is invrep which has only one flit.
wire [15:0] OUT_req_flit; // flit outputed to OUT req fifo
wire OUT_req_ack; // same as rdy signal saying now I'm a valid flit, also a enq signal for OUT req fifo
wire [1:0] OUT_rep_ctrl; // similar function as above
wire [15:0] OUT_rep_flit;
wire OUT_rep_ack;
wire v_inst_rep; // saying that is a valid rep data back to pipeline
wire [31:0] inst_data; // rep data (inst word) back to pipeline.
wire [143:0] flits_dcache; // arbiter select a flits to dcache
wire v_flits_dcache; // means it's a valid flits to dcache
// output
wire v_m_download; // valic flits from m_download to mem
wire [175:0] m_donwload; //flits from m_download to mem
wire v_d_m_areg; // valid flits from d_m_areg to mem
wire [175:0] d_m_areg; // flits from d_m_areg to mem
wire v_i_m_areg;
wire [31:0] i_m_areg;
wire [1:0] ic_download_fsm_state; //here are some fsm state indicating whether some state elements is idle or busy
wire m_d_areg_fsm_state; // which is useful to decide whether or not to output flits from mem to these elements
wire m_rep_fsm_state;
wire m_req_fsm_state;
wire [1:0] d_m_areg_fsm_state; // fsm state outputed from commu_assist intended to tell dcache if it's able
// to send flits to these units
wire [1:0] dc_req_fsm_state;
wire [1:0] dc_rep_fsm_state;
//dcache_cpu_network_ctrler output
//output to cpu access regs saying that data cache doesn't need cpu_addr anymore!
wire done_access_cpu_addr;
//output to tell arbiter that data cache has been accessed!
wire dcache_done_access;
//output to d_m_areg when the generated msg is a local msg
wire [175:0] flits_d_m_areg; // at most 11 flits
wire v_flits_d_m_areg;
//output to dc_upload_req regs
wire [47:0] flits_dc_upload_req; // always 3 flits
wire v_flits_dc_upload_req;
wire en_flit_max_req_d;
wire [1:0] flit_max_req_d;
//output to dc_upload_rep regs
wire [175:0] flits_dc_upload_rep; // at most 11 flits
wire v_flits_dc_upload_rep;
wire en_flit_max_rep_d;
wire [3:0] flit_max_rep_d;
// output to cpu tell whether cpu access has done
wire [31:0] data_cpu;
wire v_rep_cpu;
//inst cache output
wire v_ic_req;
wire local_or_OUT; //1:local ,0:OUT_req
wire [47:0] req_msg;
wire v_inst;
wire [31:0] inst;
//memory output
// output to local d cache
wire v_req_d;
wire v_rep_d;
wire [15:0] head_out_local_d;
wire [31:0] addr_out_local_d;
wire [127:0] data_out_local_d;
// output to local i cahce
wire v_rep_i;
wire [127:0] data_out_local_i;
// output to OUT req fifo
wire en_inv_ids;
wire [3:0] inv_ids_in;
wire [1:0] flit_max_req_m;
wire en_flit_max_req_m;
wire v_req_out;
wire [15:0] head_out_req_out;
wire [31:0] addr_out_req_out;
wire [127:0] data_out_req_out;
// output to OUT rep fifo
wire [3:0] flit_max_rep_m;
wire en_flit_max_rep_m;
wire v_rep_out;
wire [15:0] head_out_rep_out;
wire [31:0] addr_out_rep_out;
wire [127:0] data_out_rep_out;
// core output
//output
wire [31:0] pc;
wire v_pc;
wire v_mem;
wire [3:0] mem_head;
wire [31:0] mem_addr;
wire [31:0] mem_data;
network_interface my_NI (
//input
.clk(clk), //global clock
.rst(rst), //global reset
.ctrl_in(ctrl_in), //[2:0] for guiding flit flowing ; 00:nothing, 01:head flit, 10:body flit, 11:tail flit
//ctrl[2] 1:next_node; 0:not_next_node;
.flit_in(flit_in),
.dest_fifo_in(dest_fifo_in),
.en_IN_req_deq(ack_req), // from arbiter_for_IN_node in commu_assist
.en_IN_rep_deq(ack_rep),
.enq_req_data({OUT_req_ctrl,OUT_req_flit}), // from arbiter_for_OUT_req fifo in commu_assist (include ctrl)
.enq_rep_data({OUT_rep_ctrl,OUT_rep_flit}), // from arbiter_for_OUT_rep fifo in commu_assist (include ctrl)
.en_OUT_req_enq(OUT_req_ack), // from arbiter_for_OUT_req fifo in commu_assist
.en_OUT_rep_enq(OUT_rep_ack), // from arbiter_for_OUT_rep fifo in commu_assist
.en_local_req_in(en_local_req_in),
.en_local_rep_in(en_local_rep_in),
.en_pass_req_in(en_pass_req_in),
.en_pass_rep_in(en_pass_rep_in),
.used_slots_pass_req_in(used_slots_pass_req_in),
.used_slots_pass_rep_in(used_slots_pass_rep_in), //the pass req fifo of next node says it can receive a flit
//output
.deq_req_data(deq_req_data), //[17:0]cache or memory dequeue a flit from IN_local req fifo
.deq_rep_data(deq_rep_data), //[17:0]cache or memory dequeue a flit from IN_local rep fifo
.req_rdy(req_rdy),
.rep_rdy(rep_rdy),
.en_local_req(en_local_req), // to previous node refer to below notes
.en_local_rep(en_local_rep),
.en_pass_req(en_pass_req), // from next node //local_in_req fifo in next node says that it can receive
.en_pass_rep(en_pass_rep), // refer to notes below
.used_slots_pass_req(used_slots_pass_req),
.used_slots_pass_rep(used_slots_pass_rep),
.flit_out(flit_out),
.ctrl_out(ctrl_out),
.dest_fifo_out(dest_fifo_out),
.OUT_req_rdy(OUT_req_rdy),
.OUT_rep_rdy(OUT_rep_rdy)
);
commu_assist my_CA(//input
.clk(clk),
.rst(rst),
// I/O between arbiter and IN fifos
// input
.req_flit_in(deq_req_data[15:0]), //flit from IN req fifo
.req_rdy(req_rdy), // it's ready for arbiter_IN_node to dequeue flit from In req fifo
.req_ctrl_in(deq_req_data[17:16]), //control signals from In fifo indicate what kind of flit under transfering
.rep_flit_in(deq_rep_data[15:0]),
.rep_rdy(rep_rdy),
.rep_ctrl_in(deq_rep_data[17:16]),
// output
.ack_rep(ack_rep), // arbiter tell IN rep fifo that it's ready to receive flit,
// as well as been used by IN rep fifo as a deq rdy signal
.ack_req(ack_req), //req_rep and req_req are better!
/// I/O about OUT_req/rep fifo
//input
.OUT_req_rdy(OUT_req_rdy), // arbiter_OUT_req tell OUT req fifo to be ready to receive flit from commu_assist
.OUT_rep_rdy(OUT_rep_rdy), // arbiter_OUT_rep ......
// output
.OUT_req_ctrl(OUT_req_ctrl), // used to tell the frame of msg. 00 means nothing 01 means head flit,
// 10 means body flit,11 means tail flit, exception is invrep which has only one flit.
.OUT_req_flit(OUT_req_flit), // flit outputed to OUT req fifo
.OUT_req_ack(OUT_req_ack), // same as rdy signal saying now I'm a valid flit, also a enq signal for OUT req fifo
.OUT_rep_ctrl(OUT_rep_ctrl), // similar function as above
.OUT_rep_flit(OUT_rep_flit),
.OUT_rep_ack(OUT_rep_ack),
/// I/O about inst cache
// input
// .v_req_inst(), // indicate that's a valid inst request from pc
// .pc_addr(), // addr of pc used to look up inst cache to find intended inst
// to OUT_req
.v_flits_2_ic_req(local_or_OUT), // saying I'm a valid req flits to OUT req fifo
.flits_2_ic_req(req_msg), // req flits output to OUT req fifo
// to local mem
.v_req_i_m_areg(!local_or_OUT), // saying I'm a valid req flits to local home(memory)
.req_i_m_areg(req_msg[31:0]), // req flits output to local home
// output
.v_inst_rep(v_inst_rep), // saying that is a valid rep data back to pipeline
.inst_data(inst_data), // rep data (inst word) back to inst cahe.
/// I/O about data cache
// input
.dcache_done_access(dcache_done_access), // data cache tell arbiter_for_dcache previous access had done via this signal
// output
.flits_dcache(flits_dcache), // arbiter select a flits to dcache
.v_flits_dcache(v_flits_dcache), // means it's a valid flits to dcache
/// I/O about cpu_req_cache about ll/ld/st/sc
// input
.v_cpu_access(v_mem), // means it's a valid access from pipeline
.cpu_head(mem_head), // this part include access ctrl info such as ll or ld ,sc or st ,wr or rd
.cpu_addr(mem_addr), //addr of mem ops
.cpu_data(mem_data), // data of store or store-condition
/// I/O about memory
// input
.ack_m_donwload(v_m_download), // response to m_download saying i'm now reading flits
.ack_d_m_donwload(v_d_m_areg), // similar as above
.ack_i_m_donwload(v_i_m_areg), //similar as above
.mem_access_done(mem_access_done),
.mem_ic_download(data_out_local_i), // flits from mem to ic_download
.v_mem_ic_download(v_rep_i), // flit above is valid
.mem_m_d_areg({head_out_local_d,addr_out_local_d,data_out_local_d}), // flits from mem to m_d_areg
.v_mem_m_d_areg(v_req_d||v_rep_d), // it's a valid flits to m_d_areg
.mem_m_req({head_out_rep_out,addr_out_rep_out}), // similar as above
.v_mem_m_req(v_req_out),
.mem_m_rep({head_out_rep_out,addr_out_rep_out,data_out_rep_out}),
.v_mem_m_rep(v_rep_out), //similar as above
.en_m_flits_max_rep(en_flit_max_rep_m),
.m_flits_max_rep(flit_max_rep_m),
.en_m_flits_max_req(en_flit_max_req_m),
.m_flits_max_req(flit_max_req_m),
.en_inv_ids(en_inv_ids),
.inv_ids_in(inv_ids_in),
// output
.v_m_download(v_m_download), // valic flits from m_download to mem
.m_donwload(m_donwload), //flits from m_download to mem
.v_d_m_areg(v_d_m_areg), // valid flits from d_m_areg to mem
.d_m_areg(d_m_areg), // flits from d_m_areg to mem
.v_i_m_areg(v_i_m_areg),
.i_m_areg(i_m_areg),
.ic_download_fsm_state(ic_download_fsm_state), //here are some fsm state indicating whether some state elements is idle or busy
.m_d_areg_fsm_state(m_d_areg_fsm_state), // which is useful to decide whether or not to output flits from mem to these elements
.m_rep_fsm_state(m_rep_fsm_state),
.m_req_fsm_state(m_req_fsm_state),
/// I/O about data cache
//input
.dcache_d_m_areg(flits_d_m_areg), //access via flits from data cache to local mem
.v_dcache_d_m_areg(v_flits_d_m_areg), // means it's avalid access
.dcache_dc_req(flits_dc_upload_req), // access via flits to OUT_req_upload corresponding to dcache
.v_dcache_dc_req(v_flits_dc_upload_req), // means it's avalid access
.dcache_dc_rep(flits_dc_upload_rep),
.v_dcache_dc_rep(v_flits_dc_upload_rep),
.en_dc_flits_max_rep(en_flit_max_rep_d),
.dc_flits_max_rep(flit_max_rep_d),
/// output
.d_m_areg_fsm_state(d_m_areg_fsm_state), // fsm state outputed from commu_assist intended to tell dcache if it's able
// to send flits to these units
.dc_req_fsm_state(dc_req_fsm_state),
.dc_rep_fsm_state(dc_rep_fsm_state)
);
dcache_cpu_network_ctrler
my_dc( //global ctrl signals
.clk(clk),
.rst(rst),
//input from arbiter_for_dcache
.flits_in(flits_dcache),
.v_flits_in(v_flits_dcache),
.v_cpu_req(v_mem),
// input from cpu access regs used for cpu_side wait state:shrep or exrep or SH_exrep or invrep
.cpu_addr_for_wait(mem_addr),
.v_cpu_addr_for_wait(v_mem),
.cpu_access_head(mem_head),
//input from dc_upload_req regs : fsm_state to tell dcache whether it's idle
.d_req_state(dc_req_fsm_state),
//input from dc_upload_rep regs : fsm state to tell dcache whether it's idle
.d_rep_state(dc_rep_fsm_state),
// input from d_m_areg(=>data cache to mem access regs) :fsm state. used to tell dcache whether it's idle
.m_fsm_state(d_m_areg_fsm_state),
//output to cpu access regs saying that data cache doesn't need cpu_addr anymore!
.done_access_cpu_addr(done_access_cpu_addr),
//output to tell arbiter that data cache has been accessed!
.dcache_done_access(dcache_done_access),
//output to d_m_areg when the generated msg is a local msg
.flits_d_m_areg(flits_d_m_areg), // at most 11 flits
.v_flits_d_m_areg(v_flits_d_m_areg),
//output to dc_upload_req regs
.flits_dc_upload_req(flits_dc_upload_req), // always 3 flits
.v_flits_dc_upload_req(v_flits_dc_upload_req),
.en_flit_max_req(en_flit_max_req_d),
.flit_max_req(flit_max_req_d),
//output to dc_upload_rep regs
.flits_dc_upload_rep(flits_dc_upload_rep), // at most 11 flits
.v_flits_dc_upload_rep(v_flits_dc_upload_rep),
.en_flit_max_rep(en_flit_max_rep_d),
.flit_max_rep(flit_max_rep_d),
// output to cpu tell whether cpu access has done
.data_cpu(data_cpu),
.v_rep_cpu(v_rep_cpu)
);
//wire [47:0] req_msg_local;
//wire [47:0] req_msg_OUT;
//assign req_msg_local=local_or_OUT?48'hzzzz:req_msg;
//assign req_msg_OUT=local_or_OUT?req_msg:48'hzzzz;
// here should be inst cache ,but by now i haven't written it
inst_cache my_ic(//input
.clk(clk),
.rst(rst),
// from pc
.v_pc(v_pc),
.pc(pc),
//from ic_download
.inst_4word(inst_data),
.v_inst_4word(v_inst_rep),
//output
// to local mem or OUT_req upload
.v_ic_req(v_ic_req),
.local_or_OUT(local_or_OUT), //1:local ,0:OUT_req
.req_msg(req_msg),
.v_inst(v_inst),
.inst(inst)
);
memory my_mem(//input
.clk(clk),
.rst(rst),
//fsm state of rep paralle-serial port corresponding to mem
.m_rep_fsm_state(m_rep_fsm_state),
//fsm state of req paralle-serial port corresponding to mem
.m_req_fsm_state(m_req_fsm_state),
// fsm state of req paralle-serial port corresponding to data cache
.d_fsm_state(m_d_areg_fsm_state),
// input from local d cache
.v_d_req(v_flits_d_m_areg),
.v_d_rep(v_flits_d_m_areg),
.local_d_head_in(flits_d_m_areg[175:160]),
.local_d_addr_in(flits_d_m_areg[159:128]),
.local_d_data_in(flits_d_m_areg[127:0]),
// input from local i cache
.v_i_rep(!local_or_OUT),
// local_i_head, // no need for local i cache miss
.local_i_addr_in(req_msg[31:0]),
// input form INfifos
.v_INfifos(v_m_download),
.infifos_head_in(m_donwload[175:160]),
.infifos_addr_in(m_donwload[159:128]),
.infifos_data_in(m_donwload[127:0]),
// output to local d cache
.v_req_d(v_req_d),
.v_rep_d(v_rep_d),
.head_out_local_d(head_out_local_d),
.addr_out_local_d(addr_out_local_d),
.data_out_local_d(data_out_local_d),
// output to local i cahce
.v_rep_i(v_rep_i),
.data_out_local_i(data_out_local_i),
// output to OUT req fifo
.en_inv_ids(en_inv_ids),
.inv_ids_in(inv_ids_in),
.flit_max_req(flit_max_req_m),
.en_flit_max_req(en_flit_max_req_m),
.v_req_out(v_req_out),
.head_out_req_out(head_out_req_out),
.addr_out_req_out(addr_out_req_out),
// .data_out_req_out(data_out_req_out),
// output to OUT rep fifo
.flit_max_rep(flit_max_rep_m),
.en_flit_max_rep(en_flit_max_rep_m),
.v_rep_out(v_rep_out),
.head_out_rep_out(head_out_rep_out),
.addr_out_rep_out(addr_out_rep_out),
.data_out_rep_out(data_out_rep_out),
//
.mem_access_done(mem_access_done)
);
core my_core(//input
.clk(clk),
.rst(rst),
.v_inst(v_inst),
.inst(inst),
.v_data(v_rep_cpu),
.data(data_cpu),
//output
.pc(pc),
.v_pc(v_pc),
.v_mem(v_mem),
.mem_head(mem_head),
.mem_addr(mem_addr),
.mem_data(mem_data)
);
endmodule
|
/// date:2016/3/9
/// engineer: ZhaiShaoMin
module m_d_areg(//input
clk,
rst,
m_flits_d,
v_m_flits_d,
dc_done_access,
//output
m_d_areg_flits,
v_m_d_areg_flits,
m_d_areg_state
);
//input
input clk;
input rst;
input [143:0] m_flits_d;
input v_m_flits_d;
input dc_done_access;
//output
output [143:0] m_d_areg_flits;
output v_m_d_areg_flits;
output m_d_areg_state;
reg m_d_cstate;
reg [143:0] flits_reg;
assign v_m_d_areg_flits=m_d_cstate;
assign m_d_areg_state=m_d_cstate;// when m_d_cstate is 1, it means this module is busy and
// can't receive other flits. oterwise,able to receiving flits
always@(posedge clk)
begin
if(rst||dc_done_access)
flits_reg<=144'h0000;
else if(v_m_flits_d)
flits_reg<=m_flits_d;
end
always@(posedge clk)
begin
if(rst||dc_done_access)
m_d_cstate<=1'b0;
else if(v_m_flits_d)
m_d_cstate<=1'b1;
end
assign m_d_areg_flits=flits_reg;
endmodule
|
/// date:2016/3/9
/// engineer: ZhaiShaoMin
module d_m_areg(//input
clk,
rst,
d_flits_m,
v_d_flits_m,
mem_done_access,
//output
d_m_areg_flits,
v_d_m_areg_flits,
d_m_areg_state
);
//input
input clk;
input rst;
input [143:0] d_flits_m;
input v_d_flits_m;
input mem_done_access;
//output
output [175:0] d_m_areg_flits;
output v_d_m_areg_flits;
output d_m_areg_state;
reg d_m_cstate;
reg [175:0] flits_reg;
assign v_d_m_areg_flits=d_m_cstate;
assign d_m_areg_state=d_m_cstate;// when m_d_cstate is 1, it means this module is busy and
// can't receive other flits. oterwise,able to receiving flits
always@(posedge clk)
begin
if(rst||mem_done_access)
flits_reg<=175'h0000;
else if(v_d_flits_m)
flits_reg<=d_flits_m;
end
always@(posedge clk)
begin
if(rst||mem_done_access)
d_m_cstate<=1'b0;
else if(v_d_flits_m)
d_m_cstate<=1'b1;
end
assign d_m_areg_flits=flits_reg;
endmodule
|
// date:2016/3/15
//engineer: zhaishaomin
// module function: output inst_word according to coming pc ,
// if missed , it will stall the pipeline and gen a msg to find the requested cache block
// including the origal inst_word
module inst_cache (//input
clk,
rst,
// from pc
v_pc,
pc,
//from ic_download
inst_4word,
v_inst_4word,
//output
// to local mem or OUT_req upload
v_ic_req,
local_or_OUT, //1:local ,0:OUT_req
req_msg,
v_inst,
inst
);
//input
input clk;
input rst;
// from pc
input v_pc;
input [31:0] pc;
//from ic_download
input [127:0] inst_4word;
input v_inst_4word;
//output
// to local mem or OUT_req upload
output v_ic_req;
output local_or_OUT; //1:local ,0:OUT_req
output [47:0] req_msg;
output v_inst;
output [31:0] inst;
/////////////////////////////////////////////////////////////////////
////////////////inst cache data and tag//////////////////////////////
reg tag_we;
reg tag_re;
reg data_we;
reg data_re;
reg [5:0] state_tag_in;
wire [5:0] state_tag_out;
reg [31:0] seled_addr;
reg [127:0]data_write;
wire [127:0]data_read;
reg [31:0] inst1;
reg [31:0] inst2;
reg v_inst;
reg local_or_OUT;
reg [47:0] req_msg;
reg inst1_inst2;
reg v_ic_req;
SP_BRAM_SRd #(32,6,5) tag_ram(.clk(clk), .we(tag_we), .re(tag_re), .a(seled_addr[8:4]), .di(state_tag_in), .dout(state_tag_out));
SP_BRAM_SRd #(32,128,5) data_ram(.clk(clk), .we(data_we), .re(data_re), .a(seled_addr[8:4]), .di(data_write), .dout(data_read));
/////////////////////////////////////////////////////////////////////
/////////////////inst cache fsm//////////////////////////////////////
//paramter
parameter inst_idle=2'b00;
parameter inst_comp_tag=2'b01;
parameter inst_gen_req=2'b10;
parameter inst_wait_rep=2'b11;
parameter local_id=2'b00;
parameter instreq_cmd=5'b00110;
reg [1:0] inst_cstate;
reg [1:0] inst_nstate;
always@(posedge clk)
begin
if(rst)
inst_cstate<=2'b00;
else
inst_cstate<=inst_nstate;
end
//fsm always block
always@(*)
begin
//default values
v_inst=1'b0;
\t v_ic_req=1'b0;
tag_we=1'b0;
tag_re=1'b0;
data_we=1'b0;
data_re=1'b0;
state_tag_in=5'b00000;
seled_addr=32'h0000;
data_write=128'h0000;
local_or_OUT=1'b0;
req_msg=48'h0000;
inst_nstate=inst_cstate;
inst1 = data_read[31:0];
inst2 = inst_4word[31:0];
inst1_inst2=1'b0;
/////////////////////////////////////////////////
/*read out correct word(32-bit) from cache (to if_id)*/
case(pc[3:2])
2'b00:inst1 = data_read[31:0];
2'b01:inst1 = data_read[63:32];
2'b10:inst1 = data_read[95:64];
2'b11:inst1 = data_read[127:96];
endcase
/////////////////////////////////////////////////
/* read inst_word directly from inst_4word (to if_id) */
case(pc[3:2])
2'b00:inst2 = inst_4word[31:0];
2'b01:inst2 = inst_4word[63:32];
2'b10:inst2 = inst_4word[95:64];
2'b11:inst2 = inst_4word[127:96];
endcase
case(inst_cstate)
inst_idle:
begin
if(v_pc)
inst_nstate=inst_comp_tag;
end
inst_comp_tag:
begin
tag_re=1'b1;
data_re=1'b1;
if(pc[12:9]==state_tag_out[3:0])
// tag equals
begin // [5:4] 00 inv, 01 wait inst rep , 10 valid
if(state_tag_out[5:4]==2'b10)//read hit
begin
//gen read hit ctrl signals
v_inst=1'b1;
inst1_inst2=1'b0;
inst_nstate=inst_idle;
end
/* else if(state_tag_out[5:4]==2'b01) // state is inv ,so read miss
// NOTE:the core only allow one outstanding cache access,
// so there won't be a case that cpu aceesses see apending state!
begin
if(pc[12:11]==local_id)
begin
req_local_remote=1'b0;
end // local 0 ;remote 1; default :remote ?
nstate=inst_gen_req;
// oneORmore=1'b0;
end */
end
else// tag miss
begin
// gen new tag to tag ram
tag_we=1'b1;
/*new tag*/
state_tag_in = {2'b01,pc[12:9]};
inst_nstate=inst_gen_req;
end
end
inst_gen_req:
begin
if(pc[12:11]==local_id)
begin
local_or_OUT=1'b0;
end // local 0 ;remote 1; default :remote ?
req_msg={pc[12:11],1'b1,local_id,1'b0,instreq_cmd,5'b00000,pc};
\t\t\t v_ic_req=1'b1;
inst_nstate=inst_wait_rep;
end
inst_wait_rep:
begin
if(v_inst_4word)
begin
tag_re=1'b1;
data_write=inst_4word;
data_we=1'b1;
inst1_inst2=1'b1;
v_inst=1'b1;
// gen new tag to tag ram
tag_we=1'b1;
/*new tag*/
state_tag_in = {2'b10,pc[12:9]}; // 10 means valid
end
end
endcase
end
assign inst=inst1_inst2?inst2:inst1;
endmodule
|
//date:2016/8/03
//engineer:ZhaiShaoMin
//module name :excution stage of core
//module function :tset the function of core_ex
`timescale 1ns/1ps
`include "define.v"
module tb_core_ex();
//reg
reg [31:0] alusrc_a;
reg [31:0] alusrc_b;
reg [3:0] aluop;
reg regdst;
reg [1:0] alusrc;
reg [4:0] id_ex_rs;
reg [4:0] id_ex_rt;
reg [4:0] id_ex_rd;
reg mem_regwrite;
reg wb_regwrite;
reg [4:0] mem_regrd;
reg [4:0] wb_regrd;
reg [31:0] mem_reg_data;
reg [31:0] wb_reg_data;
reg [31:0] id_ex_sign_extend;
//wire
wire [31:0] alu_result;
wire [31:0] data_to_mem;
wire [4:0] ex_dest_rd;
wire zero;
core_ex duv(//input
.alusrc_a(alusrc_a),
.alusrc_b(alusrc_b),
.aluop(aluop),
.regdst(regdst),
.alusrc(alusrc),
.id_ex_rs(id_ex_rs),
.id_ex_rt(id_ex_rt),
.id_ex_rd(id_ex_rd),
.mem_regwrite(mem_regwrite),
.wb_regwrite(wb_regwrite),
.mem_regrd(mem_regrd),
.wb_regrd(wb_regrd),
.mem_reg_data(mem_reg_data),
\t\t\t\t\t\t .wb_reg_data(wb_reg_data),
.id_ex_sign_extend(id_ex_sign_extend),
//output
.alu_result(alu_result),
.data_to_mem(data_to_mem),
.ex_dest_rd(ex_dest_rd),
.zero(zero)
);
//always #5 clk=~clk;
\t
\t `define clk_step #7;
\t integer log_file ;
\t
\t
\t
\t
\t initial begin
\t
alusrc_a=32\'h00000001;
alusrc_b=32\'h00000002;
aluop=4\'b0000;
regdst=1\'b0;
alusrc=2\'b00;
id_ex_rs=1;
id_ex_rt=2;
id_ex_rd=3;
mem_regwrite=1\'b0;
wb_regwrite=1\'b0;
mem_regrd=4;
wb_regrd=5;
mem_reg_data=32\'h00000003;
\t\t wb_reg_data=32\'h00000004;
id_ex_sign_extend=32\'h00000005;
\t\t
\t\t
\t\t log_file= $fopen("tb_core_ex_logfile");
\t\t end
\t\t
\t\t
\t\t ////////////////////////////////////////////////////////////////////////////////////
\t\t //////////////////////////////////////begin test////////////////////////////////////
\tinitial begin
\t ////////////////we need to delay the time to display result compared to input////////////////////////////
\t #3;///////////////////////ensure that alu_result is ready for the ops to be displayed////////////////////////
\t /////////////////////////////////////////////////////////////////////////////////////////////////////////////
`clk_step
\t\t// rst=1\'b0;
\t\t #3;
\t\t `clk_step
\t\t
\t\t //////case 1:just test forwarding unit///////////////////
\t\t
\t\t //src_1 forward data from mem
\t\t //src_2 forward data from regread
\t\t
\t\t //case 1: mem_reg and wb_reg=rs and mem_regwrite and wb_regwrite=1 ;while we need to get latest value from mem, but simlation show taht
\t\t // forward from wb. 2+4=6
\t\t /////////////////////////////////////wrong,from wb instead of mem
\t\t id_ex_rs=1;
id_ex_rt=2;
id_ex_rd=3;
mem_regwrite=1\'b1;
wb_regwrite=1\'b1;
mem_regrd=1;
wb_regrd=1;
mem_reg_data=32\'h00000003;
\t\t wb_reg_data=32\'h00000004;
\t\t id_ex_sign_extend[5:0]=\t`add_funct;
\t\t aluop=4\'b0010;
\t\t alusrc=2\'b00;
\t\t #3;
\t\t $display("///add_funct, alu_result should be 32\'h00000005,actually is %h",alu_result);
\t\t $fdisplay(log_file,"///add_funct, alu_result should be 32\'h00000005,actually is %h",alu_result);
\t\t
\t\t `clk_step
\t\t //case 2: mem_reg =rs and mem_regwrite =1 ;while we need to get latest value from mem;
\t\t id_ex_rs=1;
id_ex_rt=2;
id_ex_rd=3;
mem_regwrite=1\'b1;
wb_regwrite=1\'b0;
mem_regrd=1;
wb_regrd=1;
mem_reg_data=32\'h00000003;
\t\t wb_reg_data=32\'h00000004;
\t\t id_ex_sign_extend[5:0]=\t`add_funct;
\t\t aluop=4\'b0010;
\t\t alusrc=2\'b00;
\t\t #3;
\t\t $display("///add_funct, alu_result should be 32\'h00000005,actually is %h",alu_result);
\t\t $fdisplay(log_file,"///add_funct, alu_result should be 32\'h00000005,actually is %h",alu_result);
\t\t
\t\t `clk_step
\t\t
\t\t //src_1 forward data from wb
\t\t //src_2 forward data from regread
\t\t //////////////////////////////////wrong, should from wb but seems from reg
\t\t //case 1: wb_reg=rs and wb_regwrite=1 ;while we need to get latest value from wb mem_rd != rs;
\t\t id_ex_rs=1;
id_ex_rt=2;
id_ex_rd=3;
mem_regwrite=1\'b1;
wb_regwrite=1\'b1;
mem_regrd=4;
wb_regrd=1;
mem_reg_data=32\'h00000003;
\t\t wb_reg_data=32\'h00000004;
\t\t id_ex_sign_extend[5:0]=\t`add_funct;
\t\t aluop=4\'b0010;
\t\t alusrc=2\'b00;
\t\t #3;
\t\t $display("///add_funct, alu_result should be 32\'h00000006,actually is %h",alu_result);
\t\t $fdisplay(log_file,"///add_funct, alu_result should be 32\'h00000006,actually is %h",alu_result);
\t\t`clk_step\t
\t\t
\t\t //src_1 forward data from regread because not matching
\t\t //src_2 forward data from regread because not matching
\t\t id_ex_rs=1;
id_ex_rt=2;
id_ex_rd=3;
mem_regwrite=1\'b1;
wb_regwrite=1\'b1;
mem_regrd=4;
wb_regrd=5;
mem_reg_data=32\'h00000003;
\t\t wb_reg_data=32\'h00000004;
\t\t id_ex_sign_extend[5:0]=\t`add_funct;
\t\t aluop=4\'b0010;
\t\t alusrc=2\'b00;
\t\t #3;
\t\t $display("///add_funct, alu_result should be 32\'h00000003,actually is %h",alu_result);
\t\t $fdisplay(log_file,"///add_funct, alu_result should be 32\'h00000003,actually is %h",alu_result);
\t\t
\t\t
\t\t `clk_step
\t\t
\t\t //src_1 forward data from regread
\t\t //src_2 forward data from regread
\t\t id_ex_rs=1;
id_ex_rt=2;
id_ex_rd=3;
mem_regwrite=1\'b1;
wb_regwrite=1\'b0;
mem_regrd=4;
wb_regrd=1;
mem_reg_data=32\'h00000003;
\t\t wb_reg_data=32\'h00000004;
\t\t id_ex_sign_extend[5:0]=\t`add_funct;
\t\t aluop=4\'b0010;
\t\t alusrc=2\'b00;
\t\t #3;
\t\t $display("///add_funct, alu_result should be 32\'h00000003,actually is %h",alu_result);
\t\t $fdisplay(log_file,"///add_funct, alu_result should be 32\'h00000003,actually is %h",alu_result);
\t\t
\t\t `clk_step
\t\t
\t\t //src_1 forward data from regread
\t\t //src_2 forward data from regread
\t\t id_ex_rs=1;
id_ex_rt=2;
id_ex_rd=3;
mem_regwrite=1\'b0;
wb_regwrite=1\'b1;
mem_regrd=4;
wb_regrd=3;
mem_reg_data=32\'h00000003;
\t\t wb_reg_data=32\'h00000004;
\t\t id_ex_sign_extend[5:0]=\t`add_funct;
\t\t aluop=4\'b0010;
\t\t alusrc=2\'b00;
\t\t #3;
\t\t $display("///add_funct, alu_result should be 32\'h00000003,actually is %h",alu_result);
\t\t $fdisplay(log_file,"///add_funct, alu_result should be 32\'h00000003,actually is %h",alu_result);
\t\t
\t\t `clk_step
\t\t
\t\t //src_1 forward data from regread
\t\t //src_2 forward data from mem
\t\t /////////////////////////////////wrong ,seems forward from wb instead of mem////////////////
\t\t id_ex_rs=1;
id_ex_rt=2;
id_ex_rd=3;
mem_regwrite=1\'b1;
wb_regwrite=1\'b1;
mem_regrd=2;
wb_regrd=2;
mem_reg_data=32\'h00000003;
\t\t wb_reg_data=32\'h00000004;
\t\t id_ex_sign_extend[5:0]=\t`add_funct;
\t\t aluop=4\'b0010;
\t\t alusrc=2\'b00;
\t\t #3;
\t\t $display("///add_funct, alu_result should be 32\'h00000004,actually is %h",alu_result);
\t\t $fdisplay(log_file,"///add_funct, alu_result should be 32\'h00000004,actually is %h",alu_result);
\t\t
\t\t `clk_step
\t\t
\t\t id_ex_rs=1;
id_ex_rt=2;
id_ex_rd=3;
mem_regwrite=1\'b1;
wb_regwrite=1\'b0;
mem_regrd=2;
wb_regrd=2;
mem_reg_data=32\'h00000003;
\t\t wb_reg_data=32\'h00000004;
\t\t id_ex_sign_extend[5:0]=\t`add_funct;
\t\t aluop=4\'b0010;
\t\t alusrc=2\'b00;
\t\t #3;
\t\t $display("///add_funct, alu_result should be 32\'h00000004,actually is %h",alu_result);
\t\t $fdisplay(log_file,"///add_funct, alu_result should be 32\'h00000004,actually is %h",alu_result);
\t\t
\t\t `clk_step
\t\t
\t\t //src_1 forward data from regread
\t\t //src_2 forward data from wb
\t\t ///////////////////////////////wrong, should from wb but seems from reg
\t\t id_ex_rs=1;
id_ex_rt=2;
id_ex_rd=3;
mem_regwrite=1\'b1;
wb_regwrite=1\'b1;
mem_regrd=23;
wb_regrd=2;
mem_reg_data=32\'h00000003;
\t\t wb_reg_data=32\'h00000004;
\t\t id_ex_sign_extend[5:0]=\t`add_funct;
\t\t aluop=4\'b0010;
\t\t alusrc=2\'b00;
\t\t #3;
\t\t $display("///add_funct, alu_result should be 32\'h00000005,actually is %h",alu_result);
\t\t $fdisplay(log_file,"///add_funct, alu_result should be 32\'h00000005,actually is %h",alu_result);
\t\t
\t\t `clk_step
\t\t
\t\t //src_1 forward data from mem
\t\t //src_2 forward data from wb
\t\t id_ex_rs=4;
id_ex_rt=6;
id_ex_rd=3;
mem_regwrite=1\'b1;
wb_regwrite=1\'b1;
mem_regrd=4;
wb_regrd=6;
mem_reg_data=32\'h00000003;
\t\t wb_reg_data=32\'h00000004;
\t\t id_ex_sign_extend[5:0]=\t`add_funct;
\t\t aluop=4\'b0010;
\t\t alusrc=2\'b00;
\t\t #3;
\t\t $display("///add_funct, alu_result should be 32\'h00000007,actually is %h",alu_result);
\t\t $fdisplay(log_file,"///add_funct, alu_result should be 32\'h00000007,actually is %h",alu_result);
\t\t
\t\t `clk_step
\t\t
\t\t //src_1 forward data from wb
\t\t //src_2 forward data from wb
\t\t ///////////////////////////////wrong, should from wb but seems from reg
\t\t id_ex_rs=6;
id_ex_rt=6;
id_ex_rd=3;
mem_regwrite=1\'b1;
wb_regwrite=1\'b1;
mem_regrd=4;
wb_regrd=6;
mem_reg_data=32\'h00000003;
\t\t wb_reg_data=32\'h00000004;
\t\t id_ex_sign_extend[5:0]=\t`add_funct;
\t\t aluop=4\'b0010;
\t\t alusrc=2\'b00;
\t\t #3;
\t\t $display("///add_funct, alu_result should be 32\'h00000008,actually is %h",alu_result);
\t\t $fdisplay(log_file,"///add_funct, alu_result should be 32\'h00000008,actually is %h",alu_result);
\t\t
\t\t `clk_step
\t\t
\t\t //src_1 forward data from mem
\t\t //src_2 forward data from mem
\t\t id_ex_rs=4;
id_ex_rt=4;
id_ex_rd=3;
mem_regwrite=1\'b1;
wb_regwrite=1\'b1;
mem_regrd=4;
wb_regrd=6;
mem_reg_data=32\'h00000003;
\t\t wb_reg_data=32\'h00000004;
\t\t id_ex_sign_extend[5:0]=\t`add_funct;
\t\t aluop=4\'b0010;
\t\t alusrc=2\'b00;
\t\t #3;
\t\t $display("///add_funct, alu_result should be 32\'h00000006,actually is %h",alu_result);
\t\t $fdisplay(log_file,"///add_funct, alu_result should be 32\'h00000006,actually is %h",alu_result);
\t\t
\t\t `clk_step
\t\t
\t\t
\t\t //////case 2: all kinds of aluops////////////////////////
\t\t //RESET
\t\t alusrc_a=32\'h00000001;
alusrc_b=32\'h00000002;
aluop=4\'b0000;
regdst=1\'b0;
alusrc=2\'b00;
id_ex_rs=1;
id_ex_rt=2;
id_ex_rd=3;
mem_regwrite=1\'b0;
wb_regwrite=1\'b0;
mem_regrd=4;
wb_regrd=5;
mem_reg_data=32\'h00000003;
\t\t wb_reg_data=32\'h00000004;
id_ex_sign_extend=32\'h00000005;
\t\t `clk_step
\t\t
\t\t //lw,sw,ll,sc,addiu,addi
\t\t aluop=4\'b0000;
\t\t alusrc=2\'b01;
\t\t #3;
\t\t $display("//lw,sw,ll,sc,addiu,addi; alu_result should be 32\'h00000006,actually is %h",alu_result);
\t\t $fdisplay(log_file,"//lw,sw,ll,sc,addiu,addi;alu_result should be 32\'h00000006,actually is %h",alu_result);
\t\t `clk_step
\t\t
\t\t //beq, bne, blez, bgtz ,bltz, bgez
\t\t //beq
\t\t aluop=4\'b0001;
\t\t alusrc=2\'b00;
\t\t #3;
\t\t $display("//beq zero should be 0,actually is %h",alu_result);
\t\t $fdisplay(log_file,"//beq zero should be 0,actually is %h",alu_result);
\t\t `clk_step
\t\t
\t\t //bne
\t\t aluop=4\'b0011;
\t\t alusrc=2\'b00;
\t\t #3;
\t\t $display("//bne zero should be 0,actually is %h",alu_result);
\t\t $fdisplay(log_file,"//bne zero should be 0,actually is %h",alu_result);
\t\t `clk_step
\t\t
\t\t //blez
\t\t aluop=4\'b0100;
\t\t alusrc=2\'b00;
\t\t #3;
\t\t $display("//blez here we don\'t care about alu_result should be ,actually is %h",alu_result);
\t\t $fdisplay(log_file,"//blez here we don\'t care about alu_result should be ,actually is %h",alu_result);
\t\t $display("alu_result should be ,actually is %h",alu_result);
\t\t $fdisplay(log_file,"alu_result should be ,actually is %h",alu_result);
\t\t `clk_step
\t\t
\t\t //bgtz
\t\t aluop=4\'b0101;
\t\t alusrc=2\'b00;
\t\t #3;
\t\t $display("//bgtz here we don\'t care about alu_result should be ,actually is %h",alu_result);
\t\t $fdisplay(log_file,"//bgtz here we don\'t care about alu_result should be ,actually is %h",alu_result);
\t\t `clk_step
\t\t
\t\t //bltz
\t\t aluop=4\'b0110;
\t\t alusrc=2\'b00;
\t\t #3;
\t\t $display("//bltz here we don\'t care about alu_result should be ,actually is %h",alu_result);
\t\t $fdisplay(log_file,"//bltz here we don\'t care about alu_result should be ,actually is %h",alu_result);
\t\t `clk_step
\t\t
\t\t //bgez
\t\t aluop=4\'b0111;
\t\t alusrc=2\'b00;
\t\t #3;
\t\t $display("//bgez here we don\'t care about alu_result should be ,actually is %h",alu_result);
\t\t $fdisplay(log_file,"//bgez here we don\'t care about alu_result should be ,actually is %h",alu_result);
\t\t `clk_step
\t\t
\t\t // R_type according to fun field
\t\t aluop=4\'b0010;
\t\t alusrc=2\'b00;
\t\t
\t\t ///add_funct,`addu_funct
\t\tid_ex_sign_extend[5:0]=\t`add_funct;
\t\t#3;
\t\t$display("///add_funct, alu_result should be 32\'h00000003,actually is %h",alu_result);
\t\t $fdisplay(log_file,"///add_funct, alu_result should be 32\'h00000003,actually is %h",alu_result);
\t\t`clk_step
\t\t
\t\tid_ex_sign_extend[5:0]=\t`addu_funct;
\t\t#3;
\t\t$display("`addu_funct alu_result should be 32\'h00000003,actually is %h",alu_result);
\t\t $fdisplay(log_file,"`addu_funct alu_result should be 32\'h00000003 ,actually is %h",alu_result);
\t\t`clk_step
\t\t\t
\t\t\t///sub_funct,`subu_funct
\t\tid_ex_sign_extend[5:0]=\t`sub_funct;
\t\t#3;
\t\t$display("`sub_funct; alu_result should be 32\'hffffffff,actually is %h",alu_result);
\t\t $fdisplay(log_file,"`sub_funct; alu_result should be 32\'hffffffff,actually is %h",alu_result);
\t\t`clk_step
\t\t
\t\tid_ex_sign_extend[5:0]=\t`subu_funct;
\t\t#3;
\t\t$display("`subu_funct; alu_result should be 32\'hffffffff,actually is %h",alu_result);
\t\t $fdisplay(log_file,"`subu_funct; alu_result should be 32\'hffffffff,actually is %h",alu_result);
\t\t`clk_step\t
\t\t\t
\t\t\t///and_funct
\t\tid_ex_sign_extend[5:0]=\t`and_funct;
\t\t#3;
\t\t$display("`and_funct; alu_result should be 32\'h00000000,actually is %h",alu_result);
\t\t $fdisplay(log_file,"`and_funct; alu_result should be 32\'h00000000,actually is %h",alu_result);
\t\t`clk_step\t
\t\t
\t\t\t///or_funct
\t\tid_ex_sign_extend[5:0]=\t`or_funct;
\t\t#3;
\t\t$display("`or_funct; alu_result should be 32\'h00000003,actually is %h",alu_result);
\t\t $fdisplay(log_file,"`or_funct; alu_result should be 32\'h00000003,actually is %h",alu_result);
\t\t`clk_step
\t\t
\t\t\t///slt_funct
\t\tid_ex_sign_extend[5:0]=\t`slt_funct;
\t\t#3;
\t\t$display("`slt_funct; alu_result should be 32\'h00000001,actually is %h",alu_result);
\t\t $fdisplay(log_file,"`slt_funct; alu_result should be 32\'h00000001,actually is %h",alu_result);
\t\t`clk_step\t
\t\t\t
\t\tid_ex_sign_extend[5:0]=\t`sltu_funct;
\t\t#3;
\t\t$display("`sltu_funct; alu_result should be 32\'h00000001,actually is %h",alu_result);
\t\t $fdisplay(log_file,"`sltu_funct; alu_result should be 32\'h00000001,actually is %h",alu_result);
\t\t`clk_step
\t\t
\t\t\t///sll_funct
\t\tid_ex_sign_extend[5:0]=\t`sll_funct;
\t\tid_ex_sign_extend[10:6]=5\'b00011;
\t\t#3;
\t\t$display("`sll_funct; alu_result should be 32\'h00000010,actually is %h",alu_result);
\t\t $fdisplay(log_file,"`sll_funct; alu_result should be 32\'h00000010,actually is %h",alu_result);
\t\t`clk_step\t
\t\t\t
\t\t\t///srl_funct
\t\tid_ex_sign_extend[5:0]=\t`srl_funct;
\t\tid_ex_sign_extend[10:6]=5\'b00011;
\t\talusrc_b=32\'h000000f0;
\t\t#3;
\t\t$display("`srl_funct; alu_result should be 32\'h0000001e;,actually is %h",alu_result);
\t\t $fdisplay(log_file,"`srl_funct; alu_result should be 32\'h0000001e;,actually is %h",alu_result);
\t\t`clk_step\t
\t\t\t
\t\t\t///sra_funct
\t\tid_ex_sign_extend[5:0]=\t`sra_funct;
\t\tid_ex_sign_extend[10:6]=5\'b00011;
\t\talusrc_b=32\'h800000f0;
\t\t#3;
\t\t$display("`sra_funct; alu_result should be 32\'h1000001e,actually is %h",alu_result);
\t\t $fdisplay(log_file,"`sra_funct; alu_result should be 32\'h1000001e,actually is %h",alu_result);
\t\t`clk_step\t
\t\t\t
\t\t\t///sllv_funct
\t\tid_ex_sign_extend[5:0]=\t`sllv_funct;
\t\talusrc_a=32\'h00000003;
\t\talusrc_b=32\'h00000ff0;
\t\t#3;
\t\t$display("\t`sllv_funct; alu_result should be 32\'h00007f80,actually is %h",alu_result);
\t\t $fdisplay(log_file,"\t`sllv_funct; alu_result should be 32\'h00007f80,actually is %h",alu_result);
\t\t`clk_step\t
\t\t\t
\t\t\t///srlv_funct
\t\tid_ex_sign_extend[5:0]=\t`srlv_funct;
\t\t#3;
\t\t$display("\t`srlv_funct; alu_result should be 32\'h000001fe,actually is %h",alu_result);
\t\t $fdisplay(log_file,"\t`srlv_funct; alu_result should be 32\'h000001fe,actually is %h",alu_result);
\t\t`clk_step\t
\t\t\t
\t\t\t///srav_funct
\t\tid_ex_sign_extend[5:0]=\t`srav_funct;
\t\talusrc_a=32\'h00000004;
\t\talusrc_b=32\'h80000ff0;
\t\t#3;
\t\t$display("`srav_funct; alu_result should be 32\'h080000ff;,actually is %h",alu_result);
\t\t $fdisplay(log_file,"`srav_funct; alu_result should be 32\'h080000ff;,actually is %h",alu_result);
\t\t`clk_step\t
\t\t\t
\t\t\t///xor_funct
\t\t\talusrc_a=32\'h00000001;
alusrc_b=32\'h00000002;
\t\tid_ex_sign_extend[5:0]=\t`xor_funct;
\t\t#3;
\t\t$display("`xor_funct; alu_result should be 32\'h00000003,actually is %h",alu_result);
\t\t $fdisplay(log_file,"`xor_funct; alu_result should be 32\'h00000003,actually is %h",alu_result);
\t\t`clk_step\t
\t\t\t
\t\t\t///nor_funct
\t\tid_ex_sign_extend[5:0]=\t`nor_funct;
\t\t#3;
\t\t$display("`nor_funct; alu_result should be 32\'hfffffffc,actually is %h",alu_result);
\t\t $fdisplay(log_file,"`nor_funct; alu_result should be 32\'hfffffffc,actually is %h",alu_result);
\t\t`clk_step\t
\t\t\t
\t\t //slt_op
\t\tid_ex_sign_extend=32\'h00000005;
\t\t
\t\taluop=4\'b1010;
\t\talusrc=2\'b01;
\t\t#3;
\t\t$display(" //slt_op alu_result should be 32\'h00000001,actually is %h",alu_result);
\t\t $fdisplay(log_file," //slt_op alu_result should be 32\'h00000001,actually is %h",alu_result);
\t\t`clk_step
\t\t
\t\t //andi
\t\taluop=4\'b1011;
\t\talusrc=2\'b10;
\t\t#3;
\t\t$display("//andi alu_result should be 32\'h00000001,actually is %h",alu_result);
\t\t $fdisplay(log_file,"//andi alu_result should be 32\'h00000001,actually is %h",alu_result);
\t\t`clk_step
\t\t
\t\t //ori
\t\taluop=4\'b1100;
\t\talusrc=2\'b10;
\t\t#3;
\t\t$display("//ori alu_result should be 32\'h00000005,actually is %h",alu_result);
\t\t $fdisplay(log_file,"//ori alu_result should be 32\'h00000005,actually is %h",alu_result);
\t\t`clk_step
\t\t
\t\t //xori
\t\taluop=4\'b1101;
\t\talusrc=2\'b10;
\t\t#3;
\t\t$display("//xori alu_result should be 32\'h00000004,actually is %h",alu_result);
\t\t $fdisplay(log_file,"//xori alu_result should be 32\'h00000004,actually is %h",alu_result);
\t\t`clk_step
\t\t
\t\t //lui
\t\taluop=4\'b1110;
\t\talusrc=2\'b01;
\t\t#3;
\t\t$display("//lui alu_result should be 32\'h00050000; actually is %h",alu_result);
\t\t $fdisplay(log_file,"//lui alu_result should be 32\'h00050000; actually is %h",alu_result);
\t\t`clk_step
\t\t
\t\t$stop;
\t\tend
\t\tendmodule
\t\t
\t\t
|
/**********************************************************************
date:2016/3/26
designer:ZhaiShaoMin
project:ring network multicore
module name:tb_arbiter_OUT_rep
module function: figure out what\'s wrong with it
***********************************************************************/
`timescale 1ns/1ps
module tb_arbiter_for_OUT_rep();
//inputs
reg clk;
reg rst;
reg OUT_rep_rdy;
reg v_dc_rep;
reg v_mem_rep;
reg [15:0] dc_rep_flit;
reg [15:0] mem_rep_flit;
reg [1:0] dc_rep_ctrl;
reg [1:0] mem_rep_ctrl;
//output
wire ack_OUT_rep;
wire ack_dc_rep;
wire ack_mem_rep;
wire [1:0] select; // select 1/2
parameter SCflurep_cmd=5\'b11100;
parameter nackrep_cmd=5\'b10101;
//instante design
arbiter_for_OUT_rep uut (//input
.clk(clk),
.rst(rst),
.OUT_rep_rdy(OUT_rep_rdy),
.v_dc_rep(v_dc_rep),
.v_mem_rep(v_mem_rep),
.dc_rep_flit(dc_rep_flit),
.mem_rep_flit(mem_rep_flit),
.dc_rep_ctrl(dc_rep_ctrl),
.mem_rep_ctrl(mem_rep_ctrl),
//output
.ack_OUT_rep(ack_OUT_rep),
.ack_dc_rep(ack_dc_rep),
.ack_mem_rep(ack_mem_rep),
.select(select) // select 1/2
);
integer log_file;
//define task for cmp actual outputs and exp outputs
task cmp_outputs;
input exp_ack_OUT_rep;
input exp_ack_dc_rep;
input exp_ack_mem_rep;
input [1:0]exp_select;
begin
$display("Time:%t",$time);
$fdisplay (log_file, "Time: %t", $time);
if (ack_OUT_rep != exp_ack_OUT_rep)
begin
$display("ERROR: Invalid ack_OUT_rep\
\\t Expected: 0x%x \
\\t Acutal: 0x%x", exp_ack_OUT_rep,ack_OUT_rep);
$fdisplay(log_file,"ERROR: Invalid ack_OUT_rep\
\\t Expected: 0x%x \
\\t Acutal: 0x%x", exp_ack_OUT_rep,ack_OUT_rep);
end
if (ack_dc_rep != exp_ack_dc_rep)
begin
$display("ERROR: Invalid ack_dc_rep\
\\t Expected: 0x%x \
\\t Acutal: 0x%x", exp_ack_dc_rep,ack_dc_rep);
$fdisplay(log_file,"ERROR: Invalid ack_dc_rep\
\\t Expected: 0x%x \
\\t Acutal: 0x%x", exp_ack_dc_rep,ack_dc_rep);
end
if (ack_mem_rep != exp_ack_mem_rep)
begin
$display("ERROR: Invalid ack_mem_rep\
\\t Expected: 0x%x \
\\t Acutal: 0x%x", exp_ack_mem_rep,ack_mem_rep);
$fdisplay(log_file,"ERROR: Invalid ack_mem_rep\
\\t Expected: 0x%x \
\\t Acutal: 0x%x", exp_ack_mem_rep,ack_mem_rep);
end
if (select != exp_select)
begin
$display("ERROR: Invalid select\
\\t Expected: 0x%x \
\\t Acutal: 0x%x", exp_select,select);
$fdisplay(log_file,"ERROR: Invalid select\
\\t Expected: 0x%x \
\\t Acutal: 0x%x", exp_select,select);
end
if((ack_OUT_rep == exp_ack_OUT_rep)&&
(ack_dc_rep == exp_ack_dc_rep)&&
(ack_mem_rep == exp_ack_mem_rep)&&
(select == exp_select))
begin
$display("passed,test");
$fdisplay(log_file,"passed,test");
end
end
endtask
//initial inputs
initial begin
clk=1\'b0;
rst=1\'b1;
OUT_rep_rdy=1\'b0;
v_dc_rep=1\'b0;
v_mem_rep=1\'b0;
dc_rep_flit=16\'h0000;
mem_rep_flit=16\'h0000;
dc_rep_ctrl=2\'b00;
mem_rep_ctrl=2\'b00;
log_file=$fopen("log_arbiter_for_OUT_rep.txt");
end
`define clk_step #14;
always #7 clk=~clk;
initial begin
// actural test arbiter_for_OUT_rep TEST//
`clk_step
$display("TEST BEGIN.......");
$fdisplay(log_file,"TEST BEGIN.......");
rst=1\'b0;
`clk_step
////////////////////////////////////////////////////
//First case both v_dc_rep and v_mem_rep are valid//
$display("First case both v_dc_rep and v_mem_rep are valid");
$fdisplay(log_file,"First case both v_dc_rep and v_mem_rep are valid");
$display("First try");
$fdisplay(log_file,"First try");
//it also means that both flits are head flit
OUT_rep_rdy=1\'b0;//don\'t care
v_dc_rep=1\'b1;
v_mem_rep=1\'b1;
dc_rep_flit=16\'habcd;
mem_rep_flit=16\'h1234;
dc_rep_ctrl=2\'b01;
mem_rep_ctrl=2\'b01;
cmp_outputs(1\'b0,//ack_OUT_rep//
1\'b0,//ack_dc_rep//
1\'b0,//ack_mem_rep//
2\'b00//select//
);
`clk_step
$display("2nd try ");
$fdisplay(log_file,"2nd try");
//it also means that both flits are head flit
OUT_rep_rdy=1\'b1;
v_dc_rep=1\'b1;
v_mem_rep=1\'b1;
dc_rep_flit=16\'habcd;
mem_rep_flit=16\'h1234;
dc_rep_ctrl=2\'b01;
mem_rep_ctrl=2\'b01;
cmp_outputs(1\'b1,//ack_OUT_rep//
1\'b0,//ack_dc_rep//
1\'b1,//ack_mem_rep//
2\'b10//select//
);
`clk_step
$display("3rd try ");
$fdisplay(log_file,"3rd try");
//it also means that both flits are head flit
OUT_rep_rdy=1\'b1;
v_dc_rep=1\'b1;
v_mem_rep=1\'b1;
dc_rep_flit=16\'habcd;
mem_rep_flit=16\'h5678;
dc_rep_ctrl=2\'b01;
mem_rep_ctrl=2\'b10;
cmp_outputs(1\'b1,//ack_OUT_rep//
1\'b0,//ack_dc_rep//
1\'b1,//ack_mem_rep//
2\'b10//select//
);
`clk_step
$display("4th try ");
$fdisplay(log_file,"4th try");
//it also means that both flits are head flit
OUT_rep_rdy=1\'b1;
v_dc_rep=1\'b1;
v_mem_rep=1\'b1;
dc_rep_flit=16\'habcd;
mem_rep_flit=16\'h2016;
dc_rep_ctrl=2\'b01;
mem_rep_ctrl=2\'b10;
cmp_outputs(1\'b1,//ack_OUT_rep//
1\'b0,//ack_dc_rep//
1\'b1,//ack_mem_rep//
2\'b10//select//
);
/*.....*/
//assuming iit\'s time for tail flit of mem msg
`clk_step
$display("3rd try ");
$fdisplay(log_file,"3rd try");
//it also means that both flits are head flit
OUT_rep_rdy=1\'b1;
v_dc_rep=1\'b1;
v_mem_rep=1\'b1;
dc_rep_flit=16\'habcd;
mem_rep_flit=16\'h5678;
dc_rep_ctrl=2\'b01;
mem_rep_ctrl=2\'b11;
cmp_outputs(1\'b1,//ack_OUT_rep//
1\'b0,//ack_dc_rep//
1\'b1,//ack_mem_rep//
2\'b10//select//
);
`clk_step
//////////////////////////////////////////////////
//2nd case both v_dc_rep and v_mem_rep are valid
$display("2nd case both v_dc_rep and v_mem_rep are valid ,but it\'s tme for dc");
$fdisplay(log_file,"2nd case both v_dc_rep and v_mem_rep are valid,but it\'s tme for dc");
$display("First try");
$fdisplay(log_file,"First try");
//it also means that both flits are head flit
OUT_rep_rdy=1\'b0;//don\'t care
v_dc_rep=1\'b1;
v_mem_rep=1\'b1;
dc_rep_flit=16\'habcd;
mem_rep_flit=16\'h1234;
dc_rep_ctrl=2\'b01;
mem_rep_ctrl=2\'b01;
cmp_outputs(1\'b0,//ack_OUT_rep//
1\'b0,//ack_dc_rep//
1\'b0,//ack_mem_rep//
2\'b00//select//
);
`clk_step
$display("2nd try ");
$fdisplay(log_file,"2nd try");
//it also means that both flits are head flit
OUT_rep_rdy=1\'b1;
v_dc_rep=1\'b1;
v_mem_rep=1\'b1;
dc_rep_flit=16\'habcd;
mem_rep_flit=16\'h1234;
dc_rep_ctrl=2\'b01;
mem_rep_ctrl=2\'b01;
cmp_outputs(1\'b1,//ack_OUT_rep//
1\'b1,//ack_dc_rep//
1\'b0,//ack_mem_rep//
2\'b01//select//
);
`clk_step
$display("3rd try ");
$fdisplay(log_file,"3rd try");
//it also means that both flits are head flit
OUT_rep_rdy=1\'b1;
v_dc_rep=1\'b1;
v_mem_rep=1\'b1;
dc_rep_flit=16\'h5678;
mem_rep_flit=16\'h5678;
dc_rep_ctrl=2\'b10;
mem_rep_ctrl=2\'b01;
cmp_outputs(1\'b1,//ack_OUT_rep//
1\'b0,//ack_dc_rep//
1\'b1,//ack_mem_rep//
2\'b01//select//
);
`clk_step
$display("4th try ");
$fdisplay(log_file,"4th try");
//it also means that both flits are head flit
OUT_rep_rdy=1\'b1;
v_dc_rep=1\'b1;
v_mem_rep=1\'b1;
dc_rep_flit=16\'habcd;
mem_rep_flit=16\'h2016;
dc_rep_ctrl=2\'b10;
mem_rep_ctrl=2\'b01;
cmp_outputs(1\'b1,//ack_OUT_rep//
1\'b1,//ack_dc_rep//
1\'b0,//ack_mem_rep//
2\'b01//select//
);
/*.....*/
//assuming iit\'s time for tail flit of mem msg
`clk_step
$display("3rd try ");
$fdisplay(log_file,"3rd try");
//it also means that both flits are head flit
OUT_rep_rdy=1\'b1;
v_dc_rep=1\'b1;
v_mem_rep=1\'b1;
dc_rep_flit=16\'h2016;
mem_rep_flit=16\'h5678;
dc_rep_ctrl=2\'b11;
mem_rep_ctrl=2\'b01;
cmp_outputs(1\'b1,//ack_OUT_rep//
1\'b1,//ack_dc_rep//
1\'b0,//ack_mem_rep//
2\'b01//select//
);
`clk_step
////////////////////////////////////////////////
/// 3rd case only v_dc_rep is valid
$display("3rd case only v_dc_rep is valid");
$fdisplay(log_file,"3rd case only v_dc_rep is valid");
$display("First try");
$fdisplay(log_file,"First try");
//it also means that both flits are head flit
OUT_rep_rdy=1\'b0;//don\'t care
v_dc_rep=1\'b1;
v_mem_rep=1\'b0;
dc_rep_flit=16\'h2016;
mem_rep_flit=16\'h1234;
dc_rep_ctrl=2\'b01;
mem_rep_ctrl=2\'b00;
cmp_outputs(1\'b0,//ack_OUT_rep//
1\'b0,//ack_dc_rep//
1\'b0,//ack_mem_rep//
2\'b00//select//
);
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
//it also means that both flits are head flit
OUT_rep_rdy=1\'b1;
v_dc_rep=1\'b1;
v_mem_rep=1\'b0;
// make it scflushrep which is only one flit long to test another path
//no need to gen it ,because it imposible for dc
dc_rep_flit=16\'h2016;
mem_rep_flit=16\'h1234;
dc_rep_ctrl=2\'b01;
mem_rep_ctrl=2\'b00;
cmp_outputs(1\'b1,//ack_OUT_rep//
1\'b1,//ack_dc_rep//
1\'b0,//ack_mem_rep//
2\'b01//select//
);
/*.....*/
//let\'s assum that there will be the tail flit of dc msg
`clk_step
$display("last try");
$fdisplay(log_file,"last try");
//it also means that both flits are head flit
OUT_rep_rdy=1\'b1;
v_dc_rep=1\'b1;
v_mem_rep=1\'b0;
dc_rep_flit=16\'h2016;
mem_rep_flit=16\'h1234;
dc_rep_ctrl=2\'b11;
mem_rep_ctrl=2\'b00;
cmp_outputs(1\'b1,//ack_OUT_rep//
1\'b1,//ack_dc_rep//
1\'b0,//ack_mem_rep//
2\'b01//select//
);
/* //just test whether state jump to idle
`clk_step
$display("last try");
$fdisplay(log_file,"last try");
//it also means that both flits are head flit
OUT_rep_rdy=1\'b1;
v_dc_rep=1\'b1;
v_mem_rep=1\'b0;
dc_rep_flit=16\'h2016;
mem_rep_flit=16\'h1234;
dc_rep_ctrl=2\'b01;
mem_rep_ctrl=2\'b00;
cmp_outputs(1\'b0,//ack_OUT_rep//
1\'b0,//ack_dc_rep//
1\'b0,//ack_mem_rep//
2\'b00//select//
);
*/
/////////////////////////////////////////////
///4th case only v_mem_rep is valid
`clk_step
$display("3rd case only v_mem_rep is valid");
$fdisplay(log_file,"3rd case only v_mem_rep is valid");
$display("First try");
$fdisplay(log_file,"First try");
//it also means that both flits are head flit
OUT_rep_rdy=1\'b1;//don\'t care
v_dc_rep=1\'b0;
v_mem_rep=1\'b1;
dc_rep_flit=16\'h2016;
mem_rep_flit=16\'h1234;
dc_rep_ctrl=2\'b01;
mem_rep_ctrl=2\'b01;
cmp_outputs(1\'b0,//ack_OUT_rep//
1\'b0,//ack_dc_rep//
1\'b0,//ack_mem_rep//
2\'b00//select//
);
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
//it also means that both flits are head flit
OUT_rep_rdy=1\'b1;
v_dc_rep=1\'b0;
v_mem_rep=1\'b1;
dc_rep_flit=16\'h2016;
mem_rep_flit=16\'h1234;
dc_rep_ctrl=2\'b01;
mem_rep_ctrl=2\'b01;
cmp_outputs(1\'b1,//ack_OUT_rep//
1\'b0,//ack_dc_rep//
1\'b1,//ack_mem_rep//
2\'b10//select//
);
`clk_step
$display("3rd try");
$fdisplay(log_file,"3rd try");
//it also means that both flits are head flit
OUT_rep_rdy=1\'b1;
v_dc_rep=1\'b0;
v_mem_rep=1\'b1;
dc_rep_flit=16\'h0328;
mem_rep_flit=16\'h1234;
dc_rep_ctrl=2\'b01;
mem_rep_ctrl=2\'b10;
cmp_outputs(1\'b1,//ack_OUT_rep//
1\'b0,//ack_dc_rep//
1\'b1,//ack_mem_rep//
2\'b10//select//
);
`clk_step
$display("last try");
$fdisplay(log_file,"last try");
//it also means that both flits are head flit
OUT_rep_rdy=1\'b1;
v_dc_rep=1\'b0;
v_mem_rep=1\'b1;
dc_rep_flit=16\'hc0de;
mem_rep_flit=16\'h1234;
dc_rep_ctrl=2\'b01;
mem_rep_ctrl=2\'b11;
cmp_outputs(1\'b1,//ack_OUT_rep//
1\'b0,//ack_dc_rep//
1\'b1,//ack_mem_rep//
2\'b10//select//
);
/* `clk_step
$display("last try,just a test for whether jump to idle");
$fdisplay(log_file,"last try,just a test for whether jump to idle");
//it also means that both flits are head flit
OUT_rep_rdy=1\'b1;
v_dc_rep=1\'b0;
v_mem_rep=1\'b1;
dc_rep_flit=16\'hc0de;
mem_rep_flit=16\'h1234;
dc_rep_ctrl=2\'b01;
mem_rep_ctrl=2\'b11;
cmp_outputs(1\'b1,//ack_OUT_rep//
1\'b0,//ack_dc_rep//
1\'b1,//ack_mem_rep//
2\'b10//select//
);
*/
/////////////////////////////////////////////
///5th case only v_mem_rep is valid and is SCflushrep
`clk_step
$display("5th case :only v_mem_rep is valid");
$fdisplay(log_file,"5th case :only v_mem_rep is valid");
$display("First try");
$fdisplay(log_file,"First try");
//it also means that both flits are head flit
OUT_rep_rdy=1\'b1;//don\'t care
v_dc_rep=1\'b0;
v_mem_rep=1\'b1;
dc_rep_flit=16\'h2016;
mem_rep_flit={6\'b110110,SCflurep_cmd,5\'b00000};
dc_rep_ctrl=2\'b01;
mem_rep_ctrl=2\'b01;
cmp_outputs(1\'b0,//ack_OUT_rep//
1\'b0,//ack_dc_rep//
1\'b0,//ack_mem_rep//
2\'b00//select//
);
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
//it also means that both flits are head flit
OUT_rep_rdy=1\'b1;
v_dc_rep=1\'b0;
v_mem_rep=1\'b1;
dc_rep_flit=16\'h2016;
mem_rep_flit={6\'b110110,SCflurep_cmd,5\'b00000};
dc_rep_ctrl=2\'b01;
mem_rep_ctrl=2\'b01;
cmp_outputs(1\'b1,//ack_OUT_rep//
1\'b0,//ack_dc_rep//
1\'b1,//ack_mem_rep//
2\'b10//select//
);
/* `clk_step
$display("last try,just a test for whether jump to idle");
$fdisplay(log_file,"last try,just a test for whether jump to idle");
//it also means that both flits are head flit
OUT_rep_rdy=1\'b1;
v_dc_rep=1\'b0;
v_mem_rep=1\'b1;
dc_rep_flit=16\'h2016;
mem_rep_flit={6\'b110110,SCflurep_cmd,5\'b00000};
dc_rep_ctrl=2\'b01;
mem_rep_ctrl=2\'b01;
cmp_outputs(1\'b1,//ack_OUT_rep//
1\'b0,//ack_dc_rep//
1\'b1,//ack_mem_rep//
2\'b10//select//
);
*/
/////////////////////////////////////////////
///6th case only v_mem_rep is valid and is nackrep
`clk_step
//nackrep_msg for test
$display("6th case :only v_mem_rep is valid");
$fdisplay(log_file,"6th case :only v_mem_rep is valid");
$display("First try");
$fdisplay(log_file,"First try");
//it also means that both flits are head flit
OUT_rep_rdy=1\'b1;//don\'t care
v_dc_rep=1\'b0;
v_mem_rep=1\'b1;
dc_rep_flit=16\'h2016;
mem_rep_flit={6\'b110110,nackrep_cmd,5\'b00000};
dc_rep_ctrl=2\'b01;
mem_rep_ctrl=2\'b01;
cmp_outputs(1\'b0,//ack_OUT_rep//
1\'b0,//ack_dc_rep//
1\'b0,//ack_mem_rep//
2\'b00//select//
);
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
//it also means that both flits are head flit
OUT_rep_rdy=1\'b1;
v_dc_rep=1\'b0;
v_mem_rep=1\'b1;
dc_rep_flit=16\'h2016;
mem_rep_flit={6\'b110110,nackrep_cmd,5\'b00000};
dc_rep_ctrl=2\'b01;
mem_rep_ctrl=2\'b01;
cmp_outputs(1\'b1,//ack_OUT_rep//
1\'b0,//ack_dc_rep//
1\'b1,//ack_mem_rep//
2\'b10//select//
);
/* `clk_step
$display("last try,just a test for whether jump to idle");
$fdisplay(log_file,"last try,just a test for whether jump to idle");
//it also means that both flits are head flit
OUT_rep_rdy=1\'b1;
v_dc_rep=1\'b0;
v_mem_rep=1\'b1;
dc_rep_flit=16\'h2016;
mem_rep_flit={6\'b110110,nackrep_cmd,5\'b00000};
dc_rep_ctrl=2\'b01;
mem_rep_ctrl=2\'b01;
cmp_outputs(1\'b1,//ack_OUT_rep//
1\'b0,//ack_dc_rep//
1\'b1,//ack_mem_rep//
2\'b10//select//
);
*/
`clk_step
$display("FINISH TEST!");
$fdisplay(log_file,"FINISH TEST!");
$stop;
end
endmodule
|
///2016/8/6
///ShaoMin Zhai
///module function : used to test core pipeline
`timescale 1ns/1ps
module tb_toplevel();
reg clk;
reg rst;
top_level duv (
.clk(clk),
.rst(rst)
);
always #5 clk=~clk;
`define clk_step #8;
initial begin
rst=1'b1;
clk=1'b0;
// forever #5 clk=~clk;
`clk_step
rst=1'b0;
#500;
repeat(20)
begin
#2;
`clk_step
end
$stop;
end
endmodule
|
//date:2016/3/20
//engineer:ZhaiShaoMin
//module name: PHT :Pattern History Table
module core_pht(//input
clk,
rst,
if_pc, // pc[10:5]
id_pc, // pc[10:5]
update_BP,
pred_right,
taken,
BHR_in,
//delayed PHT_out from previous stage , useful to avoid reading PHT when update PHT
delayed_PHT,
//output
pred_out,
BHR_rd,
PHT_out
);
//input
input clk;
input rst;
input update_BP;
input pred_right;
input taken;
input [5:0] if_pc; //part of pc
input [5:0] id_pc; // part of pc
input [3:0] BHR_in;
input [1:0] delayed_PHT;
//output
output pred_out;
output [3:0] BHR_rd;
output [1:0] PHT_out;
wire [1:0] PHT_out;
wire [3:0] BHR_rd;
reg en_update_PHT;
reg [1:0] PHT_in;
//reg of BHT
reg [3:0] BHT [7:0];
reg [1:0] PHT [127:0];
//index for update PHT
wire [6:0] index_PHT_id;
//index for look PHT
wire [6:0] index_PHT_if;
assign index_PHT_if={BHR_rd,if_pc[4:2]};
assign index_PHT_id={BHR_in,id_pc[4:2]};
//index for look BHT
wire [2:0] index_BHT_if;
wire [2:0] index_BHT_id;
//hash process for short index!
assign index_BHT_if={if_pc[5]^if_pc[4],if_pc[3]^if_pc[2],if_pc[1]^if_pc[0]};
assign index_BHT_id={id_pc[5]^id_pc[4],id_pc[3]^id_pc[2],id_pc[1]^id_pc[0]};
// update BHT
always@(posedge clk)
begin
// if(rst)
// begin :resetBHT
// integer i;
// for(i=0;i<8;i=i+1)
// begin
// BHT[index_BHT_id]<=4'b0000;
// end
// end
// else
if(update_BP)
begin
if(taken)
BHT[index_BHT_id]<={BHR_in[2:0],1'b1};
else
BHT[index_BHT_id]<={BHR_in[2:0],1'b1};
end
end
//update PHT
always@(posedge clk)
begin
// if(rst)
// begin:resetPHT
// integer j;
// for(j=0;j<128;j=j+1)
// begin
// PHT[index_PHT_id]<=2'b00;
// end
//end
//else
if(en_update_PHT)
begin
PHT[index_PHT_id]<=PHT_in;
end
end
// figure out whether updating PHT or not
always@(*)
begin
en_update_PHT=1'b0;
PHT_in=2'b00;
if(update_BP)
begin
if(delayed_PHT[1]&&pred_right)
begin
if(delayed_PHT[0]==1'b0)
begin
en_update_PHT=1'b1;
PHT_in=2'b11;
end
end
else if((!delayed_PHT[1])&&pred_right)
begin
en_update_PHT=1'b1;
PHT_in=2'b10;
end
else if(delayed_PHT[1]&&(!pred_right))
begin
en_update_PHT=1'b1;
PHT_in=2'b01;
end
else if((!delayed_PHT[1])&&(!pred_right))
begin
en_update_PHT=1'b1;
PHT_in=2'b00;
end
end
end
//read BHT
assign BHR_rd=BHT[index_BHT_if];
//read PHT
assign PHT_out=PHT[index_PHT_if];
assign pred_out=PHT_out[1];
endmodule
|
//date:2016/3/13
//engineer:ZhaiShaoMin
//module name:pipeline registers between ex and mem
module core_ex_mem(//input
clk,
rst,
branch,
mem_read,
mem_write,
ll_mem,
sc_mem,
reg_write,
memtoreg,
alu_zero,
alu_result,
reg_read2,
dest_reg,
//output
mem_branch,
mem_mem_read,
mem_mem_write,
mem_ll_mem,
mem_sc_mem,
mem_reg_write,
mem_memtoreg,
mem_alu_zero,
mem_alu_result,
mem_reg_read2,
mem_dest_reg
);
//input
input clk;
input rst;
input branch;
input mem_read;
input mem_write;
input ll_mem;
input sc_mem;
input reg_write;
input memtoreg;
input alu_zero;
input [31:0] alu_result;
input [31:0] reg_read2;
input [4:0] dest_reg;
//output
output mem_branch;
output mem_mem_read;
output mem_mem_write;
output mem_ll_mem;
output mem_sc_mem;
output mem_reg_write;
output mem_memtoreg;
output mem_alu_zero;
output [31:0] mem_alu_result;
output [31:0] mem_reg_read2;
output [4:0] mem_dest_reg;
///regs
reg mem_branch;
reg mem_mem_read;
reg mem_mem_write;
reg mem_ll_mem;
reg mem_sc_mem;
reg mem_reg_write;
reg mem_memtoreg;
reg mem_alu_zero;
reg [31:0] mem_alu_result;
reg [31:0] mem_reg_read2;
reg [4:0] mem_dest_reg;
always@(posedge clk)
begin
if(rst)
begin
mem_branch<=1'b0;
mem_mem_read<=1'b0;
mem_mem_write<=1'b0;
mem_ll_mem<=1'b0;
mem_sc_mem<=1'b0;
mem_reg_write<=1'b0;
mem_memtoreg<=1'b0;
mem_alu_zero<=1'b0;
mem_alu_result<=32'h0000;
mem_reg_read2<=32'h0000;
mem_dest_reg<=5'b00000;
end
else
begin
mem_branch<=branch;
mem_mem_read<=mem_read;
mem_mem_write<=mem_write;
mem_ll_mem<=ll_mem;
mem_sc_mem<=sc_mem;
mem_reg_write<=reg_write;
mem_memtoreg<=memtoreg;
mem_alu_zero<=alu_zero;
mem_alu_result<=alu_result;
mem_reg_read2<=reg_read2;
mem_dest_reg<=dest_reg;
end
end
endmodule
|
/// date: 2016/2/24
/// engineer: ZhaiShaoMIn
/// module name: fsm_download_flit(from IN_local fifos)
/// fsm for controlling datapath from IN_local to the regs
/// used to process rep msgs and req msgs.
module FSM_download_flit(
//input
req_flit,
req_rdy,
rep_flit,
rep_rdy,
clk,
rst,
cache_rst,
//output
en_deq_req,
en_deq_rep,
rf_rdy_for_cache_out,
head_flit,
addrHI_flit,
addrLO_flit,
data1HI_flit,
data1LO_flit,
data2HI_flit,
data2LO_flit,
data3HI_flit,
data3LO_flit,
data4HI_flit,
data4LO_flit
);
//input
input [17:0] req_flit; // with ctrl (2 bits)
input req_rdy;
input [17:0] rep_flit; // with ctrl (2 bits)
input rep_rdy;
input clk;
input rst;
input cache_rst;
//output
output en_deq_req;
output en_deq_rep;
output rf_rdy_for_cache_out;
output [15:0] head_flit;
output [15:0] addrHI_flit;
output [15:0] addrLO_flit;
output [15:0] data1HI_flit;
output [15:0] data1LO_flit;
output [15:0] data2HI_flit;
output [15:0] data2LO_flit;
output [15:0] data3HI_flit;
output [15:0] data3LO_flit;
output [15:0] data4HI_flit;
output [15:0] data4LO_flit;
//wires for interconnection
wire [1:0] ctrl_rep;
wire [1:0] ctrl_req;
assign ctrl_rep=rep_flit[17:16];
assign ctrl_req=req_flit[17:16];
//arbitration
wire tCbusy;
wire req_cacheORhome;
wire rep_cacheORhome;
assign req_cacheORhome=req_flit[13];
assign rep_cacheORhome=rep_flit[13];
//fake regs
reg deq_rep_on;
reg deq_req_on;
always@(tCbusy or rep_rdy or req_rdy or req_cacheORhome or rep_cacheORhome or ctrl)
begin
if(~tCbusy&&rep_rdy&&~rep_cacheORhome&&(ctrl_rep==2'b01))
begin
deq_rep_on=1;
deq_req_on=0;
end
else if(~tCbusy&&req_rdy&&~req_cacheORhome&&(ctrl_req==2'b01))
begin
deq_rep_on=0;
deq_req_on=1;
end
else
begin
deq_rep_on=0;
deq_req_on=0;
end
//defult: signals
deq_req_on=0;
deq_rep_on=0;
end
//parameters
parameter idle=3'b000;
parameter load_req=3'b001;
parameter load_rep=3'b101;
parameter wait_req=3'b010;
parameter wait_rep=3'b110;
//FSM
reg [2:0] rstate;
reg [2:0] nstate;
reg en_deq_req;
reg en_deq_rep;
reg en_load;
reg en_cnt;
reg rst_cnt;
reg en_read_all;
reg C_busy;
// generate flit to flit registers
wire [17:0] temp_flit;
wire [15:0] flit;
wire [1:0] ctrl;
assign temp_flit=en_deq_rep?rep_flit:req_flit;
assign ctrl=temp_flit[17:16];
assign flit=temp_flit[15:0];
always@(deq_rep_on or deq_req_on or rep_rdy or req_rdy or ctrl )
begin
//defult value for all signals !//
/*no state change by default*/
nstate=rstate;
en_deq_req=1'b0;
en_deq_rep=1'b0;
en_load=1'b0;
en_cnt=1'b0;
rst_cnt=1'b0;
en_read_all=1'b0;
case(rstate)
idle:
begin
if(deq_rep_on|deq_req_on)
begin
C_busy=1;
rst_cnt=1;
if(deq_rep_on)
nstate=load_rep;
else
nstate=load_req;
end
end
load_req:
begin
if(req_rdy==1'b0)
begin
nstate=wait_req;
end
else if(ctrl!=2'b11)
begin
en_deq_req=1'b1;
en_cnt=1'b1;
en_load=1'b1;
end
else if(ctrl==2'b11)
begin
nstate=idle;
en_read_all=1'b1;
end
end
wait_req:
begin
if(req_rdy==1'b1)
begin
if(ctrl==2'b11)
begin
nstate=idle;
en_read_all=1'b1;
end
else
begin
nstate=load_req;
end
en_deq_req=1'b1;
en_load=1'b1;
en_cnt=1'b1;
end
end
load_rep:
begin
if(rep_rdy==1'b0)
begin
nstate=wait_rep;
end
else if(ctrl!=2'b11)
begin
en_deq_rep=1'b1;
en_cnt=1'b1;
en_load=1'b1;
end
else if(ctrl==2'b11)
begin
nstate=idle;
en_load=1'b1;
en_deq_rep=1'b1;
en_read_all=1'b1;
end
end
wait_rep:
begin
if(rep_rdy==1'b1)
begin
if(ctrl==2'b11)
begin
nstate=idle;
en_read_all=1'b1;
end
else
begin
nstate=load_rep;
end
en_deq_rep=1'b1;
en_cnt=1'b1;
en_load=1'b1;
end
end
endcase
end
//counter for write address to flit regs
reg [3:0] cnt;
always@(posedge clk)
begin
if(rst_cnt|rst)
cnt<=4'b0000;
else if(en_cnt)
cnt<=cnt+1'b1;
else
cnt<=cnt;
end
//wire [3:0] cnt_sel;
//assign cnt_sel=cnt;
//Cache_busy register
reg Cbusy;
always@(posedge clk)
begin
if(rst==1'b0|cache_rst==1'b1)
Cbusy<=1'b0;
else if(C_busy==1'b1)
Cbusy<=1'b1;
else
Cbusy<=Cbusy;
end
assign tCbusy=Cbusy;
// reg indicate flit regs are ready!
reg rf_rdy_for_cache;
always@(posedge clk)
begin
if(rst==1'b0|cache_rst==1'b1)
rf_rdy_for_cache<=1'b0;
else if(C_busy==1'b1)
rf_rdy_for_cache<=1'b1;
else
rf_rdy_for_cache<=rf_rdy_for_cache;
end
wire rf_rdy_for_cache_out; //IN_local flit regs busy output!
assign rf_rdy_for_cache_out=rf_rdy_for_cache;
//FSM reg
always @(posedge clk)
begin
if (rst)
rstate <= idle; //reset to idle state
else
rstate <= nstate;
end
// instance of flit regfile
SP_rf_LUT_RAM #(11,16,4) flit_regs (
.clk(clk),
.we(en_load),
.wa(cnt),
.di(flit),
.re(en_read_all),
// .flit_rdy(flit_rdy_out),
.do0(head_flit),
.do1(addrHI_flit),
.do2(addrLO_flit),
.do3(data1HI_flit),
.do4(data1LO_flit),
.do5(data2HI_flit),
.do6(data2LO_flit),
.do7(data3HI_flit),
.do8(data3LO_flit),
.do9(data4HI_flit),
.do10(data4LO_flit)
);
endmodule
|
//date:2016/3/16
//engineer: zhaishaomin
//module function :test whether mem_download will behave as what i want it to do ,such as handling coming flit correctly
/*
// test examples
//wbrep 11 flits long
flits_d_m_areg={flits_in[140:139],1\'b1,local_id,1\'b0,wbrep_cmd,5\'b00000,seled_addr,data_read};
//ATflurep 11 flits long
flits_d_m_areg={state_tag_out[3:2],1\'b0,local_id,1\'b1,ATflurep_cmd,5\'b00000,
seled_addr[31:13],delayed_state_tag,seled_addr[8:0],data_read};
//shrep 9 flits long
msg={temp_rep_head_flit,data_read,32\'h00000000};
//SHexrep 9 flits long
msg={temp_rep_head_flit,data_read,32\'h00000000};
//exrep 9 flits long
msg={temp_rep_head_flit,data_read,32\'h00000000};
//wbreq 3 flits long
msg={temp_rep_head_flit,seled_addr,128\'h0000};
//flushreq 3 flits long
msg={temp_req_head_flit,seled_addr,128\'h0000};
//SCinvreq or invreq 3 flits long
msg={temp_req_head_flit,seled_addr,128\'h0000};
//shreq 3 flits long
flits_d_m_areg={seled_addr[12:11],1\'b0,local_id,1\'b1,shreq_cmd,5\'b00000,seled_addr,128\'hzzzz};
//exreq 3 flits long
flits_d_m_areg={state_tag_out[3:2],1\'b0,local_id,1\'b1,exreq_cmd,5\'b00000,seled_addr,128\'hzzzz};
//C2Hinvrep 3 flits long
flits_d_m_areg={state_tag_out[3:2],1\'b0,local_id,1\'b1,C2Hinvrep_cmd,5\'b00000,
seled_addr[31:13],delayed_state_tag,seled_addr[8:0],128\'hzzzz};
//flushrep 3 flits long
flits_d_m_areg={flits_in[140:139],1\'b1,local_id,1\'b0,flushrep_cmd,5\'b00000,seled_addr,128\'h0000};
//flushfail_rep 3 flits long
flits_d_m_areg={flits_in[140:139],1\'b1,flits_in[132:131],1\'b0,flushfail_rep_cmd,5\'b00000,seled_addr,128\'h0000};
//wbfail_rep 3 flits long
flits_d_m_areg={flits_in[140:139],1\'b1,flits_in[132:131],1\'b0,wbfail_rep_cmd,5\'b00000,seled_addr,128\'h0000};
//nackrep 1 flit long
msg={temp_rep_head_flit,data_read,32\'h00000000};
//C2Cinvrep 1 flit long
flits_d_m_areg={state_tag_out[3:2],1\'b0,local_id,1\'b1,C2Hinvrep_cmd,5\'b00000,
seled_addr[31:13],delayed_state_tag,seled_addr[8:0],128\'hzzzz};
//SCflushrep 1 flit long
msg={temp_rep_head_flit,data_read,32\'h00000000};
*/
`timescale 1ns/1ps
module tb_m_download();
//input
reg clk;
reg rst;
reg [15:0] IN_flit_mem;
reg v_IN_flit_mem;
reg [1:0] In_flit_ctrl;
reg mem_done_access;
//output
wire v_m_download;
wire [175:0] m_donwload_flits;
wire [1:0] m_download_state;
//instantiate the uut
m_download(//input
.clk(clk),
.rst(rst),
.IN_flit_mem(IN_flit_mem),
.v_IN_flit_mem(v_IN_flit_mem),
.In_flit_ctrl(In_flit_ctrl),
.mem_done_access(mem_done_access),
//output
.v_m_download(v_m_download),
.m_donwload_flits(m_donwload_flits),
.m_download_state(m_download_state)
);
// store the simulation log into log_file
integer logfile;
// Initialize Inputs
initial begin
clk=1\'b0;
rst=1\'b1;
IN_flit_mem=16\'h0000;
v_IN_flit_mem=1\'b0;
In_flit_ctrl=2\'b00;
mem_done_access=1\'b0;
end
always #20 clk=~clk;
`define step #40;
initial begin
/////// mem_download test /////////
// First reset all //
$display("(%t) Initializing...", $time);
$fdisplay(log_file, "(%t) Initializing...", $time);
rst=1;
`step
rst=0;
`step
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////REP MSG FROM IN_REP_FIFO//////////////////////////////////////////////////////////////////////
//after a few cycles ,a rep msg from IN_local_rep fifo come and dc_download should be ready to receive the flits
// note :here are three kinds of reps and reqs totally,
// including :9 flits long msg : exrep , shrep, sh->exrep
// 3 flits long msg : invreq, wbreq, flushreq, scflushreq,
// 1 flit long msg : C2Cinvrep so far.
/////////////////////////////////////////////////////////////
/////////////FIRST TEST 11 FLITS LONG MSG
//first flit
IN_flit_mem=16\'h1234;
v_IN_flit_mem=1\'b1;
In_flit_ctrl=2\'b01;
`step
// second flit comes and is usefull for dc_download
IN_flit_mem=16\'h1234;
v_IN_flit_mem=1\'b1;
In_flit_ctrl=2\'b10;
`step
// 3rd flit comes and is usefull for dc_download
IN_flit_mem=16\'h1234;
v_IN_flit_mem=1\'b1;
In_flit_ctrl=2\'b10;
`step
// 4th flit comes and is usefull for dc_download
IN_flit_mem=16\'h1234;
v_IN_flit_mem=1\'b1;
In_flit_ctrl=2\'b10;
// JUST a test that whether ic_download only output inst word to inst cache when it has receiverd all flits taht required!
$display("(%t)TEST ERROR msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
$fdisplay(logfile,"(%t) TEST ERROR msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
`step
// 5th flit comes and is usefull for dc_download
IN_flit_mem=16\'h1234;
v_IN_flit_mem=1\'b1;
In_flit_ctrl=2\'b10;
`step
// 6th flit comes and is usefull for dc_download
IN_flit_mem=16\'h1234;
v_IN_flit_mem=1\'b1;
In_flit_ctrl=2\'b10;
//here assume IN_fifo not ready
`step
//7th invalid
IN_flit_mem=16\'h1234;
v_IN_flit_mem=1\'b0;
In_flit_ctrl=2\'b10;
`step
// 7th flit comes and is usefull for dc_download
IN_flit_mem=16\'h1234;
v_IN_flit_mem=1\'b1;
In_flit_ctrl=2\'b10;
`step
// 8th flit comes and is usefull for dc_download
IN_flit_mem=16\'h1234;
v_IN_flit_mem=1\'b1;
In_flit_ctrl=2\'b10;
//here assume IN_fifo not ready
`step
//9th invalid
IN_flit_mem=16\'h1234;
v_IN_flit_mem=1\'b0;
In_flit_ctrl=2\'b10;
`step
// 9th flit comes and is usefull for dc_download
IN_flit_mem=16\'h1234;
v_IN_flit_mem=1\'b1;
In_flit_ctrl=2\'b10;
`step
// 10th flit comes and is usefull for dc_download
IN_flit_mem=16\'h1234;
v_IN_flit_mem=1\'b1;
In_flit_ctrl=2\'b10;
`step
// 11th flit comes and is usefull for dc_download
IN_flit_mem=16\'h1234;
v_IN_flit_mem=1\'b1;
In_flit_ctrl=2\'b11;
`step
//at this time, inst cache is ready to receive inst word and all inst words have been recceived by ic_download
$display("(%t) msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
$fdisplay(logfile,"(%t) msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
mem_done_access=1\'b1;
/////////////////////////////////////////////////////////////
/////////////FIRST TEST 9 FLITS LONG MSG
//first flit
IN_flit_mem=16\'h1234;
v_IN_flit_mem=1\'b1;
In_flit_ctrl=2\'b01;
//note :the 2nd to 9th are the flits which includes actual inst word betys
`step
// second flit comes and is usefull for ic_download
IN_flit_mem=16\'h1234;
v_IN_flit_mem=1\'b1;
In_flit_ctrl=2\'b10;
`step
// 3rd flit comes and is usefull for ic_download
IN_flit_mem=16\'h1234;
v_IN_flit_mem=1\'b1;
In_flit_ctrl=2\'b10;
`step
// 4th flit comes and is usefull for ic_download
IN_flit_mem=16\'h1234;
v_IN_flit_mem=1\'b1;
In_flit_ctrl=2\'b10;
// JUST a test that whether ic_download only output inst word to inst cache when it has receiverd all flits taht required!
$display("(%t)TEST ERROR msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
$fdisplay(logfile,"(%t) TEST ERROR msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
`step
// 5th flit comes and is usefull for ic_download
IN_flit_mem=16\'h1234;
v_IN_flit_mem=1\'b1;
In_flit_ctrl=2\'b10;
//here assume IN_fifo not ready
`step
//6th invalid
IN_flit_mem=16\'h1234;
v_IN_flit_mem=1\'b0;
In_flit_ctrl=2\'b10;
`step
// 6th flit comes and is usefull for ic_download
IN_flit_mem=16\'h1234;
v_IN_flit_mem=1\'b1;
In_flit_ctrl=2\'b10;
// just test that whether ic_download only output inst word to inst cache when it has receiverd all flits taht required!
`step
// 7th flit comes and is usefull for ic_download
IN_flit_mem=16\'h1234;
v_IN_flit_mem=1\'b1;
In_flit_ctrl=2\'b10;
`step
// 8th flit comes and is usefull for ic_download
IN_flit_mem=16\'h1234;
v_IN_flit_mem=1\'b1;
In_flit_ctrl=2\'b10;
`step
// 9th flit comes and is usefull for ic_download
IN_flit_mem=16\'h1234;
v_IN_flit_mem=1\'b1;
In_flit_ctrl=2\'b11;
`step
//at this time, inst cache is ready to receive inst word and all inst words have been recceived by ic_download
$display("(%t) msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
$fdisplay(logfile,"(%t) msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
`step
`step
`step
mem_done_access=1\'b1;
/////////////////////////////////////////////////////////////
/////////////FIRST TEST 3 FLITS LONG MSG
//first flit
IN_flit_mem=16\'h1234;
v_IN_flit_mem=1\'b1;
In_flit_ctrl=2\'b01;
//here assume IN_fifo not ready
`step
//2th invalid
IN_flit_mem=16\'h1234;
v_IN_flit_mem=1\'b0;
In_flit_ctrl=2\'b10;
`step
// second flit comes and is usefull for ic_download
IN_flit_mem=16\'h1234;
v_IN_flit_mem=1\'b1;
In_flit_ctrl=2\'b10;
// JUST a test that whether ic_download only output inst word to inst cache when it has receiverd all flits taht required!
$display("(%t)TEST ERROR msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
$fdisplay(logfile,"(%t) TEST ERROR msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
`step
// 3rd flit comes and is usefull for ic_download
IN_flit_mem=16\'h1234;
v_IN_flit_mem=1\'b1;
In_flit_ctrl=2\'b11;
`step
//at this time, inst cache is ready to receive inst word and all inst words have been recceived by ic_download
$display("(%t) msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
$fdisplay(logfile,"(%t) msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
`step
mem_done_access=1\'b1;
/////////////////////////////////////////////////////////////
/////////////FIRST TEST 1 FLITS LONG MSG
//first flit
IN_flit_mem=16\'h1234;
v_IN_flit_mem=1\'b1;
In_flit_ctrl=2\'b01;
`step
$display("(%t) msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
$fdisplay(logfile,"(%t) msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
`step
`step
`step
`step
mem_done_access=1\'b1;
`step
$display("(%t) msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
$fdisplay(logfile,"(%t) msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
$stop;
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////LOADABLE COUNTER////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//Generic n-bit incrementable loadable counter
module counter_loadable (CLK, //input assert posedge to increment/decrement counter
EN, //input enable signal (assert to allow counter to count)
RST, //input assert to set counter
DIN, //input data to set counter to
DONE, //output asserted if count is reached
COUNT); //output [n:0] current count
//////////MODULE PARAMETERS//////////
parameter n=4, //width of counter
start=0, //This value doesn't matter.. dummy var to make parameters the same
final=8, //ending value of counter
step=1; //step to increment by (set to -1 for decrementing)
//////////SIGNALS ///////////////////
input CLK;
input RST;
input EN;
input [n-1:0] DIN;
output DONE;
output [n-1:0] COUNT;
///////////IMPLEMENTATION//////////////////////
reg [n-1:0] COUNT;
always @ (posedge CLK or posedge RST)
begin
if (RST)
#5 COUNT = DIN;
else if (EN)
#5 COUNT = COUNT + step;
end
assign DONE = (COUNT == final);
endmodule
|
// date:2016/3/20
// engineer:ZhaiShaoMin
// module name: PHT :Pattern History Table,actually should be direction predictor.
// moduel implementation:
// this is a local predictor
// in read stage(if stage) first we index BHR, then use conbination of BHR and pc to index PHT
// then we get the direction infos to judge which path to go .
// in write stage(id stage) we use BHR_rd of id stage to generate index of PHT,
// then use delayed PHT to judge whether we need to update the PHT.
//
// test plan is shown below! I think it will be ok for 3 bits BHR if it works well for 2 bits BHR.
//
/***from MIT 6-823-fall-2005\\contents\\assignments
loop: LW R4, 0(R3)
ADDI R3, R3, 4
SUBI R1, R1, 1
b1: BEQZ R4, b2ADDI R2, R2, 1
b2: BNEZ R1, loop
PC R3/R4 b1 bits b2 bits Predicted Actual
b1 4/1 10 10 N N
b2 4/1 10 10 N T
b1 8/0 10 11 N T
b2 8/0 11 11 N T
b1 12/1 11 00 N N
b2 12/1 10 00 T T
b1 16/0 10 00 N T
b2 16/0 11 00 T T
b1 20/1 11 00 N N
b2 20/1 10 00 T T
b1 24/0 10 00 N T
b2 24/0 11 00 T T
b1 28/1 11 00 N N
b2 28/1 10 00 T T
b1 32/0 10 00 N T
b2 32/0 11 00 T N
Assume the initial value of R1 is n (n>0).
Assume the initial value of R2 is 0 (R2 holds the result of the program).
Assume the initial value of R3 is p (a pointer to the beginning of an array of 32-bit integers).
******/
// the only thing I need to do is to figure out the chart above , according to this module
`timescale 1ns/1ps
`include "define.v"
module tb_core_pht();
//input
reg clk;
reg rst;
reg update_BP;
reg pred_right;
reg taken;
reg [9:0] if_pc; //part of pc
reg [9:0] id_pc; // part of pc
//reg [3:0] BHR_in;
reg [1:0] delayed_PHT;
//output
wire pred_out;
//wire [3:0] BHR_rd;
wire [1:0] PHT_out;
core_pht duv(//input
.clk(clk),
.rst(rst),
.if_pc(if_pc), // pc[10:5]
.id_pc(id_pc), // pc[10:5]
.update_BP(update_BP),
.pred_right(pred_right),
.taken(taken),
// .BHR_in(BHR_in),
//delayed PHT_out from previous stage , useful to avoid reading PHT when update PHT
.delayed_PHT(delayed_PHT),
//output
.pred_out(pred_out),
// .BHR_rd(BHR_rd),
.PHT_out(PHT_out)
);
\t\t\t\t\t\t
\tinitial begin
\t clk=1\'b0;
\t\trst=1\'b1;
\t\tif_pc=16\'d1430;
\t\tid_pc=16\'d1450;
\t\tupdate_BP=1\'b0;
pred_right=1\'b0;
delayed_PHT=2\'b00;
\t\ttaken=1\'b0;
\t\t
\t\tend
\t\t
\t\talways #5 clk=~clk;
\t\t`define clk_step #10;
\t\t
\t//////////////////////////////////////////////////////////////////////
\t//////////////////////////////begin test//////////////////////////////
\t
\tinitial begin
// R3/R4\t
\t`clk_step
\trst=1\'b0;
// 4/1
\tif_pc = 16\'d1430;
\t//$display("b1 bits should be 2\'b00, actually pht array: %b or pred_out: %b ", PHT[if_pc], PHT_out);
\t
\t`clk_step
// 4/1
//update
id_pc = 16\'d1430;
\tupdate_BP=1\'b1;
\ttaken = 1\'b0;
\tdelayed_PHT=2\'b00;
\t//predict
\tif_pc = 16\'d1450;
\t
\t`clk_step
// 8/0
\t//update
\tid_pc = 16\'d1450;
\tupdate_BP=1\'b1;
\ttaken = 1\'b1;
\tdelayed_PHT=2\'b00;
//predict
\tif_pc = 16\'d1430;
\t
\t`clk_step
// 8/0
\t//update
\tid_pc = 16\'d1430;
\tupdate_BP=1\'b1;
\ttaken = 1\'b1;
\tdelayed_PHT=2\'b00;
\t//predict
\tif_pc = 16\'d1450;
\t
\t`clk_step
// 12/1
\t//update
\tid_pc = 16\'d1450;
\tupdate_BP=1\'b1;
\ttaken = 1\'b1;
\tdelayed_PHT=2\'b01;
\t//predict
\tif_pc = 16\'d1430;
\t
\t`clk_step
// 12/1
\t//update
\tid_pc = 16\'d1430;
\tupdate_BP=1\'b1;
\ttaken = 1\'b0;
\tdelayed_PHT=2\'b01;
\t//predict
\tif_pc = 16\'d1450;
\t
\t`clk_step
// 16/0
\t//update
\tid_pc = 16\'d1450;
\tupdate_BP=1\'b1;
\ttaken = 1\'b1;
\tdelayed_PHT=2\'b10;
\t//predict
\tif_pc = 16\'d1430;
\t
\t`clk_step
// 16/0
\t//update
\tid_pc = 16\'d1430;
\tupdate_BP=1\'b1;
\ttaken = 1\'b1;
\tdelayed_PHT=2\'b00;
\t//predict
\tif_pc = 16\'d1450;
\t
\t`clk_step
// 20/1
\t//update
\tid_pc = 16\'d1450;
\tupdate_BP=1\'b1;
\ttaken = 1\'b1;
\tdelayed_PHT=2\'b10;
\t//predict
\tif_pc = 16\'d1430;
\t
\t`clk_step
// 20/1
\t//update
\tid_pc = 16\'d1430;
\tupdate_BP=1\'b1;
\ttaken = 1\'b0;
\tdelayed_PHT=2\'b01;
\t//predict
\tif_pc = 16\'d1450;
\t
\t`clk_step
// 24/0
\t//update
\tid_pc = 16\'d1450;
\tupdate_BP=1\'b1;
\ttaken = 1\'b1;
\tdelayed_PHT=2\'b10;
\t//predict
\tif_pc = 16\'d1430;
\t
\t`clk_step
// 24/0
\t//update
\tid_pc = 16\'d1430;
\tupdate_BP=1\'b1;
\ttaken = 1\'b1;
\tdelayed_PHT=2\'b00;
\t//predict
\tif_pc = 16\'d1450;
\t
\t`clk_step
// 28/1
\t//update
\tid_pc = 16\'d1450;
\tupdate_BP=1\'b1;
\ttaken = 1\'b1;
\tdelayed_PHT=2\'b10;
\t//predict
\tif_pc = 16\'d1430;
\t
\t`clk_step
// 28/1
\t//update
\tid_pc = 16\'d1430;
\tupdate_BP=1\'b1;
\ttaken = 1\'b0;
\tdelayed_PHT=2\'b01;
\t//predict
\tif_pc = 16\'d1450;
\t
\t`clk_step
// 32/0
\t//update
\tid_pc = 16\'d1450;
\tupdate_BP=1\'b1;
\ttaken = 1\'b1;
\tdelayed_PHT=2\'b10;
\t//predict
\tif_pc = 16\'d1430;
\t
\t`clk_step
// 32/0
\t//update
\tid_pc = 16\'d1430;
\tupdate_BP=1\'b1;
\ttaken = 1\'b1;
\tdelayed_PHT=2\'b00;
\t//predict
\tif_pc = 16\'d1450;
\t
\t $stop;
\t end
\tendmodule
|
//date:2016/3/12
//engineer:ZhaiShaoMin
//module name :excution stage of core
module core_ex(//input
alusrc_a,
alusrc_b,
aluop,
// inst_lo,
regdst,
alusrc,
id_ex_rs,
id_ex_rt,
id_ex_rd,
mem_regwrite,
wb_regwrite,
mem_regrd,
wb_regrd,
wb_reg_data,
mem_reg_data,
id_ex_sign_extend,
//output
alu_result,
data_to_mem,
ex_dest_rd,
zero
);
//parameter
parameter sll_fun=6'b000000;
parameter srl_fun=6'b000010;
parameter sra_fun=6'b000011;
parameter sllv_fun=6'b000100;
parameter srlv_fun=6'b000110;
parameter srav_fun=6'b000111;
parameter addu_fun =6'b100001;
parameter subu_fun =6'b100011;
parameter and_fun =6'b100100;
parameter or_fun =6'b100101;
parameter xor_fun =6'b100110;
parameter nor_fun =6'b100111;
parameter sltu_fun =6'b101011;
//op of i_type
parameter slti_op=4'b0011;
parameter sltiu_op=4'b0100;
parameter andi_op=4'b0101;
parameter ori_op=4'b0110;
parameter xori_op=4'b0111;
parameter lui_op=4'b1000;
//input
input [31:0] alusrc_a;
input [31:0] alusrc_b;
input [3:0] aluop;
//input [5:0] inst_fun;
input regdst;
input [1:0] alusrc;
input [4:0] id_ex_rs;
input [4:0] id_ex_rt;
input [4:0] id_ex_rd;
input mem_regwrite;
input wb_regwrite;
input [4:0] mem_regrd;
input [4:0] wb_regrd;
input [31:0] mem_reg_data;
input [31:0] wb_reg_data;
input [31:0] id_ex_sign_extend;
//output
output [31:0] alu_result;
output [31:0] data_to_mem;
output [4:0] ex_dest_rd;
output zero;
// mux alu_operand_src for alu
wire [31:0] alu_src1;
wire [31:0] alu_src2;
//forwarding_unit_for_alu_src_operand
reg [1:0] forwarda;
reg [1:0] forwardb;
//alu
reg [31:0] alu_result;
reg zero;
reg [31:0] alu_temp;
wire [31:0] shift_src;
wire [31:0] zero_ext;
wire [31:0] temp_shift;
wire [31:0] alu_src_reg_imm;
always@(*)
begin
//default values
if(wb_regwrite&&(wb_regrd!=5'b00000)&&!(mem_regwrite&&(mem_regrd!=5'b00000)&&(mem_regrd!=id_ex_rs))&&(wb_regrd==id_ex_rs))
forwarda=2'b10;
else if(mem_regwrite&&(mem_regrd!=5'b00000)&&(mem_regrd==id_ex_rs))
forwarda=2'b01;
else
forwarda=2'b00;
if(wb_regwrite&&(wb_regrd!=5'b00000)&&!(mem_regwrite&&(mem_regrd!=5'b00000)&&(mem_regrd!=id_ex_rt))&&(wb_regrd==id_ex_rt))
forwardb=2'b10;
else if(mem_regwrite&&(mem_regrd!=5'b00000)&&(mem_regrd==id_ex_rt))
forwardb=2'b01;
else
forwardb=2'b00;
end
//forward alu_src
assign alu_src1=(forwarda==2'b10)? wb_reg_data: ((forwarda==2'b01)? mem_reg_data:alusrc_a);
assign alu_src2=(forwardb==2'b10)? wb_reg_data: ((forwardb==2'b01)? mem_reg_data:alusrc_b);
assign alu_src_reg_imm=(alusrc==2'b00)?alu_src2:(alusrc==2'b01)?id_ex_sign_extend:zero_ext;
// mux dest_reg for inst intended to write reg
assign ex_dest_rd=regdst?id_ex_rd:id_ex_rt;
assign data_to_mem=alu_src2;
reg shamt_rs;
reg [3:0] alu_ctrl;
// alu_control unit
always@(*)
begin
//default values
shamt_rs=1'b0; // 0:shamt 1:rs as a shift distence of shift inst
alu_ctrl=4'b0000;
case(aluop)
4'b0000:
//lw,sw
begin
alu_ctrl=4'b0000;
end
4'b0001:
//branch eq
begin
alu_ctrl=4'b1111;
end
4'b0010:
// R_type according to fun field
begin
case(id_ex_sign_extend[5:0])
//add
6'b100000:alu_ctrl=4'b0000;
//sub
6'b100010:alu_ctrl=4'b0001;
//and
6'b100100:alu_ctrl=4'b0010;
//or
6'b100101:alu_ctrl=4'b0011;
//set on less than
6'b101010:alu_ctrl=4'b0100;
//R_type
sll_fun:
begin
alu_ctrl=4'b0101;
end
srl_fun:
begin
alu_ctrl=4'b0110;
end
sra_fun:
begin
alu_ctrl=4'b0111;
end
sllv_fun:
begin
alu_ctrl=4'b0101;
shamt_rs=1'b1;
end
srlv_fun:
begin
alu_ctrl=4'b0110;
shamt_rs=1'b1;
end
srav_fun:
begin
alu_ctrl=4'b0111;
shamt_rs=1'b1;
end
addu_fun:
begin
alu_ctrl=4'b0000;
end
subu_fun:
begin
alu_ctrl=4'b0001;
end
xor_fun:
begin
alu_ctrl=4'b1000;
end
nor_fun:
begin
alu_ctrl=4'b1001;
end
sltu_fun:
begin
alu_ctrl=4'b0100;
end
endcase
end
slti_op:alu_ctrl=4'b0100;
sltiu_op:alu_ctrl=4'b0100;
andi_op:alu_ctrl=4'b0001;
ori_op:alu_ctrl=4'b0011;
xori_op:alu_ctrl=4'b1000;
lui_op:alu_ctrl=4'b1010;
endcase
end
assign temp_shift={alu_src_reg_imm[31],31'b0000000000000000000000000000000};
assign zero_ext={16'h0000,id_ex_sign_extend[15:0]};
assign shift_src=shamt_rs?{27'h0000,id_ex_sign_extend[10:6]}:alu_src1;
always@(*)
begin
alu_result=32'h0001;
zero=1'b0;
alu_temp=32'h0000;
case(alu_ctrl)
//add
4'b0000:alu_result=alu_src1+alu_src_reg_imm;
//sub
4'b0001:
begin
alu_result=alu_src1-alu_src_reg_imm;
if(alu_result==32'h0000)
zero=1'b1;
end
//and
4'b0010:alu_result=alu_src1&alu_src_reg_imm;
//or
4'b0011:alu_result=alu_src1|alu_src_reg_imm;
//set on less than
4'b0100:
begin
alu_temp=alu_src1-alu_src_reg_imm;
if(alu_temp[31]==1'b0)
alu_result=32'h0000;
end
//sll
4'b0101:alu_result=alu_src_reg_imm<<shift_src;
//srl
4'b0110:alu_result=alu_src_reg_imm>>shift_src;
//sra
4'b0111:alu_result=(alu_src_reg_imm>>shift_src)|(temp_shift>>shift_src);
//xor
4'b1000:alu_result=alu_src1^alu_src_reg_imm;
//nor
4'b1001:alu_result=!(alu_src1|alu_src_reg_imm);
//lui
4'b1010:alu_result={id_ex_sign_extend[15:0],16'h0000};
endcase
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////RAM BASED FIFO//////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
module fifo (CLK, //input - clock to sample data in at. (e.g. DRAM_CLK)
DIN, //input [18:0] - data to input into FIFO width is 19 or some other 19=1( whether next_node is dest id)
RST, //input - reset trigger for shift register +2(ctrl 00:nothing 01:head 10:body 11:tail
IN_EN, //input - input enable (allow shifting to start) +16(flit is 16 bits long)
OUT_EN, //input - output enable (allow shifting to start)
DOUT, //output [18:0] - data to output from FIFO
FULL, //output - indicate that fifo is full
EMPTY //output - indicate that fifo is empty
);
// parameter fifo_depth=16;
// parameter fifo_width=19;
input CLK;
input [18:0] DIN;
input RST;
input IN_EN;
input OUT_EN;
output[18:0] DOUT;
output FULL;
output EMPTY;
wire empty_en;
wire full_en;
reg [3:0] cnthead;
reg [3:0] cnttail;
reg full;
reg empty;
reg [18:0] fifo [0:15] ;
reg [18:0] DOUT_temp;
reg [4:0] fcnt;
//fifo counter
always @(posedge CLK or posedge RST)
begin
if(RST)
fcnt<=5'b0;
else if((!OUT_EN&&IN_EN)||(OUT_EN&&!IN_EN))
begin
if(IN_EN)
fcnt<=fcnt+1'b1;
else
fcnt<=fcnt-1'b1;
end
else fcnt<=fcnt;
end
//head counter
always@(posedge CLK or posedge RST )
if(RST)
cnthead=4'b0000;
else if(OUT_EN)
cnthead=cnthead+1;
//tail counter
always@(posedge CLK or posedge RST )
if(RST)
cnttail=4'b0000;
else if(IN_EN)
cnttail=cnttail+1;
// reg full state
always@(posedge CLK or posedge RST )
if(RST)
full=0;
else if(full_en)
full=1;
//reg empty state
always@(posedge CLK or posedge RST )
if(RST)
empty=0;
else if(empty_en)
empty=1;
// write data into fifo
always@(IN_EN )
begin
if(IN_EN)
fifo[cnttail]=DIN;
end
// read data from fifo
always@( OUT_EN)
begin
if(OUT_EN)
DOUT_temp=fifo[cnthead];
else
DOUT_temp=19'h00000;
end
/// assign some signals!
assign full_en=((fcnt==5'b01111&&IN_EN))? 1:0;
assign empty_en=((fcnt==5'b00001&&OUT_EN))? 1:0;
assign DOUT=DOUT_temp;
assign FULL=full;
assign EMPTY=empty;
endmodule
|
/// date:2016/3/9
/// engineer: ZhaiShaoMin
module i_m_areg(//input
clk,
rst,
i_flits_m,
v_i_flits_m,
mem_done_access,
//output
i_m_areg_flits,
v_i_areg_m_flits
);
//input
input clk;
input rst;
input [47:0] i_flits_m;
input v_i_flits_m;
input mem_done_access;
//output
output [47:0] i_m_areg_flits;
output v_i_areg_m_flits;
reg i_m_cstate;
reg [47:0] flits_reg;
//assign i_m_areg_state=i_m_cstate;// when m_d_cstate is 1, it means this module is busy and
// can't receive other flits. otherwise,able to receiving flits
always@(posedge clk)
begin
if(rst||mem_done_access)
flits_reg<=48'h0000;
else if(v_i_flits_m)
flits_reg<=i_flits_m;
end
always@(posedge clk)
begin
if(rst||mem_done_access)
i_m_cstate<=1'b0;
else if(v_i_flits_m)
i_m_cstate<=1'b1;
end
assign v_i_areg_m_flits=i_m_cstate;
assign i_m_areg_flits=flits_reg;
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: my_scfifo.v
// Megafunction Name(s):
// \t\t\tscfifo
//
// Simulation Library Files(s):
// \t\t\taltera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation\'s design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module my_scfifo (
\taclr,
\tclock,
\tdata,
\trdreq,
\twrreq,
\tempty,
\tfull,
\tq,
\tusedw);
\tinput\t aclr;
\tinput\t clock;
\tinput\t[17:0] data;
\tinput\t rdreq;
\tinput\t wrreq;
\toutput\t empty;
\toutput\t full;
\toutput\t[17:0] q;
\toutput\t[3:0] usedw;
\twire [3:0] sub_wire0;
\twire sub_wire1;
\twire sub_wire2;
\twire [17:0] sub_wire3;
\twire [3:0] usedw = sub_wire0[3:0];
\twire empty = sub_wire1;
\twire full = sub_wire2;
\twire [17:0] q = sub_wire3[17:0];
\tscfifo\tscfifo_component (
\t\t\t\t.clock (clock),
\t\t\t\t.wrreq (wrreq),
\t\t\t\t.aclr (aclr),
\t\t\t\t.data (data),
\t\t\t\t.rdreq (rdreq),
\t\t\t\t.usedw (sub_wire0),
\t\t\t\t.empty (sub_wire1),
\t\t\t\t.full (sub_wire2),
\t\t\t\t.q (sub_wire3),
\t\t\t\t.almost_empty (),
\t\t\t\t.almost_full (),
\t\t\t\t.sclr ());
\tdefparam
\t\tscfifo_component.add_ram_output_register = "OFF",
\t\tscfifo_component.intended_device_family = "Cyclone IV E",
\t\tscfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M9K",
\t\tscfifo_component.lpm_numwords = 16,
\t\tscfifo_component.lpm_showahead = "OFF",
\t\tscfifo_component.lpm_type = "scfifo",
\t\tscfifo_component.lpm_width = 18,
\t\tscfifo_component.lpm_widthu = 4,
\t\tscfifo_component.overflow_checking = "ON",
\t\tscfifo_component.underflow_checking = "ON",
\t\tscfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "18"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "18"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M9K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "18"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL "data[17..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL "q[17..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 4 0 OUTPUT NODEFVAL "usedw[3..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 18 0 data 0 0 18 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 18 0 @q 0 0 18 0
// Retrieval info: CONNECT: usedw 0 0 4 0 @usedw 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL my_scfifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL my_scfifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL my_scfifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL my_scfifo.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL my_scfifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL my_scfifo_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// date:2016/3/16
// engineer:ZhaiShaoMin
// project:multicore ring based project
// module function: testbench for ic_download
`timescale 1ns/1ps
//`include "constants.v"
module tb_ic_download();
//inputs
reg clk;
reg rst;
reg [15:0] rep_flit_ic;
reg v_rep_flit_ic;
reg [1:0] rep_ctrl_ic;
reg [127:0] mem_flits_ic;
reg v_mem_flits_ic;
//outputs
wire ic_download_state;
wire inst_word_ic;
wire v_inst_word;
//instantiate the uut
ic_download uut(//input
.clk(clk),
.rst(rst),
.rep_flit_ic(rep_flit_ic),
.v_rep_flit_ic(v_rep_flit_ic),
.rep_ctrl_ic(rep_ctrl_ic),
.mem_flits_ic(mem_flits_ic),
.v_mem_flits_ic(v_mem_flits_ic),
//output
.ic_download_state(ic_download_state),
.inst_word_ic(inst_word_ic),
.v_inst_word(v_inst_word)
);
integer i,j;
integer log_file;
// Initialize Inputs
initial begin
clk = 0;
rst = 0;
rep_flit_ic=16\'h1234;
v_rep_flit_ic=1\'b0;
rep_ctrl_ic=2\'b00;
mem_flits_ic=128\'h12345678123456781234567812345678;
v_mem_flits_ic=1\'b0;
end
always #20 clk=~clk;
`define step #40;
initial begin
/////// ic_download test /////////
// First reset all //
$display("(%t) Initializing...", $time);
$fdisplay(log_file, "(%t) Initializing...", $time);
rst=1;
`step
rst=0;
//////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////REP MSG FROM LOCAL MEM/////////////////////////////////////////////////////////////
//here we assume that m_i_areg send a rep msg to test datapath from mem to inst cache
mem_flits_ic=128\'h12345678123456781234567812345678;
v_mem_flits_ic=1\'b1;
`step
$display("(%t)inst word sent to inst cache is valid:%d inst:%h and ic_download_state is :%b",$time,v_inst_word_ic,inst_word_ic,ic_download_state);
$fdisplay(logfile,"(%t) inst word sent to inst cache is :%h and ic_download_state is :%b",$time,v_inst_word_ic,inst_word_ic,ic_download_state);
`step
`step
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////REP MSG FROM IN_REP_FIFO//////////////////////////////////////////////////////////////////////
//after a few cycles ,another rep msg from IN_local_rep fifo come and ic_download should be ready to receive the flits
// note : because head flit of inst_rep is useless for inst cache ,first flit will be droped by ic_download
//first flit
rep_flit_ic=16\'h1234;
v_rep_flit_ic=1\'b1;
rep_ctrl_ic=2\'b01;
//note :the 2nd to 9th are the flits which includes actual inst word betys
`step
// second flit comes and is usefull for ic_download
rep_flit_ic=16\'h1234;
v_rep_flit_ic=1\'b1;
rep_ctrl_ic=2\'b10;
`step
// 3rd flit comes and is usefull for ic_download
rep_flit_ic=16\'h1234;
v_rep_flit_ic=1\'b1;
rep_ctrl_ic=2\'b10;
`step
// 4th flit comes and is usefull for ic_download
rep_flit_ic=16\'h1234;
v_rep_flit_ic=1\'b1;
rep_ctrl_ic=2\'b10;
// JUST a test that whether ic_download only output inst word to inst cache when it has receiverd all flits taht required!
$display("(%t)just test ERROR:inst word sent to inst cache is valid:%d inst:%h and ic_download_state is :%b",$time,v_inst_word_ic,inst_word_ic,ic_download_state);
$fdisplay(logfile,"(%t)just test ERROR: inst word sent to inst cache is :%h and ic_download_state is :%b",$time,v_inst_word_ic,inst_word_ic,ic_download_state);
`step
// 5th flit comes and is usefull for ic_download
rep_flit_ic=16\'h1234;
v_rep_flit_ic=1\'b1;
rep_ctrl_ic=2\'b10;
`step
// 6th flit comes and is usefull for ic_download
rep_flit_ic=16\'h1234;
v_rep_flit_ic=1\'b1;
rep_ctrl_ic=2\'b10;
// just test that whether ic_download only output inst word to inst cache when it has receiverd all flits taht required!
`step
// 7th flit comes and is usefull for ic_download
rep_flit_ic=16\'h1234;
v_rep_flit_ic=1\'b1;
rep_ctrl_ic=2\'b10;
`step
// 8th flit comes and is usefull for ic_download
rep_flit_ic=16\'h1234;
v_rep_flit_ic=1\'b1;
rep_ctrl_ic=2\'b10;
`step
// 9th flit comes and is usefull for ic_download
rep_flit_ic=16\'h1234;
v_rep_flit_ic=1\'b1;
rep_ctrl_ic=2\'b11;
`step
//at this time, inst cache is ready to receive inst word and all inst words have been recceived by ic_download
$display("(%t)inst word sent to inst cache is valid:%d inst:%h and ic_download_state is :%b",$time,v_inst_word_ic,inst_word_ic,ic_download_state);
$fdisplay(logfile,"(%t) inst word sent to inst cache is :%h and ic_download_state is :%b",$time,v_inst_word_ic,inst_word_ic,ic_download_state);
$stop;
end
endmodule
|
// date:2016/3/1
// engineer: ZhaiShaoMin
// module name:FSM_unload_flit
//transfer flit of msg from cache or mem to network local out fifos
// parallel msg to serial flits stream for transfering on ring network
module FSM_upload_flit(// input
clk,
rst,
en_for_reg,
out_req_fifo_rdy,
cnt_invs_eq_3,
cnt_eq_max,
head_flit,
inv_ids_reg,
sel_cnt_invs,
sel_cnt_eq_0,
// output
en_inv_ids,
en_flit_max_in,
inc_sel_cnt_invs,
inc_sel_cnt,
ctrl,
clr_max,
clr_inv_ids,
clr_sel_cnt_inv,
clr_sel_cnt,
dest_sel,
fsm_state_out,
en_flit_out
);
//input
input clk;
input rst;
input out_req_fifo_rdy; // enable for inv_ids reg
input en_for_reg; // enable for all kinds of flits regs
input cnt_invs_eq_3;
input cnt_eq_max;
input [15:0] head_flit;
input [3:0] inv_ids_reg;
input [1:0] sel_cnt_invs;
input sel_cnt_eq_0;
// output
output en_inv_ids;
output en_flit_max_in;
output inc_sel_cnt_invs;
output inc_sel_cnt;
output [1:0] ctrl;
output clr_max;
output clr_inv_ids;
output clr_sel_cnt_inv;
output clr_sel_cnt;
output dest_sel;
output [1:0] fsm_state_out;
output en_flit_out;
/// parameter for cmd
parameter shreq_cmd=5'b00000;
parameter exreq_cmd=5'b00001;
parameter SCexreq_cmd=5'b00010;
parameter instreq_cmd=5'b00110;
parameter wbreq_cmd=5'b00011;
parameter invreq_cmd=5'b00100;
parameter flushreq_cmd=5'b00101;
parameter SCinvreq_cmd=5'b00110;
parameter wbrep_cmd=5'b10000;
parameter C2Hinvrep_cmd=5'b10001;
parameter flushrep_cmd=5'b10010;
parameter ATflurep_cmd=5'b10011;
parameter shrep_cmd=5'b11000;
parameter exrep_cmd=5'b11001;
parameter SH_exrep_cmd=5'b11010;
parameter SCflurep_cmd=5'b11100;
parameter instrep=5'b10100;
parameter C2Cinvrep_cmd=5'b11011;
///////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////CONTROL UNIT/////////////////////////////////////////////////
parameter upload_idle=2'b00;
parameter upload_scORinvreqs=2'b01;
parameter upload_wbORflushreqs=2'b10;
reg [1:0] upload_rstate;
reg [1:0] upload_nstate;
// update FSM
always@(posedge clk)
begin
if(rst)
upload_rstate<=2'b00;
else
upload_rstate<=upload_nstate;
end
assign fsm_state_out=upload_rstate;
reg en_inv_ids;
reg en_flit_max_in;
reg inc_sel_cnt_invs;
reg inc_sel_cnt;
reg [1:0] ctrl;
reg clr_max;
reg clr_inv_ids;
reg clr_sel_cnt_inv;
reg clr_sel_cnt;
reg dest_sel;
reg en_flit_out;
// next state function
always@(*)
begin
//default signals
upload_nstate=upload_idle;
en_inv_ids=1'b0;
en_flit_max_in=1'b0;
inc_sel_cnt_invs=1'b0;
inc_sel_cnt=1'b0;
ctrl=2'b00;
clr_max=1'b0;
clr_inv_ids=1'b0;
clr_sel_cnt_inv=1'b0;
clr_sel_cnt=1'b0;
dest_sel=1'b0;
en_flit_out=1'b0;
case(upload_rstate)
upload_idle:
begin
if(en_for_reg&&(head_flit[9:5]==invreq_cmd||head_flit[9:5]==SCinvreq_cmd))
begin
upload_nstate=upload_scORinvreqs;
en_inv_ids=1'b1;
end
if(en_for_reg&&(head_flit[9:5]==wbreq_cmd||head_flit[9:5]==flushreq_cmd))
upload_nstate=upload_wbORflushreqs;
en_flit_max_in=1'b1;
end
upload_scORinvreqs:
begin
if(out_req_fifo_rdy==1'b0)
begin
upload_nstate=upload_scORinvreqs;
end
else
begin
\t\t\t en_flit_out=1'b1;
if(inv_ids_reg[sel_cnt_invs]==1'b0)
inc_sel_cnt_invs=1'b1;
else
begin
if(cnt_invs_eq_3==1'b1)
begin
if(cnt_eq_max==1'b1)
begin
ctrl=2'b11;
clr_max=1'b1;
clr_inv_ids=1'b1;
clr_sel_cnt_inv=1'b1;
clr_sel_cnt=1'b1;
upload_nstate=upload_idle;
end
else
begin
upload_nstate=upload_scORinvreqs;
inc_sel_cnt=1'b1;
if(sel_cnt_eq_0)
begin
ctrl=2'b01;
dest_sel=1'b0;
end
else
begin
ctrl=2'b10;
end
end
end
else
begin
upload_nstate=upload_scORinvreqs;
if(cnt_eq_max)
begin
inc_sel_cnt_invs=1'b1;
clr_sel_cnt=1'b1;
end
else
begin
inc_sel_cnt=1'b1;
if(sel_cnt_eq_0)
begin
ctrl=2'b01;
dest_sel=1'b0;
end
else
begin
ctrl=2'b10;
end
end
end
end//
end//end of upload_scorinvreqs's else begin
end // end of upload_scorinvreqs
upload_wbORflushreqs:
begin
if(out_req_fifo_rdy==1'b0)
begin
upload_nstate=upload_wbORflushreqs;
end
else
begin
\t\t\t en_flit_out=1'b1;
if(cnt_eq_max)
begin
upload_nstate=upload_idle;
clr_sel_cnt=1'b1;
clr_max=1'b1;
ctrl=2'b11;
end
else
begin
upload_nstate=upload_wbORflushreqs;
inc_sel_cnt=1'b1;
if(sel_cnt_eq_0)
begin
ctrl=2'b01;
dest_sel=1'b1;
end
else
begin
ctrl=2'b10;
end
end
end
end
endcase
end
endmodule
|
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
University of Illinois/NCSA
Open Source License
Copyright(C) 2004, The Board of Trustees of the
University of Illinois. All rights reserved
IVM 1.0
Developed by:
Advanced Computing Systems Group
Center for Reliable and High-Performance Computing
University of Illinois at Urbana-Champaign
http://www.crhc.uiuc.edu/ACS
-- with support from --
Center for Circuits and Systems Solutions (C2S2)
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the Software), to
deal with the Software without restriction, including without limitation the
rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
sell copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimers.
Redistributions in binary, gate-level, layout-level, or physical form must
reproduce the above copyright notice, this list of conditions and the
following disclaimers in the documentation and/or other materials provided
with the distribution.
Neither the names of Advanced Computing Systems Group, Center for Reliable
and High-Performance Computing, Center for Circuits and Systems Solution
(C2S2), University of Illinois at Urbana-Champaign, nor the names of its
contributors may be used to endorse or promote products derived from this
Software without specific prior written permission.
THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
WITH THE SOFTWARE.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
/*******************************************************************************
File: MUXn_8_1.v
Description: This file contains the definition of a n-bit 8-to-1 MUX
******************************************************************************/
`timescale 1ns/100ps
/*
* FUNC_NAME: MUXn_2_1
*
* DESCRIPTION:
*\tDefinition for a n-bit 2-to-1 MUX
*
* INPUT:
*\tmux_in0 - the input to be output if mux_sel is 0
* \tmux_in1 - the input to be output if mux_sel is 1
* \tmux_sel - chooses between the inputs
*
* OUTPUT:
*\tmux_out - the output of the mux
*
* ASSUMPTIONS:
*
* AUTHOR:
*\tJustin Quek
* DATE:
*\t25-apr-03
* LAST MODIFICATION:
* <modifier's name> <date modified>
*/
module MUXn_2_1(mux_in0, mux_in1, mux_sel, mux_out);
parameter MuxLen = 63;
// outputs
output [MuxLen:0] mux_out;
// inputs
input [MuxLen:0] mux_in0;
input [MuxLen:0] mux_in1;
input mux_sel;
// internal vars
// assign vars
// assing outputs
reg [MuxLen:0] mux_out;
// instantiate other modules
// code
always @(mux_in0 or mux_in1 or mux_sel)
begin
if (mux_sel == 1'b1)
mux_out = mux_in1;
else
mux_out = mux_in0;
end
endmodule // MUXn_2_1
/*
* FUNC_NAME: MUXn_4_1
*
* DESCRIPTION:
*\tDefinition for a n-bit 4-to-1 MUX
*
* INPUT:
*\tmux_in0 - the input to be output if mux_sel is 00
* \tmux_in1 - the input to be output if mux_sel is 01
*\tmux_in2 - the input to be output if mux_sel is 10
*\tmux_in3 - the input to be output if mux_sel is 11
* \tmux_sel - chooses between the inputs
*
* OUTPUT:
*\tmux_out - the output of the mux
*
* ASSUMPTIONS:
*
* AUTHOR:
*\tJustin Quek
* DATE:
*\t25-apr-03
* LAST MODIFICATION:
* <modifier's name> <date modified>
*/
module MUXn_4_1(mux_in0, mux_in1, mux_in2, mux_in3, mux_sel, mux_out);
parameter MuxLen = 63;
// outputs
output [MuxLen:0] mux_out;
// inputs
input [MuxLen:0] mux_in0;
input [MuxLen:0] mux_in1;
input [MuxLen:0] mux_in2;
input [MuxLen:0] mux_in3;
input [1:0] mux_sel;
// internal vars
wire [MuxLen:0] mux_tmp0;
wire [MuxLen:0] mux_tmp1;
// assign vars
// assing outputs
// instantiate other modules
MUXn_2_1 #(MuxLen) mux0(mux_in0, mux_in1, mux_sel[0], mux_tmp0);
MUXn_2_1 #(MuxLen) mux1(mux_in2, mux_in3, mux_sel[0], mux_tmp1);
MUXn_2_1 #(MuxLen) msel(mux_tmp0, mux_tmp1, mux_sel[1], mux_out);
// code
endmodule // MUXn_4_1
/*
* FUNC_NAME: MUXn_8_1
*
* DESCRIPTION:
*\tDefinition for a n-bit 8-to-1 MUX
*
* INPUT:
*\tmux_in0 - the input to be output if mux_sel is 000
* mux_in1 - the input to be output if mux_sel is 001
*\tmux_in2 - the input to be output if mux_sel is 010
*\tmux_in3 - the input to be output if mux_sel is 011
*\tmux_in4 - the input to be output if mux_sel is 100
*\tmux_in5 - the input to be output if mux_sel is 101
*\tmux_in6 - the input to be output if mux_sel is 110
*\tmux_in7 - the input to be output if mux_sel is 111
* \tmux_sel - chooses between the inputs
*
* OUTPUT:
*\tmux_out - the output of the mux
*
* ASSUMPTIONS:
*
* AUTHOR:
*\tJustin Quek
* DATE:
*\t25-apr-03
* LAST MODIFICATION:
* <modifier's name> <date modified>
*/
module MUXn_8_1(mux_in0, mux_in1, mux_in2, mux_in3, mux_in4, mux_in5, mux_in6, mux_in7, mux_sel, mux_out);
parameter MuxLen = 63;
// outputs
output [MuxLen:0] mux_out;
// inputs
input [MuxLen:0] mux_in0;
input [MuxLen:0] mux_in1;
input [MuxLen:0] mux_in2;
input [MuxLen:0] mux_in3;
input [MuxLen:0] mux_in4;
input [MuxLen:0] mux_in5;
input [MuxLen:0] mux_in6;
input [MuxLen:0] mux_in7;
input [2:0] mux_sel;
// internal vars
wire [MuxLen:0] mux_tmp0;
wire [MuxLen:0] mux_tmp1;
// assign vars
// assing outputs
// instantiate other modules
MUXn_4_1 #(MuxLen) mux0(mux_in0, mux_in1, mux_in2, mux_in3, mux_sel[1:0], mux_tmp0);
MUXn_4_1 #(MuxLen) mux1(mux_in4, mux_in5, mux_in6, mux_in7, mux_sel[1:0], mux_tmp1);
MUXn_2_1 #(MuxLen) msel(mux_tmp0, mux_tmp1, mux_sel[2], mux_out);
// code
endmodule // MUXn_8_1
|
/// date:2016/3/3
/// engineer:ZhaiShaoMin
/// module name:upload_fsm_datapath
/// module function:combine fsm of upload and datapath of upload
module upload_fsm_datapath(//input
clk,
rst,
v_flits_in,
out_req_fifo_rdy_in,
en_inv_ids,
inv_ids_in,
flits_max_in,
head_flit,
addrhi,
addrlo,
// datahi1,
// datalo1,
// datahi2,
// datalo2,
// datahi3,
// datalo3,
// datahi4,
// datalo4,
//output
ctrl_out,
flit_out,
fsm_state,
v_flit_to_req_fifo
);
// input
input clk;
input rst;
input v_flits_in;
input out_req_fifo_rdy_in;
input en_inv_ids;
input [3:0] inv_ids_in;
input [3:0] flits_max_in;
input [15:0] head_flit;
input [15:0] addrhi;
input [15:0] addrlo;
/*input [15:0] datahi1;
//input [15:0] datalo1;
input [15:0] datahi2;
input [15:0] datalo2;
input [15:0] datahi3;
input [15:0] datalo3;
input [15:0] datahi4;
input [15:0] datalo4;
*/
//output
output [1:0] ctrl_out;
output [15:0] flit_out;
output [1:0] fsm_state;
output v_flit_to_req_fifo;
//nets of upload_datapath output
wire [3:0] inv_ids_reg_net;
wire [1:0] sel_cnt_invs_net;
wire [15:0] flit_out_net;
wire cnt_eq_max_net;
wire cnt_invs_eq_3_net;
wire cnt_eq_0_net;
//net of fsm_upload_flit output
wire dest_sel_net;
wire clr_max_net;
wire clr_inv_ids_net;
wire clr_sel_cnt_inv_net;
wire clr_sel_cnt_net;
wire inc_sel_cnt_net;
wire inc_sel_cnt_invs_net;
wire en_flit_max_in_net;
wire en_inv_ids_net;
FSM_upload_flit req_fsm_dut (// input
.clk(clk),
.rst(rst),
.en_for_reg(v_flits_in),
.out_req_fifo_rdy(out_req_fifo_rdy_in),
.cnt_invs_eq_3(cnt_invs_eq_3_net),
.cnt_eq_max(cnt_eq_max_net),
.head_flit(head_flit),
.inv_ids_reg(inv_ids_reg_net),
.sel_cnt_invs(sel_cnt_invs_net),
.sel_cnt_eq_0(cnt_eq_0_net),
// output
.en_inv_ids(en_inv_ids_net),
.en_flit_max_in(en_flit_max_in_net),
.inc_sel_cnt_invs(inc_sel_cnt_invs_net),
.inc_sel_cnt(inc_sel_cnt_net),
.ctrl(ctrl_out),
.clr_max(clr_max_net),
.clr_inv_ids(clr_inv_ids_net),
.clr_sel_cnt_inv(clr_sel_cnt_inv_net),
.clr_sel_cnt(clr_sel_cnt_net),
.dest_sel(dest_sel_net),
.fsm_state_out(fsm_state),
.en_flit_out(v_flit_to_req_fifo)
);
upload_datapath req_datapath_dut(// input
.clk(clk),
.rst(rst),
.clr_max(clr_max_net),
.clr_inv_ids(clr_inv_ids_net),
.clr_sel_cnt_inv(clr_sel_cnt_inv_net),
.clr_sel_cnt(clr_sel_cnt_net),
.inc_sel_cnt(inc_sel_cnt_net),
.inc_sel_cnt_inv(inc_sel_cnt_invs_net),
.en_flit_max_in(en_flit_max_in_net),
.en_for_reg(v_flits_in),
.en_inv_ids(en_inv_ids_net),
.inv_ids_in(inv_ids_in),
.dest_sel(dest_sel_net),
.flit_max_in(flits_max_in),
.head_flit(head_flit),
.addrhi(addrhi),
.addrlo(addrlo),
/* .datahi1(datahi1),
.datalo1(datalo1),
.datahi2(datahi2),
.datalo2(datalo2),
.datahi3(datahi3),
.datalo3(datalo3),
.datahi4(datahi4),
.datalo4(datalo4), */
//output
.flit_out(flit_out_net),
.cnt_eq_max(cnt_eq_max_net),
.cnt_invs_eq_3(cnt_invs_eq_3_net),
.cnt_eq_0(cnt_eq_0_net),
.inv_ids_reg_out(inv_ids_reg_net),
.sel_cnt_invs_out(sel_cnt_invs_net)
);
endmodule
|
/*******************************************************************
date:2016/3/30
designer:ZhaiShaoMin
module name :tb_arbiter_for_dcache
moduel function : check errors in arbiter_for_dcache
********************************************************************/
`timescale 1ns/1ps
module tb_arbiter_for_dcache();
//input
reg clk;
reg rst;
reg dcache_done_access;
reg v_dc_download;
reg [143:0] dc_download_flits;
reg v_cpu;
reg [67:0] cpu_access_flits;
reg v_m_d_areg;
reg [143:0] m_d_areg_flits;
//output
wire [143:0] flits_dc;
wire v_flits_dc;
wire re_dc_download_flits;
wire re_cpu_access_flits;
wire re_m_d_areg_flits;
wire cpu_done_access;
wire dc_download_done_access;
wire m_d_areg_done_access;
//instante design
arbiter_for_dcache(//input
.clk(clk),
.rst(rst),
.dcache_done_access(dcache_done_access),
.v_dc_download(v_dc_download),
.dc_download_flits(dc_download_flits),
.v_cpu(v_cpu),
.cpu_access_flits(cpu_access_flits),
.v_m_d_areg(v_m_d_areg),
.m_d_areg_flits(m_d_areg_flits),
//output
.flits_dc(flits_dc),
.v_flits_dc(v_flits_dc),
.re_dc_download_flits(re_dc_download_flits),
.re_cpu_access_flits(re_cpu_access_flits),
.re_m_d_areg_flits(re_m_d_areg_flits),
.cpu_done_access(cpu_done_access),
.dc_download_done_access(dc_download_done_access),
.m_d_areg_done_access(m_d_areg_done_access)
);
integer log_file;
//initial inputs
initial
begin
clk=1\'b0;
rst=1\'b1;
dcache_done_access=1\'b0;
v_dc_download=1\'b0;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b0;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b0;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
log_file=$fopen("log_arbiter_for_dcache");
end
`define clk_step #14;
always #7 clk=~clk;
//////////////////////////////////////////////////////////////
////////////////BEGIN TEST!///////////////////////////////////
initial begin
`clk_step
$display("begin test!");
$fdisplay("begin test!");
rst=1\'b1;
/////////////////////////////////////////////////
///////////////first case: all valid ///////////
//// m_d_flits win,due to priority3 was reset to 3\'b001!
`clk_step
dcache_done_access=1\'b0;
v_dc_download=1\'b1;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b1;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b1;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1\'b0;
v_dc_download=1\'b1;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b1;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b1;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1\'b0;
v_dc_download=1\'b1;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b1;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b1;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
///dcache has processed m_d_flits ,due to RR it will be turn of cpu access
`clk_step
dcache_done_access=1\'b1;
v_dc_download=1\'b1;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b1;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b1;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1\'b0;
v_dc_download=1\'b1;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b1;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b1;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1\'b0;
v_dc_download=1\'b1;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b1;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b1;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
//dcache has processed dc_download flits, due to RR now it\'s turn of dc_download
`clk_step
dcache_done_access=1\'b1;
v_dc_download=1\'b1;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b1;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b1;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1\'b0;
v_dc_download=1\'b1;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b1;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b1;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1\'b0;
v_dc_download=1\'b1;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b1;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b1;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1\'b1;
v_dc_download=1\'b1;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b1;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b1;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
//////////////////////////////////////////////////////////////////////
///////////2nd case:both cpu access and dc_download flit are valid////
///////turn of cpu due to RR
`clk_step
dcache_done_access=1\'b0;
v_dc_download=1\'b1;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b1;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b0;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1\'b0;
v_dc_download=1\'b1;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b1;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b0;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1\'b1;
v_dc_download=1\'b1;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b1;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b0;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
///turn of dc access
`clk_step
dcache_done_access=1\'b0;
v_dc_download=1\'b1;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b1;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b0;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1\'b0;
v_dc_download=1\'b1;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b1;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b0;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1\'b1;
v_dc_download=1\'b1;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b1;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b0;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
//////////////////////////////////////////////////////////////////
////////3rd case: cpu and mem valid///////////////////////////////
///////turn of mem due to RR
`clk_step
dcache_done_access=1\'b0;
v_dc_download=1\'b0;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b1;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b1;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1\'b0;
v_dc_download=1\'b0;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b1;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b1;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1\'b1;
v_dc_download=1\'b0;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b1;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b1;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
///turn of cpu access
`clk_step
dcache_done_access=1\'b0;
v_dc_download=1\'b1;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b1;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b0;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1\'b0;
v_dc_download=1\'b1;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b1;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b0;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1\'b1;
v_dc_download=1\'b1;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b1;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b0;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
/////////////////////////////////////////////////////////////////
///////// 4th case: dc and mem are valid/////////////////////////
/// turn of mem
`clk_step
dcache_done_access=1\'b0;
v_dc_download=1\'b1;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b0;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b1;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1\'b0;
v_dc_download=1\'b1;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b0;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b1;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1\'b1;
v_dc_download=1\'b1;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b0;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b1;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
///turn of dc access
`clk_step
dcache_done_access=1\'b0;
v_dc_download=1\'b1;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b0;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b1;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1\'b0;
v_dc_download=1\'b1;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b0;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b1;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1\'b1;
v_dc_download=1\'b1;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b0;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b1;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
//////////////////////////////////////////////////////////////////
/////////5th case :only dc valid//////////////////////////////////
///turn of dc access
`clk_step
dcache_done_access=1\'b0;
v_dc_download=1\'b1;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b0;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b0;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1\'b0;
v_dc_download=1\'b1;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b0;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b0;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1\'b1;
v_dc_download=1\'b1;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b0;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b0;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
/////////////////////////////////////////////////////////////////
/////////6th case: only cpu valid////////////////////////////////
///turn of dc access
`clk_step
dcache_done_access=1\'b0;
v_dc_download=1\'b0;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b1;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b0;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1\'b0;
v_dc_download=1\'b0;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b1;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b0;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1\'b1;
v_dc_download=1\'b0;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b1;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b0;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
/////////////////////////////////////////////////////////
///////////////////7th case :only mem valid//////////////
///turn of dc access
`clk_step
dcache_done_access=1\'b0;
v_dc_download=1\'b0;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b0;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b1;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1\'b0;
v_dc_download=1\'b0;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b0;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b1;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1\'b1;
v_dc_download=1\'b0;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b0;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b1;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
////////////////////////////////////////////////////////////
//////////////8th case: nothing comes //////////////////////
///turn of dc access
`clk_step
dcache_done_access=1\'b0;
v_dc_download=1\'b0;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b0;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b0;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1\'b0;
v_dc_download=1\'b0;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b0;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b0;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1\'b1;
v_dc_download=1\'b0;
dc_download_flits=144\'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1\'b0;
cpu_access_flits=68\'h01234c0de5678c0de;
v_m_d_areg=1\'b0;
m_d_areg_flits=144\'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
$display("FINISH TEST!");
$fdisplay(log_file,"FINISH TEST!");
end
endmodule
|
//==================================================================================================
// Filename : antares_divider.v
// Created On : Thu Sep 3 08:41:07 2015
// Last Modified : Sat Nov 07 12:01:42 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Sim\xc3\xb3n Bol\xc3\xadvar
// Email : [email protected]
//
// Description : A multi-cycle divider unit.
// op_div and op_divu MUST BE dis-asserted after the setup
// cycle for normal operation, or the operation will be restarted.
// WARNING: no exception if divisor == 0.
//==================================================================================================
module antares_divider (
input clk,
input rst,
input op_divs,
input op_divu,
input [31:0] dividend,
input [31:0] divisor,
output [31:0] quotient,
output [31:0] remainder,
output div_stall
);
//--------------------------------------------------------------------------
// Signal Declaration: reg
//--------------------------------------------------------------------------
reg active; // 1 while running
reg neg_result; // 1 if the result must be negative
reg neg_remainder; // 1 if the remainder must be negative
reg [4:0] cycle; // number of cycles needed.
reg [31:0] result; // Store the result.
reg [31:0] denominator; // divisor
reg [31:0] residual; // current remainder
//--------------------------------------------------------------------------
// Signal Declaration: wire
//--------------------------------------------------------------------------
wire [32:0] partial_sub; // temp
//--------------------------------------------------------------------------
// assignments
//--------------------------------------------------------------------------
assign quotient = !neg_result ? result : -result;
assign remainder = !neg_remainder ? residual : -residual;
assign div_stall = active;
assign partial_sub = {residual[30:0], result[31]} - denominator; // calculate partial result
//--------------------------------------------------------------------------
// State Machine. This needs 32 cycles to calculate the result.
// The result is loaded after 34 cycles
// The first cycle is setup.
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
active <= 1'h0;
cycle <= 5'h0;
denominator <= 32'h0;
neg_result <= 1'h0;
neg_remainder <= 1'h0;
residual <= 32'h0;
result <= 32'h0;
// End of automatics
end
else begin
if(op_divs) begin
// Signed division.
cycle <= 5'd31;
result <= (dividend[31] == 1'b0) ? dividend : -dividend;
denominator <= (divisor[31] == 1'b0) ? divisor : -divisor;
residual <= 32'b0;
neg_result <= dividend[31] ^ divisor[31];
neg_remainder <= dividend[31];
active <= 1'b1;
end
else if (op_divu) begin
// Unsigned division.
cycle <= 5'd31;
result <= dividend;
denominator <= divisor;
residual <= 32'b0;
neg_result <= 1'b0;
neg_remainder <= 1'h0;
active <= 1'b1;
end
else if (active) begin
// run a iteration
if(partial_sub[32] == 1'b0) begin
residual <= partial_sub[31:0];
result <= {result[30:0], 1'b1};
end
else begin
residual <= {residual[30:0], result[31]};
result <= {result[30:0], 1'b0};
end
if (cycle == 5'b0) begin
active <= 1'b0;
end
cycle <= cycle - 5'd1;
end
end
end
endmodule // antares_divider
|
//==================================================================================================
// Filename : antares_mux_4_1.v
// Created On : Mon Aug 31 23:14:22 2015
// Last Modified : Sat Nov 07 12:14:18 2015
// Revision : 0.1
// Author : Angel Terrones
// Company : Universidad Sim\xc3\xb3n Bol\xc3\xadvar
// Email : [email protected]
//
// Description : A 4-input multiplexer, with parameterizable width.
//==================================================================================================
module antares_mux_4_1 #(parameter WIDTH = 32)
(
input [1:0] select,
input [WIDTH-1:0] in0,
input [WIDTH-1:0] in1,
input [WIDTH-1:0] in2,
input [WIDTH-1:0] in3,
output reg [WIDTH-1:0] out
);
always @ ( /*AUTOSENSE*/in0 or in1 or in2 or in3 or select) begin
case (select)
2'b00: out = in0;
2'b01: out = in1;
2'b10: out = in2;
2'b11: out = in3;
endcase // case (select)
end // always @ (...
endmodule // antares_mux_4_1
|
//==================================================================================================
// Filename : antares_pc_register.v
// Created On : Tue Sep 1 10:21:01 2015
// Last Modified : Sat Nov 07 12:14:50 2015
// Revision : 0.1
// Author : Angel Terrones
// Company : Universidad Sim\xc3\xb3n Bol\xc3\xadvar
// Email : [email protected]
//
// Description : Program Counter (PC)
//==================================================================================================
`include "antares_defines.v"
module antares_pc_register (
input clk,
input rst,
input [31:0] if_new_pc,
input if_stall,
output reg [31:0] if_pc
);
always @ ( posedge clk ) begin
if_pc <= (rst) ? `ANTARES_VECTOR_BASE_RESET : ((if_stall) ? if_pc : if_new_pc);
end
endmodule // antares_pc_register
|
//==================================================================================================
// Filename : antares_control_unit.v
// Created On : Fri Sep 4 11:55:21 2015
// Last Modified : Sat Nov 07 11:53:12 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Sim\xc3\xb3n Bol\xc3\xadvar
// Email : [email protected]
//
// Description : Instruction decode and control unit (no pipeline control)
//==================================================================================================
`include "antares_defines.v"
module antares_control_unit #(parameter ENABLE_HW_MULT = 1, // Enable multiply instructions
parameter ENABLE_HW_DIV = 1, // Enable div instructions
parameter ENABLE_HW_CLOZ = 1 // Enable CL=/CLZ instructions
)(
input [5:0] opcode, // The instruction opcode
input [5:0] op_function, // For RR-type instruction
input [4:0] op_rs, // For mtc0 and mfc0 instructions
input [4:0] op_rt, // For branch instructions
output [7:0] dp_hazard,
output id_imm_sign_ext, // sign extend the imm16
output id_movn, // MOVN instruction
output id_movz, // MOVZ instruction
output id_llsc, // LL/SC instructions
output id_syscall, // Syscall exception
output id_breakpoint, // Breakpoint exception
output id_reserved, // Reserved instruction exception
output id_mfc0, // Coprocessor 0 instruction
output id_mtc0, // Coprocessor 0 instruction
output id_eret, // Coprocessor 0 instruction
output id_cp1_instruction, // Coprocessor 1 instruction
output id_cp2_instruction, // Coprocessor 2 instruction
output id_cp3_instruction, // Coprocessor 3 instruction
output id_id_exception_source, // Instruction is a potential source of exception
output id_ex_exception_source, // Instruction is a potential source of exception
output id_mem_exception_source, // Instruction is a potential source of exception
output id_trap, // Trap instruction
output id_trap_condition, // Trap condition
output id_gpr_we, // write data from WB stage, to GPR
output id_mem_to_gpr_select, // Select GPR write data: MEM or ALU
output [4:0] id_alu_operation, // ALU function
output [1:0] id_alu_port_a_select, // Shift, jump and link
output [1:0] id_alu_port_b_select, // R-instruction, I-instruction or jump
output [1:0] id_gpr_wa_select, // Select GPR write address
output id_jump, // Jump instruction
output id_branch, // Branch instruction
output id_mem_write, // Write to Memory: 0 = read, 1 = write.
output id_mem_byte, // Read/Write one byte
output id_mem_halfword, // Read/Write halfword (16 bits )
output id_mem_data_sign_ext // Sign extend for byte/halfword memory operations
);
//--------------------------------------------------------------------------
// Signal Declaration: reg
//--------------------------------------------------------------------------
reg [31:0] datapath; // all control signals
//--------------------------------------------------------------------------
// Signal Declaration: wires
//--------------------------------------------------------------------------
wire no_mult;
wire no_div;
wire no_clo_clz;
//--------------------------------------------------------------------------
// assigments
//--------------------------------------------------------------------------
assign id_imm_sign_ext = (opcode != `OP_ANDI) & (opcode != `OP_ORI) & (opcode != `OP_XORI);
assign id_movn = (opcode == `OP_TYPE_R) & (op_function == `FUNCTION_OP_MOVN);
assign id_movz = (opcode == `OP_TYPE_R) & (op_function == `FUNCTION_OP_MOVZ);
assign id_llsc = (opcode == `OP_LL) | (opcode == `OP_SC);
assign id_syscall = (opcode == `OP_TYPE_R) & (op_function == `FUNCTION_OP_SYSCALL);
assign id_breakpoint = (opcode == `OP_TYPE_R) & (op_function == `FUNCTION_OP_BREAK);
assign id_mfc0 = (opcode == `OP_TYPE_CP0) & (op_rs == `RS_OP_MFC);
assign id_mtc0 = (opcode == `OP_TYPE_CP0) & (op_rs == `RS_OP_MTC);
assign id_eret = (opcode == `OP_TYPE_CP0) & (op_rs == `RS_OP_ERET) & (op_function == `FUNCTION_OP_ERET);
assign id_cp1_instruction = (opcode == `OP_TYPE_CP1);
assign id_cp2_instruction = (opcode == `OP_TYPE_CP2);
assign id_cp3_instruction = (opcode == `OP_TYPE_CP3);
assign id_reserved = no_mult | no_div | no_clo_clz;
//--------------------------------------------------------------------------
// Check for mult instructions
//--------------------------------------------------------------------------
generate
if(ENABLE_HW_MULT) begin
assign no_mult = 1\'b0;
end
else begin
assign no_mult = ((datapath[20:16] == `ALU_OP_MADD) | (datapath[20:16] == `ALU_OP_MADDU) |
(datapath[20:16] == `ALU_OP_MSUB) | (datapath[20:16] == `ALU_OP_MSUBU) |
(datapath[20:16] == `ALU_OP_MULS) | (datapath[20:16] == `ALU_OP_MULU));
end
endgenerate
//--------------------------------------------------------------------------
// Check for div instructions
//--------------------------------------------------------------------------
generate
if(ENABLE_HW_DIV) begin
assign no_div = 1\'b0;
end
else begin
assign no_div = ((datapath[20:16] == `ALU_OP_DIV) | (datapath[20:16] == `ALU_OP_DIVU));
end
endgenerate
//--------------------------------------------------------------------------
// Check for CL0/CLZ instructions
//--------------------------------------------------------------------------
generate
if(ENABLE_HW_CLOZ) begin
assign no_clo_clz = 1\'b0;
end
else begin
assign no_clo_clz = ((datapath[20:16] == `ALU_OP_CLO) | (datapath[20:16] == `ALU_OP_CLZ));
end
endgenerate
/*
Datapath controls.
All signals are active High.
----------------------------------------------------------------------------
Bit Name Description
----------------------------------------------------------------------------
31 : Wants Rs by ID
30 : Needs Rs by ID
29 : Wants Rt by ID
28 : Needs Rt by ID
27 : Wants Rs by EX
26 : Needs Rs by EX
25 : Wants Rt by EX
24 : Needs Rt by EX
-------------------------------
23 : id_id_exception_source Instruction can cause exception @ ID
22 : id_ex_exception_source Instruction can cause exception @ EX
21 : id_mem_exception_source Instruction can cause exception @ MEM
-------------------------------
20 : id_alu_operation Operation to execute.
19 : .
18 : .
17 : .
16 : .
-------------------------------
15: id_trap Trap instruction
14: id_trap_condition Condition: ALU result = 0 (0), ALU result != 0 (1)
-------------------------------
13 : id_gpr_we Write enable (GPR)
12 : id_mem_to_gpr_select Select data: ALU(0), MEM(1)
-------------------------------
11 : id_alu_port_a_select Select: Rs(0), shamt(1), 0x04(2), 0x10(3)
10 : .
9 : id_alu_port_b_select Select: Rt(0), SImm16(1), PCAdd4(2), ZImm16(3)
8 : .
7 : id_gpr_wa_select Select register: Rd(0), Rt(1), 31(2)
6 : .
-------------------------------
5 : id_jump Jump instruction
4 : id_branch Branch instruction
-------------------------------
3 : id_mem_write Write to data memory
2 : id_mem_byte Enable read/write one byte
1 : id_mem_halfword Enable read/write 2 bytes (16 bits data)
0 : id_mem_data_sign_ext Zero extend data (0) or Sign extend data (1)
----------------------------------------------------------------------------
*/
assign dp_hazard = datapath[31:24];
assign id_id_exception_source = datapath[23];
assign id_ex_exception_source = datapath[22];
assign id_mem_exception_source = datapath[21];
assign id_alu_operation = datapath[20:16];
assign id_trap = datapath[15];
assign id_trap_condition = datapath[14];
assign id_gpr_we = datapath[13];
assign id_mem_to_gpr_select = datapath[12];
assign id_alu_port_a_select = datapath[11:10];
assign id_alu_port_b_select = datapath[9:8];
assign id_gpr_wa_select = datapath[7:6];
assign id_jump = datapath[5];
assign id_branch = datapath[4];
assign id_mem_write = datapath[3];
assign id_mem_byte = datapath[2];
assign id_mem_halfword = datapath[1];
assign id_mem_data_sign_ext = datapath[0];
//--------------------------------------------------------------------------
// set the control signals
//--------------------------------------------------------------------------
always @(*) begin
case(opcode)
`OP_TYPE_R : begin
case (op_function)
`FUNCTION_OP_ADD : begin datapath = `DP_ADD; end
`FUNCTION_OP_ADDU : begin datapath = `DP_ADDU; end
`FUNCTION_OP_AND : begin datapath = `DP_AND; end
`FUNCTION_OP_BREAK : begin datapath = `DP_BREAK; end
`FUNCTION_OP_DIV : begin datapath = `DP_DIV; end
`FUNCTION_OP_DIVU : begin datapath = `DP_DIVU; end
`FUNCTION_OP_JALR : begin datapath = `DP_JALR; end
`FUNCTION_OP_JR : begin datapath = `DP_JR; end
`FUNCTION_OP_MFHI : begin datapath = `DP_MFHI; end
`FUNCTION_OP_MFLO : begin datapath = `DP_MFLO; end
`FUNCTION_OP_MOVN : begin datapath = `DP_MOVN; end
`FUNCTION_OP_MOVZ : begin datapath = `DP_MOVZ; end
`FUNCTION_OP_MTHI : begin datapath = `DP_MTHI; end
`FUNCTION_OP_MTLO : begin datapath = `DP_MTLO; end
`FUNCTION_OP_MULT : begin datapath = `DP_MULT; end
`FUNCTION_OP_MULTU : begin datapath = `DP_MULTU; end
`FUNCTION_OP_NOR : begin datapath = `DP_NOR; end
`FUNCTION_OP_OR : begin datapath = `DP_OR; end
`FUNCTION_OP_SLL : begin datapath = `DP_SLL; end
`FUNCTION_OP_SLLV : begin datapath = `DP_SLLV; end
`FUNCTION_OP_SLT : begin datapath = `DP_SLT; end
`FUNCTION_OP_SLTU : begin datapath = `DP_SLTU; end
`FUNCTION_OP_SRA : begin datapath = `DP_SRA; end
`FUNCTION_OP_SRAV : begin datapath = `DP_SRAV; end
`FUNCTION_OP_SRL : begin datapath = `DP_SRL; end
`FUNCTION_OP_SRLV : begin datapath = `DP_SRLV; end
`FUNCTION_OP_SUB : begin datapath = `DP_SUB; end
`FUNCTION_OP_SUBU : begin datapath = `DP_SUBU; end
`FUNCTION_OP_SYSCALL : begin datapath = `DP_SYSCALL; end
`FUNCTION_OP_TEQ : begin datapath = `DP_TEQ; end
`FUNCTION_OP_TGE : begin datapath = `DP_TGE; end
`FUNCTION_OP_TGEU : begin datapath = `DP_TGEU; end
`FUNCTION_OP_TLT : begin datapath = `DP_TLT; end
`FUNCTION_OP_TLTU : begin datapath = `DP_TLTU; end
`FUNCTION_OP_TNE : begin datapath = `DP_TNE; end
`FUNCTION_OP_XOR : begin datapath = `DP_XOR; end
default : begin datapath = `DP_NONE; end
endcase // case (op_function)
end // case: `OP_TYPE_R
`OP_TYPE_R2 : begin
case (op_function)
`FUNCTION_OP_CLO : begin datapath = `DP_CLO; end
`FUNCTION_OP_CLZ : begin datapath = `DP_CLZ; end
`FUNCTION_OP_MADD : begin datapath = `DP_MADD; end
`FUNCTION_OP_MADDU : begin datapath = `DP_MADDU; end
`FUNCTION_OP_MSUB : begin datapath = `DP_MSUB; end
`FUNCTION_OP_MSUBU : begin datapath = `DP_MSUBU; end
default : begin datapath = `DP_NONE; end
endcase // case (op_function)
end // case: `OP_TYPE_R2
`OP_TYPE_REGIMM : begin
case (op_rt)
`RT_OP_BGEZ : begin datapath = `DP_BGEZ; end
`RT_OP_BGEZAL : begin datapath = `DP_BGEZAL; end
`RT_OP_BLTZ : begin datapath = `DP_BLTZ; end
`RT_OP_BLTZAL : begin datapath = `DP_BLTZAL; end
`RT_OP_TEQI : begin datapath = `DP_TEQI; end
`RT_OP_TGEI : begin datapath = `DP_TGEI; end
`RT_OP_TGEIU : begin datapath = `DP_TGEIU; end
`RT_OP_TLTI : begin datapath = `DP_TLTI; end
`RT_OP_TLTIU : begin datapath = `DP_TLTIU; end
`RT_OP_TNEI : begin datapath = `DP_TNEI; end
default : begin datapath = `DP_NONE; end
endcase // case (op_rt)
end // case: `OP_TYPE_REGIMM
`OP_TYPE_CP0 : begin
case (op_rs)
`RS_OP_MFC : begin datapath = `DP_MFC0; end
`RS_OP_MTC : begin datapath = `DP_MTC0; end
`RS_OP_ERET : begin datapath = `DP_ERET; end
default : begin datapath = `DP_NONE; end
endcase // case (op_rs)
end
`OP_ADDI : begin datapath = `DP_ADDI; end
`OP_ADDIU : begin datapath = `DP_ADDIU; end
`OP_ANDI : begin datapath = `DP_ANDI; end
`OP_BEQ : begin datapath = `DP_BEQ; end
`OP_BGTZ : begin datapath = `DP_BGTZ; end
`OP_BLEZ : begin datapath = `DP_BLEZ; end
`OP_BNE : begin datapath = `DP_BNE; end
`OP_J : begin datapath = `DP_J; end
`OP_JAL : begin datapath = `DP_JAL; end
`OP_LB : begin datapath = `DP_LB; end
`OP_LBU : begin datapath = `DP_LBU; end
`OP_LH : begin datapath = `DP_LH; end
`OP_LHU : begin datapath = `DP_LHU; end
`OP_LL : begin datapath = `DP_LL; end
`OP_LUI : begin datapath = `DP_LUI; end
`OP_LW : begin datapath = `DP_LW; end
`OP_ORI : begin datapath = `DP_ORI; end
`OP_SB : begin datapath = `DP_SB; end
`OP_SC : begin datapath = `DP_SC; end
`OP_SH : begin datapath = `DP_SH; end
`OP_SLTI : begin datapath = `DP_SLTI; end
`OP_SLTIU : begin datapath = `DP_SLTIU; end
`OP_SW : begin datapath = `DP_SW; end
`OP_XORI : begin datapath = `DP_XORI; end
default : begin datapath = `DP_NONE; end
endcase // case (opcode)
end // always @ (*)
endmodule // antares_control_unit
|
//==================================================================================================
// Filename : antares_memwb_register.v
// Created On : Sat Sep 5 21:41:57 2015
// Last Modified : Sat Nov 07 12:10:59 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Sim\xc3\xb3n Bol\xc3\xadvar
// Email : [email protected]
//
// Description : Pipeline register: MEM -> WB
//==================================================================================================
module antares_memwb_register (
input clk, // main clock
input rst, // main reset
input [31:0] mem_read_data, // data from Memory
input [31:0] mem_alu_data, // data from ALU
input [4:0] mem_gpr_wa, // GPR write enable
input mem_mem_to_gpr_select, // select MEM/ALU to GPR
input mem_gpr_we, // GPR write enable
input mem_flush,
input mem_stall, // stall MEM stage
input wb_stall, // stall WB stage
output reg [31:0] wb_read_data, // data from Memory
output reg [31:0] wb_alu_data, // data from ALU
output reg [4:0] wb_gpr_wa, // GPR write address
output reg wb_mem_to_gpr_select, // select MEM/ALU to GPR
output reg wb_gpr_we // GPR write enable
);
//--------------------------------------------------------------------------
// Propagate signals
//--------------------------------------------------------------------------
always @(posedge clk) begin
wb_read_data <= (rst) ? 32'b0 : ((wb_stall) ? wb_read_data : mem_read_data);
wb_alu_data <= (rst) ? 32'b0 : ((wb_stall) ? wb_alu_data : mem_alu_data);
wb_gpr_wa <= (rst) ? 5'b0 : ((wb_stall) ? wb_gpr_wa : mem_gpr_wa);
wb_mem_to_gpr_select <= (rst) ? 1'b0 : ((wb_stall) ? wb_mem_to_gpr_select : mem_mem_to_gpr_select);
wb_gpr_we <= (rst) ? 1'b0 : ((wb_stall) ? wb_gpr_we : ((mem_stall | mem_flush) ? 1'b0 : mem_gpr_we));
end
endmodule // antares_memwb_register
|
//==================================================================================================
// Filename : antares_exmem_register.v
// Created On : Sat Sep 5 21:23:28 2015
// Last Modified : Sat Nov 07 12:04:18 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Sim\xc3\xb3n Bol\xc3\xadvar
// Email : [email protected]
//
// Description : Pipeline register: EX -> MEM
//==================================================================================================
module antares_exmem_register (
input clk, // main clock
input rst, // main reset
input [31:0] ex_alu_result, // ALU result
input [31:0] ex_mem_store_data, // data to memory
input [4:0] ex_gpr_wa, // GPR write address
input ex_gpr_we, // GPR write enable
input ex_mem_to_gpr_select, // Select MEM/ALU to GPR
input ex_mem_write, // Mem write operation
input ex_mem_byte, // byte access
input ex_mem_halfword, // halfword access
input ex_mem_data_sign_ext, // Sign/Zero extend data from memory
input [31:0] ex_exception_pc,
input ex_movn,
input ex_movz,
input ex_b_is_zero,
input ex_llsc,
input ex_kernel_mode,
input ex_is_bds,
input ex_trap,
input ex_trap_condition,
input ex_mem_exception_source, //
input ex_flush, // clean
input ex_stall, // stall EX stage
input mem_stall, // stall MEM stage
output reg [31:0] mem_alu_result, // Same signals, but on mem stage
output reg [31:0] mem_mem_store_data, //
output reg [4:0] mem_gpr_wa, //
output reg mem_gpr_we, //
output reg mem_mem_to_gpr_select, //
output reg mem_mem_write, //
output reg mem_mem_byte, //
output reg mem_mem_halfword, //
output reg mem_mem_data_sign_ext, //
output reg [31:0] mem_exception_pc,
output reg mem_llsc,
output reg mem_kernel_mode,
output reg mem_is_bds,
output reg mem_trap,
output reg mem_trap_condition,
output reg mem_mem_exception_source
);
// Check for MOVN or MOVZ instruction
wire mov_reg_write = (ex_movn & ~ex_b_is_zero) | (ex_movz & ex_b_is_zero);
//--------------------------------------------------------------------------
// Propagate signals
// Clear WE and Write signals only, on EX stall.
//--------------------------------------------------------------------------
always @(posedge clk) begin
mem_alu_result <= (rst) ? 32'b0 : ((mem_stall) ? mem_alu_result : ex_alu_result);
mem_mem_store_data <= (rst) ? 32'b0 : ((mem_stall) ? mem_mem_store_data : ex_mem_store_data);
mem_gpr_wa <= (rst) ? 5'b0 : ((mem_stall) ? mem_gpr_wa : ex_gpr_wa);
mem_gpr_we <= (rst) ? 1'b0 : ((mem_stall) ? mem_gpr_we : ((ex_stall | ex_flush) ? 1'b0 : ((ex_movz | ex_movn) ? mov_reg_write : ex_gpr_we)));
mem_mem_to_gpr_select <= (rst) ? 1'b0 : ((mem_stall) ? mem_mem_to_gpr_select : ((ex_stall | ex_flush) ? 1'b0 : ex_mem_to_gpr_select)); // test
mem_mem_write <= (rst) ? 1'b0 : ((mem_stall) ? mem_mem_write : ((ex_stall | ex_flush) ? 1'b0 : ex_mem_write));
mem_mem_byte <= (rst) ? 1'b0 : ((mem_stall) ? mem_mem_byte : ex_mem_byte);
mem_mem_halfword <= (rst) ? 1'b0 : ((mem_stall) ? mem_mem_halfword : ex_mem_halfword);
mem_mem_data_sign_ext <= (rst) ? 1'b0 : ((mem_stall) ? mem_mem_data_sign_ext : ex_mem_data_sign_ext);
mem_exception_pc <= (rst) ? 32'b0 : ((mem_stall) ? mem_exception_pc : ex_exception_pc);
mem_llsc <= (rst) ? 1'b0 : ((mem_stall) ? mem_llsc : ex_llsc);
mem_kernel_mode <= (rst) ? 1'b0 : ((mem_stall) ? mem_kernel_mode : ex_kernel_mode);
mem_is_bds <= (rst) ? 1'b0 : ((mem_stall) ? mem_is_bds : ex_is_bds);
mem_trap <= (rst) ? 1'b0 : ((mem_stall) ? mem_trap : ((ex_stall | ex_flush) ? 1'b0 : ex_trap));
mem_trap_condition <= (rst) ? 1'b0 : ((mem_stall) ? mem_trap_condition : ex_trap_condition);
mem_mem_exception_source <= (rst) ? 1'b0 : ((mem_stall) ? mem_mem_exception_source : ((ex_stall | ex_flush) ? 1'b0 : ex_mem_exception_source));
end // always @ (posedge clk)
endmodule // antares_exmem_register
|
//==================================================================================================
// Filename : antares_branch_unit.v
// Created On : Fri Sep 4 21:35:54 2015
// Last Modified : Sat Nov 07 11:49:10 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Sim\xc3\xb3n Bol\xc3\xadvar
// Email : [email protected]
//
// Description : Branch target calculation
//==================================================================================================
`include "antares_defines.v"
module antares_branch_unit (
input [5:0] opcode, // Instruction opcode
input [31:0] id_pc_add4, // Instruction address + 4
input [31:0] id_data_rs, // Data from R0
input [31:0] id_data_rt, // Data from R1
input [25:0] op_imm26, // imm21/Imm16
output reg [31:0] pc_branch_address, // Destination address
output reg id_take_branch // Valid branch
) ;
//--------------------------------------------------------------------------
// Signal Declaration: wire
//--------------------------------------------------------------------------
wire beq;
wire bne;
wire bgez;
wire bgtz;
wire blez;
wire bltz;
wire [31:0] long_jump;
wire [31:0] short_jump;
wire [5:0] inst_function;
wire [4:0] op_rt;
//--------------------------------------------------------------------------
// assignments
//--------------------------------------------------------------------------
assign beq = id_data_rs == id_data_rt;
assign bne = ~beq;
assign bgez = ~bltz;
assign bgtz = ~blez;
assign blez = bltz | ~(|id_data_rs);
assign bltz = id_data_rs[31];
assign long_jump = {id_pc_add4[31:28], op_imm26, 2\'b00 };
assign short_jump = $signed(id_pc_add4) + $signed( { {14{op_imm26[15]}}, op_imm26[`ANTARES_INSTR_IMM16], 2\'b00 } );
assign inst_function = op_imm26[`ANTARES_INSTR_FUNCT];
assign op_rt = op_imm26[`ANTARES_INSTR_RT];
//--------------------------------------------------------------------------
// Get branch address
//--------------------------------------------------------------------------
always @(*) begin
case (opcode)
`OP_BEQ : begin pc_branch_address = short_jump; id_take_branch = beq; end
`OP_BGTZ : begin pc_branch_address = short_jump; id_take_branch = bgtz; end
`OP_BLEZ : begin pc_branch_address = short_jump; id_take_branch = blez; end
`OP_BNE : begin pc_branch_address = short_jump; id_take_branch = bne; end
`OP_J : begin pc_branch_address = long_jump; id_take_branch = 1\'b1; end
`OP_JAL : begin pc_branch_address = long_jump; id_take_branch = 1\'b1; end
`OP_TYPE_REGIMM : begin
case (op_rt)
`RT_OP_BGEZ : begin pc_branch_address = short_jump; id_take_branch = bgez; end
`RT_OP_BGEZAL : begin pc_branch_address = short_jump; id_take_branch = bgez; end
`RT_OP_BLTZ : begin pc_branch_address = short_jump; id_take_branch = bltz; end
`RT_OP_BLTZAL : begin pc_branch_address = short_jump; id_take_branch = bltz; end
default : begin pc_branch_address = 32\'bx; id_take_branch = 1\'b0; end
endcase // case (op_rt)
end
`OP_TYPE_R : begin
case(inst_function)
`FUNCTION_OP_JALR : begin pc_branch_address = id_data_rs; id_take_branch = 1\'b1; end
`FUNCTION_OP_JR : begin pc_branch_address = id_data_rs; id_take_branch = 1\'b1; end
default : begin pc_branch_address = 32\'bx; id_take_branch = 1\'b0; end
endcase // case (inst_function)
end
default : begin pc_branch_address = 32\'bx; id_take_branch = 1\'b0; end
endcase // case (opcode)
end // always @ (*)
endmodule // antares_branch_unit
|
//==================================================================================================
// Filename : antares_ifid_register.v
// Created On : Sat Sep 5 21:00:32 2015
// Last Modified : Sat Nov 07 12:08:03 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Sim\xc3\xb3n Bol\xc3\xadvar
// Email : [email protected]
//
// Description : Pipeline register: IF -> ID
//==================================================================================================
module antares_ifid_register (
input clk, // main clock
input rst, // main reset
input [31:0] if_instruction, // Instruction from IF
input [31:0] if_pc_add4, // PC + 1 from IF
input [31:0] if_exception_pc, // PC from IF
input if_is_bds, // This instruction is a BDS.
input if_flush, // clean
input if_stall, // Stall IF
input id_stall, // Stall ID
output reg [31:0] id_instruction, // ID instruction
output reg [31:0] id_pc_add4, // PC + 1 to ID
output reg [31:0] id_exception_pc, // PC to ID
output reg id_is_bds, // Instruction is a BDS
output reg id_is_flushed // This instruction must be ignored
);
always @(posedge clk) begin
id_instruction <= (rst) ? 32'b0 : ((id_stall) ? id_instruction : ((if_stall | if_flush) ? 32'b0 : if_instruction));
id_pc_add4 <= (rst) ? 32'b0 : ((id_stall) ? id_pc_add4 : if_pc_add4);
id_exception_pc <= (rst) ? 32'b0 : ((id_stall) ? id_exception_pc : if_exception_pc);
id_is_bds <= (rst) ? 1'b0 : ((id_stall) ? id_is_bds : if_is_bds);
id_is_flushed <= (rst) ? 1'b0 : ((id_stall) ? id_is_flushed : if_flush);
end
endmodule // antares_ifid_register
|
//==================================================================================================
// Filename : antares_defines.v
// Created On : Mon Aug 31 19:32:04 2015
// Last Modified : Sun Sep 06 11:09:43 2015
// Revision : 0.1
// Author : Angel Terrones
// Company : Universidad Sim\xc3\xb3n Bol\xc3\xadvar
// Email : [email protected]
//
// Description : Opcodes and processor configuration
//==================================================================================================
//------------------------------------------------------------------------------
// Virtual/Physical Space
// No MMU, so VA = PA.
// First 0.5 GB: Kernel space
// Last 3.5 GB: User space
//
// WARNING: The address space is different to Standard MIPS
//------------------------------------------------------------------------------
`define ANTARES_SEG_0_SPACE_LOW 32'h0000_0000 // 256 MB: Internal Memory
`define ANTARES_SEG_0_SPACE_HIGH 32'h0FFF_FFFF
`define ANTARES_SEG_1_SPACE_LOW 32'h1000_0000 // 256 MB: I/O
`define ANTARES_SEG_1_SPACE_HIGH 32'h1FFF_FFFF
`define ANTARES_SEG_2_SPACE_LOW 32'h2000_0000 // 3.5 GB: External Memory
`define ANTARES_SEG_3_SPACE_HIGH 32'hFFFF_FFFF
//------------------------------------------------------------------------------
// Endianess
// 0 -> little-endian. 1 -> big-endian
//------------------------------------------------------------------------------
`define ANTARES_LITTLE_ENDIAN 0 //
`define ANTARES_BIG_ENDIAN 1 //
//------------------------------------------------------------------------------
// Exception Vector
//------------------------------------------------------------------------------
`define ANTARES_VECTOR_BASE_RESET 32'h0000_0010 // MIPS Standard is 0xBFC0_0000. Reset, soft-reset, NMI
`define ANTARES_VECTOR_BASE_BOOT 32'h0000_0000 // MIPS Standard is 0xBFC0_0200. Bootstrap (Status_BEV = 1)
`define ANTARES_VECTOR_BASE_NO_BOOT 32'h0000_0000 // MIPS Standard is 0x8000_0000. Normal (Status_BEV = 0)
`define ANTARES_VECTOR_OFFSET_GENERAL 32'h0000_0000 // MIPS Standard is 0x0000_0180. General exception, but TBL
`define ANTARES_VECTOR_OFFSET_SPECIAL 32'h0000_0008 // MIPS Standard is 0x0000_0200. Interrupts (Cause_IV = 1)
//------------------------------------------------------------------------------
/*
Encoding for the MIPS Release 1 Architecture
3 types of instructions:
- R : Register-Register
- I : Register-Immediate
- J : Jump
Format:
------
- R : Opcode(6) + Rs(5) + Rt(5) + Rd(5) + shamt(5) + function(6)
- I : Opcode(6) + Rs(5) + Rt(5) + Imm(16)
- I : Opcode(6) + Imm(26)
*/
//------------------------------------------------------------------------------
// Opcode field for special instructions
//------------------------------------------------------------------------------
`define OP_TYPE_R 6'b00_0000 // Special
`define OP_TYPE_R2 6'b01_1100 // Special 2
`define OP_TYPE_REGIMM 6'b00_0001 // Branch/Trap
`define OP_TYPE_CP0 6'b01_0000 // Coprocessor 0
`define OP_TYPE_CP1 6'b01_0001 // Coprocessor 1
`define OP_TYPE_CP2 6'b01_0010 // Coprocessor 2
`define OP_TYPE_CP3 6'b01_0011 // Coprocessor 3
//------------------------------------------------------------------------------
// Instructions fields
//------------------------------------------------------------------------------
`define ANTARES_INSTR_OPCODE 31:26
`define ANTARES_INSTR_RS 25:21
`define ANTARES_INSTR_RT 20:16
`define ANTARES_INSTR_RD 15:11
`define ANTARES_INSTR_SHAMT 10:6
`define ANTARES_INSTR_FUNCT 5:0
`define ANTARES_INSTR_CP0_SEL 2:0
`define ANTARES_INSTR_IMM16 15:0
`define ANTARES_INSTR_IMM26 25:0
//------------------------------------------------------------------------------
// Opcode list
//------------------------------------------------------------------------------
`define OP_ADD `OP_TYPE_R
`define OP_ADDI 6'b00_1000
`define OP_ADDIU 6'b00_1001
`define OP_ADDU `OP_TYPE_R
`define OP_AND `OP_TYPE_R
`define OP_ANDI 6'b00_1100
`define OP_BEQ 6'b00_0100
`define OP_BGEZ `OP_TYPE_REGIMM
`define OP_BGEZAL `OP_TYPE_REGIMM
`define OP_BGTZ 6'b00_0111
`define OP_BLEZ 6'b00_0110
`define OP_BLTZ `OP_TYPE_REGIMM
`define OP_BLTZAL `OP_TYPE_REGIMM
`define OP_BNE 6'b00_0101
`define OP_BREAK `OP_TYPE_R
`define OP_CLO `OP_TYPE_R2
`define OP_CLZ `OP_TYPE_R2
`define OP_DIV `OP_TYPE_R
`define OP_DIVU `OP_TYPE_R
`define OP_ERET `OP_TYPE_CP0
`define OP_J 6'b00_0010
`define OP_JAL 6'b00_0011
`define OP_JALR `OP_TYPE_R
`define OP_JR `OP_TYPE_R
`define OP_LB 6'b10_0000
`define OP_LBU 6'b10_0100
`define OP_LH 6'b10_0001
`define OP_LHU 6'b10_0101
`define OP_LL 6'b11_0000
`define OP_LUI 6'b00_1111
`define OP_LW 6'b10_0011
`define OP_MADD `OP_TYPE_R2
`define OP_MADDU `OP_TYPE_R2
`define OP_MFC0 `OP_TYPE_CP0
`define OP_MFHI `OP_TYPE_R
`define OP_MFLO `OP_TYPE_R
`define OP_MOVN `OP_TYPE_R
`define OP_MOVZ `OP_TYPE_R
`define OP_MSUB `OP_TYPE_R2
`define OP_MSUBU `OP_TYPE_R2
`define OP_MTC0 `OP_TYPE_CP0
`define OP_MTHI `OP_TYPE_R
`define OP_MTLO `OP_TYPE_R
`define OP_MULT `OP_TYPE_R
`define OP_MULTU `OP_TYPE_R
`define OP_NOR `OP_TYPE_R
`define OP_OR `OP_TYPE_R
`define OP_ORI 6'b00_1101
`define OP_SB 6'b10_1000
`define OP_SC 6'b11_1000
`define OP_SH 6'b10_1001
`define OP_SLL `OP_TYPE_R
`define OP_SLLV `OP_TYPE_R
`define OP_SLT `OP_TYPE_R
`define OP_SLTI 6'b00_1010
`define OP_SLTIU 6'b00_1011
`define OP_SLTU `OP_TYPE_R
`define OP_SRA `OP_TYPE_R
`define OP_SRAV `OP_TYPE_R
`define OP_SRL `OP_TYPE_R
`define OP_SRLV `OP_TYPE_R
`define OP_SUB `OP_TYPE_R
`define OP_SUBU `OP_TYPE_R
`define OP_SW 6'b10_1011
`define OP_SYSCALL `OP_TYPE_R
`define OP_TEQ `OP_TYPE_R
`define OP_TEQI `OP_TYPE_REGIMM
`define OP_TGE `OP_TYPE_R
`define OP_TGEI `OP_TYPE_REGIMM
`define OP_TGEIU `OP_TYPE_REGIMM
`define OP_TGEU `OP_TYPE_R
`define OP_TLT `OP_TYPE_R
`define OP_TLTI `OP_TYPE_REGIMM
`define OP_TLTIU `OP_TYPE_REGIMM
`define OP_TLTU `OP_TYPE_R
`define OP_TNE `OP_TYPE_R
`define OP_TNEI `OP_TYPE_REGIMM
`define OP_XOR `OP_TYPE_R
`define OP_XORI 6'b00_1110
//------------------------------------------------------------------------------
// Function field for R(2)-type instructions
//------------------------------------------------------------------------------
`define FUNCTION_OP_ADD 6'b10_0000
`define FUNCTION_OP_ADDU 6'b10_0001
`define FUNCTION_OP_AND 6'b10_0100
`define FUNCTION_OP_BREAK 6'b00_1101
`define FUNCTION_OP_CLO 6'b10_0001
`define FUNCTION_OP_CLZ 6'b10_0000
`define FUNCTION_OP_DIV 6'b01_1010
`define FUNCTION_OP_DIVU 6'b01_1011
`define FUNCTION_OP_JALR 6'b00_1001
`define FUNCTION_OP_JR 6'b00_1000
`define FUNCTION_OP_MADD 6'b00_0000
`define FUNCTION_OP_MADDU 6'b00_0001
`define FUNCTION_OP_MFHI 6'b01_0000
`define FUNCTION_OP_MFLO 6'b01_0010
`define FUNCTION_OP_MOVN 6'b00_1011
`define FUNCTION_OP_MOVZ 6'b00_1010
`define FUNCTION_OP_MSUB 6'b00_0100
`define FUNCTION_OP_MSUBU 6'b00_0101
`define FUNCTION_OP_MTHI 6'b01_0001
`define FUNCTION_OP_MTLO 6'b01_0011
`define FUNCTION_OP_MULT 6'b01_1000
`define FUNCTION_OP_MULTU 6'b01_1001
`define FUNCTION_OP_NOR 6'b10_0111
`define FUNCTION_OP_OR 6'b10_0101
`define FUNCTION_OP_SLL 6'b00_0000
`define FUNCTION_OP_SLLV 6'b00_0100
`define FUNCTION_OP_SLT 6'b10_1010
`define FUNCTION_OP_SLTU 6'b10_1011
`define FUNCTION_OP_SRA 6'b00_0011
`define FUNCTION_OP_SRAV 6'b00_0111
`define FUNCTION_OP_SRL 6'b00_0010
`define FUNCTION_OP_SRLV 6'b00_0110
`define FUNCTION_OP_SUB 6'b10_0010
`define FUNCTION_OP_SUBU 6'b10_0011
`define FUNCTION_OP_SYSCALL 6'b00_1100
`define FUNCTION_OP_TEQ 6'b11_0100
`define FUNCTION_OP_TGE 6'b11_0000
`define FUNCTION_OP_TGEU 6'b11_0001
`define FUNCTION_OP_TLT 6'b11_0010
`define FUNCTION_OP_TLTU 6'b11_0011
`define FUNCTION_OP_TNE 6'b11_0110
`define FUNCTION_OP_XOR 6'b10_0110
//------------------------------------------------------------------------------
// Branch >/< zero (and link), traps: Rt
//------------------------------------------------------------------------------
`define RT_OP_BGEZ 5'b00001
`define RT_OP_BGEZAL 5'b10001
`define RT_OP_BLTZ 5'b00000
`define RT_OP_BLTZAL 5'b10000
`define RT_OP_TEQI 5'b01100
`define RT_OP_TGEI 5'b01000
`define RT_OP_TGEIU 5'b01001
`define RT_OP_TLTI 5'b01010
`define RT_OP_TLTIU 5'b01011
`define RT_OP_TNEI 5'b01110
//------------------------------------------------------------------------------
// Rs field for Coprocessor instructions
//------------------------------------------------------------------------------
`define RS_OP_MFC 5'b00000
`define RS_OP_MTC 5'b00100
//------------------------------------------------------------------------------
// ERET
//------------------------------------------------------------------------------
`define RS_OP_ERET 5'b10000
`define FUNCTION_OP_ERET 6'b01_1000
//------------------------------------------------------------------------------
// ALU Operations
//------------------------------------------------------------------------------
`define ALU_OP_ADDU 5'd0
`define ALU_OP_ADD 5'd1
`define ALU_OP_SUB 5'd2
`define ALU_OP_SUBU 5'd3
`define ALU_OP_AND 5'd4
`define ALU_OP_MULS 5'd5
`define ALU_OP_MULU 5'd6
`define ALU_OP_NOR 5'd7
`define ALU_OP_OR 5'd8
`define ALU_OP_SLL 5'd9
`define ALU_OP_SRA 5'd10
`define ALU_OP_SRL 5'd11
`define ALU_OP_XOR 5'd12
`define ALU_OP_MFHI 5'd13
`define ALU_OP_MFLO 5'd14
`define ALU_OP_MTHI 5'd15
`define ALU_OP_MTLO 5'd16
`define ALU_OP_SLT 5'd17
`define ALU_OP_SLTU 5'd18
`define ALU_OP_DIV 5'd19
`define ALU_OP_DIVU 5'd20
`define ALU_OP_CLO 5'd21
`define ALU_OP_CLZ 5'd22
`define ALU_OP_MADD 5'd23
`define ALU_OP_MADDU 5'd24
`define ALU_OP_MSUB 5'd25
`define ALU_OP_MSUBU 5'd26
`define ALU_OP_A 5'd27
`define ALU_OP_B 5'd28
//------------------------------------------------------------------------------
/*
Exception.
All signals are active High.
----------------------------------------------------------------------------
Bit Meaning
----------------------------------------------------------------------------
2 : Instruction can cause exception @ ID
1 : Instruction can cause exception @ EX
0 : Instruction can cause exception @ MEM
----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
`define EXCEPTION_NONE 3'b000
`define EXCEPTION_ID 3'b100
`define EXCEPTION_EX 3'b010
`define EXCEPTION_MEM 3'b001
//
`define EXC_ADD `EXCEPTION_EX
`define EXC_ADDI `EXCEPTION_EX
`define EXC_ADDIU `EXCEPTION_NONE
`define EXC_ADDU `EXCEPTION_NONE
`define EXC_AND `EXCEPTION_NONE
`define EXC_ANDI `EXCEPTION_NONE
`define EXC_BEQ `EXCEPTION_NONE
`define EXC_BGEZ `EXCEPTION_NONE
`define EXC_BGEZAL `EXCEPTION_NONE
`define EXC_BGTZ `EXCEPTION_NONE
`define EXC_BLEZ `EXCEPTION_NONE
`define EXC_BLTZ `EXCEPTION_NONE
`define EXC_BLTZAL `EXCEPTION_NONE
`define EXC_BNE `EXCEPTION_NONE
`define EXC_BREAK `EXCEPTION_ID
`define EXC_CLO `EXCEPTION_NONE
`define EXC_CLZ `EXCEPTION_NONE
`define EXC_DIV `EXCEPTION_NONE
`define EXC_DIVU `EXCEPTION_NONE
`define EXC_ERET `EXCEPTION_ID
`define EXC_J `EXCEPTION_NONE
`define EXC_JAL `EXCEPTION_NONE
`define EXC_JALR `EXCEPTION_NONE
`define EXC_JR `EXCEPTION_NONE
`define EXC_LB `EXCEPTION_MEM
`define EXC_LBU `EXCEPTION_MEM
`define EXC_LH `EXCEPTION_MEM
`define EXC_LHU `EXCEPTION_MEM
`define EXC_LL `EXCEPTION_MEM
`define EXC_LUI `EXCEPTION_NONE
`define EXC_LW `EXCEPTION_MEM
`define EXC_MADD `EXCEPTION_NONE
`define EXC_MADDU `EXCEPTION_NONE
`define EXC_MFC0 `EXCEPTION_ID
`define EXC_MFHI `EXCEPTION_NONE
`define EXC_MFLO `EXCEPTION_NONE
`define EXC_MOVN `EXCEPTION_NONE
`define EXC_MOVZ `EXCEPTION_NONE
`define EXC_MSUB `EXCEPTION_NONE
`define EXC_MSUBU `EXCEPTION_NONE
`define EXC_MTC0 `EXCEPTION_ID
`define EXC_MTHI `EXCEPTION_NONE
`define EXC_MTLO `EXCEPTION_NONE
`define EXC_MULT `EXCEPTION_NONE
`define EXC_MULTU `EXCEPTION_NONE
`define EXC_NOR `EXCEPTION_NONE
`define EXC_OR `EXCEPTION_NONE
`define EXC_ORI `EXCEPTION_NONE
`define EXC_SB `EXCEPTION_MEM
`define EXC_SC `EXCEPTION_MEM
`define EXC_SH `EXCEPTION_MEM
`define EXC_SLL `EXCEPTION_NONE
`define EXC_SLLV `EXCEPTION_NONE
`define EXC_SLT `EXCEPTION_NONE
`define EXC_SLTI `EXCEPTION_NONE
`define EXC_SLTIU `EXCEPTION_NONE
`define EXC_SLTU `EXCEPTION_NONE
`define EXC_SRA `EXCEPTION_NONE
`define EXC_SRAV `EXCEPTION_NONE
`define EXC_SRL `EXCEPTION_NONE
`define EXC_SRLV `EXCEPTION_NONE
`define EXC_SUB `EXCEPTION_EX
`define EXC_SUBU `EXCEPTION_EX
`define EXC_SW `EXCEPTION_MEM
`define EXC_SYSCALL `EXCEPTION_ID
`define EXC_TEQ `EXCEPTION_MEM // Requieres result from EX, so it triggers in the MEM stage
`define EXC_TEQI `EXCEPTION_MEM // Requieres result from EX, so it triggers in the MEM stage
`define EXC_TGE `EXCEPTION_MEM // Requieres result from EX, so it triggers in the MEM stage
`define EXC_TGEI `EXCEPTION_MEM // Requieres result from EX, so it triggers in the MEM stage
`define EXC_TGEIU `EXCEPTION_MEM // Requieres result from EX, so it triggers in the MEM stage
`define EXC_TGEU `EXCEPTION_MEM // Requieres result from EX, so it triggers in the MEM stage
`define EXC_TLT `EXCEPTION_MEM // Requieres result from EX, so it triggers in the MEM stage
`define EXC_TLTI `EXCEPTION_MEM // Requieres result from EX, so it triggers in the MEM stage
`define EXC_TLTIU `EXCEPTION_MEM // Requieres result from EX, so it triggers in the MEM stage
`define EXC_TLTU `EXCEPTION_MEM // Requieres result from EX, so it triggers in the MEM stage
`define EXC_TNE `EXCEPTION_MEM // Requieres result from EX, so it triggers in the MEM stage
`define EXC_TNEI `EXCEPTION_MEM // Requieres result from EX, so it triggers in the MEM stage
`define EXC_XOR `EXCEPTION_NONE
`define EXC_XORI `EXCEPTION_NONE
//------------------------------------------------------------------------------
/*
Hazard and forwarding signals.
All signals are Active High.
------------
Bit Meaning
------------
7: Wants Rs by ID
6: Needs Rs by ID
5: Wants Rt by ID
4: Needs Rt by ID
3: Wants Rs by EX
2: Needs Rs by EX
1: Wants Rt by EX
0: Needs Rt by EX
*/
//------------------------------------------------------------------------------
`define HAZ_NOTHING 8'b00000000 // Jumps, Lui, Mfhi/lo, special, etc.
`define HAZ_ID_RS_ID_RT 8'b11110000 // Beq, Bne, Traps
`define HAZ_ID_RS 8'b11000000 // Most branches, Jumps to registers
`define HAZ_ID_RT 8'b00110000 // Mtc0
`define HAZ_ID_RT_EX_RS 8'b10111100 // Movn, Movz
`define HAZ_EX_RS_EX_RT 8'b10101111 // Many R-Type ops
`define HAZ_EX_RS 8'b10001100 // Immediates: Loads, Clo/z, Mthi/lo, etc.
`define HAZ_EX_RS_W_RT 8'b10101110 // Stores
`define HAZ_EX_RT 8'b00100011 // Shifts using Shamt field
//-----------------------------------------
`define HAZ_ADD `HAZ_EX_RS_EX_RT
`define HAZ_ADDI `HAZ_EX_RS
`define HAZ_ADDIU `HAZ_EX_RS
`define HAZ_ADDU `HAZ_EX_RS_EX_RT
`define HAZ_AND `HAZ_EX_RS_EX_RT
`define HAZ_ANDI `HAZ_EX_RS
`define HAZ_BEQ `HAZ_ID_RS_ID_RT
`define HAZ_BGEZ `HAZ_ID_RS
`define HAZ_BGEZAL `HAZ_ID_RS
`define HAZ_BGTZ `HAZ_ID_RS
`define HAZ_BLEZ `HAZ_ID_RS
`define HAZ_BLTZ `HAZ_ID_RS
`define HAZ_BLTZAL `HAZ_ID_RS
`define HAZ_BNE `HAZ_ID_RS_ID_RT
`define HAZ_BREAK `HAZ_NOTHING
`define HAZ_CLO `HAZ_EX_RS
`define HAZ_CLZ `HAZ_EX_RS
`define HAZ_DIV `HAZ_EX_RS_EX_RT
`define HAZ_DIVU `HAZ_EX_RS_EX_RT
`define HAZ_ERET `HAZ_NOTHING
`define HAZ_J `HAZ_NOTHING
`define HAZ_JAL `HAZ_NOTHING
`define HAZ_JALR `HAZ_ID_RS
`define HAZ_JR `HAZ_ID_RS
`define HAZ_LB `HAZ_EX_RS
`define HAZ_LBU `HAZ_EX_RS
`define HAZ_LH `HAZ_EX_RS
`define HAZ_LHU `HAZ_EX_RS
`define HAZ_LL `HAZ_EX_RS
`define HAZ_LUI `HAZ_NOTHING
`define HAZ_LW `HAZ_EX_RS
`define HAZ_MADD `HAZ_EX_RS_EX_RT
`define HAZ_MADDU `HAZ_EX_RS_EX_RT
`define HAZ_MFC0 `HAZ_NOTHING
`define HAZ_MFHI `HAZ_NOTHING
`define HAZ_MFLO `HAZ_NOTHING
`define HAZ_MOVN `HAZ_ID_RT_EX_RS
`define HAZ_MOVZ `HAZ_ID_RT_EX_RS
`define HAZ_MSUB `HAZ_EX_RS_EX_RT
`define HAZ_MSUBU `HAZ_EX_RS_EX_RT
`define HAZ_MTC0 `HAZ_ID_RT
`define HAZ_MTHI `HAZ_EX_RS
`define HAZ_MTLO `HAZ_EX_RS
`define HAZ_MULT `HAZ_EX_RS_EX_RT
`define HAZ_MULTU `HAZ_EX_RS_EX_RT
`define HAZ_NOR `HAZ_EX_RS_EX_RT
`define HAZ_OR `HAZ_EX_RS_EX_RT
`define HAZ_ORI `HAZ_EX_RS
`define HAZ_SB `HAZ_EX_RS_W_RT
`define HAZ_SC `HAZ_EX_RS_W_RT
`define HAZ_SH `HAZ_EX_RS_W_RT
`define HAZ_SLL `HAZ_EX_RT
`define HAZ_SLLV `HAZ_EX_RS_EX_RT
`define HAZ_SLT `HAZ_EX_RS_EX_RT
`define HAZ_SLTI `HAZ_EX_RS
`define HAZ_SLTIU `HAZ_EX_RS
`define HAZ_SLTU `HAZ_EX_RS_EX_RT
`define HAZ_SRA `HAZ_EX_RT
`define HAZ_SRAV `HAZ_EX_RS_EX_RT
`define HAZ_SRL `HAZ_EX_RT
`define HAZ_SRLV `HAZ_EX_RS_EX_RT
`define HAZ_SUB `HAZ_EX_RS_EX_RT
`define HAZ_SUBU `HAZ_EX_RS_EX_RT
`define HAZ_SW `HAZ_EX_RS_W_RT
`define HAZ_SYSCALL `HAZ_NOTHING
`define HAZ_TEQ `HAZ_EX_RS_EX_RT
`define HAZ_TEQI `HAZ_EX_RS
`define HAZ_TGE `HAZ_EX_RS_EX_RT
`define HAZ_TGEI `HAZ_EX_RS
`define HAZ_TGEIU `HAZ_EX_RS
`define HAZ_TGEU `HAZ_EX_RS_EX_RT
`define HAZ_TLT `HAZ_EX_RS_EX_RT
`define HAZ_TLTI `HAZ_EX_RS
`define HAZ_TLTIU `HAZ_EX_RS
`define HAZ_TLTU `HAZ_EX_RS_EX_RT
`define HAZ_TNE `HAZ_EX_RS_EX_RT
`define HAZ_TNEI `HAZ_EX_RS
`define HAZ_XOR `HAZ_EX_RS_EX_RT
`define HAZ_XORI `HAZ_EX_RS
//------------------------------------------------------------------------------
/*
Datapath controls.
All signals are active High.
----------------------------------------------------------------------------
Bit Name Description
----------------------------------------------------------------------------
31 : Wants Rs by ID
30 : Needs Rs by ID
29 : Wants Rt by ID
28 : Needs Rt by ID
27 : Wants Rs by EX
26 : Needs Rs by EX
25 : Wants Rt by EX
24 : Needs Rt by EX
-------------------------------
23 : id_id_exception_source Instruction can cause exception @ ID
22 : id_ex_exception_source Instruction can cause exception @ EX
21 : id_mem_exception_source Instruction can cause exception @ MEM
-------------------------------
20 : id_alu_operation Operation to execute.
19 : .
18 : .
17 : .
16 : .
-------------------------------
15: id_trap Trap instruction
14: id_trap_condition Condition: ALU result = 0 (0), ALU result != 0 (1)
-------------------------------
13 : id_gpr_we Write enable (GPR)
12 : id_mem_to_gpr_select Select data: ALU(0), MEM(1)
-------------------------------
11 : id_alu_port_a_select Select: Rs(0), shamt(1), 0x04(2), 0x10(3)
10 : .
9 : id_alu_port_b_select Select: Rt(0), S/ZImm16(1), PCAdd4(2), CP0(3)
8 : .
7 : id_gpr_wa_select Select register: Rd(0), Rt(1), 31(2)
6 : .
-------------------------------
5 : id_jump Jump instruction
4 : id_branch Branch instruction
-------------------------------
3 : id_mem_write Write to data memory
2 : id_mem_byte Enable read/write one byte
1 : id_mem_halfword Enable read/write 2 bytes (16 bits data)
0 : id_mem_data_sign_ext Zero extend data (0) or Sign extend data (1)
----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
`define DP_NONE {`HAZ_NOTHING , `EXCEPTION_NONE, `ALU_OP_AND, 16'b00_00_000000_00_0000}
`define DP_ADD {`HAZ_EX_RS_EX_RT, `EXCEPTION_EX , `ALU_OP_ADD, 16'b00_10_000000_00_0000}
`define DP_ADDI {`HAZ_EX_RS , `EXCEPTION_EX , `ALU_OP_ADD, 16'b00_10_000101_00_0000}
`define DP_ADDIU {`HAZ_EX_RS , `EXCEPTION_NONE, `ALU_OP_ADDU, 16'b00_10_000101_00_0000}
`define DP_ADDU {`HAZ_EX_RS_EX_RT, `EXCEPTION_NONE, `ALU_OP_ADDU, 16'b00_10_000000_00_0000}
`define DP_AND {`HAZ_EX_RS_EX_RT, `EXCEPTION_NONE, `ALU_OP_AND, 16'b00_10_000000_00_0000}
`define DP_ANDI {`HAZ_EX_RS , `EXCEPTION_NONE, `ALU_OP_AND, 16'b00_10_000101_00_0000}
`define DP_BEQ {`HAZ_ID_RS_ID_RT, `EXCEPTION_NONE, `ALU_OP_AND, 16'b00_00_000000_01_0000}
`define DP_BGEZ {`HAZ_ID_RS , `EXCEPTION_NONE, `ALU_OP_AND, 16'b00_00_000000_01_0000}
`define DP_BGEZAL {`HAZ_ID_RS , `EXCEPTION_NONE, `ALU_OP_ADD, 16'b00_10_101010_01_0000}
`define DP_BGTZ {`HAZ_ID_RS , `EXCEPTION_NONE, `ALU_OP_AND, 16'b00_00_000000_01_0000}
`define DP_BLEZ {`HAZ_ID_RS , `EXCEPTION_NONE, `ALU_OP_AND, 16'b00_00_000000_01_0000}
`define DP_BLTZ {`HAZ_ID_RS , `EXCEPTION_NONE, `ALU_OP_AND, 16'b00_00_000000_01_0000}
`define DP_BLTZAL {`HAZ_ID_RS , `EXCEPTION_NONE, `ALU_OP_ADD, 16'b00_10_101010_01_0000}
`define DP_BNE {`HAZ_ID_RS_ID_RT, `EXCEPTION_NONE, `ALU_OP_AND, 16'b00_00_000000_01_0000}
`define DP_BREAK {`HAZ_NOTHING , `EXCEPTION_ID , `ALU_OP_AND, 16'b00_00_000000_00_0000}
`define DP_CLO {`HAZ_EX_RS , `EXCEPTION_NONE, `ALU_OP_CLO, 16'b00_10_000000_00_0000}
`define DP_CLZ {`HAZ_EX_RS , `EXCEPTION_NONE, `ALU_OP_CLZ, 16'b00_10_000000_00_0000}
`define DP_DIV {`HAZ_EX_RS_EX_RT, `EXCEPTION_NONE, `ALU_OP_DIV, 16'b00_00_000000_00_0000}
`define DP_DIVU {`HAZ_EX_RS_EX_RT, `EXCEPTION_NONE, `ALU_OP_DIVU, 16'b00_00_000000_00_0000}
`define DP_ERET {`HAZ_NOTHING , `EXCEPTION_ID , `ALU_OP_AND, 16'b00_00_000000_00_0000}
`define DP_J {`HAZ_NOTHING , `EXCEPTION_NONE, `ALU_OP_AND, 16'b00_00_000000_10_0000}
`define DP_JAL {`HAZ_NOTHING , `EXCEPTION_NONE, `ALU_OP_ADD, 16'b00_10_101010_10_0000}
`define DP_JALR {`HAZ_ID_RS , `EXCEPTION_NONE, `ALU_OP_ADD, 16'b00_10_101010_01_0000}
`define DP_JR {`HAZ_ID_RS , `EXCEPTION_NONE, `ALU_OP_AND, 16'b00_00_000000_01_0000}
`define DP_LB {`HAZ_EX_RS , `EXCEPTION_MEM , `ALU_OP_ADDU, 16'b00_11_000101_00_0101}
`define DP_LBU {`HAZ_EX_RS , `EXCEPTION_MEM , `ALU_OP_ADDU, 16'b00_11_000101_00_0100}
`define DP_LH {`HAZ_EX_RS , `EXCEPTION_MEM , `ALU_OP_ADDU, 16'b00_11_000101_00_0011}
`define DP_LHU {`HAZ_EX_RS , `EXCEPTION_MEM , `ALU_OP_ADDU, 16'b00_11_000101_00_0010}
`define DP_LL {`HAZ_EX_RS , `EXCEPTION_MEM , `ALU_OP_ADDU, 16'b00_11_000101_00_0000}
`define DP_LUI {`HAZ_NOTHING , `EXCEPTION_NONE, `ALU_OP_SLL, 16'b00_10_110101_00_0000}
`define DP_LW {`HAZ_EX_RS , `EXCEPTION_MEM , `ALU_OP_ADDU, 16'b00_11_000101_00_0000}
`define DP_MADD {`HAZ_EX_RS_EX_RT, `EXCEPTION_NONE, `ALU_OP_MADD, 16'b00_00_000000_00_0000}
`define DP_MADDU {`HAZ_EX_RS_EX_RT, `EXCEPTION_NONE, `ALU_OP_MADDU, 16'b00_00_000000_00_0000}
`define DP_MFC0 {`HAZ_NOTHING , `EXCEPTION_ID , `ALU_OP_B, 16'b00_10_001101_00_0000}
`define DP_MFHI {`HAZ_NOTHING , `EXCEPTION_NONE, `ALU_OP_MFHI, 16'b00_10_000000_00_0000}
`define DP_MFLO {`HAZ_NOTHING , `EXCEPTION_NONE, `ALU_OP_MFLO, 16'b00_10_000000_00_0000}
`define DP_MOVN {`HAZ_ID_RT_EX_RS, `EXCEPTION_NONE, `ALU_OP_A, 16'b00_00_000000_00_0000}
`define DP_MOVZ {`HAZ_ID_RT_EX_RS, `EXCEPTION_NONE, `ALU_OP_A, 16'b00_00_000000_00_0000}
`define DP_MSUB {`HAZ_EX_RS_EX_RT, `EXCEPTION_NONE, `ALU_OP_MSUB, 16'b00_00_000000_00_0000}
`define DP_MSUBU {`HAZ_EX_RS_EX_RT, `EXCEPTION_NONE, `ALU_OP_MSUBU, 16'b00_00_000000_00_0000}
`define DP_MTC0 {`HAZ_ID_RT , `EXCEPTION_ID , `ALU_OP_AND, 16'b00_00_000000_00_0000}
`define DP_MTHI {`HAZ_EX_RS , `EXCEPTION_NONE, `ALU_OP_MTHI, 16'b00_00_000000_00_0000}
`define DP_MTLO {`HAZ_EX_RS , `EXCEPTION_NONE, `ALU_OP_MTLO, 16'b00_00_000000_00_0000}
`define DP_MULT {`HAZ_EX_RS_EX_RT, `EXCEPTION_NONE, `ALU_OP_MULS, 16'b00_00_000000_00_0000}
`define DP_MULTU {`HAZ_EX_RS_EX_RT, `EXCEPTION_NONE, `ALU_OP_MULU, 16'b00_00_000000_00_0000}
`define DP_NOR {`HAZ_EX_RS_EX_RT, `EXCEPTION_NONE, `ALU_OP_NOR, 16'b00_10_000000_00_0000}
`define DP_OR {`HAZ_EX_RS_EX_RT, `EXCEPTION_NONE, `ALU_OP_OR, 16'b00_10_000000_00_0000}
`define DP_ORI {`HAZ_EX_RS , `EXCEPTION_NONE, `ALU_OP_OR, 16'b00_10_000101_00_0000}
`define DP_SB {`HAZ_EX_RS_W_RT , `EXCEPTION_MEM , `ALU_OP_ADDU, 16'b00_00_000100_00_1100}
`define DP_SC {`HAZ_EX_RS_W_RT , `EXCEPTION_MEM , `ALU_OP_ADDU, 16'b00_11_000101_00_1000}
`define DP_SH {`HAZ_EX_RS_W_RT , `EXCEPTION_MEM , `ALU_OP_ADDU, 16'b00_00_000100_00_1010}
`define DP_SLL {`HAZ_EX_RT , `EXCEPTION_NONE, `ALU_OP_SLL, 16'b00_10_010000_00_0000}
`define DP_SLLV {`HAZ_EX_RS_EX_RT, `EXCEPTION_NONE, `ALU_OP_SLL, 16'b00_10_000000_00_0000}
`define DP_SLT {`HAZ_EX_RS_EX_RT, `EXCEPTION_NONE, `ALU_OP_SLT, 16'b00_10_000000_00_0000}
`define DP_SLTI {`HAZ_EX_RS , `EXCEPTION_NONE, `ALU_OP_SLT, 16'b00_10_000101_00_0000}
`define DP_SLTIU {`HAZ_EX_RS , `EXCEPTION_NONE, `ALU_OP_SLTU, 16'b00_10_000101_00_0000}
`define DP_SLTU {`HAZ_EX_RS_EX_RT, `EXCEPTION_NONE, `ALU_OP_SLTU, 16'b00_10_000000_00_0000}
`define DP_SRA {`HAZ_EX_RT , `EXCEPTION_NONE, `ALU_OP_SRA, 16'b00_10_010000_00_0000}
`define DP_SRAV {`HAZ_EX_RS_EX_RT, `EXCEPTION_NONE, `ALU_OP_SRA, 16'b00_10_000000_00_0000}
`define DP_SRL {`HAZ_EX_RT , `EXCEPTION_NONE, `ALU_OP_SRL, 16'b00_10_010000_00_0000}
`define DP_SRLV {`HAZ_EX_RS_EX_RT, `EXCEPTION_NONE, `ALU_OP_SRL, 16'b00_10_000000_00_0000}
`define DP_SUB {`HAZ_EX_RS_EX_RT, `EXCEPTION_EX , `ALU_OP_SUB, 16'b00_10_000000_00_0000}
`define DP_SUBU {`HAZ_EX_RS_EX_RT, `EXCEPTION_EX , `ALU_OP_SUBU, 16'b00_10_000000_00_0000}
`define DP_SW {`HAZ_EX_RS_W_RT , `EXCEPTION_MEM , `ALU_OP_ADDU, 16'b00_00_000100_00_1000}
`define DP_SYSCALL {`HAZ_NOTHING , `EXCEPTION_ID , `ALU_OP_ADDU, 16'b00_00_000000_00_0000}
`define DP_TEQ {`HAZ_EX_RS_EX_RT, `EXCEPTION_MEM , `ALU_OP_SUBU, 16'b10_00_000000_00_0000}
`define DP_TEQI {`HAZ_EX_RS , `EXCEPTION_MEM , `ALU_OP_SUBU, 16'b10_00_000000_00_0000}
`define DP_TGE {`HAZ_EX_RS_EX_RT, `EXCEPTION_MEM , `ALU_OP_SLT, 16'b10_00_000000_00_0000}
`define DP_TGEI {`HAZ_EX_RS , `EXCEPTION_MEM , `ALU_OP_SLT, 16'b10_00_000000_00_0000}
`define DP_TGEIU {`HAZ_EX_RS , `EXCEPTION_MEM , `ALU_OP_SLTU, 16'b10_00_000000_00_0000}
`define DP_TGEU {`HAZ_EX_RS_EX_RT, `EXCEPTION_MEM , `ALU_OP_SLTU, 16'b10_00_000000_00_0000}
`define DP_TLT {`HAZ_EX_RS_EX_RT, `EXCEPTION_MEM , `ALU_OP_SLT, 16'b11_00_000000_00_0000}
`define DP_TLTI {`HAZ_EX_RS , `EXCEPTION_MEM , `ALU_OP_SLT, 16'b11_00_000000_00_0000}
`define DP_TLTIU {`HAZ_EX_RS , `EXCEPTION_MEM , `ALU_OP_SLTU, 16'b11_00_000000_00_0000}
`define DP_TLTU {`HAZ_EX_RS_EX_RT, `EXCEPTION_MEM , `ALU_OP_SLTU, 16'b11_00_000000_00_0000}
`define DP_TNE {`HAZ_EX_RS_EX_RT, `EXCEPTION_MEM , `ALU_OP_SUBU, 16'b11_00_000000_00_0000}
`define DP_TNEI {`HAZ_EX_RS , `EXCEPTION_MEM , `ALU_OP_SUBU, 16'b11_00_000000_00_0000}
`define DP_XOR {`HAZ_EX_RS_EX_RT, `EXCEPTION_NONE, `ALU_OP_XOR, 16'b00_10_000000_00_0000}
`define DP_XORI {`HAZ_EX_RS , `EXCEPTION_NONE, `ALU_OP_XOR, 16'b00_10_000101_00_0000}
// EOF
|
//==================================================================================================
// Filename : antares_add.v
// Created On : Tue Sep 1 10:15:22 2015
// Last Modified : Sat Nov 07 11:45:24 2015
// Revision : 0.1
// Author : Angel Terrones
// Company : Universidad Sim\xc3\xb3n Bol\xc3\xadvar
// Email : [email protected]
//
// Description : A simple 32-bits adder
//==================================================================================================
module antares_add (
input [31:0] a,
input [31:0] b,
output [31:0] c
);
assign c = a + b;
endmodule // antares_add
|
//==================================================================================================
// Filename : memory.v
// Created On : Wed Sep 9 18:40:13 2015
// Last Modified : Wed Sep 09 18:45:50 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Sim\xc3\xb3n Bol\xc3\xadvar
// Email : [email protected]
//
// Description : Dual-port memory (Simulation)
//==================================================================================================
module memory#(
parameter MEM_ADDR_WIDTH = 8 // Default: 256 words/1 KB
)(
input clk,
input rst,
//port A
input [MEM_ADDR_WIDTH-1:0] a_addr, // Address
input [31:0] a_din, // Data input
input [3:0] a_wr, // Write/Read
input a_enable, // Valid operation
output reg [31:0] a_dout, // Data output
output reg a_ready, // Data output ready (valid)
// port B
input [MEM_ADDR_WIDTH-1:0] b_addr, // Address
input [31:0] b_din, // Data input
input [3:0] b_wr, // Write/Read
input b_enable, // Valid operation
output reg [31:0] b_dout, // Data output
output reg b_ready // Data output ready (valid)
);
//--------------------------------------------------------------------------
// Signal Declaration: reg
//--------------------------------------------------------------------------
reg [31:0] a_data_out;
reg [31:0] b_data_out;
//--------------------------------------------------------------------------
// Set the ready signal
//--------------------------------------------------------------------------
always @(posedge clk) begin
a_ready <= (rst) ? 1\'b0 : a_enable;
b_ready <= (rst) ? 1\'b0 : b_enable;
end
//--------------------------------------------------------------------------
// assigment
//--------------------------------------------------------------------------
always @(*) begin
a_dout = (a_ready) ? a_data_out : 32\'bz;
b_dout = (b_ready) ? b_data_out : 32\'bz;
end
//--------------------------------------------------------------------------
// inicializar memoria
//--------------------------------------------------------------------------
reg [31:0] mem [0:(2**MEM_ADDR_WIDTH)-1];
initial begin
$readmemh("mem.hex", mem);
end
//--------------------------------------------------------------------------
// Port A
//--------------------------------------------------------------------------
always @(posedge clk) begin
a_data_out <= mem[a_addr];
if(a_wr != 4\'b0) begin
a_data_out <= a_din;
mem[a_addr][7:0] <= (a_wr[0] & a_enable) ? a_din[7:0] : mem[a_addr][7:0];
mem[a_addr][15:8] <= (a_wr[1] & a_enable) ? a_din[15:8] : mem[a_addr][15:8];
mem[a_addr][23:16] <= (a_wr[2] & a_enable) ? a_din[23:16] : mem[a_addr][23:16];
mem[a_addr][31:24] <= (a_wr[3] & a_enable) ? a_din[31:24] : mem[a_addr][31:24];
end
end
//--------------------------------------------------------------------------
// Port B
//--------------------------------------------------------------------------
always @(posedge clk) begin
b_data_out <= mem[b_addr];
if(b_wr != 4\'b0) begin
b_data_out <= b_din;
mem[b_addr][7:0] <= (b_wr[0] & b_enable) ? b_din[7:0] : mem[b_addr][7:0];
mem[b_addr][15:8] <= (b_wr[1] & b_enable) ? b_din[15:8] : mem[b_addr][15:8];
mem[b_addr][23:16] <= (b_wr[2] & b_enable) ? b_din[23:16] : mem[b_addr][23:16];
mem[b_addr][31:24] <= (b_wr[3] & b_enable) ? b_din[31:24] : mem[b_addr][31:24];
end
end
endmodule
// Local Variables:
// verilog-library-flags:("-y ../../../Hardware/")
// flycheck-verilator-include-path:("../../../Hardware/")
// End:
|
//==================================================================================================
// Filename : antares_mux_2_1.v
// Created On : Mon Aug 31 21:12:26 2015
// Last Modified : Sat Nov 07 12:13:45 2015
// Revision : 0.1
// Author : Angel Terrones
// Company : Universidad Sim\xc3\xb3n Bol\xc3\xadvar
// Email : [email protected]
//
// Description : A 2-input multiplexer, with parameterizable width
//==================================================================================================
module antares_mux_2_1 #(parameter WIDTH = 32)
(
input [WIDTH-1:0] in0,
input [WIDTH-1:0] in1,
input select,
output reg [WIDTH-1:0] out
);
always @(/*AUTOSENSE*/in0 or in1 or select) begin
case (select)
1'b0: out = in0;
1'b1: out = in1;
endcase // case (select)
end // always @ (...
endmodule // antares_mux_2_1
|
//==================================================================================================
// Filename : antares_alu.v
// Created On : Thu Sep 3 09:14:03 2015
// Last Modified : Sat Nov 07 11:45:51 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Sim\xc3\xb3n Bol\xc3\xadvar
// Email : [email protected]
//
// Description : The Execution unit.
// Performs the following operations:
// - Arithmetic
// - Logical
// - Shift
// - Comparison
//==================================================================================================
`include "antares_defines.v"
module antares_alu #(parameter ENABLE_HW_MULT = 1,
parameter ENABLE_HW_DIV = 1,
parameter ENABLE_HW_CLOZ = 1
)(
input clk,
input rst,
input [31:0] ex_alu_port_a,
input [31:0] ex_alu_port_b,
input [4:0] ex_alu_operation,
input ex_stall,
input ex_flush,
output ex_request_stall,
output reg [31:0] ex_alu_result,
output ex_b_is_zero,
output reg exc_overflow
);
//--------------------------------------------------------------------------
// Signal Declaration: reg
//--------------------------------------------------------------------------
reg [63:0] hilo; // hold the result from MULT instruction
reg div_active; // 1 if the divider is currently active.
reg hilo_access; // check access
///-------------------------------------------------------------------------
// Signal Declaration: wire
//--------------------------------------------------------------------------
wire [31:0] A; // Port A (unsigned)
wire [31:0] B; // Port B (unsigned)
wire signed [31:0] add_sub_result; // A+B or A - B
wire [4:0] ex_alu_operation; // Operation
wire [63:0] mult_result; // Multiplication result
wire [31:0] hi; // HILO[63:32]
wire [31:0] lo; // HILO[31:0]
wire [31:0] shift_result; // Shift result
wire [31:0] quotient; // Division
wire [31:0] remainder; // Division
wire op_divs; // Signed division
wire op_divu; // Unsigned division
wire div_stall; // Stall
wire [31:0] dividend;
wire [31:0] divisor;
wire enable_ex; // Enable operations
wire op_mults; // Signed multiplication
wire op_multu; // Unsigned multiplication
wire mult_active; // Mult ex_alu_operation active inside the pipeline
wire mult_ready; // Mult result ready
wire mult_stall;
wire [31:0] mult_input_a;
wire [31:0] mult_input_b;
wire mult_signed_op;
wire mult_enable_op;
wire _op_divs;
wire _op_divu;
wire _op_mults;
wire _op_multu;
wire [31:0] shift_input_data;
wire [4:0] shift_shamnt;
wire shift_direction;
wire shift_sign_extend;
wire [5:0] clo_result;
wire [5:0] clz_result;
//--------------------------------------------------------------------------
// assignments
//--------------------------------------------------------------------------
assign A = ex_alu_port_a; // unsigned
assign B = ex_alu_port_b; // unsigned
assign ex_b_is_zero = (B == 32\'b0);
assign add_sub_result = ((ex_alu_operation == `ALU_OP_ADD) | (ex_alu_operation == `ALU_OP_ADDU)) ? (A + B) : (A - B);
assign hi = hilo[63:32];
assign lo = hilo[31:0];
assign enable_ex = ~((ex_stall ^ ex_request_stall) | ex_flush);
assign _op_divs = (B != 32\'d0) & (div_active == 1\'b0) & (ex_alu_operation == `ALU_OP_DIV);
assign _op_divu = (B != 32\'d0) & (div_active == 1\'b0) & (ex_alu_operation == `ALU_OP_DIVU);
assign _op_mults = (mult_active == 1\'b0) & (ex_alu_operation == `ALU_OP_MULS);
assign _op_multu = (mult_active == 1\'b0) & (ex_alu_operation == `ALU_OP_MULU);
assign op_divs = _op_divs & enable_ex;
assign op_divu = _op_divu & enable_ex;
assign op_mults = _op_mults & enable_ex;
assign op_multu = _op_multu & enable_ex;
// request stall if: division, multiplication, and device unit is busy.
// Do not use the op_XXX signal: combinatorial loop. So, this will stall the unit waiting for the instruction.
assign ex_request_stall = (_op_divu | _op_divs | div_stall | _op_mults | _op_multu | (mult_active ^ mult_ready)) & hilo_access;
assign mult_stall = ex_stall ^ex_request_stall;
assign mult_input_a = ex_alu_port_a[31:0];
assign mult_input_b = ex_alu_port_b[31:0];
assign mult_signed_op = ex_alu_operation == `ALU_OP_MULS;
assign mult_enable_op = op_mults | op_multu;
assign shift_input_data = ex_alu_port_b;
assign shift_shamnt = ex_alu_port_a[4:0];
assign shift_direction = ex_alu_operation == `ALU_OP_SLL;
assign shift_sign_extend = ex_alu_operation == `ALU_OP_SRA;
assign dividend = ex_alu_port_a[31:0];
assign divisor = ex_alu_port_b[31:0];
//--------------------------------------------------------------------------
// the BIG multiplexer
//--------------------------------------------------------------------------
always @(*) begin
case(ex_alu_operation)
`ALU_OP_ADD : ex_alu_result = add_sub_result;
`ALU_OP_ADDU : ex_alu_result = add_sub_result;
`ALU_OP_SUB : ex_alu_result = add_sub_result;
`ALU_OP_SUBU : ex_alu_result = add_sub_result;
`ALU_OP_AND : ex_alu_result = ex_alu_port_a & ex_alu_port_b;
`ALU_OP_CLO : ex_alu_result = {26\'b0, clo_result};
`ALU_OP_CLZ : ex_alu_result = {26\'b0, clz_result};
`ALU_OP_NOR : ex_alu_result = ~(ex_alu_port_a | ex_alu_port_b);
`ALU_OP_OR : ex_alu_result = ex_alu_port_a | ex_alu_port_b;
`ALU_OP_SLL : ex_alu_result = shift_result;
`ALU_OP_SRA : ex_alu_result = shift_result;
`ALU_OP_SRL : ex_alu_result = shift_result;
`ALU_OP_XOR : ex_alu_result = ex_alu_port_a ^ ex_alu_port_b;
`ALU_OP_MFHI : ex_alu_result = hi;
`ALU_OP_MFLO : ex_alu_result = lo;
`ALU_OP_SLT : ex_alu_result = {31\'b0, $signed(ex_alu_port_a) < $signed(ex_alu_port_b)};
`ALU_OP_SLTU : ex_alu_result = {31\'b0, ex_alu_port_a < ex_alu_port_b};
`ALU_OP_A : ex_alu_result = ex_alu_port_a;
`ALU_OP_B : ex_alu_result = ex_alu_port_b;
default : ex_alu_result = 32\'bx;
endcase // case (ex_alu_operation)
end // always @ (*)
//--------------------------------------------------------------------------
// Detect Overflow
//--------------------------------------------------------------------------
always @(*) begin
case (ex_alu_operation)
`ALU_OP_ADD : exc_overflow = ((A[31] ~^ B[31]) & (A[31] ^ add_sub_result[31]));
`ALU_OP_SUB : exc_overflow = ((A[31] ^ B[31]) & (A[31] ^ add_sub_result[31]));
default : exc_overflow = 1\'b0;
endcase // case (ex_alu_operation)
end
//--------------------------------------------------------------------------
// Write to HILO register
// Div has priority over mult
//
// WARNING: THIS HAVE A BUG: HILO + X can\'t be done, unless the multiplier
// has finished.
// TODO: CHECK
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
hilo <= 64\'h0;
// End of automatics
end
else if ((div_stall == 1\'b0) & (div_active == 1\'b1)) begin // Divider unit has finished.
hilo <= {remainder, quotient};
end
else if(mult_ready) begin
case (ex_alu_operation)
`ALU_OP_MULS : hilo <= mult_result;
`ALU_OP_MULU : hilo <= mult_result;
`ALU_OP_MADD : hilo <= hilo + mult_result;
`ALU_OP_MADDU : hilo <= hilo + mult_result;
`ALU_OP_MSUB : hilo <= hilo - mult_result;
`ALU_OP_MSUBU : hilo <= hilo - mult_result;
default : hilo <= hilo;
endcase // case (ex_alu_operation)
end // if (enable_ex & mult_ready)
else if (enable_ex) begin
case (ex_alu_operation)
`ALU_OP_MTHI : hilo <= {A, lo};
`ALU_OP_MTLO : hilo <= {hi, A};
default : hilo <= hilo;
endcase // case (ex_alu_operation)
end
end // always @ (posedge clk)
//--------------------------------------------------------------------------
// Check if the div unit is currently active
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
div_active <= 1\'h0;
// End of automatics
end
else begin
case(div_active)
1\'d0 : div_active <= (op_divs || op_divu) ? 1\'b1 : 1\'b0;
1\'d1 : div_active <= (~div_stall) ? 1\'b0 : 1\'b1;
endcase // case (div_active)
end // else: !if(rst)
end // always @ (posedge clk)
//--------------------------------------------------------------------------
// Detect access to HILO register
//--------------------------------------------------------------------------
always @(*) begin
case (ex_alu_operation)
`ALU_OP_DIV : hilo_access = 1\'b1;
`ALU_OP_DIVU : hilo_access = 1\'b1;
`ALU_OP_MULS : hilo_access = 1\'b1;
`ALU_OP_MULU : hilo_access = 1\'b1;
`ALU_OP_MADD : hilo_access = 1\'b1;
`ALU_OP_MADDU : hilo_access = 1\'b1;
`ALU_OP_MSUB : hilo_access = 1\'b1;
`ALU_OP_MSUBU : hilo_access = 1\'b1;
`ALU_OP_MTHI : hilo_access = 1\'b1;
`ALU_OP_MTLO : hilo_access = 1\'b1;
`ALU_OP_MFHI : hilo_access = 1\'b1;
`ALU_OP_MFLO : hilo_access = 1\'b1;
default : hilo_access = 1\'b0;
endcase
end
//--------------------------------------------------------------------------
// Count Leading Ones/Zeros
//--------------------------------------------------------------------------
generate
// Hardware CLO_CLZ
if (ENABLE_HW_CLOZ) begin
antares_cloz cloz(/*AUTOINST*/
// Outputs
.clo_result (clo_result[5:0]),
.clz_result (clz_result[5:0]),
// Inputs
.A (A[31:0]));
end
// Disable
else begin
assign clo_result = 6\'dx;
assign clz_result = 6\'bx;
end // else: !if(ENABLE_HW_CLOZ)
endgenerate
//--------------------------------------------------------------------------
// Shifter: instantiation
//--------------------------------------------------------------------------
antares_shifter shifter(/*AUTOINST*/
// Outputs
.shift_result (shift_result[31:0]),
// Inputs
.shift_input_data (shift_input_data[31:0]),
.shift_shamnt (shift_shamnt[4:0]),
.shift_direction (shift_direction),
.shift_sign_extend (shift_sign_extend));
//--------------------------------------------------------------------------
// 32 x 32 bits multiplier: instantiation
//--------------------------------------------------------------------------
generate
// Hardware multiplier
if (ENABLE_HW_MULT) begin
antares_multiplier mult(// Inputs
.flush (ex_flush),
/*AUTOINST*/
// Outputs
.mult_result (mult_result[63:0]),
.mult_active (mult_active),
.mult_ready (mult_ready),
// Inputs
.clk (clk),
.rst (rst),
.mult_input_a (mult_input_a[31:0]),
.mult_input_b (mult_input_b[31:0]),
.mult_signed_op (mult_signed_op),
.mult_enable_op (mult_enable_op),
.mult_stall (mult_stall));
end // if (ENABLE_HW_MULT)
// No hardware multiplier
else begin
assign mult_result = 64\'h0; // disabled
assign mult_active = 1\'b0; // disabled
assign mult_ready = 1\'b0; // disabled
end // else: !if(ENABLE_HW_MULT)
endgenerate
//--------------------------------------------------------------------------
// instantiate the divider unit
//--------------------------------------------------------------------------
generate
// Hardware divider
if (ENABLE_HW_DIV) begin
antares_divider divider(/*AUTOINST*/
// Outputs
.quotient (quotient[31:0]),
.remainder (remainder[31:0]),
.div_stall (div_stall),
// Inputs
.clk (clk),
.rst (rst),
.op_divs (op_divs),
.op_divu (op_divu),
.dividend (dividend[31:0]),
.divisor (divisor[31:0]));
end // if (ENABLE_HW_DIV)
// No hardware divider
else begin
assign quotient = 32\'h0; // disabled
assign remainder = 32\'h0; // disabled
assign div_stall = 1\'b0; // disabled
end // else: !if(ENABLE_HW_DIV)
endgenerate
endmodule // antares_alu
|
//==================================================================================================
// Filename : antares_cloz.v
// Created On : Thu Sep 3 16:03:13 2015
// Last Modified : Sat Nov 07 11:49:40 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Sim\xc3\xb3n Bol\xc3\xadvar
// Email : [email protected]
//
// Description : Count leading ones/zeros unit.
//==================================================================================================
module antares_cloz (
input [31:0] A,
output [5:0] clo_result,
output [5:0] clz_result
);
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [5:0] clo_result;
reg [5:0] clz_result;
// End of automatics
//--------------------------------------------------------------------------
// Count Leading Ones
//--------------------------------------------------------------------------
always @(*) begin
casez (A)
32'b0zzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd0;
32'b10zz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd1;
32'b110z_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd2;
32'b1110_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd3;
32'b1111_0zzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd4;
32'b1111_10zz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd5;
32'b1111_110z_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd6;
32'b1111_1110_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd7;
32'b1111_1111_0zzz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd8;
32'b1111_1111_10zz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd9;
32'b1111_1111_110z_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd10;
32'b1111_1111_1110_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd11;
32'b1111_1111_1111_0zzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd12;
32'b1111_1111_1111_10zz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd13;
32'b1111_1111_1111_110z_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd14;
32'b1111_1111_1111_1110_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd15;
32'b1111_1111_1111_1111_0zzz_zzzz_zzzz_zzzz : clo_result = 6'd16;
32'b1111_1111_1111_1111_10zz_zzzz_zzzz_zzzz : clo_result = 6'd17;
32'b1111_1111_1111_1111_110z_zzzz_zzzz_zzzz : clo_result = 6'd18;
32'b1111_1111_1111_1111_1110_zzzz_zzzz_zzzz : clo_result = 6'd19;
32'b1111_1111_1111_1111_1111_0zzz_zzzz_zzzz : clo_result = 6'd20;
32'b1111_1111_1111_1111_1111_10zz_zzzz_zzzz : clo_result = 6'd21;
32'b1111_1111_1111_1111_1111_110z_zzzz_zzzz : clo_result = 6'd22;
32'b1111_1111_1111_1111_1111_1110_zzzz_zzzz : clo_result = 6'd23;
32'b1111_1111_1111_1111_1111_1111_0zzz_zzzz : clo_result = 6'd24;
32'b1111_1111_1111_1111_1111_1111_10zz_zzzz : clo_result = 6'd25;
32'b1111_1111_1111_1111_1111_1111_110z_zzzz : clo_result = 6'd26;
32'b1111_1111_1111_1111_1111_1111_1110_zzzz : clo_result = 6'd27;
32'b1111_1111_1111_1111_1111_1111_1111_0zzz : clo_result = 6'd28;
32'b1111_1111_1111_1111_1111_1111_1111_10zz : clo_result = 6'd29;
32'b1111_1111_1111_1111_1111_1111_1111_110z : clo_result = 6'd30;
32'b1111_1111_1111_1111_1111_1111_1111_1110 : clo_result = 6'd31;
32'b1111_1111_1111_1111_1111_1111_1111_1111 : clo_result = 6'd32;
default : clo_result = 6'd0;
endcase // casez (A)
end // always @ (*)
//--------------------------------------------------------------------------
// Count Leading Zeros
//--------------------------------------------------------------------------
always @(*) begin
casez (A)
32'b1zzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd0;
32'b01zz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd1;
32'b001z_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd2;
32'b0001_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd3;
32'b0000_1zzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd4;
32'b0000_01zz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd5;
32'b0000_001z_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd6;
32'b0000_0001_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd7;
32'b0000_0000_1zzz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd8;
32'b0000_0000_01zz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd9;
32'b0000_0000_001z_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd10;
32'b0000_0000_0001_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd11;
32'b0000_0000_0000_1zzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd12;
32'b0000_0000_0000_01zz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd13;
32'b0000_0000_0000_001z_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd14;
32'b0000_0000_0000_0001_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd15;
32'b0000_0000_0000_0000_1zzz_zzzz_zzzz_zzzz : clz_result = 6'd16;
32'b0000_0000_0000_0000_01zz_zzzz_zzzz_zzzz : clz_result = 6'd17;
32'b0000_0000_0000_0000_001z_zzzz_zzzz_zzzz : clz_result = 6'd18;
32'b0000_0000_0000_0000_0001_zzzz_zzzz_zzzz : clz_result = 6'd19;
32'b0000_0000_0000_0000_0000_1zzz_zzzz_zzzz : clz_result = 6'd20;
32'b0000_0000_0000_0000_0000_01zz_zzzz_zzzz : clz_result = 6'd21;
32'b0000_0000_0000_0000_0000_001z_zzzz_zzzz : clz_result = 6'd22;
32'b0000_0000_0000_0000_0000_0001_zzzz_zzzz : clz_result = 6'd23;
32'b0000_0000_0000_0000_0000_0000_1zzz_zzzz : clz_result = 6'd24;
32'b0000_0000_0000_0000_0000_0000_01zz_zzzz : clz_result = 6'd25;
32'b0000_0000_0000_0000_0000_0000_001z_zzzz : clz_result = 6'd26;
32'b0000_0000_0000_0000_0000_0000_0001_zzzz : clz_result = 6'd27;
32'b0000_0000_0000_0000_0000_0000_0000_1zzz : clz_result = 6'd28;
32'b0000_0000_0000_0000_0000_0000_0000_01zz : clz_result = 6'd29;
32'b0000_0000_0000_0000_0000_0000_0000_001z : clz_result = 6'd30;
32'b0000_0000_0000_0000_0000_0000_0000_0001 : clz_result = 6'd31;
32'b0000_0000_0000_0000_0000_0000_0000_0000 : clz_result = 6'd32;
default : clz_result = 6'd0;
endcase // casez (A)
end // always @ (*)
endmodule // antares_cloz
|
//==================================================================================================
// Filename : antares_idex_register.v
// Created On : Sat Sep 5 21:08:59 2015
// Last Modified : Sat Nov 07 12:09:34 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Sim\xc3\xb3n Bol\xc3\xadvar
// Email : [email protected]
//
// Description : Pipeline register: ID -> EX
//==================================================================================================
module antares_idex_register (
input clk, // Main clock
input rst, // Main reset
input [4:0] id_alu_operation, // ALU operation from ID stage
input [31:0] id_data_rs, // Data Rs (forwarded)
input [31:0] id_data_rt, // Data Rt (forwarded)
input id_gpr_we, // GPR write enable
input id_mem_to_gpr_select, // Select MEM/ALU to GPR
input id_mem_write, // write to memory
input [1:0] id_alu_port_a_select, // Select: GPR, shamt, 0x00000004
input [1:0] id_alu_port_b_select, // Select: GPR, Imm16, PCAdd4
input [1:0] id_gpr_wa_select, // Select: direccion: Rt, Rd, $31
input id_mem_byte, // byte access
input id_mem_halfword, // halfword access
input id_mem_data_sign_ext, // Zero/Sign extend
input [4:0] id_rs, // Rs
input [4:0] id_rt, // Rt
input [3:0] id_dp_hazard,
input id_imm_sign_ext, // extend the imm16
input [15:0] id_sign_imm16, // sign_ext(imm16)
input [31:0] id_cp0_data, //
input [31:0] id_exception_pc, // Current PC
input id_movn,
input id_movz,
input id_llsc,
input id_kernel_mode,
input id_is_bds,
input id_trap,
input id_trap_condition,
input id_ex_exception_source,
input id_mem_exception_source,
input id_flush, // clean
input id_stall, // Stall ID stage
input ex_stall, // Stall EX stage
output reg [4:0] ex_alu_operation, // Same signals, but on EX stage
output reg [31:0] ex_data_rs, //
output reg [31:0] ex_data_rt, //
output reg ex_gpr_we, //
output reg ex_mem_to_gpr_select, //
output reg ex_mem_write, //
output reg [1:0] ex_alu_port_a_select, //
output reg [1:0] ex_alu_port_b_select, //
output reg [1:0] ex_gpr_wa_select, //
output reg ex_mem_byte, //
output reg ex_mem_halfword, //
output reg ex_mem_data_sign_ext, //
output reg [4:0] ex_rs, //
output reg [4:0] ex_rt, //
output reg [3:0] ex_dp_hazard,
output reg [16:0] ex_sign_imm16, //
output reg [31:0] ex_cp0_data,
output reg [31:0] ex_exception_pc,
output reg ex_movn,
output reg ex_movz,
output reg ex_llsc,
output reg ex_kernel_mode,
output reg ex_is_bds,
output reg ex_trap,
output reg ex_trap_condition,
output reg ex_ex_exception_source,
output reg ex_mem_exception_source
);
// sign extend the imm16
wire [16:0] id_imm_extended = (id_imm_sign_ext) ? {id_sign_imm16[15], id_sign_imm16[15:0]} : {1'b0, id_sign_imm16};
//--------------------------------------------------------------------------
// Propagate signals
// Clear only critical signals: op, WE, MEM write and Next PC
//--------------------------------------------------------------------------
always @(posedge clk) begin
ex_alu_operation <= (rst) ? 5'b0 : ((ex_stall & ~id_flush) ? ex_alu_operation : ((id_stall | id_flush) ? 5'b0 : id_alu_operation));
ex_data_rs <= (rst) ? 32'b0 : ((ex_stall & ~id_flush) ? ex_data_rs : id_data_rs);
ex_data_rt <= (rst) ? 32'b0 : ((ex_stall & ~id_flush) ? ex_data_rt : id_data_rt);
ex_gpr_we <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_gpr_we : ((id_stall | id_flush) ? 1'b0 : id_gpr_we));
ex_mem_to_gpr_select <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_mem_to_gpr_select : ((id_stall | id_flush) ? 1'b0 : id_mem_to_gpr_select));
ex_mem_write <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_mem_write : ((id_stall | id_flush) ? 1'b0 : id_mem_write));
ex_alu_port_a_select <= (rst) ? 2'b0 : ((ex_stall & ~id_flush) ? ex_alu_port_a_select : id_alu_port_a_select);
ex_alu_port_b_select <= (rst) ? 2'b0 : ((ex_stall & ~id_flush) ? ex_alu_port_b_select : id_alu_port_b_select);
ex_gpr_wa_select <= (rst) ? 2'b0 : ((ex_stall & ~id_flush) ? ex_gpr_wa_select : id_gpr_wa_select);
ex_mem_byte <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_mem_byte : id_mem_byte);
ex_mem_halfword <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_mem_halfword : id_mem_halfword);
ex_mem_data_sign_ext <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_mem_data_sign_ext : id_mem_data_sign_ext);
ex_rs <= (rst) ? 5'b0 : ((ex_stall & ~id_flush) ? ex_rs : id_rs);
ex_rt <= (rst) ? 5'b0 : ((ex_stall & ~id_flush) ? ex_rt : id_rt);
ex_dp_hazard <= (rst) ? 4'b0 : ((ex_stall & ~id_flush) ? ex_dp_hazard : ((id_stall | id_flush) ? 4'b0 : id_dp_hazard));
ex_sign_imm16 <= (rst) ? 17'b0 : ((ex_stall & ~id_flush) ? ex_sign_imm16 : id_imm_extended);
ex_cp0_data <= (rst) ? 32'b0 : ((ex_stall & ~id_flush) ? ex_cp0_data : id_cp0_data);
ex_exception_pc <= (rst) ? 32'b0 : ((ex_stall & ~id_flush) ? ex_exception_pc : id_exception_pc);
ex_movn <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_movn : ((id_stall | id_flush) ? 1'b0 : id_movn));
ex_movz <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_movz : ((id_stall | id_flush) ? 1'b0 : id_movz));
ex_llsc <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_llsc : id_llsc);
ex_kernel_mode <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_kernel_mode : id_kernel_mode);
ex_is_bds <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_is_bds : id_is_bds);
ex_trap <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_trap : ((id_stall | id_flush) ? 1'b0 : id_trap));
ex_trap_condition <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_trap_condition : id_trap_condition);
ex_ex_exception_source <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_ex_exception_source : ((id_stall | id_flush) ? 1'b0 : id_ex_exception_source));
ex_mem_exception_source <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_mem_exception_source : ((id_stall | id_flush) ? 1'b0 : id_mem_exception_source));
end // always @ (posedge clk)
endmodule // antares_idex_register
|
//==================================================================================================
// Filename : antares_multiplier.v
// Created On : Wed Sep 2 22:05:36 2015
// Last Modified : Sat Nov 07 12:11:51 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Sim\xc3\xb3n Bol\xc3\xadvar
// Email : [email protected]
//
// Description : 32 x 32 pipelined multiplier.
// For signed operations: invert, perform unsigned mult, set result sign.
//==================================================================================================
module antares_multiplier(
input clk, // clock
input rst, // reset
input [31:0] mult_input_a, // Data
input [31:0] mult_input_b, // Data
input mult_signed_op, // Unsigned (0) or signed operation (1)
input mult_enable_op, // Signal a valid operation
input mult_stall, // Freeze the pipeline
input flush, // Flush the pipeline
output [63:0] mult_result, // Result
output mult_active, // Active operations @ pipeline
output mult_ready // Valid data on output port (result)
);
//--------------------------------------------------------------------------
// Signal Declaration: reg
//--------------------------------------------------------------------------
reg [32:0] A;
reg [32:0] B;
reg [31:0] result_ll_0;
reg [31:0] result_lh_0;
reg [31:0] result_hl_0;
reg [31:0] result_hh_0; // keep only 32 bits (ISE Warning)
reg [31:0] result_ll_1;
reg [31:0] result_hh_1; // keep only 32 bits (ISE Warning)
reg [32:0] result_mid_1;
reg [63:0] result_mult;
reg active0; // Pipeline the enable signal, so HDU can know if a valid operation is in the pipeline
reg active1;
reg active2;
reg active3;
reg sign_result0;
reg sign_result1;
reg sign_result2;
reg sign_result3;
///-------------------------------------------------------------------------
// Signal Declaration: wire
//--------------------------------------------------------------------------
wire sign_a;
wire sign_b;
wire [47:0] partial_sum;
wire [32:0] a_sign_ext;
wire [32:0] b_sign_ext;
//--------------------------------------------------------------------------
// assignments
//--------------------------------------------------------------------------
assign sign_a = (mult_signed_op) ? mult_input_a[31] : 1'b0;
assign sign_b = (mult_signed_op) ? mult_input_b[31] : 1'b0;
assign a_sign_ext = {sign_a, mult_input_a};
assign b_sign_ext = {sign_b, mult_input_b};
assign partial_sum = {15'b0, result_mid_1} + {result_hh_1[31:0], result_ll_1[31:16]};
assign mult_result = (sign_result3) ? -result_mult : result_mult; // Set true sign.
assign mult_ready = active3;
assign mult_active = active0 | active1 | active2 | active3; // 4th stage holds the result
//--------------------------------------------------------------------------
// Implement the pipeline
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst | flush) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
A <= 33'h0;
B <= 33'h0;
active0 <= 1'h0;
active1 <= 1'h0;
active2 <= 1'h0;
active3 <= 1'h0;
result_hh_0 <= 32'h0;
result_hh_1 <= 32'h0;
result_hl_0 <= 32'h0;
result_lh_0 <= 32'h0;
result_ll_0 <= 32'h0;
result_ll_1 <= 32'h0;
result_mid_1 <= 33'h0;
result_mult <= 64'h0;
sign_result0 <= 1'h0;
sign_result1 <= 1'h0;
sign_result2 <= 1'h0;
sign_result3 <= 1'h0;
// End of automatics
end
else if(~mult_stall) begin
// --- first stage
// Change sign. Perform unsigned multiplication. Save the result sign.
A <= sign_a ? -a_sign_ext : a_sign_ext;
B <= sign_b ? -b_sign_ext : b_sign_ext;
sign_result0 <= sign_a ^ sign_b;
active0 <= mult_enable_op;
// --- second stage
result_ll_0 <= A[15:0] * B[15:0]; // 16 x 16
result_lh_0 <= A[15:0] * B[32:16]; // 16 x 17
result_hl_0 <= A[32:16] * B[15:0]; // 17 x 16
result_hh_0 <= A[31:16] * B[31:16]; // 16 x 16
sign_result1 <= sign_result0;
active1 <= active0;
// --- third stage
result_ll_1 <= result_ll_0;
result_hh_1 <= result_hh_0;
result_mid_1 <= result_lh_0 + result_hl_0; // sum mid
sign_result2 <= sign_result1;
active2 <= active1;
// -- fourth stage
result_mult <= {partial_sum, result_ll_1[15:0]};
sign_result3 <= sign_result2;
active3 <= active2;
end
end
endmodule
|
//==================================================================================================
// Filename : antares_core.v
// Created On : Sat Sep 5 21:45:33 2015
// Last Modified : Sat Nov 07 11:56:09 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Sim\xc3\xb3n Bol\xc3\xadvar
// Email : [email protected]
//
// Description : Antares core.
//==================================================================================================
`include "antares_defines.v"
module antares_core #(parameter ENABLE_HW_MULT = 1,
parameter ENABLE_HW_DIV = 1,
parameter ENABLE_HW_CLOZ = 1
)(
input clk,
input rst,
output halted, // CP0 Status Register, bit 16
// Interrupts
input [4:0] interrupts, // External interrupts
input nmi, // Non-maskable interrupt
// External Instruction Memory/Instruction Cache
input [31:0] iport_data_i, // Data from memory
input iport_ready, // memory is ready
input iport_error, // Bus error
output [31:0] iport_address, // data address
output [3:0] iport_wr, // write = byte select, read = 0000,
output iport_enable, // enable operation
// External Data Memory/Data Cache
input [31:0] dport_data_i, // Data from memory
input dport_ready, // memory is ready
input dport_error, // Bus error
output [31:0] dport_address, // data address
output [31:0] dport_data_o, // data to memory
output [3:0] dport_wr, // write = byte select, read = 0000,
output dport_enable // enable operation
);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] cp0_data_output; // From cpzero0 of antares_cpzero.v
wire dmem_request_stall; // From load_store_unit0 of antares_load_store_unit.v
wire [7:0] dp_hazard; // From control_unit0 of antares_control_unit.v
wire [4:0] ex_alu_operation; // From IDEX_register of antares_idex_register.v
wire [1:0] ex_alu_port_a_select; // From IDEX_register of antares_idex_register.v
wire [1:0] ex_alu_port_b_select; // From IDEX_register of antares_idex_register.v
wire [31:0] ex_data_rs; // From IDEX_register of antares_idex_register.v
wire [31:0] ex_data_rt; // From IDEX_register of antares_idex_register.v
wire [3:0] ex_dp_hazard; // From IDEX_register of antares_idex_register.v
wire ex_flush; // From cpzero0 of antares_cpzero.v
wire [1:0] ex_gpr_wa_select; // From IDEX_register of antares_idex_register.v
wire ex_gpr_we; // From IDEX_register of antares_idex_register.v
wire ex_mem_byte; // From IDEX_register of antares_idex_register.v
wire ex_mem_data_sign_ext; // From IDEX_register of antares_idex_register.v
wire ex_mem_halfword; // From IDEX_register of antares_idex_register.v
wire ex_mem_to_gpr_select; // From IDEX_register of antares_idex_register.v
wire ex_mem_write; // From IDEX_register of antares_idex_register.v
wire [4:0] ex_rs; // From IDEX_register of antares_idex_register.v
wire [4:0] ex_rt; // From IDEX_register of antares_idex_register.v
wire [16:0] ex_sign_imm16; // From IDEX_register of antares_idex_register.v
wire ex_stall; // From hazard_unit0 of antares_hazard_unit.v
wire exc_address_if; // From load_store_unit0 of antares_load_store_unit.v
wire exc_address_l_mem; // From load_store_unit0 of antares_load_store_unit.v
wire exc_address_s_mem; // From load_store_unit0 of antares_load_store_unit.v
wire exc_syscall; // From control_unit0 of antares_control_unit.v
wire [1:0] forward_ex_rs; // From hazard_unit0 of antares_hazard_unit.v
wire [1:0] forward_ex_rt; // From hazard_unit0 of antares_hazard_unit.v
wire [1:0] forward_id_rs; // From hazard_unit0 of antares_hazard_unit.v
wire [1:0] forward_id_rt; // From hazard_unit0 of antares_hazard_unit.v
wire [4:0] id_alu_operation; // From control_unit0 of antares_control_unit.v
wire [1:0] id_alu_port_a_select; // From control_unit0 of antares_control_unit.v
wire [1:0] id_alu_port_b_select; // From control_unit0 of antares_control_unit.v
wire id_branch; // From control_unit0 of antares_control_unit.v
wire id_flush; // From cpzero0 of antares_cpzero.v
wire [1:0] id_gpr_wa_select; // From control_unit0 of antares_control_unit.v
wire id_gpr_we; // From control_unit0 of antares_control_unit.v
wire [31:0] id_instruction; // From IFID_register of antares_ifid_register.v
wire id_jump; // From control_unit0 of antares_control_unit.v
wire id_mem_byte; // From control_unit0 of antares_control_unit.v
wire id_mem_data_sign_ext; // From control_unit0 of antares_control_unit.v
wire id_mem_halfword; // From control_unit0 of antares_control_unit.v
wire id_mem_to_gpr_select; // From control_unit0 of antares_control_unit.v
wire id_mem_write; // From control_unit0 of antares_control_unit.v
wire [31:0] id_pc_add4; // From IFID_register of antares_ifid_register.v
wire id_stall; // From hazard_unit0 of antares_hazard_unit.v
wire id_take_branch; // From branch_unit0 of antares_branch_unit.v
wire if_flush; // From cpzero0 of antares_cpzero.v
wire [31:0] if_new_pc; // From pc_source_exception of antares_mux_2_1.v
wire [31:0] if_pc; // From pc_register of antares_pc_register.v
wire [31:0] if_pc_add4; // From pc_add4 of antares_add.v
wire if_stall; // From hazard_unit0 of antares_hazard_unit.v
wire imem_request_stall; // From load_store_unit0 of antares_load_store_unit.v
wire [31:0] mem_alu_result; // From EXMEM_register of antares_exmem_register.v
wire mem_flush; // From cpzero0 of antares_cpzero.v
wire [4:0] mem_gpr_wa; // From EXMEM_register of antares_exmem_register.v
wire mem_gpr_we; // From EXMEM_register of antares_exmem_register.v
wire mem_mem_byte; // From EXMEM_register of antares_exmem_register.v
wire mem_mem_data_sign_ext; // From EXMEM_register of antares_exmem_register.v
wire mem_mem_halfword; // From EXMEM_register of antares_exmem_register.v
wire [31:0] mem_mem_store_data; // From EXMEM_register of antares_exmem_register.v
wire mem_mem_to_gpr_select; // From EXMEM_register of antares_exmem_register.v
wire mem_mem_write; // From EXMEM_register of antares_exmem_register.v
wire mem_stall; // From hazard_unit0 of antares_hazard_unit.v
wire [31:0] pc_branch_address; // From branch_unit0 of antares_branch_unit.v
wire [31:0] wb_alu_data; // From MEMWB_register of antares_memwb_register.v
wire [4:0] wb_gpr_wa; // From MEMWB_register of antares_memwb_register.v
wire wb_gpr_we; // From MEMWB_register of antares_memwb_register.v
wire wb_mem_to_gpr_select; // From MEMWB_register of antares_memwb_register.v
wire [31:0] wb_read_data; // From MEMWB_register of antares_memwb_register.v
wire wb_stall; // From hazard_unit0 of antares_hazard_unit.v
// End of automatics
// manual wires
wire [5:0] opcode;
wire [4:0] op_rs;
wire [4:0] op_rt;
wire [4:0] op_rd;
wire [5:0] op_function;
wire [15:0] op_imm16;
wire [25:0] op_imm26;
wire [2:0] op_cp0_select;
wire [31:0] if_instruction;
wire [31:0] id_gpr_rs;
wire [31:0] id_gpr_rt;
wire [31:0] wb_gpr_wd;
wire [31:0] id_forward_rs;
wire [31:0] id_forward_rt;
wire [31:0] ex_forward_rs;
wire [31:0] ex_forward_rt;
wire [31:0] ex_alu_result;
wire ex_request_stall;
wire [31:0] ex_alu_port_a;
wire [31:0] ex_alu_port_b;
wire [4:0] ex_gpr_wa;
wire [31:0] mem_read_data;
wire halt_0;
reg halt_1;
reg halt_2;
reg halt_3;
wire id_mfc0;
wire id_mtc0;
wire id_eret;
wire id_cp1_instruction;
wire id_cp2_instruction;
wire id_cp3_instruction;
wire exc_overflow;
wire exc_trap;
wire exc_breakpoint;
wire exc_reserved;
wire [31:0] id_exception_pc;
wire [31:0] ex_exception_pc;
wire [31:0] mem_exception_pc;
wire id_exception_source;
wire ex_exception_source;
wire mem_exception_source;
wire id_is_flushed;
wire if_is_bds;
wire id_is_bds;
wire ex_is_bds;
wire mem_is_bds;
wire id_kernel_mode;
wire ex_kernel_mode;
wire mem_kernel_mode;
wire if_exception_stall;
wire id_exception_stall;
wire ex_exception_stall;
wire mem_exception_stall;
wire exception_pc_select;
wire [31:0] pc_exception;
wire [31:0] pc_pre_exc_selection;
wire id_llsc;
wire ex_llsc;
wire mem_llsc;
wire id_movn;
wire id_movz;
wire ex_movn;
wire ex_movz;
wire ex_b_is_zero;
wire id_trap;
wire ex_trap;
wire id_trap_condition;
wire ex_trap_condition;
wire mem_trap;
wire mem_trap_condition;
wire id_id_exception_source;
wire id_ex_exception_source;
wire id_mem_exception_source;
wire ex_ex_exception_source;
wire ex_mem_exception_source;
wire mem_mem_exception_source;
wire id_imm_sign_ext;
wire [31:0] ex_cp0_data;
wire exception_ready;
wire pc_source_select;
wire if_stall_pc_register;
wire [7:0] haz_dp_hazards;
//--------------------------------------------------------------------------
// assignments
//--------------------------------------------------------------------------
assign opcode = id_instruction[`ANTARES_INSTR_OPCODE];
assign op_rs = id_instruction[`ANTARES_INSTR_RS];
assign op_rt = id_instruction[`ANTARES_INSTR_RT];
assign op_rd = id_instruction[`ANTARES_INSTR_RD];
assign op_function = id_instruction[`ANTARES_INSTR_FUNCT];
assign op_imm16 = id_instruction[`ANTARES_INSTR_IMM16];
assign op_imm26 = id_instruction[`ANTARES_INSTR_IMM26];
assign op_cp0_select = id_instruction[`ANTARES_INSTR_CP0_SEL];
assign id_exception_source = id_id_exception_source | id_ex_exception_source | id_mem_exception_source;
assign ex_exception_source = ex_ex_exception_source | ex_mem_exception_source;
assign mem_exception_source = mem_mem_exception_source;
assign if_is_bds = id_take_branch;
assign exc_trap = mem_trap & (mem_trap_condition ^ (mem_alu_result == 32\'b0));
assign pc_source_select = (id_take_branch & id_branch) | id_jump;
assign if_stall_pc_register = if_stall | id_stall | halt_0;
assign haz_dp_hazards = {dp_hazard[7:4], ex_dp_hazard};
//------------------------------------------------------------------------------------------------------------------
// UPDATE: Getting the halt signal from the CP0.
always @(posedge clk) begin
if (rst) begin
halt_1 <= 1\'b0;
halt_2 <= 1\'b0;
halt_3 <= 1\'b0;
end
else begin
halt_1 <= halt_0;
halt_2 <= halt_1;
halt_3 <= halt_2;
end
end // always @ (posedge clk)
assign halted = halt_3;
//--------------------------------------------------------------------------
// IF stage (A)
//--------------------------------------------------------------------------
antares_mux_2_1 pc_source(// Outputs
.out (pc_pre_exc_selection[31:0]),
// Inputs
.in0 (if_pc_add4[31:0]),
.in1 (pc_branch_address[31:0]),
.select (pc_source_select)
/*AUTOINST*/);
antares_mux_2_1 pc_source_exception (// Outputs
.out (if_new_pc[31:0]),
// Inputs
.in0 (pc_pre_exc_selection[31:0]),
.in1 (pc_exception[31:0]),
.select (exception_pc_select)
/*AUTOINST*/);
antares_pc_register pc_register (// Inputs
.if_stall (if_stall_pc_register),
/*AUTOINST*/
// Outputs
.if_pc (if_pc[31:0]),
// Inputs
.clk (clk),
.rst (rst),
.if_new_pc (if_new_pc[31:0]));
//--------------------------------------------------------------------------
// IF stage (B)
//--------------------------------------------------------------------------
antares_add pc_add4 (// Outputs
.c (if_pc_add4[31:0]),
// Inputs
.a (if_pc[31:0]),
.b (32\'d4)
/*AUTOINST*/);
antares_ifid_register IFID_register (// Inputs
.if_exception_pc (if_pc[31:0]),
/*AUTOINST*/
// Outputs
.id_instruction (id_instruction[31:0]),
.id_pc_add4 (id_pc_add4[31:0]),
.id_exception_pc (id_exception_pc[31:0]),
.id_is_bds (id_is_bds),
.id_is_flushed (id_is_flushed),
// Inputs
.clk (clk),
.rst (rst),
.if_instruction (if_instruction[31:0]),
.if_pc_add4 (if_pc_add4[31:0]),
.if_is_bds (if_is_bds),
.if_flush (if_flush),
.if_stall (if_stall),
.id_stall (id_stall));
//--------------------------------------------------------------------------
// ID stage
//--------------------------------------------------------------------------
antares_reg_file GPR (// Outputs
.gpr_rd_a (id_gpr_rs[31:0]),
.gpr_rd_b (id_gpr_rt[31:0]),
// Inputs
.clk (clk),
.gpr_ra_a (op_rs[4:0]),
.gpr_ra_b (op_rt[4:0]),
.gpr_wa (wb_gpr_wa[4:0]),
.gpr_wd (wb_gpr_wd[31:0]),
.gpr_we (wb_gpr_we)
/*AUTOINST*/);
antares_branch_unit branch_unit0 (// Inputs
.id_data_rs (id_forward_rs[31:0]),
.id_data_rt (id_forward_rt[31:0]),
/*AUTOINST*/
// Outputs
.pc_branch_address(pc_branch_address[31:0]),
.id_take_branch (id_take_branch),
// Inputs
.opcode (opcode[5:0]),
.id_pc_add4 (id_pc_add4[31:0]),
.op_imm26 (op_imm26[25:0]));
antares_control_unit #(/*AUTOINSTPARAM*/
// Parameters
.ENABLE_HW_MULT (ENABLE_HW_MULT),
.ENABLE_HW_DIV (ENABLE_HW_DIV),
.ENABLE_HW_CLOZ (ENABLE_HW_CLOZ))
control_unit0 (// Outputs
.id_syscall (exc_syscall),
.id_breakpoint (exc_breakpoint),
.id_reserved (exc_reserved),
/*AUTOINST*/
// Outputs
.dp_hazard (dp_hazard[7:0]),
.id_imm_sign_ext (id_imm_sign_ext),
.id_movn (id_movn),
.id_movz (id_movz),
.id_llsc (id_llsc),
.id_mfc0 (id_mfc0),
.id_mtc0 (id_mtc0),
.id_eret (id_eret),
.id_cp1_instruction (id_cp1_instruction),
.id_cp2_instruction (id_cp2_instruction),
.id_cp3_instruction (id_cp3_instruction),
.id_id_exception_source (id_id_exception_source),
.id_ex_exception_source (id_ex_exception_source),
.id_mem_exception_source (id_mem_exception_source),
.id_trap (id_trap),
.id_trap_condition (id_trap_condition),
.id_gpr_we (id_gpr_we),
.id_mem_to_gpr_select (id_mem_to_gpr_select),
.id_alu_operation (id_alu_operation[4:0]),
.id_alu_port_a_select (id_alu_port_a_select[1:0]),
.id_alu_port_b_select (id_alu_port_b_select[1:0]),
.id_gpr_wa_select (id_gpr_wa_select[1:0]),
.id_jump (id_jump),
.id_branch (id_branch),
.id_mem_write (id_mem_write),
.id_mem_byte (id_mem_byte),
.id_mem_halfword (id_mem_halfword),
.id_mem_data_sign_ext (id_mem_data_sign_ext),
// Inputs
.opcode (opcode[5:0]),
.op_function (op_function[5:0]),
.op_rs (op_rs[4:0]),
.op_rt (op_rt[4:0]));
antares_mux_4_1 ForwardRsID (// Outputs
.out (id_forward_rs[31:0]),
// Inputs
.in0 (id_gpr_rs[31:0]),
.in1 (mem_alu_result[31:0]),
.in2 (wb_gpr_wd[31:0]),
.in3 (32\'bx),
.select (forward_id_rs[1:0])
/*AUTOINST*/);
antares_mux_4_1 ForwardRtID (// Outputs
.out (id_forward_rt[31:0]),
// Inputs
.in0 (id_gpr_rt[31:0]),
.in1 (mem_alu_result[31:0]),
.in2 (wb_gpr_wd[31:0]),
.in3 (32\'bx),
.select (forward_id_rt[1:0])
/*AUTOINST*/);
antares_idex_register IDEX_register (// Inputs
.id_data_rs (id_forward_rs[31:0]),
.id_data_rt (id_forward_rt[31:0]),
.id_sign_imm16 (op_imm16[15:0]),
.id_cp0_data (cp0_data_output[31:0]),
.id_rs (op_rs[4:0]),
.id_rt (op_rt[4:0]),
.id_dp_hazard (dp_hazard[3:0]),
/*AUTOINST*/
// Outputs
.ex_alu_operation (ex_alu_operation[4:0]),
.ex_data_rs (ex_data_rs[31:0]),
.ex_data_rt (ex_data_rt[31:0]),
.ex_gpr_we (ex_gpr_we),
.ex_mem_to_gpr_select (ex_mem_to_gpr_select),
.ex_mem_write (ex_mem_write),
.ex_alu_port_a_select (ex_alu_port_a_select[1:0]),
.ex_alu_port_b_select (ex_alu_port_b_select[1:0]),
.ex_gpr_wa_select (ex_gpr_wa_select[1:0]),
.ex_mem_byte (ex_mem_byte),
.ex_mem_halfword (ex_mem_halfword),
.ex_mem_data_sign_ext (ex_mem_data_sign_ext),
.ex_rs (ex_rs[4:0]),
.ex_rt (ex_rt[4:0]),
.ex_dp_hazard (ex_dp_hazard[3:0]),
.ex_sign_imm16 (ex_sign_imm16[16:0]),
.ex_cp0_data (ex_cp0_data[31:0]),
.ex_exception_pc (ex_exception_pc[31:0]),
.ex_movn (ex_movn),
.ex_movz (ex_movz),
.ex_llsc (ex_llsc),
.ex_kernel_mode (ex_kernel_mode),
.ex_is_bds (ex_is_bds),
.ex_trap (ex_trap),
.ex_trap_condition (ex_trap_condition),
.ex_ex_exception_source (ex_ex_exception_source),
.ex_mem_exception_source (ex_mem_exception_source),
// Inputs
.clk (clk),
.rst (rst),
.id_alu_operation (id_alu_operation[4:0]),
.id_gpr_we (id_gpr_we),
.id_mem_to_gpr_select (id_mem_to_gpr_select),
.id_mem_write (id_mem_write),
.id_alu_port_a_select (id_alu_port_a_select[1:0]),
.id_alu_port_b_select (id_alu_port_b_select[1:0]),
.id_gpr_wa_select (id_gpr_wa_select[1:0]),
.id_mem_byte (id_mem_byte),
.id_mem_halfword (id_mem_halfword),
.id_mem_data_sign_ext (id_mem_data_sign_ext),
.id_imm_sign_ext (id_imm_sign_ext),
.id_exception_pc (id_exception_pc[31:0]),
.id_movn (id_movn),
.id_movz (id_movz),
.id_llsc (id_llsc),
.id_kernel_mode (id_kernel_mode),
.id_is_bds (id_is_bds),
.id_trap (id_trap),
.id_trap_condition (id_trap_condition),
.id_ex_exception_source (id_ex_exception_source),
.id_mem_exception_source (id_mem_exception_source),
.id_flush (id_flush),
.id_stall (id_stall),
.ex_stall (ex_stall));
//--------------------------------------------------------------------------
// EX stage
//--------------------------------------------------------------------------
antares_alu #(/*AUTOINSTPARAM*/
// Parameters
.ENABLE_HW_MULT (ENABLE_HW_MULT),
.ENABLE_HW_DIV (ENABLE_HW_DIV),
.ENABLE_HW_CLOZ (ENABLE_HW_CLOZ))
execution_unit (/*AUTOINST*/
// Outputs
.ex_request_stall (ex_request_stall),
.ex_alu_result (ex_alu_result[31:0]),
.ex_b_is_zero (ex_b_is_zero),
.exc_overflow (exc_overflow),
// Inputs
.clk (clk),
.rst (rst),
.ex_alu_port_a (ex_alu_port_a[31:0]),
.ex_alu_port_b (ex_alu_port_b[31:0]),
.ex_alu_operation (ex_alu_operation[4:0]),
.ex_stall (ex_stall),
.ex_flush (ex_flush));
antares_mux_4_1 forward_rs_ex (// Outputs
.out (ex_forward_rs[31:0]),
// Inputs
.in0 (ex_data_rs[31:0]),
.in1 (mem_alu_result[31:0]),
.in2 (wb_gpr_wd[31:0]),
.in3 (32\'bx),
.select (forward_ex_rs[1:0])
/*AUTOINST*/);
antares_mux_4_1 forward_rt_ex (// Outputs
.out (ex_forward_rt[31:0]),
// Inputs
.in0 (ex_data_rt[31:0]),
.in1 (mem_alu_result[31:0]),
.in2 (wb_gpr_wd[31:0]),
.in3 (32\'bx),
.select (forward_ex_rt[1:0])
/*AUTOINST*/);
antares_mux_4_1 ALUPortA (// Outputs
.out (ex_alu_port_a[31:0]),
// Inputs
.in0 (ex_forward_rs[31:0]),
.in1 ({27\'b0, ex_sign_imm16[10:6]}), // shamnt
.in2 (32\'d8), // PC + 8
.in3 (32\'d16),
.select (ex_alu_port_a_select[1:0])
/*AUTOINST*/);
antares_mux_4_1 ALUPortB (// Outputs
.out (ex_alu_port_b[31:0]),
// Inputs
.in0 (ex_forward_rt[31:0]),
.in1 ({{15{ex_sign_imm16[16]}}, ex_sign_imm16[16:0]}),
.in2 (ex_exception_pc[31:0]),
.in3 (ex_cp0_data[31:0]),
.select (ex_alu_port_b_select[1:0])
/*AUTOINST*/);
antares_mux_4_1 #(.WIDTH(5))
mux_reg_wa(// Outputs
.out (ex_gpr_wa[4:0]),
// Inputs
.in0 (ex_sign_imm16[15:11]), // Rd
.in1 (ex_rt[4:0]),
.in2 (5\'b11111), // $31 = $Ra
.in3 (5\'b00000), // NOP
.select (ex_gpr_wa_select[1:0])
/*AUTOINST*/);
antares_exmem_register EXMEM_register (// Inputs
.ex_mem_store_data (ex_forward_rt[31:0]),
/*AUTOINST*/
// Outputs
.mem_alu_result (mem_alu_result[31:0]),
.mem_mem_store_data (mem_mem_store_data[31:0]),
.mem_gpr_wa (mem_gpr_wa[4:0]),
.mem_gpr_we (mem_gpr_we),
.mem_mem_to_gpr_select (mem_mem_to_gpr_select),
.mem_mem_write (mem_mem_write),
.mem_mem_byte (mem_mem_byte),
.mem_mem_halfword (mem_mem_halfword),
.mem_mem_data_sign_ext (mem_mem_data_sign_ext),
.mem_exception_pc (mem_exception_pc[31:0]),
.mem_llsc (mem_llsc),
.mem_kernel_mode (mem_kernel_mode),
.mem_is_bds (mem_is_bds),
.mem_trap (mem_trap),
.mem_trap_condition (mem_trap_condition),
.mem_mem_exception_source (mem_mem_exception_source),
// Inputs
.clk (clk),
.rst (rst),
.ex_alu_result (ex_alu_result[31:0]),
.ex_gpr_wa (ex_gpr_wa[4:0]),
.ex_gpr_we (ex_gpr_we),
.ex_mem_to_gpr_select (ex_mem_to_gpr_select),
.ex_mem_write (ex_mem_write),
.ex_mem_byte (ex_mem_byte),
.ex_mem_halfword (ex_mem_halfword),
.ex_mem_data_sign_ext (ex_mem_data_sign_ext),
.ex_exception_pc (ex_exception_pc[31:0]),
.ex_movn (ex_movn),
.ex_movz (ex_movz),
.ex_b_is_zero (ex_b_is_zero),
.ex_llsc (ex_llsc),
.ex_kernel_mode (ex_kernel_mode),
.ex_is_bds (ex_is_bds),
.ex_trap (ex_trap),
.ex_trap_condition (ex_trap_condition),
.ex_mem_exception_source (ex_mem_exception_source),
.ex_flush (ex_flush),
.ex_stall (ex_stall),
.mem_stall (mem_stall));
//--------------------------------------------------------------------------
// MEM stage
//--------------------------------------------------------------------------
antares_memwb_register MEMWB_register (// Inputs
.mem_alu_data (mem_alu_result[31:0]),
/*AUTOINST*/
// Outputs
.wb_read_data (wb_read_data[31:0]),
.wb_alu_data (wb_alu_data[31:0]),
.wb_gpr_wa (wb_gpr_wa[4:0]),
.wb_mem_to_gpr_select (wb_mem_to_gpr_select),
.wb_gpr_we (wb_gpr_we),
// Inputs
.clk (clk),
.rst (rst),
.mem_read_data (mem_read_data[31:0]),
.mem_gpr_wa (mem_gpr_wa[4:0]),
.mem_mem_to_gpr_select (mem_mem_to_gpr_select),
.mem_gpr_we (mem_gpr_we),
.mem_flush (mem_flush),
.mem_stall (mem_stall),
.wb_stall (wb_stall));
//--------------------------------------------------------------------------
// WB stage
//--------------------------------------------------------------------------
antares_mux_2_1 mux_mem_ex_result (// Outputs
.out (wb_gpr_wd[31:0]),
// Inputs
.in0 (wb_alu_data[31:0]),
.in1 (wb_read_data[31:0]),
.select (wb_mem_to_gpr_select)
/*AUTOINST*/);
//--------------------------------------------------------------------------
// HDU, LSU and CP0
//--------------------------------------------------------------------------
antares_hazard_unit hazard_unit0 (// Inputs
.id_rs (op_rs[4:0]),
.id_rt (op_rt[4:0]),
.mem_mem_read (mem_mem_to_gpr_select),
.DP_Hazards (haz_dp_hazards[7:0]),
/*AUTOINST*/
// Outputs
.forward_id_rs (forward_id_rs[1:0]),
.forward_id_rt (forward_id_rt[1:0]),
.forward_ex_rs (forward_ex_rs[1:0]),
.forward_ex_rt (forward_ex_rt[1:0]),
.if_stall (if_stall),
.id_stall (id_stall),
.ex_stall (ex_stall),
.mem_stall (mem_stall),
.wb_stall (wb_stall),
// Inputs
.ex_rs (ex_rs[4:0]),
.ex_rt (ex_rt[4:0]),
.ex_gpr_wa (ex_gpr_wa[4:0]),
.mem_gpr_wa (mem_gpr_wa[4:0]),
.wb_gpr_wa (wb_gpr_wa[4:0]),
.ex_gpr_we (ex_gpr_we),
.mem_gpr_we (mem_gpr_we),
.wb_gpr_we (wb_gpr_we),
.mem_mem_write (mem_mem_write),
.ex_request_stall (ex_request_stall),
.dmem_request_stall (dmem_request_stall),
.imem_request_stall (imem_request_stall),
.if_exception_stall (if_exception_stall),
.id_exception_stall (id_exception_stall),
.ex_exception_stall (ex_exception_stall),
.mem_exception_stall (mem_exception_stall));
antares_load_store_unit load_store_unit0 (// Outputs
.imem_data (if_instruction[31:0]),
.dmem_data_o (mem_read_data[31:0]),
// Inputs
.imem_address (if_pc[31:0]),
.dmem_address (mem_alu_result[31:0]),
.dmem_data_i (mem_mem_store_data[31:0]),
.dmem_halfword (mem_mem_halfword),
.dmem_byte (mem_mem_byte),
.dmem_read (mem_mem_to_gpr_select),
.dmem_write (mem_mem_write),
.dmem_sign_extend (mem_mem_data_sign_ext),
/*AUTOINST*/
// Outputs
.iport_address (iport_address[31:0]),
.iport_wr (iport_wr[3:0]),
.iport_enable (iport_enable),
.dport_address (dport_address[31:0]),
.dport_data_o (dport_data_o[31:0]),
.dport_wr (dport_wr[3:0]),
.dport_enable (dport_enable),
.exc_address_if (exc_address_if),
.exc_address_l_mem (exc_address_l_mem),
.exc_address_s_mem (exc_address_s_mem),
.imem_request_stall (imem_request_stall),
.dmem_request_stall (dmem_request_stall),
// Inputs
.clk (clk),
.rst (rst),
.iport_data_i (iport_data_i[31:0]),
.iport_ready (iport_ready),
.iport_error (iport_error),
.dport_data_i (dport_data_i[31:0]),
.dport_ready (dport_ready),
.dport_error (dport_error),
.exception_ready (exception_ready),
.mem_kernel_mode (mem_kernel_mode),
.mem_llsc (mem_llsc),
.id_eret (id_eret));
antares_cpzero cpzero0 (// Outputs
.halt (halt_0),
// Inputs
.mfc0 (id_mfc0),
.mtc0 (id_mtc0),
.eret (id_eret),
.cp1_instruction (id_cp1_instruction),
.cp2_instruction (id_cp2_instruction),
.cp3_instruction (id_cp3_instruction),
.register_address (op_rd[4:0]),
.select (op_cp0_select[2:0]),
.data_input (id_forward_rt[31:0]),
.exc_nmi (nmi),
.exc_ibus_error (iport_error),
.exc_dbus_error (dport_error),
.bad_address_if (if_pc[31:0]),
.bad_address_mem (mem_alu_result[31:0]),
/*AUTOINST*/
// Outputs
.cp0_data_output (cp0_data_output[31:0]),
.id_kernel_mode (id_kernel_mode),
.if_exception_stall (if_exception_stall),
.id_exception_stall (id_exception_stall),
.ex_exception_stall (ex_exception_stall),
.mem_exception_stall (mem_exception_stall),
.if_flush (if_flush),
.id_flush (id_flush),
.ex_flush (ex_flush),
.mem_flush (mem_flush),
.exception_ready (exception_ready),
.exception_pc_select (exception_pc_select),
.pc_exception (pc_exception[31:0]),
// Inputs
.clk (clk),
.if_stall (if_stall),
.id_stall (id_stall),
.interrupts (interrupts[4:0]),
.rst (rst),
.exc_address_if (exc_address_if),
.exc_address_l_mem (exc_address_l_mem),
.exc_address_s_mem (exc_address_s_mem),
.exc_overflow (exc_overflow),
.exc_trap (exc_trap),
.exc_syscall (exc_syscall),
.exc_breakpoint (exc_breakpoint),
.exc_reserved (exc_reserved),
.id_exception_pc (id_exception_pc[31:0]),
.ex_exception_pc (ex_exception_pc[31:0]),
.mem_exception_pc (mem_exception_pc[31:0]),
.id_exception_source (id_exception_source),
.ex_exception_source (ex_exception_source),
.mem_exception_source (mem_exception_source),
.id_is_flushed (id_is_flushed),
.if_is_bds (if_is_bds),
.id_is_bds (id_is_bds),
.ex_is_bds (ex_is_bds),
.mem_is_bds (mem_is_bds));
endmodule // antares_core
|
//==================================================================================================
// Filename : antares_hazard_unit.v
// Created On : Fri Sep 4 22:32:20 2015
// Last Modified : Sat Nov 07 12:03:58 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Sim\xc3\xb3n Bol\xc3\xadvar
// Email : [email protected]
//
// Description : Hazard detection and pipeline control unit.
//==================================================================================================
`include "antares_defines.v"
module antares_hazard_unit (
input [7:0] DP_Hazards, //
input [4:0] id_rs, // Rs @ ID stage
input [4:0] id_rt, // Rt @ ID stage
input [4:0] ex_rs, // Rs @ EX stage
input [4:0] ex_rt, // Rt @ EX stage
input [4:0] ex_gpr_wa, // Write Address @ EX stage
input [4:0] mem_gpr_wa, // Write Address @ MEM stage
input [4:0] wb_gpr_wa, // Write Address @ WB stage
input ex_gpr_we, // GPR write enable @ EX
input mem_gpr_we, // GPR write enable @ MEM
input wb_gpr_we, // GPR write enable @ WB
input mem_mem_write, //
input mem_mem_read, //
input ex_request_stall, // Ex unit request a stall
input dmem_request_stall, // LSU: stall for Data access
input imem_request_stall, // LSU: stall for Instruction Fetch
input if_exception_stall, // Stall waiting for possible exception
input id_exception_stall, // Stall waiting for possible exception
input ex_exception_stall, // Stall waiting for possible exception
input mem_exception_stall, //
output [1:0] forward_id_rs, // Forwarding Rs multiplexer: Selector @ ID
output [1:0] forward_id_rt, // Forwarding Rt multiplexer: Selector @ ID
output [1:0] forward_ex_rs, // Forwarding Rs multiplexer: Selector @ EX
output [1:0] forward_ex_rt, // Forwarding Rt multiplexer: Selector @ EX
output if_stall, // Stall pipeline register
output id_stall, // Stall pipeline register
output ex_stall, // Stall pipeline register
//output ex_stall_unit; // Stall the EX unit.
output mem_stall, // Stall pipeline register
output wb_stall // Stall pipeline register
);
//--------------------------------------------------------------------------
// Signal Declaration: wire
//--------------------------------------------------------------------------
// no forwarding if reading register zero
wire ex_wa_nz;
wire mem_wa_nz;
wire wb_wa_nz;
// Need/Want signals
wire WantRsID;
wire WantRtID;
wire WantRsEX;
wire WantRtEX;
wire NeedRsID;
wire NeedRtID;
wire NeedRsEX;
wire NeedRtEX;
// verify match: register address and write address (EX, MEM & WB)
wire id_ex_rs_match;
wire id_ex_rt_match;
wire id_mem_rs_match;
wire id_mem_rt_match;
wire id_wb_rs_match;
wire id_wb_rt_match;
wire ex_mem_rs_match;
wire ex_mem_rt_match;
wire ex_wb_rs_match;
wire ex_wb_rt_match;
// stall signals
wire stall_id_1;
wire stall_id_2;
wire stall_id_3;
wire stall_id_4;
wire stall_ex_1;
wire stall_ex_2;
// forward signals
wire forward_mem_id_rs;
wire forward_mem_id_rt;
wire forward_wb_id_rs;
wire forward_wb_id_rt;
wire forward_mem_ex_rs;
wire forward_mem_ex_rt;
wire forward_wb_ex_rs;
wire forward_wb_ex_rt;
//--------------------------------------------------------------------------
// assignments
//--------------------------------------------------------------------------
assign WantRsID = DP_Hazards[7];
assign NeedRsID = DP_Hazards[6];
assign WantRtID = DP_Hazards[5];
assign NeedRtID = DP_Hazards[4];
assign WantRsEX = DP_Hazards[3];
assign NeedRsEX = DP_Hazards[2];
assign WantRtEX = DP_Hazards[1];
assign NeedRtEX = DP_Hazards[0];
// Check if the register to use is $zero
assign ex_wa_nz = |(ex_gpr_wa);
assign mem_wa_nz = |(mem_gpr_wa);
assign wb_wa_nz = |(wb_gpr_wa);
// ID dependencies
assign id_ex_rs_match = (ex_wa_nz) & (id_rs == ex_gpr_wa) & (WantRsID | NeedRsID) & ex_gpr_we;
assign id_ex_rt_match = (ex_wa_nz) & (id_rt == ex_gpr_wa) & (WantRtID | NeedRtID) & ex_gpr_we;
assign id_mem_rs_match = (mem_wa_nz) & (id_rs == mem_gpr_wa) & (WantRsID | NeedRsID) & mem_gpr_we;
assign id_mem_rt_match = (mem_wa_nz) & (id_rt == mem_gpr_wa) & (WantRtID | NeedRtID) & mem_gpr_we;
assign id_wb_rs_match = (wb_wa_nz) & (id_rs == wb_gpr_wa) & (WantRsID | NeedRsID) & wb_gpr_we;
assign id_wb_rt_match = (wb_wa_nz) & (id_rt == wb_gpr_wa) & (WantRtID | NeedRtID) & wb_gpr_we;
// EX dependencies
assign ex_mem_rs_match = (mem_wa_nz) & (ex_rs == mem_gpr_wa) & (WantRsEX | NeedRsEX) & mem_gpr_we;
assign ex_mem_rt_match = (mem_wa_nz) & (ex_rt == mem_gpr_wa) & (WantRtEX | NeedRtEX) & mem_gpr_we;
assign ex_wb_rs_match = (wb_wa_nz) & (ex_rs == wb_gpr_wa) & (WantRsEX | NeedRsEX) & wb_gpr_we;
assign ex_wb_rt_match = (wb_wa_nz) & (ex_rt == wb_gpr_wa) & (WantRtEX | NeedRtEX) & wb_gpr_we;
// stall signals
assign stall_id_1 = id_ex_rs_match & NeedRsID; // Needs data from EX (Rs)
assign stall_id_2 = id_ex_rt_match & NeedRtID; // Needs data from EX (Rt)
assign stall_id_3 = id_mem_rs_match & NeedRsID & (mem_mem_read | mem_mem_write); // Needs data from MEM (Rs)
assign stall_id_4 = id_mem_rt_match & NeedRtID & (mem_mem_read | mem_mem_write); // Needs data from MEM (Rt)
assign stall_ex_1 = ex_mem_rs_match & NeedRsEX & (mem_mem_read | mem_mem_write); // Needs data from MEM (Rs)
assign stall_ex_2 = ex_mem_rt_match & NeedRtEX & (mem_mem_read | mem_mem_write); // Needs data from MEM (Rt)
// forwarding signals
assign forward_mem_id_rs = id_mem_rs_match & ~(mem_mem_read | mem_mem_write); // forward if not mem access
assign forward_mem_id_rt = id_mem_rt_match & ~(mem_mem_read | mem_mem_write); // forward if not mem access;
assign forward_wb_id_rs = id_wb_rs_match;
assign forward_wb_id_rt = id_wb_rt_match;
assign forward_mem_ex_rs = ex_mem_rs_match & ~(mem_mem_read | mem_mem_write);
assign forward_mem_ex_rt = ex_mem_rt_match & ~(mem_mem_read | mem_mem_write);
assign forward_wb_ex_rs = ex_wb_rs_match;
assign forward_wb_ex_rt = ex_wb_rt_match;
//--------------------------------------------------------------------------
// Assign stall signals
//--------------------------------------------------------------------------
assign wb_stall = mem_stall;
assign mem_stall = dmem_request_stall | mem_exception_stall | if_stall; // check the if_stall
assign ex_stall = stall_ex_1 | stall_ex_2 | ex_exception_stall | ex_request_stall | mem_stall;
assign id_stall = stall_id_1 | stall_id_2 | stall_id_3 | stall_id_4 | id_exception_stall | ex_stall;
assign if_stall = imem_request_stall | if_exception_stall;
//--------------------------------------------------------------------------
// forwarding control signals
//--------------------------------------------------------------------------
// sel | ID stage | EX stage
//--------------------------------------------------------------------------
// 00 -> ID (no forwarding) | EX (no forwarding)
// 01 -> MEM | MEM
// 10 -> WB | WB
// 11 -> don\'t care | don\'t care
//--------------------------------------------------------------------------
assign forward_id_rs = (forward_mem_id_rs) ? 2\'b01 : ((forward_wb_id_rs) ? 2\'b10 : 2\'b00);
assign forward_id_rt = (forward_mem_id_rt) ? 2\'b01 : ((forward_wb_id_rt) ? 2\'b10 : 2\'b00);
assign forward_ex_rs = (forward_mem_ex_rs) ? 2\'b01 : ((forward_wb_ex_rs) ? 2\'b10 : 2\'b00);
assign forward_ex_rt = (forward_mem_ex_rt) ? 2\'b01 : ((forward_wb_ex_rt) ? 2\'b10 : 2\'b00);
endmodule // antares_hazard_unit
|
//==================================================================================================
// Filename : antares_shifter.v
// Created On : Wed Sep 2 09:04:04 2015
// Last Modified : Sat Nov 07 12:16:18 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Sim\xc3\xb3n Bol\xc3\xadvar
// Email : [email protected]
//
// Description : Arithmetic/Loogic shifter.
// WARNING: shift_shamnt range is 0 -> 31
//==================================================================================================
module antares_shifter (
input [31:0] shift_input_data, // Input data
input [4:0] shift_shamnt, // Shift amount
input shift_direction, // 0: right, 1: left
input shift_sign_extend, // 1: Signed operation
output [31:0] shift_result // Result
);
//-------------------------------------------------------------------------
// Signal Declaration: reg
//--------------------------------------------------------------------------
reg [31:0] input_inv; // invert input for shift left
reg [31:0] result_shift_temp; // shift result
reg [31:0] result_inv; // invert output for shift left
//-------------------------------------------------------------------------
// Signal Declaration: wire
//--------------------------------------------------------------------------
wire sign;
wire [31:0] operand;
//-------------------------------------------------------------------------
// assignments
//-------------------------------------------------------------------------
assign sign = (shift_sign_extend) ? shift_input_data[31] : 1'b0;
assign operand = (shift_direction) ? input_inv : shift_input_data;
assign shift_result = (shift_direction) ? result_inv : result_shift_temp;
//-------------------------------------------------------------------------
// invert data if the operation is SLL
//-------------------------------------------------------------------------
integer index0;
integer index1;
// first inversion: input data
always @ (*) begin
for (index0 = 0; index0 < 32; index0 = index0 + 1) begin
input_inv[31 - index0] = shift_input_data[index0];
end
end
// second inversion : output
always @(*) begin
for (index1 = 0; index1 < 32; index1 = index1 + 1)
result_inv[31 - index1] = result_shift_temp[index1];
end
//--------------------------------------------------------------------------
// the BIG multiplexer
// Perform SRA. Sign depends if operation is SRA or SRL (shift_sign_extend)
//--------------------------------------------------------------------------
always @(*) begin
case(shift_shamnt)
5'd0 : result_shift_temp = operand[31:0];
5'd1 : result_shift_temp = { {1 {sign}}, operand[31:1] };
5'd2 : result_shift_temp = { {2 {sign}}, operand[31:2] };
5'd3 : result_shift_temp = { {3 {sign}}, operand[31:3] };
5'd4 : result_shift_temp = { {4 {sign}}, operand[31:4] };
5'd5 : result_shift_temp = { {5 {sign}}, operand[31:5] };
5'd6 : result_shift_temp = { {6 {sign}}, operand[31:6] };
5'd7 : result_shift_temp = { {7 {sign}}, operand[31:7] };
5'd8 : result_shift_temp = { {8 {sign}}, operand[31:8] };
5'd9 : result_shift_temp = { {9 {sign}}, operand[31:9] };
5'd10 : result_shift_temp = { {10{sign}}, operand[31:10] };
5'd11 : result_shift_temp = { {11{sign}}, operand[31:11] };
5'd12 : result_shift_temp = { {12{sign}}, operand[31:12] };
5'd13 : result_shift_temp = { {13{sign}}, operand[31:13] };
5'd14 : result_shift_temp = { {14{sign}}, operand[31:14] };
5'd15 : result_shift_temp = { {15{sign}}, operand[31:15] };
5'd16 : result_shift_temp = { {16{sign}}, operand[31:16] };
5'd17 : result_shift_temp = { {17{sign}}, operand[31:17] };
5'd18 : result_shift_temp = { {18{sign}}, operand[31:18] };
5'd19 : result_shift_temp = { {19{sign}}, operand[31:19] };
5'd20 : result_shift_temp = { {20{sign}}, operand[31:20] };
5'd21 : result_shift_temp = { {21{sign}}, operand[31:21] };
5'd22 : result_shift_temp = { {22{sign}}, operand[31:22] };
5'd23 : result_shift_temp = { {23{sign}}, operand[31:23] };
5'd24 : result_shift_temp = { {24{sign}}, operand[31:24] };
5'd25 : result_shift_temp = { {25{sign}}, operand[31:25] };
5'd26 : result_shift_temp = { {26{sign}}, operand[31:26] };
5'd27 : result_shift_temp = { {27{sign}}, operand[31:27] };
5'd28 : result_shift_temp = { {28{sign}}, operand[31:28] };
5'd29 : result_shift_temp = { {29{sign}}, operand[31:29] };
5'd30 : result_shift_temp = { {30{sign}}, operand[31:30] };
5'd31 : result_shift_temp = { {31{sign}}, operand[31:31] };
default : result_shift_temp = 32'bx;
endcase
end
endmodule // antares_shifter
|
//==================================================================================================
// Filename : antares_cpzero.v
// Created On : Sat Sep 5 18:48:44 2015
// Last Modified : Sat Nov 07 11:59:09 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Sim\xc3\xb3n Bol\xc3\xadvar
// Email : [email protected]
//
// Description : The Coprocessor 0 (CP0)
// This module allows interrupts; traps, system calls and other exceptions.
// No Virtual Memory management
// Only a subset of CP0 (MIPS32 compliant).
//==================================================================================================
`include "antares_defines.v"
module antares_cpzero (
input clk,
// CP0
input mfc0, // mfc0 instruction
input mtc0, // mtc0 instruction
input eret, // eret instruction
input cp1_instruction, // Instruction for co-processor 1 (invalid for now)
input cp2_instruction, // Instruction for co-processor 2 (invalid for now)
input cp3_instruction, // Instruction for co-processor 3 (invalid for now)
input [4:0] register_address, // CP0 Register
input [2:0] select, // Select register
input [31:0] data_input, // Input data (write)
input if_stall, // Can not write to CP0 if IF/ID is stalled
input id_stall, // Can not write to CP0 if IF/ID is stalled
output reg [31:0] cp0_data_output, // Output data (read)
output id_kernel_mode, // Kernel mode: 0 Kernel, 1 User
// Hardware/External Interrupts
input [4:0] interrupts, // Up to 5 external interrupts
// exceptions
input rst, // External reset
input exc_nmi, // Non-maskable interrupt
input exc_address_if, // Address error: IF stage
input exc_address_l_mem, // Address error: MEM stage, load instruction
input exc_address_s_mem, // Address error: MEM stage, store instruction
input exc_ibus_error, // Instruction Bus Error
input exc_dbus_error, // Data Bus Error
input exc_overflow, // Integer overflow: EX stage
input exc_trap, // Trap exception
input exc_syscall, // System call
input exc_breakpoint, // Breakpoint
input exc_reserved, // Reserved Instruction
// exception data
input [31:0] id_exception_pc, // Exception PC @ ID stage
input [31:0] ex_exception_pc, // Exception PC @ EX stage
input [31:0] mem_exception_pc, // Exception PC @ MEM stage
input [31:0] bad_address_if, // Bad address that caused the exception
input [31:0] bad_address_mem, // Bad address that caused the exception
input id_exception_source, // Instruction @ ID stage is a potential source of exception
input ex_exception_source, // Instruction @ EX stage is a potential source of exception
input mem_exception_source, // Instruction @ MEM stage is a potential source of exception
input id_is_flushed, // BDS for ERET instruction
input if_is_bds, // Instruction at this stage is a Branch Delay Slot
input id_is_bds, // Instruction at this stage is a Branch Delay Slot
input ex_is_bds, // Instruction at this stage is a Branch Delay Slot
input mem_is_bds, // Instruction at this stage is a Branch Delay Slot
// pipeline control
output halt, // Halt the processor.
output if_exception_stall, // Stall pipeline: exception and wait for a clean pipeline
output id_exception_stall, // Stall pipeline: exception and wait for a clean pipeline
output ex_exception_stall, // Stall pipeline: exception and wait for a clean pipeline
output mem_exception_stall, // Stall pipeline: exception and wait for a clean pipeline
output if_flush, // Flush the pipeline: exception.
output id_flush, // Flush the pipeline: exception.
output ex_flush, // Flush the pipeline: exception.
output mem_flush, // Flush the pipeline: exception.
output exception_ready,
output exception_pc_select, // Select the PC from CP0
output reg [31:0] pc_exception // Address for the new PC (exception/return from exception)
);
//--------------------------------------------------------------------------
// Internal wires/registers
//--------------------------------------------------------------------------
wire exception_cp; // Unusable co-processor
wire interrupt_5; // Hardware interrupt #5: Count/Compare (timer)
wire interrupt_enabled; // Interrupt?
wire exception_interrupt; // The interrupt is OK to process.
wire cp0_enable_write; // Write to CP0 is OK (no hazards)
wire exception_no_interrupts; // All exceptions, but Interrupts, Reset, Soft-Reset, NMI
reg [4:0] cause_ExcCode_aux; // Hold the ExcCode (?)
wire if_exception; // exceptions by stage
wire id_exception; // exceptions by stage
wire ex_exception; // exceptions by stage
wire mem_exception; // exceptions by stage
wire if_exception_mask; // enable exception at this stage
wire id_exception_mask; // enable exception at this stage
wire ex_exception_mask; // enable exception at this stage
wire mem_exception_mask; // enable exception at this stage
wire if_exception_ready; // ready to process
wire id_exception_ready; // ready to process
wire ex_exception_ready; // ready to process
wire mem_exception_ready; // ready to process
//--------------------------------------------------------------------------
// CP0 Registers
// Defined in "MIPS32 Architecture for Programmers Volume III:
// The MIPS32 Privileged Resource Architecture" by Imagination Technologies, LTD.
// Only a subset.
//--------------------------------------------------------------------------
// Status Register:
wire [2:0] Status_CU_321 = 3\'b000; // Access Control to CPs, [2]->Cp3, ... [0]->Cp1
reg Status_CU_0; // Access Control to CP0
wire Status_RP = 0;
wire Status_FR = 0;
wire Status_RE = 0; // Reverse Endian Memory for User Mode
wire Status_MX = 0;
wire Status_PX = 0;
reg Status_BEV; // Exception vector locations (0->Norm, 1->Bootstrap)
wire Status_TS = 0;
wire Status_SR = 0; // Soft reset (Not implemented)
reg Status_NMI; // Non-Maskable Interrupt
wire [1:0] Status_RES = 0; // Reserved.
reg Status_HALT; // Stop processor
reg [7:0] Status_IM; // Interrupt mask
wire Status_KX = 0; // 64-bits mode. (Not implemented)
wire Status_SX = 0; // 64-bits mode. (Not implemented)
wire Status_UX = 0; // 64-bits mode. (Not implemented)
reg [1:0] Status_KSU; // CPU privileged level: 0 -> kernel, 1 -> supervisor, 2 -> user
reg Status_ERL; // Error Level (0->Normal, 1->Error (reset, NMI))
reg Status_EXL; // Exception level (0->Normal, 1->Exception)
reg Status_IE; // Interrupt Enable
wire [31:0] Status; // Status Register (Register 12, Select 0)
// Cause Register:
reg Cause_BD; // Exception at BDS
reg [1:0] Cause_CE; // Co-processor error: Unusable co-processor
reg Cause_IV; // Special exception entry point
wire Cause_WP = 0; // Enable watchpoint exception mode.
reg [7:0] Cause_IP; // Pending hardware interrupts
reg [4:0] Cause_ExcCode; // Exception code.
wire [31:0] Cause; // Cause Register (Register 13, Select 0)
// Processor Identification:
wire [7:0] ID_Options = 8\'b0000_0000; // Company Options -> to define
wire [7:0] ID_CID = 8\'b0000_0000; // Company ID -> to zero
wire [7:0] ID_PID = 8\'b0000_0000; // CPU ID
wire [7:0] ID_Rev = 8\'b0000_0001; // Revision
wire [31:0] PRId; // Processor ID (Register 15, Select 0)
// Configuration Register:
wire Config_M = 1; // Continuation bit. 1-> if another config register is available
wire [14:0] Config_Impl = 15\'b000_0000_0000_0000; // Implementation-dependent configuration flags.
wire Config_BE = `ANTARES_LITTLE_ENDIAN; // Endiannes
wire [1:0] Config_AT = 2\'b00; // MIPS32
wire [2:0] Config_AR = 3\'b000; // MIPS32 Release 1
wire [2:0] Config_MT = 3\'b000; // MMU -> none
wire Config_VI = 1\'b0; // L1 I-cache do not use virtual address
wire [2:0] Config_K0 = 3\'b000; // Fixed kseg0 region is cached or uncached? behavior?
wire [31:0] Config; // Config Register (Register 16, Select 0)
// Configuration Register 1:
wire Config1_M = 0; // Continuation bit
wire [5:0] Config1_MMU = 6\'b000000; // MMU size
wire [2:0] Config1_IS = 3\'b000; // Number of index positions: 64 x 2^S
wire [2:0] Config1_IL = 3\'b000; // 0 -> no cache. Else: 2^(L + 1)
wire [2:0] Config1_IA = 3\'b000; // Associativity -> (A + 1)
wire [2:0] Config1_DS = 3\'b000; // Number of index positions: 64 x 2^S
wire [2:0] Config1_DL = 3\'b000; // 0 -> no cache. Else: 2^(L + 1)
wire [2:0] Config1_DA = 3\'b000; // Associativity -> (A + 1)
wire Config1_C2 = 0; // Co-processor 2?
wire Config1_MD = 0; // MDMX ASE?
wire Config1_PC = 0; // Performance Counters ?
wire Config1_WR = 0; // Watch Registers ?
wire Config1_CA = 0; // MIPS16?
wire Config1_EP = 0; // EJTAG?
wire Config1_FP = 0; // Floating-point?
wire [31:0] Config1; // Config Register (Register 16, Select 1)
reg [31:0] BadVAddr; // BadVAddr Register (Register 8, Select 0)
reg [31:0] Count; // Count Register (Register 9, Select 0)
reg [31:0] Compare; // Compare Register (Register 11, Select 0)
reg [31:0] EPC; // Exception Program Counter (Register 14, Select 0)
reg [31:0] ErrorEPC; // Error Register (Register 30, Select 0)
//--------------------------------------------------------------------------
// assignments
//--------------------------------------------------------------------------
assign Status = {Status_CU_321, Status_CU_0, Status_RP, Status_FR, Status_RE, Status_MX, // bits 31-24
Status_PX, Status_BEV, Status_TS, Status_SR, Status_NMI, Status_RES, Status_HALT, // bits 23-16
Status_IM, // bits 15-8
Status_KX, Status_SX, Status_UX, Status_KSU, Status_ERL, Status_EXL, Status_IE}; // bits 7-0
assign Cause = {Cause_BD, 1\'b0, Cause_CE, 4\'b0000, // bits 31-24
Cause_IV, Cause_WP, 6\'b000000, // bits 23-16
Cause_IP, // bits 15-8
1\'b0, Cause_ExcCode, 2\'b0}; // bits 7-0
assign PRId = {ID_Options, // bits 31-24
ID_CID, // bits 23-16
ID_PID, // bits 15-8
ID_Rev}; // bits 7-0
assign Config = {Config_M, Config_Impl, // bits 31-16
Config_BE, Config_AT, Config_AR, Config_MT, // bits 15-7
3\'b000, Config_VI, Config_K0}; // bits 6-0
assign Config1 = {Config1_M, Config1_MMU,
Config1_IS, Config1_IL, Config1_IA,
Config1_DS, Config1_DL, Config1_DA,
Config1_C2, Config1_MD, Config1_PC, Config1_WR, Config1_CA, Config1_EP, Config1_FP};
assign exception_cp = cp1_instruction | cp2_instruction | cp3_instruction | // Check if the co-processor instruction is valid.
( (mtc0 | mfc0 | eret) & ~(Status_CU_0 | id_kernel_mode) ); // For CP0 : only if it has been enabled, or in kernel mode, it\'s ok to use these instructions.
// For CP3-1 : Always trap.
assign exception_no_interrupts = exc_address_if | exc_ibus_error | exc_syscall | exc_breakpoint | exc_reserved | // All exceptions, but interrupts, reset, soft-reset and nmi
exception_cp | exc_overflow | exc_address_l_mem | exc_address_s_mem | //
exc_dbus_error | exc_trap; //
assign id_kernel_mode = (Status_KSU != 2\'b10) | Status_EXL | Status_ERL; // Kernel mode if mode != user, Exception level or Error level. To inhibit new exceptions/interrupts
assign interrupt_5 = (Count == Compare) & Status_IM[7]; // Counter interrupt (#5)
assign interrupt_enabled = exc_nmi | ( Status_IE & ( (Cause_IP[7:0] & Status_IM[7:0]) != 8\'b0 ) ); // Interrupt if NMI, Interrupts are enabled (global) and the individual interrupt is enable.
assign exception_interrupt = interrupt_enabled & ~Status_EXL & ~Status_ERL & ~id_is_flushed; // Interrupt is OK to process if: no exception level and no error level, and the instruction is a forced NOP.
assign cp0_enable_write = mtc0 & ~id_stall & (Status_CU_0 | id_kernel_mode) &
(~mem_exception & ~ex_exception & ~id_exception & ~if_exception); // Write to CP0 if ID is not stalled, CP0 is enabled or in kernel mode, and no exceptions
assign halt = Status_HALT;
//--------------------------------------------------------------------------
// Hazards
// Rules:
// - In case of exception, the stage could be stalled if:
// - A forward stage is capable of causing an exception, AND
// - A forward stage is not causing an exception.
// - An exception is ready to process if not stalled.
//
// In case of exception: clear commits, convert to NOP (a.k.a. flush the stage).
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Exceptions by stage
//--------------------------------------------------------------------------
assign mem_exception = exc_address_l_mem | exc_address_s_mem | exc_dbus_error | exc_trap; // Error on load, store, data read, or trap
assign ex_exception = exc_overflow; // overflow
assign id_exception = exc_syscall | exc_breakpoint | exc_reserved | exception_cp | exception_interrupt; // Syscall, breakpoint, reserved instruction, Co-processor or interrupt
assign if_exception = exc_address_if | exc_ibus_error; // Error on load or bus
//--------------------------------------------------------------------------
// Mask exception: assert in case of possible exceptions in forward stages,
// or if being stalled.
// Can not process the exception if IF is stalled (unable to commit the new PC)
//
// NOTE: Abort IF operation in case of exception
//--------------------------------------------------------------------------
assign mem_exception_mask = 0;
assign ex_exception_mask = mem_exception_source;
assign id_exception_mask = mem_exception_source | ex_exception_source;
assign if_exception_mask = mem_exception_source | ex_exception_source | id_exception_source | exception_interrupt; // In case of interrupt, abort this
//--------------------------------------------------------------------------
// Generate the stall signals
// No writes to CP0 until a clean state (no stalls).
//--------------------------------------------------------------------------
assign mem_exception_stall = mem_exception & mem_exception_mask;
assign ex_exception_stall = ex_exception & ex_exception_mask & ~mem_exception;
assign id_exception_stall = (id_exception | eret | mtc0) & id_exception_mask & ~(mem_exception | ex_exception);
assign if_exception_stall = if_exception & if_exception_mask & ~(mem_exception | ex_exception | id_exception);
//--------------------------------------------------------------------------
// Signal the valid exception to process
//--------------------------------------------------------------------------
assign mem_exception_ready = mem_exception & ~mem_exception_mask;
assign ex_exception_ready = ex_exception & ~ex_exception_mask;
assign id_exception_ready = id_exception & ~id_exception_mask;
assign if_exception_ready = if_exception & ~if_exception_mask;
//--------------------------------------------------------------------------
// Flush the stages in case of exception
//--------------------------------------------------------------------------
assign mem_flush = mem_exception;
assign ex_flush = mem_exception | ex_exception;
assign id_flush = mem_exception | ex_exception | id_exception;
assign if_flush = mem_exception | ex_exception | id_exception | if_exception | (eret & ~id_stall); // ERET doest not execute the next instruction!!
//--------------------------------------------------------------------------
// Read CP0 registers
//--------------------------------------------------------------------------
always @(*) begin
if(mfc0 & (Status_CU_0 | id_kernel_mode)) begin
case (register_address)
5\'d8 : cp0_data_output = BadVAddr;
5\'d9 : cp0_data_output = Count;
5\'d11 : cp0_data_output = Compare;
5\'d12 : cp0_data_output = Status;
5\'d13 : cp0_data_output = Cause;
5\'d14 : cp0_data_output = EPC;
5\'d15 : cp0_data_output = PRId;
5\'d16 : cp0_data_output = (select == 3\'b000) ? Config : Config1;
5\'d30 : cp0_data_output = ErrorEPC;
default: cp0_data_output = 32\'h0000_0000;
endcase
end
else begin
cp0_data_output = 32\'h0000_0000;
end
end
//--------------------------------------------------------------------------
// Write CP0 registers.
// Reset, soft-reset, NMI.
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
Status_BEV <= 1\'b1;
Status_NMI <= 1\'b0;
Status_ERL <= 1\'b1;
ErrorEPC <= 32\'b0;
end
else if (id_exception_ready & exc_nmi) begin
Status_BEV <= 1\'b1;
Status_NMI <= 1\'b1;
Status_ERL <= 1\'b1;
ErrorEPC <= id_exception_pc;
end
else begin
Status_BEV <= (cp0_enable_write & (register_address == 5\'d12) & (select == 3\'b000)) ? data_input[22] : Status_BEV;
Status_NMI <= (cp0_enable_write & (register_address == 5\'d12) & (select == 3\'b000)) ? data_input[19] : Status_NMI;
Status_ERL <= (cp0_enable_write & (register_address == 5\'d12) & (select == 3\'b000)) ? data_input[2] : ((Status_ERL & eret & ~id_stall) ? 1\'b0 : Status_ERL);
ErrorEPC <= (cp0_enable_write & (register_address == 5\'d30) & (select == 3\'b000)) ? data_input : ErrorEPC;
end
end
//--------------------------------------------------------------------------
// Write CP0 registers.
// Other registers
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
Count <= 32\'b0;
Compare <= 32\'b0;
Status_HALT <= 1\'b0;
Status_CU_0 <= 1\'b0;
//Status_RE <= 1\'b0;
Status_IM <= 8\'b0;
Status_KSU <= 2\'b0;
Status_IE <= 1\'b0;
Cause_IV <= 1\'b0;
Cause_IP <= 8\'b0;
end
else begin
Count <= (cp0_enable_write & (register_address == 5\'d9 ) & (select == 3\'b000)) ? data_input : Count + 1\'b1;
Compare <= (cp0_enable_write & (register_address == 5\'d11) & (select == 3\'b000)) ? data_input : Compare;
Status_HALT <= (cp0_enable_write & (register_address == 5\'d12) & (select == 3\'b000)) ? data_input[16] : Status_HALT;
Status_CU_0 <= (cp0_enable_write & (register_address == 5\'d12) & (select == 3\'b000)) ? data_input[28] : Status_CU_0;
//Status_RE <= (cp0_enable_write & (register_address == 5\'d12) & (select == 3\'b000)) ? data_input[25] : Status_RE;
Status_IM <= (cp0_enable_write & (register_address == 5\'d12) & (select == 3\'b000)) ? data_input[15:8] : Status_IM;
Status_KSU <= (cp0_enable_write & (register_address == 5\'d12) & (select == 3\'b000)) ? data_input[4:3] : Status_KSU;
Status_IE <= (cp0_enable_write & (register_address == 5\'d12) & (select == 3\'b000)) ? data_input[0] : Status_IE;
Cause_IV <= (cp0_enable_write & (register_address == 5\'d13) & (select == 3\'b000)) ? data_input[23] : Cause_IV;
/* Cause_IP indicates 8 interrupts:
[7] is set by the timer comparison, and cleared by writing to "Compare".
[6:2] are set and cleared by external hardware.
[1:0] are set and cleared by software.
*/
Cause_IP[7] <= (cp0_enable_write & (register_address == 5\'d11) & (select == 3\'b000)) ? 1\'b0 : ((Cause_IP[7] == 0) ? interrupt_5 : Cause_IP[7]); // If reading -> 0, Otherwise if 0 -> interrupt_5.
Cause_IP[6:2] <= interrupts[4:0];
Cause_IP[1:0] <= (cp0_enable_write & (register_address == 5\'d13) & (select == 3\'b000)) ? data_input[9:8] : Cause_IP[1:0];
end
end
//--------------------------------------------------------------------------
// Write CP0 registers.
// Exception and Interrupt Processing
// Ignore if EXL or ERL is asserted
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
Cause_BD <= 1\'b0;
Cause_CE <= 2\'b00;
Cause_ExcCode <= 5\'b0;
Status_EXL <= 1\'b0;
EPC <= 32\'h0;
BadVAddr <= 32\'h0;
end
else begin
// MEM stage
if (mem_exception_ready) begin
Cause_BD <= (Status_EXL) ? Cause_BD : mem_is_bds;
Cause_CE <= (cp3_instruction) ? 2\'b11 : ((cp2_instruction) ? 2\'b10 : ((cp1_instruction) ? 2\'b01 : 2\'b00));
Cause_ExcCode <= cause_ExcCode_aux;
Status_EXL <= 1\'b1;
EPC <= (Status_EXL) ? EPC : mem_exception_pc;
BadVAddr <= bad_address_mem;
end
// EX stage
else if (ex_exception_ready) begin
Cause_BD <= (Status_EXL) ? Cause_BD : ex_is_bds;
Cause_CE <= (cp3_instruction) ? 2\'b11 : ((cp2_instruction) ? 2\'b10 : ((cp1_instruction) ? 2\'b01 : 2\'b00));
Cause_ExcCode <= cause_ExcCode_aux;
Status_EXL <= 1\'b1;
EPC <= (Status_EXL) ? EPC : ex_exception_pc;
BadVAddr <= BadVAddr;
end
// ID stage
else if (id_exception_ready) begin
Cause_BD <= (Status_EXL) ? Cause_BD : id_is_bds;
Cause_CE <= (cp3_instruction) ? 2\'b11 : ((cp2_instruction) ? 2\'b10 : ((cp1_instruction) ? 2\'b01 : 2\'b00));
Cause_ExcCode <= cause_ExcCode_aux;
Status_EXL <= 1\'b1;
EPC <= (Status_EXL) ? EPC : id_exception_pc;
BadVAddr <= BadVAddr;
end
// IF stage
else if (if_exception_ready) begin
Cause_BD <= (Status_EXL) ? Cause_BD : if_is_bds;
Cause_CE <= (cp3_instruction) ? 2\'b11 : ((cp2_instruction) ? 2\'b10 : ((cp1_instruction) ? 2\'b01 : 2\'b00));
Cause_ExcCode <= cause_ExcCode_aux;
Status_EXL <= 1\'b1;
EPC <= (Status_EXL) ? EPC : bad_address_if;
BadVAddr <= bad_address_if;
end
// No exceptions this cycle
else begin
Cause_BD <= 1\'b0;
Cause_CE <= Cause_CE;
Cause_ExcCode <= Cause_ExcCode;
// Without new exceptions, \'Status_EXL\' is set by software or cleared by ERET.
Status_EXL <= (cp0_enable_write & (register_address == 5\'d12) & (select == 3\'b000)) ? data_input[1] : ((Status_EXL & eret & ~id_stall) ? 1\'b0 : Status_EXL);
// The EPC is also writable by software
EPC <= (cp0_enable_write & (register_address == 5\'d14) & (select == 3\'b000)) ? data_input : EPC;
BadVAddr <= BadVAddr;
end
end
end
//--------------------------------------------------------------------------
// Set the program counter
// The PC register handles the reset scenario.
//--------------------------------------------------------------------------
always @(*) begin
if (rst) begin
pc_exception = `ANTARES_VECTOR_BASE_RESET;
end
if (eret & ~id_stall) begin
pc_exception = (Status_ERL) ? ErrorEPC : EPC;
end
else if (exception_no_interrupts) begin
pc_exception = (Status_BEV) ? (`ANTARES_VECTOR_BASE_BOOT + `ANTARES_VECTOR_OFFSET_GENERAL) : (`ANTARES_VECTOR_BASE_NO_BOOT + `ANTARES_VECTOR_OFFSET_GENERAL);
end
else if (exc_nmi) begin
pc_exception = `ANTARES_VECTOR_BASE_RESET;
end
else if (exception_interrupt & Cause_IV) begin
pc_exception = (Status_BEV) ? (`ANTARES_VECTOR_BASE_BOOT + `ANTARES_VECTOR_OFFSET_SPECIAL) : (`ANTARES_VECTOR_BASE_NO_BOOT + `ANTARES_VECTOR_OFFSET_SPECIAL);
end
else begin
pc_exception = (Status_BEV) ? (`ANTARES_VECTOR_BASE_BOOT + `ANTARES_VECTOR_OFFSET_GENERAL) : (`ANTARES_VECTOR_BASE_NO_BOOT + `ANTARES_VECTOR_OFFSET_GENERAL);
end
end
assign exception_ready = if_exception_ready | id_exception_ready | ex_exception_ready | mem_exception_ready;
assign exception_pc_select = rst | (eret & ~id_stall) | exception_ready;
//--------------------------------------------------------------------------
// Set the Cause register
// Ordered by Pipeline Stage with Interrupts last
//--------------------------------------------------------------------------
always @(*) begin
if (exc_address_l_mem) cause_ExcCode_aux = 5\'h4; // 00100 (EXC_AdEL)
else if (exc_address_s_mem) cause_ExcCode_aux = 5\'h5; // 00101 (EXC_AdES)
else if (exc_dbus_error) cause_ExcCode_aux = 5\'h7; // 00111 (EXC_DBE)
else if (exc_trap) cause_ExcCode_aux = 5\'hd; // 01101 (EXC_Tr)
else if (exc_overflow) cause_ExcCode_aux = 5\'hc; // 01100 (EXC_Ov)
else if (exc_syscall) cause_ExcCode_aux = 5\'h8; // 01000 (EXC_Sys)
else if (exc_breakpoint) cause_ExcCode_aux = 5\'h9; // 01001 (EXC_Bp)
else if (exc_reserved) cause_ExcCode_aux = 5\'ha; // 01010 (EXC_RI)
else if (exception_cp) cause_ExcCode_aux = 5\'hb; // 01011 (EXC_CpU)
else if (exc_address_if) cause_ExcCode_aux = 5\'h4; // 00100 (EXC_AdIF)
else if (exc_ibus_error) cause_ExcCode_aux = 5\'h6; // 00110 (EXC_IBE)
else if (exception_interrupt) cause_ExcCode_aux = 5\'h0; // 00000 (EXC_Int)
else cause_ExcCode_aux = 5\'bxxxx; // What the hell?
end
endmodule // antares_cpzero
|
//==================================================================================================
// Filename : antares_reg_file.v
// Created On : Tue Sep 1 10:29:48 2015
// Last Modified : Sat Nov 07 12:15:25 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Sim\xc3\xb3n Bol\xc3\xadvar
// Email : [email protected]
//
// Description : 32 General Purpose Registers (GPR)
// WARNING: This register file DO NOT HAVE A RESET.
//==================================================================================================
module antares_reg_file (
input clk,
input [4:0] gpr_ra_a,
input [4:0] gpr_ra_b,
input [4:0] gpr_wa,
input [31:0] gpr_wd,
input gpr_we,
output [31:0] gpr_rd_a,
output [31:0] gpr_rd_b
);
// Register file of 32 32-bit registers. Register 0 is always 0
reg [31:0] registers [1:31];
// Clocked write
always @ ( posedge clk ) begin
if(gpr_wa != 5'b0)
registers[gpr_wa] <= (gpr_we) ? gpr_wd : registers[gpr_wa];
end
// Combinatorial read (no delay). Register 0 is read as 0 always.
assign gpr_rd_a = (gpr_ra_a == 5'b0) ? 32'b0 : registers[gpr_ra_a];
assign gpr_rd_b = (gpr_ra_b == 5'b0) ? 32'b0 : registers[gpr_ra_b];
endmodule // antares_reg_file
|
//==================================================================================================
// Filename : monitor.v
// Created On : Wed Sep 9 19:00:41 2015
// Last Modified : Sat Nov 07 12:24:38 2015
// Revision : 0.1
// Author : \xc3\x81ngel Terrones
// Company : Universidad Sim\xc3\xb3n Bol\xc3\xadvar
// Email : [email protected]
//
// Description : Core monitor
//==================================================================================================
/* verilator lint_off STMTDLY */
`include "antares_defines.v"
`timescale 1ns / 100ps
`define cycle 20 // ns
`define TRACE_BUFFER_SIZE 10000000 // bytes
`define EXCEPTION_BUFFER_SIZE 10000000 // bytes
`define TIMEOUT_DEFAULT 30000 // For short tests.
`define REG_FILE "register.log" // Dump for the register file
`define MEM_DUMP "memory.log" // Memoty dump (instruction + data)
`define TRACE_FILE "trace.log" // instruction trace
module monitor(
input halt,
input if_stall,
input if_flush,
input id_stall,
input id_flush,
input ex_stall,
input ex_flush,
input mem_stall,
input mem_flush,
input wb_stall,
input [31:0] mem_exception_pc,
input [31:0] id_instruction,
input [4:0] wb_gpr_wa,
input [31:0] wb_gpr_wd,
input wb_gpr_we,
input [31:0] mem_address,
input [31:0] mem_data,
input if_exception_ready,
input id_exception_ready,
input ex_exception_ready,
input mem_exception_ready,
output reg clk_core,
output reg clk_bus,
output reg rst
);
//--------------------------------------------------------------------------
// wires
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// registers
//--------------------------------------------------------------------------
reg [256*8-1:0] trace_buffer[0:`TRACE_BUFFER_SIZE];
reg [256*8-1:0] exception_buffer[0:`EXCEPTION_BUFFER_SIZE];
reg [31:0] wb_exception_pc;
reg [31:0] ex_instruction;
reg [31:0] mem_instruction;
reg [31:0] wb_instruction;
reg [31:0] wb_mem_address;
reg [31:0] wb_mem_store_data;
reg id_instruction_stalled;
reg id_instruction_flushed;
reg ex_instruction_stalled;
reg ex_instruction_flushed;
reg mem_instruction_stalled;
reg mem_instruction_flushed;
reg wb_instruction_stalled;
reg wb_instruction_flushed;
reg [31:0] cause_reg;
reg [256*8-1:0] cause_string;
//--------------------------------------------------------------------------
// counters
//--------------------------------------------------------------------------
integer trace_fill_counter;
integer exception_buffer_counter;
//--------------------------------------------------------------------------
// Tasks
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Get CP0 register
task get_cp0_reg;
input [4:0] cp0_addr;
output [31:0] cp0_data;
begin
case (cp0_addr)
5\'d8 : cp0_data = core.cpzero0.BadVAddr;
5\'d9 : cp0_data = core.cpzero0.Count;
5\'d11 : cp0_data = core.cpzero0.Compare;
5\'d12 : cp0_data = core.cpzero0.Status;
5\'d13 : cp0_data = core.cpzero0.Cause;
5\'d14 : cp0_data = core.cpzero0.EPC;
5\'d15 : cp0_data = core.cpzero0.PRId;
5\'d16 : cp0_data = core.cpzero0.Config1;
5\'d30 : cp0_data = core.cpzero0.ErrorEPC;
default: cp0_data = 32\'h0000_0000;
endcase // case (cp0_addr)
end
endtask // get_cp0_reg
//--------------------------------------------------------------------------
// Decode the exception cause
task decode_cause;
input [31:0] cause;
output [20*8-1:0] exception_code;
begin
case (cause[6:2])
5\'h4 : $sformat(exception_code, "EXC_AdEL");
5\'h5 : $sformat(exception_code, "EXC_AdES");
5\'h7 : $sformat(exception_code, "EXC_DBE");
5\'hd : $sformat(exception_code, "EXC_Tr");
5\'hc : $sformat(exception_code, "EXC_Ov");
5\'h8 : $sformat(exception_code, "EXC_Sys");
5\'h9 : $sformat(exception_code, "EXC_Bp");
5\'ha : $sformat(exception_code, "EXC_RI");
5\'hb : $sformat(exception_code, "EXC_CpU");
5\'h4 : $sformat(exception_code, "EXC_AdIF");
5\'h6 : $sformat(exception_code, "EXC_IBE");
5\'h0 : $sformat(exception_code, "EXC_Int");
default : $sformat(exception_code, "UNKNOWN CAUSE");
endcase // case (cause[6:2])
end
endtask // decode_cause
//--------------------------------------------------------------------------
// Print GPR
task print_gpr;
integer index;
integer file;
begin
file = $fopen(`REG_FILE, "w");
// $display("INFO-MONITOR:\\tRegister dump:");
for(index = 1; index < 32; index = index + 1) begin
$fwrite(file, "R[%02d] = 0x%8h ( %d | %d )\
", index, core.GPR.registers[index], core.GPR.registers[index], $signed(core.GPR.registers[index]));
//$display("\\tR[%02d] = 0x%8h ( %d | %d )", index, core.GPR.registers[index], core.GPR.registers[index], $signed(core.GPR.registers[index]));
end
$display("INFO-MONITOR:\\tRegister dump: DONE.");
$fclose(file);
end
endtask // print_gpr
//--------------------------------------------------------------------------
// Dump the memory
task dump_memory;
begin
$writememh(`MEM_DUMP, memory0.mem);
$display("INFO-MONITOR:\\tMemory dump: DONE.");
end
endtask // dump_memory
//--------------------------------------------------------------------------
// Print trace
task print_trace;
integer file;
integer index;
begin
file = $fopen(`TRACE_FILE, "w");
$fwrite(file, "---------------------------------------------------------------------------------------------------------------------------------------\
");
$fwrite(file, "| %-9s | %-11s | %-11s | %-30s | %-48s | %-s |\
", "Time (ns)", "PC", "Instruction", "Assembler", "Result", "Flushed");
$fwrite(file, "---------------------------------------------------------------------------------------------------------------------------------------\
");
for(index = 0; index < trace_fill_counter; index = index + 1) begin
$fwrite(file, "%-0s\
", trace_buffer[index]);
end
$fwrite(file, "---------------------------------------------------------------------------------------------------------------------------------------\
");
$display("INFO-MONITOR:\\tPrint trace: DONE.");
$fclose(file);
end
endtask // print_trace
//--------------------------------------------------------------------------
// Decode instruction, and store in a buffer
task decode_instruction;
input [31:0] id_pc;
input [31:0] instruction;
input [4:0] wb_register;
input [31:0] wb_data;
input wb_we;
input [31:0] mem_address;
input [31:0] mem_store_data;
reg [5:0] opcode;
reg [4:0] op_rs;
reg [4:0] op_rt;
reg [4:0] op_rd;
reg [5:0] op_function;
reg signed [15:0] op_imm16;
reg [25:0] op_imm26;
reg [2:0] op_cp0_select;
reg [256*8-1:0] instruction_string;
reg [256*8-1:0] wb_register_string;
reg [256*8-1:0] trace;
begin
if (~rst & ~halt) begin
opcode = instruction[`ANTARES_INSTR_OPCODE];
op_rs = instruction[`ANTARES_INSTR_RS];
op_rt = instruction[`ANTARES_INSTR_RT];
op_rd = instruction[`ANTARES_INSTR_RD];
op_function = instruction[`ANTARES_INSTR_FUNCT];
op_imm16 = instruction[`ANTARES_INSTR_IMM16];
op_imm26 = instruction[`ANTARES_INSTR_IMM26];
op_cp0_select = instruction[`ANTARES_INSTR_CP0_SEL];
instruction_string = 0;
wb_register_string = 0;
//$write("| %-5d ns | 0x%h: | 0x%h | ", $time - 1, id_pc, instruction); // time - 1 (delay)
case(opcode)
`OP_TYPE_R : begin
case (op_function)
`FUNCTION_OP_ADD : begin
$sformat(instruction_string, "%-10s r%-2d, r%-2d, r%-2d", "ADD", op_rd, op_rs, op_rt);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
end
`FUNCTION_OP_ADDU : begin
$sformat(instruction_string, "%-10s r%-2d, r%-2d, r%-2d", "ADDU", op_rd, op_rs, op_rt);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
end
`FUNCTION_OP_AND : begin
$sformat(instruction_string, "%-10s r%-2d, r%-2d, r%-2d", "AND", op_rd, op_rs, op_rt);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
end
`FUNCTION_OP_BREAK : begin $sformat(instruction_string, "%-10s ", "BREAK"); end
`FUNCTION_OP_DIV : begin $sformat(instruction_string, "%-10s r%-2d, r%-2d", "DIV", op_rs, op_rt); end
`FUNCTION_OP_DIVU : begin $sformat(instruction_string, "%-10s r%-2d, r%-2d", "DIVU", op_rs, op_rt); end
`FUNCTION_OP_JALR : begin $sformat(instruction_string, "%-10s r%-2d", "JALR", op_rs); end
`FUNCTION_OP_JR : begin $sformat(instruction_string, "%-10s r%-2d", "JR", op_rs); end
`FUNCTION_OP_MFHI : begin
$sformat(instruction_string, "%-10s r%-2d", "MFHI", op_rd);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
end
`FUNCTION_OP_MFLO : begin
$sformat(instruction_string, "%-10s r%-2d", "MFLO", op_rd);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
end
`FUNCTION_OP_MOVN : begin
$sformat(instruction_string, "%-10s r%-2d, r%-2d, r%-2d", "MOVN", op_rd, op_rs, op_rt);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
end
`FUNCTION_OP_MOVZ : begin
$sformat(instruction_string, "%-10s r%-2d, r%-2d, r%-2d", "MOVZ", op_rd, op_rs, op_rt);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
end
`FUNCTION_OP_MTHI : begin $sformat(instruction_string, "%-10s r%-2d", "MTHI", op_rs); end
`FUNCTION_OP_MTLO : begin $sformat(instruction_string, "%-10s r%-2d", "MTLO", op_rs); end
`FUNCTION_OP_MULT : begin $sformat(instruction_string, "%-10s r%-2d, r%-2d", "MULT", op_rs, op_rt); end
`FUNCTION_OP_MULTU : begin $sformat(instruction_string, "%-10s r%-2d, r%-2d", "MULTU", op_rs, op_rt); end
`FUNCTION_OP_NOR : begin
$sformat(instruction_string, "%-10s r%-2d, r%-2d, r%-2d", "NOR", op_rd, op_rs, op_rt);
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
`FUNCTION_OP_OR : begin
$sformat(instruction_string, "%-10s r%-2d, r%-2d, r%-2d", "OR", op_rd, op_rs, op_rt);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
end
`FUNCTION_OP_SLL : begin
if (instruction == 32\'b0) begin
$sformat(instruction_string, "%-10s", "NOP");
end
else begin
$sformat(instruction_string, "%-10s r%-2d, r%-2d, %0d", "SLL", op_rd, op_rt, op_imm16[`ANTARES_INSTR_SHAMT]);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
end
end // case: `FUNCTION_OP_SLL
`FUNCTION_OP_SLLV : begin
$sformat(instruction_string, "%-10s r%-2d, r%-2d, r%-2d", "SLLV", op_rd, op_rt, op_rs);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
end
`FUNCTION_OP_SLT : begin
$sformat(instruction_string, "%-10s t\\tr%-2d, r%-2d, r%-2d", "SLT", op_rd, op_rs, op_rt);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
end
`FUNCTION_OP_SLTU : begin
$sformat(instruction_string, "%-10s r%-2d, r%-2d, r%-2d", "SLTU", op_rd, op_rs, op_rt);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
end
`FUNCTION_OP_SRA : begin
$sformat(instruction_string, "%-10s r%-2d, r%-2d, %0d ", "SRA", op_rd, op_rt, op_imm16[`ANTARES_INSTR_SHAMT]);
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
`FUNCTION_OP_SRAV : begin
$sformat(instruction_string, "%-10s r%-2d, r%-2d, r%-2d", "SRAV", op_rd, op_rt, op_rs);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
end
`FUNCTION_OP_SRL : begin
$sformat(instruction_string, "%-10s r%-2d, r%-2d, %0d ", "SRL", op_rd, op_rt, op_imm16[`ANTARES_INSTR_SHAMT]);
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
`FUNCTION_OP_SRLV : begin
$sformat(instruction_string, "%-10s r%-2d, r%-2d, r%-2d", "SRLV", op_rd, op_rt, op_rs);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
end
`FUNCTION_OP_SUB : begin
$sformat(instruction_string, "%-10s r%-2d, r%-2d, r%-2d", "SUB", op_rd, op_rs, op_rt);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
end
`FUNCTION_OP_SUBU : begin
$sformat(instruction_string, "%-10s r%-2d, r%-2d, r%-2d", "SUBU", op_rd, op_rs, op_rt);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
end
`FUNCTION_OP_SYSCALL : begin $sformat(instruction_string, "%-10s ", "SYSCALL"); end
`FUNCTION_OP_TEQ : begin $sformat(instruction_string, "%-10s r%-2d, r%-2d ", "TEQ", op_rs, op_rt); end
`FUNCTION_OP_TGE : begin $sformat(instruction_string, "%-10s r%-2d, r%-2d ", "TGE", op_rs, op_rt); end
`FUNCTION_OP_TGEU : begin $sformat(instruction_string, "%-10s r%-2d, r%-2d ", "TGEU", op_rs, op_rt); end
`FUNCTION_OP_TLT : begin $sformat(instruction_string, "%-10s r%-2d, r%-2d ", "TLT", op_rs, op_rt); end
`FUNCTION_OP_TLTU : begin $sformat(instruction_string, "%-10s r%-2d, r%-2d ", "TLTU", op_rs, op_rt); end
`FUNCTION_OP_TNE : begin $sformat(instruction_string, "%-10s r%-2d, r%-2d ", "TNE", op_rs, op_rt); end
`FUNCTION_OP_XOR : begin
$sformat(instruction_string, "%-10s r%-2d, r%-2d, r%-2d", "XOR", op_rd, op_rs, op_rt);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
end
default : begin $sformat(instruction_string, "Invalid R instruction"); end
endcase // case (op_function)
end // case: `OP_TYPE_R
`OP_TYPE_R2 : begin
case (op_function)
`FUNCTION_OP_CLO : begin
$sformat(instruction_string, "%-10s r%-2d, r%-2d ", "CLO", op_rs, op_rt);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
end
`FUNCTION_OP_CLZ : begin
$sformat(instruction_string, "%-10s r%-2d, r%-2d ", "CLZ", op_rs, op_rt);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
end
`FUNCTION_OP_MADD : begin $sformat(instruction_string, "%-10s r%-2d, r%-2d ", "MADD", op_rs, op_rt); end
`FUNCTION_OP_MADDU : begin $sformat(instruction_string, "%-10s r%-2d, r%-2d ", "MADDU", op_rs, op_rt); end
`FUNCTION_OP_MSUB : begin $sformat(instruction_string, "%-10s r%-2d, r%-2d ", "MSUB", op_rs, op_rt); end
`FUNCTION_OP_MSUBU : begin $sformat(instruction_string, "%-10s r%-2d, r%-2d ", "MSUBU", op_rs, op_rt); end
default : begin $sformat(instruction_string, "Invalid R2 instruction"); end
endcase // case (op_function)
end // case: `OP_TYPE_R2
`OP_TYPE_REGIMM : begin
case (op_rt)
`RT_OP_BGEZ : begin $sformat(instruction_string, "%-10s r%-2d, %0d", "BGEZ", op_rs, $signed(id_pc) + $signed({op_imm16, 2\'b0}) + 4); end
`RT_OP_BGEZAL : begin $sformat(instruction_string, "%-10s r%-2d, %0d", "BGEZAL", op_rs, $signed(id_pc) + $signed({op_imm16, 2\'b0}) + 4); end
`RT_OP_BLTZ : begin $sformat(instruction_string, "%-10s r%-2d, %0d", "BLTZ", op_rs, $signed(id_pc) + $signed({op_imm16, 2\'b0}) + 4); end
`RT_OP_BLTZAL : begin $sformat(instruction_string, "%-10s r%-2d, %0d", "BLTZAL", op_rs, $signed(id_pc) + $signed({op_imm16, 2\'b0}) + 4); end
`RT_OP_TEQI : begin $sformat(instruction_string, "%-10s r%-2d, %0d", "TEQI", op_rs, op_imm16); end
`RT_OP_TGEI : begin $sformat(instruction_string, "%-10s r%-2d, %0d", "TGEI", op_rs, op_imm16); end
`RT_OP_TGEIU : begin $sformat(instruction_string, "%-10s r%-2d, %0d", "TGEIU", op_rs, op_imm16); end
`RT_OP_TLTI : begin $sformat(instruction_string, "%-10s r%-2d, %0d", "TLTI", op_rs, op_imm16); end
`RT_OP_TLTIU : begin $sformat(instruction_string, "%-10s r%-2d, %0d", "TLTIU", op_rs, op_imm16); end
`RT_OP_TNEI : begin $sformat(instruction_string, "%-10s r%-2d, %0d", "TNEI", op_rs, op_imm16); end
default : begin $sformat(instruction_string, "Invalid REGIMM instruction"); end
endcase // case (op_rt)
end // case: `OP_TYPE_REGIMM
`OP_TYPE_CP0 : begin
case (op_rs)
`RS_OP_MFC : begin
$sformat(instruction_string, "%-10s r%-2d, r%-2d", "MFC0", op_rt, op_rd);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
end
`RS_OP_MTC : begin $sformat(instruction_string, "%-10s r%-2d, r%-2d", "MTC0", op_rt, op_rd); end
`RS_OP_ERET : begin $sformat(instruction_string, "%-10s", "ERET"); end
default : begin $sformat(instruction_string, "Invalid CP0 instruction"); end
endcase // case (op_rs)
end // case: `OP_TYPE_CP0
`OP_ADDI : begin
$sformat(instruction_string, "%-10s r%-2d, r%-2d, %-0d", "ADDI", op_rt, op_rs, op_imm16);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
end
`OP_ADDIU : begin
$sformat(instruction_string, "%-10s r%-2d, r%-2d, %-0d", "ADDIU", op_rt, op_rs, op_imm16);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
end
`OP_ANDI : begin
$sformat(instruction_string, "%-10s r%-2d, r%-2d, 0x%-h", "ANDI", op_rt, op_rs, op_imm16);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
end
`OP_BEQ : begin $sformat(instruction_string, "%-10s r%-2d, r%-2d, 0x%-0h", "BEQ", op_rt, op_rs, $signed(id_pc) + $signed({op_imm16, 2\'b0}) + 4); end
`OP_BGTZ : begin $sformat(instruction_string, "%-10s r%-2d, 0x%-0h", "BGTZ", op_rs, $signed(id_pc) + $signed({op_imm16, 2\'b0}) + 4); end
`OP_BLEZ : begin $sformat(instruction_string, "%-10s r%-2d, 0x%-0h", "BLEZ", op_rs, $signed(id_pc) + $signed({op_imm16, 2\'b0}) + 4); end
`OP_BNE : begin $sformat(instruction_string, "%-10s r%-2d, r%-2d, 0x%-0h", "BNE", op_rt, op_rs, $signed(id_pc) + $signed({op_imm16, 2\'b0}) + 4); end
`OP_J : begin $sformat(instruction_string, "%-10s 0x%-h ", "J", {id_pc[31:28], op_imm26, 2\'b0}); end
`OP_JAL : begin $sformat(instruction_string, "%-10s 0x%-h ", "JAL", {id_pc[31:28], op_imm26, 2\'b0}); end
`OP_LB : begin
$sformat(instruction_string, "%-10s r%-2d, %0d(r%-2d)", "LB", op_rt, op_imm16, op_rs);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= mem[0x%h] = 0x%h (%0d)", wb_register, mem_address, wb_data, wb_data);
end
end
`OP_LBU : begin
$sformat(instruction_string, "%-10s r%-2d, %0d(r%-2d)", "LBU", op_rt, op_imm16, op_rs);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= mem[0x%h] = 0x%h (%0d)", wb_register, mem_address, wb_data, wb_data);
end
end
`OP_LH : begin
$sformat(instruction_string, "%-10s r%-2d, %0d(r%-2d)", "LH", op_rt, op_imm16, op_rs);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= mem[0x%h] = 0x%h (%0d)", wb_register, mem_address, wb_data, wb_data);
end
end
`OP_LHU : begin
$sformat(instruction_string, "%-10s r%-2d, %0d(r%-2d)", "LHU", op_rt, op_imm16, op_rs);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= mem[0x%h] = 0x%h (%0d)", wb_register, mem_address, wb_data, wb_data);
end
end
`OP_LL : begin
$sformat(instruction_string, "%-10s r%-2d, %0d(r%-2d)", "LL", op_rt, op_imm16, op_rs);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= mem[0x%h] = 0x%h (%0d)", wb_register, mem_address, wb_data, wb_data);
end
end
`OP_LUI : begin
$sformat(instruction_string, "%-10s r%-2d, %-5d", "LUI", op_rt, op_imm16);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
end
`OP_LW : begin
$sformat(instruction_string, "%-10s r%-2d, %0d(r%-2d)", "LW", op_rt, op_imm16, op_rs);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= mem[0x%h] = 0x%h (%0d)", wb_register, mem_address, wb_data, wb_data);
end
end
`OP_ORI : begin
$sformat(instruction_string, "%-10s r%-2d, r%-2d, 0x%0h", "ORI", op_rt, op_rs, op_imm16);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
end
`OP_SB : begin
$sformat(instruction_string, "%-10s r%-2d, %0d(r%-2d)", "SB", op_rt, op_imm16, op_rs);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "mem[0x%h] <= 0x%2h", mem_address, mem_store_data & 32\'hFF);
end
end
`OP_SC : begin
$sformat(instruction_string, "%-10s r%-2d, %0d(r%-2d)", "SC", op_rt, op_imm16, op_rs);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "mem[0x%h] <= 0x%h (%0d)", mem_address, mem_store_data, mem_store_data);
end
end
`OP_SH : begin
$sformat(instruction_string, "%-10s r%-2d, %0d(r%-2d)", "SH", op_rt, op_imm16, op_rs);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "mem[0x%h] <= 0x%4h", mem_address, mem_store_data & 32\'hFFFF);
end
end
`OP_SLTI : begin
$sformat(instruction_string, "%-10s r%-2d, r%-2d, %-0d", "SLTI", op_rt, op_rs, op_imm16);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
end
`OP_SLTIU : begin
$sformat(instruction_string, "%-10s r%-2d, r%-2d, %-0d", "SLTIU", op_rt, op_rs, op_imm16);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
end
`OP_SW : begin
$sformat(instruction_string, "%-10s r%-2d, %0d(r%-2d)", "SW", op_rt, op_imm16, op_rs);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "mem[0x%h] <= 0x%h (%0d)", mem_address, mem_store_data, mem_store_data);
end
end
`OP_XORI : begin
$sformat(instruction_string, "%-10s r%-2d, r%-2d, 0x%0h","XORI", op_rt, op_rs, op_imm16);
if (~wb_instruction_flushed) begin
$sformat(wb_register_string, "r%-2d <= 0x%h ( %-d ) | WE = %0d", wb_register, wb_data, wb_data, wb_we);
end
end
default : begin $sformat(instruction_string, "Invalid instruction"); end
endcase // case (opcode)
// store info to buffer
$sformat(trace, "| %9d | 0x%h: | 0x%h | %-30s | %-48s | %-7s |", $time - 1, id_pc, instruction, instruction_string, wb_register_string, (wb_instruction_flushed) ? "yes" : " "); // time - 1 (delay)
trace_buffer[trace_fill_counter] = trace;
trace_fill_counter = trace_fill_counter + 1;
end // if (~rst & ~halt)
end
endtask // decode_instruction
//--------------------------------------------------------------------------
// Decode exception and store in a buffer
task decode_exception;
reg [64*8-1:0] exception_string;
reg [31:0] cause_reg;
reg [20*8-1:0] cause_string;
begin
exception_string = 0;
cause_string = 0;
if(if_exception_ready | id_exception_ready | ex_exception_ready | mem_exception_ready) begin
#1
get_cp0_reg(13, cause_reg);
decode_cause(cause_reg, cause_string);
$sformat(exception_string, "INFO-MONITOR:\\tException. Cause: %-0s. Time: %0d ns", cause_string, $time - 1);
exception_buffer[exception_buffer_counter] = exception_string;
exception_buffer_counter = exception_buffer_counter + 1;
end
end
endtask // decode_exception
//--------------------------------------------------------------------------
// print stats
task print_stats;
integer index;
begin
$display("INFO-MONITOR:\\tHalt signal assertion (Time: %0d ns).", $time - 1);
if(exception_buffer_counter != 0) begin
$display("INFO-MONITOR:\\tPrinting exceptions:");
$display("------------");
for(index = 0; index < exception_buffer_counter; index = index + 1) begin
$display("%-0s", exception_buffer[index]);
end
$display("------------");
end
$display("INFO-MONITOR:\\tPrinting program trace, performing the memory dump, and the register dump.");
print_trace();
dump_memory();
print_gpr();
$display();
end
endtask // print_stats
//--------------------------------------------------------------------------
// Initial
//--------------------------------------------------------------------------
initial begin
trace_fill_counter <= 0;
exception_buffer_counter <= 0;
clk_core <= 1;
clk_bus <= 1;
rst <= 1;
end
//--------------------------------------------------------------------------
// clock
//--------------------------------------------------------------------------
always begin
#(`cycle/2) clk_core = !clk_core; // Core clock
end
always begin
#(`cycle/4) clk_bus = !clk_bus; // Bus clock = 2*Core clock
end
//--------------------------------------------------------------------------
// Decode instruction @ WB stage (finished instructions)
//--------------------------------------------------------------------------
always @(posedge clk_core) begin
#1
if((wb_exception_pc != 32\'b0 | wb_instruction != 32\'b0) & ~wb_instruction_stalled )begin // ignore first nops in the pipeline & bubbles
decode_instruction(wb_exception_pc,
wb_instruction,
wb_gpr_wa,
wb_gpr_wd,
wb_gpr_we,
wb_mem_address,
wb_mem_store_data
);
end
end // always @ (posedge clk_core)
//--------------------------------------------------------------------------
// Log exceptions
//--------------------------------------------------------------------------
always @(posedge clk_core) begin
decode_exception();
end
//--------------------------------------------------------------------------
// pipeline
//--------------------------------------------------------------------------
always @(posedge clk_core) begin
wb_exception_pc <= (rst) ? 32\'b0 : ((wb_stall) ? wb_exception_pc : mem_exception_pc);
ex_instruction <= (rst) ? 1\'b0 : ((ex_stall) ? ex_instruction : id_instruction);
mem_instruction <= (rst) ? 1\'b0 : ((mem_stall) ? mem_instruction : ex_instruction);
wb_instruction <= (rst) ? 32\'b0 : ((wb_stall) ? wb_instruction : mem_instruction);
wb_mem_address <= (rst) ? 32\'b0 : ((wb_stall) ? wb_mem_address : mem_address);
wb_mem_store_data <= (rst) ? 32\'b0 : ((wb_stall) ? wb_mem_store_data : mem_data);
id_instruction_stalled <= (rst) ? 1\'b0 : ((ex_stall) ? ex_instruction_stalled : if_stall);
id_instruction_flushed <= (rst) ? 1\'b0 : ((ex_stall) ? ex_instruction_flushed : if_flush);
ex_instruction_stalled <= (rst) ? 1\'b0 : ((ex_stall) ? ex_instruction_stalled : id_instruction_stalled | id_stall);
ex_instruction_flushed <= (rst) ? 1\'b0 : ((ex_stall) ? ex_instruction_flushed : id_instruction_flushed | id_flush);
mem_instruction_stalled <= (rst) ? 1\'b0 : ((mem_stall) ? mem_instruction_stalled : ex_instruction_stalled | ex_stall);
mem_instruction_flushed <= (rst) ? 1\'b0 : ((mem_stall) ? mem_instruction_flushed : ex_instruction_flushed | ex_flush);
wb_instruction_stalled <= (rst) ? 1\'b0 : ((wb_stall) ? wb_instruction_stalled : mem_instruction_stalled | mem_stall);
wb_instruction_flushed <= (rst) ? 1\'b0 : ((wb_stall) ? wb_instruction_flushed : mem_instruction_flushed | mem_flush);
end // always @ (posedge clk_core)
//--------------------------------------------------------------------------
// Start Simulation
//--------------------------------------------------------------------------
initial begin
$display("");
$display("--------------------------------------------------------------------------");
$display("INFO-MONITOR:\\tTesting the MIPS Core: BEGIN.");
$display("--------------------------------------------------------------------------");
$display();
`ifdef TEST
$display("INFO-MONITOR:\\tUsing the <%s> test", `TEST);
`endif
// dump the wave file
`ifdef NODUMP
$display("INFO-MONITOR:\\tDump of variables: DISABLED.");
`else
$display("INFO-MONITOR:\\tDump of variables: ENABLED.");
$dumpfile("tb_core.vcd");
$dumpvars(0, tb_core); // check this
`endif
// Reset
$display("INFO-MONITOR:\\tReset assertion (Time: %0d ns).", $time);
#(5*`cycle + 5)
rst <= 0;
$display("INFO-MONITOR:\\tReset deassertion (Time: %0d ns).", $time);
// wait until end
`ifdef TIMEOUT
$display("INFO-MONITOR:\\tUser timeout value: %0d cycles", `TIMEOUT);
$display("INFO-MONITOR:\\tCPU (core) frequency: %0d MHz", 1000/`cycle);
$display("------------");
#(`TIMEOUT*`cycle)
`else
$display("INFO-MONITOR:\\tUsind default timeout value: %d cycles", `TIMEOUT_DEFAULT);
$display("INFO-MONITOR:\\tCPU (core) frequency: %d MHz", 1000/`cycle);
$display("------------");
#(`TIMEOUT_DEFAULT*`cycle)
`endif // !`ifdef TIMEOUT
// Timeout. Abort
print_stats();
$display("--------------------------------------------------------------------------");
$display("INFO-MONITOR:\\tTesting the MIPS Core: Aborted. Timeout after %0d cycles.", $time/`cycle);
$display("--------------------------------------------------------------------------");
$display("");
$finish;
end // initial begin
//--------------------------------------------------------------------------
// Exit 0: Stop Simulation
//--------------------------------------------------------------------------
always @(negedge clk_core) begin
if(halt) begin
#1
print_stats();
$display("--------------------------------------------------------------------------");
$display("INFO-MONITOR:\\tTesting the MIPS Core: Finished after %0d cycles.", $time/`cycle);
$display("--------------------------------------------------------------------------");
$display("");
$finish;
end
end // always @ (negedge clk_core)
endmodule // monitor
// Local Variables:
// verilog-library-flags:("-y ../../../../Hardware/ -y utils/")
// flycheck-verilator-include-path:("../../../../Hardware/" "utils/")
// End:
|
//==================================================================================================
// Filename : antares_load_store_unit.v
// Created On : Sat Sep 5 10:38:09 2015
// Last Modified : Sat Nov 07 12:09:07 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Sim\xc3\xb3n Bol\xc3\xadvar
// Email : [email protected]
//
// Description : Handle memory access; using a 4-way handshaking protocol:
// 1.- Assert enable signal.
// 2.- Ready goes high when data is available.
// 3.- If Ready is high; enable signal goes low.
// 4.- Next cycle; if enable is low, clear Ready signal.
//
// Time diagram:
//
// Clock Tick: | | | | | | | | | | |
// ______ ___
// Enable: __| |_______| |______
// __ __
// Ready: _____| |________| |____
//==================================================================================================
`include "antares_defines.v"
module antares_load_store_unit (
input clk, // Clock
input rst, // Reset
// Instruction interface: LSU <-> CPU
input [31:0] imem_address, // Instruction address
output reg [31:0] imem_data, // Instruction data
// MEM interface: LSU <-> CPU
input [31:0] dmem_address, // Data address
input [31:0] dmem_data_i, // Data to memory
input dmem_halfword, // halfword access
input dmem_byte, // byte access
input dmem_read, // read data memory
input dmem_write, // write data memory
input dmem_sign_extend, // read data (byte/half) with sign extended
output reg [31:0] dmem_data_o, // data from memory
// Instruction Port: LSU <-> MEM[instruction]
input [31:0] iport_data_i, // Data from memory
input iport_ready, // memory is ready
input iport_error, // Bus error
output [31:0] iport_address, // data address
output [3:0] iport_wr, // write = byte select, read = 0000,
output iport_enable, // enable operation
// Data Port : LSU <-> (MEM[data], I/O)
input [31:0] dport_data_i, // Data from memory
input dport_ready, // memory is ready
input dport_error, // Bus error
output [31:0] dport_address, // data address
output [31:0] dport_data_o, // data to memory
output reg [3:0] dport_wr, // write = byte select, read = 0000,
output dport_enable, // enable operation
// pipeline signals
input exception_ready,
input mem_kernel_mode, // For exception logic
input mem_llsc, // Atomic operation
input id_eret, // for llsc1
output exc_address_if, // panic
output exc_address_l_mem, // panic
output exc_address_s_mem, // panic
output imem_request_stall, // long operation
output dmem_request_stall // long operation
);
//--------------------------------------------------------------------------
// wire and registers
//--------------------------------------------------------------------------
wire exc_invalid_word_iaddress; // Not word-aligned instructions address
wire exc_invalid_space_iaddress; // try to access I/O space
wire exc_invalid_word_maddress; // Not word-aligned data address
wire exc_invalid_half_maddress; // Not halfword-aligned data address
wire exc_invalid_space_maddress; // try to access kernel space
wire dmem_operation; // Read or Write?
wire data_word; // LW/SW operation
wire exc_invalid_maddress;
wire write_enable;
wire read_enable;
reg [29:0] llsc_address;
reg llsc_atomic;
wire llsc_mem_write_mask;
//--------------------------------------------------------------------------
// assignments
//--------------------------------------------------------------------------
// Check for invalid access from instruction port.
assign exc_invalid_word_iaddress = imem_address[1] | imem_address[0];
assign exc_invalid_space_iaddress = 0; // TODO: check for invalid IM access.
// Check for invalid access from data port.
assign exc_invalid_word_maddress = (dmem_address[1] | dmem_address[0]) & data_word;
assign exc_invalid_half_maddress = dmem_address[0] & dmem_halfword;
assign exc_invalid_space_maddress = ~mem_kernel_mode & (dmem_address < `ANTARES_SEG_2_SPACE_LOW);
assign exc_invalid_maddress = exc_invalid_space_maddress | exc_invalid_word_maddress | exc_invalid_half_maddress;
// Exception signals.
assign exc_address_if = exc_invalid_word_iaddress | exc_invalid_space_iaddress;
assign exc_address_l_mem = dmem_read & exc_invalid_maddress;
assign exc_address_s_mem = dmem_write & exc_invalid_maddress;
assign write_enable = dmem_write & ~exc_invalid_maddress & ~llsc_mem_write_mask;
assign read_enable = dmem_read & ~exc_invalid_maddress;
assign dmem_operation = (write_enable ^ read_enable) | mem_llsc;
assign data_word = ~(dmem_halfword | dmem_byte);
assign imem_request_stall = iport_enable;
assign dmem_request_stall = dport_enable;
assign iport_enable = (~rst & ~iport_ready & ~exception_ready & ~iport_error);
assign dport_enable = ~dport_ready & dmem_operation & ~dport_error;
//--------------------------------------------------------------------------
// Load Linked and Store Conditional logic
//--------------------------------------------------------------------------
/*
From XUM project:
A 32-bit register keeps track of the address for atomic Load Linked / Store Conditional
operations. This register can be updated during stalls since it is not visible to
forward stages. It does not need to be flushed during exceptions, since ERET destroys
the atomicity condition and there are no detrimental effects in an exception handler.
The atomic condition is set with a Load Linked instruction, and cleared on an ERET
instruction or when any store instruction writes to one or more bytes covered by
the word address register. It does not update on a stall condition.
The MIPS32 spec states that an ERET instruction between LL and SC will cause the
atomicity condition to fail. This implementation uses the ERET signal from the ID
stage, which means instruction sequences such as "LL SC" could appear to have an
ERET instruction between them even though they don\'t. One way to fix this is to pass
the ERET signal through the pipeline to the MEM stage. However, because of the nature
of LL/SC operations (they occur in a loop which checks the result at each iteration),
an ERET will normally never be inserted into the pipeline programmatically until the
LL/SC sequence has completed (exceptions such as interrupts can still cause ERET, but
they can still cause them in the LL SC sequence as well). In other words, by not passing
ERET through the pipeline, the only possible effect is a performance penalty. Also this
may be irrelevant since currently ERET stalls for forward stages which can cause exceptions,
which includes LL and SC.
*/
always @(posedge clk) begin
llsc_address <= (rst) ? 30\'b0 : ( (dmem_read & mem_llsc) ? dmem_address[31:2] : llsc_address );
end
always @(posedge clk) begin
if (rst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
llsc_atomic <= 1\'h0;
// End of automatics
end
else if (dmem_read) begin
llsc_atomic <= (mem_llsc) ? 1\'b1 : llsc_atomic;
end
else if (id_eret | (~dmem_request_stall & dmem_write & (dmem_address[31:2] == llsc_address))) begin
llsc_atomic <= 1\'b0;
end
else begin
llsc_atomic <= llsc_atomic;
end
end // always @ (posedge clk)
// If atomic and using the same address: enable the write. Else, ignore.
assign llsc_mem_write_mask = (mem_llsc & dmem_write & (~llsc_atomic | (dmem_address[31:2] != llsc_address)));
//--------------------------------------------------------------------------
// Map address and I/O ports
//--------------------------------------------------------------------------
assign iport_address = imem_address[31:0]; // full assign
assign dport_address = dmem_address[31:0]; // full assign
//--------------------------------------------------------------------------
// Read instruction memory
//--------------------------------------------------------------------------
assign iport_wr = 4\'b0000; // DO NOT WRITE
always @(*) begin
imem_data = iport_data_i; // simple
end
//--------------------------------------------------------------------------
// Read from data data port.
//--------------------------------------------------------------------------
always @(*) begin
if (dmem_byte) begin
case (dmem_address[1:0])
2\'b00 : dmem_data_o = (dmem_sign_extend) ? { {24{dport_data_i[7]} }, dport_data_i[7:0] } : {24\'b0, dport_data_i[7:0]};
2\'b01 : dmem_data_o = (dmem_sign_extend) ? { {24{dport_data_i[15]} }, dport_data_i[15:8] } : {24\'b0, dport_data_i[15:8]};
2\'b10 : dmem_data_o = (dmem_sign_extend) ? { {24{dport_data_i[23]} }, dport_data_i[23:16] } : {24\'b0, dport_data_i[23:16]};
2\'b11 : dmem_data_o = (dmem_sign_extend) ? { {24{dport_data_i[31]} }, dport_data_i[31:24] } : {24\'b0, dport_data_i[31:24]};
default : dmem_data_o = 32\'hx;
endcase // case (dmem_address[1:0])
end
else if (dmem_halfword) begin
case (dmem_address[1])
1\'b0 : dmem_data_o = (dmem_sign_extend) ? { {16{dport_data_i[15]} }, dport_data_i[15:0] } : {16\'b0, dport_data_i[15:0]};
1\'b1 : dmem_data_o = (dmem_sign_extend) ? { {16{dport_data_i[31]} }, dport_data_i[31:16] } : {16\'b0, dport_data_i[31:16]};
default : dmem_data_o = 32\'hx;
endcase // case (dmem_address[1])
end
else if (mem_llsc & dmem_write) begin
dmem_data_o = (llsc_atomic & (dmem_address[31:2] == llsc_address)) ? 32\'h0000_0001 : 32\'h0000_0000;
end
else begin
dmem_data_o = dport_data_i;
end
end // always @ (*)
//--------------------------------------------------------------------------
// Write to data port
// Format data:
// byte : {b, b, b, b}
// half : {h, h}
// word : {w}
//
// Modify to implement Reverse Endian
//--------------------------------------------------------------------------
always @(*) begin
dport_wr = 4\'b0000;
if (write_enable) begin
dport_wr[3] = (dmem_byte & (dmem_address[1:0] == 2\'b11)) | (dmem_halfword & dmem_address[1]) | data_word;
dport_wr[2] = (dmem_byte & (dmem_address[1:0] == 2\'b10)) | (dmem_halfword & dmem_address[1]) | data_word;
dport_wr[1] = (dmem_byte & (dmem_address[1:0] == 2\'b01)) | (dmem_halfword & ~dmem_address[1]) | data_word;
dport_wr[0] = (dmem_byte & (dmem_address[1:0] == 2\'b00)) | (dmem_halfword & ~dmem_address[1]) | data_word;
end
end
assign dport_data_o[31:24] = (dmem_byte) ? dmem_data_i[7:0] : ((dmem_halfword) ? dmem_data_i[15:8] : dmem_data_i[31:24]);
assign dport_data_o[23:16] = (dmem_byte | dmem_halfword) ? dmem_data_i[7:0] : dmem_data_i[23:16];
assign dport_data_o[15:8] = (dmem_byte) ? dmem_data_i[7:0]: dmem_data_i[15:8];
assign dport_data_o[7:0] = dmem_data_i[7:0];
endmodule // antares_load_store_unit
|
//==================================================================================================
// Filename : tb_core.v
// Created On : Sun Sep 6 22:43:11 2015
// Last Modified : Sat Sep 12 21:24:12 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Sim\xc3\xb3n Bol\xc3\xadvar
// Email : [email protected]
//
// Description : Antares core testbench
//==================================================================================================
`include "antares_defines.v"
`timescale 1ns / 100ps
`define MEM_ADDR_WIDTH 12 // 2^(MEM_ADDR_WIDTH + 2) = 16 KB of memory
module tb_core;
//--------------------------------------------------------------------------
// wires
//--------------------------------------------------------------------------
wire clk_core;
wire clk_bus;
wire rst;
wire [31:0] dport_address;
wire [31:0] dport_data_i;
wire [31:0] dport_data_o;
wire dport_enable;
wire [3:0] dport_wr;
wire dport_ready;
wire dport_error;
wire [31:0] iport_address;
wire [31:0] iport_data_i;
wire iport_enable;
wire [3:0] iport_wr;
wire iport_ready;
wire iport_error;
wire halted;
reg rst_sync;
//--------------------------------------------------------------------------
// Assigns
//--------------------------------------------------------------------------
assign iport_error = 1\'b0; // No errors
assign dport_error = 1\'b0; // No errors
always @(posedge clk_core) begin
rst_sync <= rst;
end
//--------------------------------------------------------------------------
// MIPS CORE
//--------------------------------------------------------------------------
antares_core #(
.ENABLE_HW_MULT ( 1 ),
.ENABLE_HW_DIV ( 1 ),
.ENABLE_HW_CLOZ ( 1 )
)
core(
// Outputs
.halted ( halted ),
.iport_address ( iport_address[31:0] ),
.iport_wr ( iport_wr[3:0] ),
.iport_enable ( iport_enable ),
.dport_address ( dport_address[31:0] ),
.dport_data_o ( dport_data_o[31:0] ),
.dport_wr ( dport_wr[3:0] ),
.dport_enable ( dport_enable ),
// Inputs
.clk ( clk_core ),
.rst ( rst_sync ),
.interrupts ( 5\'b0 ), // No external interrupts.
.nmi ( 1\'b0 ), // No external interrupts.
.iport_data_i ( iport_data_i[31:0] ),
.iport_ready ( iport_ready ),
.dport_data_i ( dport_data_i[31:0] ),
.dport_ready ( dport_ready ),
.iport_error ( iport_error ),
.dport_error ( dport_error )
);
//--------------------------------------------------------------------------
// Instruction/Data Memory
// Port A = Instruccion
// Port B = Data
//--------------------------------------------------------------------------
memory #(
.MEM_ADDR_WIDTH( `MEM_ADDR_WIDTH ) // Memory size
)
memory0(
.clk ( clk_bus ),
.rst ( rst_sync ),
.a_addr ( iport_address[2 +: `MEM_ADDR_WIDTH] ), // instruction port
.a_din ( 32\'hB00B_B00B ),
.a_wr ( iport_wr[3:0] ),
.a_enable ( iport_enable ),
.a_dout ( iport_data_i[31:0] ),
.a_ready ( iport_ready ),
.b_addr ( dport_address[2 +: `MEM_ADDR_WIDTH] ), // data port
.b_din ( dport_data_o[31:0] ),
.b_wr ( dport_wr[3:0] ),
.b_enable ( dport_enable ),
.b_dout ( dport_data_i[31:0] ),
.b_ready ( dport_ready )
);
//--------------------------------------------------------------------------
// Monitor
//--------------------------------------------------------------------------
monitor monitor0(
.halt ( halted ),
.if_stall ( core.if_stall ),
.if_flush ( core.if_flush ),
.id_stall ( core.id_stall ),
.id_flush ( core.id_flush ),
.ex_stall ( core.ex_stall ),
.ex_flush ( core.ex_flush ),
.mem_stall ( core.mem_stall ),
.mem_flush ( core.mem_flush ),
.wb_stall ( core.wb_stall ),
.mem_exception_pc ( core.mem_exception_pc ),
.id_instruction ( core.id_instruction ),
.wb_gpr_wa ( core.wb_gpr_wa ),
.wb_gpr_wd ( core.wb_gpr_wd ),
.wb_gpr_we ( core.wb_gpr_we ),
.mem_address ( core.mem_alu_result ),
.mem_data ( core.mem_mem_store_data ),
.if_exception_ready ( core.cpzero0.if_exception_ready ),
.id_exception_ready ( core.cpzero0.id_exception_ready ),
.ex_exception_ready ( core.cpzero0.ex_exception_ready ),
.mem_exception_ready ( core.cpzero0.mem_exception_ready ),
.clk_core ( clk_core ),
.clk_bus ( clk_bus ),
.rst ( rst )
);
endmodule
// Local Variables:
// verilog-library-flags:("-y ../../../Hardware/ -y utils/")
// flycheck-verilator-include-path:("../../../Hardware/" "utils/")
// End:
|
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|
always @(negedge reset or posedge clk) begin
if (reset == 0) begin
d_out <= 16'h0000;
d_out_mem[resetcount] <= d_out;
laststoredvalue <= d_out;
end else begin
d_out <= d_out + 1'b1;
end
end
always @(bufreadaddr)
bufreadval = d_out_mem[bufreadaddr];
|
/*
* Utility functions for verilog testbenches
*
* Copyright (C) 2016 Olof Kindgren <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
//I have been patched
module vlog_functions;
task progress_bar;
input [8*32:1] msg;
input integer current;
input integer total;
begin
\t if(!(current%(total/10)))
\t $display("%0s %0d/%0d", msg, current, total);
end
endtask
endmodule
|
module ID_stage(
input [5:0] opcode,
//other inputs
input RS_full, ROB_full, free_list_empty,
input stall_recover,
input stall_arbiter, //when one ALU op and one load complete together, stall one cycle
//control signal used in Decode
output writeRd,
//control signal used in Dispatch
output isDispatch, //rob enable signal
output MemOp, //used in LSQ, and ROB, asserted if it is a memory operation
output RegDest, //freelist read enable
output RS_en,
output ldic, isSignEx, immed,
output alu_ctrl0, alu_ctrl1, alu_ctrl2, alu_ctrl3,
output isJump, isJR,
output ld, //this signal is 1 for load and 0 for stores
output mem_wen, //memory write enable
output link,
output strcnt, stpcnt,
output halt
);
decoder i_decoder();
stall_control i_stall_control();
endmodule
|
module OoO_cpu(
input clk, rst
);
//////////////////////////insturction fetch and IF/DP pipeline////////////////////////////////
/////////////////some temporary signals/////////////////
wire changeFlow_IF; assign changeFlow_IF = 0;
wire [31:0] jb_addr_IF; assign jb_addr_IF = {32{1'b0}};
wire stall_PC; assign stall_PC = 0;
wire stall_IF_DP; assign stall_IF_DP = 0;
wire flush_IF_DP; assign flush_IF_DP = 0;
wire [31:0] instr_IF_DP;
wire [31:0] pc_1_IF_DP;
///////////////////////////////////////////////////////
IF_stage i_IF_stage(
.clk(clk),
.rst(rst),
.changeFlow(changeFlow_IF),
.jb_addr(jb_addr_IF),
.stall_PC(stall_PC),
.stall_IF_DP(stall_IF_DP),
.flush_IF_DP(flush_IF_DP),
.instr_IF_DP(instr_IF_DP),
.pc_1_IF_DP(pc_1_IF_DP));
/////////////////////////////////decoder////////////////////////////////////
wire writeRd; //asserted for write rd, deasserted for write rt
wire RegDest; //asserted when write register
wire isDispatch; //
wire mem_wen;
wire mem_ren;
wire read_rs, read_rt;
//to alu reservation station
wire alloca_RS_en;
wire ldic, isSignedEx, isImmed;
wire alu_ctrl0, alu_ctrl1, alu_ctrl2, alu_ctrl3;
wire isJump, isJR;
wire link;
decoder i_decoder(
.opcode(instr_IF_DP[31:26]),
.writeRd(writeRd),
.RegDest(RegDest),
.isDispatch(isDispatch),
.mem_wen(mem_wen),
.mem_ren(mem_ren),
.read_rs(read_rs),
.read_rt(read_rt),
.alloc_RS_en(alloc_RS_en),
.ldic(ldic),
.isSignEx(isSignEx),
.isImmed(isImmed),
.alu_ctrl0(alu_ctrl0),
.alu_ctrl1(alu_ctrl1),
.alu_ctrl2(alu_ctrl2),
.alu_ctrl3(alu_ctrl3),
.isJump(isJump),
.isJR(isJR),
.link(link));
////////////////////////////////////////////////////////////////////////////
//////////////////////////map table//////////////////////////////////////////
////temporary signals/////////////////////////////////////////////////////
wire hazard_stall_map_table; assign hazard_stall_map_table = 0;
/////////////recovery////////////////
wire [4:0] recover_rd;
wire [5:0] p_rd_flush;
/////////////////complete///////
wire [5:0] p_rd_compl; assign p_rd_compl = 6'h00;
wire complete = 0;
wire RegDest_compl = 0;
//////////////////////////////////////////////////////////////////////////
wire [4:0] l_rs_map_table;
wire [4:0] l_rt_map_table;
wire [4:0] l_rd_map_table;
wire [5:0] PR_new; //from free list
////////////////these four to reservation station
wire [5:0] p_rs;
wire p_rs_v;
wire [5:0] p_rt;
wire p_rt_v;
wire [5:0] PR_old_DP; //to ROB
//from ROB, for recovery
wire recover;
wire RegDest_ROB;
wire [4:0] flush_rd;
wire [5:0] PR_old_flush;
assign l_rs_map_table = instr_IF_DP[25:21];
assign l_rt_map_table = instr_IF_DP[20:16];
assign l_rd_map_table = writeRd ? instr_IF_DP[15:11] : instr_IF_DP[20:16];
map_table i_map_table(
.clk(clk),
.rst(rst),
.hazard_stall(hazard_stall_map_table),
.l_rs(l_rs_map_table),
.l_rt(l_rt_map_table),
.l_rd(l_rd_map_table),
.isDispatch(isDispatch),
.RegDest(RegDest),
.p_rd_new(PR_new),
.recover_rd(flush_rd),
.p_rd_flush(PR_old_flush),
.recover(recover),
.RegDest_ROB(RegDest_ROB),
.p_rd_compl(p_rd_compl),
.complete(complete),
.RegDest_compl(RegDest_compl),
.p_rs(p_rs),
.p_rt(p_rt),
.p_rs_v(p_rs_v),
.p_rt_v(p_rt_v),
.PR_old_rd(PR_old_DP));
///////////////////////////////free list ////////////////////////////////////
///////////////temporary signals//////////////////////
wire hazard_stall_free_list = 0;
/////////////////////////////////////////////////////
wire free_list_empty;
wire [5:0] PR_old_RT; //from re-order buffer
wire RegDest_retire;
wire retire_reg;
//for recovery
wire [5:0] PR_new_flush;
free_list_new i_free_list_new(
.PR_old(PR_old_RT),
.RegDest_retire(RegDest_retire),
.retire_reg(retire_reg),
.RegDest(RegDest),
.clk(clk),
.rst(rst),
.hazard_stall(hazard_stall_free_list),
.recover(recover),
.PR_new_flush(PR_new_flush),
.RegDest_ROB(RegDest_ROB),
.PR_new(PR_new),
.empty(free_list_empty));
////////////////////////////reorder buffer/////////////////////////////////////
///////////////temporary signals/////////////////////
wire [3:0] rob_num_compl = 4'h0;
/////////////these two from complete stage
wire changeFlow_rob_in = 0;
wire [31:0] jb_addr_rob_in = {32{1'b0}};
wire hazard_stall_rob = 0;
/////////////////////////////////////////////////////
//////these two go to store queue
wire retire_ST;
wire [3:0] retire_rob;
wire rob_full, rob_empty;
wire [3:0] flush_rob_num;
wire [3:0] rob_num_dp; //rob number written into reservation station
reorder_buffer_beh i_reorder_buffer(
.rst(rst),
.clk(clk),
.isDispatch(isDispatch),
.isSW(mem_wen),
.RegDest(RegDest),
.PR_old_DP(PR_old_DP),
.PR_new_DP(PR_new),
.rd_DP(l_rd_map_table),
.complete(complete),
.rob_number(rob_num_compl),
.jb_addr(jb_addr_rob_in),
.changeFlow(changeFlow_rob_in),
.hazard_stall(hazard_stall_rob),
.rob_num_dp(rob_num_dp),
.PR_old_RT(PR_old_RT),
.RegDest_retire(RegDest_retire),
.retire_reg(retire_reg),
.retire_ST(retire_ST),
.retire_rob(retire_rob),
.full(full),
.empty(empty),
.RegDest_out(RegDest_ROB),
.PR_old_flush(PR_old_flush),
.PR_new_flush(PR_new_flush),
.rd_flush(flush_rd),
.out_rob_num(flush_rob_num),
.changeFlow_out(changeFlow_IF),
.changeFlow_addr(jb_addr_IF),
.recover(recover));
///////////////////////////////////////////ls_station//////////////////////////////////
///////////temporary wires/////////////////
wire hazard_stall_lss; assign hazard_stall_lss = 0;
wire stall_issue_lss = 0;
///////////////////////////////////////////
wire [5:0] p_rs_lss, p_rt_lss, p_rd_lss;
wire [15:0] immed_lss;
wire [3:0] rob_num_lss;
wire RegDest_lss, mem_ren_lss, mem_wen_lss;
wire issue_lss;
wire lss_full;
ls_station i_lss( .clk(clk),
.rst(rst),
.isDispatch(isDispatch),
.rob_num_dp(rob_num_dp), //from rob in dispatch stage
.p_rd_new(PR_new), //from free list
.p_rs(p_rs), //these four signals from map table
.read_rs(read_rs), //from decoder ********
.v_rs(p_rs_v),
.p_rt(p_rt),
.read_rt(read_rt), //from decoder ********
.v_rt(p_rt_v),
.mem_ren(mem_ren), //from decoder ********
.mem_wen(mem_wen), //from decoder ********
.immed(instr_IF_DP[15:0]), //from decode
.stall_hazard(hazard_stall_lss),
.stall_issue(stall_issue_lss),
.recover(recover), //from ROB
.rob_num_rec(flush_rob_num), //from ROB
.p_rd_compl(p_rd_compl),
.RegDest_compl(RegDest_compl),
.complete(complete),
.p_rs_out(p_rs_lss),
.p_rt_out(p_rt_lss),
.p_rd_out(p_rd_lss),
.immed_out(immed_lss),
.rob_num_out(rob_num_lss),
.RegDest_out(RegDest_lss),
.mem_ren_out(mem_ren_lss),
.mem_wen_out(mem_wen_lss),
.issue(issue_lss),
.lss_full(lss_full));
////////////////////////////////ALU reservation station///////////////////////////////////
wire rs_alu_full;
///////////////temporary signals////////////
wire stall_hazard_rs_alu;
assign stall_hazard_rs_alu = 0;
wire stall_issue_alu = 0;
////////////////////////////////////////////
wire issue_en_alu;
//to EX (IS/EX pipeline reg)
wire [16:0] EX_ctrl_in;
//[5:0] opcode, [6] ldic, [7] isSignEx, [8] isImmed, [9] alu_ctrl0, [10] alu_ctrl1, [11] alu_ctrl2, [12] alu_ctrl3
//[13] isJump, [14] isJR, [15] RegDest, [16] link
assign EX_ctrl_in = { link,
RegDest,
isJR,
isJump,
alu_ctrl3, alu_ctrl2, alu_ctrl1, alu_ctrl0,
isImmed, isSignEx,
ldic, //load instruction count
instr_IF_DP[31:26] };
wire [31:0] PC_out_rs_alu;
wire [15:0] imm_rs_alu;
//go through EX (IS/EX pipeline reg)stage, but used in COMPL stage
wire [3:0] EX_rob_alu;
wire [16:0] EX_ctrl_out;
wire [5:0] p_rd_rs_alu;
//to physical register
wire [5:0] p_rs_out_alu, p_rt_out_alu;
rs_alu i_rs_alu(
.clk(clk),
.rst(rst),
.num_rob_entry(rob_num_dp), //rob number of rob in dispatch stage
.PC_in(pc_1_IF_DP), //
.EX_ctrl_in(EX_ctrl_in),
.p_rs_in(p_rs), //from map table
.p_rt_in(p_rt),
.p_rs_rdy_in(p_rs_v), //valid bits from map table
.p_rt_rdy_in(p_rt_v),
.rs_read(read_rs), //from the decoder, indicates if read rs/rt
.rt_read(read_rt),
.imm_bits_in(instr_IF_DP[15:0]), //immediate value
.p_rd_new(PR_new), //from free list
.alloc_RS_en(alloc_RS_en),
.recover(recover),
.rec_rob_entry(flush_rob_num),
.stall_hazard(stall_hazard_rs_alu),
.stall_issue(stall_issue_alu),
.bus_en(complete && RegDest_compl), //set ready bit only if RegDest is 1
.tag(p_rd_compl),
.issue_en(issue_en_alu),
.PC_out(PC_out_rs_alu), //to EX stage
.rob_id_out(EX_rob_alu),
.EX_ctrl_out(EX_ctrl_out), //one part to EX, the other part used in COMPL
.p_rs_out(p_rs_out_alu), //to physical register
.p_rt_out(p_rt_out_alu),
.imm_bits_out(imm_rs_alu),
.p_rd_out(p_rd_rs_alu),
.stl_dec_rs_alu_full(rs_alu_full));
/////////temporary wires////////////////////
wire [31:0] result_compl;
assign result_compl = 32'h00000000;
////////////////////////////////////////////
wire [31:0] rs_data_IS_EX_alu, rt_data_IS_EX_alu;
/////////////////////////////////physical register for ALU////////////////////////////
physical_register i_physical_register_ALU(
.raddr0(p_rs_out_alu),
.raddr1(p_rt_out_alu),
.we(RegDest_compl),
.waddr(p_rd_compl),
.din(result_compl),
.clk(clk),
.dout0(rs_data_IS_EX_alu),
.dout1(rt_data_IS_EX_alu));
//////////////////////////////IS/EX pipeline register for ALU instructions///////////////
//control signals
reg ldic_IS_EX, isSignedEx_IS_EX, immed_IS_EX_alu;
reg alu_ctrl0_IS_EX, alu_ctrl1_IS_EX, alu_ctrl2_IS_EX, alu_ctrl3_IS_EX;
reg isJump_IS_EX, isJR_IS_EX;
reg link_IS_EX, RegDest_IS_EX_alu;
///data and address signals
reg [31:0] pc_1_IS_EX;
reg [15:0] immed_value_IS_EX_alu;
reg [3:0] rob_IS_EX_alu;
reg [5:0] p_rd_IS_EX_alu;
reg [5:0] opcode_IS_EX;
reg issue_en_IS_EX_alu;
//[5:0] opcode, [6] ldic, [7] isSignEx, [8] isImmed, [9] alu_ctrl0, [10] alu_ctrl1, [11] alu_ctrl2, [12] alu_ctrl3
//[13] isJump, [14] isJR, [15] RegDest, [16] link
/////////////////////////////
///////control signals
always @(posedge clk or negedge rst) begin
if (!rst) begin
{ldic_IS_EX, isSignedEx_IS_EX, immed_IS_EX_alu, alu_ctrl0_IS_EX, alu_ctrl1_IS_EX, alu_ctrl2_IS_EX, alu_ctrl3_IS_EX} <= 0;
{isJump_IS_EX, isJR_IS_EX} <= 0;
{link_IS_EX, RegDest_IS_EX_alu} <= 0;
end
else if ((recover && (rob_IS_EX_alu == flush_rob_num)) || !issue_en_alu) begin //flush this pipeline register
{ldic_IS_EX, isSignedEx_IS_EX, immed_IS_EX_alu, alu_ctrl0_IS_EX, alu_ctrl1_IS_EX, alu_ctrl2_IS_EX, alu_ctrl3_IS_EX} <= 0;
{isJump_IS_EX, isJR_IS_EX} <= 0;
{link_IS_EX, RegDest_IS_EX_alu} <= 0;
issue_en_IS_EX_alu <= 0;
end
else begin
{ldic_IS_EX, isSignedEx_IS_EX, immed_IS_EX_alu, alu_ctrl0_IS_EX, alu_ctrl1_IS_EX, alu_ctrl2_IS_EX, alu_ctrl3_IS_EX}
<= {EX_ctrl_out[6], EX_ctrl_out[7], EX_ctrl_out[8], EX_ctrl_out[9], EX_ctrl_out[10], EX_ctrl_out[11], EX_ctrl_out[12]};
{isJump_IS_EX, isJR_IS_EX} <= {EX_ctrl_out[13], EX_ctrl_out[14]};
{link_IS_EX, RegDest_IS_EX_alu} <= {EX_ctrl_out[16], EX_ctrl_out[15]};
issue_en_IS_EX_alu <= issue_en_alu;
end
end
//data and address pipeline register
always @(posedge clk or negedge rst) begin
if (!rst) begin
pc_1_IS_EX <= 0;
immed_value_IS_EX_alu <= 0;
rob_IS_EX_alu <= 0;
p_rd_IS_EX_alu <= 0;
opcode_IS_EX <= 0;
end
else begin
pc_1_IS_EX <= PC_out_rs_alu;
immed_value_IS_EX_alu <= imm_rs_alu;
rob_IS_EX_alu <= EX_rob_alu;
p_rd_IS_EX_alu <= p_rd_rs_alu;
opcode_IS_EX <= EX_ctrl_out[5:0];
end
end
////temporary wires//////////
wire [15:0] instr_cnt, cycle_cnt;
assign instr_cnt = 16'h0000;
assign cycle_cnt = 16'h0000;
/////////////////////////////
wire [31:0] alu_result_EX;
wire [31:0] jb_addr_EX;
wire changeFlow_EX;
/////////////////////////////////functional units////////////////////////////////////////
EX_stage_OoO i_EX_stage_OoO(
.instr_cnt(instr_cnt),
.cycle_cnt(cycle_cnt),
.rs_data(rs_data_IS_EX_alu),
.rt_data(rt_data_IS_EX_alu),
.pc_1(pc_1_IS_EX),
.immed_value(immed_value_IS_EX_alu),
.opcode(opcode_IS_EX),
.ldic(ldic_IS_EX),
.isSignEx(isSignedEx_IS_EX),
.immed(immed_IS_EX_alu),
.alu_ctrl0(alu_ctrl0_IS_EX),
.alu_ctrl1(alu_ctrl1_IS_EX),
.alu_ctrl2(alu_ctrl2_IS_EX),
.alu_ctrl3(alu_ctrl3_IS_EX),
.isJump(isJump_IS_EX),
.isJR(isJR_IS_EX),
.link(link_IS_EX),
.alu_result(alu_result_EX),
.changeFlow(changeFlow_EX),
.jb_addr(jb_addr_EX));
wire [5:0] p_rd_EX_alu;
assign p_rd_EX_alu = link ? 6'h19 : p_rd_IS_EX_alu; //don't use $r31 in assembly code
/////////////////////////////////physical register for MEM////////////////////////////
//////////////////////////////////
//physical register serves as part of IS_EX pipeline register
wire [31:0] rs_data_IS_EX_ls, rt_data_IS_EX_ls;
physical_register i_physical_register_LS(
.raddr0(p_rs_lss),
.raddr1(p_rt_lss),
.we(RegDest_compl),
.waddr(p_rd_compl),
.din(result_compl),
.clk(clk),
.dout0(rs_data_IS_EX_ls),
.dout1(rt_data_IS_EX_ls));
/////////////IS_EX pipeline register, for LS/ST/////////////////////////////////////
///*****************WILL CONSIDER STALL HERE later
reg [5:0] p_rd_IS_EX_ls;
reg [15:0] immed_IS_EX_ls;
reg [3:0] rob_num_IS_EX_ls;
reg RegDest_IS_EX_ls;
reg mem_ren_IS_EX_ls;
reg mem_wen_IS_EX_ls;
reg issue_IS_EX_ls;
always @(posedge clk or negedge rst) begin
if (!rst) begin
{p_rd_IS_EX_ls, immed_IS_EX_ls, rob_num_IS_EX_ls} <= 0;
{RegDest_IS_EX_ls, mem_ren_IS_EX_ls, mem_wen_IS_EX_ls, issue_IS_EX_ls} <= 0;
end
else if ((recover && (rob_num_IS_EX_ls == flush_rob_num)) || (!issue_lss)) begin
{RegDest_IS_EX_ls, mem_ren_IS_EX_ls, mem_wen_IS_EX_ls, issue_IS_EX_ls} <= 0;
end
else begin
{p_rd_IS_EX_ls, immed_IS_EX_ls, rob_num_IS_EX_ls} <= {p_rd_lss, immed_lss, rob_num_lss};
{RegDest_IS_EX_ls, mem_ren_IS_EX_ls, mem_wen_IS_EX_ls, issue_IS_EX_ls} <= {RegDest_lss, mem_ren_lss, mem_wen_lss, issue_lss};
end
end
/////////////////////////////store queue/////////////////////////////
////////temporary wires/////////////
wire hazard_stall_store_queue; assign hazard_stall_store_queue = 0;
///////////////////////////////////
wire sq_full;
wire isLS_CMP; //************************need to check later***********************//
wire [31:0] load_result_CMP;
wire [5:0] ls_p_rd_CMP;
wire [3:0] ls_rob_CMP;
wire ls_RegDest_CMP;
////////////////////////////first connect the complete from store queue
store_queue i_store_queue(
.clk(clk),
.rst(rst),
.issue(issue_IS_EX_ls),
.mem_wen(mem_wen_IS_EX_ls),
.mem_ren(mem_ren_IS_EX_ls),
.rs_data(rs_data_IS_EX_ls),
.rt_data(rt_data_IS_EX_ls),
.immed(immed_IS_EX_ls),
.rob_in(rob_num_IS_EX_ls),
.p_rd_in(p_rd_IS_EX_ls),
.stall_hazard(hazard_stall_store_queue),
.retire_ST(retire_ST),
.retire_rob(retire_rob),
.recover(recover),
.rec_rob(flush_rob_num),
.sq_full(sq_full),
.isLS(isLS_CMP),
.load_result(load_result_CMP),
.ls_p_rd(ls_p_rd_CMP),
.ls_rob(ls_rob_CMP),
.ls_RegDest(ls_RegDest_CMP));
endmodule
|
//load_store station is for load-store instruction, they will be issued in order
//dispatch: p_rs, p_rt, immed, p_rd, some control signals
//issue: if the head is ready, issue it
//complete: receive <PR_rd#, RegDest_compl> from CDB, set the valid bit
module ls_station(
input clk, rst,
//from dispatch stage
input isDispatch,
input [3:0] rob_num_dp,
input [5:0] p_rd_new, //this rd from decode stage, it is actually rt for load
input [5:0] p_rs,
input read_rs, //asserted if rs is read
input v_rs, //this input is from map table, if rs is not used, set this to 1
input [5:0] p_rt,
input read_rt,
input v_rt,\t
input mem_ren, mem_wen, //enable signal for LSQ can be generated from these two signals
input [15:0] immed,
input stall_hazard,
input stall_issue,
//from branch/jump recovery
input recover,
input [3:0] rob_num_rec, //flush the instruction that has ROB match
//from complete stage
input [5:0] p_rd_compl, //set the complete bit if register p_rd_compl match rs or rt
input RegDest_compl,
input complete,
output [5:0] p_rs_out, p_rt_out,
output [5:0] p_rd_out, //part of the result
output [15:0] immed_out,
output [3:0] rob_num_out,
output RegDest_out, //for load instruction, write register, if mem_ren is 1, this must be 1, part of result
output mem_ren_out, //for load instruction, read memory
output mem_wen_out, //for store instruction, write memory
output issue, //asserted if an instruction issued
output lss_full
);
//[41]: isLW, [40]: isST, [39:36]:rob_num, [35:30] p_rd, [29:24]: p_rs, [23]:v_rs
//[22:17]: p_rt, [16] v_rt, [15:0] immed,
reg [41:0] ls_station [0:3];
reg [3:0] lss_valid; //valid array for the lss, initialized to 0, when allocate set to 1, deallocated set to 0
reg [2:0] counter;
reg [3:0] head, tail;
reg [1:0] head_addr;
wire read, write;
wire head_rdy; //the head is ready to be issued
assign write = isDispatch && !stall_hazard && !lss_full && !recover && (mem_ren || mem_wen);
assign read = !stall_hazard && !recover && head_rdy && lss_valid[head_addr] && !stall_issue; //stall_hazard from outside, asserted if other blocks have hazard
//counter recording full or empty status
always @(posedge clk or negedge rst) begin
if (!rst)
counter <= 3'b000;
else if (write && read)
counter <= counter;
else if (write)
counter <= counter + 1;
else if (read)
counter <= counter - 1;
end
assign lss_full = (counter == 3'b100);
//increase head when read, increase tail when write
always @(posedge clk or negedge rst) begin
if (!rst) begin
head <= 4'b0001;
head_addr <= 2'b00;
tail <= 4'b0001;
end
else begin
if (write) begin
tail <= {tail[2:0], tail[3]};
\t\tend
if (read) begin
head <= {head[2:0], head[3]};
head_addr <= head_addr + 1;
end\t\t\t
end
end
///////////////////////////////////combinational logic///////////////////////////////////////////////////
wire [3:0] rob_match_array; //[2] ismatch [1:0] addr
wire [3:0] rs_match_array, rt_match_array;
//comparator array for flushing instruction
genvar j;
generate
for (j = 0; j < 4; j = j + 1) begin : combinational
assign rob_match_array[j] = (ls_station[j][39:36] == rob_num_rec) && lss_valid[j];
assign rs_match_array[j] = (ls_station[j][29:24] == p_rd_compl) && lss_valid[j] && RegDest_compl;
assign rt_match_array[j] = (ls_station[j][22:17] == p_rd_compl) && lss_valid[j] && RegDest_compl;
end
endgenerate
\t\t\t\t\t\t
////////////////////////////////seqnential logic///////////////////////////////////
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin : sequential
always @(posedge clk or negedge rst) begin
if (!rst) begin
ls_station[i] <= {42{1'b0}};
lss_valid[i] <= 1'b0;
end
else begin
if (write && tail[i]) begin //this is ok, because if a entry is tail, valid[i] is 0, head[i] is 0
ls_station[i] <= {mem_ren, mem_wen, rob_num_dp, p_rd_new, p_rs, v_rs || (!read_rs),
p_rt, v_rt || (!read_rt), immed};
lss_valid[i] <= 1'b1;
end
else begin
if (recover && rob_match_array[i]) begin //flush during recovery
ls_station[i][41:40] <= 2'b00;
end
if (complete && rs_match_array[i]) begin //set rs complete/valid
ls_station[i][23] <= 1'b1;
end
if (complete && rt_match_array[i]) begin
ls_station[i][16] <= 1'b1;
end
if (read && head[i]) begin
lss_valid[i] <= 1'b0;
end
end
end
end
end
endgenerate
//////////////////////////////////////issue logic outputs/////////////////////////////////////
assign head_rdy = ls_station[head_addr][23] && ls_station[head_addr][16];
assign p_rs_out = ls_station[head_addr][29:24];
assign p_rt_out = ls_station[head_addr][22:17];
assign p_rd_out = ls_station[head_addr][35:30];
assign immed_out = ls_station[head_addr][15:0];
assign RegDest_out = ls_station[head_addr][41]; //from isLW (mem_ren)
assign mem_ren_out = ls_station[head_addr][41]; //from isLW (mem_ren)
assign mem_wen_out = ls_station[head_addr][40]; //from isSW (mem_wen)
assign rob_num_out = ls_station[head_addr][39:36];
assign issue = read;
endmodule
|
//when there is a mis-prediction or jump, need to restore the PRs allocated for younger instructions
//will consider this later
module free_list_new(
input [5:0] PR_old, //the previous physical register that needs to be freed when current instruction retires
input RegDest_retire,
input retire_reg, //from retire stage, if there is instruction retire at this cycle, assert retire_reg
input RegDest, //from D stage, to see if current instruction need to get a new physical register
input clk, rst,
input hazard_stall, //stall for any events such as ROB full, RS full, etc.
input recover,
input [5:0] PR_new_flush, //from ROB, when doing branch recovery
input RegDest_ROB, //during roll back, if the instr being flushed has RegDest_ROB = 0, don't add it to free list
output [5:0] PR_new, //the assigned register for current instruction in D stage
output empty //indicate whether free list is empty.
);
reg [5:0] mem [0:63];
reg [5:0] head, tail; //read from head, write to tail + 1
wire write, read;
assign write = (retire_reg || recover) && ~hazard_stall; //just to make it more readable
assign read = RegDest && ~recover && ~empty && ~hazard_stall; //no need to detect full since the FIFO have 64 entries, will never be full
reg [5:0] counter;
//counter recording full or empty status
always @(posedge clk or negedge rst) begin
if (!rst)
counter <= 6'h20; //at rst, AR 0-31 mapped to PR 0-31, PR 32-63 are in free list
else if (write && read)
counter <= counter;
else if (write)
counter <= counter + 1;
else if (read)
counter <= counter - 1;
end
//increase head when read, increase tail when write
always @(posedge clk or negedge rst) begin
if (!rst) begin
head <= 6'h00; //at rst, AR 0-31 mapped to PR 0-31, PR 32-63 are in free list
tail <= 6'h20; //next write will write to mem[tail]
end
else begin
if ((write && recover && RegDest_ROB) || (write && !recover && RegDest_retire))
tail <= tail + 1;
if (read)
head <= head + 1;
end
end
//initialization of free list and write to free list in retire stage
integer i;
always @(posedge clk or negedge rst) begin
if (!rst) begin
for (i = 0; i < 32; i = i + 1) begin
mem[i] <= i + 32;
end
for (i = 32; i < 63; i = i + 1) begin
mem[i] <= 0;
end
end
else if (write && recover && RegDest_ROB)
mem[tail] <= PR_new_flush;
else if (write && !recover && RegDest_retire)
mem[tail] <= PR_old;
end
assign PR_new = mem[head];
assign empty = ~(|counter); //when counter counts to 0, the list is empty
endmodule
|
//Data memory model
//Has one read and one write port
//Reads and writes are carried out on posedge clk
module data_mem(clk, en, we, wdata, addr, rdata);
\tinput clk;
\tinput en;
\tinput we;
\tinput [13:0] addr;
\tinput [31:0] wdata;
\t
\toutput reg [31:0] rdata;
\treg [31:0] mem [0:16383];
\talways@(posedge clk) begin
\t\tif(en)
\t\t\trdata <= mem[addr];
\t\telse
\t\t\trdata <= 32\'hxxxxxxxx;
\tend
\talways@(posedge clk) begin
\t\tif(we)
\t\t\tmem[addr] <= wdata;
\tend
\t//initial begin
\t\t//$readmemh("../FastFiveSim/BranchData", mem);
\t//end
endmodule
|
module rob_tb();
reg rst;
reg clk;
reg isDispatch, MemOp, RegDest;
reg [5:0] PR_old_DP, PR_new_DP;
reg [4:0] rd_DP;
reg complete;
reg [3:0] rob_number;
reg [31:0] jb_addr;
reg changeFlow;
reg hazard_stall;
wire rob_num_dp;
//retire stage,
wire [5:0] PR_old_RT;
wire RegDest_retire;
wire retire_reg;
//to LSQ
wire retire_LWST;
wire [3:0] retire_rob;
wire full;
wire empty;
//roll back
wire RegDest_out;
wire [5:0] PR_old_flush;
wire [5:0] PR_new_flush;
wire [4:0] rd_flush;
wire [3:0] out_rob_num;
wire changeFlow_out; //jump or branch misprediction
wire [31:0] changeFlow_addr; //jump or branch misprediction
wire recover;
reorder_buffer i_reorder_buffer(
.rst(rst),
.clk(clk),
.isDispatch(isDispatch),
.isSW(MemOp),
.RegDest(RegDest),
.PR_old_DP(PR_old_DP),
.PR_new_DP(PR_new_DP),
.rd_DP(rd_DP),
.complete(complete),
.rob_number(rob_number),
.jb_addr(jb_addr),
.changeFlow(changeFlow),
.hazard_stall(hazard_stall),
.rob_num_dp(rob_num_dp),
.PR_old_RT(PR_old_RT),
.RegDest_retire(RegDest_retire),
.retire_reg(retire_reg),
.retire_ST(retire_LWST),
.retire_rob(retire_rob),
.full(full),
.empty(empty),
.RegDest_out(RegDest_out),
.PR_old_flush(PR_old_flush),
.PR_new_flush(PR_new_flush),
.rd_flush(rd_flush),
.out_rob_num(out_rob_num),
.changeFlow_out(changeFlow_out),
.changeFlow_addr(changeFlow_addr),
.recover(recover));
initial begin
clk = 0;
rst = 0;
hazard_stall = 0;
#2 rst = 1;
set_dispatch(0, 0, 0, 6'h00, 6'h00, 6'h00); //set isDispatch to 0
set_complete(0, 4'h0, 32'h00000000, 0); //set complete to 0
@(posedge clk);
set_dispatch(1, 0, 1, 6'h01, 6'h21, 6'h01); //start dispatch
set_complete(0, 4'h0, 32'h00000000, 0); //set complete to 0
@(posedge clk);
set_dispatch(1, 0, 1, 6'h02, 6'h22, 6'h02); //dispatch
set_complete(0, 4'h0, 32'h00000000, 0); //set complete to 0
@(posedge clk);
set_dispatch(1, 0, 1, 6'h03, 6'h23, 6'h03); //dispatch
set_complete(1, 4'h1, 32'h00000000, 0); //the instruction in ROB #1 completes
@(posedge clk);
set_dispatch(1, 0, 1, 6'h04, 6'h24, 6'h04); //dispatch
set_complete(1, 4'h0, 32'h00000000, 0); //the instruction in ROB #0 completes
@(posedge clk);
set_dispatch(1, 0, 1, 6'h05, 6'h25, 6'h05); //dispatch
set_complete(1, 4'h2, 32'h00000000, 0); //the instruction in ROB #2 completes
@(posedge clk);
set_dispatch(0, 0, 0, 6'h01, 6'h21, 6'h01); //set isDispatch to 0
set_complete(0, 4'h0, 32'h00000000, 0); //set complete to 0
@(posedge clk);
set_dispatch(1, 0, 0, 6'h06, 6'h26, 6'h06); //dispatch
set_complete(0, 4'h0, 32'h00000000, 0); //set complete to 0
@(posedge clk);
hazard_stall = 1;
repeat (3) @(posedge clk);
hazard_stall = 0;
set_dispatch(1, 0, 1, 6'h07, 6'h27, 6'h07); //dispatch
set_complete(1, 4'h3, 32'h00000010, 1); //the instruction in ROB #3 completes, a jump instruction
@(posedge clk);
set_dispatch(0, 0, 1, 6'h08, 6'h28, 6'h08);
set_complete(1, 4'h4, 32'h00000000, 0);
repeat (4) @(posedge clk); //waiting for roll back
$stop;
end
always
#5 clk = ~clk;
task set_dispatch(input isDis, input Mop, input regD, input [5:0] pr_old_dp, input [5:0] pr_new_dp,
input [4:0] rd_dp);
begin
isDispatch = isDis; MemOp = Mop; RegDest = regD; PR_old_DP = pr_old_dp; PR_new_DP = pr_new_dp;
rd_DP = rd_dp;
end
endtask
task set_complete(input compl, input [3:0] ROB_num, input [31:0] jb_add, input changeflow);
begin
complete = compl; rob_number = ROB_num; jb_addr = jb_add; changeFlow = changeflow;
end
endtask
endmodule
|
module in_order_cpu(\r
input clk, rst,\r
input switch_program,\r
input [31:0] SPART_pc,\r
output spart_wrt_en,\r
output [31:0] spart_wrt_add,\r
output [31:0] spart_wrt_data\r
);\r
\r
wire changeFlow; //from EX stage, when branch or jump or branch mis_prediction\r
wire [31:0] jb_addr; //from EX stage, provide address for jump or branch\r
wire [31:0] instr_IF; //instruction coming from I-mem\r
wire [31:0] pc_1_IF; //pc+1 from IF stage\r
\r
wire flush_ID, flush_EX, stall_PC_ID;\r
wire taken, not_taken; //from EX stage, change the state of predictor\r
wire pred_taken;\r
wire halt;\r
\r
IF_stage i_IF_stage(.instr(instr_IF), .pc_1(pc_1_IF), .jb_addr(jb_addr), .changeFlow(changeFlow), \r
.clk(clk), .rst(rst), .stall_PC(stall_PC_ID), .taken(taken), .not_taken(not_taken),\r
.pred_taken(pred_taken), .switch_program(switch_program), .SPART_pc(SPART_pc), \r
.halt(halt));\r
\r
reg [31:0] instr_IF_ID; //the IF_ID pipe reg for instr\r
reg [31:0] pc_1_IF_ID; //the IF_ID pipe reg for pc_1\r
reg pred_taken_IF_ID;\r
//IF/ID pipeline register\r
always @(posedge clk or negedge rst) begin\r
if (!rst)\r
{instr_IF_ID, pc_1_IF_ID, pred_taken_IF_ID} <= 0;\r
else if (flush_ID || (halt && !switch_program && !stall_PC_ID)) \r
{instr_IF_ID, pc_1_IF_ID, pred_taken_IF_ID} <= 0; \r
else if (!stall_PC_ID)\r
{instr_IF_ID, pc_1_IF_ID, pred_taken_IF_ID} <= {instr_IF, pc_1_IF, pred_taken};\r
end\r
\r
//register data\r
wire [31:0] rs_data, rt_data;\r
//signals from WB\r
wire [31:0] wdata_WB;\r
wire [4:0] waddr_WB;\r
reg reg_wen_WB;\r
\r
//control signals\r
//control signals for EX stage\r
wire writeRd, ldic, isSignEx, immed;\r
wire alu_ctrl0, alu_ctrl1, alu_ctrl2, alu_ctrl3;\r
wire isJump, isJR;\r
wire rs_read, rt_read;\r
//control signals for MEM stage\r
wire mem_ren, mem_wen;\r
//contorl signals for WB stage\r
wire lw, link, reg_wen;\r
//special control signals\r
wire str_ccnt, str_icnt, stp_cnt;\r
wire inc_instr;\r
\r
//ID_stage\r
ID_stage i_ID_stage(\r
.instr(instr_IF_ID),\r
.clk(clk),\r
\t\t .rst(rst),\r
.wdata(wdata_WB),\r
.waddr(waddr_WB),\r
.reg_wen_WB(reg_wen_WB),\r
.rs_data(rs_data),\r
.rt_data(rt_data),\r
.rs_read(rs_read),\r
.rt_read(rt_read),\r
.writeRd(writeRd),\r
.ldic(ldic),\r
.isSignEx(isSignEx),\r
.immed(immed),\r
.alu_ctrl0(alu_ctrl0),\r
.alu_ctrl1(alu_ctrl1),\r
.alu_ctrl2(alu_ctrl2),\r
.alu_ctrl3(alu_ctrl3),\r
.isJump(isJump),\r
.isJR(isJR),\r
.mem_ren(mem_ren),\r
.mem_wen(mem_wen),\r
.lw(lw),\r
.link(link),\r
.reg_wen(reg_wen),\r
.str_ccnt(str_ccnt),\r
.str_icnt(str_icnt),\r
.stp_cnt(stp_cnt),\r
.inc_instr(inc_instr));\r
\r
//from IF/ID pipeline\r
reg [31:0] instr_ID_EX; //the IF_ID pipe reg for instr\r
reg [31:0] pc_1_ID_EX; //the IF_ID pipe reg for pc_1\r
//control signals for EX stage\r
reg writeRd_ID_EX, ldic_ID_EX, isSignEx_ID_EX, immed_ID_EX;\r
reg alu_ctrl0_ID_EX, alu_ctrl1_ID_EX, alu_ctrl2_ID_EX, alu_ctrl3_ID_EX;\r
reg isJump_ID_EX, isJR_ID_EX;\r
//control signals for MEM stage\r
reg mem_ren_ID_EX, mem_wen_ID_EX;\r
//contorl signals for WB stage\r
reg lw_ID_EX, link_ID_EX, reg_wen_ID_EX;\r
reg str_icnt_ID_EX, stp_cnt_ID_EX; //counter control signal\r
reg inc_instr_ID_EX;\r
reg pred_taken_ID_EX;\r
\r
reg [31:0] rs_data_ID_EX, rt_data_ID_EX;\r
//ID/EX pipeline for register data\r
always @(posedge clk or negedge rst) begin\r
if (!rst) begin\r
{rs_data_ID_EX, rt_data_ID_EX} <= 0;\r
end\r
else begin\r
{rs_data_ID_EX, rt_data_ID_EX} <= {rs_data, rt_data};\r
end\r
end\r
\r
//ID/EX pipeline for control signals\r
always @(posedge clk or negedge rst) begin\r
if (!rst) begin\r
{writeRd_ID_EX, ldic_ID_EX, isSignEx_ID_EX, immed_ID_EX} <= 0;\r
{alu_ctrl0_ID_EX, alu_ctrl1_ID_EX, alu_ctrl2_ID_EX, alu_ctrl3_ID_EX} <= 0;\r
{isJump_ID_EX, isJR_ID_EX} <= 0;\r
{mem_ren_ID_EX, mem_wen_ID_EX} <= 0;\r
{lw_ID_EX, link_ID_EX, reg_wen_ID_EX} <= 0;\r
{instr_ID_EX, pc_1_ID_EX} <= 0;\r
{str_icnt_ID_EX, stp_cnt_ID_EX, inc_instr_ID_EX} <= 0;\r
pred_taken_ID_EX <= 0;\r
end\r
else if (flush_EX) begin\r
{writeRd_ID_EX, ldic_ID_EX, isSignEx_ID_EX, immed_ID_EX} <= 0;\r
{alu_ctrl0_ID_EX, alu_ctrl1_ID_EX, alu_ctrl2_ID_EX, alu_ctrl3_ID_EX} <= 0;\r
{isJump_ID_EX, isJR_ID_EX} <= 0;\r
{mem_ren_ID_EX, mem_wen_ID_EX} <= 0;\r
{lw_ID_EX, link_ID_EX, reg_wen_ID_EX} <= 0;\r
{instr_ID_EX, pc_1_ID_EX} <= 0;\r
{str_icnt_ID_EX, stp_cnt_ID_EX, inc_instr_ID_EX} <= 0;\r
pred_taken_ID_EX <= 0;\r
end\r
else begin\r
{writeRd_ID_EX, ldic_ID_EX, isSignEx_ID_EX, immed_ID_EX} <= {writeRd, ldic, isSignEx, immed};\r
{alu_ctrl0_ID_EX, alu_ctrl1_ID_EX, alu_ctrl2_ID_EX, alu_ctrl3_ID_EX} <= {alu_ctrl0, alu_ctrl1, alu_ctrl2, alu_ctrl3};\r
{isJump_ID_EX, isJR_ID_EX} <= {isJump, isJR};\r
{mem_ren_ID_EX, mem_wen_ID_EX} <= {mem_ren, mem_wen};\r
{lw_ID_EX, link_ID_EX, reg_wen_ID_EX} <= {lw, link, reg_wen};\r
{instr_ID_EX, pc_1_ID_EX} <= {instr_IF_ID, pc_1_IF_ID};\r
{str_icnt_ID_EX, stp_cnt_ID_EX, inc_instr_ID_EX} <= {str_icnt, stp_cnt, inc_instr};\r
pred_taken_ID_EX <= pred_taken_IF_ID;\r
end\r
end\r
\r
//EX stage outputs\r
wire [31:0] alu_result;\r
wire [31:0] mem_addr;\r
wire [4:0] dst_reg;\r
wire [15:0] instr_cnt, cycle_cnt;\r
//EX_stage\r
EX_stage i_EX_stage(\r
.rs_data(rs_data_ID_EX),\r
.rt_data(rt_data_ID_EX),\r
.instr(instr_ID_EX),\r
.instr_cnt(instr_cnt),\r
.cycle_cnt(cycle_cnt),\r
.pc_1(pc_1_ID_EX),\r
.writeRd(writeRd_ID_EX),\r
.ldic(ldic_ID_EX),\r
.isSignEx(isSignEx_ID_EX),\r
.immed(immed_ID_EX),\r
.alu_ctrl0(alu_ctrl0_ID_EX),\r
.alu_ctrl1(alu_ctrl1_ID_EX),\r
.alu_ctrl2(alu_ctrl2_ID_EX),\r
.alu_ctrl3(alu_ctrl3_ID_EX),\r
.isJump(isJump_ID_EX),\r
.isJR(isJR_ID_EX),\r
.pred_taken(pred_taken_ID_EX),\r
.alu_result(alu_result),\r
.mem_addr(mem_addr),\r
.jb_addr(jb_addr),\r
.dst_reg(dst_reg),\r
.changeFlow(changeFlow),\r
.taken(taken),\r
.not_taken(not_taken));\r
\r
reg [31:0] store_data;\r
reg [31:0] pc_1_EX_MEM; \r
reg [31:0] alu_result_EX_MEM;\r
reg [31:0] mem_addr_EX_MEM;\r
reg [4:0] dst_reg_EX_MEM;\r
//control signals for MEM stage\r
reg mem_ren_EX_MEM, mem_wen_EX_MEM;\r
//contorl signals for WB stage\r
reg lw_EX_MEM, link_EX_MEM, reg_wen_EX_MEM; \r
reg str_icnt_EX_MEM, stp_cnt_EX_MEM;\r
reg inc_instr_EX_MEM;\r
\r
//EX_MEM pipeline\r
always @(posedge clk or negedge rst) begin\r
if (!rst) begin \r
{store_data, pc_1_EX_MEM, alu_result_EX_MEM, mem_addr_EX_MEM, dst_reg_EX_MEM} <= 0; //data\r
{mem_ren_EX_MEM, mem_wen_EX_MEM} <= 0; //control for MEM stage\r
{lw_EX_MEM, link_EX_MEM, reg_wen_EX_MEM} <= 0; //control for WB stage\r
{str_icnt_EX_MEM, stp_cnt_EX_MEM, inc_instr_EX_MEM} <= 0;\r
end\r
else begin\r
{store_data, pc_1_EX_MEM, alu_result_EX_MEM} <= {rt_data_ID_EX, pc_1_ID_EX, alu_result}; //data\r
{mem_addr_EX_MEM, dst_reg_EX_MEM} <= {mem_addr, dst_reg}; //data\r
{mem_ren_EX_MEM, mem_wen_EX_MEM} <= {mem_ren_ID_EX, mem_wen_ID_EX}; //control for MEM stage\r
{lw_EX_MEM, link_EX_MEM, reg_wen_EX_MEM} <= {lw_ID_EX, link_ID_EX, reg_wen_ID_EX}; //control for WB stage\r
{str_icnt_EX_MEM, stp_cnt_EX_MEM, inc_instr_EX_MEM} <= {str_icnt_ID_EX, stp_cnt_ID_EX, inc_instr_ID_EX};\r
end\r
end\r
\r
//stall and hazard detection control\r
hazard_detect i_hazard_detect(\r
.changeFlow(changeFlow),\r
.ID_rs(instr_IF_ID[25:21]),\r
.ID_rt(instr_IF_ID[20:16]),\r
.rs_read(rs_read),\r
.rt_read(rt_read),\r
.EX_dst_reg(dst_reg),\r
.MEM_dst_reg(dst_reg_EX_MEM),\r
.EX_reg_wen(reg_wen_ID_EX),\r
.MEM_reg_wen(reg_wen_EX_MEM),\r
.flush_ID(flush_ID),\r
.flush_EX(flush_EX),\r
.stall_PC_ID(stall_PC_ID));\r
wire [31:0] mem_rdata_MEM_WB;\r
//MEM stage\r
MEM_stage i_MEM_stage(\r
.clk(clk),\r
.mem_addr(mem_addr_EX_MEM),\r
.mem_wdata(store_data),\r
.mem_ren(mem_ren_EX_MEM),\r
.mem_wen(mem_wen_EX_MEM),\r
.mem_rdata(mem_rdata_MEM_WB));\r
\r
assign spart_wrt_en = mem_wen_EX_MEM;\r
assign spart_wrt_add = mem_addr_EX_MEM;\r
assign spart_wrt_data = store_data;\r
\r
reg [31:0] pc_1_MEM_WB;\r
reg [31:0] alu_result_MEM_WB;\r
reg [4:0] dst_reg_MEM_WB;\r
reg lw_MEM_WB, link_MEM_WB; //reg_wen_WB is defined in ID stage\r
reg str_icnt_MEM_WB, stp_cnt_MEM_WB;\r
reg inc_instr_MEM_WB;\r
\r
//MEM_WB pipeline\r
always @(posedge clk or negedge rst) begin\r
if (!rst) begin\r
{pc_1_MEM_WB, alu_result_MEM_WB, dst_reg_MEM_WB} <= 0;\r
{lw_MEM_WB, link_MEM_WB, reg_wen_WB} <= 0;\r
{str_icnt_MEM_WB, stp_cnt_MEM_WB} <= 0;\r
end\r
else begin\r
{pc_1_MEM_WB, alu_result_MEM_WB, dst_reg_MEM_WB} <= {pc_1_EX_MEM, alu_result_EX_MEM, dst_reg_EX_MEM};\r
{lw_MEM_WB, link_MEM_WB, reg_wen_WB} <= {lw_EX_MEM, link_EX_MEM, reg_wen_EX_MEM};\r
{str_icnt_MEM_WB, stp_cnt_MEM_WB, inc_instr_MEM_WB} <= {str_icnt_EX_MEM, stp_cnt_EX_MEM, inc_instr_EX_MEM};\r
end\r
end\r
\r
WB_stage i_WB_stage(\r
.pc_1(pc_1_MEM_WB),\r
.alu_result(alu_result_MEM_WB),\r
.mem_rdata(mem_rdata_MEM_WB),\r
.dst_reg(dst_reg_MEM_WB),\r
.lw(lw_MEM_WB),\r
.link(link_MEM_WB),\r
.wb_data(wdata_WB),\r
.wb_addr(waddr_WB));\r
\r
//perf_cnt i_perf_cnt(.str_ccnt(str_ccnt), .str_icnt(str_icnt_MEM_WB), .stp_cnt(stp_cnt_MEM_WB), .clk(clk), .rst(rst), .inc_instr(inc_instr_MEM_WB),\r
// .instr_cnt(instr_cnt), .cycle_cnt(cycle_cnt));\r
endmodule\r
|
//Instruction memory model
//Initializes from file
//Read only
//Reads on posedge clk
module inst_mem(clk, addr, dout);
\tinput clk;
\tinput [9:0] addr;
\toutput reg [31:0] dout;
\treg [31:0] mem [1023:0];
\t
\tinitial begin
\t\t$readmemh("test_alu02.txt", mem);
\tend
\t
\talways@(posedge clk) begin
\t\tdout <= mem[addr];
\tend
endmodule
|
module abiter (
\tinput rst,
\tinput clk,
\tinput is_alu,
\tinput is_ls,
\toutput sel_result,
\toutput stall_alu,
\toutput stall_ls
);
\treg int_reg;
\tassign sel_result = (is_alu && is_ls)? int_reg : (is_ls? 1'b1 : 0);
\tassign stall_alu = is_alu && is_ls && int_reg;
\tassign stall_ls = is_alu && is_ls && ~int_reg;
\talways @(posedge clk)
\tif (!rst)
\t\tint_reg <= 0;
\telse
\t\tif (is_alu && is_ls)
\t\t\tint_reg <= ~int_reg;
\t
endmodule
|
`timescale 1ns / 1ps\r
//////////////////////////////////////////////////////////////////////////////////\r
// Company: \r
// Engineer: \r
// \r
// Create Date: 14:35:11 11/08/2015 \r
// Design Name: \r
// Module Name: prf_tb \r
// Project Name: \r
// Target Devices: \r
// Tool versions: \r
// Description: \r
//\r
// Dependencies: \r
//\r
// Revision: \r
// Revision 0.01 - File Created\r
// Additional Comments: \r
//\r
//////////////////////////////////////////////////////////////////////////////////\r
module prf_tb( );\r
\r
reg clk, rst, RegDest_compl, tbclk2x;\t\t//clk, rst, write enable, testbench 2x clk\r
reg [5:0] p_rs, p_rt, p_rd;\t\t//reg addresses\r
reg [31:0] wr_data_in;\r
wire [31:0] rd_data_rs, rd_data_rt;\r
\r
phy_reg_file prf(
clk,
rst,\t
\t//Read interface
p_rs, //Read Address 1
p_rt, //Read Address 2
rd_data_rs, //Read Data out1
rd_data_rt, //Read Data out2
\t//Write interface
p_rd,\t\t\t //From CDB.Tag (complete stage)
wr_data_in, //From CDB.Value (complete stage)
RegDest_compl //RegDest from complete stage, it is 1 if this instruction writes register
);\r
\r
always #5 clk = ~clk;\r
//always #2.5 tbclk2x = ~tbclk2x;\r
\r
initial begin\r
clk = 0;\r
rst = 1;\r
RegDest_compl = 0;\r
p_rs = 6'b0;\r
p_rt = 6'b0;\r
p_rd = 6'b0;\r
wr_data_in = 32'h0;\r
\r
@(posedge clk);\r
repeat (2) @(posedge clk);\t\t\t\t\t\t//rst needs to be asserted for 3 cycles\r
@(negedge clk) rst = 0;\r
repeat (10) @(posedge clk); \t\t\t\t\t//wait 10 clk cycles before clk2x is valid\r
p_rs = 6'h1;\r
@(posedge clk)\r
\twr_data_in = 32'hDEADBEEF;\r
\tRegDest_compl = 1'b1;\r
\tp_rs = 6'h0;\r
@(posedge clk) //RegDest_compl = 1'b0;\r
p_rt = 6'h2;\r
p_rd = 6'h4;\r
p_rs = 6'h4;\r
wr_data_in = 32'habababab;\r
@(posedge clk) RegDest_compl = 1'b0;\r
\r
//repeat (3) @(posedge clk);\r
//p_rt = 6'h0;\r
\r
\r
end\r
\r
\r
endmodule\r
\r
|
//dispatch: read p_rs, p_rt, write new p_rd and reset this valid bit, read p_old, use p_rs, p_rt, p_rd_old to index valid array getting valid bit
//complete: set valid bit of the completed physical register number
//recovery: inedxed by recover_rd, if RegDest_ROB = 1, write the p_rd_flush to that entry, and restore the valid bit
module map_table(
output [5:0] p_rs, p_rt,
output p_rs_v, p_rt_v,
output [5:0] PR_old_rd,
input clk, rst,
input hazard_stall, //from hazard detection logic
//from dispatch stage
input isDispatch,
input [4:0] l_rs, l_rt, l_rd,
input RegDest,
input [5:0] p_rd_new,
//from recovery
input [4:0] recover_rd,
input [5:0] p_rd_flush,
input recover,
input RegDest_ROB,
//from complete stage
input [5:0] p_rd_compl,
input complete,
input RegDest_compl
);
reg [5:0] mt [0:31];
reg [63:0] PR_valid; //logically separate with map table
/////////////////////////////////writing/reading map table////////////////////////////
wire write_new_rd;
integer i;
assign write_new_rd = isDispatch && RegDest && !hazard_stall && !recover;
always @(posedge clk or negedge rst) begin
if (!rst) begin //initial begin
for (i = 0; i < 32; i = i + 1) begin
mt[i] <= i;
end
end
else if (write_new_rd)
mt[l_rd] <= p_rd_new;
else if (RegDest_ROB && recover)
mt[recover_rd] <= p_rd_flush;
end
assign p_rs = mt[l_rs];
assign p_rt = mt[l_rt];
assign PR_old_rd = mt[l_rd];
/////////////////////////////valid array/////////////////////////////////
always @(posedge clk or negedge rst) begin
if (!rst) begin
PR_valid <= 64'hFFFFFFFFFFFFFFFF;
end
else begin
if (write_new_rd)
PR_valid[p_rd_new] <= 1'b0;
if (complete && RegDest_compl) //it should be ok during recovery because if complete is 1, the valid will be set to 1 several times, finally it will
PR_valid[p_rd_compl] <= 1'b1; //be 1
end
end
assign p_rs_v = PR_valid[p_rs];
assign p_rt_v = PR_valid[p_rt];
endmodule
|
/*******************************************************************************\r
* This file is owned and controlled by Xilinx and must be used solely *\r
* for design, simulation, implementation and creation of design files *\r
* limited to Xilinx devices or technologies. Use with non-Xilinx *\r
* devices or technologies is expressly prohibited and immediately *\r
* terminates your license. *\r
* *\r
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *\r
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *\r
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *\r
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *\r
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *\r
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *\r
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *\r
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *\r
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *\r
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *\r
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *\r
* PARTICULAR PURPOSE. *\r
* *\r
* Xilinx products are not intended for use in life support appliances, *\r
* devices, or systems. Use in such applications are expressly *\r
* prohibited. *\r
* *\r
* (c) Copyright 1995-2015 Xilinx, Inc. *\r
* All rights reserved. *\r
*******************************************************************************/\r
// You must compile the wrapper file blockram.v when simulating\r
// the core, blockram. When compiling the wrapper file, be sure to\r
// reference the XilinxCoreLib Verilog simulation library. For detailed\r
// instructions, please refer to the "CORE Generator Help".\r
\r
// The synthesis directives "translate_off/translate_on" specified below are\r
// supported by Xilinx, Mentor Graphics and Synplicity synthesis\r
// tools. Ensure they are correct for your synthesis tool(s).\r
\r
`timescale 1ns/1ps\r
\r
module blockram(\r
clka,\r
wea,\r
addra,\r
dina,\r
douta,\r
clkb,\r
web,\r
addrb,\r
dinb,\r
doutb\r
);\r
\r
input clka;\r
input [0 : 0] wea;\r
input [5 : 0] addra;\r
input [31 : 0] dina;\r
output [31 : 0] douta;\r
input clkb;\r
input [0 : 0] web;\r
input [5 : 0] addrb;\r
input [31 : 0] dinb;\r
output [31 : 0] doutb;\r
\r
// synthesis translate_off\r
\r
BLK_MEM_GEN_V7_3 #(\r
.C_ADDRA_WIDTH(6),\r
.C_ADDRB_WIDTH(6),\r
.C_ALGORITHM(1),\r
.C_AXI_ID_WIDTH(4),\r
.C_AXI_SLAVE_TYPE(0),\r
.C_AXI_TYPE(1),\r
.C_BYTE_SIZE(9),\r
.C_COMMON_CLK(1),\r
.C_DEFAULT_DATA("0"),\r
.C_DISABLE_WARN_BHV_COLL(0),\r
.C_DISABLE_WARN_BHV_RANGE(0),\r
.C_ENABLE_32BIT_ADDRESS(0),\r
.C_FAMILY("virtex5"),\r
.C_HAS_AXI_ID(0),\r
.C_HAS_ENA(0),\r
.C_HAS_ENB(0),\r
.C_HAS_INJECTERR(0),\r
.C_HAS_MEM_OUTPUT_REGS_A(0),\r
.C_HAS_MEM_OUTPUT_REGS_B(0),\r
.C_HAS_MUX_OUTPUT_REGS_A(0),\r
.C_HAS_MUX_OUTPUT_REGS_B(0),\r
.C_HAS_REGCEA(0),\r
.C_HAS_REGCEB(0),\r
.C_HAS_RSTA(0),\r
.C_HAS_RSTB(0),\r
.C_HAS_SOFTECC_INPUT_REGS_A(0),\r
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),\r
.C_INIT_FILE("BlankString"),\r
.C_INIT_FILE_NAME("no_coe_file_loaded"),\r
.C_INITA_VAL("0"),\r
.C_INITB_VAL("0"),\r
.C_INTERFACE_TYPE(0),\r
.C_LOAD_INIT_FILE(0),\r
.C_MEM_TYPE(2),\r
.C_MUX_PIPELINE_STAGES(0),\r
.C_PRIM_TYPE(1),\r
.C_READ_DEPTH_A(64),\r
.C_READ_DEPTH_B(64),\r
.C_READ_WIDTH_A(32),\r
.C_READ_WIDTH_B(32),\r
.C_RST_PRIORITY_A("CE"),\r
.C_RST_PRIORITY_B("CE"),\r
.C_RST_TYPE("SYNC"),\r
.C_RSTRAM_A(0),\r
.C_RSTRAM_B(0),\r
.C_SIM_COLLISION_CHECK("ALL"),\r
.C_USE_BRAM_BLOCK(0),\r
.C_USE_BYTE_WEA(0),\r
.C_USE_BYTE_WEB(0),\r
.C_USE_DEFAULT_DATA(0),\r
.C_USE_ECC(0),\r
.C_USE_SOFTECC(0),\r
.C_WEA_WIDTH(1),\r
.C_WEB_WIDTH(1),\r
.C_WRITE_DEPTH_A(64),\r
.C_WRITE_DEPTH_B(64),\r
.C_WRITE_MODE_A("WRITE_FIRST"),\r
.C_WRITE_MODE_B("WRITE_FIRST"),\r
.C_WRITE_WIDTH_A(32),\r
.C_WRITE_WIDTH_B(32),\r
.C_XDEVICEFAMILY("virtex5")\r
)\r
inst (\r
.CLKA(clka),\r
.WEA(wea),\r
.ADDRA(addra),\r
.DINA(dina),\r
.DOUTA(douta),\r
.CLKB(clkb),\r
.WEB(web),\r
.ADDRB(addrb),\r
.DINB(dinb),\r
.DOUTB(doutb),\r
.RSTA(),\r
.ENA(),\r
.REGCEA(),\r
.RSTB(),\r
.ENB(),\r
.REGCEB(),\r
.INJECTSBITERR(),\r
.INJECTDBITERR(),\r
.SBITERR(),\r
.DBITERR(),\r
.RDADDRECC(),\r
.S_ACLK(),\r
.S_ARESETN(),\r
.S_AXI_AWID(),\r
.S_AXI_AWADDR(),\r
.S_AXI_AWLEN(),\r
.S_AXI_AWSIZE(),\r
.S_AXI_AWBURST(),\r
.S_AXI_AWVALID(),\r
.S_AXI_AWREADY(),\r
.S_AXI_WDATA(),\r
.S_AXI_WSTRB(),\r
.S_AXI_WLAST(),\r
.S_AXI_WVALID(),\r
.S_AXI_WREADY(),\r
.S_AXI_BID(),\r
.S_AXI_BRESP(),\r
.S_AXI_BVALID(),\r
.S_AXI_BREADY(),\r
.S_AXI_ARID(),\r
.S_AXI_ARADDR(),\r
.S_AXI_ARLEN(),\r
.S_AXI_ARSIZE(),\r
.S_AXI_ARBURST(),\r
.S_AXI_ARVALID(),\r
.S_AXI_ARREADY(),\r
.S_AXI_RID(),\r
.S_AXI_RDATA(),\r
.S_AXI_RRESP(),\r
.S_AXI_RLAST(),\r
.S_AXI_RVALID(),\r
.S_AXI_RREADY(),\r
.S_AXI_INJECTSBITERR(),\r
.S_AXI_INJECTDBITERR(),\r
.S_AXI_SBITERR(),\r
.S_AXI_DBITERR(),\r
.S_AXI_RDADDRECC()\r
);\r
\r
// synthesis translate_on\r
\r
endmodule\r
|
//re-order buffer did three things
//In dispatch, unless ROB is full, allocate new ROB entry for incoming instruction at tail, increase the tail
//during the recovery time (when dec_tail|recover is 1), the ROB will not allocate new entry for instructions in dispatch stage
//In complete, if the completed instruction is not a branch. The ROB entry indexed by rob_number will be marked as complete.
//if it is a branch misprediction or jump, stall all things (flush IF/DP) in the first cycle (when stall_recover is high),
//decrease the tail by 1 (since the tail points to next allocated instr, cannot recover from tail entry). Then,
//assert the recover signal, all data(PR_old, PR_new, rd) are ready, during the time recover is high, flush RS entry (ROB# match),
//flush MT, FL, LSQ (all for ROB# match), flush IS/EX(if ROB# match), EX/CMP(ROB# match). If ROB# doesn't match, stall that block.
//after recover becomes low, the changeFlow_out becomes 1 for 1 cycle, thus PC changes to correct PC, changeFlow also flush the IF/DP
//when recover is low, other parts are allowed to go (MT,RS,FL will not allocate since the IF/DP is NOP, however some instructions
//might still in IS/EX or EX/CMP, let them go
module reorder_buffer_beh(
input rst, clk,
input isDispatch, //serve as the write enable of FIFO
input isSW, //
input RegDest, //stored for roll back, if it is 1, MT and FL need to be restored
input [5:0] PR_old_DP, //from map table, the previous PR#
input [5:0] PR_new_DP,
input [4:0] rd_DP, //architectural destinatioMn register
input complete, //from complete stage, if there is intruction completes
input [3:0] rob_number, //from the complete stage, used to set complete bit
input [31:0] jb_addr, //from complete stage
input changeFlow, //asserted if branch-misprediction or jump, from complete, start the state machine
input hazard_stall, //stall because of structure hazard, won't allocate new entry
output [3:0] rob_num_dp, //rob number in dispatch stage
output [5:0] PR_old_RT, //PR_old to be retired
output RegDest_retire, //only if the instruction write register, the PR_old is returned to MT and FL
output retire_reg, //read enable signal of FIFO
output retire_ST,
output [3:0] retire_rob, //for load/store queue, indicate which ROB entry is retired
output full, empty,
output RegDest_out,
output [5:0] PR_old_flush,
output [5:0] PR_new_flush,
output [4:0] rd_flush,
output [3:0] out_rob_num, //for recovery, provide the current ROB number for FL, MT, RS
output reg changeFlow_out, //asserted for one cycle after all recovery works done
output reg [31:0] changeFlow_addr,
output reg recover //recover signal, inform RS, MT, FL, LSQ, IS/EX, EX/CMP to flush(ROB# match) or stall (ROB# not match)
);
reg [18:0] rob [0:15]; //[18]: RegDest, (whether bet PR back to MT and FL) [17]: isSW, [16:12]rd, [11:6] pr_old, [5:0] pr_new
reg [15:0] complete_array;
/////////////////////////////////////////////Synch FIFO structure///////////////////////////////////////////
reg [3:0] head, tail;
reg dec_tail; //for recovery
assign rob_num_dp = tail;
wire read, write;
//no read or write of ROB during recovery
assign write = isDispatch && !full && !recover && !hazard_stall;
assign read = retire_reg && !empty && !recover && !hazard_stall;
//head logic
always @(posedge clk or negedge rst) begin
if (!rst) begin
head <= 4'h0;
end
else if (read) begin
head <= head + 1;
end
end
assign retire_reg = complete_array[head]; //if the head is complete, retire it
assign PR_old_RT = rob[head][11:6]; //the PR returned to free list
assign retire_ST = rob[head][17]; //tell SQ now a load/store is retired
assign RegDest_retire = rob[head][18];
assign retire_rob = head;
//tail logic
always @(posedge clk or negedge rst) begin
if (!rst)
tail <= 4'h0;
else if (dec_tail)
tail <= tail - 1; //when decreasing tail, the ROB will not accept new instructions
else if (write) begin
tail <= tail + 1;
rob[tail] <= {RegDest, isSW, rd_DP, PR_old_DP, PR_new_DP};
complete_array[tail] <= 0; //reset complete bit when allocate a new entry
end
end
//Synch FIFO counter
reg [4:0] status_cnt;
always @(posedge clk or negedge rst) begin
if (!rst)
status_cnt <= 4'h0;
else if (write && !read) //write but not read
status_cnt <= status_cnt + 1;
else if (read && !write) //read but not write
status_cnt <= status_cnt - 1;
else if (dec_tail)
status_cnt <= status_cnt - 1;
end
assign full = status_cnt[4]; //if counter = 16, the FIFO is full
assign empty = ~(|status_cnt);
///////////////////////////////////////////////////end of synch FIFO///////////////////////////////////////////////////
//////////////////////////////complete part////////////////////////////////////
reg [3:0] branch_rob;
reg store_jb_addr;
always @(posedge clk or negedge rst) begin
if (!rst)
complete_array <= 0;
else if (complete)
complete_array[rob_number] <= 1'b1; //ROB# cannot equal to tail, will this synthesize?
end
//changeFlow address and ROB number for branch/jump
always @(posedge clk or negedge rst) begin
if (!rst) begin
changeFlow_addr <= 0;
branch_rob <= 0;
end
else if (store_jb_addr) begin
changeFlow_addr <= jb_addr;
branch_rob <= rob_number; //store the ROB# of branch when here comes a branch
end
end
//////////////////////////////end of complete part/////////////////////////////////////
assign out_rob_num = tail; //may need to store ROB number in RS, when completing instructions can index the ROB to set
//during recovery, this number is also used for indexing the flush entry
localparam IDLE = 1'b0;
localparam REC = 1'b1;
reg state, nstate;
always @(posedge clk or negedge rst) begin
if (!rst)
state <= IDLE;
else
state <= nstate;
end
wire recover_end = (branch_rob + 1 == tail);
always @(*) begin
nstate = IDLE;
dec_tail = 0;
recover = 0;
store_jb_addr = 0;
changeFlow_out = 0;
case (state)
IDLE: begin
if(complete && changeFlow) begin
nstate = REC;
dec_tail = 1;
recover = 1;
store_jb_addr = 1;
end
else
nstate = IDLE;
end
default: begin //recover
if(recover_end) begin
nstate = IDLE;
changeFlow_out = 1;
end
else begin
nstate = REC;
dec_tail = 1;
recover = 1;
end
end
endcase
end
//[16:12]rd, [11:6] t_old, [5:0] t_new
assign rd_flush = rob[tail-1][16:12];
assign PR_old_flush = rob[tail-1][11:6];
assign PR_new_flush = rob[tail-1][5:0];
assign RegDest_out = rob[tail-1][18];
//out_rob_tail assigned before, since it is used both in recovery and normal dispatch
endmodule
|
module ALU(
output reg [31:0] alu_out,
output flag_z, flag_v, flag_n,
input [31:0] in0, in1, //in0 is rs, in1 can be rt or sign/unsign-extended immediate value
input [4:0] shamt,
input [15:0] perf_cnt, //input from performance counter
input alu_ctrl0, alu_ctrl1, alu_ctrl2, alu_ctrl3
);
localparam ADD = 4'h0, SUB = 4'h1, LUI = 4'h2, MOV = 4'h3;
localparam AND = 4'h4, SLL = 4'h5, SRA = 4'h6, SRL = 4'h7;
localparam NOT = 4'h8, OR = 4'h9, XOR = 4'ha, ADDB = 4'hb;
localparam ADDBI = 4'hc, SUBB = 4'hd, SUBBI = 4'he, LLDC = 4'hf; //LDC stands for load counters
wire [3:0] alu_ctrl = {alu_ctrl3, alu_ctrl2, alu_ctrl1, alu_ctrl0};
//////wires for shift
wire [31:0] dsll0, dsll1, dsll2, dsll3, dsll4;
wire [31:0] dsrl0, dsrl1, dsrl2, dsrl3, dsrl4;
wire [31:0] dsra0, dsra1, dsra2, dsra3, dsra4;
//////wires for byte-wise arithmetic
wire [8:0] addb0_int, addb1_int, addb2_int, addb3_int;
wire [7:0] addb0, addb1, addb2, addb3;
wire [7:0] subb0, subb1, subb2, subb3;
//////ALU result
always @(alu_ctrl or in0 or in1) begin
case (alu_ctrl)
ADD: alu_out = in0 + in1;
SUB: alu_out = in0 - in1;
LUI: alu_out = {in1[15:0], 16'h0000}; //the concatenation is done before going into ALU
MOV: alu_out = in0;
AND: alu_out = in0 & in1;
SLL: alu_out = dsll4;
SRA: alu_out = dsra4;
SRL: alu_out = dsrl4;
NOT: alu_out = ~in0;
OR: alu_out = in0 | in1;
XOR: alu_out = in0 ^ in1;
ADDB: alu_out = {addb3, addb2, addb1, addb0}; //currently don't care about the correctness of these byte-wise ops
ADDBI: alu_out = {addb3, addb2, addb1, addb0};
SUBB: alu_out = {subb3, subb2, subb1, subb0};
SUBBI: alu_out = {subb3, subb2, subb1, subb0};
LLDC: alu_out = {16'h0000, perf_cnt};
endcase
end
//////flags //////our flag only used in branch instruction, we don't have overflow exception
assign flag_z = ~(|alu_out);
assign flag_n = alu_out[31];
assign flag_v = (in0[31] & in1[31] & ~alu_out[31]) || (~in0[31] & ~in1[31] & alu_out[31]);
///////////////////////////////////////////////////////////////////////////////////////////////
//////////////////log shifter//////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////
//shifter left logically (SLL) block
assign dsll0 = shamt[0] ? {in0[30:0], 1'b0} : in0; //shift left logic/arithmetic
assign dsll1 = shamt[1] ? {dsll0[29:0], 2'b00} : dsll0;
assign dsll2 = shamt[2] ? {dsll1[27:0], 4'h0} : dsll1;
assign dsll3 = shamt[3] ? {dsll2[23:0], 8'h00} : dsll2;
assign dsll4 = shamt[4] ? {dsll3[15:0], 16'h0000} : dsll3;
//SRL block
assign dsrl0 = shamt[0] ? {1'b0, in0[31:1]} : in0; //shift right logically
assign dsrl1 = shamt[1] ? {2'b00, dsrl0[31:2]} : dsrl0;
assign dsrl2 = shamt[2] ? {4'h0, dsrl1[31:4]} : dsrl1;
assign dsrl3 = shamt[3] ? {8'h00, dsrl2[31:8]} : dsrl2;
assign dsrl4 = shamt[4] ? {16'h0000, dsrl3[31:16]} : dsrl3;
//SRA block
assign dsra0 = shamt[0] ? { in0[31], in0[31:1]} : in0;
assign dsra1 = shamt[1] ? { {2{dsra0[31]}} , dsra0[31:2]} : dsra0; //shift right arithmetically
assign dsra2 = shamt[2] ? { {4{dsra1[31]}} , dsra1[31:4]} : dsra1;
assign dsra3 = shamt[3] ? { {8{dsra2[31]}} , dsra2[31:8]} : dsra2;
assign dsra4 = shamt[4] ? { {16{dsra3[31]}} , dsra3[31:16]} : dsra3;
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////saturating unsigned arithmetic for byte-wise operation//////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
assign addb0_int = in0[7:0] + in1[7:0];
assign addb1_int = (alu_ctrl == ADDBI) ? in0[15:8] + in1[7:0] : in0[15:8] + in1[15:8];
assign addb2_int = (alu_ctrl == ADDBI) ? in0[15:8] + in1[7:0] : in0[23:16] + in1[23:16];
assign addb3_int = (alu_ctrl == ADDBI) ? in0[15:8] + in1[7:0] : in0[31:24] + in1[31:24];
assign addb0 = addb0_int[8] ? 8'hFF : addb0_int[7:0];
assign addb1 = addb1_int[8] ? 8'hFF : addb1_int[7:0];
assign addb2 = addb2_int[8] ? 8'hFF : addb2_int[7:0];
assign addb3 = addb3_int[8] ? 8'hFF : addb3_int[7:0];
assign subb0 = in0[7:0] - in1[7:0];
assign subb1 = (alu_ctrl == SUBBI) ? in0[15:8] - in1[7:0] : in0[15:8] - in1[15:8];
assign subb2 = (alu_ctrl == SUBBI) ? in0[15:8] - in1[7:0] : in0[23:16] - in1[23:16];
assign subb3 = (alu_ctrl == SUBBI) ? in0[15:8] - in1[7:0] : in0[31:24] - in1[31:24];
endmodule
|
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