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module cclk_detector #(
parameter CLK_RATE = 50000000
)(
input clk,
input rst,
input cclk,
output ready
);
parameter CTR_SIZE = $clog2(CLK_RATE/50000);
reg [CTR_SIZE-1:0] ctr_d, ctr_q;
reg ready_d, ready_q;
assign ready = ready_q;
// ready should only go high once cclk has been high for a while
// if cclk ever falls, ready should go low again
always @(ctr_q or cclk) begin
ready_d = 1'b0;
if (cclk == 1'b0) begin // when cclk is 0 reset the counter
ctr_d = 1'b0;
end else if (ctr_q != {CTR_SIZE{1'b1}}) begin
ctr_d = ctr_q + 1'b1; // counter isn't max value yet
end else begin
ctr_d = ctr_q;
ready_d = 1'b1; // counter reached the max, we are ready
end
end
always @(posedge clk) begin
if (rst) begin
ctr_q <= 1'b0;
ready_q <= 1'b0;
end else begin
ctr_q <= ctr_d;
ready_q <= ready_d;
end
end
endmodule
|
module avr_interface #(
parameter CLK_RATE = 50000000,
parameter SERIAL_BAUD_RATE = 500000
)(
input clk,
input rst,
// cclk, or configuration clock is used when the FPGA is begin configured.
// The AVR will hold cclk high when it has finished initializing.
// It is important not to drive the lines connecting to the AVR
// until cclk is high for a short period of time to avoid contention.
input cclk,
// signal the rest of the chip we are ready
output ready,
// AVR SPI Signals
output spi_miso,
input spi_mosi,
input spi_sck,
input spi_ss,
// AVR Serial Signals
output tx,
input rx,
// Serial Interface
output [7:0] rx_data,
output new_rx_data,
input [7:0] tx_data,
input new_tx_data,
output tx_busy,
input tx_block,
// Register interface signals
output [5:0] reg_addr,
output write,
output new_req,
output [7:0] write_value,
input [7:0] read_value
);
wire n_rdy = !ready;
wire spi_done;
wire [7:0] spi_dout;
wire frame_start, frame_end;
wire tx_m;
wire spi_miso_m;
localparam STATE_SIZE = 2;
localparam IDLE = 0,
ADDR = 1,
WRITE = 2,
READ = 3;
reg [STATE_SIZE-1:0] state_d, state_q;
reg [7:0] write_value_d, write_value_q;
reg write_d, write_q;
reg auto_inc_d, auto_inc_q;
reg [5:0] reg_addr_d, reg_addr_q;
reg new_req_d, new_req_q;
reg first_write_d, first_write_q;
assign reg_addr = reg_addr_q;
assign write = write_q;
assign new_req = new_req_q;
assign write_value = write_value_q;
// these signals connect to the AVR and should be Z when the AVR isn't ready
assign spi_miso = ready && !spi_ss ? spi_miso_m : 1'bZ;
assign tx = ready ? tx_m : 1'bZ;
// cclk_detector is used to detect when cclk is high signaling when
// the AVR is ready
cclk_detector #(.CLK_RATE(CLK_RATE)) cclk_detector (
.clk(clk),
.rst(rst),
.cclk(cclk),
.ready(ready)
);
spi_slave spi_slave (
.clk(clk),
.rst(n_rdy),
.ss(spi_ss),
.mosi(spi_mosi),
.miso(spi_miso_m),
.sck(spi_sck),
.done(spi_done),
.din(read_value),
.dout(spi_dout),
.frame_start(frame_start),
.frame_end(frame_end)
);
// CLK_PER_BIT is the number of cycles each 'bit' lasts for
// rtoi converts a 'real' number to an 'integer'
parameter CLK_PER_BIT = $rtoi($ceil(CLK_RATE/SERIAL_BAUD_RATE));
serial_rx #(.CLK_PER_BIT(CLK_PER_BIT)) serial_rx (
.clk(clk),
.rst(n_rdy),
.rx(rx),
.data(rx_data),
.new_data(new_rx_data)
);
serial_tx #(.CLK_PER_BIT(CLK_PER_BIT)) serial_tx (
.clk(clk),
.rst(n_rdy),
.tx(tx_m),
.block(tx_block),
.busy(tx_busy),
.data(tx_data),
.new_data(new_tx_data)
);
always @(*) begin
write_value_d = write_value_q;
write_d = write_q;
auto_inc_d = auto_inc_q;
reg_addr_d = reg_addr_q;
new_req_d = 1'b0;
state_d = state_q;
first_write_d = first_write_q;
case (state_q)
IDLE: begin
if (frame_start)
state_d = ADDR;
end
ADDR: begin
if (spi_done) begin
first_write_d = 1'b1;
{write_d, auto_inc_d, reg_addr_d} = spi_dout;
if (spi_dout[7]) begin
state_d = WRITE;
end else begin
state_d = READ;
new_req_d = 1'b1;
end
end
end
WRITE: begin
if (spi_done) begin
first_write_d = 1'b0;
if (auto_inc_q && !first_write_q)
reg_addr_d = reg_addr_q + 1'b1;
new_req_d = 1'b1;
write_value_d = spi_dout;
end
end
READ: begin
if (spi_done) begin
if (auto_inc_q)
reg_addr_d = reg_addr_q + 1'b1;
new_req_d = 1'b1;
end
end
default: state_d = IDLE;
endcase
if (frame_end)
state_d = IDLE;
end
always @(posedge clk) begin
if (n_rdy) begin
state_q <= IDLE;
end else begin
state_q <= state_d;
end
write_value_q <= write_value_d;
write_q <= write_d;
auto_inc_q <= auto_inc_d;
reg_addr_q <= reg_addr_d;
new_req_q <= new_req_d;
first_write_q <= first_write_d;
end
endmodule
|
module mojo_top(
// 50MHz clock input
input clk,
// Input from reset button (active low)
input rst_n,
// cclk input from AVR, high when AVR is ready
input cclk,
// Outputs to the 8 onboard LEDs
output[7:0]led,
// AVR SPI connections
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
// AVR ADC channel select
output [3:0] spi_channel,
// Serial connections
input avr_tx, // AVR Tx => FPGA Rx
output avr_rx, // AVR Rx => FPGA Tx
input avr_rx_busy, // AVR Rx buffer full
\t
\t //Additional connections
\t //Serial
\t output ext_tx, //FPGA Tx
\t input ext_rx, //FPGA Rx
\t //Spi
\t output ext_miso, //35
\t input ext_mosi, //34
\t input ext_ss, //40
\t input ext_sck, //41
\t
\t input [NUM_ULTRASONICS-1:0] echo, //ultrasonic received dur.
\t output [NUM_ULTRASONICS-1:0] trigger //ultrasonic start
);
wire rst = ~rst_n; // make reset active high
// these signals should be high-z when not used
assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;
//assign ext_miso = 1'bz;
assign ext_tx = 1'bz;
//Setup clock
wire clk_10us;
clk_divider #(.DIV(500)) div_clk10us(
\t .clk(clk),
\t .rst(rst),
\t .div_clk(clk_10us));
//Setup hcsr04s
wire measure_dist;
assign measure_dist = 1'b1;
parameter NUM_ULTRASONICS = 9;
//Each distance takes 16 bits
wire [NUM_ULTRASONICS * 16 -1:0] us_dists;
wire [NUM_ULTRASONICS - 1: 0] us_dists_valid;
genvar i;
generate
for (i = 0; i < NUM_ULTRASONICS; i=i+1) begin: us_gen_loop
hcsr04 #(
\t .TRIGGER_DURATION(1),
\t .MAX_COUNT(3800)
) ultrasonic(
\t .clk(clk),
\t .tclk(clk_10us),
\t .rst(rst),
\t .measure(measure_dist),
\t .echo(echo[i]),
\t .ticks(us_dists[16*i+16 - 1: 16*i]),
\t .valid(us_dists_valid[i]),
\t .trigger(trigger[i]));
end
endgenerate
//Setup comm protocol
localparam ADDR_SPACE = 64;
wire [8*ADDR_SPACE -1:0] mojo_com_rx_arr;
wire [8*ADDR_SPACE -1:0] mojo_com_tx_arr;
//assign mojo_com_tx_arr = {8'hde,8'had,8'hbe,8'hef, us_dists};
assign mojo_com_tx_arr = {300'b0,8'hde,8'had,8'hbe,8'hef, us_dists[15:0]};
wire mojo_com_rx_busy, mojo_com_new_rx, mojo_com_tx_busy;
mojo_com #(
\t.ADDR_SPACE(ADDR_SPACE))
com_unit(
\t.clk(clk),
\t.rst(rst),
\t//SPI wires
\t.ss(ext_ss),
\t.sck(ext_sck),
\t.mosi(ext_mosi),
\t.miso(ext_miso),
\t//Interface wires
\t.rx_arr(mojo_com_rx_arr),
\t.rx_busy(mojo_com_rx_busy),
\t.new_rx(mojo_com_new_rx),
\t.tx_arr(mojo_com_tx_arr),
\t.tx_busy(mojo_com_tx_busy)
);
assign led = mojo_com_rx_arr[15:8];
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:10:03 03/27/2015
// Design Name: mojo_com_logic
// Module Name: /home/michael/Projects/mojo/ultrasonic-fountain/hardware/mojo_com_logic_test.v
// Project Name: Mojo-Base
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: mojo_com_logic
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module mojo_com_logic_test;
\t// Inputs
\treg clk;
\treg rst;
\treg ser_tx_busy;
\treg [7:0] ser_rx_data;
\treg ser_new_rx_data;
\treg [2047:0] tx_arr;
\t// Outputs
\twire [7:0] ser_tx_data;
\twire ser_new_tx_data;
\twire [2047:0] rx_arr;
\tlocalparam WATCH_SPACE = 48;
\twire [WATCH_SPACE -1:0] rx_arr_watch;
\tassign rx_arr_watch = rx_arr[WATCH_SPACE-1:0];
\twire rx_busy;
\twire new_rx;
\twire tx_busy;
\t
\twire [31:0] cur_addr, end_addr;
\twire [2:0] cur_state;
\t// Instantiate the Unit Under Test (UUT)
\tmojo_com_logic uut (
\t\t.clk(clk),
\t\t.rst(rst),
\t\t.ser_tx_data(ser_tx_data),
\t\t.ser_new_tx_data(ser_new_tx_data),
\t\t.ser_tx_busy(ser_tx_busy),
\t\t.ser_rx_data(ser_rx_data),
\t\t.ser_new_rx_data(ser_new_rx_data),
\t\t.rx_arr(rx_arr),
\t\t.rx_busy(rx_busy),
\t\t.new_rx(new_rx),
\t\t.tx_arr(tx_arr),
\t\t.tx_busy(tx_busy)
\t\t//debug
\t\t, .cur_addr(cur_addr),
\t\t.end_addr(end_addr),
\t\t.cur_state(cur_state)
\t);
\tinitial begin
\t\t// Initialize Inputs
\t\tclk = 0;
\t\tser_tx_busy = 0;
\t\tser_rx_data = 0;
\t\tser_new_rx_data = 0;
\t\ttx_arr = 32'hdeadbeef;
rst = 1'b1;
repeat(4) #10 clk = ~clk;
rst = 1'b0;
forever #10 clk = ~clk; // generate a clock
end
initial begin
@(negedge rst); // wait for reset
\t\t //Test receive
ser_rx_data = 8'b10000001; //write 1 long to
\t\t ser_new_rx_data = 1;
\t\t repeat(1) @(posedge clk);
\t\t ser_new_rx_data = 0;
repeat(100) @(posedge clk);
\t\t ser_rx_data = 8'b00000010; //@ address 2
\t\t ser_new_rx_data = 1;
\t\t repeat(1) @(posedge clk);
\t\t ser_new_rx_data = 0;
\t\t repeat(100) @(posedge clk);
\t\t ser_rx_data = 8'b00000110; //write 6
\t\t ser_new_rx_data = 1;
\t\t repeat(1) @(posedge clk);
\t\t ser_new_rx_data = 0;
\t\t repeat(100) @(posedge clk);
\t\t ser_rx_data = 8'b10000010; //write 2 long at
\t\t ser_new_rx_data = 1;
\t\t repeat(1) @(posedge clk);
\t\t ser_new_rx_data = 0;
repeat(100) @(posedge clk);
\t\t ser_rx_data = 8'b00000000; //@ address 0
\t\t ser_new_rx_data = 1;
\t\t repeat(1) @(posedge clk);
\t\t ser_new_rx_data = 0;
\t\t repeat(100) @(posedge clk);
\t\t ser_rx_data = 8'had; //write ad
\t\t ser_new_rx_data = 1;
\t\t repeat(1) @(posedge clk);
\t\t ser_new_rx_data = 0;
\t\t repeat(100) @(posedge clk);
\t\t ser_rx_data = 8'hde; //write de
\t\t ser_new_rx_data = 1;
\t\t repeat(1) @(posedge clk);
\t\t ser_new_rx_data = 0;
\t\t repeat(1000) @(posedge clk);
\t\t //Done testing receive, rx_arr[23:0] should == 24'h06dead
\t\t
\t\t //TEST SEND!
\t\t ser_rx_data = 8'b1; //read 1 long from
\t\t ser_new_rx_data = 1;
\t\t repeat(1) @(posedge clk);
\t\t ser_new_rx_data = 0;
repeat(100) @(posedge clk);
\t\t ser_rx_data = 8'b00000000; //@ address 0
\t\t ser_new_rx_data = 1;
\t\t repeat(1) @(posedge clk);
\t\t ser_new_rx_data = 0;
\t\t repeat(100) @(posedge clk);
\t\t ser_rx_data = 8'b11; //read 3 long from
\t\t ser_new_rx_data = 1;
\t\t repeat(1) @(posedge clk);
\t\t ser_new_rx_data = 0;
repeat(100) @(posedge clk);
\t\t ser_rx_data = 8'b1; //@ address 1
\t\t ser_new_rx_data = 1;
\t\t repeat(1) @(posedge clk);
\t\t ser_new_rx_data = 0;
\t\t repeat(2) @(posedge clk);
\t\t ser_tx_busy = 1;
\t\t repeat(10) @(posedge clk);
\t\t ser_tx_busy = 0;
\t\t repeat(100) @(posedge clk);
\t\t //done testing send, ser_tx_data should look like [ef,... be,ad, ... de]
\t\t //second wait is from ser_tx_busy
\t\t //Might need to slow down serial response, because don't have busy line
\t\t
$finish;
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:03:09 03/24/2015
// Design Name: clk_divider
// Module Name: /home/michael/Projects/mojo/ultrasonic-fountain/clk_divider_test.v
// Project Name: Mojo-Base
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: clk_divider
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module clk_divider_test;
\t// Inputs
\treg rst;
\treg clk;
\t// Outputs
\twire div_clk_2, div_clk_3, div_clk_4;
\t// Instantiate the Unit Under Test (UUT)
\tclk_divider #(.DIV(2)) uut2 (
\t\t.rst(rst),
\t\t.clk(clk),
\t\t.div_clk(div_clk_2)
\t);
\tclk_divider #(.DIV(3)) uut3 (
\t\t.rst(rst),
\t\t.clk(clk),
\t\t.div_clk(div_clk_3)
\t);
\tclk_divider #(.DIV(500)) uut4 (
\t\t.rst(rst),
\t\t.clk(clk),
\t\t.div_clk(div_clk_4)
\t);
\t
\treg [31:0] ctr_d, ctr_q;
\talways @(*) begin
\t\tctr_d = ctr_q;
\t\tif(div_clk_4) begin
\t\t\tctr_d = ctr_q + 1;
\t\tend
\tend
\talways @(posedge clk) begin
\t\tif (rst) begin
\t\t\tctr_q <= 0;
\t\tend else begin
\t\t\tctr_q <= ctr_d;
\t\tend
\tend
\tinitial begin
\t\t// Initialize Inputs
\t\tclk = 0;
rst = 1'b1;
repeat(4) #10 clk = ~clk;
rst = 1'b0;
forever #10 clk = ~clk; // generate a clock
end
initial begin
@(negedge rst); // wait for reset
repeat(5000) @(posedge clk); //wait for trigger to finish, 10us
$finish;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Michael Christen
//
// Create Date: 11:32:43 03/09/2015
// Design Name:
// Module Name: hcsr04
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module hcsr04 #(
\tparameter TRIGGER_DURATION = 500,
\tparameter MAX_COUNT = 3000000
)(
\tinput rst,
\tinput clk,
\tinput tclk,
\tinput measure,
\tinput echo,
\t
\toutput reg [15:0] ticks,
\toutput reg valid,
\toutput reg trigger
);
\t
localparam STATE_SIZE = 3,
\t CTR_SIZE = 16;
localparam STATE_RESET = 3'd0,
STATE_IDLE = 3'd1,
STATE_TRIGGER = 3'd2,
\t STATE_COUNT = 3'd3,
\t STATE_COOLDOWN = 3'd4;
\t
\t reg [CTR_SIZE-1:0] ctr_d, ctr_q;
\t reg [STATE_SIZE-1:0] state_d, state_q;
\t reg [15:0] ticks_d;
\t reg trigger_d, valid_d;
\t reg echo_old;
\t
\t reg echo_chg, echo_pos, echo_neg;
\t
\t
\t always @(*) begin
\t\techo_chg = echo_old ^ echo;
\t\techo_pos = echo_chg & echo;
\t\techo_neg = echo_chg & (~echo);
\t\tctr_d = ctr_q;
\t\tstate_d = state_q;
\t\ttrigger_d = 0;
\t\tvalid_d = valid;
\t\tticks_d = ticks;
\t\t
\t\tcase (state_q)
\t\t\tSTATE_RESET: begin
\t\t\t\tctr_d = 0;
\t\t\t\tvalid_d = 0;
\t\t\t\tticks_d = 0;
\t\t\t\tstate_d = STATE_IDLE;
\t\t\tend
\t\t\tSTATE_IDLE: begin
\t\t\t\tctr_d = 0;
\t\t\t\tif(measure) begin
\t\t\t\t\tstate_d = STATE_TRIGGER;
\t\t\t\tend else begin
\t\t\t\t\tstate_d = STATE_IDLE;
\t\t\t\tend
\t\t\tend
\t\t\tSTATE_TRIGGER: begin
\t\t\t\tif(tclk) begin
\t\t\t\t\tctr_d = ctr_q + 1;
\t\t\t\tend
\t\t\t\ttrigger_d = 1'b1;
\t\t\t\tif(ctr_q == TRIGGER_DURATION) begin
\t\t\t\t\tstate_d = STATE_COUNT;
\t\t\t\tend
\t\t\tend
\t\t\tSTATE_COUNT: begin
\t\t\t\tif(tclk) begin
\t\t\t\t\tctr_d = ctr_q + 1;
\t\t\t\tend
\t\t\t\tif(ctr_q == MAX_COUNT) begin
\t\t\t\t\tticks_d = MAX_COUNT;
\t\t\t\t\tstate_d = STATE_IDLE;
\t\t\t\tend else if(echo_neg) begin
\t\t\t\t\tticks_d = ctr_q;
\t\t\t\t\tvalid_d = 1'b1;
\t\t\t\t\tstate_d = STATE_IDLE;
\t\t\t\tend else if(echo_pos) begin
\t\t\t\t\tctr_d = 0;
\t\t\t\tend
\t\t\tend
\t\tendcase
\t end
always @(posedge clk) begin
if (rst) begin
state_q <= STATE_RESET;
\t\t\t\tctr_q <= 0;
\t\t\t\tticks <= 0;
\t\t\t\tvalid <= 0;
\t\t\t\ttrigger <= 0;
\t\t\t\techo_old <= 0;
end else begin
\t\t\t\tstate_q <= state_d;
\t\t\t\tctr_q <= ctr_d;
\t\t\t\tticks <= ticks_d;
\t\t\t\tvalid <= valid_d;
\t\t\t\ttrigger <= trigger_d;
\t\t\t\techo_old <= echo;
\t\t end
\t end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16.03.2017 13:00:32
// Design Name:
// Module Name: arb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module arb(
input clk25,
input uartrx,
output[11:0] outA,
output[11:0] outB
);
reg[63:0] freqA = 1000;
reg[63:0] freqB = 1000;
wire rxready;
wire[7:0] recv_data;
wire rxidle;
async_receiver uart(clk25, uartrx, rxready, recv_data, rxidle);
reg chan = 1;
reg[15:0] write_i = 0;
reg[7:0] msb = 0;
reg[1:0] rxstate = 0;
reg[31:0] phase_accA = 0;
reg[31:0] phase_accB = 0;
reg[15:0] writedata = 0;
reg writeen = 0;
reg[13:0] options = 0;
reg burst_modeA = 0;
reg burstA = 0;
reg burst_modeB = 0;
reg burstB = 0;
wire frame_ch1 = (msb[7:6] == 1);
wire frame_ch2 = (msb[7:6] == 2);
wire frame_opt = (msb[7:6] == 3);
wire[13:0] header_payload = {msb[5:0],recv_data};
wire[15:0] phaseoutA = phase_accA[31:16];
wire[15:0] phaseoutB = phase_accB[31:16];
always @(posedge clk25) begin
if(rxready) begin
msb <= recv_data;
rxstate = (rxstate==0)?1:(rxstate==1)?2:1;
if(rxstate == 2) begin
writedata <= {msb, recv_data};
writeen = !(frame_ch1 || frame_ch2);
freqA = frame_ch1 ? header_payload : freqA;
freqB = frame_ch2 ? header_payload : freqB;
options = frame_opt ? header_payload : options;
write_i = (writedata[15:14] != 0) ? 0 : write_i + 1;
chan = (frame_ch1) ? 0 : (frame_ch2) ? 1 : chan;
end else begin
options = 0;
writeen = 0;
end
end else begin
options = 0;
if(rxidle)
rxstate = 0;
end
burst_modeA = burst_modeA ? (options[1]==0) : (options[0]==1);
burstA <= burstA ? (phaseoutA < 65535) : (options[2]);
phase_accA = (burst_modeA && !burstA) ? 0 : phase_accA + ((freqA*1717987)/10000);
burst_modeB = burst_modeB ? (options[4]==0) : (options[3]==1);
burstB <= burstB ? (phaseoutB < 65535) : (options[5]);
phase_accB = (burst_modeB && !burstB) ? 0 : phase_accB + ((freqB*1717987)/10000);
end
blk_mem_gen_arb ddsram1(.clka(clk25), .ena(~chan), .wea(writeen), .addra(write_i), .dina(writedata[11:0]), .clkb(clk25), .enb(1'b1), .addrb(phaseoutA), .doutb(outA));
blk_mem_gen_arb ddsram2(.clka(clk25), .ena(chan), .wea(writeen), .addra(write_i), .dina(writedata[11:0]), .clkb(clk25), .enb(1'b1), .addrb(phaseoutB), .doutb(outB));
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
/******************************************************************************
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
*****************************************************************************
*
* Filename: blk_mem_gen_v8_3_5.v
*
* Description:
* This file is the Verilog behvarial model for the
* Block Memory Generator Core.
*
*****************************************************************************
* Author: Xilinx
*
* History: Jan 11, 2006 Initial revision
* Jun 11, 2007 Added independent register stages for
* Port A and Port B (IP1_Jm/v2.5)
* Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)
* Mar 13, 2008 Behavioral model optimizations
* April 07, 2009 : Added support for Spartan-6 and Virtex-6
* features, including the following:
* (i) error injection, detection and/or correction
* (ii) reset priority
* (iii) special reset behavior
*
*****************************************************************************/
`timescale 1ps/1ps
module STATE_LOGIC_v8_3 (O, I0, I1, I2, I3, I4, I5);
parameter INIT = 64\'h0000000000000000;
input I0, I1, I2, I3, I4, I5;
output O;
reg O;
reg tmp;
always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin
tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5;
if ( tmp == 0 || tmp == 1)
O = INIT[{I5, I4, I3, I2, I1, I0}];
end
endmodule
module beh_vlog_muxf7_v8_3 (O, I0, I1, S);
output O;
reg O;
input I0, I1, S;
\talways @(I0 or I1 or S)
\t if (S)
\t\tO = I1;
\t else
\t\tO = I0;
endmodule
module beh_vlog_ff_clr_v8_3 (Q, C, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CLR, D;
reg Q;
initial Q= 1\'b0;
always @(posedge C )
if (CLR)
\tQ<= 1\'b0;
else
\tQ<= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_pre_v8_3 (Q, C, D, PRE);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, D, PRE;
reg Q;
initial Q= 1\'b0;
always @(posedge C )
if (PRE)
Q <= 1\'b1;
else
\t Q <= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_ce_clr_v8_3 (Q, C, CE, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CE, CLR, D;
reg Q;
initial Q= 1\'b0;
always @(posedge C )
if (CLR)
Q <= 1\'b0;
else if (CE)
\t Q <= #FLOP_DELAY D;
endmodule
module write_netlist_v8_3
#(
parameter\t C_AXI_TYPE = 0
)
(
S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,
w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,
S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c
);
input S_ACLK;
input S_ARESETN;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input S_AXI_BREADY;
input w_last_c;
input bready_timeout_c;
output aw_ready_r;
output S_AXI_WREADY;
output S_AXI_BVALID;
output S_AXI_WR_EN;
output addr_en_c;
output incr_addr_c;
output bvalid_c;
//-------------------------------------------------------------------------
//AXI LITE
//-------------------------------------------------------------------------
generate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm
wire w_ready_r_7;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSignal_bvalid_c;
wire NlwRenamedSignal_incr_addr_c;
wire present_state_FSM_FFd3_13;
wire present_state_FSM_FFd2_14;
wire present_state_FSM_FFd1_15;
wire present_state_FSM_FFd4_16;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd4_In1_21;
wire [0:0] Mmux_aw_ready_c ;
begin
assign
S_AXI_WREADY = w_ready_r_7,
S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,
S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,
incr_addr_c = NlwRenamedSignal_incr_addr_c,
bvalid_c = NlwRenamedSignal_bvalid_c;
assign NlwRenamedSignal_incr_addr_c = 1\'b0;
beh_vlog_ff_clr_v8_3 #(
.INIT (1\'b0))
aw_ready_r_2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1\'b0))
w_ready_r (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_7)
);
beh_vlog_ff_pre_v8_3 #(
.INIT (1\'b1))
present_state_FSM_FFd4 (
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_16)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1\'b0))
present_state_FSM_FFd3 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_13)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1\'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1\'b0))
present_state_FSM_FFd1 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_15)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h0000000055554440))
present_state_FSM_FFd3_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 (1\'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h0000000088880800))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_AWVALID),
.I1 ( S_AXI_WVALID),
.I2 ( bready_timeout_c),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1\'b0),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h00000000AAAA2000))
Mmux_addr_en_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_WVALID),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1\'b0),
.O ( addr_en_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'hF5F07570F5F05500))
Mmux_w_ready_c_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( w_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h88808880FFFF8880))
present_state_FSM_FFd1_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd3_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd1_15),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( present_state_FSM_FFd3_13),
.I3 (1\'b0),
.I4 (1\'b0),
.I5 (1\'b0),
.O ( NlwRenamedSignal_bvalid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h2F0F27072F0F2200))
present_state_FSM_FFd4_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( present_state_FSM_FFd4_In1_21)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h00000000000000F8))
present_state_FSM_FFd4_In2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_In1_21),
.I3 (1\'b0),
.I4 (1\'b0),
.I5 (1\'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h7535753575305500))
Mmux_aw_ready_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_WVALID),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 ( present_state_FSM_FFd2_14),
.O ( Mmux_aw_ready_c[0])
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h00000000000000F8))
Mmux_aw_ready_c_0_2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( Mmux_aw_ready_c[0]),
.I3 (1\'b0),
.I4 (1\'b0),
.I5 (1\'b0),
.O ( aw_ready_c)
);
end
end
endgenerate
//---------------------------------------------------------------------
// AXI FULL
//---------------------------------------------------------------------
generate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm
wire w_ready_r_8;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSig_OI_bvalid_c;
wire present_state_FSM_FFd1_16;
wire present_state_FSM_FFd4_17;
wire present_state_FSM_FFd3_18;
wire present_state_FSM_FFd2_19;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd2_In1_24;
wire present_state_FSM_FFd4_In1_25;
wire N2;
wire N4;
begin
assign
S_AXI_WREADY = w_ready_r_8,
bvalid_c = NlwRenamedSig_OI_bvalid_c,
S_AXI_BVALID = 1\'b0;
beh_vlog_ff_clr_v8_3 #(
.INIT (1\'b0))
aw_ready_r_2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1\'b0))
w_ready_r
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_8)
);
beh_vlog_ff_pre_v8_3 #(
.INIT (1\'b1))
present_state_FSM_FFd4
(
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_17)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1\'b0))
present_state_FSM_FFd3
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_18)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1\'b0))
present_state_FSM_FFd2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_19)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1\'b0))
present_state_FSM_FFd1
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_16)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h0000000000005540))
present_state_FSM_FFd3_In1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd4_17),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1\'b0),
.I5 (1\'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'hBF3FBB33AF0FAA00))
Mmux_aw_ready_c_0_2
(
.I0 ( S_AXI_BREADY),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd1_16),
.I4 ( present_state_FSM_FFd4_17),
.I5 ( NlwRenamedSig_OI_bvalid_c),
.O ( aw_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'hAAAAAAAA20000000))
Mmux_addr_en_c_0_1
(
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( S_AXI_WVALID),
.I4 ( w_last_c),
.I5 ( present_state_FSM_FFd4_17),
.O ( addr_en_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_19),
.I2 ( present_state_FSM_FFd3_18),
.I3 (1\'b0),
.I4 (1\'b0),
.I5 (1\'b0),
.O ( S_AXI_WR_EN)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h0000000000002220))
Mmux_incr_addr_c_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1\'b0),
.I5 (1\'b0),
.O ( incr_addr_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h0000000000008880))
Mmux_aw_ready_c_0_11
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1\'b0),
.I5 (1\'b0),
.O ( NlwRenamedSig_OI_bvalid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h000000000000D5C0))
present_state_FSM_FFd2_In1
(
.I0 ( w_last_c),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1\'b0),
.I5 (1\'b0),
.O ( present_state_FSM_FFd2_In1_24)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'hFFFFAAAA08AAAAAA))
present_state_FSM_FFd2_In2
(
.I0 ( present_state_FSM_FFd2_19),
.I1 ( S_AXI_AWVALID),
.I2 ( bready_timeout_c),
.I3 ( w_last_c),
.I4 ( S_AXI_WVALID),
.I5 ( present_state_FSM_FFd2_In1_24),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h00C0004000C00000))
present_state_FSM_FFd4_In1
(
.I0 ( S_AXI_AWVALID),
.I1 ( w_last_c),
.I2 ( S_AXI_WVALID),
.I3 ( bready_timeout_c),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( present_state_FSM_FFd4_In1_25)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h00000000FFFF88F8))
present_state_FSM_FFd4_In2
(
.I0 ( present_state_FSM_FFd1_16),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( S_AXI_AWVALID),
.I4 ( present_state_FSM_FFd4_In1_25),
.I5 (1\'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h0000000000000007))
Mmux_w_ready_c_0_SW0
(
.I0 ( w_last_c),
.I1 ( S_AXI_WVALID),
.I2 (1\'b0),
.I3 (1\'b0),
.I4 (1\'b0),
.I5 (1\'b0),
.O ( N2)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'hFABAFABAFAAAF000))
Mmux_w_ready_c_0_Q
(
.I0 ( N2),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd4_17),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( w_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h0000000000000008))
Mmux_aw_ready_c_0_11_SW0
(
.I0 ( bready_timeout_c),
.I1 ( S_AXI_WVALID),
.I2 (1\'b0),
.I3 (1\'b0),
.I4 (1\'b0),
.I5 (1\'b0),
.O ( N4)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h88808880FFFF8880))
present_state_FSM_FFd1_In1
(
.I0 ( w_last_c),
.I1 ( N4),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 ( present_state_FSM_FFd1_16),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
end
end
endgenerate
endmodule
module read_netlist_v8_3 #(
parameter C_AXI_TYPE = 1,
parameter C_ADDRB_WIDTH = 12
) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,
S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,
S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,
S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);
input S_AXI_R_LAST_INT;
input S_ACLK;
input S_ARESETN;
input S_AXI_ARVALID;
input S_AXI_RREADY;
output S_AXI_INCR_ADDR;
output S_AXI_ADDR_EN;
output S_AXI_SINGLE_TRANS;
output S_AXI_MUX_SEL;
output S_AXI_R_LAST;
output S_AXI_ARREADY;
output S_AXI_RLAST;
output S_AXI_RVALID;
output S_AXI_RD_EN;
input [7:0] S_AXI_ARLEN;
wire present_state_FSM_FFd1_13 ;
wire present_state_FSM_FFd2_14 ;
wire gaxi_full_sm_outstanding_read_r_15 ;
wire gaxi_full_sm_ar_ready_r_16 ;
wire gaxi_full_sm_r_last_r_17 ;
wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ;
wire gaxi_full_sm_r_valid_c ;
wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ;
wire gaxi_full_sm_ar_ready_c ;
wire gaxi_full_sm_outstanding_read_c ;
wire NlwRenamedSig_OI_S_AXI_R_LAST ;
wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ;
wire present_state_FSM_FFd2_In ;
wire present_state_FSM_FFd1_In ;
wire Mmux_S_AXI_R_LAST13 ;
wire N01 ;
wire N2 ;
wire Mmux_gaxi_full_sm_ar_ready_c11 ;
wire N4 ;
wire N8 ;
wire N9 ;
wire N10 ;
wire N11 ;
wire N12 ;
wire N13 ;
assign
S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,
S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,
S_AXI_RLAST = gaxi_full_sm_r_last_r_17,
S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
beh_vlog_ff_clr_v8_3 #(
.INIT (1\'b0))
gaxi_full_sm_outstanding_read_r (
.C (S_ACLK),
.CLR(S_ARESETN),
.D(gaxi_full_sm_outstanding_read_c),
.Q(gaxi_full_sm_outstanding_read_r_15)
);
beh_vlog_ff_ce_clr_v8_3 #(
.INIT (1\'b0))
gaxi_full_sm_r_valid_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (gaxi_full_sm_r_valid_c),
.Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1\'b0))
gaxi_full_sm_ar_ready_r (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (gaxi_full_sm_ar_ready_c),
.Q (gaxi_full_sm_ar_ready_r_16)
);
beh_vlog_ff_ce_clr_v8_3 #(
.INIT(1\'b0))
gaxi_full_sm_r_last_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (NlwRenamedSig_OI_S_AXI_R_LAST),
.Q (gaxi_full_sm_r_last_r_17)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1\'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1\'b0))
present_state_FSM_FFd1 (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (present_state_FSM_FFd1_In),
.Q (present_state_FSM_FFd1_13)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h000000000000000B))
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (
.I0 ( S_AXI_RREADY),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (1\'b0),
.I3 (1\'b0),
.I4 (1\'b0),
.I5 (1\'b0),
.O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h0000000000000008))
Mmux_S_AXI_SINGLE_TRANS11 (
.I0 (S_AXI_ARVALID),
.I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 (1\'b0),
.I3 (1\'b0),
.I4 (1\'b0),
.I5 (1\'b0),
.O (S_AXI_SINGLE_TRANS)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h0000000000000004))
Mmux_S_AXI_ADDR_EN11 (
.I0 (present_state_FSM_FFd1_13),
.I1 (S_AXI_ARVALID),
.I2 (1\'b0),
.I3 (1\'b0),
.I4 (1\'b0),
.I5 (1\'b0),
.O (S_AXI_ADDR_EN)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'hECEE2022EEEE2022))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_ARVALID),
.I1 ( present_state_FSM_FFd1_13),
.I2 ( S_AXI_RREADY),
.I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h0000000044440444))
Mmux_S_AXI_R_LAST131 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_RREADY),
.I5 (1\'b0),
.O ( Mmux_S_AXI_R_LAST13)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h4000FFFF40004000))
Mmux_S_AXI_INCR_ADDR11 (
.I0 ( S_AXI_R_LAST_INT),
.I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( Mmux_S_AXI_R_LAST13),
.O ( S_AXI_INCR_ADDR)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h00000000000000FE))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (
.I0 ( S_AXI_ARLEN[2]),
.I1 ( S_AXI_ARLEN[1]),
.I2 ( S_AXI_ARLEN[0]),
.I3 ( 1\'b0),
.I4 ( 1\'b0),
.I5 ( 1\'b0),
.O ( N01)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h0000000000000001))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (
.I0 ( S_AXI_ARLEN[7]),
.I1 ( S_AXI_ARLEN[6]),
.I2 ( S_AXI_ARLEN[5]),
.I3 ( S_AXI_ARLEN[4]),
.I4 ( S_AXI_ARLEN[3]),
.I5 ( N01),
.O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h0000000000000007))
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 ( 1\'b0),
.I3 ( 1\'b0),
.I4 ( 1\'b0),
.I5 ( 1\'b0),
.O ( N2)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h0020000002200200))
Mmux_gaxi_full_sm_outstanding_read_c1 (
.I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd1_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( gaxi_full_sm_outstanding_read_r_15),
.I5 ( N2),
.O ( gaxi_full_sm_outstanding_read_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h0000000000004555))
Mmux_gaxi_full_sm_ar_ready_c12 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( 1\'b0),
.I5 ( 1\'b0),
.O ( Mmux_gaxi_full_sm_ar_ready_c11)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h00000000000000EF))
Mmux_S_AXI_R_LAST11_SW0 (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I3 ( 1\'b0),
.I4 ( 1\'b0),
.I5 ( 1\'b0),
.O ( N4)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'hFCAAFC0A00AA000A))
Mmux_S_AXI_R_LAST11 (
.I0 ( S_AXI_ARVALID),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( N4),
.I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.O ( gaxi_full_sm_r_valid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h00000000AAAAAA08))
S_AXI_MUX_SEL1 (
.I0 (present_state_FSM_FFd1_13),
.I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (S_AXI_RREADY),
.I3 (present_state_FSM_FFd2_14),
.I4 (gaxi_full_sm_outstanding_read_r_15),
.I5 (1\'b0),
.O (S_AXI_MUX_SEL)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'hF3F3F755A2A2A200))
Mmux_S_AXI_RD_EN11 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 ( S_AXI_RREADY),
.I3 ( gaxi_full_sm_outstanding_read_r_15),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( S_AXI_ARVALID),
.O ( S_AXI_RD_EN)
);
beh_vlog_muxf7_v8_3 present_state_FSM_FFd1_In3 (
.I0 ( N8),
.I1 ( N9),
.S ( present_state_FSM_FFd1_13),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h000000005410F4F0))
present_state_FSM_FFd1_In3_F (
.I0 ( S_AXI_RREADY),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( S_AXI_ARVALID),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( 1\'b0),
.O ( N8)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h0000000072FF7272))
present_state_FSM_FFd1_In3_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1\'b0),
.O ( N9)
);
beh_vlog_muxf7_v8_3 Mmux_gaxi_full_sm_ar_ready_c14 (
.I0 ( N10),
.I1 ( N11),
.S ( present_state_FSM_FFd1_13),
.O ( gaxi_full_sm_ar_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h00000000FFFF88A8))
Mmux_gaxi_full_sm_ar_ready_c14_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( Mmux_gaxi_full_sm_ar_ready_c11),
.I5 ( 1\'b0),
.O ( N10)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h000000008D008D8D))
Mmux_gaxi_full_sm_ar_ready_c14_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1\'b0),
.O ( N11)
);
beh_vlog_muxf7_v8_3 Mmux_S_AXI_R_LAST1 (
.I0 ( N12),
.I1 ( N13),
.S ( present_state_FSM_FFd1_13),
.O ( NlwRenamedSig_OI_S_AXI_R_LAST)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h0000000088088888))
Mmux_S_AXI_R_LAST1_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1\'b0),
.O ( N12)
);
STATE_LOGIC_v8_3 #(
.INIT (64\'h00000000E400E4E4))
Mmux_S_AXI_R_LAST1_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( S_AXI_R_LAST_INT),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1\'b0),
.O ( N13)
);
endmodule
module blk_mem_axi_write_wrapper_beh_v8_3
# (
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface
parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full;
parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
parameter C_WRITE_DEPTH_A = 0,
parameter C_AXI_AWADDR_WIDTH = 32,
parameter C_ADDRA_WIDTH \t = 12,
parameter C_AXI_WDATA_WIDTH = 32,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
// AXI OUTSTANDING WRITES
parameter C_AXI_OS_WR = 2
)
(
// AXI Global Signals
input S_ACLK,
input S_ARESETN,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,
input [8-1:0] S_AXI_AWLEN,
input [2:0] S_AXI_AWSIZE,
input [1:0] S_AXI_AWBURST,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
input S_AXI_WVALID,
output S_AXI_WREADY,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,
output S_AXI_BVALID,
input S_AXI_BREADY,
// Signals for BMG interface
output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,
output S_AXI_WR_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:
((C_AXI_WDATA_WIDTH==16)?1:
((C_AXI_WDATA_WIDTH==32)?2:
((C_AXI_WDATA_WIDTH==64)?3:
((C_AXI_WDATA_WIDTH==128)?4:
((C_AXI_WDATA_WIDTH==256)?5:0))))));
wire bvalid_c ;
reg bready_timeout_c = 0;
wire [1:0] bvalid_rd_cnt_c;
reg bvalid_r \t= 0;
reg [2:0] bvalid_count_r = 0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;
reg [1:0] bvalid_wr_cnt_r = 0;
reg [1:0] bvalid_rd_cnt_r = 0;
wire w_last_c ;
wire addr_en_c ;
wire incr_addr_c ;
wire aw_ready_r \t ;
wire dec_alen_c ;
reg bvalid_d1_c = 0;
reg [7:0] awlen_cntr_r = 0;
reg [7:0] awlen_int = 0;
reg [1:0] awburst_int = 0;
integer total_bytes = 0;
integer wrap_boundary = 0;
integer wrap_base_addr = 0;
integer num_of_bytes_c = 0;
integer num_of_bytes_r = 0;
// Array to store BIDs
reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;
wire S_AXI_BVALID_axi_wr_fsm;
//-------------------------------------
//AXI WRITE FSM COMPONENT INSTANTIATION
//-------------------------------------
write_netlist_v8_3 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm
(
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
.S_AXI_AWVALID(S_AXI_AWVALID),
.aw_ready_r(aw_ready_r),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_WR_EN(S_AXI_WR_EN),
.w_last_c(w_last_c),
.bready_timeout_c(bready_timeout_c),
.addr_en_c(addr_en_c),
.incr_addr_c(incr_addr_c),
.bvalid_c(bvalid_c),
.S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm)
\t );
//Wrap Address boundary calculation
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);
total_bytes = (num_of_bytes_r)*(awlen_int+1);
wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);
wrap_boundary = wrap_base_addr+total_bytes;
end
//-------------------------------------------------------------------------
// BMG address generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1\'b1) begin
awaddr_reg <= 0;
\t num_of_bytes_r <= 0;
\t awburst_int <= 0;
\t end else begin
if (addr_en_c == 1\'b1) begin
awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ;
\t num_of_bytes_r <= num_of_bytes_c;
\t awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2\'b01);
\t end else if (incr_addr_c == 1\'b1) begin
\t if (awburst_int == 2\'b10) begin
\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin
\t\t awaddr_reg <= wrap_base_addr;
\t\tend else begin
\t\t awaddr_reg <= awaddr_reg + num_of_bytes_r;
\t\tend
\t end else if (awburst_int == 2\'b01 || awburst_int == 2\'b11) begin
\t\tawaddr_reg <= awaddr_reg + num_of_bytes_r;
\t end
end
end
end
assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
\t\t\t \t awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);
//-------------------------------------------------------------------------
// AXI wlast generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1\'b1) begin
awlen_cntr_r <= 0;
\t awlen_int <= 0;
\t end else begin
if (addr_en_c == 1\'b1) begin
\t awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
\t awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
\t end else if (dec_alen_c == 1\'b1) begin
awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ;
end
end
end
assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1\'b1)?1\'b1:1\'b0;
assign dec_alen_c = (incr_addr_c | w_last_c);
//-------------------------------------------------------------------------
// Generation of bvalid counter for outstanding transactions
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1\'b1) begin
\tbvalid_count_r <= 0;
\tend else begin
\t// bvalid_count_r generation
\tif (bvalid_c == 1\'b1 && bvalid_r == 1\'b1 && S_AXI_BREADY == 1\'b1) begin
\t bvalid_count_r <= #FLOP_DELAY bvalid_count_r ;
\t end else if (bvalid_c == 1\'b1) begin
\t bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ;
\t end else if (bvalid_r == 1\'b1 && S_AXI_BREADY == 1\'b1 && bvalid_count_r != 0) begin
\t bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ;
\tend
end
end
//-------------------------------------------------------------------------
// Generation of bvalid when BID is used
//-------------------------------------------------------------------------
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1\'b1) begin
bvalid_r <= 0;
bvalid_d1_c <= 0;
\tend else begin
// Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
//external bvalid signal generation
if (bvalid_d1_c == 1\'b1) begin
bvalid_r <= #FLOP_DELAY 1\'b1 ;
\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1\'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of bvalid when BID is not used
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1\'b1) begin
bvalid_r <= 0;
\tend else begin
//external bvalid signal generation
if (bvalid_c == 1\'b1) begin
bvalid_r <= #FLOP_DELAY 1\'b1 ;
\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1\'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of Bready timeout
//-------------------------------------------------------------------------
always @(bvalid_count_r) begin
\t// bready_timeout_c generation
\tif(bvalid_count_r == C_AXI_OS_WR-1) begin
\t bready_timeout_c <= 1\'b1;
\tend else begin
\t bready_timeout_c <= 1\'b0;
\tend
end
//-------------------------------------------------------------------------
// Generation of BID
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1\'b1) begin
bvalid_wr_cnt_r <= 0;
bvalid_rd_cnt_r <= 0;
\tend else begin
// STORE AWID IN AN ARRAY
if(bvalid_c == 1\'b1) begin
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1;
end
\t // generate BID FROM AWID ARRAY
\t bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;
\t S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c];
end
end
assign bvalid_rd_cnt_c = (bvalid_r == 1\'b1 && S_AXI_BREADY == 1\'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;
//-------------------------------------------------------------------------
// Storing AWID for generation of BID
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if(S_ARESETN == 1\'b1) begin
\taxi_bid_array[0] = 0;
\taxi_bid_array[1] = 0;
\taxi_bid_array[2] = 0;
\taxi_bid_array[3] = 0;
\tend else if(aw_ready_r == 1\'b1 && S_AXI_AWVALID == 1\'b1) begin
\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;
end
end
end
endgenerate
assign S_AXI_BVALID = bvalid_r;
assign S_AXI_AWREADY = aw_ready_r;
endmodule
module blk_mem_axi_read_wrapper_beh_v8_3
# (
//// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_WRITE_WIDTH_A = 4,
parameter C_WRITE_DEPTH_A = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_PIPELINE_STAGES = 0,
parameter C_AXI_ARADDR_WIDTH = 12,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_ADDRB_WIDTH = 12
)
(
//// AXI Global Signals
input S_ACLK,
input S_ARESETN,
//// AXI Full/Lite Slave Read (Read side)
input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,
input [7:0] S_AXI_ARLEN,
input [2:0] S_AXI_ARSIZE,
input [1:0] S_AXI_ARBURST,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
output S_AXI_RLAST,
output S_AXI_RVALID,
input S_AXI_RREADY,
input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,
//// AXI Full/Lite Read Address Signals to BRAM
output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,
output S_AXI_RD_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:
((C_WRITE_WIDTH_A==16)?1:
((C_WRITE_WIDTH_A==32)?2:
((C_WRITE_WIDTH_A==64)?3:
((C_WRITE_WIDTH_A==128)?4:
((C_WRITE_WIDTH_A==256)?5:0))))));
reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;
wire addr_en_c;
wire rd_en_c;
wire incr_addr_c;
wire single_trans_c;
wire dec_alen_c;
wire mux_sel_c;
wire r_last_c;
wire r_last_int_c;
wire [C_ADDRB_WIDTH-1 : 0] araddr_out;
reg [7:0] arlen_int_r=0;
reg [7:0] arlen_cntr=8\'h01;
reg [1:0] arburst_int_c=0;
reg [1:0] arburst_int_r=0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;
integer num_of_bytes_c = 0;
integer total_bytes = 0;
integer num_of_bytes_r = 0;
integer wrap_base_addr_r = 0;
integer wrap_boundary_r = 0;
reg [7:0] arlen_int_c=0;
integer total_bytes_c = 0;
integer wrap_base_addr_c = 0;
integer wrap_boundary_c = 0;
assign dec_alen_c = incr_addr_c | r_last_int_c;
read_netlist_v8_3
#(.C_AXI_TYPE (1),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_read_fsm (
.S_AXI_INCR_ADDR(incr_addr_c),
.S_AXI_ADDR_EN(addr_en_c),
.S_AXI_SINGLE_TRANS(single_trans_c),
.S_AXI_MUX_SEL(mux_sel_c),
.S_AXI_R_LAST(r_last_c),
.S_AXI_R_LAST_INT(r_last_int_c),
//// AXI Global Signals
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
//// AXI Full/Lite Slave Read (Read side)
.S_AXI_ARLEN(S_AXI_ARLEN),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RLAST(S_AXI_RLAST),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
//// AXI Full/Lite Read Address Signals to BRAM
.S_AXI_RD_EN(rd_en_c)
);
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);
total_bytes = (num_of_bytes_r)*(arlen_int_r+1);
wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);
wrap_boundary_r = wrap_base_addr_r+total_bytes;
//////// combinatorial from interface
arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);
total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1);
wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);
wrap_boundary_c = wrap_base_addr_c+total_bytes_c;
arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);
end
////-------------------------------------------------------------------------
//// BMG address generation
////-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1\'b1) begin
araddr_reg \t<= 0;
\tarburst_int_r <= 0;
\tnum_of_bytes_r <= 0;
end else begin
if (incr_addr_c == 1\'b1 && addr_en_c == 1\'b1 && single_trans_c == 1\'b0) begin
\t arburst_int_r <= arburst_int_c;
\t num_of_bytes_r <= num_of_bytes_c;
\t if (arburst_int_c == 2\'b10) begin
\t\t if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin
\t\t araddr_reg <= wrap_base_addr_c;
\t\t end else begin
\t\t araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
\t\t end
\t end else if (arburst_int_c == 2\'b01 || arburst_int_c == 2\'b11) begin
\t\t araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
\t end
end else if (addr_en_c == 1\'b1) begin
araddr_reg <= S_AXI_ARADDR;
\t num_of_bytes_r <= num_of_bytes_c;
\t arburst_int_r <= arburst_int_c;
\t end else if (incr_addr_c == 1\'b1) begin
\t if (arburst_int_r == 2\'b10) begin
\t \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin
\t \t araddr_reg <= wrap_base_addr_r;
\t \tend else begin
\t \t araddr_reg <= araddr_reg + num_of_bytes_r;
\t \tend
\t end else if (arburst_int_r == 2\'b01 || arburst_int_r == 2\'b11) begin
\t\t araddr_reg <= araddr_reg + num_of_bytes_r;
\t end
end
end
end
assign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);
////-----------------------------------------------------------------------
//// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
////-----------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1\'b1) begin
arlen_cntr <= 8\'h01;
\t arlen_int_r <= 0;
\tend else begin
if (addr_en_c == 1\'b1 && dec_alen_c == 1\'b1 && single_trans_c == 1\'b0) begin
\t arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= S_AXI_ARLEN - 1\'b1;
\t end else if (addr_en_c == 1\'b1) begin
\t arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
\t arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
\t end else if (dec_alen_c == 1\'b1) begin
arlen_cntr <= arlen_cntr - 1\'b1 ;
end
\t else begin
\t arlen_cntr <= arlen_cntr;
\t end
end
end
assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1\'b1)?1\'b1:1\'b0;
////------------------------------------------------------------------------
//// AXI FULL FSM
//// Mux Selection of ARADDR
//// ARADDR is driven out from the read fsm based on the mux_sel_c
//// Based on mux_sel either ARADDR is given out or the latched ARADDR is
//// given out to BRAM
////------------------------------------------------------------------------
\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1\'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;
////------------------------------------------------------------------------
//// Assign output signals - AXI FULL FSM
////------------------------------------------------------------------------
assign S_AXI_RD_EN = rd_en_c;
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1\'b1) begin
S_AXI_RID <= 0;
ar_id_r <= 0;
\tend else begin
if (addr_en_c == 1\'b1 && rd_en_c == 1\'b1) begin
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
end else if (addr_en_c == 1\'b1 && rd_en_c == 1\'b0) begin
\t ar_id_r <= S_AXI_ARID;
end else if (rd_en_c == 1\'b1) begin
S_AXI_RID <= ar_id_r;
end
end
end
end
endgenerate
endmodule
module blk_mem_axi_regs_fwd_v8_3
#(parameter C_DATA_WIDTH = 8
)(
input ACLK,
input ARESET,
input S'b'_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
wire S_READY_I;
reg M_VALID_I;
reg [1:0] ARESET_D;
//assign local signal to its output signal
assign S_READY = S_READY_I;
assign M_VALID = M_VALID_I;
always @(posedge ACLK) begin
\t ARESET_D <= {ARESET_D[0], ARESET};
\tend
//Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK or ARESET) begin
if (ARESET == 1\'b1) begin
\t STORAGE_DATA <= 0;
\tend else begin
\t if(S_VALID == 1\'b1 && S_READY_I == 1\'b1 ) begin
\t STORAGE_DATA <= S_PAYLOAD_DATA;
\t end
\tend
end
always @(posedge ACLK) begin
M_PAYLOAD_DATA = STORAGE_DATA;
end
//M_Valid set to high when we have a completed transfer on slave side
//Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK or ARESET_D) begin
\tif (ARESET_D != 2\'b00) begin
\t M_VALID_I <= 1\'b0;
\tend else begin
\t if (S_VALID == 1\'b1) begin
\t //Always set M_VALID_I when slave side is valid
M_VALID_I <= 1\'b1;
\t end else if (M_READY == 1\'b1 ) begin
\t //Clear (or keep) when no slave side is valid but master side is ready
\t M_VALID_I <= 1\'b0;
\t end
\tend
end
//Slave Ready is either when Master side drives M_READY or we have space in our storage data
assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
endmodule
//*****************************************************************************
// Output Register Stage module
//
// This module builds the output register stages of the memory. This module is
// instantiated in the main memory module (blk_mem_gen_v8_3_5) which is
// declared/implemented further down in this file.
//*****************************************************************************
module blk_mem_gen_v8_3_5_output_stage
#(parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RST = 0,
parameter C_RSTRAM = 0,
parameter C_RST_PRIORITY = "CE",
parameter C_INIT_VAL = "0",
parameter C_HAS_EN = 0,
parameter C_HAS_REGCE = 0,
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_MEM_OUTPUT_REGS = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter NUM_STAGES = 1,
\tparameter C_EN_ECC_PIPE = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input RST,
input EN,
input REGCE,
input [C_DATA_WIDTH-1:0] DIN_I,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN_I,
input DBITERR_IN_I,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN_I,
input ECCPIPECE,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RST : Determines the presence of the RST port
// C_RSTRAM : Determines if special reset behavior is used
// C_RST_PRIORITY : Determines the priority between CE and SR
// C_INIT_VAL : Initialization value
// C_HAS_EN : Determines the presence of the EN port
// C_HAS_REGCE : Determines the presence of the REGCE port
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// NUM_STAGES : Determines the number of output stages
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// RST : Reset input to reset memory outputs to a user-defined
// reset state
// EN : Enable all read and write operations
// REGCE : Register Clock Enable to control each pipeline output
// register stages
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
// Fix for CR-509792
localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;
// Declare the pipeline registers
// (includes mem output reg, mux pipeline stages, and mux output reg)
reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;
reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;
reg [REG_STAGES-1:0] sbiterr_regs;
reg [REG_STAGES-1:0] dbiterr_regs;
reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL;
reg [C_DATA_WIDTH-1:0] init_val ;
//*********************************************
// Wire off optional inputs based on parameters
//*********************************************
wire en_i;
wire regce_i;
wire rst_i;
// Internal signals
reg [C_DATA_WIDTH-1:0] DIN;
reg [C_ADDRB_WIDTH-1:0] RDADDRECC_IN;
reg SBITERR_IN;
reg DBITERR_IN;
// Internal enable for output registers is tied to user EN or \'1\' depending
// on parameters
assign en_i = (C_HAS_EN==0 || EN);
// Internal register enable for output registers is tied to user REGCE, EN or
// \'1\' depending on parameters
// For V4 ECC, REGCE is always 1
// Virtex-4 ECC Not Yet Supported
assign regce_i = ((C_HAS_REGCE==1) && REGCE) ||
((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));
//Internal SRR is tied to user RST or \'0\' depending on parameters
assign rst_i = (C_HAS_RST==1) && RST;
//****************************************************
// Power on: load up the output registers and latches
//****************************************************
initial begin
if (!($sscanf(init_str, "%h", init_val))) begin
init_val = 0;
end
DOUT = init_val;
RDADDRECC = 0;
SBITERR = 1\'b0;
DBITERR = 1\'b0;
\tDIN = {(C_DATA_WIDTH){1\'b0}};
RDADDRECC_IN = 0;
SBITERR_IN = 0;
\tDBITERR_IN = 0;
\t// This will be one wider than need, but 0 is an error
out_regs = {(REG_STAGES+1){init_val}};
rdaddrecc_regs = 0;
sbiterr_regs = {(REG_STAGES+1){1\'b0}};
dbiterr_regs = {(REG_STAGES+1){1\'b0}};
end
//***********************************************
// NUM_STAGES = 0 (No output registers. RAM only)
//***********************************************
generate if (NUM_STAGES == 0) begin : zero_stages
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg
always @* begin
DIN = DIN_I;
\t SBITERR_IN = SBITERR_IN_I;
DBITERR_IN = DBITERR_IN_I;
RDADDRECC_IN = RDADDRECC_IN_I;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg
always @(posedge CLK) begin
if(ECCPIPECE == 1) begin
\t DIN <= #FLOP_DELAY DIN_I;
SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;
DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;
RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;
end
\tend
end
endgenerate
//***********************************************
// NUM_STAGES = 1
// (Mem Output Reg only or Mux Output Reg only)
//***********************************************
// Possible valid combinations:
// Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
// +-----------------------------------------+
// | C_RSTRAM_* | Reset Behavior |
// +----------------+------------------------+
// | 0 | Normal Behavior |
// +----------------+------------------------+
// | 1 | Special Behavior |
// +----------------+------------------------+
//
// Normal = REGCE gates reset, as in the case of all families except S3ADSP.
// Special = EN gates reset, as in the case of S3ADSP.
generate if (NUM_STAGES == 1 &&
(C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) ||
C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))
begin : one_stages_norm
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1\'b0;
DBITERR <= #FLOP_DELAY 1\'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY 1\'b0;
DBITERR <= #FLOP_DELAY 1\'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end //end Priority conditions
end //end RST Type conditions
end //end one_stages_norm generate statement
endgenerate
// Special Reset Behavior for S3ADSP
generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp"))
begin : one_stage_splbhv
always @(posedge CLK) begin
if (en_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
end else if (regce_i && !rst_i) begin
DOUT <= #FLOP_DELAY DIN;
end //Output signal assignments
end //end CLK
end //end one_stage_splbhv generate statement
endgenerate
//************************************************************
// NUM_STAGES > 1
// Mem Output Reg + Mux Output Reg
// or
// Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
// or
// Mux Pipeline Stages (>0) + Mux Output Reg
//*************************************************************
generate if (NUM_STAGES > 1) begin : multi_stage
//Asynchronous Reset
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1\'b0;
DBITERR <= #FLOP_DELAY 1\'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1\'b0;
DBITERR <= #FLOP_DELAY 1\'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end //end Priority conditions
// Shift the data through the output stages
if (en_i) begin
out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;
rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;
sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;
dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;
end
end //end CLK
end //end multi_stage generate statement
endgenerate
endmodule
module blk_mem_gen_v8_3_5_softecc_output_reg_stage
#(parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input [C_DATA_WIDTH-1:0] DIN,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
reg [C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
//*****************************************************************************
// Main Memory module
//
// This module is the top-level behavioral model and this implements the RAM
//*****************************************************************************
module blk_mem_gen_v8_3_5_mem_module
#(parameter C_CORENAME = "blk_mem_gen_v8_3_5",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter FLOP_DELAY = 100,
parameter C_DISABLE_WARN_BHV_COLL = 0,
\tparameter C_EN_ECC_PIPE = 0,
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input CLKA,
input RSTA,
input ENA,
input REGCEA,
input [C_WEA_WIDTH-1:0] WEA,
input [C_ADDRA_WIDTH-1:0] ADDRA,
input [C_WRITE_WIDTH_A-1:0] DINA,
output [C_READ_WIDTH_A-1:0] DOUTA,
input CLKB,
input RSTB,
input ENB,
input REGCEB,
input [C_WEB_WIDTH-1:0] WEB,
input [C_ADDRB_WIDTH-1:0] ADDRB,
input [C_WRITE_WIDTH_B-1:0] DINB,
output [C_READ_WIDTH_B-1:0] DOUTB,
input INJECTSBITERR,
input INJECTDBITERR,
input ECCPIPECE,
input SLEEP,
output SBITERR,
output DBITERR,
output [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
// Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v8_3_5" and it is
// only used by this module to print warning messages. It is neither passed
// down from blk_mem_gen_v8_3_5_xst.v nor present in the instantiation template
// coregen generates
//***************************************************************************
// constants for the core behavior
//***************************************************************************
// file handles for logging
//--------------------------------------------------
localparam ADDRFILE = 32\'h8000_0001; //stdout for addr out of range
localparam COLLFILE = 32\'h8000_0001; //stdout for coll detection
localparam ERRFILE = 32\'h8000_0001; //stdout for file I/O errors
// other constants
//--------------------------------------------------
localparam COLL_DELAY = 100; // 100 ps
// locally derived parameters to determine memory shape
//-----------------------------------------------------
localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0)))));
localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?
C_WRITE_WIDTH_A : C_READ_WIDTH_A;
localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?
C_WRITE_WIDTH_B : C_READ_WIDTH_B;
localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?
MIN_WIDTH_A : MIN_WIDTH_B;
localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?
C_WRITE_DEPTH_A : C_READ_DEPTH_A;
localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?
C_WRITE_DEPTH_B : C_READ_DEPTH_B;
localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?
MAX_DEPTH_A : MAX_DEPTH_B;
// locally derived parameters to assist memory access
//----------------------------------------------------
// Calculate the width ratios of each port with respect to the narrowest
// port
localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;
localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH;
localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;
localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH;
// To modify the LSBs of the \'wider\' data to the actual
// address value
//----------------------------------------------------
localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A;
localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A;
localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B;
localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B;
// If byte writes aren\'t being used, make sure BYTE_SIZE is not
// wider than the memory elements to avoid compilation warnings
localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;
// The memory
reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1];
reg [MIN_WIDTH-1:0] temp_mem_array [0:MAX_DEPTH-1];
reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;
// ECC error arrays
reg sbiterr_arr [0:MAX_DEPTH-1];
reg dbiterr_arr [0:MAX_DEPTH-1];
reg softecc_sbiterr_arr [0:MAX_DEPTH-1];
reg softecc_dbiterr_arr [0:MAX_DEPTH-1];
// Memory output \'latches\'
reg [C_READ_WIDTH_A-1:0] memory_out_a;
reg [C_READ_WIDTH_B-1:0] memory_out_b;
// ECC error inputs and outputs from output_stage module:
reg sbiterr_in;
wire sbiterr_sdp;
reg dbiterr_in;
wire dbiterr_sdp;
wire [C_READ_WIDTH_B-1:0] dout_i;
wire dbiterr_i;
wire sbiterr_i;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp;
// Reset values
reg [C_READ_WIDTH_A-1:0] inita_val;
reg [C_READ_WIDTH_B-1:0] initb_val;
// Collision detect
reg is_collision;
reg is_collision_a, is_collision_delay_a;
reg is_collision_b, is_collision_delay_b;
// Temporary variables for initialization
//---------------------------------------
integer status;
integer initfile;
integer meminitfile;
// data input buffer
reg [C_WRITE_WIDTH_A-1:0] mif_data;
reg [C_WRITE_WIDTH_A-1:0] mem_data;
// string values in hex
reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL;
reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL;
reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA;
// initialization filename
reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME;
reg [1023*8-1:0] mem_init_file_str = C_INIT_FILE;
//Constants used to calculate the effective address widths for each of the
//four ports.
integer cnt = 1;
integer write_addr_a_width, read_addr_a_width;
integer write_addr_b_width, read_addr_b_width;
localparam C_FAMILY_LOCALPARAM = (C_FAMILY=="zynquplus"?"virtex7":(C_FAMILY=="kintexuplus"?"virtex7":(C_FAMILY=="virtexuplus"?"virtex7":(C_FAMILY=="virtexu"?"virtex7":(C_FAMILY=="kintexu" ? "virtex7":(C_FAMILY=="virtex7" ? "virtex7" : (C_FAMILY=="virtex7l" ? "virtex7" : (C_FAMILY=="qvirtex7" ? "virtex7" : (C_FAMILY=="qvirtex7l" ? "virtex7" : (C_FAMILY=="kintex7" ? "virtex7" : (C_FAMILY=="kintex7l" ? "virtex7" : (C_FAMILY=="qkintex7" ? "virtex7" : (C_FAMILY=="qkintex7l" ? "virtex7" : (C_FAMILY=="artix7" ? "virtex7" : (C_FAMILY=="artix7l" ? "virtex7" : (C_FAMILY=="qartix7" ? "virtex7" : (C_FAMILY=="qartix7l" ? "virtex7" : (C_FAMILY=="aartix7" ? "virtex7" : (C_FAMILY=="zynq" ? "virtex7" : (C_FAMILY=="azynq" ? "virtex7" : (C_FAMILY=="qzynq" ? "virtex7" : C_FAMILY)))))))))))))))))))));
// Internal configuration parameters
//---------------------------------------------
localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);
localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4);
localparam HAS_A_WRITE = (!IS_ROM);
localparam HAS_B_WRITE = (C_MEM_TYPE==2);
localparam HAS_A_READ = (C_MEM_TYPE!=1);
localparam HAS_B_READ = (!SINGLE_PORT);
localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE);
// Calculate the mux pipeline register stages for Port A and Port B
//------------------------------------------------------------------
localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?
C_MUX_PIPELINE_STAGES : 0;
localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?
C_MUX_PIPELINE_STAGES : 0;
// Calculate total number of register stages in the core
// -----------------------------------------------------
localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);
localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);
wire ena_i;
wire enb_i;
wire reseta_i;
wire resetb_i;
wire [C_WEA_WIDTH-1:0] wea_i;
wire [C_WEB_WIDTH-1:0] web_i;
wire rea_i;
wire reb_i;
wire rsta_outp_stage;
wire rstb_outp_stage;
// ECC SBITERR/DBITERR Outputs
// The ECC Behavior is modeled by the behavioral models only for Virtex-6.
// For Virtex-5, these outputs will be tied to 0.
assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;
assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;
assign RDADDRECC = (((C_FAMILY_LOCALPARAM == "virtex7") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;
// This effectively wires off optional inputs
assign ena_i = (C_HAS_ENA==0) || ENA;
assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;
// To match RTL : In RTL, write enable of the primitive is tied to all 1\'s and
// the enable of the primitive is ANDing of wea(0) and ena. so eventually, the
// write operation depends on both enable and write enable. So, the below code
// which is actually doing the write operation only on enable ignoring the wea
// is removed to be in consistent with RTL.
// To Fix CR855535 (The fix to this CR is reverted to match RTL)
//assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? \'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : \'b0;
assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : \'b0;
assign web_i = (HAS_B_WRITE && enb_i) ? WEB : \'b0;
assign rea_i = (HAS_A_READ) ? ena_i : \'b0;
assign reb_i = (HAS_B_READ) ? enb_i : \'b0;
// These signals reset the memory latches
assign reseta_i =
((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||
(C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));
assign resetb_i =
((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||
(C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));
// Tasks to access the memory
//---------------------------
//**************
// write_a
//**************
task write_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg [C_WEA_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_A-1:0] data,
input inj_sbiterr,
input inj_dbiterr);
reg [C_WRITE_WIDTH_A-1:0] current_contents;
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_A_DIV);
if (address >= C_WRITE_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEA) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_A + i];
end
end
// Apply incoming bytes
if (C_WEA_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Insert double bit errors:
if (C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1\'b1) begin
// Modified for Implementing CR_859399
current_contents[0] = !(current_contents[30]);
current_contents[1] = !(current_contents[62]);
/*current_contents[0] = !(current_contents[0]);
current_contents[1] = !(current_contents[1]);*/
end
end
// Insert softecc double bit errors:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1\'b1) begin
doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];
doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];
doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];
current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];
end
end
// Write data to memory
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_A] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_A + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
// Store the address at which error is injected:
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1\'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1\'b1 && inj_dbiterr != 1\'b1))
begin
sbiterr_arr[addr] = 1;
end else begin
sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1\'b1) begin
dbiterr_arr[addr] = 1;
end else begin
dbiterr_arr[addr] = 0;
end
end
// Store the address at which softecc error is injected:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1\'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1\'b1 && inj_dbiterr != 1\'b1))
begin
softecc_sbiterr_arr[addr] = 1;
end else begin
softecc_sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1\'b1) begin
softecc_dbiterr_arr[addr] = 1;
end else begin
softecc_dbiterr_arr[addr] = 0;
end
end
end
end
endtask
//**************
// write_b
//**************
task write_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg [C_WEB_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_B-1:0] data);
reg [C_WRITE_WIDTH_B-1:0] current_contents;
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_B_DIV);
if (address >= C_WRITE_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEB) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_B + i];
end
end
// Apply incoming bytes
if (C_WEB_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Write data to memory
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_B] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_B + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
end
end
endtask
//**************
// read_a
//**************
task read_a
'b' (input reg [C_ADDRA_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_a <= #FLOP_DELAY inita_val;
end else begin
// Shift the address by the ratio
address = (addr/READ_ADDR_A_DIV);
if (address >= C_READ_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Read",
C_CORENAME, addr);
end
memory_out_a <= #FLOP_DELAY \'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_A==1) begin
memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];
end else begin
// Increment through the \'partial\' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin
memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];
end
end //end READ_WIDTH_RATIO_A==1 loop
end //end valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// read_b
//**************
task read_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_b <= #FLOP_DELAY initb_val;
sbiterr_in <= #FLOP_DELAY 1\'b0;
dbiterr_in <= #FLOP_DELAY 1\'b0;
rdaddrecc_in <= #FLOP_DELAY 0;
end else begin
// Shift the address
address = (addr/READ_ADDR_B_DIV);
if (address >= C_READ_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Read",
C_CORENAME, addr);
end
memory_out_b <= #FLOP_DELAY \'bX;
sbiterr_in <= #FLOP_DELAY 1\'bX;
dbiterr_in <= #FLOP_DELAY 1\'bX;
rdaddrecc_in <= #FLOP_DELAY \'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_B==1) begin
memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];
end else begin
// Increment through the \'partial\' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin
memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];
end
end
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1\'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1\'b0;
end
if (dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1\'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1\'b0;
end
end else if (C_USE_SOFTECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (softecc_sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1\'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1\'b0;
end
if (softecc_dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1\'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1\'b0;
end
end else begin
rdaddrecc_in <= #FLOP_DELAY 0;
dbiterr_in <= #FLOP_DELAY 1\'b0;
sbiterr_in <= #FLOP_DELAY 1\'b0;
end //end SOFTECC Loop
end //end Valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// reset_a
//**************
task reset_a (input reg reset);
begin
if (reset) memory_out_a <= #FLOP_DELAY inita_val;
end
endtask
//**************
// reset_b
//**************
task reset_b (input reg reset);
begin
if (reset) memory_out_b <= #FLOP_DELAY initb_val;
end
endtask
//**************
// init_memory
//**************
task init_memory;
integer i, j, addr_step;
integer status;
reg [C_WRITE_WIDTH_A-1:0] default_data;
begin
default_data = 0;
//Display output message indicating that the behavioral model is being
//initialized
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator module loading initial data...");
// Convert the default to hex
if (C_USE_DEFAULT_DATA) begin
if (default_data_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME);
$finish;
end else begin
status = $sscanf(default_data_str, "%h", default_data);
if (status == 0) begin
$fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read",
"from C_DEFAULT_DATA: %0s"},
C_CORENAME, C_DEFAULT_DATA);
$finish;
end
end
end
// Step by WRITE_ADDR_A_DIV through the memory via the
// Port A write interface to hit every location once
addr_step = WRITE_ADDR_A_DIV;
// \'write\' to every location with default (or 0)
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
write_a(i, {C_WEA_WIDTH{1\'b1}}, default_data, 1\'b0, 1\'b0);
end
// Get specialized data from the MIF file
if (C_LOAD_INIT_FILE) begin
if (init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!",
C_CORENAME);
$finish;
end else begin
initfile = $fopen(init_file_str, "r");
if (initfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE_NAME: %0s!"},
C_CORENAME, init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
status = $fscanf(initfile, "%b", mif_data);
if (status > 0) begin
write_a(i, {C_WEA_WIDTH{1\'b1}}, mif_data, 1\'b0, 1\'b0);
end
end
$fclose(initfile);
end //initfile
end //init_file_str
end //C_LOAD_INIT_FILE
if (C_USE_BRAM_BLOCK) begin
// Get specialized data from the MIF file
if (C_INIT_FILE != "NONE") begin
if (mem_init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE is empty!",
C_CORENAME);
$finish;
end else begin
meminitfile = $fopen(mem_init_file_str, "r");
if (meminitfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE: %0s!"},
C_CORENAME, mem_init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
$readmemh(mem_init_file_str, memory );
for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin
end
$fclose(meminitfile);
end //meminitfile
end //mem_init_file_str
end //C_INIT_FILE
end //C_USE_BRAM_BLOCK
//Display output message indicating that the behavioral model is done
//initializing
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE)
$display(" Block Memory Generator data initialization complete.");
end
endtask
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//*******************
// collision_check
//*******************
function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,
input integer iswrite_a,
input reg [C_ADDRB_WIDTH-1:0] addr_b,
input integer iswrite_b);
reg c_aw_bw, c_aw_br, c_ar_bw;
integer scaled_addra_to_waddrb_width;
integer scaled_addrb_to_waddrb_width;
integer scaled_addra_to_waddra_width;
integer scaled_addrb_to_waddra_width;
integer scaled_addra_to_raddrb_width;
integer scaled_addrb_to_raddrb_width;
integer scaled_addra_to_raddra_width;
integer scaled_addrb_to_raddra_width;
begin
c_aw_bw = 0;
c_aw_br = 0;
c_ar_bw = 0;
//If write_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_b_width. Once both are scaled to
//write_addr_b_width, compare.
scaled_addra_to_waddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_b_width));
scaled_addrb_to_waddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_b_width));
//If write_addr_a_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_a_width. Once both are scaled to
//write_addr_a_width, compare.
scaled_addra_to_waddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_a_width));
scaled_addrb_to_waddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_a_width));
//If read_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_b_width. Once both are scaled to
//read_addr_b_width, compare.
scaled_addra_to_raddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_b_width));
scaled_addrb_to_raddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_b_width));
//If read_addr_a_width is smaller, scale both addresses to that width for
//comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_a_width. Once both are scaled to
//read_addr_a_width, compare.
scaled_addra_to_raddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_a_width));
scaled_addrb_to_raddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_a_width));
//Look for a write-write collision. In order for a write-write
//collision to exist, both ports must have a write transaction.
if (iswrite_a && iswrite_b) begin
if (write_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end //width
end //iswrite_a and iswrite_b
//If the B port is reading (which means it is enabled - so could be
//a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
//to asymmetric write/read ports.
if (iswrite_a) begin
if (write_addr_a_width > read_addr_b_width) begin
if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end //width
end //iswrite_a
//If the A port is reading (which means it is enabled - so could be
// a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
// to asymmetric write/read ports.
if (iswrite_b) begin
if (read_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end else begin
if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end //width
end //iswrite_b
collision_check = c_aw_bw | c_aw_br | c_ar_bw;
end
endfunction
//*******************************
// power on values
//*******************************
initial begin
// Load up the memory
init_memory;
// Load up the output registers and latches
if ($sscanf(inita_str, "%h", inita_val)) begin
memory_out_a = inita_val;
end else begin
memory_out_a = 0;
end
if ($sscanf(initb_str, "%h", initb_val)) begin
memory_out_b = initb_val;
end else begin
memory_out_b = 0;
end
sbiterr_in = 1\'b0;
dbiterr_in = 1\'b0;
rdaddrecc_in = 0;
// Determine the effective address widths for each of the 4 ports
write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);
write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);
$display("Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.");
end
//***************************************************************************
// These are the main blocks which schedule read and write operations
// Note that the reset priority feature at the latch stage is only supported
// for Spartan-6. For other families, the default priority at the latch stage
// is "CE"
//***************************************************************************
// Synchronous clocks: schedule port operations with respect to
// both write operating modes
generate
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_wf_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_rf_wf
always @(posedge CLKA) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_wf_rf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_rf_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_wf_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_rf_nc
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_nc_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_nc_rf
always @(posedge CLKA) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_nc_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK) begin: com_clk_sched_default
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
endgenerate
// Asynchronous clocks: port operation is independent
generate
if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
end
end
endgenerate
generate
if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf
always @(posedge CLKB) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
endgenerate
//***************************************************************
// Instantiate the variable depth output register stage module
//***************************************************************
// Port A
assign rsta_outp_stage = RSTA & (~SLEEP);
blk_mem_gen_v8_3_5_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTA),
.C_RSTRAM (C_RSTRAM_A),
.C_RST_PRIORITY (C_RST_PRIORITY_A),
.C_INIT_VAL (C_INITA_VAL),
.C_HAS_EN (C_HAS_ENA),
.C_HAS_REGCE (C_HAS_REGCEA),
.C_DATA_WIDTH (C_READ_WIDTH_A),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_A),
\t .C_EN_ECC_PIPE (0),
.FLOP_DELAY (FLOP_DELAY))
reg_a
(.CLK (CLKA),
.RST (rsta_outp_stage),//(RSTA),
.EN (ENA),
.REGCE (REGCEA),
.DIN_I (memory_out_a),
.DOUT (DOUTA),
.SBITERR_IN_I (1\'b0),
.DBITERR_IN_I (1\'b0),
.SBITERR (),
.DBITERR (),
.RDADDRECC_IN_I ({C_ADDRB_WIDTH{1\'b0}}),
\t\t .ECCPIPECE (1\'b0),
.RDADDRECC ()
);
assign rstb_outp_stage = RSTB & (~SLEEP);
// Port B
blk_mem_gen_v8_3_5_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTB),
.C_RSTRAM (C_RSTRAM_B),
.C_RST_PRIORITY (C_RST_PRIORITY_B),
.C_INIT_VAL (C_INITB_VAL),
.C_HAS_EN (C_HAS_ENB),
.C_HAS_REGCE (C_HAS_REGCEB),
.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_B),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.FLOP_DELAY (FLOP_DELAY))
reg_b
(.CLK (CLKB),
.RST (rstb_outp_stage),//(RSTB),
.EN (ENB),
.REGCE (REGCEB),
.DIN_I (memory_out_b),
.DOUT (dout_i),
.SBITERR_IN_I (sbiterr_in),
.DBITERR_IN_I (dbiterr_in),
.SBITERR (sbiterr_i),
.DBITERR (dbiterr_i),
.RDADDRECC_IN_I (rdaddrecc_in),
.ECCPIPECE (ECCPIPECE),
.RDADDRECC (rdaddrecc_i)
);
//***************************************************************
// Instantiate the Input and Output register stages
//***************************************************************
blk_mem_gen_v8_3_5_softecc_output_reg_stage
#(.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.FLOP_DELAY (FLOP_DELAY))
has_softecc_output_reg_stage
(.CLK (CLKB),
.DIN (dout_i),
.DOUT (DOUTB),
.SBITERR_IN (sbiterr_i),
.DBITERR_IN (dbiterr_i),
.SBITERR (sbiterr_sdp),
.DBITERR (dbiterr_sdp),
.RDADDRECC_IN (rdaddrecc_i),
.RDADDRECC (rdaddrecc_sdp)
);
//****************************************************
// Synchronous collision checks
//****************************************************
// CR 780544 : To make verilog model\'s collison warnings in consistant with
// vhdl model, the non-blocking assignments are replaced with blocking
// assignments.
generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision = 0;
end
end else begin
is_collision = 0;
end
// If the write port is in READ_FIRST mode, there is no collision
if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin
is_collision = 0;
end
if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin
is_collision = 0;
end
// Only flag if one of the accesses is a write
if (is_collision && (wea_i || web_i)) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B %0s address: %0h\
",
wea_i ? "write" : "read", ADDRA,
web_i ? "write" : "read", ADDRB);
end
end
//****************************************************
// Asynchronous collision checks
//****************************************************
end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll
// Delay A and B addresses in order to mimic setup/hold times
wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA;
wire [0:0] #COLL_DELAY wea_delay = wea_i;
wire #COLL_DELAY ena_delay = ena_i;
wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB;
wire [0:0] #COLL_DELAY web_delay = web_i;
wire #COLL_DELAY enb_delay = enb_i;
// Do the checks w/rt A
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_a = 0;
end
end else begin
is_collision_a = 0;
end
if (ena_i && enb_delay) begin
if(wea_i || web_delay) begin
is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,
web_delay);
end else begin
is_collision_delay_a = 0;
end
end else begin
is_collision_delay_a = 0;
end
// Only flag if B access is a write
if (is_collision_a && web_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\
",
wea_i ? "write" : "read", ADDRA, ADDRB);
end else if (is_collision_delay_a && web_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\
",
wea_i ? "write" : "read", ADDRA, addrb_delay);
end
end
// Do the checks w/rt B
always @(posedge CLKB) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_b = 0;
end
end else begin
is_collision_b = 0;
end
if (ena_delay && enb_i) begin
if (wea_delay || web_i) begin
is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,
web_i);
end else begin
is_collision_delay_b = 0;
end
end else begin
is_collision_delay_b = 0;
end
// Only flag if A access is a write
if (is_collision_b && wea_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\
",
ADDRA, web_i ? "write" : "read", ADDRB);
end else if (is_collision_delay_b && wea_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\
",
addra_delay, web_i ? "write" : "read", ADDRB);
end
end
end
endgenerate
endmodule
//*****************************************************************************
// Top module wraps Input register and Memory module
//
// This module is the top-level behavioral model and this implements the memory
// module and the input registers
//*****************************************************************************
module blk_mem_gen_v8_3_5
#(parameter C_CORENAME = "blk_mem_gen_v8_3_5",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_ELABORATION_DIR = "",
parameter C_INTERFACE_TYPE = 0,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_CTRL_ECC_ALGO = "NONE",
parameter C_ENABLE_32BIT_ADDRESS = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
//parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
\tparameter C_EN_ECC_PIPE = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter C_DISABLE_WARN_BHV_COLL = 0,
\tparameter C_EN_SLEEP_PIN = 0,
parameter C_USE_URAM = 0,
parameter C_EN_RDADDRA_CHG = 0,
parameter C_EN_RDADDRB_CHG = 0,
parameter C_EN_DEEPSLEEP_PIN = 0,
parameter C_EN_SHUTDOWN_PIN = 0,
\tparameter C_EN_SAFETY_CKT = 0,
\tparameter C_COUNT_36K_BRAM = "",
\tparameter C_COUNT_18K_BRAM = "",
\tparameter C_EST_POWER_SUMMARY = "",
\tparameter C_DISABLE_WARN_BHV_RANGE = 0
\t
)
(input clka,
input rsta,
input ena,
input regcea,
input [C_WEA_WIDTH-1:0] wea,
input [C_ADDRA_WIDTH-1:0] addra,
input [C_WRITE_WIDTH_A-1:0] dina,
output [C_READ_WIDTH_A-1:0] douta,
input clkb,
input rstb,
input enb,
input regceb,
input [C_WEB_WIDTH-1:0] web,
input [C_ADDRB_WIDTH-1:0] addrb,
input [C_WRITE_WIDTH_B-1:0] dinb,
output [C_READ_WIDTH_B-1:0] doutb,
input injectsbiterr,
input injectdbiterr,
output sbiterr,
output dbiterr,
output [C_ADDRB_WIDTH-1:0] rdaddrecc,
input eccpipece,
input sleep,
input deepsleep,
input shutdown,
output rsta_busy,
output rstb_busy,
//AXI BMG Input and Output Port Declarations
//AXI Global Signals
input s_aclk,
input s_aresetn,
//AXI Full/lite slave write (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [31:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input s_axi_awvalid,
output s_axi_awready,
input [C_WRITE_WIDTH_A-1:0] s_axi_wdata,
input [C_WEA_WIDTH-1:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
//AXI Full/lite slave read (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [31:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_WRITE_WIDTH_B-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
input s_axi_rready,
//AXI Full/lite sideband signals
input s_axi_injectsbiterr,
input s_axi_injectdbiterr,
output s_axi_sbiterr,
output s_axi_dbiterr,
output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_HAS_SOFTECC_INPUT_REGS_A :
// C_HAS_SOFTECC_OUTPUT_REGS_B :
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
wire SBITERR;
wire DBITERR;
wire S_AXI_AWREADY;
wire S_AXI_WREADY;
wire S_AXI_BVALID;
wire S_AXI_ARREADY;
wire S_AXI_RLAST;
wire S_AXI_RVALID;
wire S_AXI_SBITERR;
wire S_AXI_DBITERR;
wire [C_WEA_WIDTH-1:0] WEA = wea;
wire [C_ADDRA_WIDTH-1:0] ADDRA = addra;
wire [C_WRITE_WIDTH_A-1:0] DINA = dina;
wire [C_READ_WIDTH_A-1:0] DOUTA;
wire [C_WEB_WIDTH-1:0] WEB = web;
wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb;
wire [C_WRITE_WIDTH_B-1:0] DINB = dinb;
wire [C_READ_WIDTH_B-1:0] DOUTB;
wire [C_ADDRB_WIDTH-1:0] RDADDRECC;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid;
wire [31:0] S_AXI_AWADDR = s_axi_awaddr;
wire [7:0] S_AXI_AWLEN = s_axi_awlen;
wire [2:0] S_AXI_AWSIZE = s_axi_awsize;
wire [1:0] S_AXI_AWBURST = s_axi_awburst;
wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata;
wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [1:0] S_AXI_BRESP;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid;
wire [31:0] S_AXI_ARADDR = s_axi_araddr;
wire [7:0] S_AXI_ARLEN = s_axi_arlen;
wire [2:0] S_AXI_ARSIZE = s_axi_arsize;
wire [1:0] S_AXI_ARBURST = s_axi_arburst;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA;
wire [1:0] S_AXI_RRESP;
wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC;
// Added to fix the simulation warning #CR731605
wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0;
wire ECCPIPECE;
wire SLEEP;
reg RSTA_BUSY = 0;
reg RSTB_BUSY = 0;
// Declaration of internal signals to avoid warnings #927399
wire CLKA;
wire RSTA;
wire ENA;
wire REGCEA;
wire CLKB;
wire RSTB;
wire ENB;
wire REGCEB;
wire INJECTSBITERR;
wire INJECTDBITERR;
wire S_ACLK;
wire S_ARESETN;
wire S_AXI_AWVALID;
wire S_AXI_WLAST;
wire S_AXI_WVALID;
wire S_AXI_BREADY;
wire S_AXI_ARVALID;
wire S_AXI_RREADY;
wire S_AXI_INJECTSBITERR;
wire S_AXI_INJECTDBITERR;
assign CLKA = clka;
assign RSTA = rsta;
assign ENA = ena;
assign REGCEA = regcea;
assign CLKB = clkb;
assign RSTB = rstb;
assign ENB = enb;
assign REGCEB = regceb;
assign INJECTSBITERR = injectsbiterr;
assign INJECTDBITERR = injectdbiterr;
assign ECCPIPECE = eccpipece;
assign SLEEP = sleep;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr;
assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr;
assign s_axi_sbiterr = S_AXI_SBITERR;
assign s_axi_dbiterr = S_AXI_DBITERR;
assign rsta_busy = RSTA_BUSY;
assign rstb_busy = RSTB_BUSY;
assign doutb = DOUTB;
assign douta = DOUTA;
assign rdaddrecc = RDADDRECC;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_rdaddrecc = S_AXI_RDADDRECC;
localparam FLOP_DELAY = 100; // 100 ps
reg injectsbiterr_in;
reg injectdbiterr_in;
reg rsta_in;
reg ena_in;
reg regcea_in;
reg [C_WEA_WIDTH-1:0] wea_in;
reg [C_ADDRA_WIDTH-1:0] addra_in;
reg [C_WRITE_WIDTH_A-1:0] dina_in;
wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;
wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;
wire s_axi_wr_en_c;
wire s_axi_rd_en_c;
wire s_aresetn_a_c;
wire [7:0] s_axi_arlen_c ;
wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;
wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;
wire [1:0] s_axi_rresp_c;
wire s_axi_rlast_c;
wire s_axi_rvalid_c;
wire s_axi_rready_c;
wire regceb_c;
localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;
wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;
wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;
// Safety logic related signals
reg [4:0] RSTA_SHFT_REG = 0;
reg POR_A = 0;
reg [4:0] RSTB_SHFT_REG = 0;
reg POR_B = 0;
reg ENA_dly = 0;
reg ENA_dly_D = 0;
reg ENB_dly = 0;
reg ENB_dly_D = 0;
wire RSTA_I_SAFE;
wire RSTB_I_SAFE;
wire ENA_I_SAFE;
wire ENB_I_SAFE;
reg ram_rstram_a_busy = 0;
reg ram_rstreg_a_busy = 0;
reg ram_rstram_b_busy = 0;
reg ram_rstreg_b_busy = 0;
reg ENA_dly_reg = 0;
reg ENB_dly_reg = 0;
reg ENA_dly_reg'b'_D = 0;
reg ENB_dly_reg_D = 0;
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//**************
// log2int
//**************
function integer log2int (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
\t\t cnt= data_value;
for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin
width = width + 1;
end //loop
log2int = width;
end //log2int
endfunction
//**************************************************************************
// FUNCTION : divroundup
// Returns the ceiling value of the division
// Data_value - the quantity to be divided, dividend
// Divisor - the value to divide the data_value by
//**************************************************************************
function integer divroundup (input integer data_value,input integer divisor);
integer div;
begin
div = data_value/divisor;
if ((data_value % divisor) != 0) begin
div = div+1;
end //if
divroundup = div;
end //if
endfunction
localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);
localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB;
//Data Width Number of LSB address bits to be discarded
//1 to 16 1
//17 to 32 2
//33 to 64 3
//65 to 128 4
//129 to 256 5
//257 to 512 6
//513 to 1024 7
// The following two constants determine this.
localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);
localparam C_AXI_OS_WR = 2;
//***********************************************
// INPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage
always @* begin
injectsbiterr_in = INJECTSBITERR;
injectdbiterr_in = INJECTDBITERR;
rsta_in = RSTA;
ena_in = ENA;
regcea_in = REGCEA;
wea_in = WEA;
addra_in = ADDRA;
dina_in = DINA;
end //end always
end //end no_softecc_input_reg_stage
endgenerate
generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage
always @(posedge CLKA) begin
injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;
injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;
rsta_in <= #FLOP_DELAY RSTA;
ena_in <= #FLOP_DELAY ENA;
regcea_in <= #FLOP_DELAY REGCEA;
wea_in <= #FLOP_DELAY WEA;
addra_in <= #FLOP_DELAY ADDRA;
dina_in <= #FLOP_DELAY DINA;
end //end always
end //end input_reg_stages generate statement
endgenerate
//**************************************************************************
// NO SAFETY LOGIC
//**************************************************************************
generate
if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN
assign ENA_I_SAFE = ena_in;
assign ENB_I_SAFE = ENB;
assign RSTA_I_SAFE = rsta_in;
assign RSTB_I_SAFE = RSTB;
end
endgenerate
//***************************************************************************
// SAFETY LOGIC
// Power-ON Reset Generation
//***************************************************************************
generate
if (C_EN_SAFETY_CKT == 1) begin
always @(posedge clka) RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1\'b1} ;
always @(posedge clka) POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];
always @(posedge clkb) RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1\'b1} ;
always @(posedge clkb) POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0];
assign RSTA_I_SAFE = rsta_in | POR_A;
assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1\'b0 : (RSTB | POR_B);
end
endgenerate
//-----------------------------------------------------------------------------
// -- RSTA/B_BUSY Generation
//-----------------------------------------------------------------------------
generate
if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG
always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;
always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG
always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;
always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;
end
endgenerate
generate
if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY
always @(*) RSTB_BUSY = 1\'b0;
end
endgenerate
generate
if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_NO_REG
always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;
always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG
always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;
always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;
end
endgenerate
//-----------------------------------------------------------------------------
// -- ENA/ENB Generation
//-----------------------------------------------------------------------------
generate
if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG
always @(posedge clka) begin
ENA_dly <= #FLOP_DELAY RSTA_I_SAFE;
ENA_dly_D <= #FLOP_DELAY ENA_dly;
end
assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1\'b1 : (ENA_dly_D | ena_in);
end
endgenerate
generate
if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG
always @(posedge clka) begin
ENA_dly_reg <= #FLOP_DELAY RSTA_I_SAFE;
ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;
end
assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1\'b1 : (ENA_dly_reg_D | ena_in);
end
endgenerate
generate
if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB
assign ENB_I_SAFE = 1\'b0;
end
endgenerate
generate
if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG
always @(posedge clkb) begin : PROC_ENB_GEN
ENB_dly <= #FLOP_DELAY RSTB_I_SAFE;
ENB_dly_D <= #FLOP_DELAY ENB_dly;
end
assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1\'b1 : (ENB_dly_D | ENB);
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG
always @(posedge clkb) begin : PROC_ENB_GEN
ENB_dly_reg <= #FLOP_DELAY RSTB_I_SAFE;
ENB_dly_reg_D <= #FLOP_DELAY ENB_dly_reg;
end
assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1\'b1 : (ENB_dly_reg_D | ENB);
end
endgenerate
generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module
blk_mem_gen_v8_3_5_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_ALGORITHM (C_ALGORITHM),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_5_inst
(.CLKA (CLKA),
.RSTA (RSTA_I_SAFE),//(rsta_in),
.ENA (ENA_I_SAFE),//(ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB_I_SAFE),//(RSTB),
.ENB (ENB_I_SAFE),//(ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module
localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);
localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);
localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
// localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);
// localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);
localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB;
localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB;
// Data Width Number of LSB address bits to be discarded
// 1 to 16 1
// 17 to 32 2
// 33 to 64 3
// 65 to 128 4
// 129 to 256 5
// 257 to 512 6
// 513 to 1024 7
// The following two constants determine this.
localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;
localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;
wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;
wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;
wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;
assign msb_zero_i = 0;
assign lsb_zero_i = 0;
assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i};
blk_mem_gen_v8_3_5_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_5_inst
(.CLKA (CLKA),
.RSTA (RSTA_I_SAFE),//(rsta_in),
.ENA (ENA_I_SAFE),//(ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB_I_SAFE),//(RSTB),
.ENB (ENB_I_SAFE),//(ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (rdaddrecc_i)
);
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RLAST = s_axi_rlast_c;
assign S_AXI_RVALID = s_axi_rvalid_c;
assign S_AXI_RID = s_axi_rid_c;
assign S_AXI_RRESP = s_axi_rresp_c;
assign s_axi_rready_c = S_AXI_RREADY;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb
assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb
assign regceb_c = REGCEB;
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd
blk_mem_axi_regs_fwd_v8_3
#(.C_DATA_WIDTH (C_AXI_PAYLOAD))
axi_regs_inst (
.ACLK (S_ACLK),
.ARESET (s_aresetn_a_c),
.S_VALID (s_axi_rvalid_c),
.S_READY (s_axi_rready_c),
.S_PAYLOAD_DATA (s_axi_payload_c),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY),
.M_PAYLOAD_DATA (m_axi_payload_c)
);
end
endgenerate
generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module
assign s_aresetn_a_c = !S_ARESETN;
assign S_AXI_BRESP = 2\'b00;
assign s_axi_rresp_c = 2\'b00;
assign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8\'h0;
blk_mem_axi_write_wrapper_beh_v8_3
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A),
.C_AXI_OS_WR (C_AXI_OS_WR))
axi_wr_fsm (
// AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
// AXI Full/Lite Slave Write interface
.S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
.S_AXI_BID (S_AXI_BID),
// Signals for BRAM interfac(
.S_AXI_AWADDR_OUT (s_axi_awaddr_out_c),
.S_AXI_WR_EN (s_axi_wr_en_c)
);
blk_mem_axi_read_wrapper_beh_v8_3
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE\t\t (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_PIPELINE_STAGES (1),
.C_AXI_ARADDR_WIDTH\t ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_rd_sm(
//AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
//AXI Full/Lite Read Side
.S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_ARLEN (s_axi_arlen_c),
.S_AXI_ARSIZE (S_AXI_ARSIZE),
.S_AXI_ARBURST (S_AXI_ARBURST),
.S_AXI_ARVALID (S_AXI_ARVALID),
.S_AXI_ARREADY (S_AXI_ARREADY),
.S_AXI_RLAST (s_axi_rlast_c),
.S_AXI_RVALID (s_axi_rvalid_c),
.S_AXI_RREADY (s_axi_rready_c),
.S_AXI_ARID (S_AXI_ARID),
.S_AXI_RID (s_axi_rid_c),
//AXI Full/Lite Read FSM Outputs
.S_AXI_ARADDR_OUT (s_axi_araddr_out_c),
.S_AXI_RD_EN (s_axi_rd_en_c)
);
blk_mem_gen_v8_3_5_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (1),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (1),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (1),
.C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_BYTE_WEB (1),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (0),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (0),
.C_HAS_MUX_OUTPUT_REGS_B (0),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
\t.C_EN_ECC_PIPE (0),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_5_inst
(.CLKA (S_ACLK),
.RSTA (s_aresetn_a_c),
.ENA (s_axi_wr_en_c),
.REGCEA (regcea_in),
.WEA (S_AXI_WSTRB),
.ADDRA (s_axi_awaddr_out_c),
.DINA (S_AXI_WDATA),
.DOUTA (DOUTA),
.CLKB (S_ACLK),
.RSTB (s_aresetn_a_c),
.ENB (s_axi_rd_en_c),
.REGCEB (regceb_c),
.WEB (WEB_parameterized),
.ADDRB (s_axi_araddr_out_c),
.DINB (DINB),
.DOUTB (s_axi_rdata_c),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.ECCPIPECE (1\'b0),
.SLEEP (1\'b0),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10.03.2017 10:36:26
// Design Name:
// Module Name: main
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module var_clock(input clkin, output reg clkout = 0);
parameter load = 32'd2;
reg[31:0] count = 0;
always @(posedge clkin) begin
count <= (count == 0) ? load - 1 : count - 1;
clkout <= (count == 0) ? ~clkout : clkout;
end
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Tue Mar 28 02:26:33 2017
// Host : DESKTOP-B1QME94 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dds_compiler_0_stub.v
// Design : dds_compiler_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "dds_compiler_v6_0_13,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, s_axis_phase_tvalid,
s_axis_phase_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_phase_tvalid,s_axis_phase_tdata[23:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]" */;
input aclk;
input s_axis_phase_tvalid;
input [23:0]s_axis_phase_tdata;
output m_axis_data_tvalid;
output [15:0]m_axis_data_tdata;
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11.03.2017 20:05:08
// Design Name:
// Module Name: debounce
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module debounce(input clk, input btn, output out);
reg[1:0] ff = 0;
always @(posedge clk) ff <= {ff[0],btn};
assign out = ff[0] & ~ff[1];
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Tue Mar 28 05:22:50 2017
// Host : DESKTOP-B1QME94 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/sidxb/FPGA/ee2020/ee2020.runs/dds_compiler_0_synth_1/dds_compiler_0_stub.v
// Design : dds_compiler_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "dds_compiler_v6_0_13,Vivado 2016.4" *)
module dds_compiler_0(aclk, s_axis_phase_tvalid,
s_axis_phase_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_phase_tvalid,s_axis_phase_tdata[23:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]" */;
input aclk;
input s_axis_phase_tvalid;
input [23:0]s_axis_phase_tdata;
output m_axis_data_tvalid;
output [15:0]m_axis_data_tdata;
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10.03.1017 9:36:26
// Design Name:
// Module Name: main
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module myDAC(
input clk,
inout PS2Clk,
inout PS2Data,
input[15:0] sw,
output[7:0] JA,
output reg[3:0] vgaRed,
output reg[3:0] vgaGreen,
output reg[3:0] vgaBlue,
output reg Vsync,
output reg Hsync,
input RsRx,
input btnC,
input btnU,
input btnD,
input btnL,
input btnR,
output[15:0] led,
output[6:0] seg,
output[3:0] an,
output dp
);
localparam MAXVOLTAGE = 3300;
localparam MAXCHAN = 3;
localparam MAXAMP = 4095;
localparam MAXFREQ = 250000;
localparam MAXDUTY = 999;
wire clksamp;
reg clk50 = 0;
wire clkvga = clk50;
reg clk25 = 0;
wire clkdeb;
wire clkseg;
var_clock #(32\'d100) vcsamp(clk, clksamp);
var_clock #(32\'d1000000) vcdeb(clk, clkdeb);
var_clock #(32\'h20000) vcseg(clk, clkseg);
always @(posedge clk) clk50 = ~clk50;
always @(posedge clk50) clk25 = ~clk25;
wire btnu,btnd,btnl,btnr,btnc;
debounce dbu(clkdeb, btnU, btnu);
debounce dbd(clkdeb, btnD, btnd);
debounce dbl(clkdeb, btnL, btnl);
debounce dbr(clkdeb, btnR, btnr);
debounce dbc(clkdeb, btnC, btnc);
wire[10:0] mx;
wire[10:0] my;
wire left_button;
wire right_button;
wire middle_button;
MouseCtl ms(.clk(clk), .rst(1\'b0), .xpos(mx), .ypos(my), .left(left_button), .middle(middle_button), .right(right_button), .value(12\'b0), .setx(0), .sety(0), .setmax_x(0), .setmax_y(0), .ps2_clk(PS2Clk), .ps2_data(PS2Data));
wire vgactive;
wire hs, vs;
wire [10:0] hc;
wire [10:0] vc;
vga_ctrl vct(clkvga, vgactive, hs, vs, hc, vc);
reg[13:0] step = 1;
reg[17:0] freqa = 1000;
reg[11:0] ampa = 2048;
reg[11:0] offa = 2048;
reg[17:0] freqb = 1000;
reg[11:0] ampb = 2048;
reg[11:0] offb = 2048;
reg[9:0] dutya = 500;
reg[9:0] dutyb = 500;
reg[1:0] chanA = 1;
reg[1:0] chanB = 1;
reg [1:0] lbreg = 0;
reg [1:0] rbreg = 0;
reg [1:0] mbreg = 0;
reg [1:0] btncreg = 0;
reg [1:0] btnureg = 0;
reg [1:0] btndreg = 0;
reg [1:0] btnlreg = 0;
reg [1:0] btnrreg = 0;
localparam btn_y_start = 462;
localparam btn_y_width = 50;
localparam btn_x_start_left = 110;
localparam btn_x_start_right = 460;
localparam btn_x_width = 50;
localparam btn_x_spacing = 10;
wire btn4 = (hc >= btn_x_start_left && hc <= btn_x_start_left+btn_x_width && vc >= btn_y_start && vc <= btn_y_start+btn_y_width);
wire btn5 = (hc >= btn_x_start_left+btn_x_width+btn_x_spacing && hc <= btn_x_start_left+btn_x_width+btn_x_spacing+btn_x_width && vc >= btn_y_start && vc <= btn_y_start+btn_y_width);
wire btn6 = (hc >= btn_x_start_left+btn_x_width+btn_x_spacing+btn_x_width+btn_x_spacing && hc <= btn_x_start_left+btn_x_width+btn_x_spacing+btn_x_width+btn_x_spacing+btn_x_width && vc >= btn_y_start && vc <= btn_y_start+btn_y_width);
wire btn7 = (hc >= btn_x_start_left+btn_x_width+btn_x_spacing+btn_x_width+btn_x_spacing+btn_x_width+btn_x_spacing && hc <= btn_x_start_left+btn_x_width+btn_x_spacing+btn_x_width+btn_x_spacing+btn_x_width+btn_x_spacing+btn_x_width && vc >= btn_y_start && vc <= btn_y_start+btn_y_width);
wire btn8 = (hc >= btn_x_start_right && hc <= btn_x_start_right+btn_x_width && vc >= btn_y_start && vc <= btn_y_start+btn_y_width);
wire btn9 = (hc >= btn_x_start_right+btn_x_width+btn_x_spacing && hc <= btn_x_start_right+btn_x_width+btn_x_spacing+btn_x_width && vc >= btn_y_start && vc <= btn_y_start+btn_y_width);
wire btn10 = (hc >= btn_x_start_right+btn_x_width+btn_x_spacing+btn_x_width+btn_x_spacing && hc <= btn_x_start_right+btn_x_width+btn_x_spacing+btn_x_width+btn_x_spacing+btn_x_width && vc >= btn_y_start && vc <= btn_y_start+btn_y_width);
wire btn11 = (hc >= btn_x_start_right+btn_x_width+btn_x_spacing+btn_x_width+btn_x_spacing+btn_x_width+btn_x_spacing && hc <= btn_x_start_right+btn_x_width+btn_x_spacing+btn_x_width+btn_x_spacing+btn_x_width+btn_x_spacing+btn_x_width && vc >= btn_y_start && vc <= btn_y_start+btn_y_width);
wire cbtn4 = (mx >= btn_x_start_left && mx <= btn_x_start_left+btn_x_width && my >= btn_y_start && my <= btn_y_start+btn_y_width);
wire cbtn5 = (mx >= btn_x_start_left+btn_x_width+btn_x_spacing && mx <= btn_x_start_left+btn_x_width+btn_x_spacing+btn_x_width && my >= btn_y_start && my <= btn_y_start+btn_y_width);
wire cbtn6 = (mx >= btn_x_start_left+btn_x_width+btn_x_spacing+btn_x_width+btn_x_spacing && mx <= btn_x_start_left+btn_x_width+btn_x_spacing+btn_x_width+btn_x_spacing+btn_x_width && my >= btn_y_start && my <= btn_y_start+btn_y_width);
wire cbtn7 = (mx >= btn_x_start_left+btn_x_width+btn_x_spacing+btn_x_width+btn_x_spacing+btn_x_width+btn_x_spacing && mx <= btn_x_start_left+btn_x_width+btn_x_spacing+btn_x_width+btn_x_spacing+btn_x_width+btn_x_spacing+btn_x_width && my >= btn_y_start && my <= btn_y_start+btn_y_width);
wire cbtn8 = (mx >= btn_x_start_right && mx <= btn_x_start_right+btn_x_width && my >= btn_y_start && my <= btn_y_start+btn_y_width);
wire cbtn9 = (mx >= btn_x_start_right+btn_x_width+btn_x_spacing && mx <= btn_x_start_right+btn_x_width+btn_x_spacing+btn_x_width && my >= btn_y_start && my <= btn_y_start+btn_y_width);
wire cbtn10 = (mx >= btn_x_start_right+btn_x_width+btn_x_spacing+btn_x_width+btn_x_spacing && mx <= btn_x_start_right+btn_x_width+btn_x_spacing+btn_x_width+btn_x_spacing+btn_x_width && my >= btn_y_start && my <= btn_y_start+btn_y_width);
wire cbtn11 = (mx >= btn_x_start_right+btn_x_width+btn_x_spacing+btn_x_width+btn_x_spacing+btn_x_width+btn_x_spacing && mx <= btn_x_start_right+btn_x_width+btn_x_spacing+btn_x_width+btn_x_spacing+btn_x_width+btn_x_spacing+btn_x_width && my >= btn_y_start && my <= btn_y_start+btn_y_width);
wire selected_btna = (chanA == 0) ? btn4 :
(chanA == 1) ? btn5 :
(chanA == 2) ? btn6 :
btn7;
wire selected_btnb = (chanB == 0) ? btn8 :
(chanB == 1) ? btn9 :
(chanB == 2) ? btn10 :
btn11;
wire unselected_btnsa = (chanA == 0) ? btn5 | btn6 | btn7 :
(chanA == 1) ? btn4 | btn6 | btn7 :
(chanA == 2) ? btn4 | btn5 | btn7 :
btn4 | btn5 | btn6;
wire unselected_btnsb = (chanB == 0) ? btn9 | btn10 | btn11 :
(chanB == 1) ? btn8 | btn10 | btn11 :
(chanB == 2) ? btn8 | btn9 | btn11 :
btn8 | btn9 | btn10;
wire[7:0] text;
wire freq_b;
wire amp_b;
wire off_b;
wire duty_b;
wire freqb_b;
wire ampb_b;
wire offb_b;
wire dutyb_b;
wire combword;
wire combinverse;
text_mod my_text(hc, vc, combword, combinverse);
wire[3:0] fqath,fqahun,fqaten,fqaone;
wire[3:0] apath,apahun,apaten,apaone;
wire[3:0] ofath,ofahun,ofaten,ofaone;
wire[3:0] dyath,dyahun,dyaten,dyaone;
wire[3:0] fqbth,fqbhun,fqbten,fqbone;
wire[3:0] apbth,apbhun,apbten,apbone;
wire[3:0] ofbth,ofbhun,ofbten,ofbone;
wire[3:0] dybth,dybhun,dybten,dybone;
num_to_digits1 nd1(freqa, fqath, fqahun, fqaten, fqaone);
num_to_digits nd2(sw[13]?((ampa*MAXVOLTAGE)/4096):ampa, apath, apahun, apaten, apaone);
num_to_digits nd3(sw[13]?((offa*MAXVOLTAGE)/4096):offa, ofath, ofahun, ofaten, ofaone);
num_to_digits nd4(dutya, dyath, dyahun, dyaten, dyaone);
num_to_digits1 nd5(freqb, fqbth, fqbhun, fqbten, fqbone);
num_to_digits nd6(sw[13]?((ampb*MAXVOLTAGE)/4096):ampb, apbth, apbhun, apbten, apbone);
num_to_digits nd7(sw[13]?((offb*MAXVOLTAGE)/4096):offb, ofbth, ofbhun, ofbten, ofbone);
num_to_digits nd8(dutyb, dybth, dybhun, dybten, dybone);
localparam num_y_width = 30;
localparam num_y_start = 202;
localparam num_y_spacing = 25;
localparam num_x_start_left_4 = 248;
localparam num_x_start_left_6 = 202;
localparam num_x_width = 15;
localparam num_x_start_right = 460;
localparam num_x_spacing = 8;
clickable_num6_left #(num_x_width,num_x_spacing) num0(freqa, fqath, fqahun, fqaten, fqaone, hc, vc, num_x_start_left_6+num_x_spacing, num_y_start, mx, my, text[0], freq_b);
clickable_num4 #(num_x_width,num_x_spacing) num1(ampa, apath, apahun, apaten, apaone, hc, vc, num_x_start_left_4+num_x_spacing, num_y_start+num_y_width+num_y_spacing, mx, my, text[1], amp_b);
clickable_num4 #(num_x_width,num_x_spacing) num2(offa, ofath, ofahun, ofaten, ofaone, hc, vc, num_x_start_left_4+num_x_spacing, num_y_start+num_y_width+num_y_spacing+num_y_width+num_y_spacing, mx, my, text[2], off_b);
clickable_num4 #(num_x_width,num_x_spacing) num3(dutya, dyath, dyahun, dyaten, dyaone,hc, vc, num_x_start_left_4+num_x_spacing, num_y_start+num_y_width+num_y_spacing+num_y_width+num_y_spacing+num_y_width+num_y_spacing, mx, my, text[3], duty_b);
clickable_num6_right #(num_x_width,num_x_spacing) num4(freqb, fqbth, fqbhun, fqbten, fqbone, hc, vc, num_x_start_right, num_y_start, mx, my, text[4], freqb_b);
clickable_num4 #(num_x_width,num_x_spacing) num5(ampb, apbth, apbhun, apbten, apbone, hc, vc, num_x_start_right, num_y_start+num_y_width+num_y_spacing, mx, my, text[5], ampb_b);
clickable_num4 #(num_x_width,num_x_spacing) num6(offb, ofbth, ofbhun, ofbten, ofbone, hc, vc, num_x_start_right, num_y_start+num_y_width+num_y_spacing+num_y_width+num_y_spacing, mx, my, text[6], offb_b);
clickable_num4 #(num_x_width,num_x_spacing) num7(dutyb, dybth, dybhun, dybten, dybone, hc, vc, num_x_start_right-num_x_width-num_x_spacing, num_y_start+num_y_width+num_y_spacing+num_y_width+num_y_spacing+num_y_width+num_y_spacing, mx, my, text[7], dutyb_b);
wire combtext = combinverse|(|text);
wire[3:0] s1 = ~sw[0] ? sw[1] ? fqath :
\t\t\t\t\t sw[2] ? apath :
\t\t\t\t\t sw[3] ? ofath :
\t\t\t\t\t sw[4] ? dyath : 2
\t\t\t\t : sw[1] ? fqbth :
\t\t\t\t\t sw[2] ? apbth :
\t\t\t\t\t sw[3] ? ofbth :
\t\t\t\t\t sw[4] ? dybth : 2;
\t\t\t\t\t
wire[3:0] s2 = ~sw[0] ? sw[1] ? fqahun :
\t\t\t\t\t sw[2] ? apahun :
\t\t\t\t\t sw[3] ? ofahun :
\t\t\t\t\t sw[4] ? dyahun : 0
\t\t\t\t : sw[1] ? fqbhun :
\t\t\t\t\t sw[2] ? apbhun :
\t\t\t\t\t sw[3] ? ofbhun :
\t\t\t\t\t sw[4] ? dybhun : 0;
\t\t\t\t\t
wire[3:0] s3 = ~sw[0] ? sw[1] ? fqaten :
\t\t\t\t\t sw[2] ? apaten :
\t\t\t\t\t sw[3] ? ofaten :
\t\t\t\t\t sw[4] ? dyaten : 2
\t\t\t\t : sw[1] ? fqbten :
\t\t\t\t\t sw[2] ? apbten :
\t\t\t\t\t sw[3] ? ofbten :
\t\t\t\t\t sw[4] ? dybten : 2;
\t\t\t\t\t
wire[3:0] s4 = ~sw[0] ? sw[1] ? fqaone :
\t\t\t\t\t sw[2] ? apaone :
\t\t\t\t\t sw[3] ? ofaone :
\t\t\t\t\t sw[4] ? dyaone : 0
\t\t\t\t : sw[1] ? fqbone :
\t\t\t\t\t sw[2] ? apbone :
\t\t\t\t\t sw[3] ? ofbone :
\t\t\t\t\t sw[4] ? dybone : 0;
seg_disp segd(clkseg, s1, s2, s3, s4, 1\'b0, seg, an, dp);
assign led[3] = sw[0] ? (chanB == 0) : (chanA == 0);
assign led[2] = sw[0] ? (chanB == 1) : (chanA == 1);
assign led[1] = sw[0] ? (chanB == 2) : (chanA == 2);
assign led[0] = sw[0] ? (chanB == 3) : (chanA == 3);
assign led[15] = step==1;
assign led[14] = step==10;
assign led[13] = step==100;
assign led[12] = step==1000;
assign led[11] = step==10000;
wire[17:0] resetfreq = sw[14]?0:1000;
always @(posedge clk) begin
lbreg <= {lbreg[0], left_button};
rbreg <= {rbreg[0], right_button};
mbreg <= {mbreg[0], middle_button};
btncreg <= {btncreg[0], btnc};
btnureg <= {btnureg[0], btnu};
btndreg <= {btndreg[0], btnd};
btnlreg <= {btnlreg[0], btnl};
btnrreg <= {btnrreg[0], btnr};
if(lbreg==2\'b01) begin
chanA <= (cbtn4) ? 0 :
(cbtn5) ? 1 :
(cbtn6) ? 2 :
(cbtn7) ? 3 : chanA;
\t\tchanB <= (cbtn8) ? 0 :
(cbtn9) ? 1 :
(cbtn10) ? 2 :
(cbtn11) ? 3 : chanB;
freqa <= (freq_b && freqa <= MAXFREQ-step) ? freqa + step : freqa;
ampa <= (amp_b && ampa <= MAXAMP-step) ? ampa + step : ampa;
offa <= (off_b && offa <= MAXAMP-step) ? offa + step : offa;
dutya <= (duty_b && dutya <= MAXDUTY-step) ? dutya + step : dutya;
freqb <= (freqb_b && freqb <= MAXFREQ-step) ? freqb + step : freqb;
ampb <= (ampb_b && ampb <= MAXAMP-step) ? ampb + step : ampb;
offb <= (offb_b && offb <= MAXAMP-step) ? offb + step : offb;
dutyb <= (dutyb_b && dutyb <= MAXDUTY-step) ? dutyb + step : dutyb;
end else if(rbreg==2\'b01) begin
freqa <= (freq_b && freqa >= step) ? freqa - step : freqa;
\t\tampa <= (amp_b && ampa >= step) ? ampa - step : ampa;
\t\toffa <= (off_b && offa >= step) ? offa - step : offa;
\t\tdutya <= (duty_b && dutya >= step) ? dutya - step : dutya;
\t\tfreqb <= (freqb_b && freqb >= step) ? freqb - step : freqb;
\t\tampb <= (ampb_b && ampb >= step) ? ampb - step : ampb;
\t\toffb <= (offb_b && offb >= step) ? offb - step : offb;
\t\tdutyb <= (dutyb_b && dutyb >= step) ? dutyb - step : dutyb;
end else if(mbreg==2\'b01) begin
case(step)
1:step<=10;
10:step<=100;
100:step<=1000;
1000:step<=10000;
10000:step<=1;
default:step<=1;
endcase
end else if(btncreg==2\'b01) begin
chanA <= 1;
chanB <= 1;
freqa <= resetfreq;
ampa <= 2048;
offa <= 2048;
dutya <= 500;
freqb <= resetfreq;
ampb <= 2048;
offb <= 2048;
dutyb <= 500;
step <= 1;
end else if(btnureg==2\'b01) begin
\t\tfreqa <= (sw[4:0]==2 && freqa <= MAXFREQ-step) ? freqa + step : freqa;
ampa <= (sw[4:0]==4 && ampa <= MAXAMP-step) ? ampa + step : ampa;
offa <= (sw[4:0]==8 && offa <= MAXAMP-step) ? offa + step : offa;
dutya <= (sw[4:0]==16 && dutya <= MAXDUTY-step) ? dutya + step : dutya;
freqb <= (sw[4:0]==3 && freqb <= MAXFREQ-step) ? freqb + step : freqb;
ampb <= (sw[4:0]==5 && ampb <= MAXAMP-step) ? ampb + step : ampb;
offb <= (sw[4:0]==9 && offb <= MAXAMP-step) ? offb + step : offb;
dutyb <= (sw[4:0]==17 && dutyb <= MAXDUTY-step) ? dutyb + step : dutyb;
\tend else if(btndreg==2\'b01) begin
\t\tfreqa <= (sw[4:0]==2 && freqa >= step) ? freqa - step : freqa;
\t\tampa <= (sw[4:0]==4 && ampa >= step) ? ampa - step : ampa;
\t\toffa <= (sw[4:0]==8 && offa >= step) ? offa - step : offa;
\t\tdutya <= (sw[4:0]==16 && dutya >= step) ? dutya - step : dutya;
\t\tfreqb <= (sw[4:0]==3 && freqb >= step) ? freqb - step : freqb;
\t\tampb <= (sw[4:0]==5 && ampb >= step) ? ampb - step : ampb;
\t\toffb <= (sw[4:0]==9 && offb >= step) ? offb - step : offb;
\t\tdutyb <= (sw[4:0]==17 && dutyb >= step) ? dutyb - step : dutyb;
\tend else if(btnlreg==2\'b01) begin
\t\tchanA <= ~sw[15] && ~sw[0] && chanA > 0 ? chanA - 1 : chanA;
chanB <= ~sw[15] && sw[0] && chanB > 0 ? chanB - 1 : chanB;
step <= sw[15] ? step==10000?1000:step==1000?100:step==100?10:1 : step;
\tend else if(btnrreg==2\'b01) begin
\t\tchanA <= ~sw[15] && ~sw[0] && chanA < MAXCHAN ? chanA + 1 : chanA;
chanB <= ~sw[15] && sw[0] && chanB < MAXCHAN ? chanB + 1 : chanB;
step <= sw[15] ? step==1?10:step==10?100:step==100?1000:10000 : step;
\tend
end
wire[11:0] arbA, arbB;
arb arbmod(clk25, RsRx, arbA, arbB);
wire[11:0] sinA, sinB;
sinemod mysineA(clksamp, freqa, ampa, offa, sinA);
sinemod mysineB(clksamp, freqb, ampb, offb, sinB);
wire[11:0] sqA, sqB;
square #(500_000) sqmodA(clksamp, freqa, ampa, offa, dutya, sqA);
square #(500_000) sqmodB(clksamp, freqb, ampb, offb, dutyb, sqB);
wire[11:0] triA, triB;
triangle #(500_000) trimodA(clksamp, freqa, ampa, offa, dutya, triA);
triangle #(500_000) trimodB(clksamp, freqb, ampb, offb, dutyb, triB);
wire[11:0] DATA_A = (chanA == 0) ? arbA :
(chanA == 1) ? sinA :
(chanA == 2) ? sqA : triA;
wire[11:0] DATA_B = (chanB == 0) ? arbB :
(chanB == 1) ? sinB :
(chanB == 2) ? sqB : triB;
DA2RefComp dac(.CLK(clk50), .D1(JA[1]), .D2(JA[2]), .CLK_OUT(JA[3]), .nSYNC(JA[0]), .DATA1(DATA_A), .DATA2(DATA_B), .START(clksamp));
wire mouse_inner;
wire mouse_outline;
region_mouse_white rmw(hc, vc, mx, my, mouse_inner);
region_mouse_black rmb(hc, vc, mx, my, mouse_outline);
wire vgawhite = unselected_btnsa | unselected_btnsb | combtext;
wire vgared = vgawhite;
wire vgagreen = vgawhite | selected_btna | selected_btnb;
wire vgablu = vgawhite | selected_btna | selected_btnb;
wire vgablack = mouse_outline | combword;
always@(posedge clkvga) begin
vgaRed <= {4{vgactive & ((vgared & ~vgablack) | mouse_inner)}};
vgaGreen <= {4{vgactive & ((vgagreen & ~vgablack) | mouse_inner)}};
vgaBlue <= {4{vgactive & ((vgablu & ~vgablack) | mouse_inner)}};
Hsync <= hs;
Vsync <= vs;
end
endmodule
module text_mod(input[10:0] hc, input[10:0] vc, output text_out1, output text_out2);
localparam sp = 10;
localparam header_x = 320;
localparam header_y = 96;
localparam freq_x = 380;
localparam freq_y = 212;
localparam amp_x = 385;
localparam amp_y = 267;
localparam offset_x = 370;
localparam offset_y = 322;
localparam duty_x = 380;
localparam duty_y = 377;
localparam btn_y = 462+20;
localparam arba_x = 110+10;
localparam arbb_x = 460+10;
localparam sina_x = 170+5;
localparam sinb_x = 520+5;
localparam sqa_x = 230+15;
localparam sqb_x = 580+15;
localparam tria_x = 290+10;
localparam trib_x = 640+10;
localparam cha_x = 290;
localparam cha_y = 96;
localparam chb_x = 490;
localparam chb_y = 96;
wire[3:0] wordcha;
alphanum #("C") acha1(hc, vc, cha_x, cha_y, wordcha[0]);
alphanum #("h") acha2(hc, vc, cha_x+sp, cha_y+1, wordcha[1]);
alphanum #("A") acha3(hc, vc, cha_x+sp+sp+sp, cha_y, wordcha[2]);
wire[3:0] wordchb;
alphanum #("C") achb1(hc, vc, chb_x, chb_y, wordchb[0]);
alphanum #("h") achb2(hc, vc, chb_x+sp, chb_y+1, wordchb[1]);
alphanum #("B") achb3(hc, vc, chb_x+sp+sp+sp, chb_y, wordchb[2]);
wire[3:0] wordarb1;
alphanum #("A") aarb1(hc, vc, arba_x, btn_y, wordarb1[0]);
alphanum #("r") aarb2(hc, vc, arba_x+sp, btn_y+1, wordarb1[1]);
alphanum #("b") aarb3(hc, vc, arba_x+sp+sp, btn_y+1, wordarb1[2]);
wire[3:0] wordarb2;
alphanum #("A") aarb4(hc, vc, arbb_x, btn_y, wordarb2[0]);
alphanum #("r") aarb5(hc, vc, arbb_x+sp, btn_y+1, wordarb2[1]);
alphanum #("b") aarb6(hc, vc, arbb_x+sp+sp, btn_y+1, wordarb2[2]);
wire[3:0] wordsin1;
alphanum #("S") asine1(hc, vc, sina_x, btn_y, wordsin1[0]);
alphanum #("i") asine2(hc, vc, sina_x+sp, btn_y+1, wordsin1[1]);
alphanum #("n") asine3(hc, vc, sina_x+sp+sp, btn_y+1, wordsin1[2]);
alphanum #("e") asine4(hc, vc, sina_x+sp+sp+sp, btn_y+1, wordsin1[3]);
wire[3:0] wordsin2;
alphanum #("S") asine5(hc, vc, sinb_x, btn_y, wordsin2[0]);
alphanum #("i") asine6(hc, vc, sinb_x+sp, btn_y+1, wordsin2[1]);
alphanum #("n") asine7(hc, vc, sinb_x+sp+sp, btn_y+1, wordsin2[2]);
alphanum #("e") asine8(hc, vc, sinb_x+sp+sp+sp, btn_y+1, wordsin2[3]);
wire[1:0] wordsq1;
alphanum #("S") asq1(hc, vc, sqa_x, btn_y, wordsq1[0]);
alphanum #("q") aqs2(hc, vc, sqa_x+sp, btn_y+1, wordsq1[1]);
wire[1:0] wordsq2;
alphanum #("S") asq3(hc, vc, sqb_x, btn_y, wordsq2[0]);
alphanum #("q") asq4(hc, vc, sqb_x+sp, btn_y+1, wordsq2[1]);
wire[2:0] wordtri1;
alphanum #("T") atri1(hc, vc, tria_x, btn_y, wordtri1[0]);
alphanum #("r") atri2(hc, vc, tria_x+sp, btn_y+1, wordtri1[1]);
alphanum #("i") atri3(hc, vc, tria_x+sp+sp, btn_y+1, wordtri1[2]);
wire[2:0] wordtri2;
alphanum #("T") atri4(hc, vc, trib_x, btn_y, wordtri2[0]);
alphanum #("r") atri5(hc, vc, trib_x+sp, btn_y+1, wordtri2[1]);
alphanum #("i") atri6(hc, vc, trib_x+sp+sp, btn_y+1, wordtri2[2]);
wire[3:0] wordsfreqa;
alphanum #("F") afreq1(hc, vc, freq_x, freq_y, wordsfreqa[0]);
alphanum #("r") afreq2(hc, vc, freq_x+sp, freq_y+1, wordsfreqa[1]);
alphanum #("e") afreq3(hc, vc, freq_x+sp+sp, freq_y+1, wordsfreqa[2]);
alphanum #("q") afreq4(hc, vc, freq_x+sp+sp+sp, freq_y+1, wordsfreqa[3]);
wire[2:0] wordampa;
alphanum #("A") aamp1(hc, vc, amp_x, amp_y, wordampa[0]);
alphanum #("m") aamp2(hc, vc, amp_x+sp, amp_y+1, wordampa[1]);
alphanum #("p") aamp3(hc, vc, amp_x+sp+sp, amp_y+1, wordampa[2]);
wire[5:0] wordoffa;
alphanum #("O") aoff1(hc, vc, offset_x, offset_y, wordoffa[0]);
alphanum #("f") aoff2(hc, vc, offset_x+sp, offset_y+1, wordoffa[1]);
alphanum #("f") aoff3(hc, vc, offset_x+sp+sp, offset_y+1, wordoffa[2]);
alphanum #("s") aoff4(hc, vc, offset_x+sp+sp+sp, offset_y+1, wordoffa[3]);
alphanum #("e") aoff5(hc, vc, offset_x+sp+sp+sp+sp, offset_y+1, wordoffa[4]);
alphanum #("t") aoff6(hc, vc, offset_x+sp+sp+sp+sp+sp, offset_y+1, wordoffa[5]);
wire[3:0] worddutya;
alphanum #("D") aduty1(hc, vc, duty_x, duty_y, worddutya[0]);
alphanum #("u") aduty2(hc, vc, duty_x+sp, duty_y+1, worddutya[1]);
alphanum #("t") aduty3(hc, vc, duty_x+sp+sp, duty_y+1, worddutya[2]);
alphanum #("y") aduty4(hc, vc, duty_x+sp+sp+sp, duty_y+1, worddutya[3]);
assign text_out1 = (| wordarb1)|(| wordarb2)|(| wordsin1)|(| wordsin2)|(| wordsq1)|(| wordsq2)|(| wordtri1)|(| wordtri2);
assign text_out2 = (| wordsfreqa)|(| wordampa)|(| wordoffa)|(| worddutya)|(| wordcha)|(| wordchb);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11.03.2017 19:31:22
// Design Name:
// Module Name: main
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module triangle(input clksamp, input signed[33:0] freq, input signed[33:0] amp, input signed[33:0] off, input signed[33:0] duty, output[11:0] dac);
parameter SAMP_FREQ = 100_000_000;
reg signed[33:0] level = 0;
reg state = 1'b0;
wire signed[33:0] clipped_duty = duty < 15 ? 15 : duty > 989 ? 999 : duty;
wire signed[33:0] delta = (2 * freq * 262144) / SAMP_FREQ;
wire signed[33:0] delta_div = delta * 1000;
wire signed[33:0] delta_up = delta_div / {clipped_duty[33:1],1'b1};
wire signed[33:0] delta_down = delta_div / (1000 - {clipped_duty[33:1],1'b1});
always @(posedge clksamp) begin
level = state ? ((level - delta_down) < -262144 ? -262144 : level - delta_down) : ((level + delta_up) > 262144 ? 262144 : level + delta_up);
state = state ? level - delta_down <= -262144 ? 0 : state : level + delta_up >= 262144 ? 1 : state;
end
wire signed[33:0] preclip = off + (level*amp)/262144;
assign dac = preclip < 0 ? 0 : preclip > 4095 ? 4095 : preclip;
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19.02.2017 01:26:40
// Design Name:
// Module Name: seg_disp
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module seg_disp(
input clk,
input[7:0] d1,
input[7:0] d2,
input[7:0] d3,
input[7:0] d4,
input dp,
output reg[6:0] seg,
output reg[3:0] an,
output dp_pin
);
wire[6:0] seg1;
wire[6:0] seg2;
wire[6:0] seg3;
wire[6:0] seg4;
reg[2:0] state = 0;
assign dp_pin = 1;
number_to_seg dd1(d1, seg1);
number_to_seg dd2(d2, seg2);
number_to_seg dd3(d3, seg3);
number_to_seg dd4(d4, seg4);
wire nd1 = (d1 == 0);
wire nd2 = (d2 == 0);
wire nd3 = (d3 == 0);
always @(posedge clk) begin
case (state)
default: state <= 0;
0: begin
seg <= seg1;
an <= nd1 ? 4'b1111 : 4'b0111;
state <= state + 1;
end
1: begin
seg <= seg2;
an <= nd1 && nd2 ? 4'b1111 : 4'b1011;
state <= state + 1;
end
2: begin
seg <= seg3;
an <= nd1 && nd2 && nd3 ? 4'b1111 : 4'b1101;
state <= state + 1;
end
3: begin
seg <= seg4;
an <= 4'b1110;
state <= 0;
end
endcase
end
endmodule
module number_to_seg(input[7:0] d, output[6:0] seg);
assign seg = (d == 0) ? 7'b1000000 :
(d == 1) ? 7'b1111001 :
(d == 2) ? 7'b0100100 :
(d == 3) ? 7'b0110000 :
(d == 4) ? 7'b0011001 :
(d == 5) ? 7'b0010010 :
(d == 6) ? 7'b0000010 :
(d == 7) ? 7'b1111000 :
(d == 8) ? 7'b0000000 :
(d == 9) ? 7'b0010000 : 7'b1000000;
endmodule
module num_to_digits(input[11:0] _num, output[3:0] _thousands, output [3:0] _hundreds, output [3:0] _tens, output [3:0] _ones);
assign _thousands = (_num % 10000) / 1000;
assign _hundreds = (_num % 1000) / 100;
assign _tens = (_num % 100) / 10;
assign _ones = _num % 10;
endmodule
module num_to_digits1(input[17:0] _num, output[3:0] _thousands, output [3:0] _hundreds, output [3:0] _tens, output [3:0] _ones);
assign _thousands = (_num % 10000) / 1000;
assign _hundreds = (_num % 1000) / 100;
assign _tens = (_num % 100) / 10;
assign _ones = _num % 10;
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Tue Mar 28 05:22:49 2017
// Host : DESKTOP-B1QME94 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dds_compiler_0_stub.v
// Design : dds_compiler_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "dds_compiler_v6_0_13,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, s_axis_phase_tvalid,
s_axis_phase_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_phase_tvalid,s_axis_phase_tdata[23:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]" */;
input aclk;
input s_axis_phase_tvalid;
input [23:0]s_axis_phase_tdata;
output m_axis_data_tvalid;
output [15:0]m_axis_data_tdata;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10.03.2017 09:19:09
// Design Name:
// Module Name: sine
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sinemod(
input clkdds,
input[31:0] freq,
input signed[15:0] amp,
input signed[15:0] amp_off,
output[11:0] sin
);
wire data_valid;
reg phase_valid = 1;
wire signed[16:0] data;
wire[23:0] phase = (freq*83886)/10000;
dds_compiler_0 sine_dds(clkdds, phase_valid, phase, data_valid, data);
reg signed[16:0] amped = 16'b0;
reg signed[16:0] offseted = 16'b0;
reg signed[16:0] clipped = 16'b0;
wire signed[16:0] amp_clipped = amp > 2048 ? 2048 : amp;
always @(posedge clkdds) begin
amped <= (data * amp_clipped) / 1024; // max 2048 to -2048
offseted <= amp_off + amped;
clipped <= offseted < 0 ? 0 : offseted > 4095 ? 4095 : offseted;
end
assign sin = data_valid?clipped:0;
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14.03.2017 00:48:48
// Design Name:
// Module Name: uart
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: Referenced from fpga4fun
//
//////////////////////////////////////////////////////////////////////////////////
module async_receiver(
\tinput clk,
\tinput RxD,
\toutput reg RxD_data_ready = 0,
\toutput reg [7:0] RxD_data = 0, // data received, valid only (for one clock cycle) when RxD_data_ready is asserted
\t// We also detect if a gap occurs in the received stream of characters
\t// That can be useful if multiple characters are sent in burst
\t// so that multiple characters can be treated as a "packet"
\toutput RxD_idle, // asserted when no data has been received for a while
\toutput reg RxD_endofpacket = 0 // asserted for one clock cycle when a packet has been detected (i.e. RxD_idle is going high)
);
parameter ClkFrequency = 25000000; // 25MHz
parameter Baud = 1152000;
parameter Oversampling = 16; // needs to be a power of 2
// we oversample the RxD line at a fixed rate to capture each RxD data bit at the "right" time
// 8 times oversampling by default, use 16 for higher quality reception
generate
\tif(ClkFrequency<Baud*Oversampling) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency too low for current Baud rate and oversampling");
\tif(Oversampling<8 || ((Oversampling & (Oversampling-1))!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Invalid oversampling value");
endgenerate
////////////////////////////////
reg [3:0] RxD_state = 0;
wire OversamplingTick;
BaudTickGen #(ClkFrequency, Baud, Oversampling) tickgen(.clk(clk), .enable(1\'b1), .tick(OversamplingTick));
// synchronize RxD to our clk domain
reg [1:0] RxD_sync = 2\'b11;
always @(posedge clk) if(OversamplingTick) RxD_sync <= {RxD_sync[0], RxD};
// and filter it
reg [1:0] Filter_cnt = 2\'b11;
reg RxD_bit = 1\'b1;
always @(posedge clk)
if(OversamplingTick)
begin
\tif(RxD_sync[1]==1\'b1 && Filter_cnt!=2\'b11) Filter_cnt <= Filter_cnt + 1\'d1;
\telse
\tif(RxD_sync[1]==1\'b0 && Filter_cnt!=2\'b00) Filter_cnt <= Filter_cnt - 1\'d1;
\tif(Filter_cnt==2\'b11) RxD_bit <= 1\'b1;
\telse
\tif(Filter_cnt==2\'b00) RxD_bit <= 1\'b0;
end
// and decide when is the good time to sample the RxD line
function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction
localparam l2o = log2(Oversampling);
reg [l2o-2:0] OversamplingCnt = 0;
always @(posedge clk) if(OversamplingTick) OversamplingCnt <= (RxD_state==0) ? 1\'d0 : OversamplingCnt + 1\'d1;
wire sampleNow = OversamplingTick && (OversamplingCnt==Oversampling/2-1);
// now we can accumulate the RxD bits in a shift-register
always @(posedge clk)
case(RxD_state)
\t4\'b0000: if(~RxD_bit) RxD_state <= `ifdef SIMULATION 4\'b1000 `else 4\'b0001 `endif; // start bit found?
\t4\'b0001: if(sampleNow) RxD_state <= 4\'b1000; // sync start bit to sampleNow
\t4\'b1000: if(sampleNow) RxD_state <= 4\'b1001; // bit 0
\t4\'b1001: if(sampleNow) RxD_state <= 4\'b1010; // bit 1
\t4\'b1010: if(sampleNow) RxD_state <= 4\'b1011; // bit 2
\t4\'b1011: if(sampleNow) RxD_state <= 4\'b1100; // bit 3
\t4\'b1100: if(sampleNow) RxD_state <= 4\'b1101; // bit 4
\t4\'b1101: if(sampleNow) RxD_state <= 4\'b1110; // bit 5
\t4\'b1110: if(sampleNow) RxD_state <= 4\'b1111; // bit 6
\t4\'b1111: if(sampleNow) RxD_state <= 4\'b0010; // bit 7
\t4\'b0010: if(sampleNow) RxD_state <= 4\'b0000; // stop bit
\tdefault: RxD_state <= 4\'b0000;
endcase
always @(posedge clk)
if(sampleNow && RxD_state[3]) RxD_data <= {RxD_bit, RxD_data[7:1]};
//reg RxD_data_error = 0;
always @(posedge clk)
begin
\tRxD_data_ready <= (sampleNow && RxD_state==4\'b0010 && RxD_bit); // make sure a stop bit is received
\t//RxD_data_error <= (sampleNow && RxD_state==4\'b0010 && ~RxD_bit); // error if a stop bit is not received
end
reg [l2o+1:0] GapCnt = 0;
always @(posedge clk) if (RxD_state!=0) GapCnt<=0; else if(OversamplingTick & ~GapCnt[log2(Oversampling)+1]) GapCnt <= GapCnt + 1\'h1;
assign RxD_idle = GapCnt[l2o+1];
always @(posedge clk) RxD_endofpacket <= OversamplingTick & ~GapCnt[l2o+1] & &GapCnt[l2o:0];
endmodule
////////////////////////////////////////////////////////
// dummy module used to be able to raise an assertion in Verilog
module ASSERTION_ERROR();
endmodule
////////////////////////////////////////////////////////
module BaudTickGen(
\tinput clk, enable,
\toutput tick // generate a tick at the specified baud rate * oversampling
);
parameter ClkFrequency = 25000000;
parameter Baud = 1152000;
parameter Oversampling = 16;
function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction
localparam AccWidth = log2(ClkFrequency/Baud)+8; // +/- 2% max timing error over a byte
reg [AccWidth:0] Acc = 0;
localparam ShiftLimiter = log2(Baud*Oversampling >> (31-AccWidth)); // this makes sure Inc calculation doesn\'t overflow
localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter);
always @(posedge clk) if(enable) Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0]; else Acc <= Inc[AccWidth:0];
assign tick = Acc[AccWidth];
endmodule
////////////////////////////////////////////////////////
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module blk_mem_gen_arb (
clka,
ena,
wea,
addra,
dina,
clkb,
enb,
addrb,
doutb
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [15 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [11 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *)
input wire clkb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *)
input wire enb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *)
input wire [15 : 0] addrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *)
output wire [11 : 0] doutb;
blk_mem_gen_v8_3_5 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(1),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("blk_mem_gen_arb.mif"),
.C_INIT_FILE("blk_mem_gen_arb.mem"),
.C_USE_DEFAULT_DATA(1),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_READ_WIDTH_A(12),
.C_WRITE_DEPTH_A(65536),
.C_READ_DEPTH_A(65536),
.C_ADDRA_WIDTH(16),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(1),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(12),
.C_READ_WIDTH_B(12),
.C_WRITE_DEPTH_B(65536),
.C_READ_DEPTH_B(65536),
.C_ADDRB_WIDTH(16),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(1),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("22"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 18.3292 mW")
) inst (
.clka(clka),
.rsta(1\'D0),
.ena(ena),
.regcea(1\'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(),
.clkb(clkb),
.rstb(1\'D0),
.enb(enb),
.regceb(1\'D0),
.web(1\'B0),
.addrb(addrb),
.dinb(12\'B0),
.doutb(doutb),
.injectsbiterr(1\'D0),
.injectdbiterr(1\'D0),
.eccpipece(1\'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1\'D0),
.deepsleep(1\'D0),
.shutdown(1\'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1\'H0),
.s_aresetn(1\'D0),
.s_axi_awid(4\'B0),
.s_axi_awaddr(32\'B0),
.s_axi_awlen(8\'B0),
.s_axi_awsize(3\'B0),
.s_axi_awburst(2\'B0),
.s_axi_awvalid(1\'D0),
.s_axi_awready(),
.s_axi_wdata(12\'B0),
.s_axi_wstrb(1\'B0),
.s_axi_wlast(1\'D0),
.s_axi_wvalid(1\'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1\'D0),
.s_axi_arid(4\'B0),
.s_axi_araddr(32\'B0),
.s_axi_arlen(8\'B0),
.s_axi_arsize(3\'B0),
.s_axi_arburst(2\'B0),
.s_axi_arvalid(1\'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1\'D0),
.s_axi_injectsbiterr(1\'D0),
.s_axi_injectdbiterr(1\'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Tue Mar 28 02:08:39 2017
// Host : DESKTOP-B1QME94 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dds_compiler_0_stub.v
// Design : dds_compiler_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "dds_compiler_v6_0_13,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, s_axis_phase_tvalid,
s_axis_phase_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_phase_tvalid,s_axis_phase_tdata[23:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]" */;
input aclk;
input s_axis_phase_tvalid;
input [23:0]s_axis_phase_tdata;
output m_axis_data_tvalid;
output [15:0]m_axis_data_tdata;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11.03.2017 18:31:22
// Design Name:
// Module Name: main
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module square(input clksamp,
input[31:0] freq,
input signed[16:0] amp,
input signed[16:0] offset,
input[9:0] duty,
output[11:0] sq);
parameter SAMP_FREQ = 100_000_000;
reg state = 1'b0;
reg[15:0] period_counter = 16'b0;
reg[15:0] duty_counter = 16'b0;
wire[15:0] period_load = (SAMP_FREQ/freq);
wire[15:0] duty_load = (period_load * duty) / 1000;
reg[15:0] period_load_reg = 32'b0;
reg[15:0] duty_load_reg = 32'b0;
always @(posedge clksamp) begin
period_load_reg <= period_load;
duty_load_reg <= duty_load;
period_counter <= (period_load_reg != period_load) ? period_load_reg - 1 : (period_counter > 0) ? period_counter - 1 : period_load_reg - 1;
duty_counter <= (duty_load_reg != duty_load) ? duty_load_reg - 1 : (duty_counter > 0) ? duty_counter - 1 : (period_counter > 0) ? 0 : duty_load_reg - 1;
state <= (duty_counter == 0 && period_counter > 0) ? 0 : 1;
end
wire signed[16:0] preclip = state ? offset + amp : offset - amp;
assign sq = (freq == 0 || amp == 0) ? offset > 4095 ? 4095 : offset : duty == 0 ? 0 : preclip > 4095 ? 4095 : preclip < 0 ? 0 : preclip;
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14.03.2017 18:36:26
// Design Name:
// Module Name: main
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//Inspired by https://github.com/tlautrec/EE2020_FPGA_project/blob/master/project.srcs/sources_1/imports/skeleton_sources/vga_ctrl.vhd
module vga_ctrl(
input clkvga,
output reg active,
output reg hs = 0,
output reg vs = 0,
output reg[10:0] hc = 0,
output reg[10:0] vc = 0
);
parameter width = 800;
parameter height = 600;
parameter H_FP = 56;
parameter H_PW = 120;
parameter H_MAX = 1040;
parameter V_FP = 37;
parameter V_PW = 6;
parameter V_MAX = 666;
always @(posedge clkvga) begin
hc <= (hc == H_MAX - 1) ? 0 : hc + 1;
if((hc == (H_MAX - 1)) && (vc == (V_MAX - 1)))
vc <= 0;
else if(hc == (H_MAX - 1))
vc <= vc + 1;
hs <= (hc >= (H_FP + width - 1)) && (hc < (H_FP + width + H_PW - 1)) ? 1 : 0;
vs <= (vc >= (V_FP + height - 1)) && (vc < (V_FP + height + V_PW - 1)) ? 1 : 0;
active <= (hc < width && vc < height);
end
endmodule
//Rest created with python script and coe file from https://forums.xilinx.com/t5/Spartan-Family-FPGAs/Character-ROM-generation/m-p/46351#M3721
module alphanum(
input [10:0] hc,
input [10:0] vc,
input [10:0] hs,
input [10:0] vs,
output reg yes
);
parameter code = 0;
parameter x_wrap = 0;
always @ (*) begin
case (code)
\t\t\t//A
\t\t\t8'd65:yes=((hc==hs+1||hc==hs+7)&&(vc>=vs+5&&vc<=vs+11))||((hc==hs+2||hc==hs+6)&&(vc>=vs+4&&vc<=vs+11))||((hc==hs+3||hc==hs+5)&&((vc>=vs+3&&vc<=vs+4)||(vc==vs+8)))||((hc==hs+4)&&((vc>=vs+2&&vc<=vs+3)||(vc==vs+8)));
\t\t\t//B
\t\t\t8'd66:yes=((hc==hs+1||hc==hs+6)&&(vc==vs+2||vc==vs+11))||((hc==hs+2||hc==hs+3)&&(vc>=vs+2&&vc<=vs+11))||((hc==hs+4||hc==hs+5)&&(vc==vs+2||vc==vs+6||vc==vs+11))||((hc==hs+7)&&((vc>=vs+3&&vc<=vs+5)||(vc>=vs+7&&vc<=vs+10)));
\t\t\t//C
\t\t\t8'd67:yes=((hc==hs+1)&&(vc>=vs+4&&vc<=vs+9))||((hc==hs+2)&&(vc>=vs+3&&vc<=vs+10))||((hc==hs+3||hc==hs+6)&&((vc>=vs+2&&vc<=vs+3)||(vc>=vs+10&&vc<=vs+11)))||((hc==hs+4||hc==hs+5)&&(vc==vs+2||vc==vs+11))||((hc==hs+7)&&((vc>=vs+3&&vc<=vs+4)||(vc>=vs+9&&vc<=vs+10)));
\t\t\t//D
\t\t\t8'd68:yes=((hc==hs+1||hc==hs+4)&&(vc==vs+2||vc==vs+11))||((hc==hs+2||hc==hs+3)&&(vc>=vs+2&&vc<=vs+11))||((hc==hs+5)&&((vc>=vs+2&&vc<=vs+11)||(vc>=vs+10&&vc<=vs+11)))||((hc==hs+6)&&(vc>=vs+3&&vc<=vs+10))||((hc==hs+7)&&(vc>=vs+4&&vc==vs+9));
\t\t\t//E
\t\t\t8'd69:yes=((hc==hs+1)&&(vc==vs+2||vc==vs+11))||((hc==hs+2||hc==hs+3)&&(vc>=vs+2&&vc<=vs+11))||((hc==hs+4)&&(vc==vs+2||vc==vs+6||vc==vs+11))||((hc==hs+5)&&(vc==vs+2||(vc>=vs+5&&vc<=vs+7)||vc==vs+11))||((hc==hs+6)&&((vc>=vs+2&&vc<=vs+3)||(vc>=vs+10&&vc<=vs+11)))||((hc==hs+7)&&((vc>=vs+2&&vc<=vs+4)||(vc>=vs+9&&vc<=vs+11)));
\t\t\t//F
\t\t\t8'd70:yes=((hc==hs+1)&&(vc==vs+2||vc==vs+11))||((hc==hs+2||hc==hs+3)&&(vc>=vs+2&&vc<=vs+11))||((hc==hs+4)&&(vc==vs+2||vc==vs+6||vc==vs+11))||((hc==hs+5)&&(vc==vs+2||(vc>=vs+5&&vc<=vs+7)))||((hc==hs+6)&&(vc>=vs+2&&vc<=vs+3))||((hc==hs+7)&&(vc>=vs+2&&vc<=vs+4));
\t\t\t//G
\t\t\t8'd71:yes=((vc==vs+2)&&((hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+3)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+4)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||0))||((vc==vs+5)&&((hc==hs+1)||(hc==hs+2)||0))||((vc==vs+6)&&((hc==hs+1)||(hc==hs+2)||0))||((vc==vs+7)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+8)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+9)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+10)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+11)&&((hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+7)||0))||0;
\t\t\t//H
\t\t\t8'd72:yes=((vc==vs+2)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+3)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+4)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+5)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+6)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+7)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+8)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+9)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+10)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+11)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||0;
\t\t\t//I
\t\t\t8'd73:yes=((vc==vs+2)&&((hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+3)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+4)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+5)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+6)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+7)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+8)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+9)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+10)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+11)&&((hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||0;
\t\t\t//J
\t\t\t8'd74:yes=((vc==vs+2)&&((hc==hs+4)||(hc==hs+5)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+3)&&((hc==hs+5)||(hc==hs+6)||0))||((vc==vs+4)&&((hc==hs+5)||(hc==hs+6)||0))||((vc==vs+5)&&((hc==hs+5)||(hc==hs+6)||0))||((vc==vs+6)&&((hc==hs+5)||(hc==hs+6)||0))||((vc==vs+7)&&((hc==hs+5)||(hc==hs+6)||0))||((vc==vs+8)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+9)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+10)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+11)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||0))||0;
\t\t\t//K
\t\t\t8'd75:yes=((vc==vs+2)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+3)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+4)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+5)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+6)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||0))||((vc==vs+7)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||0))||((vc==vs+8)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+9)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+10)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+11)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||0;
\t\t\t//L
\t\t\t8'd76:yes=((vc==vs+2)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+4)||0))||((vc==vs+3)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+4)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+5)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+6)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+7)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+8)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+9)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+7)||0))||((vc==vs+10)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+11)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||(hc==hs+7)||0))||0;
\t\t\t//M
\t\t\t8'd77:yes=((vc==vs+2)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+3)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+4)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+5)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+6)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+4)||(hc==hs+5)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+7)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+8)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+9)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+10)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+11)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||0;
\t\t\t//N
\t\t\t8'd78:yes=((vc==vs+2)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+3)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+4)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+5)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+6)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+7)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+5)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+8)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+9)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+10)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+11)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||0;
\t\t\t//O
\t\t\t8'd79:yes=((vc==vs+2)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+3)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+4)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+5)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+6)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+7)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+8)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+9)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+10)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+11)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||0;
\t\t\t//P
\t\t\t8'd80:yes=((vc==vs+2)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+3)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+4)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+5)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+6)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+7)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+8)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+9)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+10)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+11)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+4)||0))||0;
\t\t\t//Q
\t\t\t8'd81:yes=((vc==vs+2)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+3)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+4)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+5)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+6)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+7)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+8)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+9)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+4)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+10)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+11)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+12)&&((hc==hs+5)||(hc==hs+6)||0))||((vc==vs+13)&&((hc==hs+5)||(hc==hs+6)||(hc==hs+7)||0))||0;
\t\t\t//R
\t\t\t8'd82:yes=((vc==vs+2)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+3)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+4)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+5)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+6)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+7)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+8)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+9)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+10)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+11)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||0;
\t\t\t//S
\t\t\t8'd83:yes=((vc==vs+2)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+3)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+4)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+5)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+6)&&((hc==hs+3)||(hc==hs+4)||(hc==hs+5)||0))||((vc==vs+7)&&((hc==hs+5)||(hc==hs+6)||0))||((vc==vs+8)&&((hc==hs+6)||(hc==hs+7)||0))||((vc==vs+9)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+10)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+11)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||0;
\t\t\t//T
\t\t\t8'd84:yes=((vc==vs+2)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+3)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+4)||(hc==hs+5)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+4)&&((hc==hs+1)||(hc==hs+4)||(hc==hs+5)||(hc==hs+8)||0))||((vc==vs+5)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+6)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+7)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+8)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+9)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+10)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+11)&&((hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||0;
\t\t\t//U
\t\t\t8'd85:yes=((vc==vs+2)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+3)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+4)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+5)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+6)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+7)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+8)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+9)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+10)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+11)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||0;
\t\t\t//V
\t\t\t8'd86:yes=((vc==vs+2)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+3)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+4)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+5)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+6)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+7)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+8)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+9)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+10)&&((hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+11)&&((hc==hs+4)||(hc==hs+5)||0))||0;
\t\t\t//W
\t\t\t8'd87:yes=((vc==vs+2)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+3)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+4)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+5)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+6)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+7)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+4)||(hc==hs+5)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+8)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+4)||(hc==hs+5)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+9)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+10)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+11)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||0;
\t\t\t//X
\t\t\t8'd88:yes=((vc==vs+2)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+3)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+4)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+5)&&((hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+6)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+7)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+8)&&((hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+9)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+10)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+11)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||0;
\t\t\t//Y
\t\t\t8'd89:yes=((vc==vs+2)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+3)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+4)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+5)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+6)&&((hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+7)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+8)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+9)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+10)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+11)&&((hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||0;
\t\t\t//Z
\t\t\t8'd90:yes=((vc==vs+2)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+3)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+4)&&((hc==hs+1)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+5)&&((hc==hs+5)||(hc==hs+6)||0))||((vc==vs+6)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+7)&&((hc==hs+3)||(hc==hs+4)||0))||((vc==vs+8)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+9)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+8)||0))||((vc==vs+10)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+11)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||(hc==hs+7)||(hc==hs+8)||0))||0;
\t\t\t//a
\t\t\t8'd97:yes=((vc==vs+4)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||0))||((vc==vs+5)&&((hc==hs+5)||(hc==hs+6)||0))||((vc==vs+6)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+7)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+8)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+9)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+10)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+6)||(hc==hs+7)||0))||0;
\t\t\t//b
\t\t\t8'd98:yes=((vc==vs+1)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||0))||((vc==vs+2)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+3)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+4)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||0))||((vc==vs+5)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+6)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+7)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+8)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+9)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+10)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||0;
\t\t\t//c
\t\t\t8'd99:yes=((vc==vs+4)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+5)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+6)&&((hc==hs+1)||(hc==hs+2)||0))||((vc==vs+7)&&((hc==hs+1)||(hc==hs+2)||0))||((vc==vs+8)&&((hc==hs+1)||(hc==hs+2)||0))||((vc==vs+9)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+10)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||0;
\t\t\t//d
\t\t\t8'd100:yes=((vc==vs+1)&&((hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+2)&&((hc==hs+5)||(hc==hs+6)||0))||((vc==vs+3)&&((hc==hs+5)||(hc==hs+6)||0))||((vc==vs+4)&&((hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+5)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+6)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+7)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+8)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+9)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+10)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+6)||(hc==hs+7)||0))||0;
\t\t\t//e
\t\t\t8'd101:yes=((vc==vs+4)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+5)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+6)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+7)&&((hc==hs+1)||(hc==hs+2)||0))||((vc==vs+8)&&((hc==hs+1)||(hc==hs+2)||0))||((vc==vs+9)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+10)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||0;
\t\t\t//f
\t\t\t8'd102:yes=((vc==vs+1)&&((hc==hs+3)||(hc==hs+4)||(hc==hs+5)||0))||((vc==vs+2)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+3)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||0))||((vc==vs+4)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+5)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+4)||0))||((vc==vs+6)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+7)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+8)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+9)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+10)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+4)||0))||0;
\t\t\t//g
\t\t\t8'd103:yes=((vc==vs+4)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+5)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+6)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+7)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+8)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+9)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+10)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+11)&&((hc==hs+5)||(hc==hs+6)||0))||((vc==vs+12)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+13)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||0))||0;
\t\t\t//h
\t\t\t8'd104:yes=((vc==vs+1)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||0))||((vc==vs+2)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+3)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+4)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+5)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+6)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+7)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+8)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+9)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+10)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||0;
\t\t\t//i
\t\t\t8'd105:yes=((vc==vs+1)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+2)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+4)&&((hc==hs+3)||(hc==hs+4)||(hc==hs+5)||0))||((vc==vs+5)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+6)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+7)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+8)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+9)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+10)&&((hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||0;
\t\t\t//j
\t\t\t8'd106:yes=((vc==vs+1)&&((hc==hs+6)||(hc==hs+7)||0))||((vc==vs+2)&&((hc==hs+6)||(hc==hs+7)||0))||((vc==vs+4)&&((hc==hs+5)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+5)&&((hc==hs+6)||(hc==hs+7)||0))||((vc==vs+6)&&((hc==hs+6)||(hc==hs+7)||0))||((vc==vs+7)&&((hc==hs+6)||(hc==hs+7)||0))||((vc==vs+8)&&((hc==hs+6)||(hc==hs+7)||0))||((vc==vs+9)&&((hc==hs+6)||(hc==hs+7)||0))||((vc==vs+10)&&((hc==hs+6)||(hc==hs+7)||0))||((vc==vs+11)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+12)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+13)&&((hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||0;
\t\t\t//k
\t\t\t8'd107:yes=((vc==vs+1)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||0))||((vc==vs+2)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+3)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+4)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+5)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+6)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||0))||((vc==vs+7)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||0))||((vc==vs+8)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+9)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+10)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||0;
\t\t\t//l
\t\t\t8'd108:yes=((vc==vs+1)&&((hc==hs+3)||(hc==hs+4)||(hc==hs+5)||0))||((vc==vs+2)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+3)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+4)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+5)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+6)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+7)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+8)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+9)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+10)&&((hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||0;
\t\t\t//m
\t\t\t8'd109:yes=((vc==vs+4)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+5)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+6)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+4)||(hc==hs+5)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+7)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+4)||(hc==hs+5)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+8)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+4)||(hc==hs+5)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+9)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+4)||(hc==hs+5)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+10)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+4)||(hc==hs+5)||(hc==hs+7)||(hc==hs+8)||0))||0;
\t\t\t//n
\t\t\t8'd110:yes=((vc==vs+4)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+5)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+6)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+7)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+8)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+9)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+10)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||0;
\t\t\t//o
\t\t\t8'd111:yes=((vc==vs+4)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+5)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+6)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+7)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+8)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+9)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+10)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||0;
\t\t\t//p
\t\t\t8'd112:yes=((vc==vs+4)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+5)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+6)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+7)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+8)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+9)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+10)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+11)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+12)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+13)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+4)||0))||0;
\t\t\t//q
\t\t\t8'd113:yes=((vc==vs+4)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+5)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+6)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+7)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+8)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+9)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+10)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+11)&&((hc==hs+5)||(hc==hs+6)||0))||((vc==vs+12)&&((hc==hs+5)||(hc==hs+6)||0))||((vc==vs+13)&&((hc==hs+4)||(hc==hs+5)||(hc==hs+6)||(hc==hs+7)||0))||0;
\t\t\t//r
\t\t\t8'd114:yes=((vc==vs+4)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+5)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+6)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+7)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+8)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+9)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+10)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+4)||0))||0;
\t\t\t//s
\t\t\t8'd115:yes=((vc==vs+4)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+5)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+6)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+7)&&((hc==hs+3)||(hc==hs+4)||(hc==hs+5)||0))||((vc==vs+8)&&((hc==hs+5)||(hc==hs+6)||0))||((vc==vs+9)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+10)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||0;
\t\t\t//t
\t\t\t8'd116:yes=((vc==vs+1)&&((hc==hs+4)||0))||((vc==vs+2)&&((hc==hs+3)||(hc==hs+4)||0))||((vc==vs+3)&&((hc==hs+3)||(hc==hs+4)||0))||((vc==vs+4)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+5)&&((hc==hs+3)||(hc==hs+4)||0))||((vc==vs+6)&&((hc==hs+3)||(hc==hs+4)||0))||((vc==vs+7)&&((hc==hs+3)||(hc==hs+4)||0))||((vc==vs+8)&&((hc==hs+3)||(hc==hs+4)||0))||((vc==vs+9)&&((hc==hs+3)||(hc==hs+4)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+10)&&((hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||0;
\t\t\t//u
\t\t\t8'd117:yes=((vc==vs+4)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+5)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+6)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+7)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+8)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+9)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+10)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+6)||(hc==hs+7)||0))||0;
\t\t\t//v
\t\t\t8'd118:yes=((vc==vs+4)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+5)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+6)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+7)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+8)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+9)&&((hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+10)&&((hc==hs+4)||(hc==hs+5)||0))||0;
\t\t\t//w
\t\t\t8'd119:yes=((vc==vs+4)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+5)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+6)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+7)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+4)||(hc==hs+5)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+8)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+4)||(hc==hs+5)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+9)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+10)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||0;
\t\t\t//x
\t\t\t8'd120:yes=((vc==vs+4)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||((vc==vs+5)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+6)&&((hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+7)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+8)&&((hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+9)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+10)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+7)||(hc==hs+8)||0))||0;
\t\t\t//y
\t\t\t8'd121:yes=((vc==vs+4)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+5)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+6)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+7)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+8)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+9)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+10)&&((hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+11)&&((hc==hs+6)||(hc==hs+7)||0))||((vc==vs+12)&&((hc==hs+5)||(hc==hs+6)||0))||((vc==vs+13)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||0))||0;
\t\t\t//z
\t\t\t8'd122:yes=((vc==vs+4)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+5)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+5)||(hc==hs+6)||0))||((vc==vs+6)&&((hc==hs+4)||(hc==hs+5)||0))||((vc==vs+7)&&((hc==hs+3)||(hc==hs+4)||0))||((vc==vs+8)&&((hc==hs+2)||(hc==hs+3)||0))||((vc==vs+9)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+6)||(hc==hs+7)||0))||((vc==vs+10)&&((hc==hs+1)||(hc==hs+2)||(hc==hs+3)||(hc==hs+4)||(hc==hs+5)||(hc==hs+6)||(hc==hs+7)||0))||0;
\t\t\tdefault:yes=0;
\t\tendcase
\tend
endmodule
module clickable_num6_left(input[17:0] num, input[3:0] th, input[3:0] hun, input[3:0] ten, input[3:0] ones, input[10:0] hc, input[10:0] vc, input[10:0] hs, input[10:0] vs, input[10:0] mx, input[10:0] my, output text_out, output within);
parameter x_width = 15;
parameter x_space = 8;
parameter y_width = 30;
wire [5:0] text;
wire [3:0] hth;
wire [3:0] tth;
assign hth = (num % 1000000) / 100000;
assign tth = (num % 100000) / 10000;
vga_seg a1(hth, hc, vc, hs, vs, text[5]);
vga_seg a2(tth, hc, vc, hs+x_width+x_space, vs, text[4]);
vga_seg a3(th, hc, vc, hs+x_width+x_space+x_width+x_space, vs, text[3]);
vga_seg a4(hun, hc, vc, hs+x_width+x_space+x_width+x_space+x_width+x_space, vs, text[2]);
vga_seg a5(ten, hc, vc, hs+x_width+x_space+x_width+x_space+x_width+x_space+x_width+x_space, vs, text[1]);
vga_seg a6(ones, hc, vc, hs+x_width+x_space+x_width+x_space+x_width+x_space+x_width+x_space+x_width+x_space, vs, text[0]);
assign text_out = (( | hth ) ? ( | text[5:0] ) :
( | tth ) ? ( | text[4:0] ) :
( | th ) ? ( | text[3:0] ) :
( | hun ) ? ( | text[2:0] ) :
( | ten ) ? ( | text[1:0] ) :
text[0])? 1 : 0;
assign within = (mx>=hs && mx<=hs+x_width+x_space+x_width+x_space+x_width+x_space+x_width+x_space+x_width+x_space+x_width && my>=vs && my<=vs+y_width);
endmodule
module clickable_num6_right(input[17:0] num, input[3:0] th, input[3:0] hun, input[3:0] ten, input[3:0] ones, input[10:0] hc, input[10:0] vc, input[10:0] hs, input[10:0] vs, input[10:0] mx, input[10:0] my, output text_out, output within);
parameter x_width = 15;
parameter x_space = 8;
parameter y_width = 30;
wire [5:0] text;
wire [3:0] hth;
wire [3:0] tth;
assign hth = (num % 1000000) / 100000;
assign tth = (num % 100000) / 10000;
wire hth_ne = ( | hth );
wire tth_ne = ( | tth );
wire th_ne = ( | th );
wire hun_ne = ( | hun );
wire ten_ne = ( | ten );
wire[3:0] d1 = hth_ne ? hth :
tth_ne ? tth :
th_ne ? th :
hun_ne ? hun :
ten_ne ? ten : ones;
wire[3:0] d2 = hth_ne ? tth :
\t\t\t tth_ne ? th :
\t\t\t th_ne ? hun :
\t\t\t hun_ne ? ten : ones;
wire[3:0] d3 = hth_ne ? th :
\t\t\t tth_ne ? hun :
\t\t\t th_ne ? ten : ones;
wire[3:0] d4 = hth_ne ? hun :
\t\t\t tth_ne ? ten : ones;
wire[3:0] d5 = hth_ne ? ten : ones;
wire[3:0] d6 = ones;
vga_seg a1(d1, hc, vc, hs, vs, text[5]);
vga_seg a2(d2, hc, vc, hs+x_width+x_space, vs, text[4]);
vga_seg a3(d3, hc, vc, hs+x_width+x_space+x_width+x_space, vs, text[3]);
vga_seg a4(d4, hc, vc, hs+x_width+x_space+x_width+x_space+x_width+x_space, vs, text[2]);
vga_seg a5(d5, hc, vc, hs+x_width+x_space+x_width+x_space+x_width+x_space+x_width+x_space, vs, text[1]);
vga_seg a6(d6, hc, vc, hs+x_width+x_space+x_width+x_space+x_width+x_space+x_width+x_space+x_width+x_space, vs, text[0]);
assign text_out = (hth_ne ? ( | text[5:0] ) :
tth_ne ? ( | text[5:1] ) :
th_ne ? ( | text[5:2] ) :
hun_ne ? ( | text[5:3] ) :
ten_ne ? ( | text[5:4] ) :
text[5] )? 1 : 0;
assign within = (mx>=hs && mx<=hs+x_width+x_space+x_width+x_space+x_width+x_space+x_width+x_space+x_width+x_space+x_width && my>=vs && my<=vs+y_width);
endmodule
module clickable_num4(input[15:0] num, input[3:0] th, input[3:0] hun, input[3:0] ten, input[3:0] ones, input[10:0] hc, input[10:0] vc, input[10:0] hs, input[10:0] vs, input[10:0] mx, input[10:0] my, output text_out, output within);
parameter x_width = 15;
parameter x_space = 8;
wire [4:0] text;
vga_seg a3(th, hc, vc, hs, vs, text[3]);
vga_seg a4(hun, hc, vc, hs+x_width+x_space, vs, text[2]);
vga_seg a5(ten, hc, vc, hs+x_width+x_space+x_width+x_space, vs, text[1]);
vga_seg a6(ones, hc, vc, hs+x_width+x_space+x_width+x_space+x_width+x_space, vs, text[0]);
assign text_out = (( | th ) ? ( | text[3:0] ) :
( | hun ) ? ( | text[2:0] ) :
( | ten ) ? ( | text[1:0] ) :
text[0])? 1 : 0;
assign within = (mx>=hs && mx<=hs+120 && my>=vs && my<=vs+30);
endmodule
module region_mouse_white(input[10:0] x, input[10:0] y, input[10:0] mx, input[10:0] my, output[3:0] yes);
assign yes = (((y==(my+1))&&((x==(mx+1))||0))||((y==(my+2))&&((x==(mx+1))||(x==(mx+2))||0))||((y==(my+3))&&((x==(mx+1))||(x==(mx+2))||(x==(mx+3))||0))||((y==(my+4))&&((x==(mx+1))||(x==(mx+2))||(x==(mx+3))||(x==(mx+4))||0))||((y==(my+5))&&((x==(mx+1))||(x==(mx+2))||(x==(mx+3))||(x==(mx+4))||(x==(mx+5))||0))||((y==(my+6))&&((x==(mx+1))||(x==(mx+2))||(x==(mx+3))||(x==(mx+4))||(x==(mx+5))||(x==(mx+6))||0))||((y==(my+7))&&((x==(mx+1))||(x==(mx+2))||(x==(mx+3))||(x==(mx+4))||(x==(mx+5))||(x==(mx+6))||(x==(mx+7))||0))||((y==(my+8))&&((x==(mx+1))||(x==(mx+2))||(x==(mx+3))||(x==(mx+4))||(x==(mx+5))||0))||((y==(my+9))&&((x==(mx+1))||(x==(mx+2))||(x==(mx+3))||(x==(mx+4))||(x==(mx+5))||0))||((y==(my+10))&&((x==(mx+1))||(x==(mx+4))||(x==(mx+5))||0))||((y==(my+11))&&((x==(mx+5))||(x==(mx+6))||0))||((y==(my+12))&&((x==(mx+5))||(x==(mx+6))||0))||((y==(my+13))&&((x==(mx+6))||(x==(mx+7))||0))||((y==(my+14))&&((x==(mx+6))||(x==(mx+7))||0))||0) ? 4'b1111 : 4'b0;
endmodule
module region_mouse_black(input[10:0] x, input[10:0] y, input[10:0] mx, input[10:0] my, output[3:0] yes);
assign yes = (((y==(my+0))&&((x==(mx+0))||(x==(mx+1))||0))||((y==(my+1))&&((x==(mx+0))||(x==(mx+2))||0))||((y==(my+2))&&((x==(mx+0))||(x==(mx+3))||0))||((y==(my+3))&&((x==(mx+0))||(x==(mx+4))||0))||((y==(my+4))&&((x==(mx+0))||(x==(mx+5))||0))||((y==(my+5))&&((x==(mx+0))||(x==(mx+6))||0))||((y==(my+6))&&((x==(mx+0))||(x==(mx+7))||0))||((y==(my+7))&&((x==(mx+0))||(x==(mx+8))||0))||((y==(my+8))&&((x==(mx+0))||(x==(mx+6))||(x==(mx+7))||(x==(mx+8))||(x==(mx+9))||0))||((y==(my+9))&&((x==(mx+0))||(x==(mx+6))||0))||((y==(my+10))&&((x==(mx+0))||(x==(mx+2))||(x==(mx+3))||(x==(mx+6))||0))||((y==(my+11))&&((x==(mx+0))||(x==(mx+1))||(x==(mx+4))||(x==(mx+7))||0))||((y==(my+12))&&((x==(mx+0))||(x==(mx+4))||(x==(mx+7))||0))||((y==(my+13))&&((x==(mx+5))||(x==(mx+8))||0))||((y==(my+14))&&((x==(mx+5))||(x==(mx+8))||0))||((y==(my+15))&&((x==(mx+6))||(x==(mx+7))||0))||0) ? 4'b1111 : 4'b0;
endmodule
module vga_seg(
input [3:0] num,
input [10:0] hc,
input [10:0] vc,
input [10:0] hs,
input [10:0] vs,
output yes);
wire a = (hc>=hs+2 && hc<=hs+13 && vc>=vs && vc<=vs+2);
wire b = (hc>=hs+13 && hc<=hs+15 && vc>=vs+2 && vc<=vs+14);
wire c = (hc>=hs+13 && hc<=hs+15 && vc>=vs+16 && vc<=vs+28);
wire d = (hc>=hs+2 && hc<=hs+13 && vc>=vs+28 && vc<=vs+30);
wire e = (hc>=hs && hc<=hs+2 && vc>=vs+16 && vc<=vs+28);
wire f = (hc>=hs && hc<=hs+2 && vc>=vs+2 && vc<=vs+14);
wire g = (hc>=hs+2 && hc<=hs+13 && vc>=vs+14 && vc<=vs+16);
assign yes = (num == 0) ? a|b|c|d|e|f :
(num == 1) ? b|c :
(num == 2) ? a|b|d|e|g :
(num == 3) ? a|b|c|d|g :
(num == 4) ? b|c|f|g :
(num == 5) ? a|c|d|f|g :
(num == 6) ? a|c|d|e|f|g :
(num == 7) ? a|b|c :
(num == 8) ? a|b|c|d|e|f|g :
(num == 9) ? a|b|c|d|f|g : 0;
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
\tinput [31:0] x;
\toutput [31:0] y;
\tassign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
\tinput [31:0] x;
\toutput [31:0] y;
\tassign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
\tinput [31:0] x, y, z;
\toutput [31:0] o;
\tassign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
\tinput [31:0] x, y, z;
\toutput [31:0] o;
\tassign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
\tinput [31:0] x;
\toutput [31:0] y;
\tassign y[31:29] = x[6:4] ^ x[17:15];
\tassign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
\tinput [31:0] x;
\toutput [31:0] y;
\tassign y[31:22] = x[16:7] ^ x[18:9];
\tassign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
/* wb_cdc. Part of wb_intercon
*
* ISC License
*
* Copyright (C) 2016 Olof Kindgren <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/*Wishbone Clock-domain crossing core.
TODO:
- Bursts
- Pipelining
*/
module wb_cdc
#(parameter AW = 32)
(input wire\t\twbm_clk,
input wire\t\twbm_rst,
input wire [AW-1:0]\twbm_adr_i,
input wire [31:0]\twbm_dat_i,
input wire [3:0]\twbm_sel_i,
input wire\t\twbm_we_i,
input wire\t\twbm_cyc_i,
input wire\t\twbm_stb_i,
output wire [31:0]\twbm_dat_o,
output wire\t\twbm_ack_o,
input wire\t\twbs_clk,
input wire\t\twbs_rst,
output wire [AW-1:0]\twbs_adr_o,
output wire [31:0]\twbs_dat_o,
output wire [3:0]\twbs_sel_o,
output wire\t\twbs_we_o,
output wire\t\twbs_cyc_o,
output wire\t\twbs_stb_o,
input wire [31:0]\twbs_dat_i,
input wire\t\twbs_ack_i);
wire \t wbm_m2s_en;
reg \t\t wbm_busy = 1\'b0;
wire \t wbm_cs;
wire \t wbm_done;
wire \t wbs_m2s_en;
reg \t\t wbs_cs = 1\'b0;
cc561
#(.DW (AW+32+4+1))
cdc_m2s
(.aclk (wbm_clk),
.arst (wbm_rst),
.adata ({wbm_adr_i, wbm_dat_i, wbm_sel_i, wbm_we_i}),
.aen (wbm_m2s_en),
.bclk (wbs_clk),
.bdata ({wbs_adr_o, wbs_dat_o, wbs_sel_o, wbs_we_o}),
.ben (wbs_m2s_en));
assign wbm_cs = wbm_cyc_i & wbm_stb_i;
assign wbm_m2s_en = wbm_cs & ~wbm_busy;
always @(posedge wbm_clk) begin
if (wbm_ack_o | wbm_rst)
\twbm_busy <= 1\'b0;
else if (wbm_cs)
\twbm_busy <= 1\'b1;
end
always @(posedge wbs_clk) begin
if (wbs_ack_i)
\twbs_cs <= 1\'b0;
else if (wbs_m2s_en)
\twbs_cs <= 1\'b1;
end
assign wbs_cyc_o = wbs_m2s_en | wbs_cs;
assign wbs_stb_o = wbs_m2s_en | wbs_cs;
cc561
#(.DW (32))
cdc_s2m
(.aclk (wbs_clk),
.arst (wbs_rst),
.adata (wbs_dat_i),
.aen (wbs_ack_i),
.bclk (wbm_clk),
.bdata (wbm_dat_o),
.ben (wbm_ack_o));
endmodule
|
/* wb_cdc_tb. Part of wb_intercon
*
* ISC License
*
* Copyright (C) 2019 Olof Kindgren <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/*Testbench for wb_cdc
*/
`default_nettype none
module wb_cdc_tb
#(parameter AUTORUN = 1);
localparam aw = 32;
localparam dw = 32;
localparam MEM_SIZE = 256;
reg wbm_clk = 1\'b1;
reg wbm_rst = 1\'b1;
reg wbs_clk = 1\'b1;
reg wbs_rst = 1\'b1;
wire [aw-1:0] wbm_m2s_adr;
wire [dw-1:0] wbm_m2s_dat;
wire [3:0] \t wbm_m2s_sel;
wire \t wbm_m2s_we ;
wire \t wbm_m2s_cyc;
wire \t wbm_m2s_stb;
wire [dw-1:0] wbm_s2m_dat;
wire \t wbm_s2m_ack;
wire [aw-1:0] wbs_m2s_adr;
wire [dw-1:0] wbs_m2s_dat;
wire [3:0] \t wbs_m2s_sel;
wire \t wbs_m2s_we ;
wire \t wbs_m2s_cyc;
wire \t wbs_m2s_stb;
wire [dw-1:0] wbs_s2m_dat;
wire \t wbs_s2m_ack;
wire \t done;
integer TRANSACTIONS;
generate
if (AUTORUN) begin
vlog_tb_utils vtu();
vlog_tap_generator #("wb_cdc.tap", 1) vtg();
initial begin
run;
vtg.ok("wb_cdc: All tests passed!");
$finish;
end
end
endgenerate
task run;
begin
transactor.bfm.reset;
\t @(posedge wbs_clk) wbs_rst = 1\'b0;
\t @(posedge wbm_clk) wbm_rst = 1\'b0;
\t if($value$plusargs("transactions=%d", TRANSACTIONS))
\t transactor.set_transactions(TRANSACTIONS);
\t transactor.display_settings;
\t transactor.run();
\t transactor.display_stats;
end
endtask
always #5 wbm_clk <= ~wbm_clk;
always #3 wbs_clk <= ~wbs_clk;
wb_bfm_transactor
#(.MEM_HIGH (MEM_SIZE-1),
.AUTORUN (0),
.VERBOSE (0))
transactor
(.wb_clk_i (wbm_clk),
.wb_rst_i (1\'b0),
.wb_adr_o (wbm_m2s_adr),
.wb_dat_o (wbm_m2s_dat),
.wb_sel_o (wbm_m2s_sel),
.wb_we_o (wbm_m2s_we),
.wb_cyc_o (wbm_m2s_cyc),
.wb_stb_o (wbm_m2s_stb),
.wb_cti_o (),
.wb_bte_o (),
.wb_dat_i (wbm_s2m_dat),
.wb_ack_i (wbm_s2m_ack),
.wb_err_i (1\'b0),
.wb_rty_i (1\'b0),
//Test Control
.done());
wb_cdc
#(.AW(aw))
dut
(.wbm_clk (wbm_clk),
.wbm_rst (wbm_rst),
// Master Interface
.wbm_adr_i (wbm_m2s_adr),
.wbm_dat_i (wbm_m2s_dat),
.wbm_sel_i (wbm_m2s_sel),
.wbm_we_i (wbm_m2s_we ),
.wbm_cyc_i (wbm_m2s_cyc),
.wbm_stb_i (wbm_m2s_stb),
.wbm_dat_o (wbm_s2m_dat),
.wbm_ack_o (wbm_s2m_ack),
// Wishbone Slave interface
.wbs_clk (wbs_clk),
.wbs_rst (wbs_rst),
.wbs_adr_o (wbs_m2s_adr),
.wbs_dat_o (wbs_m2s_dat),
.wbs_sel_o (wbs_m2s_sel),
.wbs_we_o (wbs_m2s_we),
.wbs_cyc_o (wbs_m2s_cyc),
.wbs_stb_o (wbs_m2s_stb),
.wbs_dat_i (wbs_s2m_dat),
.wbs_ack_i (wbs_s2m_ack & !wbs_rst));
wb_bfm_memory
#(.DEBUG (0),
.mem_size_bytes(MEM_SIZE))
mem
(.wb_clk_i (wbs_clk),
.wb_rst_i (wbs_rst),
.wb_adr_i (wbs_m2s_adr),
.wb_dat_i (wbs_m2s_dat),
.wb_sel_i (wbs_m2s_sel),
.wb_we_i (wbs_m2s_we),
.wb_cyc_i (wbs_m2s_cyc),
.wb_stb_i (wbs_m2s_stb),
.wb_cti_i (3\'b000),
.wb_bte_i (2\'b00),
.wb_dat_o (wbs_s2m_dat),
.wb_ack_o (wbs_s2m_ack),
.wb_err_o (),
.wb_rty_o ());
endmodule
|
/* wb_upsizer_tb. Part of wb_intercon
*
* ISC License
*
* Copyright (C) 2019 Olof Kindgren <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module wb_upsizer_tb
(input wire wb_clk_i,
input wire wb_rst_i,
output wire done);
localparam aw = 32;
localparam MEMORY_SIZE_WORDS = 2**10;
localparam DW_IN = 32;
localparam SCALE = 2;
localparam DW_OUT = DW_IN * SCALE;
wire [aw-1:0] wbm_m2s_adr;
wire [DW_IN-1:0] wbm_m2s_dat;
wire [DW_IN/8-1:0] wbm_m2s_sel;
wire \t wbm_m2s_we ;
wire \t wbm_m2s_cyc;
wire \t wbm_m2s_stb;
wire [2:0] \t wbm_m2s_cti;
wire [1:0] \t wbm_m2s_bte;
wire [DW_IN-1:0] wbm_s2m_dat;
wire \t wbm_s2m_ack;
wire \t wbm_s2m_err;
wire \t wbm_s2m_rty;
wire [aw-1:0] wbs_m2s_adr;
wire [DW_OUT-1:0] wbs_m2s_dat;
wire [DW_OUT/8-1:0] wbs_m2s_sel;
wire \t wbs_m2s_we ;
wire \t wbs_m2s_cyc;
wire \t wbs_m2s_stb;
wire [2:0] \t wbs_m2s_cti;
wire [1:0] \t wbs_m2s_bte;
wire [DW_OUT-1:0] wbs_s2m_dat;
wire \t wbs_s2m_ack;
wire \t wbs_s2m_err;
wire \t wbs_s2m_rty;
wire [31:0] \t slave_writes;
wire [31:0] \t slave_reads;
wb_bfm_transactor
#(.MEM_HIGH(MEMORY_SIZE_WORDS-1),
.MEM_LOW (0),
.VERBOSE (0))
wb_bfm_transactor0
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_adr_o (wbm_m2s_adr),
.wb_dat_o (wbm_m2s_dat),
.wb_sel_o (wbm_m2s_sel),
.wb_we_o (wbm_m2s_we ),
.wb_cyc_o (wbm_m2s_cyc),
.wb_stb_o (wbm_m2s_stb),
.wb_cti_o (wbm_m2s_cti),
.wb_bte_o (wbm_m2s_bte),
.wb_dat_i (wbm_s2m_dat),
.wb_ack_i (wbm_s2m_ack),
.wb_err_i (wbm_s2m_err),
.wb_rty_i (wbm_s2m_rty),
//Test Control
.done(done));
integer \t idx;
always @(done) begin
if(done === 1) begin
\t $display("Average wait times");
\t $display("Master : %f", ack_delay/num_transactions);
\t $display("%0d : All tests passed!", $time);
end
end
wb_upsizer
#(.DW_IN (DW_IN),
.SCALE (SCALE))
dut
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
// Master Interface
.wbs_adr_i (wbm_m2s_adr),
.wbs_dat_i (wbm_m2s_dat),
.wbs_sel_i (wbm_m2s_sel),
.wbs_we_i (wbm_m2s_we ),
.wbs_cyc_i (wbm_m2s_cyc),
.wbs_stb_i (wbm_m2s_stb),
.wbs_cti_i (wbm_m2s_cti),
.wbs_bte_i (wbm_m2s_bte),
.wbs_dat_o (wbm_s2m_dat),
.wbs_ack_o (wbm_s2m_ack),
.wbs_err_o (wbm_s2m_err),
.wbs_rty_o (wbm_s2m_rty),
// Wishbone Slave interface
.wbm_adr_o (wbs_m2s_adr),
.wbm_dat_o (wbs_m2s_dat),
.wbm_sel_o (wbs_m2s_sel),
.wbm_we_o (wbs_m2s_we),
.wbm_cyc_o (wbs_m2s_cyc),
.wbm_stb_o (wbs_m2s_stb),
.wbm_cti_o (wbs_m2s_cti),
.wbm_bte_o (wbs_m2s_bte),
.wbm_dat_i (wbs_s2m_dat),
.wbm_ack_i (wbs_s2m_ack),
.wbm_err_i (wbs_s2m_err),
.wbm_rty_i (wbs_s2m_rty));
assign slave_writes = mem.writes;
assign slave_reads = mem.reads;
time start_time;
time ack_delay;
integer num_transactions;
initial begin
ack_delay = 0;
num_transactions = 0;
while(1) begin
\t @(posedge wbm_m2s_cyc);
\t start_time = $time;
\t @(posedge wbm_s2m_ack);
\t ack_delay = ack_delay + $time-start_time;
\t num_transactions = num_transactions+1;
end
end
wb_bfm_memory #(.DEBUG (0),
\t\t .dw (DW_OUT),
\t\t .mem_size_bytes(MEMORY_SIZE_WORDS*(DW_IN/8)))
mem
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_adr_i (wbs_m2s_adr),
.wb_dat_i (wbs_m2s_dat),
.wb_sel_i (wbs_m2s_sel),
.wb_we_i (wbs_m2s_we),
.wb_cyc_i (wbs_m2s_cyc),
.wb_stb_i (wbs_m2s_stb),
.wb_cti_i (wbs_m2s_cti),
.wb_bte_i (wbs_m2s_bte),
.wb_dat_o (wbs_s2m_dat),
.wb_ack_o (wbs_s2m_ack),
.wb_err_o (wbs_s2m_err),
.wb_rty_o (wbs_s2m_rty));
endmodule
|
/* wb_arbiter. Part of wb_intercon
*
* ISC License
*
* Copyright (C) 2013-2019 Olof Kindgren <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/*
Wishbone arbiter, burst-compatible
Simple round-robin arbiter for multiple Wishbone masters
*/
module wb_arbiter
#(parameter dw = 32,
parameter aw = 32,
parameter num_masters = 0)
(
input wire\t\t\t wb_clk_i,
input wire\t\t\t wb_rst_i,
// Wishbone Master Interface
input wire [num_masters*aw-1:0] wbm_adr_i,
input wire [num_masters*dw-1:0] wbm_dat_i,
input wire [num_masters*4-1:0] wbm_sel_i,
input wire [num_masters-1:0]\t wbm_we_i,
input wire [num_masters-1:0]\t wbm_cyc_i,
input wire [num_masters-1:0]\t wbm_stb_i,
input wire [num_masters*3-1:0] wbm_cti_i,
input wire [num_masters*2-1:0] wbm_bte_i,
output wire [num_masters*dw-1:0] wbm_dat_o,
output wire [num_masters-1:0] wbm_ack_o,
output wire [num_masters-1:0] wbm_err_o,
output wire [num_masters-1:0] wbm_rty_o,
// Wishbone Slave interface
output wire [aw-1:0]\t\t wbs_adr_o,
output wire [dw-1:0]\t\t wbs_dat_o,
output wire [3:0]\t\t wbs_sel_o,
output wire\t\t\t wbs_we_o,
output wire\t\t\t wbs_cyc_o,
output wire\t\t\t wbs_stb_o,
output wire [2:0]\t\t wbs_cti_o,
output wire [1:0]\t\t wbs_bte_o,
input wire [dw-1:0]\t\t wbs_dat_i,
input wire\t\t\t wbs_ack_i,
input wire\t\t\t wbs_err_i,
input wire\t\t\t wbs_rty_i);
///////////////////////////////////////////////////////////////////////////////
// Parameters
///////////////////////////////////////////////////////////////////////////////
//ISim does not implement $clog2. Other tools have broken implementations
`ifdef BROKEN_CLOG2
function integer clog2;
input integer in;
begin
\t in = in - 1;
\t for (clog2 = 0; in > 0; clog2=clog2+1)
\t in = in >> 1;
end
endfunction
`define clog2 clog2
`else // !`ifdef BROKEN_CLOG2
`define clog2 $clog2
`endif
//Use parameter instead of localparam to work around a bug in Xilinx ISE
parameter master_sel_bits = num_masters > 1 ? `clog2(num_masters) : 1;
wire [num_masters-1:0] grant;
wire [master_sel_bits-1:0] master_sel;
wire \t\t active;
arbiter
#(.NUM_PORTS (num_masters))
arbiter0
(.clk (wb_clk_i),
.rst (wb_rst_i),
.request (wbm_cyc_i),
.grant (grant),
.select (master_sel),
.active (active));
/* verilator lint_off WIDTH */
//Mux active master
assign wbs_adr_o = wbm_adr_i[master_sel*aw+:aw];
assign wbs_dat_o = wbm_dat_i[master_sel*dw+:dw];
assign wbs_sel_o = wbm_sel_i[master_sel*4+:4];
assign wbs_we_o = wbm_we_i [master_sel];
assign wbs_cyc_o = wbm_cyc_i[master_sel] & active;
assign wbs_stb_o = wbm_stb_i[master_sel];
assign wbs_cti_o = wbm_cti_i[master_sel*3+:3];
assign wbs_bte_o = wbm_bte_i[master_sel*2+:2];
assign wbm_dat_o = {num_masters{wbs_dat_i}};
assign wbm_ack_o = ((wbs_ack_i & active) << master_sel);
assign wbm_err_o = ((wbs_err_i & active) << master_sel);
assign wbm_rty_o = ((wbs_rty_i & active) << master_sel);
/* verilator lint_on WIDTH */
endmodule // wb_arbiter
|
/* wb_data_resize. Part of wb_intercon
*
* ISC License
*
* Copyright (C) 2019 Olof Kindgren <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module wb_data_resize
#(parameter aw = 32, //Address width
parameter mdw = 32, //Master Data Width
parameter sdw = 8, //Slave Data Width
parameter [47:0] endian = "big") // Endian for byte reads/writes
(//Wishbone Master interface
input wire [aw-1:0]\t wbm_adr_i,
input wire [mdw-1:0] wbm_dat_i,
input wire [3:0]\t wbm_sel_i,
input wire\t\t wbm_we_i,
input wire\t\t wbm_cyc_i,
input wire\t\t wbm_stb_i,
input wire [2:0]\t wbm_cti_i,
input wire [1:0]\t wbm_bte_i,
output wire [mdw-1:0] wbm_dat_o,
output wire\t\t wbm_ack_o,
output wire\t\t wbm_err_o,
output wire\t\t wbm_rty_o,
// Wishbone Slave interface
output wire [aw-1:0] wbs_adr_o,
output wire [sdw-1:0] wbs_dat_o,
output wire\t\t wbs_we_o,
output wire\t\t wbs_cyc_o,
output wire\t\t wbs_stb_o,
output wire [2:0]\t wbs_cti_o,
output wire [1:0]\t wbs_bte_o,
input wire [sdw-1:0] wbs_dat_i,
input wire\t\t wbs_ack_i,
input wire\t\t wbs_err_i,
input wire\t\t wbs_rty_i);
assign wbs_adr_o[aw-1:2] = wbm_adr_i[aw-1:2];
generate if (endian == "little") begin : le_resize_gen
assign wbs_adr_o[1:0] = wbm_sel_i[3] ? 2\'d3 :
wbm_sel_i[2] ? 2\'d2 :
wbm_sel_i[1] ? 2\'d1 : 2\'d0;
end else begin : be_resize_gen
assign wbs_adr_o[1:0] = wbm_sel_i[3] ? 2\'d0 :
wbm_sel_i[2] ? 2\'d1 :
wbm_sel_i[1] ? 2\'d2 : 2\'d3;
end endgenerate
assign wbs_dat_o = wbm_sel_i[3] ? wbm_dat_i[31:24] :
wbm_sel_i[2] ? wbm_dat_i[23:16] :
wbm_sel_i[1] ? wbm_dat_i[15:8] :
wbm_sel_i[0] ? wbm_dat_i[7:0] : 8\'b0;
assign wbs_we_o = wbm_we_i;
assign wbs_cyc_o = wbm_cyc_i;
assign wbs_stb_o = wbm_stb_i;
assign wbs_cti_o = wbm_cti_i;
assign wbs_bte_o = wbm_bte_i;
assign wbm_dat_o = (wbm_sel_i[3]) ? {wbs_dat_i, 24\'d0} :
(wbm_sel_i[2]) ? {8\'d0 , wbs_dat_i, 16\'d0} :
(wbm_sel_i[1]) ? {16\'d0, wbs_dat_i, 8\'d0} :
{24\'d0, wbs_dat_i};
assign wbm_ack_o = wbs_ack_i;
assign wbm_err_o = wbs_err_i;
assign wbm_rty_o = wbs_rty_i;
endmodule
|
/* wb_arbiter_tb. Part of wb_intercon
*
* ISC License
*
* Copyright (C) 2019 Olof Kindgren <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
`default_nettype none
module wb_arbiter_tb
#(parameter NUM_MASTERS = 5,
parameter AUTORUN = 1);
localparam aw = 32;
localparam dw = 32;
localparam MEMORY_SIZE_BITS = 8;
localparam MEMORY_SIZE_WORDS = 2**MEMORY_SIZE_BITS;
parameter TRANSACTIONS_PARAM = 1000;
reg wb_clk = 1\'b1;
reg wb_rst = 1\'b1;
wire [aw-1:0] wbs_m2s_adr;
wire [dw-1:0] wbs_m2s_dat;
wire [3:0] \t wbs_m2s_sel;
wire \t wbs_m2s_we ;
wire \t wbs_m2s_cyc;
wire \t wbs_m2s_stb;
wire [2:0] \t wbs_m2s_cti;
wire [1:0] \t wbs_m2s_bte;
wire [dw-1:0] wbs_s2m_dat;
wire \t wbs_s2m_ack;
wire \t wbs_s2m_err;
wire \t wbs_s2m_rty;
wire [NUM_MASTERS*aw-1:0] \t wbm_m2s_adr;
wire [NUM_MASTERS*dw-1:0] \t wbm_m2s_dat;
wire [NUM_MASTERS*4-1:0] \t wbm_m2s_sel;
wire [NUM_MASTERS-1:0] \t wbm_m2s_we ;
wire [NUM_MASTERS-1:0]\t wbm_m2s_cyc;
wire [NUM_MASTERS-1:0]\t wbm_m2s_stb;
wire [NUM_MASTERS*3-1:0] \t wbm_m2s_cti;
wire [NUM_MASTERS*2-1:0] \t wbm_m2s_bte;
wire [NUM_MASTERS*dw-1:0] \t wbm_s2m_dat;
wire [NUM_MASTERS-1:0]\t wbm_s2m_ack;
wire [NUM_MASTERS-1:0] \t wbm_s2m_err;
wire [NUM_MASTERS-1:0] \t wbm_s2m_rty;
wire [31:0] \t slave_writes;
wire [31:0] \t slave_reads;
wire [NUM_MASTERS-1:0] done_int;
wire done;
generate
if (AUTORUN) begin
vlog_tb_utils vtu();
vlog_tap_generator #("wb_arbiter.tap", 1) vtg();
initial begin
#100 run;
vtg.ok("wb_arbiter: All tests passed!");
$finish;
end
end
endgenerate
integer \t\t TRANSACTIONS;
task run;
integer idx;
begin
\t wb_rst = 1\'b0;
@(posedge done);
\t $display("Average wait times");
\t for(idx=0;idx<NUM_MASTERS;idx=idx+1)
\t $display("Master %0d : %f",idx, ack_delay[idx]/num_transactions[idx]);
end
endtask
always #5 wb_clk <= ~wb_clk;
genvar \t i;
generate
for(i=0;i<NUM_MASTERS;i=i+1) begin : masters
initial begin
@(negedge wb_rst);
\t if($value$plusargs("transactions=%d", TRANSACTIONS))
\t transactor.set_transactions(TRANSACTIONS);
\t transactor.display_settings;
\t transactor.run();
\t transactor.display_stats;
end
\t wb_bfm_transactor
\t #(.MEM_HIGH((i+1)*MEMORY_SIZE_WORDS-1),
.AUTORUN (0),
\t .MEM_LOW (i*MEMORY_SIZE_WORDS))
\t transactor
\t (.wb_clk_i (wb_clk),
\t .wb_rst_i (wb_rst),
\t .wb_adr_o (wbm_m2s_adr[i*aw+:aw]),
\t .wb_dat_o (wbm_m2s_dat[i*dw+:dw]),
\t .wb_sel_o (wbm_m2s_sel[i*4+:4]),
\t .wb_we_o (wbm_m2s_we[i] ),
\t .wb_cyc_o (wbm_m2s_cyc[i]),
\t .wb_stb_o (wbm_m2s_stb[i]),
\t .wb_cti_o (wbm_m2s_cti[i*3+:3]),
\t .wb_bte_o (wbm_m2s_bte[i*2+:2]),
\t .wb_dat_i (wbm_s2m_dat[i*dw+:dw]),
\t .wb_ack_i (wbm_s2m_ack[i]),
\t .wb_err_i (wbm_s2m_err[i]),
\t .wb_rty_i (wbm_s2m_rty[i]),
\t //Test Control
\t .done(done_int[i]));
end // block: slaves
endgenerate
assign done = &done_int;
wb_arbiter
#(.num_masters(NUM_MASTERS))
wb_arbiter0
(.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
// Master Interface
.wbm_adr_i (wbm_m2s_adr),
.wbm_dat_i (wbm_m2s_dat),
.wbm_sel_i (wbm_m2s_sel),
.wbm_we_i (wbm_m2s_we ),
.wbm_cyc_i (wbm_m2s_cyc),
.wbm_stb_i (wbm_m2s_stb),
.wbm_cti_i (wbm_m2s_cti),
.wbm_bte_i (wbm_m2s_bte),
.wbm_dat_o (wbm_s2m_dat),
.wbm_ack_o (wbm_s2m_ack),
.wbm_err_o (wbm_s2m_err),
.wbm_rty_o (wbm_s2m_rty),
// Wishbone Slave interface
.wbs_adr_o (wbs_m2s_adr),
.wbs_dat_o (wbs_m2s_dat),
.wbs_sel_o (wbs_m2s_sel),
.wbs_we_o (wbs_m2s_we),
.wbs_cyc_o (wbs_m2s_cyc),
.wbs_stb_o (wbs_m2s_stb),
.wbs_cti_o (wbs_m2s_cti),
.wbs_bte_o (wbs_m2s_bte),
.wbs_dat_i (wbs_s2m_dat),
.wbs_ack_i (wbs_s2m_ack),
.wbs_err_i (wbs_s2m_err),
.wbs_rty_i (wbs_s2m_rty));
assign slave_writes = wb_mem_model0.writes;
assign slave_reads = wb_mem_model0.reads;
time start_time[NUM_MASTERS-1:0];
time ack_delay[NUM_MASTERS-1:0];
integer num_transactions[NUM_MASTERS-1:0];
generate
for(i=0;i<NUM_MASTERS;i=i+1) begin : wait_time
\t initial begin
\t ack_delay[i] = 0;
\t num_transactions[i] = 0;
\t while(!done) begin
\t @(posedge wbm_m2s_cyc[i]);
\t start_time[i] = $time;
\t @(posedge wbm_s2m_ack[i]);
\t ack_delay[i] = ack_delay[i] + $time-start_time[i];
\t num_transactions[i] = num_transactions[i]+1;
\t end
\t end
end
endgenerate
wb_bfm_memory #(.DEBUG (0),
\t\t .mem_size_bytes(MEMORY_SIZE_WORDS*(dw/8)*NUM_MASTERS))
wb_mem_model0
(.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.wb_adr_i (wbs_m2s_adr),
.wb_dat_i (wbs_m2s_dat),
.wb_sel_i (wbs_m2s_sel),
.wb_we_i (wbs_m2s_we),
.wb_cyc_i (wbs_m2s_cyc),
.wb_stb_i (wbs_m2s_stb),
.wb_cti_i (wbs_m2s_cti),
.wb_bte_i (wbs_m2s_bte),
.wb_dat_o (wbs_s2m_dat),
.wb_ack_o (wbs_s2m_ack),
.wb_err_o (wbs_s2m_err),
.wb_rty_o (wbs_s2m_rty));
endmodule
|
/* wb_intercon_tb. Part of wb_intercon
*
* ISC License
*
* Copyright (C) 2019 Olof Kindgren <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module wb_intercon_tb;
vlog_tb_utils vlog_tb_utils0();
vlog_tap_generator #("wb_intercon.tap", 3) vtg();
wb_mux_tb #(.AUTORUN (0)) wb_mux_tb();
wb_arbiter_tb #(.AUTORUN (0)) wb_arb_tb();
wb_cdc_tb #(.AUTORUN (0)) wb_cdc_tb();
initial begin
wb_mux_tb.run;
vtg.ok("wb_mux: All tests passed!");
wb_arb_tb.run;
vtg.ok("wb_arbiter: All tests passed!");
wb_cdc_tb.run;
vtg.ok("wb_cdc: All tests passed!");
#3 $finish;
end
endmodule
|
/* wb_mux_tb. Part of wb_intercon
*
* ISC License
*
* Copyright (C) 2019 Olof Kindgren <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
`default_nettype none
module wb_mux_tb
#(parameter AUTORUN = 1);
localparam NUM_SLAVES = 4;
localparam aw = 32;
localparam dw = 32;
localparam SEGMENT_SIZE = 32\'h100;
localparam MEMORY_SIZE_BITS = 8;
/*TODO: Find a way to generate MATCH_ADDR and MATCH_MASK based on memory
size and number of slaves. Missing support for constant
user functions in Icarus Verilog is the blocker for this*/
localparam [dw*NUM_SLAVES-1:0] MATCH_ADDR = {32\'h00000300,
\t\t\t\t\t\t32\'h00000200,
\t\t\t\t\t\t32\'h00000100,
\t\t\t\t\t\t32\'h00000000};
localparam [dw*NUM_SLAVES-1:0] MATCH_MASK = {NUM_SLAVES{32\'hffffff00}};
reg wb_clk = 1\'b1;
reg wb_rst = 1\'b1;
wire [NUM_SLAVES*aw-1:0] wbs_m2s_adr;
wire [NUM_SLAVES*dw-1:0] wbs_m2s_dat;
wire [NUM_SLAVES*4-1:0] wbs_m2s_sel;
wire [NUM_SLAVES-1:0] wbs_m2s_we ;
wire [NUM_SLAVES-1:0] wbs_m2s_cyc;
wire [NUM_SLAVES-1:0] wbs_m2s_stb;
wire [NUM_SLAVES*3-1:0] wbs_m2s_cti;
wire [NUM_SLAVES*2-1:0] wbs_m2s_bte;
wire [NUM_SLAVES*dw-1:0] wbs_s2m_dat;
wire [NUM_SLAVES-1:0] wbs_s2m_ack;
wire [NUM_SLAVES-1:0] wbs_s2m_err;
wire [NUM_SLAVES-1:0] wbs_s2m_rty;
wire [aw-1:0] wb_m2s_adr;
wire [dw-1:0] wb_m2s_dat;
wire [3:0] \t wb_m2s_sel;
wire \t wb_m2s_we ;
wire \t wb_m2s_cyc;
wire \t wb_m2s_stb;
wire [2:0] \t wb_m2s_cti;
wire [1:0] \t wb_m2s_bte;
wire [dw-1:0] wb_s2m_dat;
wire \t wb_s2m_ack;
wire \t wb_s2m_err;
wire \t wb_s2m_rty;
wire [31:0] \t slave_writes [0:NUM_SLAVES-1];
wire [31:0] \t slave_reads [0:NUM_SLAVES-1];
genvar \t i;
integer TRANSACTIONS;
generate
if (AUTORUN) begin
vlog_tb_utils vtu();
vlog_tap_generator #("wb_mux.tap", 1) vtg();
initial begin
#100 run;
vtg.ok("wb_mux: All tests passed!");
$finish;
end
end
endgenerate
task run;
integer idx;
begin
\t wb_rst = 1\'b0;
if($value$plusargs("transactions=%d", TRANSACTIONS))
\t transactor.set_transactions(TRANSACTIONS);
\t transactor.display_settings;
\t transactor.run();
\t transactor.display_stats;
\t for(idx=0;idx<NUM_SLAVES;idx=idx+1) begin
\t $display("%0d writes to slave %0d", slave_writes[idx], idx);
\t end
end
endtask
always #5 wb_clk <= ~wb_clk;
wb_bfm_transactor
#(.NUM_SEGMENTS (NUM_SLAVES),
.AUTORUN (0),
.VERBOSE (0),
.SEGMENT_SIZE (SEGMENT_SIZE))
transactor
(.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.wb_adr_o (wb_m2s_adr),
.wb_dat_o (wb_m2s_dat),
.wb_sel_o (wb_m2s_sel),
.wb_we_o (wb_m2s_we ),
.wb_cyc_o (wb_m2s_cyc),
.wb_stb_o (wb_m2s_stb),
.wb_cti_o (wb_m2s_cti),
.wb_bte_o (wb_m2s_bte),
.wb_dat_i (wb_s2m_dat),
.wb_ack_i (wb_s2m_ack),
.wb_err_i (wb_s2m_err),
.wb_rty_i (wb_s2m_rty),
//Test Control
.done());
wb_mux
#(.num_slaves(NUM_SLAVES),
.MATCH_ADDR (MATCH_ADDR),
.MATCH_MASK (MATCH_MASK))
wb_mux0
(.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
// Master Interface
.wbm_adr_i (wb_m2s_adr),
.wbm_dat_i (wb_m2s_dat),
.wbm_sel_i (wb_m2s_sel),
.wbm_we_i (wb_m2s_we ),
.wbm_cyc_i (wb_m2s_cyc),
.wbm_stb_i (wb_m2s_stb),
.wbm_cti_i (wb_m2s_cti),
.wbm_bte_i (wb_m2s_bte),
.wbm_dat_o (wb_s2m_dat),
.wbm_ack_o (wb_s2m_ack),
.wbm_err_o (wb_s2m_err),
.wbm_rty_o (wb_s2m_rty),
// Wishbone Slave interface
.wbs_adr_o (wbs_m2s_adr),
.wbs_dat_o (wbs_m2s_dat),
.wbs_sel_o (wbs_m2s_sel),
.wbs_we_o (wbs_m2s_we),
.wbs_cyc_o (wbs_m2s_cyc),
.wbs_stb_o (wbs_m2s_stb),
.wbs_cti_o (wbs_m2s_cti),
.wbs_bte_o (wbs_m2s_bte),
.wbs_dat_i (wbs_s2m_dat),
.wbs_ack_i (wbs_s2m_ack),
.wbs_err_i (wbs_s2m_err),
.wbs_rty_i (wbs_s2m_rty));
generate
for(i=0;i<NUM_SLAVES;i=i+1) begin : slaves
\t assign slave_writes[i] = wb_mem_model0.writes;
\t assign slave_reads[i] = wb_mem_model0.reads;
\t wb_bfm_memory #(.DEBUG (0),
\t\t\t .mem_size_bytes(SEGMENT_SIZE))
\t wb_mem_model0
\t (.wb_clk_i (wb_clk),
\t .wb_rst_i (wb_rst),
\t .wb_adr_i (wbs_m2s_adr[i*aw+:aw] & (2**MEMORY_SIZE_BITS-1)),
\t .wb_dat_i (wbs_m2s_dat[i*dw+:dw]),
\t .wb_sel_i (wbs_m2s_sel[i*4+:4]),
\t .wb_we_i (wbs_m2s_we[i]),
\t .wb_cyc_i (wbs_m2s_cyc[i]),
\t .wb_stb_i (wbs_m2s_stb[i]),
\t .wb_cti_i (wbs_m2s_cti[i*3+:3]),
\t .wb_bte_i (wbs_m2s_bte[i*2+:2]),
\t .wb_dat_o (wbs_s2m_dat[i*dw+:dw]),
\t .wb_ack_o (wbs_s2m_ack[i]),
\t .wb_err_o (wbs_s2m_err[i]),
\t .wb_rty_o (wbs_s2m_rty[i]));
end // block: slaves
endgenerate
endmodule
|
/* wb_mux. Part of wb_intercon
*
* ISC License
*
* Copyright (C) 2013-2019 Olof Kindgren <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/*
Wishbone multiplexer, burst-compatible
Simple mux with an arbitrary number of slaves.
The parameters MATCH_ADDR and MATCH_MASK are flattened arrays
aw*NUM_SLAVES sized arrays that are used to calculate the
active slave. slave i is selected when
(wb_adr_i & MATCH_MASK[(i+1)*aw-1:i*aw] is equal to
MATCH_ADDR[(i+1)*aw-1:i*aw]
If several regions are overlapping, the slave with the lowest
index is selected. This can be used to have fallback
functionality in the last slave, in case no other slave was
selected.
If no match is found, the wishbone transaction will stall and
an external watchdog is required to abort the transaction
Todo:
Registered master/slave connections
Rewrite with System Verilog 2D arrays when tools support them
*/
module wb_mux
#(parameter dw = 32, // Data width
parameter aw = 32, // Address width
parameter num_slaves = 2, // Number of slaves
parameter [num_slaves*aw-1:0] MATCH_ADDR = 0,
parameter [num_slaves*aw-1:0] MATCH_MASK = 0)
(
input wire\t\t\t wb_clk_i,
input wire\t\t\t wb_rst_i,
// Master Interface
input wire [aw-1:0]\t\t wbm_adr_i,
input wire [dw-1:0]\t\t wbm_dat_i,
input wire [3:0]\t\t wbm_sel_i,
input wire\t\t\t wbm_we_i,
input wire\t\t\t wbm_cyc_i,
input wire\t\t\t wbm_stb_i,
input wire [2:0]\t\t wbm_cti_i,
input wire [1:0]\t\t wbm_bte_i,
output wire [dw-1:0]\t wbm_dat_o,
output wire\t\t\t wbm_ack_o,
output wire\t\t\t wbm_err_o,
output wire\t\t\t wbm_rty_o,
// Wishbone Slave interface
output wire [num_slaves*aw-1:0] wbs_adr_o,
output wire [num_slaves*dw-1:0] wbs_dat_o,
output wire [num_slaves*4-1:0] wbs_sel_o,
output wire [num_slaves-1:0] wbs_we_o,
output wire [num_slaves-1:0] wbs_cyc_o,
output wire [num_slaves-1:0] wbs_stb_o,
output wire [num_slaves*3-1:0] wbs_cti_o,
output wire [num_slaves*2-1:0] wbs_bte_o,
input wire [num_slaves*dw-1:0] wbs_dat_i,
input wire [num_slaves-1:0]\t wbs_ack_i,
input wire [num_slaves-1:0]\t wbs_err_i,
input wire [num_slaves-1:0]\t wbs_rty_i);
///////////////////////////////////////////////////////////////////////////////
// Master/slave connection
///////////////////////////////////////////////////////////////////////////////
//Use parameter instead of localparam to work around a bug in Xilinx ISE
parameter slave_sel_bits = num_slaves > 1 ? $clog2(num_slaves) : 1;
reg \t\t\t wbm_err;
wire [slave_sel_bits-1:0] \t slave_sel;
wire [num_slaves-1:0] \t match;
genvar \t\t\t idx;
generate
for(idx=0; idx<num_slaves ; idx=idx+1) begin : addr_match
\t assign match[idx] = (wbm_adr_i & MATCH_MASK[idx*aw+:aw]) == MATCH_ADDR[idx*aw+:aw];
end
endgenerate
//
// Find First 1 - Start from MSB and count downwards, returns 0 when no bit set
//
function [slave_sel_bits-1:0] ff1;
input [num_slaves-1:0] in;
integer \t\t i;
begin
\t ff1 = 0;
\t for (i = num_slaves-1; i >= 0; i=i-1) begin
\t if (in[i])
/* verilator lint_off WIDTH */
\t ff1 = i;
/* verilator lint_on WIDTH */
\t end
end
endfunction
assign slave_sel = ff1(match);
always @(posedge wb_clk_i)
wbm_err <= wbm_cyc_i & !(|match);
assign wbs_adr_o = {num_slaves{wbm_adr_i}};
assign wbs_dat_o = {num_slaves{wbm_dat_i}};
assign wbs_sel_o = {num_slaves{wbm_sel_i}};
assign wbs_we_o = {num_slaves{wbm_we_i}};
/* verilator lint_off WIDTH */
assign wbs_cyc_o = match & (wbm_cyc_i << slave_sel);
/* verilator lint_on WIDTH */
assign wbs_stb_o = {num_slaves{wbm_stb_i}};
assign wbs_cti_o = {num_slaves{wbm_cti_i}};
assign wbs_bte_o = {num_slaves{wbm_bte_i}};
assign wbm_dat_o = wbs_dat_i[slave_sel*dw+:dw];
assign wbm_ack_o = wbs_ack_i[slave_sel];
assign wbm_err_o = wbs_err_i[slave_sel] | wbm_err;
assign wbm_rty_o = wbs_rty_i[slave_sel];
endmodule
|
/* wb_upsizer. Part of wb_intercon
*
* ISC License
*
* Copyright (C) 2019 Olof Kindgren <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module wb_upsizer
#(parameter DW_IN = 0,
parameter SCALE = 0,
parameter AW = 32)
(input wire\t\t\t wb_clk_i,
input wire\t\t\t wb_rst_i,
input wire [AW-1:0]\t\t wbs_adr_i,
input wire [DW_IN-1:0]\t wbs_dat_i,
input wire [DW_IN/8-1:0]\t wbs_sel_i,
input wire\t\t\t wbs_we_i,
input wire\t\t\t wbs_cyc_i,
input wire\t\t\t wbs_stb_i,
input wire [2:0]\t\t wbs_cti_i,
input wire [1:0]\t\t wbs_bte_i,
output wire [DW_IN-1:0]\t wbs_dat_o,
output wire\t\t\t wbs_ack_o,
output wire\t\t\t wbs_err_o,
output wire\t\t\t wbs_rty_o,
//Master port
output wire [AW-1:0]\t wbm_adr_o,
output wire reg [DW_IN*SCALE-1:0] wbm_dat_o,
output wire [DW_IN*SCALE/8-1:0] wbm_sel_o,
output wire\t\t\t wbm_we_o,
output wire\t\t\t wbm_cyc_o,
output wire\t\t\t wbm_stb_o,
output wire [2:0]\t\t wbm_cti_o,
output wire [1:0]\t\t wbm_bte_o,
input wire [DW_IN*SCALE-1:0] wbm_dat_i,
input wire\t\t\t wbm_ack_i,
input wire\t\t\t wbm_err_i,
input wire\t\t\t wbm_rty_i);
`include "wb_common.v"
localparam SELW = DW_IN/8; //sel width
localparam DW_OUT = DW_IN*SCALE;
localparam SW_OUT = SELW*SCALE;
localparam BUFW = $clog2(DW_IN/8)-1; //Buffer width
localparam ADR_LSB = BUFW+1; //Bit position of the LSB of the buffer address. Lower bits are used for index part
localparam [1:0]
S_IDLE = 2\'b00,
S_READ = 2\'b01,
S_WRITE = 2\'b10;
reg [1:0] \t\t state;
wire [AW-1:ADR_LSB] \t adr_i;
wire [BUFW-1:0] \t idx_i;
reg [AW-1:ADR_LSB] \t radr;
reg [DW_OUT-1:0] \t rdat;
reg \t\t\t rdat_vld;
wire [AW-1:0] next_adr = wb_next_adr(wbs_adr_i, wbs_cti_i, wbs_bte_i, DW_IN)>> ($clog2(SELW)+BUFW);
wire \t\t req = wbs_cyc_i & wbs_stb_i;
wire \t\t wr_req = req & wbs_we_i;
wire \t\t last = wbs_cyc_i & (wbs_cti_i == 3\'b000 | wbs_cti_i == 3\'b111);
wire \t\t last_in_batch = (adr_i != next_adr) | last;
wire \t\t bufhit = (adr_i == radr) & rdat_vld;
wire \t\t next_bufhit = (next_adr == radr);
reg [AW-1:0] \t wr_adr;
reg [DW_IN*SCALE/8-1:0] wr_sel;
reg \t\t\t wr_we;
reg \t\t\t wr_cyc;
reg \t\t\t wr_stb;
reg [2:0] \t\t wr_cti;
reg [1:0] \t\t wr_bte;
reg [DW_OUT-1:0] \t wdat;
reg [DW_OUT/8-1:0] \t sel;
reg \t\t\t write_ack;
reg \t\t\t first_ack;
assign {adr_i,idx_i} = wbs_adr_i>>$clog2(SELW);
reg [AW-1:0] next_radr;
reg \t\t wbm_stb_o_r;
wire \t rd_cyc = wbs_cyc_i & !(last & bufhit);
assign wbs_dat_o = rdat_vld ?
\t\t rdat[idx_i*DW_IN+:DW_IN] :
\t\t wbm_dat_i[idx_i*DW_IN+:DW_IN];
wire wr = (wr_req | wr_cyc);
assign wbs_ack_o = wr ? write_ack : (wbm_ack_i | bufhit);
wire [AW-1:0] rd_adr = (first_ack/*wbm_stb_o_r*/ ? next_adr : adr_i) << ($clog2(SELW) + BUFW);
assign wbm_adr_o = wr ? wr_adr : rd_adr;
assign wbm_sel_o = wr ? wr_sel : {SW_OUT{1\'b1}};
assign wbm_we_o = wr ? wr_cyc : 1\'b0;
assign wbm_cyc_o = wr ? wr_cyc : rd_cyc;
assign wbm_stb_o = wr ? wr_stb : rd_cyc;
assign wbm_cti_o = wr ? wr_cti : 3\'b111;
assign wbm_bte_o = wr ? wr_bte : 2\'b00;
always @(posedge wb_clk_i) begin
if (wbs_ack_o & !wr) begin
\t first_ack <= 1\'b1;
\t if (last) first_ack <= 1\'b0;
end
write_ack <= 1\'b0;
wbm_stb_o_r <= wbm_stb_o & ! wbm_we_o;
if (wbm_cyc_o & wbm_ack_i & last) begin
\t rdat_vld <= 1\'b0;
end
case (state)
\tS_IDLE : begin
\t wr_cyc <= 1\'b0;
\t wr_stb <= 1\'b0;
\t wr_cti <= 3\'b000;
\t wr_bte <= 2\'b00;
\t if (req) begin
\t radr <= wbm_adr_o >> ($clog2(SELW)+BUFW);
\t wr_adr <= adr_i << ($clog2(SELW)+BUFW);
\t wr_cti <= wbs_cti_i;
\t wr_bte <= wbs_bte_i;
\t if (wbs_we_i) begin
\t\t wr_cyc <= 1\'b1;
\t\t wr_stb <= last_in_batch;
\t\t wbm_dat_o[idx_i*DW_IN+:DW_IN] <= wbs_dat_i;
\t\t wr_sel[idx_i*SELW+:SELW] <= wbs_sel_i;
\t\t //FIXME
\t\t wbm_dat_o[(!idx_i)*DW_IN+:DW_IN] <= {DW_IN{1\'b0}};
\t\t wr_sel[(!idx_i)*SELW+:SELW] <= {SELW{1\'b0}};
\t\t write_ack <= 1\'b1 | (!last_in_batch) & !(last & wbs_ack_o);
\t\t state <= S_WRITE;
\t end else begin //Read request
\t\t if (wbs_cti_i == 3\'b111)
\t\t rdat_vld <= 1\'b0;
\t\t if (!next_bufhit | !first_ack/*!wbm_stb_o_r*/) begin
\t\t rdat_vld <= 1\'b0;
\t\t state <= S_READ;
\t\t end
\t end
\t end
\tend
\tS_READ : begin
\t if (wbm_ack_i) begin
\t next_radr <= wb_next_adr(wbs_adr_i, wbs_cti_i, wbs_bte_i, DW_OUT)>> ($clog2(SELW)+BUFW);
\t //next_radr <= next_adr;
\t radr <= adr_i;
\t rdat <= wbm_dat_i;
\t rdat_vld <= !last;
\t state <= S_IDLE;
\t wbm_stb_o_r <= 1\'b1;
\t end
\tend
\tS_WRITE : begin
\t //write_ack <= (!last_in_batch | wbm_ack_i) & !(last & wbs_ack_o);
\t if (!wr_stb | wbm_ack_i) begin
\t write_ack <= !last & (!last_in_batch | wbm_ack_i);
\t\t wr_adr <= adr_i << ($clog2(SELW)+BUFW);
\t\t wdat[idx_i*DW_IN+:DW_IN] <= wbs_dat_i;
\t\t sel[idx_i*SELW+:SELW] <= wbs_sel_i;
\t\t if (last_in_batch) begin
\t\t wbm_dat_o[idx_i*DW_IN+:DW_IN] <= wbs_dat_i;
\t\t wbm_dat_o[(!idx_i)*DW_IN+:DW_IN] <= wdat[(!idx_i)*DW_IN+:DW_IN];
\t\t wr_sel[idx_i*SELW+:SELW] <= wbs_sel_i;
\t\t wr_sel[(!idx_i)*SELW+:SELW] <= sel[(!idx_i)*SELW+:SELW];
\t\t sel <= 0;
\t\t end
\t\t wr_sel[idx_i*SELW+:SELW] <= wbs_sel_i;
\t\t wr_stb <= last_in_batch;
\t wr_cti <= wbs_cti_i;
\t\t wr_bte <= wbs_bte_i;
\t end
\t if ((wbm_cti_o == 3\'b111) & wbm_ack_i) begin
\t write_ack <= 1\'b0;
\t wr_adr <= 0;
\t wbm_dat_o <= 0;
\t wr_sel <= 0;
\t wr_stb <= 1\'b0;
\t wr_cyc <= 1\'b0;
\t state <= S_IDLE;
\t end
\tend
\tdefault : state <= S_IDLE;
endcase
if (wb_rst_i) begin
\tstate <= S_IDLE;
\t rdat_vld <= 1\'b0;
\t first_ack <= 1\'b0;
end
end
endmodule
|
module LZC #(
\tparameter width = 8,
\tparameter word = 4
\t)(
\tinput wire CLK,
\tinput wire RST_N,
\tinput wire MODE,
\tinput wire IVALID,
\tinput wire [width-1:0] DATA,
\toutput reg OVALID,
\toutput reg [8:0] ZEROS
);
\tparameter INPUT = 1'b0;
\tparameter OUTPUT = 1'b1;
\tinteger i;
\twire have_one;
\treg state, state_next;
\treg findOne, flag;
\treg already_have_one;
\treg [8:0] zero_cnt;
\treg [5:0] WORDS;
\tassign have_one = (findOne) ? 1 : 0;
\talways @(posedge CLK or negedge RST_N) begin
\t\tif (!RST_N) begin
\t\t\tstate <= INPUT;
\t\t\tZEROS <= 0;
\t\t\tOVALID <= 0;
\t\t\tWORDS <= 0;
\t\t\tflag <= 0;
\t\t\talready_have_one <= 0;
\t\tend\telse begin
\t\t\tstate <= state_next;
\t\t\tif (IVALID) begin
\t\t\t\tWORDS <= WORDS + 1;
\t\t\t\tZEROS <= ZEROS + ((already_have_one) ? 0 : zero_cnt);
\t\t\t\talready_have_one <= (have_one) ? 1 : already_have_one;
\t\t\tend
\t\t\tif (state_next == OUTPUT) begin
\t\t\t\tOVALID <= 1;
\t\t\tend else begin
\t\t\t\tOVALID <= 0;
\t\t\tend
\t\t\tif (state == OUTPUT) begin
\t\t\t\tZEROS <= 0;
\t\t\t\tWORDS <= 0;
\t\t\t\talready_have_one <= 0;
\t\t\tend
\t\tend
\tend
\talways @* begin
\t\tif (IVALID) begin
\t\t\tzero_cnt = 0;
\t\t\tfindOne = 0;
\t\t\tfor (i = width-1; i >= 0; i = i - 1) begin
\t\t\t\tif (!findOne && DATA[i] == 0) begin
\t\t\t\t\tzero_cnt = zero_cnt + 1;
\t\t\t\tend else begin
\t\t\t\t\tfindOne = 1;
\t\t\t\tend
\t\t\tend
\t\tend
\tend
\talways @* begin
\t\tcase (state)
\t\t\tINPUT: begin
\t\t\t\tif (!IVALID) begin
\t\t\t\t\tstate_next = INPUT;
\t\t\t\tend else begin
\t\t\t\t\tif ((MODE && (have_one || already_have_one)) || WORDS == word - 1) begin
\t\t\t\t\t\tstate_next = OUTPUT;
\t\t\t\t\tend else begin
\t\t\t\t\t\tstate_next = INPUT;
\t\t\t\t\tend
\t\t\t\tend
\t\t\tend
\t\t\tOUTPUT: begin
\t\t\t\tstate_next = INPUT;
\t\t\tend
\t\tendcase
\tend
\t
endmodule
|
`timescale\t1ns/10ps
`ifndef\t\tWIDTH
`define\tWIDTH 8
`endif
`ifndef\t\tWORD
`define\tWORD 4
`endif
|
module stimulus;
\tparameter cyc = 10;
\tparameter delay = 1;
\treg clk, rst_n, mode, ivalid;
\treg [`WIDTH-1:0] DATA;
\twire ovalid;
\twire [8:0] zeros;
\treg debug_level;
\treg [8*128-1:0] fsdbfile, inputfile, goldenfile;
\treg [`WIDTH+1:0] input_vector[0:30000];
\treg [8:0] golden_vector[0:30000];
\tinteger i, j, error;
\tLZC #(
\t\t.width(`WIDTH),
\t\t.word(`WORD))
\tlzc1 (
\t\t.CLK(clk),
\t\t.RST_N(rst_n),
\t\t.MODE(mode),
\t\t.IVALID(ivalid),
\t\t.DATA(DATA),
\t\t.OVALID(ovalid),
\t\t.ZEROS(zeros)
\t);
\talways #(cyc/2) clk = ~clk;
\t// fsdb filename
\tinitial begin
\t\tif ($value$plusargs("fsdbfile=%s", fsdbfile)) begin
\t\t\t$fsdbDumpfile(fsdbfile);
\t\tend else begin
\t\t\t$fsdbDumpfile("lzc.fsdb");
\t\tend
\t\t$fsdbDumpvars;
\tend
\t// debug mode
\tinitial begin
\t\tif ($value$plusargs("DEBUG=%d", debug_level)) begin
\t\t\tif (debug_level == 1) begin
\t\t\t\t$monitor("clk=%d,OVALID=%b,ZEROS=%d", $time, ovalid, zeros);
\t\t\tend
\t\tend
\tend
\t// test pattern
\tinitial begin
\t\tif ($value$plusargs("pattern=%s", inputfile)) begin
\t\t\t$readmemb(inputfile, input_vector);
\t\tend
\t\tif ($value$plusargs("golden=%s", goldenfile)) begin
\t\t\t$readmemb(goldenfile, golden_vector);
\t\tend
\tend
\t// testbench
\tinitial begin
\t\tclk = 1;
\t\trst_n = 1;
\t\tj = 0;
\t\terror = 0;
\t\t#(cyc);
\t\t#(delay) rst_n = 0;
\t\t#(cyc*4) rst_n = 1;
\t\tfor (i = 0; i < 30000; i = i + 1) begin
\t\t\t#(cyc) apply_pattern(input_vector[i]);
\t\tend
\t\t#(cyc*3);
\t\t$display("%d errors in %s", error, inputfile);
\t\t$finish;
\tend
\t// count error
\talways @(posedge clk) begin
\t\tif (ovalid) begin
\t\t\tif (zeros != golden_vector[j]) begin
\t\t\t\terror = error + 1;
\t\t\tend
\t\t\tj = j + 1;
\t\tend
\tend
\t// apply pattern task
\ttask apply_pattern;
\t\tinput [`WIDTH+1:0] pattern;
\t\tbegin
\t\t\t{mode, ivalid, DATA} = pattern;
\t\tend
\tendtask
endmodule
|
/*
* Copyright (c) 2009 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module hex_display (
input [15:0] num,
input en,
output [6:0] hex0,
output [6:0] hex1,
output [6:0] hex2,
output [6:0] hex3
);
// Module instantiations
seg_7 hex_group0 (
.num (num[3:0]),
.en (en),
.seg (hex0)
);
seg_7 hex_group1 (
.num (num[7:4]),
.en (en),
.seg (hex1)
);
seg_7 hex_group2 (
.num (num[11:8]),
.en (en),
.seg (hex2)
);
seg_7 hex_group3 (
.num (num[15:12]),
.en (en),
.seg (hex3)
);
endmodule
|
////////////////////////////////////////////////////////////////////////////////\r
// Original Author: Schuyler Eldridge\r
// Contact Point: Schuyler Eldridge ([email protected])\r
// t_sqrt_pipelined.v\r
// Created: 4.2.2012\r
// Modified: 4.5.2012\r
//\r
// Testbench for generic sqrt operation\r
// \r
// Copyright (C) 2012 Schuyler Eldridge, Boston University\r
//\r
// This program is free software: you can redistribute it and/or modify\r
// it under the terms of the GNU General Public License as published by\r
// the Free Software Foundation, either version 3 of the License.\r
//\r
// This program is distributed in the hope that it will be useful,\r
// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
// GNU General Public License for more details.\r
//\r
// You should have received a copy of the GNU General Public License\r
// along with this program. If not, see <http://www.gnu.org/licenses/>.\r
////////////////////////////////////////////////////////////////////////////////\r
`timescale 1ns / 1ps\r
module t_sqrt_pipelined();\r
\r
parameter \r
INPUT_BITS = 4;\r
localparam\r
OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2;\r
\r
reg [INPUT_BITS-1:0] radicand;\r
reg clk, start, reset_n;\r
\r
wire [OUTPUT_BITS-1:0] root;\r
wire data_valid;\r
// wire [7:0] root_good;\r
\r
sqrt_pipelined \r
#(\r
.INPUT_BITS(INPUT_BITS)\r
)\r
sqrt_pipelined \r
(\r
.clk(clk),\r
.reset_n(reset_n),\r
.start(start),\r
.radicand(radicand), \r
.data_valid(data_valid),\r
.root(root)\r
);\r
\r
initial begin\r
radicand = 16'bx; clk = 1'bx; start = 1'bx; reset_n = 1'bx;;\r
#10 reset_n = 0; clk = 0;\r
#50 reset_n = 1; radicand = 0;\r
// #40 radicand = 81; start = 1;\r
// #10 radicand = 16'bx; start = 0;\r
#10000 $finish;\r
end\r
\r
always\r
#5 clk = ~clk;\r
\r
always begin\r
#10 radicand = radicand + 1; start = 1;\r
#10 start = 0;\r
end\r
\r
\r
// always begin\r
// #80 start = 1;\r
// #10 start = 0;\r
// end\r
\r
endmodule\r
\r
|
////////////////////////////////////////////////////////////////////////////////\r
// Original Author: Schuyler Eldridge\r
// Contact Point: Schuyler Eldridge ([email protected])\r
// button_debounce.v\r
// Created: 10/10/2009\r
// Modified: 3/20/2012\r
//\r
// Counter based debounce circuit originally written for EC551 (back\r
// in the day) and then modified (i.e. chagned entirely) into 3 always\r
// block format. This debouncer generates a signal that goes high for\r
// 1 clock cycle after the clock sees an asserted value on the button\r
// line. This action is then disabled until the counter hits a\r
// specified count value that is determined by the clock frequency and\r
// desired debounce frequency. An alternative implementation would not\r
// use a counter, but would use the shift register approach, looking\r
// for repeated matches (say 5) on the button line.\r
// \r
// Copyright (C) 2012 Schuyler Eldridge, Boston University\r
//\r
// This program is free software: you can redistribute it and/or modify\r
// it under the terms of the GNU General Public License as published by\r
// the Free Software Foundation, either version 3 of the License.\r
//\r
// This program is distributed in the hope that it will be useful,\r
// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
// GNU General Public License for more details.\r
//\r
// You should have received a copy of the GNU General Public License\r
// along with this program. If not, see <http://www.gnu.org/licenses/>.\r
////////////////////////////////////////////////////////////////////////////////\r
`timescale 1ns / 1ps\r
module button_debounce\r
(\r
input clk, // clock\r
input reset_n, // asynchronous reset \r
input button, // bouncy button\r
output reg debounce // debounced 1-cycle signal\r
);\r
\r
parameter\r
CLK_FREQUENCY = 66000000,\r
DEBOUNCE_HZ = 2;\r
// These parameters are specified such that you can choose any power\r
// of 2 frequency for a debouncer between 1 Hz and\r
// CLK_FREQUENCY. Note, that this will throw errors if you choose a\r
// non power of 2 frequency (i.e. count_value evaluates to some\r
// number / 3 which isn't interpreted as a logical right shift). I'm\r
// assuming this will not work for DEBOUNCE_HZ values less than 1,\r
// however, I'm uncertain of the value of a debouncer for fractional\r
// hertz button presses.\r
localparam\r
COUNT_VALUE = CLK_FREQUENCY / DEBOUNCE_HZ,\r
WAIT = 0,\r
FIRE = 1,\r
COUNT = 2;\r
\r
reg [1:0] state, next_state;\r
reg [25:0] count;\r
\r
always @ (posedge clk or negedge reset_n)\r
state <= (!reset_n) ? WAIT : next_state;\r
\r
always @ (posedge clk or negedge reset_n) begin\r
if (!reset_n) begin\r
debounce <= 0;\r
count <= 0;\r
end\r
else begin\r
debounce <= 0;\r
count <= 0;\r
case (state)\r
WAIT: begin\r
end\r
FIRE: begin\r
debounce <= 1;\r
end\r
COUNT: begin\r
count <= count + 1;\r
end\r
endcase \r
end\r
end\r
\r
always @ * begin\r
case (state)\r
WAIT: next_state = (button) ? FIRE : state;\r
FIRE: next_state = COUNT;\r
COUNT: next_state = (count > COUNT_VALUE - 1) ? WAIT : state;\r
default: next_state = WAIT;\r
endcase\r
end\r
\r
endmodule\r
|
////////////////////////////////////////////////////////////////////////////////\r
// Original Author: Schuyler Eldridge\r
// Contact Point: Schuyler Eldridge ([email protected])\r
// sqrt_pipelined.v\r
// Created: 4.2.2012\r
// Modified: 4.5.2012\r
//\r
// Implements a fixed-point parameterized pipelined square root\r
// operation on an unsigned input of any bit length. The number of\r
// stages in the pipeline is equal to the number of output bits in the\r
// computation. This pipelien sustains a throughput of one computation\r
// per clock cycle.\r
// \r
// Copyright (C) 2012 Schuyler Eldridge, Boston University\r
//\r
// This program is free software: you can redistribute it and/or modify\r
// it under the terms of the GNU General Public License as published by\r
// the Free Software Foundation, either version 3 of the License.\r
//\r
// This program is distributed in the hope that it will be useful,\r
// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
// GNU General Public License for more details.\r
//\r
// You should have received a copy of the GNU General Public License\r
// along with this program. If not, see <http://www.gnu.org/licenses/>.\r
////////////////////////////////////////////////////////////////////////////////\r
`timescale 1ns / 1ps\r
module sqrt_pipelined\r
(\r
input clk, // clock\r
input reset_n, // asynchronous reset\r
input start, // optional start signal\r
input [INPUT_BITS-1:0] radicand, // unsigned radicand\r
output reg data_valid, // optional data valid signal\r
output reg [OUTPUT_BITS-1:0] root // unsigned root \r
);\r
\r
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP\r
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE\r
// OVERWRITTEN!\r
parameter\r
INPUT_BITS = 16; // number of input bits (any integer)\r
localparam\r
OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2; // number of output bits\r
\r
reg [OUTPUT_BITS-1:0] start_gen; // valid data propagation\r
reg [OUTPUT_BITS*INPUT_BITS-1:0] root_gen; // root values\r
reg [OUTPUT_BITS*INPUT_BITS-1:0] radicand_gen; // radicand values\r
wire [OUTPUT_BITS*INPUT_BITS-1:0] mask_gen; // mask values\r
\r
// This is the first stage of the pipeline.\r
always @ (posedge clk or negedge reset_n) begin\r
if (!reset_n) begin\r
start_gen[0] <= 0;\r
radicand_gen[INPUT_BITS-1:0] <= 0;\r
root_gen[INPUT_BITS-1:0] <= 0;\r
end\r
else begin\r
start_gen[0] <= start;\r
if ( mask_gen[INPUT_BITS-1:0] <= radicand ) begin\r
radicand_gen[INPUT_BITS-1:0] <= radicand - mask_gen[INPUT_BITS-1:0];\r
root_gen[INPUT_BITS-1:0] <= mask_gen[INPUT_BITS-1:0];\r
end\r
else begin\r
radicand_gen[INPUT_BITS-1:0] <= radicand;\r
root_gen[INPUT_BITS-1:0] <= 0;\r
end\r
end\r
end\r
\r
// Main generate loop to create the masks and pipeline stages.\r
generate\r
genvar i;\r
// Generate all the mask values. These are built up in the\r
// following fashion:\r
// LAST MASK: 0x00...001 \r
// 0x00...004 Increasing # OUTPUT_BITS\r
// 0x00...010 |\r
// 0x00...040 v\r
// ...\r
// FIRST MASK: 0x10...000 # masks == # OUTPUT_BITS\r
// \r
// Note that the first mask used can either be of the 0x1... or\r
// 0x4... variety. This is purely determined by the number of\r
// computation stages. However, the last mask used will always be\r
// 0x1 and the second to last mask used will always be 0x4.\r
for (i = 0; i < OUTPUT_BITS; i = i + 1) begin: mask_4\r
if (i % 2) // i is odd, this is a 4 mask\r
assign mask_gen[INPUT_BITS*(OUTPUT_BITS-i)-1:INPUT_BITS*(OUTPUT_BITS-i-1)] = 4 << 4 * (i/2);\r
else // i is even, this is a 1 mask\r
assign mask_gen[INPUT_BITS*(OUTPUT_BITS-i)-1:INPUT_BITS*(OUTPUT_BITS-i-1)] = 1 << 4 * (i/2);\r
end\r
// Generate all the pipeline stages to compute the square root of\r
// the input radicand stream. The general approach is to compare\r
// the current values of the root plus the mask to the\r
// radicand. If root/mask sum is greater than the radicand,\r
// subtract the mask and the root from the radicand and store the\r
// radicand for the next stage. Additionally, the root is\r
// increased by the value of the mask and stored for the next\r
// stage. If this test fails, then the radicand and the root\r
// retain their value through to the next stage. The one weird\r
// thing is that the mask indices appear to be incremented by one\r
// additional position. This is not the case, however, because the\r
// first mask is used in the first stage (always block after the\r
// generate statement).\r
for (i = 0; i < OUTPUT_BITS - 1; i = i + 1) begin: pipeline\r
always @ (posedge clk or negedge reset_n) begin : pipeline_stage\r
if (!reset_n) begin\r
start_gen[i+1] <= 0;\r
radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= 0;\r
root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= 0;\r
end\r
else begin\r
start_gen[i+1] <= start_gen[i];\r
if ((root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] + \r
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)]) <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i]) begin\r
\t radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] - \r
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] - \r
root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i];\r
\t root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= (root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] >> 1) + \r
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)];\r
end\r
else begin\r
\t radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i];\r
\t root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] >> 1;\r
end\r
end\r
end\r
end\r
endgenerate\r
\r
// This is the final stage which just implements a rounding\r
// operation. This stage could be tacked on as a combinational logic\r
// stage, but who cares about latency, anyway? This is NOT a true\r
// rounding stage. In order to add convergent rounding, you need to\r
// increase the input bit width by 2 (increase the number of\r
// pipeline stages by 1) and implement rounding in the module that\r
// instantiates this one. \r
always @ (posedge clk or negedge reset_n) begin\r
if (!reset_n) begin\r
data_valid <= 0;\r
root <= 0;\r
end\r
else begin\r
data_valid <= start_gen[OUTPUT_BITS-1];\r
if (root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS] > root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS])\r
root <= root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS] + 1;\r
else\r
root <= root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS];\r
end\r
end\r
\r
endmodule\r
|
////////////////////////////////////////////////////////////////////////////////\r
// Original Author: Schuyler Eldridge\r
// Contact Point: Schuyler Eldridge ([email protected])\r
// button_debounce.v\r
// Created: 4.5.2012\r
// Modified: 4.5.2012\r
//\r
// Testbench for button_debounce.v.\r
// \r
// Copyright (C) 2012 Schuyler Eldridge, Boston University\r
//\r
// This program is free software: you can redistribute it and/or modify\r
// it under the terms of the GNU General Public License as published by\r
// the Free Software Foundation, either version 3 of the License.\r
//\r
// This program is distributed in the hope that it will be useful,\r
// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
// GNU General Public License for more details.\r
//\r
// You should have received a copy of the GNU General Public License\r
// along with this program. If not, see <http://www.gnu.org/licenses/>.\r
////////////////////////////////////////////////////////////////////////////////\r
`timescale 1ns / 1ps\r
module t_button_debounce();\r
\r
parameter\r
CLK_FREQUENCY = 66000000,\r
DEBOUNCE_HZ = 2;\r
\r
reg clk, reset_n, button;\r
wire debounce;\r
\r
button_debounce\r
#(\r
.CLK_FREQUENCY(CLK_FREQUENCY),\r
.DEBOUNCE_HZ(DEBOUNCE_HZ)\r
)\r
button_debounce\r
(\r
.clk(clk),\r
.reset_n(reset_n),\r
.button(button),\r
.debounce(debounce)\r
);\r
\r
initial begin\r
clk = 1'bx; reset_n = 1'bx; button = 1'bx;\r
#10 reset_n = 1;\r
#10 reset_n = 0; clk = 0;\r
#10 reset_n = 1;\r
#10 button = 0;\r
end\r
\r
always\r
#5 clk = ~clk;\r
\r
always begin\r
#100 button = ~button;\r
#0.1 button = ~button;\r
#0.1 button = ~button;\r
#0.1 button = ~button;\r
#0.1 button = ~button;\r
#0.1 button = ~button;\r
#0.1 button = ~button;\r
#0.1 button = ~button;\r
#0.1 button = ~button;\r
end\r
\r
endmodule\r
|
`timescale 1ns / 1ps
// Copyright (C) 2008 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module control(clk,en,dsp_sel,an);
input clk, en;
output [1:0]dsp_sel;
output [3:0]an;
wire a,b,c,d,e,f,g,h,i,j,k,l;
assign an[3] = a;
assign an[2] = b;
assign an[1] = c;
assign an[0] = d;
assign dsp_sel[1] = e;
assign dsp_sel[0] = i;
FDRSE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) DFF3(
.Q(a), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(d), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF2(
.Q(b), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(a), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF1(
.Q(c), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(b), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF0(
.Q(d), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(c), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF7(
.Q(e), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(h), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF6(
.Q(f), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(e), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) DFF5(
.Q(g), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(f), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) DFF4(
.Q(h), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(g), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF11(
.Q(i), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(l), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) DFF10(
.Q(j), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(i), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF9(
.Q(k), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(j), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) DFF8(
.Q(l), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(k), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
endmodule
|
`timescale 1ns / 1ps
// Copyright (C) 2008 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module mux(opA,opB,sum,dsp_sel,out);
\tinput [3:0] opA,opB;
\tinput [4:0] sum;
\tinput [1:0] dsp_sel;
\toutput [3:0] out;
\t
\treg cout;
\t
\talways @ (sum)
\t\tbegin
\t\t\tif (sum[4] == 1)
\t\t\t\tcout <= 4'b0001;
\t\t\telse
\t\t\t\tcout <= 4'b0000;
\t\tend
\t
\treg out;
\t
\talways @(dsp_sel,sum,cout,opB,opA)
\t\tbegin
\t\t\tif (dsp_sel == 2'b00)
\t\t\t\tout <= sum[3:0];
\t\t\telse if (dsp_sel == 2'b01)
\t\t\t\tout <= cout;
\t\t\telse if (dsp_sel == 2'b10)
\t\t\t\tout <= opB;
\t\t\telse if (dsp_sel == 2'b11)
\t\t\t\tout <= opA;
\t\tend
endmodule
|
/*
* VGA top level file
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga (
// Wishbone signals
input wb_clk_i, // 25 Mhz VDU clock
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// VGA pad signals
output [ 3:0] vga_red_o,
output [ 3:0] vga_green_o,
output [ 3:0] vga_blue_o,
output horiz_sync,
output vert_sync,
// CSR SRAM master interface
output [17:1] csrm_adr_o,
output [ 1:0] csrm_sel_o,
output csrm_we_o,
output [15:0] csrm_dat_o,
input [15:0] csrm_dat_i
);
// Registers and nets
//
// csr address
reg [17:1] csr_adr_i;
reg csr_stb_i;
// Config wires
wire [15:0] conf_wb_dat_o;
wire conf_wb_ack_o;
// Mem wires
wire [15:0] mem_wb_dat_o;
wire mem_wb_ack_o;
// LCD wires
wire [17:1] csr_adr_o;
wire [15:0] csr_dat_i;
wire csr_stb_o;
wire v_retrace;
wire vh_retrace;
wire w_vert_sync;
// VGA configuration registers
wire shift_reg1;
wire graphics_alpha;
wire memory_mapping1;
wire [ 1:0] write_mode;
wire [ 1:0] raster_op;
wire read_mode;
wire [ 7:0] bitmask;
wire [ 3:0] set_reset;
wire [ 3:0] enable_set_reset;
wire [ 3:0] map_mask;
wire x_dotclockdiv2;
wire chain_four;
wire [ 1:0] read_map_select;
wire [ 3:0] color_compare;
wire [ 3:0] color_dont_care;
// Wishbone master to SRAM
wire [17:1] wbm_adr_o;
wire [ 1:0] wbm_sel_o;
wire wbm_we_o;
wire [15:0] wbm_dat_o;
wire [15:0] wbm_dat_i;
wire wbm_stb_o;
wire wbm_ack_i;
wire stb;
// CRT wires
wire [ 5:0] cur_start;
wire [ 5:0] cur_end;
wire [15:0] start_addr;
wire [ 4:0] vcursor;
wire [ 6:0] hcursor;
wire [ 6:0] horiz_total;
wire [ 6:0] end_horiz;
wire [ 6:0] st_hor_retr;
wire [ 4:0] end_hor_retr;
wire [ 9:0] vert_total;
wire [ 9:0] end_vert;
wire [ 9:0] st_ver_retr;
wire [ 3:0] end_ver_retr;
// attribute_ctrl wires
wire [3:0] pal_addr;
wire pal_we;
wire [7:0] pal_read;
wire [7:0] pal_write;
// dac_regs wires
wire dac_we;
wire [1:0] dac_read_data_cycle;
wire [7:0] dac_read_data_register;
wire [3:0] dac_read_data;
wire [1:0] dac_write_data_cycle;
wire [7:0] dac_write_data_register;
wire [3:0] dac_write_data;
// Module instances
//
vga_config_iface config_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (conf_wb_dat_o),
.wb_adr_i (wb_adr_i[4:1]),
.wb_we_i (wb_we_i),
.wb_sel_i (wb_sel_i),
.wb_stb_i (stb & wb_tga_i),
.wb_ack_o (conf_wb_ack_o),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.x_dotclockdiv2 (x_dotclockdiv2),
.chain_four (chain_four),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.cur_start (cur_start),
.cur_end (cur_end),
.start_addr (start_addr),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_lcd lcd (
.clk (wb_clk_i),
.rst (wb_rst_i),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.csr_adr_o (csr_adr_o),
.csr_dat_i (csr_dat_i),
.csr_stb_o (csr_stb_o),
.vga_red_o (vga_red_o),
.vga_green_o (vga_green_o),
.vga_blue_o (vga_blue_o),
.horiz_sync (horiz_sync),
.vert_sync (w_vert_sync),
.cur_start (cur_start),
.cur_end (cur_end),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.x_dotclockdiv2 (x_dotclockdiv2),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_cpu_mem_iface cpu_mem_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wb_adr_i),
.wbs_sel_i (wb_sel_i),
.wbs_we_i (wb_we_i),
.wbs_dat_i (wb_dat_i),
.wbs_dat_o (mem_wb_dat_o),
.wbs_stb_i (stb & !wb_tga_i),
.wbs_ack_o (mem_wb_ack_o),
.wbm_adr_o (wbm_adr_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_dat_o (wbm_dat_o),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (wbm_stb_o),
.wbm_ack_i (wbm_ack_i),
.chain_four (chain_four),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care)
);
vga_mem_arbitrer mem_arbitrer (
.clk_i (wb_clk_i),
.rst_i (wb_rst_i),
.wb_adr_i (wbm_adr_o),
.wb_sel_i (wbm_sel_o),
.wb_we_i (wbm_we_o),
.wb_dat_i (wbm_dat_o),
.wb_dat_o (wbm_dat_i),
.wb_stb_i (wbm_stb_o),
.wb_ack_o (wbm_ack_i),
.csr_adr_i (csr_adr_i),
.csr_dat_o (csr_dat_i),
.csr_stb_i (csr_stb_i),
.csrm_adr_o (csrm_adr_o),
.csrm_sel_o (csrm_sel_o),
.csrm_we_o (csrm_we_o),
.csrm_dat_o (csrm_dat_o),
.csrm_dat_i (csrm_dat_i)
);
// Continous assignments
assign wb_dat_o = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o;
assign wb_ack_o = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o;
assign stb = wb_stb_i & wb_cyc_i;
assign vert_sync = ~graphics_alpha ^ w_vert_sync;
// Behaviour
// csr_adr_i
always @(posedge wb_clk_i)
csr_adr_i <= wb_rst_i ? 17'h0 : csr_adr_o + start_addr[15:1];
// csr_stb_i
always @(posedge wb_clk_i)
csr_stb_i <= wb_rst_i ? 1'b0 : csr_stb_o;
endmodule
|
////////////////////////////////////////////////////////////////////////////////\r
// Original Author: Schuyler Eldridge\r
// Contact Point: Schuyler Eldridge ([email protected])\r
// div_pipelined.v\r
// Created: 4.3.2012\r
// Modified: 4.5.2012\r
//\r
// Testbench for div_pipelined.v\r
//\r
// Copyright (C) 2012 Schuyler Eldridge, Boston University\r
//\r
// This program is free software: you can redistribute it and/or modify\r
// it under the terms of the GNU General Public License as published by\r
// the Free Software Foundation, either version 3 of the License.\r
//\r
// This program is distributed in the hope that it will be useful,\r
// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
// GNU General Public License for more details.\r
//\r
// You should have received a copy of the GNU General Public License\r
// along with this program. If not, see <http://www.gnu.org/licenses/>.\r
////////////////////////////////////////////////////////////////////////////////\r
`timescale 1ns / 1ps\r
module t_div_pipelined();\r
\r
reg clk, start, reset_n;\r
reg [7:0] dividend, divisor;\r
wire data_valid, div_by_zero;\r
wire [7:0] quotient, quotient_correct;\r
\r
parameter\r
BITS = 8;\r
\r
div_pipelined\r
#(\r
.BITS(BITS)\r
)\r
div_pipelined\r
(\r
.clk(clk),\r
.reset_n(reset_n),\r
.dividend(dividend),\r
.divisor(divisor),\r
.quotient(quotient),\r
.div_by_zero(div_by_zero),\r
// .quotient_correct(quotient_correct),\r
.start(start),\r
.data_valid(data_valid)\r
);\r
\r
initial begin\r
#10 reset_n = 0;\r
#50 reset_n = 1;\r
#1\r
clk = 0;\r
dividend = -1;\r
divisor = 127;\r
#1000 $finish;\r
end\r
\r
// always\r
// #20 dividend = dividend + 1;\r
\r
always begin\r
#10 divisor = divisor - 1; start = 1;\r
#10 start = 0;\r
end\r
\r
always\r
#5 clk = ~clk;\r
\r
\r
endmodule\r
|
/*
* PS2 Mouse Interface
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module ps2_mouse (
input clk, // Clock Input
input reset, // Reset Input
inout ps2_clk, // PS2 Clock, Bidirectional
inout ps2_dat, // PS2 Data, Bidirectional
input [7:0] the_command, // Command to send to mouse
input send_command, // Signal to send
output command_was_sent, // Signal command finished sending
output error_communication_timed_out,
output [7:0] received_data, // Received data
output received_data_en, // If 1 - new data has been received
output start_receiving_data,
output wait_for_incoming_data
);
// --------------------------------------------------------------------
// Internal wires and registers Declarations
// --------------------------------------------------------------------
wire ps2_clk_posedge; // Internal Wires
wire ps2_clk_negedge;
reg [7:0] idle_counter; // Internal Registers
reg ps2_clk_reg;
reg ps2_data_reg;
reg last_ps2_clk;
reg [2:0] ns_ps2_transceiver; // State Machine Registers
reg [2:0] s_ps2_transceiver;
// --------------------------------------------------------------------
// Constant Declarations
// --------------------------------------------------------------------
localparam PS2_STATE_0_IDLE = 3'h0, // states
PS2_STATE_1_DATA_IN = 3'h1,
PS2_STATE_2_COMMAND_OUT = 3'h2,
PS2_STATE_3_END_TRANSFER = 3'h3,
PS2_STATE_4_END_DELAYED = 3'h4;
// --------------------------------------------------------------------
// Finite State Machine(s)
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) s_ps2_transceiver <= PS2_STATE_0_IDLE;
else s_ps2_transceiver <= ns_ps2_transceiver;
end
always @(*) begin
ns_ps2_transceiver = PS2_STATE_0_IDLE; // Defaults
case (s_ps2_transceiver)
PS2_STATE_0_IDLE:
begin
if((idle_counter == 8'hFF) && (send_command == 1'b1))
ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
else ns_ps2_transceiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_DATA_IN:
begin
// if((received_data_en == 1'b1) && (ps2_clk_posedge == 1'b1))
if((received_data_en == 1'b1)) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
end
PS2_STATE_2_COMMAND_OUT:
begin
if((command_was_sent == 1'b1) || (error_communication_timed_out == 1'b1))
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
else ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
end
PS2_STATE_3_END_TRANSFER:
begin
if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else if((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
PS2_STATE_4_END_DELAYED:
begin
if(received_data_en == 1'b1) begin
if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
else ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
end
default:
ns_ps2_transceiver = PS2_STATE_0_IDLE;
endcase
end
// --------------------------------------------------------------------
// Sequential logic
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) begin
last_ps2_clk <= 1'b1;
ps2_clk_reg <= 1'b1;
ps2_data_reg <= 1'b1;
end
else begin
last_ps2_clk <= ps2_clk_reg;
ps2_clk_reg <= ps2_clk;
ps2_data_reg <= ps2_dat;
end
end
always @(posedge clk) begin
if(reset == 1'b1) idle_counter <= 6'h00;
else if((s_ps2_transceiver == PS2_STATE_0_IDLE) && (idle_counter != 8'hFF))
idle_counter <= idle_counter + 6'h01;
else if (s_ps2_transceiver != PS2_STATE_0_IDLE)
idle_counter <= 6'h00;
end
// --------------------------------------------------------------------
// Combinational logic
// --------------------------------------------------------------------
assign ps2_clk_posedge = ((ps2_clk_reg == 1'b1) && (last_ps2_clk == 1'b0)) ? 1'b1 : 1'b0;
assign ps2_clk_negedge = ((ps2_clk_reg == 1'b0) && (last_ps2_clk == 1'b1)) ? 1'b1 : 1'b0;
assign start_receiving_data = (s_ps2_transceiver == PS2_STATE_1_DATA_IN);
assign wait_for_incoming_data = (s_ps2_transceiver == PS2_STATE_3_END_TRANSFER);
// --------------------------------------------------------------------
// Internal Modules
// --------------------------------------------------------------------
ps2_mouse_cmdout mouse_cmdout (
.clk (clk), // Inputs
.reset (reset),
.the_command (the_command),
.send_command (send_command),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_clk (ps2_clk), // Bidirectionals
.ps2_dat (ps2_dat),
.command_was_sent (command_was_sent), // Outputs
.error_communication_timed_out (error_communication_timed_out)
);
ps2_mouse_datain mouse_datain (
.clk (clk), // Inputs
.reset (reset),
.wait_for_incoming_data (wait_for_incoming_data),
.start_receiving_data (start_receiving_data),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_data (ps2_data_reg),
.received_data (received_data), // Outputs
.received_data_en (received_data_en)
);
endmodule
|
Require Export Sorted.
Require Export Mergesort.
|
////////////////////////////////////////////////////////////////////////////////\r
// Original Author: Schuyler Eldridge\r
// Contact Point: Schuyler Eldridge ([email protected])\r
// pipeline_registers.v\r
// Created: 4.4.2012\r
// Modified: 4.4.2012\r
//\r
// Implements a series of pipeline registers specified by the input\r
// parameters BIT_WIDTH and NUMBER_OF_STAGES. BIT_WIDTH determines the\r
// size of the signal passed through each of the pipeline\r
// registers. NUMBER_OF_STAGES is the number of pipeline registers\r
// generated. This accepts values of 0 (yes, it just passes data from\r
// input to output...) up to however many stages specified.\r
// Copyright (C) 2012 Schuyler Eldridge, Boston University\r
//\r
// This program is free software: you can redistribute it and/or modify\r
// it under the terms of the GNU General Public License as published by\r
// the Free Software Foundation, either version 3 of the License.\r
//\r
// This program is distributed in the hope that it will be useful,\r
// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
// GNU General Public License for more details.\r
//\r
// You should have received a copy of the GNU General Public License\r
// along with this program. If not, see <http://www.gnu.org/licenses/>.\r
////////////////////////////////////////////////////////////////////////////////\r
`timescale 1ns / 1ps\r
module pipeline_registers\r
(\r
input clk,\r
input reset_n,\r
input [BIT_WIDTH-1:0] pipe_in,\r
output reg [BIT_WIDTH-1:0] pipe_out\r
);\r
\r
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP\r
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE\r
// OVERWRITTEN!\r
parameter \r
BIT_WIDTH = 10,\r
NUMBER_OF_STAGES = 5;\r
\r
// Main generate function for conditional hardware instantiation\r
generate\r
genvar i;\r
// Pass-through case for the odd event that no pipeline stages are\r
// specified.\r
if (NUMBER_OF_STAGES == 0) begin\r
always @ *\r
pipe_out = pipe_in;\r
end\r
// Single flop case for a single stage pipeline\r
else if (NUMBER_OF_STAGES == 1) begin\r
always @ (posedge clk or negedge reset_n)\r
pipe_out <= (!reset_n) ? 0 : pipe_in;\r
end\r
// Case for 2 or more pipeline stages\r
else begin\r
// Create the necessary regs\r
reg [BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:0] pipe_gen;\r
// Create logic for the initial and final pipeline registers\r
always @ (posedge clk or negedge reset_n) begin\r
if (!reset_n) begin\r
pipe_gen[BIT_WIDTH-1:0] <= 0;\r
pipe_out <= 0;\r
end\r
else begin\r
pipe_gen[BIT_WIDTH-1:0] <= pipe_in;\r
pipe_out <= pipe_gen[BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:BIT_WIDTH*(NUMBER_OF_STAGES-2)];\r
end\r
end\r
// Create the intermediate pipeline registers if there are 3 or\r
// more pipeline stages\r
for (i = 1; i < NUMBER_OF_STAGES-1; i = i + 1) begin : pipeline\r
always @ (posedge clk or negedge reset_n)\r
pipe_gen[BIT_WIDTH*(i+1)-1:BIT_WIDTH*i] <= (!reset_n) ? 0 : pipe_gen[BIT_WIDTH*i-1:BIT_WIDTH*(i-1)];\r
end\r
end\r
endgenerate\r
\r
endmodule\r
|
////////////////////////////////////////////////////////////////////////////////\r
// Original Author: Schuyler Eldridge\r
// Contact Point: Schuyler Eldridge ([email protected])\r
// sign_extender.v\r
// Created: 5.16.2012\r
// Modified: 5.16.2012\r
//\r
// Generic sign extension module\r
//\r
// Copyright (C) 2012 Schuyler Eldridge, Boston University\r
//\r
// This program is free software: you can redistribute it and/or modify\r
// it under the terms of the GNU General Public License as published by\r
// the Free Software Foundation, either version 3 of the License.\r
//\r
// This program is distributed in the hope that it will be useful,\r
// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
// GNU General Public License for more details.\r
//\r
// You should have received a copy of the GNU General Public License\r
// along with this program. If not, see <http://www.gnu.org/licenses/>.\r
////////////////////////////////////////////////////////////////////////////////\r
`timescale 1ns/1ps\r
module sign_extender\r
#(\r
parameter\r
INPUT_WIDTH = 8,\r
OUTPUT_WIDTH = 16\r
)\r
(\r
input [INPUT_WIDTH-1:0] original,\r
output reg [OUTPUT_WIDTH-1:0] sign_extended_original\r
);\r
\r
wire [OUTPUT_WIDTH-INPUT_WIDTH-1:0] sign_extend;\r
\r
generate\r
genvar i;\r
for (i = 0; i < OUTPUT_WIDTH-INPUT_WIDTH; i = i + 1) begin : gen_sign_extend\r
assign sign_extend[i] = (original[INPUT_WIDTH-1]) ? 1'b1 : 1'b0;\r
end\r
endgenerate\r
\r
always @ * begin\r
sign_extended_original = {sign_extend,original};\r
end\r
\r
endmodule\r
|
// +UEFSHDR---------------------------------------------------------------------
// FILE NAME : sp_rom.v
// AUTHOR : Jo\xc3\xa3o Carlos Nunes Bittencourt
// AUTHOR\'S E-MAIL : [email protected]
// -----------------------------------------------------------------------------
// RELEASE HISTORY
// VERSION DATE AUTHOR DESCRIPTION
// 1.0 2013-02-15 joaocarlos initial version
// -----------------------------------------------------------------------------
// KEYWORDS: memory, rom, single-port, altera
// -----------------------------------------------------------------------------
// PURPOSE: read hexadecimal values stored in a INPUT_FILE.
// -----------------------------------------------------------------------------
// REUSE ISSUES
// Reset Strategy: N/A
// Clock Domains: system clk
// Critical Timing: N/A
// Test Features: N/A
// Asynchronous I/F: N/A
// Instantiations: N/A
// Synthesizable (y/n): y
// Other: N/A
// -UEFSHDR---------------------------------------------------------------------
// Define Input File if it isnt iet
`ifndef ROM_FILE
`define ROM_FILE "rom.out"
`endif
module sp_rom #(
parameter ADDRESS_WIDTH = 16,
parameter DATA_WIDTH = 16
)(
clk,
address, // Address input
data, \t// Data output
ren, // Read Enable
cen // Chip Enable
) /* synthesis romstyle = "M9K" */;
input clk;
input [ADDRESS_WIDTH-1:0] sink_address;
output [DATA_WIDTH-1:0] src_data;
input sink_ren, sink_cen;
// Specify rom style for ALTERA memory block
(* romstyle = "M9K" *) reg [DATA_WIDTH-1:0] mem [0:(2**ADDRESS_WIDTH)-1] ;
reg [DATA_WIDTH-1:0] src_data;
reg [8*40:1] infile;
initial
begin
$readmemh(`ROM_FILE, mem); // read memory file
data = {DATA_WIDTH{1\'b0}};
end
// Funcional read block
always @ (posedge clk)
begin
if (cen && ren)
data <= mem[address];
end
endmodule
// Thats all folks!
|
// Quartus II Verilog Template
// Simple Dual Port RAM with separate read/write addresses and
// single read/write clock
module simple_ram #(
parameter DATA_WIDTH = 8,
parameter ADDR_WIDTH = 6
) (
input clk,
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] write_addr,
input we,
input [(ADDR_WIDTH-1):0] read_addr,
output [(DATA_WIDTH-1):0] q
);
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
reg [DATA_WIDTH-1:0] read_data;
always @ (posedge clk) begin
// Write
if (we)
ram[write_addr] <= data;
// Read (if read_addr == write_addr, return OLD data). To return
// NEW data, use = (blocking write) rather than <= (non-blocking write)
// in the write assignment. NOTE: NEW data may require extra bypass
// logic around the RAM.
read_data <= ram[read_addr];
end
assign q = read_data;
endmodule
|
//
// xc3s500e_godil.v - SPI loader for GODIL with XC3S500E
//
// Copied from bscan_s3e_starter.v.
// Then the starter specific signals removed.
// Top level module renamed from top to xc3s500e_godil.
// Use with a .ucf file with the right PIN assignments.
//
module xc3s500e_godil
(
output wire MOSI,
output wire CSB,
output wire DRCK1,
// output wire dac_cs,
// output wire amp_cs,
// output wire ad_conv,
// output wire sf_ce0,
// output wire fpga_init_b,
input MISO
);
wire CAPTURE;
wire UPDATE;
wire TDI;
wire TDO1;
reg [47:0] header;
reg [15:0] len;
reg \t have_header = 0;
assign MOSI = TDI ;
wire SEL1;
wire SHIFT;
wire RESET;
reg \t CS_GO = 0;
reg \t CS_GO_PREP = 0;
reg \t CS_STOP = 0;
reg \t CS_STOP_PREP = 0;
reg [13:0] RAM_RADDR;
reg [13:0] RAM_WADDR;
wire DRCK1_INV = !DRCK1;
wire RAM_DO;
wire RAM_DI;
reg \t RAM_WE = 0;
// assign dac_cs = 1;
// assign amp_cs = 1;
// assign ad_conv = 0;
// assign sf_ce0 = 1;
// assign fpga_init_b = 1;
RAMB16_S1_S1 RAMB16_S1_S1_inst
(
.DOA(RAM_DO),
.DOB(),
.ADDRA(RAM_RADDR),
.ADDRB(RAM_WADDR),
.CLKA(DRCK1_INV),
.CLKB(DRCK1),
.DIA(1\'b0),
.DIB(RAM_DI),
.ENA(1\'b1),
.ENB(1\'b1),
.SSRA(1\'b0),
.SSRB(1\'b0),
.WEA(1\'b0),
.WEB(RAM_WE)
);
BSCAN_SPARTAN3 BSCAN_SPARTAN3_inst
(
.CAPTURE(CAPTURE),
.DRCK1(DRCK1),
.DRCK2(),
.RESET(RESET),
.SEL1(SEL1),
.SEL2(),
.SHIFT(SHIFT),
.TDI(TDI),
.UPDATE(UPDATE),
.TDO1(TDO1),
.TDO2(1\'b0)
);
`include "bscan_common.v"
endmodule
|
module top
(
output wire MOSI,
output wire CSB,
output wire DRCK1,
output wire dac_cs,
output wire amp_cs,
output wire ad_conv,
output wire sf_ce0,
output wire fpga_init_b,
input MISO
);
wire CAPTURE;
wire UPDATE;
wire TDI;
wire TDO1;
reg [47:0] header;
reg [15:0] len;
reg \t have_header = 0;
assign MOSI = TDI ;
wire SEL1;
wire SHIFT;
wire RESET;
reg \t CS_GO = 0;
reg \t CS_GO_PREP = 0;
reg \t CS_STOP = 0;
reg \t CS_STOP_PREP = 0;
reg [13:0] RAM_RADDR;
reg [13:0] RAM_WADDR;
wire DRCK1_INV = !DRCK1;
wire RAM_DO;
wire RAM_DI;
reg \t RAM_WE = 0;
assign dac_cs = 1;
assign amp_cs = 1;
assign ad_conv = 0;
assign sf_ce0 = 1;
assign fpga_init_b = 1;
RAMB16_S1_S1 RAMB16_S1_S1_inst
(
.DOA(RAM_DO),
.DOB(),
.ADDRA(RAM_RADDR),
.ADDRB(RAM_WADDR),
.CLKA(DRCK1_INV),
.CLKB(DRCK1),
.DIA(1\'b0),
.DIB(RAM_DI),
.ENA(1\'b1),
.ENB(1\'b1),
.SSRA(1\'b0),
.SSRB(1\'b0),
.WEA(1\'b0),
.WEB(RAM_WE)
);
BSCAN_SPARTAN3 BSCAN_SPARTAN3_inst
(
.CAPTURE(CAPTURE),
.DRCK1(DRCK1),
.DRCK2(),
.RESET(RESET),
.SEL1(SEL1),
.SEL2(),
.SHIFT(SHIFT),
.TDI(TDI),
.UPDATE(UPDATE),
.TDO1(TDO1),
.TDO2(1\'b0)
);
`include "bscan_common.v"
endmodule
|
module top
(
input gnd
);
wire CAPTURE;
wire UPDATE;
wire DRCK1;
wire TDI;
wire TDO1;
wire CSB;
reg [47:0] header;
reg [15:0] len;
reg \t have_header = 0;
wire MISO;
wire MOSI = TDI;
wire SEL1;
wire SHIFT;
wire RESET;
reg \t CS_GO = 0;
reg \t CS_GO_PREP = 0;
reg \t CS_STOP = 0;
reg \t CS_STOP_PREP = 0;
reg [13:0] RAM_RADDR;
reg [13:0] RAM_WADDR;
wire DRCK1_INV = !DRCK1;
wire RAM_DO;
wire RAM_DI;
reg \t RAM_WE = 0;
RAMB16_S1_S1 RAMB16_S1_S1_inst
(
.DOA(RAM_DO),
.DOB(),
.ADDRA(RAM_RADDR),
.ADDRB(RAM_WADDR),
.CLKA(DRCK1_INV),
.CLKB(DRCK1),
.DIA(1\'b0),
.DIB(RAM_DI),
.ENA(1\'b1),
.ENB(1\'b1),
.SSRA(1\'b0),
.SSRB(1\'b0),
.WEA(1\'b0),
.WEB(RAM_WE)
);
BSCAN_SPARTAN3A BSCAN_SPARTAN3A_inst
(
.CAPTURE(CAPTURE),
.DRCK1(DRCK1),
.DRCK2(),
.RESET(RESET),
.SEL1(SEL1),
.SEL2(),
.SHIFT(SHIFT),
.TCK(),
.TDI(TDI),
.TMS(),
.UPDATE(UPDATE),
.TDO1(TDO1),
.TDO2(1\'b0)
);
SPI_ACCESS
#(.SIM_DEVICE("3S50AN")
)
SPI_ACCESS_inst
\t (
\t .MISO(MISO),
\t .CLK(DRCK1),
\t .CSB(CSB),
\t .MOSI(MOSI)
\t );
`include "bscan_common.v"
endmodule
|
/* from bscan_s6_spi_isf.v */
assign CSB = !(CS_GO && !CS_STOP);
assign RAM_DI = MISO;
assign TDO1 = RAM_DO;
wire rst = CAPTURE || RESET || UPDATE || !SEL1;
always @(negedge DRCK1 or posedge rst)
if (rst)
begin
\t have_header <= 0;
\t CS_GO_PREP <= 0;
\t CS_STOP <= 0;
end
else
begin
\t CS_STOP <= CS_STOP_PREP;
\t if (!have_header)
\t begin
\t if (header[46:15] == 32\'h59a659a6)
\t\t begin
\t\t len <= {header [14:0],1\'b0};
\t\t have_header <= 1;
\t\t if ({header [14:0],1\'b0} != 0)
\t\t begin
\t\t\t CS_GO_PREP <= 1;
\t\t end
\t\t end
\t end
\t else if (len != 0)
\t begin
\t len <= len -1;
\t end // if (!have_header)
end // else: !if(CAPTRE || RESET || UPDATE || !SEL1)
reg reset_header = 0;
always @(posedge DRCK1 or posedge rst)
if (rst)
begin
\t CS_GO <= 0;
\t CS_STOP_PREP <= 0;
\t RAM_WADDR <= 0;
\t RAM_RADDR <=0;
\t RAM_WE <= 0;
reset_header <= 1;
end
else
begin
\t RAM_RADDR <= RAM_RADDR + 1;
\t RAM_WE <= !CSB;
\t if(RAM_WE)
\t RAM_WADDR <= RAM_WADDR + 1;
reset_header <=0;
//For the next if, the value of reset_header is probed at rising
//clock, before "reset_header<=0" is executed:
if(reset_header)
header <={47\'h000000000000, TDI};
else
header <= {header[46:0], TDI};
\t CS_GO <= CS_GO_PREP;
\t if (CS_GO && (len == 0))
\t CS_STOP_PREP <= 1;
end // else: !if(CAPTURE || RESET || UPDATE || !SEL1)
|
module top
(
output wire MOSI,
output wire CSB,
output wire DRCK1,
input MISO
);
wire CAPTURE;
wire UPDATE;
wire TDI;
wire TDO1;
reg [47:0] header;
reg [15:0] len;
reg \t have_header = 0;
assign MOSI = TDI ;
wire SEL1;
wire SHIFT;
wire RESET;
reg \t CS_GO = 0;
reg \t CS_GO_PREP = 0;
reg \t CS_STOP = 0;
reg \t CS_STOP_PREP = 0;
reg [13:0] RAM_RADDR;
reg [13:0] RAM_WADDR;
wire DRCK1_INV = !DRCK1;
wire RAM_DO;
wire RAM_DI;
reg \t RAM_WE = 0;
RAMB16_S1_S1 RAMB16_S1_S1_inst
(
.DOA(RAM_DO),
.DOB(),
.ADDRA(RAM_RADDR),
.ADDRB(RAM_WADDR),
.CLKA(DRCK1_INV),
.CLKB(DRCK1),
.DIA(1\'b0),
.DIB(RAM_DI),
.ENA(1\'b1),
.ENB(1\'b1),
.SSRA(1\'b0),
.SSRB(1\'b0),
.WEA(1\'b0),
.WEB(RAM_WE)
);
BSCAN_SPARTAN3A BSCAN_SPARTAN3A_inst
(
.CAPTURE(CAPTURE),
.DRCK1(DRCK1),
.DRCK2(),
.RESET(RESET),
.SEL1(SEL1),
.SEL2(),
.SHIFT(SHIFT),
.TCK(),
.TDI(TDI),
.TMS(),
.UPDATE(UPDATE),
.TDO1(TDO1),
.TDO2(1\'b0)
);
`include "bscan_common.v"
endmodule
|
//
// xc3s250e_godil.v - SPI loader for GODIL with XC3S250E
//
// Copied from bscan_s3e_starter.v.
// Then the starter specific signals removed.
// Top level module renamed from top to xc3s500e_godil.
// Use with a .ucf file with the right PIN assignments.
//
module xc3s250e_godil
(
output wire MOSI,
output wire CSB,
output wire DRCK1,
// output wire dac_cs,
// output wire amp_cs,
// output wire ad_conv,
// output wire sf_ce0,
// output wire fpga_init_b,
input MISO
);
wire CAPTURE;
wire UPDATE;
wire TDI;
wire TDO1;
reg [47:0] header;
reg [15:0] len;
reg \t have_header = 0;
assign MOSI = TDI ;
wire SEL1;
wire SHIFT;
wire RESET;
reg \t CS_GO = 0;
reg \t CS_GO_PREP = 0;
reg \t CS_STOP = 0;
reg \t CS_STOP_PREP = 0;
reg [13:0] RAM_RADDR;
reg [13:0] RAM_WADDR;
wire DRCK1_INV = !DRCK1;
wire RAM_DO;
wire RAM_DI;
reg \t RAM_WE = 0;
// assign dac_cs = 1;
// assign amp_cs = 1;
// assign ad_conv = 0;
// assign sf_ce0 = 1;
// assign fpga_init_b = 1;
RAMB16_S1_S1 RAMB16_S1_S1_inst
(
.DOA(RAM_DO),
.DOB(),
.ADDRA(RAM_RADDR),
.ADDRB(RAM_WADDR),
.CLKA(DRCK1_INV),
.CLKB(DRCK1),
.DIA(1\'b0),
.DIB(RAM_DI),
.ENA(1\'b1),
.ENB(1\'b1),
.SSRA(1\'b0),
.SSRB(1\'b0),
.WEA(1\'b0),
.WEB(RAM_WE)
);
BSCAN_SPARTAN3 BSCAN_SPARTAN3_inst
(
.CAPTURE(CAPTURE),
.DRCK1(DRCK1),
.DRCK2(),
.RESET(RESET),
.SEL1(SEL1),
.SEL2(),
.SHIFT(SHIFT),
.TDI(TDI),
.UPDATE(UPDATE),
.TDO1(TDO1),
.TDO2(1\'b0)
);
`include "bscan_common.v"
endmodule
|
module top
(
output wire MOSI,
output wire CSB,
output wire DRCK1,
input MISO
);
wire CAPTURE;
wire UPDATE;
wire TDI;
wire TDO1;
reg [47:0] header;
reg [15:0] len;
reg \t have_header = 0;
assign MOSI = TDI ;
wire SEL1;
wire SHIFT;
wire RESET;
reg \t CS_GO = 0;
reg \t CS_GO_PREP = 0;
reg \t CS_STOP = 0;
reg \t CS_STOP_PREP = 0;
reg [13:0] RAM_RADDR;
reg [13:0] RAM_WADDR;
wire DRCK1_INV = !DRCK1;
wire RAM_DO;
wire RAM_DI;
reg \t RAM_WE = 0;
RAMB16_S1_S1 RAMB16_S1_S1_inst
(
.DOA(RAM_DO),
.DOB(),
.ADDRA(RAM_RADDR),
.ADDRB(RAM_WADDR),
.CLKA(DRCK1_INV),
.CLKB(DRCK1),
.DIA(1\'b0),
.DIB(RAM_DI),
.ENA(1\'b1),
.ENB(1\'b1),
.SSRA(1\'b0),
.SSRB(1\'b0),
.WEA(1\'b0),
.WEB(RAM_WE)
);
BSCAN_SPARTAN6 BSCAN_SPARTAN6_inst
(
.CAPTURE(CAPTURE),
.DRCK(DRCK1),
.RESET(RESET),
.RUNTEST(),
.SEL(SEL1),
.SHIFT(SHIFT),
.TCK(),
.TDI(TDI),
.TMS(),
.UPDATE(UPDATE),
.TDO(TDO1)
);
`include "bscan_common.v"
endmodule
|
# comment
|
END
|
VIEW valid0
carray bin - 1 - - -
END
|
VIEW valid0
carray bin - 2 - 2 -
END
|
VIEW a
VIEW b
|
VIEW valid0
carray bin - 2 CL 2 "Y"
END
|
//----------------------------------------------------------------------------
// Copyright (C) 2014 , Atsushi Sasaki
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: tdm_to_i2s_converter.v
//
// *Module Description:
// TDM to I2S Converter
//
// *Author(s):
// - Atsushi Sasaki, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 1.00 $
// $LastChangedBy: Atsushi Sasaki $
// $LastChangedDate: 2014-06-06 $
//----------------------------------------------------------------------------
module tdm_to_i2s_converter(
\trst_i,
\tsck_i,
\tfsync_i,
\tdat_i,
\tmck_o,
\tbck_o,
\tlrck_o,
\tdat_o
);
//
// Parameters
//
//
// I/O Ports
//
\tinput rst_i;
\tinput sck_i;
\tinput fsync_i;
\tinput dat_i;
\toutput mck_o;
\toutput bck_o;
\toutput lrck_o;
\toutput reg [3:0] dat_o;
\t
//
// Wires, Registers
//
\tassign rst = rst_i;
\t
//
// Modules
//
\t// Shifted Frame Sync
\treg s_fsync;
\t
\talways @ (posedge sck_i or posedge rst) begin
\t\tif(rst) begin
\t\t\ts_fsync <= 1\'b0;
\t\tend
\t\telse begin
\t\t\ts_fsync <= fsync_i;
\t\tend
\tend
\t// Bit Counter
\treg [8:0] bit_cnt;
\talways @ (negedge sck_i or posedge rst) begin
\t\tif(rst) begin
\t\t\tbit_cnt <= 9\'b111111111;
\t\tend
\t\telse begin
\t\t\tif(s_fsync) begin
\t\t\t\tbit_cnt <= {~bit_cnt[8], 8\'b0};
\t\t\tend
\t\t\telse begin
\t\t\t\tbit_cnt <= bit_cnt + 1\'b1;
\t\t\tend
\t\tend
\tend
\t// Input Data Assign
\treg [63:0] dat_0_a, dat_0_b;
\treg [63:0] dat_1_a, dat_1_b;
\treg [63:0] dat_2_a, dat_2_b;
\treg [63:0] dat_3_a, dat_3_b;
\talways @ (posedge sck_i or posedge rst) begin
\t\tif(rst) begin
\t\t\tdat_0_a <= 64\'b0;
\t\t\tdat_1_a <= 64\'b0;
\t\t\tdat_2_a <= 64\'b0;
\t\t\tdat_3_a <= 64\'b0;
\t\t\tdat_0_b <= 64\'b0;
\t\t\tdat_1_b <= 64\'b0;
\t\t\tdat_2_b <= 64\'b0;
\t\t\tdat_3_b <= 64\'b0;
\t\tend
\t\telse begin
\t\t\tif(bit_cnt[8]) begin
\t\t\t\tcase(bit_cnt[7:6])
\t\t\t\t\t2\'b00:
\t\t\t\t\t\tbegin
\t\t\t\t\t\t\tdat_0_a[63-bit_cnt[5:0]] <= dat_i;
\t\t\t\t\t\tend
\t\t\t\t\t2\'b01:
\t\t\t\t\t\tbegin
\t\t\t\t\t\t\tdat_1_a[63-bit_cnt[5:0]] <= dat_i;
\t\t\t\t\t\tend
\t\t\t\t\t2\'b10:
\t\t\t\t\t\tbegin
\t\t\t\t\t\t\tdat_2_a[63-bit_cnt[5:0]] <= dat_i;
\t\t\t\t\t\tend
\t\t\t\t\t2\'b11:
\t\t\t\t\t\tbegin
\t\t\t\t\t\t\tdat_3_a[63-bit_cnt[5:0]] <= dat_i;
\t\t\t\t\t\tend
\t\t\t\tendcase
\t\t\tend
\t\t\telse begin
\t\t\t\tcase(bit_cnt[7:6])
\t\t\t\t\t2\'b00:
\t\t\t\t\t\tbegin
\t\t\t\t\t\t\tdat_0_b[63-bit_cnt[5:0]] <= dat_i;
\t\t\t\t\t\tend
\t\t\t\t\t2\'b01:
\t\t\t\t\t\tbegin
\t\t\t\t\t\t\tdat_1_b[63-bit_cnt[5:0]] <= dat_i;
\t\t\t\t\t\tend
\t\t\t\t\t2\'b10:
\t\t\t\t\t\tbegin
\t\t\t\t\t\t\tdat_2_b[63-bit_cnt[5:0]] <= dat_i;
\t\t\t\t\t\tend
\t\t\t\t\t2\'b11:
\t\t\t\t\t\tbegin
\t\t\t\t\t\t\tdat_3_b[63-bit_cnt[5:0]] <= dat_i;
\t\t\t\t\t\tend
\t\t\t\tendcase
\t\t\tend
\t\tend
\tend
\t
\t// I2S Clock Generator
\tassign mck_o = sck_i;
\tassign bck_o = bit_cnt[1];
\tassign lrck_o = bit_cnt[7];
\t
\talways @ (negedge bck_o or posedge rst) begin
\t\tif(rst) begin
\t\t\tdat_o <= 4\'b0;
\t\tend
\t\telse begin
\t\t\tif(bit_cnt[8]) begin
\t\t\t\tdat_o <= {dat_3_b[63-bit_cnt[7:2]], dat_2_b[63-bit_cnt[7:2]], dat_1_b[63-bit_cnt[7:2]], dat_0_b[63-bit_cnt[7:2]]};
\t\t\tend
\t\t\telse begin
\t\t\t\tdat_o <= {dat_3_a[63-bit_cnt[7:2]], dat_2_a[63-bit_cnt[7:2]], dat_1_a[63-bit_cnt[7:2]], dat_0_a[63-bit_cnt[7:2]]};
\t\t\tend
\t\tend
\tend
\t
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2014 , Atsushi Sasaki
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: i2s_to_tdm_converter.v
//
// *Module Description:
// I2S to TDM Converter
//
// *Author(s):
// - Atsushi Sasaki, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 1.00 $
// $LastChangedBy: Atsushi Sasaki $
// $LastChangedDate: 2014-06-06 $
//----------------------------------------------------------------------------
module i2s_to_tdm_comverter(
\trst_i,
\tmck_i,
\tbck_i,
\tlrck_i,
\tdat_i,
\tsck_o,
\tfsync_o,
\tdat_o
);
//
// Parameters
//
//
// I/O Ports
//
\tinput rst_i;\t\t// reset
\tinput mck_i;\t\t// 256fs
\tinput bck_i;\t\t// 64fs
\tinput lrck_i;\t\t// fs
\tinput [3:0] dat_i;
\toutput sck_o;\t\t// 256fs
\toutput fsync_o;\t\t// fs
\toutput reg dat_o;\t// multi ch output
\t
//
// Wires, Registers
//
\treg rst_int;
\twire rst = rst_i | rst_int;
\treg [8:0] bit_cnt; // input data bit counter
\twire bank = bit_cnt[8];
//\treg bank;\t\t\t// FIFO Buffer Bank
\twire sck = mck_i; \t// internal system clock
\tassign sck_o = sck;
\twire [5:0] inbit_cnt = bit_cnt[7:2];
//
// module
//
\t// LRCK Negedge Detector
\treg d_lrck_1, d_lrck_2, d_lrck_3, d_lrck_4, d_lrck_5, d_lrck_6; \t// Delayed LRCK
\twire lrck_negedge_flag;\t\t// Frame Sync for LRCK Falling Edge
\tassign lrck_negedge_flag = (d_lrck_4 ^ d_lrck_6) & ~d_lrck_4;
\talways @ (posedge sck or posedge rst_i) begin
\t\tif(rst_i) begin
\t\t\td_lrck_1 <= 1\'b0;
\t\t\td_lrck_2 <= 1\'b0;
\t\t\td_lrck_3 <= 1\'b0;
\t\t\td_lrck_5 <= 1\'b0;
\t\tend
\t\telse begin
\t\t\td_lrck_1 <= lrck_i;
\t\t\td_lrck_2 <= d_lrck_1;
\t\t\td_lrck_3 <= d_lrck_2;
\t\t\td_lrck_5 <= d_lrck_4;
\t\tend
\tend
\talways @ (negedge sck or posedge rst_i) begin
\t\tif(rst_i) begin
\t\t\td_lrck_4 <= 1\'b0;
\t\t\td_lrck_6 <= 1\'b0;
\t\tend
\t\telse begin
\t\t\td_lrck_4 <= d_lrck_3;
\t\t\td_lrck_6 <= d_lrck_5;
\t\tend
\tend
\t// Internal Async Reset
\talways @ (negedge d_lrck_4 or posedge rst_i) begin
\t\tif(rst_i) begin
\t\t\trst_int <= 1\'b1;
\t\tend
\t\telse begin
\t\t\tif(&bit_cnt[7:0]) begin
\t\t\t\trst_int <= 1\'b0;
\t\t\tend
\t\t\telse begin
\t\t\t\trst_int <= 1\'b1;
\t\t\tend
\t\tend
\tend
\t// Bit counter
\talways @ (negedge sck or posedge rst) begin
\t\tif(rst) begin
\t\t\tbit_cnt <= 9\'b111111111;
\t\tend
\t\telse begin
\t\t\tbit_cnt <= bit_cnt + 1\'b1;
\t\tend
\tend
\t\t
\t// Input Buffer
\treg [255:0] fifo_a;
\treg [255:0] fifo_b;
\talways @ (posedge bck_i or posedge rst) begin
\t\tif(rst) begin
\t\t\tfifo_a <= 256\'b0;
\t\t\tfifo_b <= 256\'b0;
\t\tend
\t\telse begin
\t\t\tif(!bank) begin
\t\t\t\tfifo_a[255-bit_cnt[7:2]] <= dat_i[0];
\t\t\t\tfifo_a[191-bit_cnt[7:2]] <= dat_i[1];
\t\t\t\tfifo_a[127-bit_cnt[7:2]] <= dat_i[2];
\t\t\t\tfifo_a[63-bit_cnt[7:2]] <= dat_i[3];
\t\t\tend
\t\t\telse begin
\t\t\t\tfifo_b[255-bit_cnt[7:2]] <= dat_i[0];
\t\t\t\tfifo_b[191-bit_cnt[7:2]] <= dat_i[1];
\t\t\t\tfifo_b[127-bit_cnt[7:2]] <= dat_i[2];
\t\t\t\tfifo_b[63-bit_cnt[7:2]] <= dat_i[3];
\t\t\tend
\t\tend
\tend
\t
\t// TDM Generator
\talways @ (posedge sck or posedge rst) begin
\t\tif(rst) begin
\t\t\tdat_o <= 1\'b0;
\t\tend
\t\telse begin
\t\t\tif(!bank) begin
\t\t\t\tdat_o <= fifo_b[255-bit_cnt[7:0]];
\t\t\tend
\t\t\telse begin
\t\t\t\tdat_o <= fifo_a[255-bit_cnt[7:0]];
\t\t\tend
\t\tend
\tend
\t
\tassign fsync_o = &bit_cnt[7:0];
\t
\t
endmodule
\t\t\t
|
//----------------------------------------------------------------------------
// Copyright (C) 2014 , Atsushi Sasaki
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: fs_counter.v
//
// *Module Description:
// Sampling Frequency Counter for Audio Clock
//
// *Author(s):
// - Atsushi Sasaki, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 1.00 $
// $LastChangedBy: Atsushi Sasaki $
// $LastChangedDate: 2014-02-27 $
//----------------------------------------------------------------------------
module fs_counter(
\t refclk_i
\t, fsclk_i
\t, rst_i
\t, result_o
);
//
// I/O Ports
//
\tinput refclk_i;\t\t\t// refclk_i must be 24.576MHz
\tinput fsclk_i;\t\t\t// sampling clock frequency input
\tinput rst_i;\t\t\t// Active Hi Reset
\toutput [3:0] result_o;\t// 0000:32k, 0001:44.1k, 0010:48k, 0100:64k, 0101:88.2k, 0110:96k
\t\t\t\t\t\t\t// 1000:128k, 1001:176.4k, 1010:192k, 1100:256k, 1101:352.8k: 1110:384k
//
// Wires & Registers
\treg [9:0] cnt;
\treg [9:0] l_cnt;
\treg [2:0] s_fsclk;
//
// Module
//
\t//Defective for Meta-stable
\talways @ (posedge rst_i or negedge refclk_i) begin
\t\tif(rst_i) begin
\t\t\ts_fsclk[0] <= 1\'b0;
\t\tend
\t\telse begin
\t\t\ts_fsclk[2:0] <= {s_fsclk[1:0], fsclk_i};
\t\tend
\tend
\t//Negative Edge Detector
\twire edgedet = (s_fsclk[1] ^ s_fsclk[2]) & ~s_fsclk[1];
\talways @ (posedge refclk_i or posedge rst_i) begin
\t\tif(rst_i) begin
\t\t\tl_cnt[9:0] <= 10\'b0;
\t\t\tcnt[9:0] <= 10\'b0;
\t\tend
\t\telse begin
\t\t\tif(edgedet) begin
\t\t\t\tl_cnt[9:0] <= cnt[9:0];
\t\t\t\tcnt[9:0] <= 10\'b0;
\t\t\tend
\t\t\telse begin
\t\t\t\tcnt[9:0] <= cnt[9:0] + 1\'b1;
\t\t\tend
\t\tend
\tend
\t
\tassign result_o = (l_cnt[9:0] >= 10\'d662) ? 4\'b0000 :
\t\t\t\t\t\t\t(l_cnt[9:0] >= 10\'d534 && l_cnt[9:0] < 662) ? 4\'b0001 :
\t\t\t\t\t\t\t(l_cnt[9:0] >= 10\'d448 && l_cnt[9:0] < 534) ? 4\'b0010 :
\t\t\t\t\t\t\t(l_cnt[9:0] >= 10\'d331 && l_cnt[9:0] < 448) ? 4\'b0100 :
\t\t\t\t\t\t\t(l_cnt[9:0] >= 10\'d267 && l_cnt[9:0] < 331) ? 4\'b0101 :
\t\t\t\t\t\t\t(l_cnt[9:0] >= 10\'d224 && l_cnt[9:0] < 267) ? 4\'b0110 :
\t\t\t\t\t\t\t(l_cnt[9:0] >= 10\'d165 && l_cnt[9:0] < 224) ? 4\'b1000 :
\t\t\t\t\t\t\t(l_cnt[9:0] >= 10\'d133 && l_cnt[9:0] < 165) ? 4\'b1001 :
\t\t\t\t\t\t\t(l_cnt[9:0] >= 10\'d112 && l_cnt[9:0] < 133) ? 4\'b1010 :
\t\t\t\t\t\t\t(l_cnt[9:0] >= 10\'d82 && l_cnt[9:0] < 112) ? 4\'b1100 :
\t\t\t\t\t\t\t(l_cnt[9:0] >= 10\'d66 && l_cnt[9:0] < 82) ? 4\'b1101 :
\t\t\t\t\t\t\t(l_cnt[9:0] >= 10\'d1 && l_cnt[9:0] < 66) ? 4\'b1110 :
\t\t\t\t\t\t\t4\'b1111;
\t\t\t
\t
\t
\t\t\t
endmodule
\t
\t\t\t
\t\t
|
//----------------------------------------------------------------------------
// Copyright (C) 2013 , Atsushi Sasaki
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: dit.v
//
// *Module Description:
// Digital Audio Interface Transmitter(DIT) Module
//
// *Author(s):
// - Atsushi Sasaki, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 1.00 $
// $LastChangedBy: Atsushi Sasaki $
// $LastChangedDate: 2013-11-28 $
//----------------------------------------------------------------------------
module dit(
\t mck_i
\t, bck_i
\t, lrck_i
\t, dat_i
\t, mck_ratio_i
\t, vbit_i
\t, mute_i
\t, ch_stat7_0_i\t\t\t\t\t\t\t\t\t// Channel Status Input
\t, ch_stat15_8_i
\t, ch_stat23_16_i
\t, ch_stat31_24_i
\t, ch_stat39_32_i
//\t, nrst_i
\t, rst_i
\t, spdif_o
//\t, err_o
);
//
// Paramters
//
//
// I/O Ports
//
\tinput mck_i;\t\t\t\t\t\t\t\t\t// Master Clock input
\tinput bck_i;\t\t\t\t\t\t\t\t\t// Bit Clock input
\tinput lrck_i;\t\t\t\t\t\t\t\t\t// LR Clock input
\tinput dat_i;\t\t\t\t\t\t\t\t\t// Data input
\tinput [1:0] mck_ratio_i;\t\t\t\t\t\t// Master Clock Ratio(00:128fs, 01:256fs, 10:512fs, 11:Reserved)
\tinput vbit_i;\t\t\t\t\t\t\t\t\t// Validity Bit Data(\'0\':Valid, \'1\':Invalid)
\tinput mute_i;\t\t\t\t\t\t\t\t\t// Output Mute Data Flag
\tinput [7:0] ch_stat7_0_i;\t\t\t\t\t\t// Channel Status Input
\tinput [7:0] ch_stat15_8_i;
\tinput [7:0] ch_stat23_16_i;
\tinput [7:0] ch_stat31_24_i;
\tinput [7:0] ch_stat39_32_i;
//\tinput nrst_i;
\tinput rst_i; \t\t\t\t\t\t\t\t\t// Active Hi Reset
//\twire rst_i = ~nrst_i;
\toutput spdif_o;
//\toutput reg err_o;\t\t\t\t\t\t\t\t// Error Output
\t
//
// Wires, Registers
//
\twire [7:0] B_PREAMBLE = 8\'b00010111;
\twire [7:0] M_PREAMBLE = 8\'b01000111;
\twire [7:0] W_PREAMBLE = 8\'b00100111;
//\twire [191:0] ch_stat = {{132{1\'b0}}, 8\'b10000000, 8\'b10000010, 8\'b00000000, 8\'b01111010, 8\'b00000100};
\treg [39:0] ch_stat_buf;
\twire [191:0] ch_stat = {{132{1\'b0}}, ch_stat_buf};
\treg [14:0] cnt;
\twire slot_state = cnt[0];\t\t\t\t\t\t// Slot State
\twire [4:0] bit_cnt = cnt[5:1];\t\t\t\t\t// Bit Counter
\twire [7:0] frame_cnt = cnt[14:7];\t\t\t\t// Frame Counter
\twire subframe = cnt[6];\t\t\t\t\t\t\t// Subframe Channel
//\twire [23:0] adat = 24\'b0;\t\t\t\t\t\t// Sample Audio Data
\treg p_bit;\t\t\t\t\t\t\t\t\t\t// Parity Bit Data
\twire v_bit = vbit_i;\t\t\t\t\t\t\t// Validity Bit Data(\'0\':Valid, \'1\':Invalid)
\t
\treg [1:0] d_clk;\t\t\t\t\t\t\t\t// Divided Clocks
\twire s_clk = (mck_ratio_i==2\'b00) ? mck_i :
\t\t\t\t\t(mck_ratio_i==2\'b01) ? d_clk[0] :
\t\t\t\t\t(mck_ratio_i==2\'b10) ? d_clk[1] : 1\'b0;\t\t\t// System Clock(=128fs)
//\twire b_clk = d_clk[MCK_RATIO];\t\t\t\t\t// Bit Clock
\t
\treg encdat;\t\t\t\t\t\t\t\t\t\t// Encoding Data
\treg spdif;\t\t\t\t\t\t\t\t\t\t// Encoded SPDIF Output
\tassign spdif_o = spdif;
//
// Modules, Components
//
\t// Internal Async Reset
\treg rst_int;
\twire rst = rst_i | rst_int;
\talways @ (negedge lrck_i or posedge rst_i) begin
\t\tif(rst_i) begin
\t\t\trst_int <= 1\'b1;
\t\tend
\t\telse begin
\t\t\tif(&bit_cnt[4:0]) begin
\t\t\t\trst_int <= 1\'b0;
\t\t\tend
\t\t\telse begin
\t\t\t\trst_int <= 1\'b1;
\t\t\tend
\t\tend
\tend
\t// System Clock & Bit Clock Generator
\talways @ (posedge mck_i or posedge rst) begin
\t\tif(rst) begin
\t\t\td_clk <= 2\'b0;
\t\tend
\t\telse begin
\t\t\td_clk <= d_clk + 1\'b1;
\t\tend
\tend
\t// LRCK Edge Detector
\treg lrck_q0, lrck_q1;
\twire lrck_edge_flag = lrck_i ^ lrck_q1;
\talways @ (posedge bck_i or posedge rst) begin
\t\tif(rst) begin
\t\t\tlrck_q0 <= 1\'b0;
\t\tend
\t\telse begin
\t\t\tlrck_q0 <= lrck_i;
\t\tend
\tend
\talways @ (negedge bck_i or posedge rst) begin
\t\tif(rst) begin
\t\t\tlrck_q1 <= 1\'b0;
\t\tend
\t\telse begin
\t\t\tlrck_q1 <= lrck_q0;
\t\tend
\tend
\t// System Clock Counter
\talways @ (posedge s_clk or posedge rst) begin
\t\tif(rst) begin
\t\t\tcnt <= 15\'b111111111111111;
\t\tend
\t\telse begin
\t\t\tif({frame_cnt, subframe, bit_cnt, slot_state}=={8\'d191, 1\'b1, 5\'b11111, 1\'b1}) begin\t// count 192frame, 2nd subframe, 32-bit, after half biphase code
\t\t\t\tcnt <= 15\'b0;
\t\t\tend
\t\t\telse begin
\t\t\t\tcnt <= cnt + 1\'b1;
\t\t\tend
\t\tend
\tend
\t// Bit Counter and RAM(Enable for I2S format)
\treg [4:0] i2s_bit_cnt;
\treg lr;\t\t\t\t\t\t// 0=Left Ch., 1=Right Ch.
\treg [23:0] dat_l, dat_r;
\treg mute;
\talways @ (posedge bck_i or posedge rst) begin
\t\tif(rst) begin
\t\t\ti2s_bit_cnt <= 5\'b11111;
\t\t\tlr <= 1\'b0;
\t\t\tdat_l <= 24\'b0;
\t\t\tdat_r <= 24\'b0;
\t\t\tmute <= 1\'b0;
\t\tend
\t\telse begin
\t\t\tif(lrck_edge_flag) begin
\t\t\t\ti2s_bit_cnt <= 5\'b0;
\t\t\t\tmute <= mute_i;
\t\t\tend
\t\t\telse begin
\t\t\t\tif(i2s_bit_cnt!=5\'d24) begin
\t\t\t\t\ti2s_bit_cnt <= i2s_bit_cnt + 1\'b1;
\t\t\t\tend
\t\t\tend
\t\t\tif(~lr) begin
\t\t\t\tdat_l[23-i2s_bit_cnt] <= dat_i & ~mute;
\t\t\tend
\t\t\telse begin
\t\t\t\tdat_r[23-i2s_bit_cnt] <= dat_i & ~mute;
\t\t\tend
\t\t\tlr <= lrck_i;
\t\tend
\tend
\talways @ (negedge lrck_edge_flag or posedge rst) begin
\t\tif(rst) begin
\t\t\tch_stat_buf <= 40\'b0;
\t\tend
\t\telse begin
\t\t\tch_stat_buf <= {ch_stat39_32_i, ch_stat31_24_i, ch_stat23_16_i, ch_stat15_8_i, ch_stat7_0_i};
\t\tend
\tend
\t// SPDIF Bit Encoder
\talways @ (posedge s_clk or posedge rst) begin
\t\tif(rst) begin
\t\t\tspdif <= 1\'b0;
\t\t\tp_bit <= 1\'b0;
\t\tend
\t\telse begin
\t\t\tif(bit_cnt==5\'d0) begin
\t\t\t\tp_bit <= 1\'b0;\t\t\t// Parity Clear
\t\t\tend
\t\t\tif(bit_cnt<5\'d4) begin
\t\t\t\t// Preamble
\t\t\t\tif(subframe) begin\t// Subframe 2
\t\t\t\t\t// W Preamble
\t\t\t\t\tspdif <= W_PREAMBLE[{bit_cnt[1:0], slot_state}];
\t\t\t\tend
\t\t\t\telse if(frame_cnt==8\'b0) begin
\t\t\t\t\t// B Preamble
\t\t\t\t\tspdif <= B_PREAMBLE[{bit_cnt[1:0], slot_state}];
\t\t\t\tend
\t\t\t\telse begin
\t\t\t\t\t// M Preamble
\t\t\t\t\tspdif <= M_PREAMBLE[{bit_cnt[1:0], slot_state}];
\t\t\t\tend
\t\t\tend
\t\t\telse begin
\t\t\t\tspdif <= (!slot_state) ? ~spdif : \t\t\t// invert @ data boundary
\t\t\t\t\t\t\t\t(encdat) ? ~spdif : spdif;\t\t// invert if encode data is \'1\'
\t\t\t\tp_bit <= p_bit + (encdat & slot_state);\t// calculate P bit @ every encoded data boundary
\t\t\tend
\t\tend
\tend
\t// BiPhase Mark Coding Data Setting
\talways @ (negedge s_clk or posedge rst) begin
\t\tif(rst) begin
\t\t\tencdat <= 1\'b0;
\t\tend
\t\telse begin
\t\t\tif(bit_cnt>5\'d3 && bit_cnt<5\'d28) begin
\t\t\t\tif(lrck_i) begin
\t\t\t\t\tencdat <= dat_l[bit_cnt-4];
\t\t\t\tend
\t\t\t\telse begin
\t\t\t\t\tencdat <= dat_r[bit_cnt-4];
\t\t\t\tend
\t\t\t\t//encdat <= 1\'b0;
\t\t\tend
\t\t\telse if(bit_cnt==5\'d28) begin
\t\t\t\tencdat <= v_bit;
\t\t\tend
\t\t\telse if(bit_cnt==5\'d29) begin
\t\t\t\t//encdat <= u_dat[frame_cnt];
\t\t\t\tencdat <= 1\'b0;
\t\t\tend
\t\t\telse if(bit_cnt==5\'d30) begin
\t\t\t\tencdat <= ch_stat[frame_cnt];
\t\t\tend
\t\t\telse if(bit_cnt==5\'d31) begin
\t\t\t\tencdat <= p_bit;
\t\t\tend
\t\tend
\tend
/*\t\t
// Output Error Detection Block
\t
\t// SPDIF Edge Detection Block
\treg edgeclr;
\twire edgedet = spdif_o ^ edgeclr;
\talways @ (negedge mck_i or posedge rst_i) begin
\t\tif(rst_i) begin
\t\t\tedgeclr <= 1\'b0;
\t\tend
\t\telse begin
\t\t\tedgeclr <= spdif_o;
\t\tend
\tend
\t// ERROR Counter
\twire err_cntclk = s_clk & ~err_o;\t// count when negeted error flag
\treg [2:0] err_cnt;
\twire cnt_clr = edgedet | rst_i;
\talways @ (negedge err_cntclk or posedge cnt_clr) begin
\t\tif(cnt_clr) begin
\t\t\terr_cnt <= 3\'b0;
\t\tend
\t\telse begin
\t\t\terr_cnt <= err_cnt + 1\'b1;
\t\tend
\tend
\talways @ (posedge err_cnt[2] or posedge rst_i) begin\t\t// Assert Error Flag when invalid biphase coding
\t if(rst_i) begin
\t err_o <= 1\'b0;
\t end
\t else begin
\t err_o <= 1\'b1;
\t end
\tend
*/
\t
endmodule
|
Require Import Deci Hexa BinPosDef BinNatDef BinIntDef.
Import DecNat.
Compute nat2dec 1.
Compute nat2dec 123.
Compute nat2dec (dec2nat (D1::D2::D3::D4::D5::D6::D7::D8::D9::nil)).
Time Compute nat2dec (dec2nat (D1::D2::D3::D4::D5::D6::D7::D8::D9::nil)).
(** 10s for 10^8 :-) *)
Import DecN.
Compute dec2n (D1::D0::nil).
Compute n2dec 1.
Compute n2dec 123456789123456789123456789123456789.
Compute n2dec (N.pow 2 10000).
Time Compute n2dec (N.pow 2 10000).
(** 4s for 2^10000 :-) *)
Import DecPos.
Compute dec2pos (D1::D0::nil).
Compute pos2dec 1.
Compute pos2dec 123456789123456789123456789123456789.
Compute pos2dec (Pos.pow 2 10000).
Time Compute pos2dec (Pos.pow 2 10000).
(** 4s for 2^10000 :-) *)
Import DecZ.
Compute dec2z (D1::D0::nil).
Compute z2dec 1.
Compute z2dec 123456789123456789123456789123456789.
Compute z2dec (Z.pow 2 10000).
Time Compute z2dec (Z.pow 2 10000).
(** 4s for 2^10000 :-) *)
Import HexNat.
Compute nat2hex 1.
Compute nat2hex 123.
Compute nat2hex (hex2nat (H1::H2::H3::H4::H5::H6::H7::HF::nil)).
Time Compute nat2hex (hex2nat (H1::H2::H3::H4::H5::H6::H7::HF::nil)).
(** 33s for 16^7 :-) *)
Import HexN.
Compute hex2n (H1::H0::nil).
Compute n2hex 1.
Compute n2hex 123456789123456789123456789123456789.
Compute n2hex (N.pow 2 30000).
Time Compute n2hex (N.pow 2 30000).
(** 0s for 2^30000 :-) *)
Import HexPos.
Compute hex2pos (H1::H0::nil).
Compute pos2hex 1.
Compute pos2hex 123456789123456789123456789123456789.
Compute pos2hex (Pos.pow 2 30000).
Time Compute pos2hex (Pos.pow 2 30000).
(** 0s for 2^10000 :-) *)
Import HexZ.
Compute hex2z (H1::H0::nil).
Compute z2hex 1.
Compute z2hex 123456789123456789123456789123456789.
Compute z2hex (Z.pow 2 30000).
Time Compute z2hex (Z.pow 2 30000).
(** 0s for 2^10000 :-) *)
|
module ram (clk, addr, data_in, write_en, data_out, rom_addr, rom_out);
parameter ADDR_SIZE = 12;
parameter WORD_SIZE = 16;
parameter ROM_SIZE = 256;
input wire clk, write_en;
input wire [ADDR_SIZE-1:0] addr;
input wire [ADDR_SIZE-1:0] rom_addr;
input wire [WORD_SIZE-1:0] data_in;
output reg [WORD_SIZE-1:0] data_out;
output reg [WORD_SIZE-1:0] rom_out;
reg [WORD_SIZE-1:0] rom [ROM_SIZE-1:0];
always @(negedge clk) begin
if(write_en)
rom[addr] <= data_in;
data_out <= rom[addr];
rom_out <= rom[rom_addr];
end
initial
$readmemh("data/ram.txt",rom);
endmodule
|
`timescale 1ns / 1ps
module control_unit();
parameter ADDR_SIZE = 12;
parameter WORD_SIZE = 16;
reg sysclk;
initial begin //clock
sysclk <= 1\'b1;
forever #1 sysclk = ~sysclk;
end
initial begin
$dumpfile("control_unit.vcd");
$dumpvars;
end
/*
* Instructions:
* 0: ACC := [S]
* 1: [S] := ACC
* 2: ACC:= ACC + [S]
* 3: ACC := ACC - [S]
* 4: PC := S
* 5: PC := S if ACC >=0
* 6: PC :=S if ACC != 0
* 7: HALT
* 8: [SP] := ACC, SP := SP + 1
* 9: ACC := [SP], SP := SP - 1
* a: IP := S, [SP] := IP, SP := SP + 1
* b: IP := [SP - 1], SP := SP - 1
* /
/*
* Specifications:
* posedge: exec
* negedge: fetch
*/
//Registers
reg [WORD_SIZE-1:0] acc;
reg [ADDR_SIZE-1:0] ip;
reg [WORD_SIZE-1:0] ir;
reg [ADDR_SIZE-1:0] sp;
//Memory
reg [ADDR_SIZE-1:0] mem_addr;
reg [WORD_SIZE-1:0] mem_in;
wire [WORD_SIZE-1:0] mem_out;
wire [WORD_SIZE-1:0] rom_out;
reg mem_write;
ram ram_blk(
.clk(sysclk),
.addr(mem_addr),
.data_in(mem_in),
.write_en(mem_write),
.data_out(mem_out),
.rom_addr(ip),
.rom_out(rom_out)
);
initial begin //default register values
ir <= 16\'h4000;
ip <= 0;
sp <= 12\'d191; //64 word stack
mem_addr <= 0;
mem_in <= 0;
mem_write <= 0;
acc <= 0;
end
//0/1 -> Fetch/Exec
reg state = 1;
//Determine pop operations
wire pop_op;
assign pop_op = (rom_out[WORD_SIZE-1:WORD_SIZE-4] == 4\'h9)
| (rom_out[WORD_SIZE-1:WORD_SIZE-4] == 4\'hb);
always @(posedge sysclk) begin
state <= ~state; //Alternate state
if (state) begin //Exec
case (ir[WORD_SIZE-1:WORD_SIZE-4])
4\'h0: begin //ACC := [S]
acc <= mem_out;
end
4\'h1: begin //[S] := ACC
mem_in <= acc;
mem_addr <= ir[WORD_SIZE-5:0];
mem_write <= 1;
end
4\'h2: begin //ACC:= ACC + [S]
acc <= acc + mem_out;
end
4\'h3: begin //ACC := ACC - [S]
acc <= acc - mem_out;
end
4\'h4: begin // PC := S
ip <= ir[WORD_SIZE-5:0];
end
4\'h5: begin //PC := S if ACC >=0
if (acc[WORD_SIZE-1] == 1\'b0)
ip <= ir[WORD_SIZE-5:0];
end
4\'h6: begin //PC := S if ACC != 0
if (acc != 8\'d0)
ip <= ir[WORD_SIZE-5:0];
end
4\'h7: begin // HALT
$finish;
end
4\'h8: begin // [SP] := ACC, SP := SP + 1
mem_addr <= sp;
mem_in <= acc;
mem_write <= 1;
sp <= sp + 12\'b1;
end
4\'h9: begin // ACC := [SP - 1], SP := SP - 1
acc <= mem_out;
sp <= sp - 12\'b1;
end
4\'ha: begin // IP := S, [SP] := IP, SP := SP + 1
ip <= mem_addr ;
mem_addr <= sp;
mem_in <= ip;
mem_write <= 1;
sp <= sp + 12\'b1;
end
4\'hb: begin // IP := [SP - 1], SP := SP - 1
ip <= mem_out;
sp <= sp - 12\'b1;
end
default: $finish;
endcase
end
else begin //Fetch
ir <= rom_out;
ip <= ip + 1;
mem_write <= 0;
//Get stack if pop/return
if (pop_op) //
mem_addr <= (sp - 12\'b1);
else //Get memory
mem_addr <= rom_out[WORD_SIZE-5:0];
end
end
endmodule
|
//--------------------------------------------------------------------
//-- IceZUM Alhambra test
//-- Hello world example
//-- Turn on all the yellow leds
//--------------------------------------------------------------------
//-- (c) BQ March, 2016. Written by Juan Gonzalez (obijuan)
//--------------------------------------------------------------------
//-- Releases under the GPL v2+ license
//--------------------------------------------------------------------
module leds_on(output wire [7:0] LPORT);
//-- Turn on all the leds
assign LPORT = 8'hFF;
endmodule
|
//-------------------------------------------------------------------
//-- leds_on_tb.v
//-- Testbench
//-------------------------------------------------------------------
//-- BQ March 2016. Written by Juan Gonzalez (Obijuan)
//-------------------------------------------------------------------
`default_nettype none
`timescale 100 ns / 10 ns
module leds_on_tb();
//-- Simulation time: 1us (10 * 100ns)
parameter DURATION = 10;
//-- Clock signal. It is not used in this simulation
reg clk = 0;
always #0.5 clk = ~clk;
//-- Leds port
wire [7:0] lport;
//-- Instantiate the unit to test
leds_on UUT (.LPORT(lport));
initial begin
//-- File were to store the simulation results
$dumpfile("leds_on_tb.vcd");
$dumpvars(0, leds_on_tb);
#(DURATION) $display("End of simulation");
$finish;
end
endmodule
|
always @(negedge reset or posedge clk) begin
if (reset == 0) begin
d_out <= 16'h0000;
d_out_mem[resetcount] <= d_out;
laststoredvalue <= d_out;
end else begin
d_out <= d_out + 1'b1;
end
end
always @(bufreadaddr)
bufreadval = d_out_mem[bufreadaddr];
|
`timescale 1 ps / 1 ps
module BRam8x512x512(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb);
input clka;
input [0:0]wea;
input [17:0]addra;
input [7:0]dina;
input clkb;
input [17:0]addrb;
output reg [7:0]doutb;
reg[7 : 0] mem[0 : 2 ** 18 - 1];
always @(posedge clka) begin
if(wea)
mem[addra] <= dina;
else
mem[addra] <= mem[addra];
end
always @(posedge clkb)
doutb <= mem[addrb];
endmodule
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
RowsGenerator
:Function
Generate rows cache, **this module just support Pipeline mode now !!!**
The lowest color_width-bits of out_data are the first row!
You can configure all fifos by yourself, but fifos in one project whcih have same name must have same configurations.
And you can just change the "Write Depth" and "Fifo Implementation", the Read Latency must be 1 !
Give the first output after rows_width * (rows_depth + 1) cycles while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-18
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module RowsGenerator(
\tclk,
\trst_n,
\tin_enable,
\tin_data,
\tout_ready,
\tout_data
\t);
\t/*
\t::description
\tThe width of rows.
\t::range
\t2 - 15
\t*/
\tparameter[3 : 0] rows_width = 3;
\t/*
\t::description
\tThe width of image.
\t::range
\t1 - 4096
\t*/
\tparameter im_width = 320;
\t/*
\t::description
\tColor\'s bit wide.
\t::range
\t1 - 12
\t*/
\tparameter[3: 0] color_width = 8;
\t/*
\t::description
\tThe bits of width of image.
\t::range
\tDepend on width of image
\t*/
\tparameter[4 : 0] im_width_bits = 9;
\t/*
\t::description
\tClock.
\t*/
\tinput clk;
\t/*
\t::description
\tReset, active low.
\t*/
\tinput rst_n;
\t/*
\t::description
\tInput data enable, it works as fifo0\'s wr_en.
\t*/
\tinput in_enable;
\t/*
\t::description
\tInput data, it must be synchronous with in_enable.
\t*/
\tinput [color_width - 1 : 0] in_data;
\t/*
\t::description
\tOutput data ready, in both two mode, it will be high while the out_data can be read.
\t*/
\toutput out_ready;
\t/*
\t::description
\tOutput data, it will be synchronous with out_ready.
\tThe lowest color_width-bits of this are the first row!
\t*/
\toutput[rows_width * color_width - 1 : 0] out_data;
\treg reg_row_wr_en[0 : rows_width];
\twire row_wr_en[0 : rows_width];
\twire row_rd_en[0 : rows_width - 1];
\twire[color_width - 1 : 0] row_din[0 : rows_width - 1];
\twire[color_width - 1 : 0] row_dout[0 : rows_width - 1];
\twire[im_width_bits - 1 : 0] row_num[0 : rows_width - 1];
\twire rst = ~rst_n;
\tgenvar i, j;
\tgenerate
\t\tassign out_ready = row_wr_en[rows_width];
\t\tfor (i = 0; i < rows_width; i = i + 1) begin : fifos
\t\t\t
\t\t\tassign row_rd_en[i] = row_num[i] == im_width - 1 ? 1 : 0;
\t\t\tif (i == 0) begin
\t\t\t\tassign row_wr_en[i] = in_enable;
\t\t\t\tassign row_din[i] = in_data;
\t\t\tend else begin
\t\t\t\tassign row_din[i] = row_dout[i - 1];
\t\t\tend
\t\t\t//One clock delay from fifo read enable to data out
\t\t\talways @(posedge clk)
\t\t\t\treg_row_wr_en[i + 1] <= row_rd_en[i];
\t\t\tassign row_wr_en[i + 1] = reg_row_wr_en[i + 1];
\t\t\tcase (color_width)
\t\t\t\t1 :
\t\t\t\t\t/*
\t\t\t\t\t::description
\t\t\t\t\tFifo which has 1 width and N depth (0 < N < 4096), used for rows cache which color_width is 1.
\t\t\t\t\tYou can configure the fifo by yourself, but all fifos in one project whcih have same name must have same configurations.
\t\t\t\t\tAnd you can just change the "Write Depth" and "Fifo Implementation", the Read Latency must be 1 !
\t\t\t\t\t*/
\t\t\t\t\tFifo1xWidthRows Fifo(
\t\t\t\t\t.clk(clk),
\t\t\t\t\t.rst(rst),
\t\t\t\t\t.din(row_din[i]),
\t\t\t\t\t.wr_en(row_wr_en[i]),
\t\t\t\t\t.rd_en(row_rd_en[i]),
\t\t\t\t\t.dout(row_dout[i]),
\t\t\t\t\t.data_count(row_num[i])
\t\t\t\t\t);
\t\t\t\t2, 3, 4 :
\t\t\t\t\t/*
\t\t\t\t\t::description
\t\t\t\t\tFifo which has 4 width and N depth (0 < N < 4096), used for rows cache which color_width is 2, 3 and 4.
\t\t\t\t\tYou can configure the fifo by yourself, but all fifos in one project whcih have same name must have same configurations.
\t\t\t\t\tAnd you can just change the "Write Depth" and "Fifo Implementation", the Read Latency must be 1 !
\t\t\t\t\t*/
\t\t\t\t\tFifo4xWidthRows Fifo(
\t\t\t\t\t.clk(clk),
\t\t\t\t\t.rst(rst),
\t\t\t\t\t.din(row_din[i]),
\t\t\t\t\t.wr_en(row_wr_en[i]),
\t\t\t\t\t.rd_en(row_rd_en[i]),
\t\t\t\t\t.dout(row_dout[i]),
\t\t\t\t\t.data_count(row_num[i])
\t\t\t\t\t);
\t\t\t\t5, 6, 7, 8 :
\t\t\t\t\t/*
\t\t\t\t\t::description
\t\t\t\t\tFifo which has 8 width and N depth (0 < N < 4096), used for rows cache which color_width is 5, 6, 7 and 8.
\t\t\t\t\tYou can configure the fifo by yourself, but all fifos in one project whcih have same name must have same configurations.
\t\t\t\t\tAnd you can just change the "Write Depth" and "Fifo Implementation", the Read Latency must be 1 !
\t\t\t\t\t*/
\t\t\t\t\tFifo8xWidthRows Fifo(
\t\t\t\t\t.clk(clk),
\t\t\t\t\t.rst(rst),
\t\t\t\t\t.din(row_din[i]),
\t\t\t\t\t.wr_en(row_wr_en[i]),
\t\t\t\t\t.rd_en(row_rd_en[i]),
\t\t\t\t\t.dout(row_dout[i]),
\t\t\t\t\t.data_count(row_num[i])
\t\t\t\t\t);
\t\t\t\t9, 10, 11, 12 :
\t\t\t\t\t/*
\t\t\t\t\t::description
\t\t\t\t\tFifo which has 12 width and N depth (0 < N < 4096), used for rows cache which color_width is 9, 10, 11 and 12.
\t\t\t\t\tYou can configure the fifo by yourself, but all fifos in one project whcih have same name must have same configurations.
\t\t\t\t\tAnd you can just change the "Write Depth" and "Fifo Implementation", the Read Latency must be 1 !
\t\t\t\t\t*/
\t\t\t\t\tFifo12xWidthRows Fifo(
\t\t\t\t\t.clk(clk),
\t\t\t\t\t.rst(rst),
\t\t\t\t\t.din(row_din[i]),
\t\t\t\t\t.wr_en(row_wr_en[i]),
\t\t\t\t\t.rd_en(row_rd_en[i]),
\t\t\t\t\t.dout(row_dout[i]),
\t\t\t\t\t.data_count(row_num[i])
\t\t\t\t\t);
\t\t\t\tdefault : /* default */;
\t\t\tendcase
\t\t\tassign out_data[(i + 1) * color_width - 1 : i * color_width] = out_ready ? row_dout[rows_width - 1 - i] : 0;
\t\t
\t\tend
\tendgenerate
endmodule
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
VGA
:Function
Show with VGA.
:Module
Main module
:Version
1.0
:Modified
2015-05-12
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
http://fil.dtysky.moe
Sources for this project:
https://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
[email protected]
My blog:
http://dtysky.moe
*/
`timescale 1ns / 1ps
module VGA640x480(
clk_25m,
rst_n,
in_data,
vga_red,
vga_green,
vga_blue,
vga_hsync,
vga_vsync,
frame_addr
);
input clk_25m;
input rst_n;
input [15 : 0] in_data;
output reg[4:0] vga_red;
output reg[5:0] vga_green;
output reg[4:0] vga_blue;
output reg vga_hsync;
output reg vga_vsync;
output [16:0] frame_addr;
reg[9:0] con_h;
reg[9:0] con_v;
reg[16:0] address;
reg blank;
parameter hRez = 640;
parameter hStartSync = 640+16;
parameter hEndSync = 640+16+96;
parameter hMaxCount = 800;
parameter vRez = 480;
parameter vStartSync = 480+10;
parameter vEndSync = 480+10+2;
parameter vMaxCount = 480+10+2+33;
parameter hsync_active =0;
parameter vsync_active = 0;
assign frame_addr = address;
always @(posedge clk_25m or negedge rst_n) begin
if(~rst_n) begin
con_h <= 0;
con_v <= 0;
end else if(con_h == hMaxCount-1) begin
\tcon_h <= 10'b0;
\tif (con_v == vMaxCount-1 )
con_v <= 10'b0;
\telse
con_v <= con_v+1;
\tend else
con_h <= con_h+1;
end
always @(posedge clk_25m or negedge rst_n) begin
if(~rst_n) begin
vga_red <= 0;
vga_green <= 0;
vga_blue <= 0;
\tend else if (blank ==0) begin
\t\tvga_red <= in_data[15:11];
\t\tvga_green <= in_data[10:5];
\t\tvga_blue <= in_data[4:0];
\t\tend else begin
\t\tvga_red <= 0;
\t\tvga_green <= 0;
\t\tvga_blue <= 0;
end;
end
always @(posedge clk_25m or negedge rst_n) begin
if(~rst_n) begin
address <= 17'b0;
blank <= 1;
\tend else if (con_v >= 360 || con_v < 120) begin
\t\taddress <= 17'b0;
\t\tblank <= 1;
end else begin
if (con_h < 480 && con_h >= 160) begin
\tblank <= 0;
\taddress <= address+1;
\tend else blank <= 1;
end;
end
always @(posedge clk_25m) begin
\tif( con_h > hStartSync && con_h <= hEndSync)
\t\tvga_hsync <= hsync_active;
\telse
vga_hsync <= ~ hsync_active;
end
always @(posedge clk_25m) begin
\tif( con_v >= vStartSync && con_v < vEndSync )
\t\tvga_vsync <= vsync_active;
\telse
\t\tvga_vsync <= ~ vsync_active;
end
endmodule
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
ColorReversal
:Function
Get a reversal of all ponit's color.
Give the first output after 1 cycle while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-16
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module ColorReversal(
\tclk,
\trst_n,
\tin_enable,
\tin_data,
\tout_ready,
\tout_data);
\t/*
\t::description
\tThis module's working mode.
\t::range
\t0 for Pipelines, 1 for Req-ack
\t*/
\tparameter[0 : 0] work_mode = 0;
\t/*
\t::description
\tChannels for color, 1 for gray, 3 for rgb, etc.
\t*/
\tparameter color_channels = 3;
\t/*
\t::description
\tColor's bit wide
\t::range
\t1 - 12
\t*/
\tparameter[3: 0] color_width = 8;
\t/*
\t::description
\tClock.
\t*/
\tinput clk;
\t/*
\t::description
\tReset, active low.
\t*/
\tinput rst_n;
\t/*
\t::description
\tInput data enable, in pipelines mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be changes.
\t*/
\tinput in_enable;
\t/*
\t::description
\tInput data, it must be synchronous with in_enable.
\t*/
\tinput [color_channels * color_width - 1 : 0] in_data;
\t/*
\t::description
\tOutput data ready, in both two mode, it will be high while the out_data can be read.
\t*/
\toutput out_ready;
\t/*
\t::description
\tOutput data, it will be synchronous with out_ready.
\t*/
\toutput[color_channels * color_width - 1 : 0] out_data;
\treg reg_out_ready;
\treg[color_channels * color_width - 1 : 0] reg_out_data;
\tgenvar i;
\tgenerate
\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\tif(~rst_n | ~in_enable)
\t\t\t\treg_out_ready <= 0;
\t\t\telse
\t\t\t\treg_out_ready <= 1;
\t\tend
\t\tassign out_ready = reg_out_ready;
\t\tif(work_mode == 0) begin
\t\t\talways @(posedge clk)
\t\t\t\treg_out_data <= ~in_data;
\t\tend else begin
\t\t\talways @(posedge in_enable)
\t\t\t\treg_out_data <= ~in_data;
\t\tend
\t\tassign out_data = out_ready == 0 ? 0 : reg_out_data;
\tendgenerate
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
// Date : Thu May 28 19:32:19 2015
// Host : Dtysky running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// b:/Complex_Mind/FPGA-Imaging-Library/Master/Geometry/Scale/HDL/Scale.srcs/sources_1/ip/Multiplier12x24SCL/Multiplier12x24SCL_funcsim.v
// Design : Multiplier12x24SCL
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "mult_gen_v12_0,Vivado 2014.4" *) (* CHECK_LICENSE_TYPE = "Multiplier12x24SCL,mult_gen_v12_0,{}" *)
(* core_generation_info = "Multiplier12x24SCL,mult_gen_v12_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=zynq,C_HAS_CE=0,C_HAS_SCLR=1,C_LATENCY=3,C_A_WIDTH=12,C_A_TYPE=1,C_B_WIDTH=24,C_B_TYPE=1,C_OUT_HIGH=35,C_OUT_LOW=17,C_MULT_TYPE=1,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}" *)
(* NotValidForBitStream *)
module Multiplier12x24SCL
(CLK,
A,
B,
SCLR,
P);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) input CLK;
input [11:0]A;
input [23:0]B;
(* x_interface_info = "xilinx.com:signal:reset:1.0 sclr_intf RST" *) input SCLR;
output [18:0]P;
wire [11:0]A;
wire [23:0]B;
wire CLK;
wire [18:0]P;
wire SCLR;
wire [47:0]NLW_U0_PCASC_UNCONNECTED;
wire [1:0]NLW_U0_ZERO_DETECT_UNCONNECTED;
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "12" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "24" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "3" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "1" *)
(* C_OPTIMIZE_GOAL = "1" *)
(* C_OUT_HIGH = "35" *)
(* C_OUT_LOW = "17" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* DONT_TOUCH *)
(* downgradeipidentifiedwarnings = "yes" *)
Multiplier12x24SCL_mult_gen_v12_0__parameterized0 U0
(.A(A),
.B(B),
.CE(1\'b1),
.CLK(CLK),
.P(P),
.PCASC(NLW_U0_PCASC_UNCONNECTED[47:0]),
.SCLR(SCLR),
.ZERO_DETECT(NLW_U0_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule
(* ORIG_REF_NAME = "mult_gen_v12_0" *) (* C_VERBOSITY = "0" *) (* C_MODEL_TYPE = "0" *)
(* C_OPTIMIZE_GOAL = "1" *) (* C_XDEVICEFAMILY = "zynq" *) (* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *) (* C_LATENCY = "3" *) (* C_A_WIDTH = "12" *)
(* C_A_TYPE = "1" *) (* C_B_WIDTH = "24" *) (* C_B_TYPE = "1" *)
(* C_OUT_HIGH = "35" *) (* C_OUT_LOW = "17" *) (* C_MULT_TYPE = "1" *)
(* C_CE_OVERRIDES_SCLR = "0" *) (* C_CCM_IMP = "0" *) (* C_B_VALUE = "10000001" *)
(* C_HAS_ZERO_DETECT = "0" *) (* C_ROUND_OUTPUT = "0" *) (* C_ROUND_PT = "0" *)
(* downgradeipidentifiedwarnings = "yes" *)
module Multiplier12x24SCL_mult_gen_v12_0__parameterized0
(CLK,
A,
B,
CE,
SCLR,
ZERO_DETECT,
P,
PCASC);
input CLK;
input [11:0]A;
input [23:0]B;
input CE;
input SCLR;
output [1:0]ZERO_DETECT;
output [18:0]P;
output [47:0]PCASC;
wire [11:0]A;
wire [23:0]B;
wire CE;
wire CLK;
wire [18:0]P;
wire [47:0]PCASC;
wire SCLR;
wire [1:0]ZERO_DETECT;
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "12" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "24" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "3" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "1" *)
(* C_OPTIMIZE_GOAL = "1" *)
(* C_OUT_HIGH = "35" *)
(* C_OUT_LOW = "17" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* downgradeipidentifiedwarnings = "yes" *)
Multiplier12x24SCL_mult_gen_v12_0_viv__parameterized0 i_mult
(.A(A),
.B(B),
.CE(CE),
.CLK(CLK),
.P(P),
.PCASC(PCASC),
.SCLR(SCLR),
.ZERO_DETECT(ZERO_DETECT));
endmodule
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`pragma protect key_block
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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`pragma protect key_block
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`pragma protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8768)
`pragma protect data_block
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`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
module\tI2C_OV7670_RGB565_Config
(
\tinput\t\t[7:0]\tLUT_INDEX,
\toutput\treg\t[15:0]\tLUT_DATA)
;
parameter\tRead_DATA\t=\t0;\t\t
parameter\tSET_OV7670\t=\t2;\t\t\t
always@(*)
begin
\tcase(LUT_INDEX)
\t
SET_OV7670 + 0 \t: \tLUT_DATA\t= \t16'h1214;\t
\tSET_OV7670 + 1 \t: \tLUT_DATA\t= \t16'h40d0;\t
\tSET_OV7670 + 2 \t: \tLUT_DATA\t= \t16'h3a04;\t
\tSET_OV7670 + 3 \t: \tLUT_DATA\t=\t16'h3dc8;
\tSET_OV7670 + 4 \t: \tLUT_DATA\t= \t16'h1e31;\t
\tSET_OV7670 + 5 \t: \tLUT_DATA\t= \t16'h6b00;\t
\tSET_OV7670 + 6 \t: \tLUT_DATA\t= \t16'h32b6;\t
\tSET_OV7670 + 7 \t: \tLUT_DATA\t= \t16'h1713;\t
\tSET_OV7670 + 8 \t: \tLUT_DATA\t= \t16'h1801;\t
\tSET_OV7670 + 9 \t: \tLUT_DATA\t= \t16'h1902;\t
\tSET_OV7670 + 10\t: \tLUT_DATA\t= \t16'h1a7a;\t
\tSET_OV7670 + 11\t: \tLUT_DATA\t= \t16'h030a;\t
\tSET_OV7670 + 12 : \tLUT_DATA\t= \t16'h0c00;
\tSET_OV7670 + 13 : \tLUT_DATA\t= \t16'h3e00;
\tSET_OV7670 + 14 : \tLUT_DATA\t= \t16'h7000;\t
\tSET_OV7670 + 15 : \tLUT_DATA\t= \t16'h7100;
\tSET_OV7670 + 16 : \tLUT_DATA\t= \t16'h7211;\t
\tSET_OV7670 + 17 : \tLUT_DATA\t= \t16'h7300;\t
\tSET_OV7670 + 18 : \tLUT_DATA\t= \t16'ha202;\t
\tSET_OV7670 + 19 : \tLUT_DATA\t= \t16'h1180;\t
\tSET_OV7670 + 20 : \tLUT_DATA\t= \t16'h7a20;
\tSET_OV7670 + 21 : \tLUT_DATA\t= \t16'h7b1c;
\tSET_OV7670 + 22 : \tLUT_DATA\t= \t16'h7c28;
\tSET_OV7670 + 23 : \tLUT_DATA\t= \t16'h7d3c;
\tSET_OV7670 + 24 : \tLUT_DATA\t= \t16'h7e55;
\tSET_OV7670 + 25 : \tLUT_DATA\t= \t16'h7f68;
\tSET_OV7670 + 26 : \tLUT_DATA\t= \t16'h8076;
\tSET_OV7670 + 27 : \tLUT_DATA\t= \t16'h8180;
\tSET_OV7670 + 28 : \tLUT_DATA\t= \t16'h8288;
\tSET_OV7670 + 29 : \tLUT_DATA\t= \t16'h838f;
\tSET_OV7670 + 30 : \tLUT_DATA\t= \t16'h8496;
\tSET_OV7670 + 31 : \tLUT_DATA\t= \t16'h85a3;
\tSET_OV7670 + 32 : \tLUT_DATA\t= \t16'h86af;
\tSET_OV7670 + 33 : \tLUT_DATA\t= \t16'h87c4;
\tSET_OV7670 + 34 : \tLUT_DATA\t= \t16'h88d7;
\tSET_OV7670 + 35 : \tLUT_DATA\t= \t16'h89e8;
\tSET_OV7670 + 36 : \tLUT_DATA\t= \t16'h13e0;
\tSET_OV7670 + 37 : \tLUT_DATA\t= \t16'h0000;
\tSET_OV7670 + 38 : \tLUT_DATA\t= \t16'h1000;
\tSET_OV7670 + 39 : \tLUT_DATA\t= \t16'h0d00;
\tSET_OV7670 + 40 : \tLUT_DATA\t= \t16'h1428;\t
\tSET_OV7670 + 41 : \tLUT_DATA\t= \t16'ha505;
\tSET_OV7670 + 42 : \tLUT_DATA\t= \t16'hab07;
\tSET_OV7670 + 43 : \tLUT_DATA\t= \t16'h2475;
\tSET_OV7670 + 44 : \tLUT_DATA\t= \t16'h2563;
\tSET_OV7670 + 45 : \tLUT_DATA\t= \t16'h26a5;
\tSET_OV7670 + 46 : \tLUT_DATA\t= \t16'h9f78;
\tSET_OV7670 + 47 : \tLUT_DATA\t= \t16'ha068;
\tSET_OV7670 + 48 : \tLUT_DATA\t= \t16'ha103;
\tSET_OV7670 + 49 : \tLUT_DATA\t= \t16'ha6df;
\tSET_OV7670 + 50 : \tLUT_DATA\t= \t16'ha7df;
\tSET_OV7670 + 51 : \tLUT_DATA\t= \t16'ha8f0;
\tSET_OV7670 + 52 : \tLUT_DATA\t= \t16'ha990;
\tSET_OV7670 + 53 : \tLUT_DATA\t= \t16'haa94;
\tSET_OV7670 + 54 : \tLUT_DATA\t= \t16'h13ef;\t
\tSET_OV7670 + 55\t: \tLUT_DATA\t= \t16'h0e61;
\tSET_OV7670 + 56\t: \tLUT_DATA\t= \t16'h0f4b;
\tSET_OV7670 + 57\t: \tLUT_DATA\t= \t16'h1602;
\t
\tSET_OV7670 + 58 : \tLUT_DATA\t= \t16'h2102;
\tSET_OV7670 + 59 : \tLUT_DATA\t= \t16'h2291;
\tSET_OV7670 + 60 : \tLUT_DATA\t= \t16'h2907;
\tSET_OV7670 + 61 : \tLUT_DATA\t= \t16'h330b;
\tSET_OV7670 + 62 : \tLUT_DATA\t= \t16'h350b;
\tSET_OV7670 + 63 : \tLUT_DATA\t= \t16'h371d;
\tSET_OV7670 + 64 : \tLUT_DATA\t= \t16'h3871;
\tSET_OV7670 + 65 : \tLUT_DATA\t= \t16'h392a;
\tSET_OV7670 + 66 : \tLUT_DATA\t= \t16'h3c78;
\tSET_OV7670 + 67 : \tLUT_DATA\t= \t16'h4d40;
\tSET_OV7670 + 68\t: \tLUT_DATA\t= \t16'h4e20;
\tSET_OV7670 + 69\t: \tLUT_DATA\t= \t16'h6900;
\t
\tSET_OV7670 + 70 : \tLUT_DATA\t= \t16'h7419;
\tSET_OV7670 + 71 : \tLUT_DATA\t= \t16'h8d4f;
\tSET_OV7670 + 72 : \tLUT_DATA\t= \t16'h8e00;
\tSET_OV7670 + 73 : \tLUT_DATA\t= \t16'h8f00;
\tSET_OV7670 + 74 : \tLUT_DATA\t= \t16'h9000;
\tSET_OV7670 + 75 : \tLUT_DATA\t= \t16'h9100;
\tSET_OV7670 + 76 : \tLUT_DATA\t= \t16'h9200;
\tSET_OV7670 + 77 : \tLUT_DATA\t= \t16'h9600;
\tSET_OV7670 + 78 : \tLUT_DATA\t= \t16'h9a80;
\tSET_OV7670 + 79 : \tLUT_DATA\t= \t16'hb084;
\tSET_OV7670 + 80 : \tLUT_DATA\t= \t16'hb10c;
\tSET_OV7670 + 81 : \tLUT_DATA\t= \t16'hb20e;
\tSET_OV7670 + 82 : \tLUT_DATA\t= \t16'hb382;
\tSET_OV7670 + 83\t: \tLUT_DATA\t= \t16'hb80a;
\tSET_OV7670 + 84 :\tLUT_DATA\t=\t16'h4314;
\tSET_OV7670 + 85 :\tLUT_DATA\t=\t16'h44f0;
\tSET_OV7670 + 86 :\tLUT_DATA\t=\t16'h4534;
\tSET_OV7670 + 87 :\tLUT_DATA\t=\t16'h4658;
\tSET_OV7670 + 88 :\tLUT_DATA\t=\t16'h4728;
\tSET_OV7670 + 89 :\tLUT_DATA\t=\t16'h483a;
\tSET_OV7670 + 90 :\tLUT_DATA\t=\t16'h5988;
\tSET_OV7670 + 91 :\tLUT_DATA\t=\t16'h5a88;
\tSET_OV7670 + 92 :\tLUT_DATA\t=\t16'h5b44;
\tSET_OV7670 + 93 :\tLUT_DATA\t=\t16'h5c67;
\tSET_OV7670 + 94 :\tLUT_DATA\t=\t16'h5d49;
\tSET_OV7670 + 95 :\tLUT_DATA\t=\t16'h5e0e;
\tSET_OV7670 + 96 :\tLUT_DATA\t=\t16'h6404;
\tSET_OV7670 + 97 :\tLUT_DATA\t=\t16'h6520;
\tSET_OV7670 + 98 :\tLUT_DATA\t=\t16'h6605;
\tSET_OV7670 + 99 :\tLUT_DATA\t=\t16'h9404;
\tSET_OV7670 + 100 :\tLUT_DATA\t=\t16'h9508;
\tSET_OV7670 + 101 :\tLUT_DATA\t=\t16'h6c0a;
\tSET_OV7670 + 102 :\tLUT_DATA\t=\t16'h6d55;
\tSET_OV7670 + 103 :\tLUT_DATA\t=\t16'h6e11;
\tSET_OV7670 + 104 :\tLUT_DATA\t=\t16'h6f9f;
\tSET_OV7670 + 105 :\tLUT_DATA\t=\t16'h6a40;
\tSET_OV7670 + 106 :\tLUT_DATA\t=\t16'h0140;
\tSET_OV7670 + 107 :\tLUT_DATA\t=\t16'h0240;
\tSET_OV7670 + 108 :\tLUT_DATA\t=\t16'h13e7;
\tSET_OV7670 + 109 :\tLUT_DATA\t=\t16'h1500;
\t
\tSET_OV7670 + 110 :\tLUT_DATA\t= \t16'h4f80;
\tSET_OV7670 + 111 :\tLUT_DATA\t= \t16'h5080;
\tSET_OV7670 + 112 :\tLUT_DATA\t= \t16'h5100;
\tSET_OV7670 + 113 :\tLUT_DATA\t= \t16'h5222;
\tSET_OV7670 + 114 :\tLUT_DATA\t= \t16'h535e;
\tSET_OV7670 + 115 :\tLUT_DATA\t= \t16'h5480;
\tSET_OV7670 + 116 :\tLUT_DATA\t= \t16'h589e;
\t
\tSET_OV7670 + 117 : \tLUT_DATA\t=\t16'h4108;
\tSET_OV7670 + 118 : \tLUT_DATA\t=\t16'h3f00;
\tSET_OV7670 + 119 : \tLUT_DATA\t=\t16'h7505;
\tSET_OV7670 + 120 : \tLUT_DATA\t=\t16'h76e1;
\tSET_OV7670 + 121 : \tLUT_DATA\t=\t16'h4c00;
\tSET_OV7670 + 122 : \tLUT_DATA\t=\t16'h7701;
\t
\tSET_OV7670 + 123 : \tLUT_DATA\t=\t16'h4b09;
\tSET_OV7670 + 124 : \tLUT_DATA\t=\t16'hc9F0;
\tSET_OV7670 + 125 : \tLUT_DATA\t=\t16'h4138;
\tSET_OV7670 + 126 : \tLUT_DATA\t=\t16'h5640;
\t
\t
\tSET_OV7670 + 127 : \tLUT_DATA\t=\t16'h3411;
\tSET_OV7670 + 128 : \tLUT_DATA\t=\t16'h3b02;
\tSET_OV7670 + 129 : \tLUT_DATA\t=\t16'ha489;
\tSET_OV7670 + 130 : \tLUT_DATA\t=\t16'h9600;
\tSET_OV7670 + 131 : \tLUT_DATA\t=\t16'h9730;
\tSET_OV7670 + 132 : \tLUT_DATA\t=\t16'h9820;
\tSET_OV7670 + 133 : \tLUT_DATA\t=\t16'h9930;
\tSET_OV7670 + 134 : \tLUT_DATA\t=\t16'h9a84;
\tSET_OV7670 + 135 : \tLUT_DATA\t=\t16'h9b29;
\tSET_OV7670 + 136 : \tLUT_DATA\t=\t16'h9c03;
\tSET_OV7670 + 137 : \tLUT_DATA\t=\t16'h9d4c;
\tSET_OV7670 + 138 : \tLUT_DATA\t=\t16'h9e3f;
\tSET_OV7670 + 139 : \tLUT_DATA\t=\t16'h7804;
\t
\t
\tSET_OV7670 + 140 :\tLUT_DATA\t=\t16'h7901;
\tSET_OV7670 + 141 :\tLUT_DATA\t= \t16'hc8f0;
\tSET_OV7670 + 142 :\tLUT_DATA\t= \t16'h790f;
\tSET_OV7670 + 143 :\tLUT_DATA\t= \t16'hc800;
\tSET_OV7670 + 144 :\tLUT_DATA\t= \t16'h7910;
\tSET_OV7670 + 145 :\tLUT_DATA\t= \t16'hc87e;
\tSET_OV7670 + 146 :\tLUT_DATA\t= \t16'h790a;
\tSET_OV7670 + 147 :\tLUT_DATA\t= \t16'hc880;
\tSET_OV7670 + 148 :\tLUT_DATA\t= \t16'h790b;
\tSET_OV7670 + 149 :\tLUT_DATA\t= \t16'hc801;
\tSET_OV7670 + 150 :\tLUT_DATA\t= \t16'h790c;
\tSET_OV7670 + 151 :\tLUT_DATA\t= \t16'hc80f;
\tSET_OV7670 + 152 :\tLUT_DATA\t= \t16'h790d;
\tSET_OV7670 + 153 :\tLUT_DATA\t= \t16'hc820;
\tSET_OV7670 + 154 :\tLUT_DATA\t= \t16'h7909;
\tSET_OV7670 + 155 :\tLUT_DATA\t= \t16'hc880;
\tSET_OV7670 + 156 :\tLUT_DATA\t= \t16'h7902;
\tSET_OV7670 + 157 :\tLUT_DATA\t= \t16'hc8c0;
\tSET_OV7670 + 158 :\tLUT_DATA\t= \t16'h7903;
\tSET_OV7670 + 159 :\tLUT_DATA\t= \t16'hc840;
\tSET_OV7670 + 160 :\tLUT_DATA\t= \t16'h7905;
\tSET_OV7670 + 161 :\tLUT_DATA\t= \t16'hc830;
\tSET_OV7670 + 162 :\tLUT_DATA\t= \t16'h7926;
\tSET_OV7670 + 163 :\tLUT_DATA\t= \t16'h0903;
\tSET_OV7670 + 164 :\tLUT_DATA\t= \t16'h3b42;
\tdefault\t\t :\tLUT_DATA\t=\t0;
\tendcase
end
endmodule
|
`timescale 1 ps / 1 ps
module BRam8x512x512(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb);
input clka;
input [0:0]wea;
input [17:0]addra;
input [7:0]dina;
input clkb;
input [17:0]addrb;
output reg [7:0]doutb;
reg[7 : 0] mem[0 : 2 ** 18 - 1];
always @(posedge clka) begin
if(wea)
mem[addra] <= dina;
else
mem[addra] <= mem[addra];
end
always @(posedge clkb)
doutb <= mem[addrb];
endmodule
|
/*
:Project
FPGA-Imaging-Library
:Design
FrameController2
:Function
Controlling a frame(block ram etc.), writing or reading with counts.
For controlling a BlockRAM from xilinx.
Give the first output after mul_delay + 2 + ram_read_latency cycles while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-25
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module FrameController2(
\tclk,
\trst_n,
\tin_count_x,
\tin_count_y,
\tin_enable,
\tin_data,
\tout_ready,
\tout_data,
\tram_addr);
\t/*
\t::description
\tThis module\'s working mode.
\t::range
\t0 for Pipline, 1 for Req-ack
\t*/
\tparameter work_mode = 0;
\t/*
\t::description
\tThis module\'s WR mode.
\t::range
\t0 for Write, 1 for Read
\t*/
\tparameter wr_mode = 0;
\t/*
\t::description
\tData bit width.
\t*/
\tparameter data_width = 8;
\t/*
\t::description
\tWidth of image.
\t::range
\t1 - 4096
\t*/
\tparameter im_width = 320;
\t/*
\t::description
\tHeight of image.
\t::range
\t1 - 4096
\t*/
\tparameter im_height = 240;
\t/*
\t::description
\tThe bits of width of image.
\t::range
\tDepend on width of image
\t*/
\tparameter im_width_bits = 9;
\t/*
\t::description
\tAddress bit width of a ram for storing this image.
\t::range
\tDepend on im_width and im_height.
\t*/
\tparameter addr_width = 17;
\t/*
\t::description
\tRL of RAM, in xilinx 7-series device, it is 2.
\t::range
\t0 - 15, Depend on your using ram.
\t*/
\tparameter ram_read_latency = 2;
\t/*
\t::description
\tDelay for multiplier.
\t::range
\tDepend on your multilpliers\' configurations
\t*/
\tparameter mul_delay = 3;
\t/*
\t::description
\tClock.
\t*/
\tinput clk;
\t/*
\t::description
\tReset, active low.
\t*/
\tinput rst_n;
\t/*
\t::description
\tInput pixel count for width.
\t*/
\tinput[im_width_bits - 1 : 0] in_count_x;
\t/*
\t::description
\tInput pixel count for height.
\t*/
\tinput[im_width_bits - 1 : 0] in_count_y;
\t/*
\t::description
\tInput data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
\t*/
\tinput in_enable;
\t/*
\t::description
\tInput data, it must be synchronous with in_enable.
\t*/
\tinput [data_width - 1 : 0] in_data;
\t/*
\t::description
\tOutput data ready, in both two mode, it will be high while the out_data can be read.
\t*/
\toutput out_ready;
\t/*
\t::description
\tOutput data, it will be synchronous with out_ready.
\t*/
\toutput[data_width - 1 : 0] out_data;
\t/*
\t::description
\tAddress for ram.
\t*/
\toutput[addr_width - 1 : 0] ram_addr;
\treg[3 : 0] con_enable;
\treg[im_width_bits - 1 : 0] reg_in_count_x;
\treg[im_width_bits - 1 : 0] reg_in_count_y;
\treg[addr_width - 1 : 0] reg_addr;
\twire[11 : 0] mul_a, mul_b;
\twire[23 : 0] mul_p;
\tassign mul_a = {{(12 - im_width_bits){1\'b0}}, in_count_y};
\tassign mul_b = im_width;
\tgenvar i;
\tgenerate
\t\t/*
\t\t::description
\t\tMultiplier for Unsigned 12bits x Unsigned 12bits, used for creating address for frame.
\t\tYou can configure the multiplier by yourself, then change the "mul_delay".
\t\tYou can not change the ports\' configurations!
\t\t*/
\t\tMultiplier12x12FR2 Mul(.CLK(clk), .A(mul_a), .B(mul_b), .SCLR(~rst_n), .P(mul_p));
\t\tfor (i = 0; i < mul_delay; i = i + 1) begin : conut_buffer
\t\t\treg[im_width_bits - 1 : 0] b;
\t\t\tif(i == 0) begin
\t\t\t\talways @(posedge clk)
\t\t\t\t\tb <= in_count_x;
\t\t\tend else begin
\t\t\t\talways @(posedge clk)
\t\t\t\t\tb <= conut_buffer[i - 1].b;
\t\t\tend
\t\tend
\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\tif(~rst_n || ~in_enable) begin
\t\t\t\treg_addr <= 0;
\t\t\tend else begin
\t\t\t\treg_addr <= mul_p + conut_buffer[mul_delay - 1].b;
\t\t\tend
\t\tend
\t\tassign ram_addr = reg_addr;
\t\tif(wr_mode == 0) begin
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\tcon_enable <= 0;
\t\t\t\telse if(con_enable == mul_delay + 1)
\t\t\t\t\tcon_enable <= con_enable;
\t\t\t\telse
\t\t\t\t\tcon_enable <= con_enable + 1;
\t\t\tend
\t\t\tassign out_ready = con_enable == mul_delay + 1 ? 1 : 0;
\t\t\tif(work_mode == 0) begin
\t\t\t\tfor (i = 0; i < mul_delay + 1; i = i + 1) begin : buffer
\t\t\t\t\treg[data_width - 1 : 0] b;
\t\t\t\t\tif(i == 0) begin
\t\t\t\t\t\talways @(posedge clk)
\t\t\t\t\t\t\tb <= in_data;
\t\t\t\t\tend else begin
\t\t\t\t\t\talways @(posedge clk)
\t\t\t\t\t\t\tb <= buffer[i - 1].b;
\t\t\t\t\tend
\t\t\t\tend
\t\t\t\tassign out_data = out_ready ? buffer[mul_delay].b : 0;
\t\t\tend else begin
\t\t\t\treg[data_width - 1 : 0] reg_out_data;
\t\t\t\talways @(posedge in_enable)
\t\t\t\t\treg_out_data = in_data;
\t\t\t\tassign out_data = out_ready ? reg_out_data : 0;
\t\t\tend
\t\tend else begin
\t\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\t\tif(~rst_n || ~in_enable)
\t\t\t\t\tcon_enable <= 0;
\t\t\t\telse if (con_enable == mul_delay + 1 + ram_read_latency)
\t\t\t\t\tcon_enable <= con_enable;
\t\t\t\telse
\t\t\t\t\tcon_enable <= con_enable + 1;
\t\t\tend
\t\t\tassign out_data = out_ready ? in_data : 0;
\t\t\tassign out_ready = con_enable == mul_delay + 1 + ram_read_latency ? 1 : 0;
\t\tend
\tendgenerate
endmodule
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
Threshold
:Function
Convert gray-scales image to binary images.
Give the first output after 1 cycles while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-15
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module Threshold(
\tclk,
\trst_n,
\tth_mode,
\tth1,
\tth2,
\tin_enable,
\tin_data,
\tout_ready,
\tout_data
);
\t/*
\t::description
\tThis module\'s working mode.
\t::range
\t0 for Pipeline, 1 for Req-ack
\t*/
\tparameter work_mode = 0;
\t/*
\t::description
\tColor\'s bit width.
\t::range
\t1 - 12
\t*/
\tparameter color_width = 8;
\t/*
\t::description
\tClock.
\t*/
\tinput clk;
\t/*
\t::description
\tReset, active low.
\t*/
\tinput rst_n;
\t/*
\t::description
\tThe method for processing.
\t::range
\t0 for Base, 1 for Contour
\t*/
\tinput th_mode;
\t/*
\t::description
\tFirst thorshold, used for all methods.
\t*/
\tinput [color_width - 1 : 0] th1;
\t/*
\t::description
\tSecond thorshold, only used for "Contour" method.
\t*/
\tinput [color_width - 1 : 0] th2;
\t/*
\t::description
\tInput data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be changes.
\t*/
\tinput in_enable;
\t/*
\t::description
\tInput data, it must be synchronous with in_enable.
\t*/
\tinput [color_width - 1 : 0] in_data;
\t/*
\t::description
\tOutput data ready, in both two mode, it will be high while the out_data can be read.
\t*/
\toutput out_ready;
\t/*
\t::description
\tOutput data, it will be synchronous with out_ready.
\t*/
\toutput out_data;
\treg reg_out_ready;
\treg reg_out_data;
\tgenerate
\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\tif(~rst_n || ~in_enable) begin
\t\t\t\treg_out_ready <= 0;
\t\t\tend else begin
\t\t\t\treg_out_ready <= 1;
\t\t\tend
\t\tend
\t\tif(work_mode == 0) begin
\t\t\talways @(posedge clk) begin
\t\t\t\tcase (th_mode)
\t\t\t\t\t0 : reg_out_data <= in_data > th1 ? 1 : 0;
\t\t\t\t\t1 : reg_out_data <= in_data > th1 && in_data <= th2 ? 1 : 0;
\t\t\t\t\tdefault : /* default */;
\t\t\t\tendcase
\t\t\tend
\t\tend else begin
\t\t\talways @(posedge in_enable) begin
\t\t\t\tcase (th_mode)
\t\t\t\t\t0 : reg_out_data <= in_data > th1 ? 1 : 0;
\t\t\t\t\t1 : reg_out_data <= in_data > th1 && in_data <= th2 ? 1 : 0;
\t\t\t\t\tdefault : /* default */;
\t\t\t\tendcase
\t\t\tend
\t\tend
\t\tassign out_ready = reg_out_ready;
\t\tassign out_data = out_ready == 0 ? 0 : reg_out_data;
\tendgenerate
endmodule
|
/*
:Project
FPGA-Imaging-Library
:Design
ColorGray2Channels
:Function
Covert Gray-scale to Channels.
:Module
Main module
:Version
1.0
:Modified
2015-05-12
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module ColorGray2Channels(
\tgray,
\tchannels
);
\tparameter color_width = 8;
\tparameter color_channels = 3;
\tinput[color_width - 1 : 0] gray;
\toutput[color_channels * color_width - 1 : 0] channels;
\tgenvar i;
\tgenerate
\t\t`define h (i + 1) * color_width - 1
\t\t`define l i * color_width
\t\tfor (i = 0; i < color_channels; i = i + 1) begin: channel
\t\t\tassign channels[`h : `l] = gray;
\t\tend
\t\t`undef h
\t\t`undef l
\tendgenerate
endmodule
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
MatchTemplateBin
:Function
Match a binary from template for binary images.
It will give the first output after 1 cycle while in_enable enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-25
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://fil.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module MatchTemplateBin(
\tclk,
\trst_n,
\ttemplate,
\tin_enable,
\tin_data,
\tout_ready,
\tout_data);
\t/*
\t::description
\tThis module's working mode.
\t::range
\t0 for Pipeline, 1 for Req-ack
\t*/
\tparameter[0 : 0] work_mode = 0;
\t/*
\t::description
\tThe width(and height) of window.
\t::range
\t2 - 15
\t*/
\tparameter[3 : 0] window_width = 3;
\t/*
\t::description
\tClock.
\t*/
\tinput clk;
\t/*
\t::description
\tReset, active low.
\t*/
\tinput rst_n;
\t/*
\t::description
\tReset, active low.
\t*/
\tinput[window_width * window_width - 1 : 0] template;
\t/*
\t::description
\tInput data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
\t*/
\tinput in_enable;
\t/*
\t::description
\tInput data, it must be synchronous with in_enable.
\t*/
\tinput [window_width * window_width - 1 : 0] in_data;
\t/*
\t::description
\tOutput data ready, in both two mode, it will be high while the out_data can be read.
\t*/
\toutput out_ready;
\t/*
\t::description
\tOutput data, it will be synchronous with out_ready.
\t*/
\toutput out_data;
\treg reg_out_data;
\treg reg_out_ready;
\tgenerate
\t\talways @(posedge clk or negedge rst_n or negedge in_enable) begin
\t\t\tif(~rst_n || ~in_enable) begin
\t\t\t\treg_out_ready <= 0;
\t\t\tend else begin
\t\t\t\treg_out_ready <= 1;
\t\t\tend
\t\tend
\t\tassign out_ready = reg_out_ready;
\t\tif(work_mode == 0) begin
\t\t\talways @(posedge clk)
\t\t\t\treg_out_data <= in_data == template ? 1 : 0;
\t\tend else begin
\t\t\talways @(posedge in_enable)
\t\t\t\treg_out_data <= in_data == template ? 1 : 0;
\t\tend
\t\tassign out_data = out_ready ? reg_out_data : 0;
\tendgenerate
endmodule
|
/*
:Project
FPGA-Imaging-Library
:Design
True2Comp
:Function
Convert true code to complemental code.
:Module
Main module
:Version
1.0
:Modified
2015-05-01
Copyright (C) 2015 Dai Tianyu (dtysky)
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
\thttp://ifl.dtysky.moe
Sources for this project:
\thttps://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
\[email protected]
My blog:
\thttp://dtysky.moe
*/
`timescale 1ns / 1ps
module True2Comp(
\ttrue,
\tcomplement);
\tparameter data_channel = 1;
\tparameter data_width = 17;
\tinput[data_channel * data_width - 1 : 0] true;
\toutput[data_channel * data_width - 1 : 0] complement;
\tgenvar i;
\tgenerate
\t\t`define h (i + 1) * data_width - 1
\t\t`define l i * data_width
\t\tfor (i = 0; i < data_channel; i = i + 1) begin
\t\t\tassign complement[`h : `l] = true[`h] == 0 ?
\t\t\t\ttrue[`h : `l] : {1'b1, ~true[`h - 1 : `l] + 1};
\t\tend
\t\t`undef h
\t\t`undef l
\tendgenerate
endmodule
|
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