text
stringlengths 1
2.1M
|
|---|
`timescale 1ns / 1ps
module tb();
reg clk, rst, is_alu, is_ls;
abiter abiter(
\t.rst(rst),
\t.clk(clk),
\t.is_alu(is_alu),
\t.is_ls(is_ls),
\t.sel_result(sel_result),
\t.stall_alu(stall_alu),
\t.stall_ls(stall_ls)
\t);
\t
\tinitial begin
\t\tclk <= 1\'b1;
\t\tforever #5 clk <= ~clk;
\tend
\tinitial begin
\t\tis_alu <= 1\'b0;
\t\tforever #20 is_alu <= ~is_alu;
\tend
\tinitial begin
\t\tis_ls <= 1\'b0;
\t\tforever #60 is_ls <= ~is_ls;
\tend
\tinitial begin
\t\t#0 rst <= 1\'b1;
\t\t#20 rst <= 1\'b0;
\t\t#150 $finish;
\tend
\tinitial begin
\t$dumpfile("z_dump.vcd");
\t$dumpvars(0,tb);
\tend
endmodule
|
//Data memory model\r
//Has one read and one write port\r
//Reads and writes are carried out on posedge clk\r
\r
module data_mem(clk, en, we, wdata, addr, rdata);\r
\r
\tinput clk;\r
\tinput en; \r
\tinput we;\r
\r
\tinput [13:0] addr;\r
\tinput [31:0] wdata;\r
\t\r
\toutput reg [31:0] rdata;\r
\r
\treg [31:0] mem [16383:0];\r
\r
\talways@(posedge clk) begin\r
\t\tif(en)\r
\t\t\trdata <= mem[addr];\r
\t\telse\r
\t\t\trdata <= 32\'hxxxxxxxx;\r
\tend\r
\r
\talways@(posedge clk) begin\r
\t\tif(we)\r
\t\t\tmem[addr] <= wdata;\r
\tend\r
\r
\tinitial begin\r
\t\t$readmemh("../test/BinayData", mem);\r
\tend\r
\r
endmodule\r
|
////////////////////////////////////////////////////////////////////////////////\r
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.\r
////////////////////////////////////////////////////////////////////////////////\r
// ____ ____ \r
// / /\\/ / \r
// /___/ \\ / Vendor: Xilinx \r
// \\ \\ \\/ Version : 14.7\r
// \\ \\ Application : xaw2verilog\r
// / / Filename : clk_mult.v\r
// /___/ /\\ Timestamp : 11/05/2015 17:51:11\r
// \\ \\ / \\ \r
// \\___\\/\\___\\ \r
//\r
//Command: xaw2verilog -intstyle I:/ECE554/554Project/regfiletest/regfiletest/ipcore_dir/clk_mult.xaw -st clk_mult.v\r
//Design Name: clk_mult\r
//Device: xc5vlx110t-1ff1136\r
//\r
// Module clk_mult\r
// Generated by Xilinx Architecture Wizard\r
// Written for synthesis tool: XST\r
`timescale 1ns / 1ps\r
\r
module clk_mult(CLKIN_IN, \r
RST_IN, \r
CLKIN_IBUFG_OUT, \r
CLK0_OUT, \r
CLK2X_OUT, \r
LOCKED_OUT);\r
\r
input CLKIN_IN;\r
input RST_IN;\r
output CLKIN_IBUFG_OUT;\r
output CLK0_OUT;\r
output CLK2X_OUT;\r
output LOCKED_OUT;\r
\r
wire CLKFB_IN;\r
wire CLKIN_IBUFG;\r
wire CLK0_BUF;\r
wire CLK2X_BUF;\r
wire GND_BIT;\r
wire [6:0] GND_BUS_7;\r
wire [15:0] GND_BUS_16;\r
\r
assign GND_BIT = 0;\r
assign GND_BUS_7 = 7\'b0000000;\r
assign GND_BUS_16 = 16\'b0000000000000000;\r
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;\r
assign CLK0_OUT = CLKFB_IN;\r
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN), \r
.O(CLKIN_IBUFG));\r
BUFG CLK0_BUFG_INST (.I(CLK0_BUF), \r
.O(CLKFB_IN));\r
BUFG CLK2X_BUFG_INST (.I(CLK2X_BUF), \r
.O(CLK2X_OUT));\r
DCM_ADV #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(1), \r
.CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("FALSE"), \r
.CLKIN_PERIOD(10.000), .CLKOUT_PHASE_SHIFT("NONE"), \r
.DCM_AUTOCALIBRATION("TRUE"), .DCM_PERFORMANCE_MODE("MAX_SPEED"), \r
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"), \r
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"), \r
.FACTORY_JF(16\'hF0F0), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE"), \r
.SIM_DEVICE("VIRTEX5") ) DCM_ADV_INST (.CLKFB(CLKFB_IN), \r
.CLKIN(CLKIN_IBUFG), \r
.DADDR(GND_BUS_7[6:0]), \r
.DCLK(GND_BIT), \r
.DEN(GND_BIT), \r
.DI(GND_BUS_16[15:0]), \r
.DWE(GND_BIT), \r
.PSCLK(GND_BIT), \r
.PSEN(GND_BIT), \r
.PSINCDEC(GND_BIT), \r
.RST(RST_IN), \r
.CLKDV(), \r
.CLKFX(), \r
.CLKFX180(), \r
.CLK0(CLK0_BUF), \r
.CLK2X(CLK2X_BUF), \r
.CLK2X180(), \r
.CLK90(), \r
.CLK180(), \r
.CLK270(), \r
.DO(), \r
.DRDY(), \r
.LOCKED(LOCKED_OUT), \r
.PSDONE());\r
endmodule\r
|
module rs_alu(
\tinput clk,
\tinput rst,
\t//To IS/EX pipe
\toutput [31:0] PC_out,
\toutput [3:0] rob_id_out,\t
\toutput [16:0] EX_ctrl_out, //To IS/EX pipe
\toutput [5:0] p_rs_out, //To PRF: Read Operand 1
\toutput [5:0] p_rt_out, //To PRF: Read Operand 2
\toutput [15:0] imm_bits_out,
\toutput [5:0] p_rd_out,\t//To ALU: ALU must store it and use it as CDB.Tag \t
\toutput stl_dec_rs_alu_full, //To Decode
\t
\tinput [3:0] num_rob_entry, //From Decode stage: ROB tail
\tinput [31:0] PC_in,
\tinput [16:0] EX_ctrl_in, //From Decode
\t//input ALU_busy,\t//From EX(ALU)
\tinput [5:0] p_rs_in, \t//From Map Table\t
\tinput [5:0] p_rt_in, \t//From Map Table
\tinput p_rs_rdy_in,\t//From Map Table, PRF Valid array
\tinput p_rt_rdy_in,\t//From Map Table, PRF Valid array
\tinput rs_read,
\tinput rt_read,
\tinput [15:0] imm_bits_in,
\tinput [5:0] p_rd_new, \t//From Free List
\tinput alloc_RS_en, \t//From Decode: rs_alu_en
\tinput stall_issue,\t//From EX stage
\toutput wire issue_en,\t//Indicates if an instruction is issued in a clock cycle
\tinput recover,\t\t\t
\tinput [3:0] rec_rob_entry, //ROB# for instructions to be flushed
\tinput stall_hazard,
\t//CDB interface
\tinput bus_en,
\tinput [5:0] tag\t\t//From CDB
\t//input [3:0] cdb_rob_id, //From CDB
\t//input [31:0] value, \t//From CDB
\t
);
\tinteger i; //Index of all the for-loops
\t//Allocation
\treg [3:0] alloc_index; //Points to the first available entry of RS from the index[0]
\twire [2:0] alloc_index_3b;
\t//Issue
\treg [2:0] issue_index; reg [2:0] flush_index;
\t//Flip-flop arrays
\treg valid[0:8];
\treg [3:0] rob_id[0:8]; //ROB entry number
\treg [5:0] prf_rs[0:8]; //6-bit PRF addresses
\treg [5:0] prf_rt[0:8]; //6-bit PRF addresses
\treg [5:0] prf_rd[0:8]; //6-bit PRF addresses\t
\treg [15:0] imm_bits[0:8]; //immediate bits
\treg [16:0] ex_ctrl[0:8]; \t
\treg [31:0] PC[0:8]; //Program Counter\t
\treg prf_rs_rdy[0:8]; //Ready bit: prf_rs
\treg prf_rt_rdy[0:8]; //Ready bit: prf_rt
\t//Allocation Index calculation
\talways@( posedge clk or negedge rst) begin
\t\tif( ~rst) begin
\t\t\talloc_index <= 4'd0;
\t\tend else begin
\t\t\tif( alloc_index[3] == 1'b1 || stall_hazard == 1'b1)
\t\t\t\talloc_index <= alloc_index;
\t\t\telse begin
\t\t\t\tif( recover==1'b1)
\t\t\t\t\talloc_index <= alloc_index - 1;
\t\t\t\telse begin
\t\t\t\tcase( {alloc_RS_en, issue_en})
\t\t\t\t2'b00: alloc_index <= alloc_index;
\t\t\t\t2'b01: alloc_index <= alloc_index - 1;
\t\t\t\t2'b10: alloc_index <= alloc_index + 1;
\t\t\t\t2'b11: alloc_index <= alloc_index;\t
\t\t\t\tendcase
\t\t\t\tend
\t\t\tend
\t\tend
\tend
\tassign alloc_index_3b = alloc_index[2:0];
\t//Flush Index calculation
\talways@( recover) begin
\tif( recover == 1'b1) begin
\t\tif( valid[0] == 1'b1 && rec_rob_entry == rob_id[0]) flush_index = 3'b000;
\t\telse if( valid[1] == 1'b1 && rec_rob_entry == rob_id[1]) flush_index = 3'b001;
\t\telse if( valid[2] == 1'b1 && rec_rob_entry == rob_id[2]) flush_index = 3'b010;
\t\telse if( valid[3] == 1'b1 && rec_rob_entry == rob_id[3]) flush_index = 3'b011;
\t\telse if( valid[4] == 1'b1 && rec_rob_entry == rob_id[4]) flush_index = 3'b100;
\t\telse if( valid[5] == 1'b1 && rec_rob_entry == rob_id[5]) flush_index = 3'b101;
\t\telse if( valid[6] == 1'b1 && rec_rob_entry == rob_id[6]) flush_index = 3'b110;
\t\telse if( valid[7] == 1'b1 && rec_rob_entry == rob_id[7]) flush_index = 3'b111;
\t\telse flush_index = 3'b000;
\tend else flush_index = 3'b000;
\tend
////////////////////
// Valid
////////////////////
\talways@( posedge clk or negedge rst) begin
\t\t\tvalid[8] <= 1'b0;
\t\t\t
\t \tfor( i=0; i<8; i=i+1) begin\t\t
\t\t if( ~rst) begin
\t\t\tvalid[i] <= 1'b0;
\t\t end else begin\t
\t\t\tif( recover == 1'b1) begin
\t\t\t\tif( i==flush_index || i>flush_index) begin\t\t\t\t\t
\t\t\t\t\tif( i < alloc_index-1 ) valid[i] <= valid[i+1];
\t\t\t\t\telse valid[i] <= 1'b0;
\t\t\t\tend else valid[i] <= valid[i];
\t\t\tend \t
\t\t\telse if( ((i == issue_index || i > issue_index) && i < alloc_index) && issue_en == 1'b1) begin
\t\t\t\tif( i == alloc_index-1 || i==7) begin//Last entry of the Array
\t\t\t\t\tif( alloc_RS_en) valid[i] <= 1'b1;
\t\t\t\t\telse valid[i] <= 1'b0;
\t\t\t\tend else
\t\t\t\t\tvalid[i] <= valid[i+1];
\t\t\tend else if( i == alloc_index_3b && alloc_index[3] == 1'b0 && alloc_RS_en == 1'b1 && issue_en == 1'b0)
\t\t\t\tvalid[i] <= 1'b1;
\t\t\telse
\t\t\t\tvalid[i] <= valid[i];
\t\t end
\t \tend //for
\tend //always\t
///////////////////////
// ROB#
///////////////////////
\talways@( posedge clk or negedge rst) begin
\t\t\trob_id[8] <= 4'd0;
\t
\t \tfor( i=0; i<8; i=i+1) begin\t\t
\t\t if( ~rst) begin
\t\t\trob_id[i] <= 4'd0;
\t\t end else begin\t
\t\t\tif( recover == 1'b1) begin
\t\t\t\tif( i == flush_index || i>flush_index) begin
\t\t\t\t\tif( i < alloc_index-1) rob_id[i] <= rob_id[i+1];
\t\t\t\t\telse rob_id[i] <= 4'd0;
\t\t\t\tend else rob_id[i] <= rob_id[i];
\t\t\tend \t
\t\t\telse if( ((i == issue_index || i > issue_index) && i < alloc_index) && issue_en == 1'b1) begin
\t\t\t\tif( i == alloc_index-1 || i==7) //Last entry of the Array
\t\t\t\t\tif( alloc_RS_en) rob_id[i] <= num_rob_entry; //value;
\t\t\t\t\telse rob_id[i] <= 4'd0;
\t\t\t\telse
\t\t\t\t\trob_id[i] <= rob_id[i+1];
\t\t\tend else if( i == alloc_index_3b && alloc_index[3] == 1'b0 && alloc_RS_en == 1'b1 && issue_en == 1'b0)
\t\t\t\trob_id[i] <= num_rob_entry; //value;
\t\t\telse
\t\t\t\trob_id[i] <= rob_id[i];
\t\t end
\t \tend //for
\tend //always\t
///////////////////////
// PRF_RS
///////////////////////
\talways@( posedge clk or negedge rst) begin
\t\t\tprf_rs[8] <= 6'd00; //The 9th and unused
\t\t\t
\t \tfor( i=0; i<8; i=i+1) begin\t\t
\t\t if( ~rst) begin
\t\t\tprf_rs[i] <= 6'd0;
\t\t end else begin\t
\t\t\tif( recover == 1'b1) begin
\t\t\t\tif( i == flush_index || i>flush_index) begin
\t\t\t\t\tif( i < alloc_index-1) prf_rs[i] <= prf_rs[i+1];
\t\t\t\t\telse prf_rs[i] <= 6'd0;
\t\t\t\tend else prf_rs[i] <= prf_rs[i];
\t\t\tend \t
\t\t\telse if( ((i == issue_index || i > issue_index) && i < alloc_index) && issue_en == 1'b1) begin
\t\t\t\tif( i == alloc_index-1 || i==7) //Last entry of the Array
\t\t\t\t\tif( alloc_RS_en) prf_rs[i] <= p_rs_in; //value;
\t\t\t\t\telse prf_rs[i] <= 6'd0;
\t\t\t\telse
\t\t\t\t\tprf_rs[i] <= prf_rs[i+1];
\t\t\tend else if( i == alloc_index_3b && alloc_index[3] == 1'b0 && alloc_RS_en == 1'b1 && issue_en == 1'b0)
\t\t\t\tprf_rs[i] <= p_rs_in; //value;
\t\t\telse
\t\t\t\tprf_rs[i] <= prf_rs[i];
\t\t end
\t \tend //for
\tend //always\t
///////////////////////
// PRF_RT
///////////////////////
\talways@( posedge clk or negedge rst) begin
\t\t\tprf_rt[8] <= 6'd00; //The 9th and unused \t
\t
\t \tfor( i=0; i<8; i=i+1) begin\t\t
\t\t if( ~rst) begin
\t\t\tprf_rt[i] <= 6'd0;
\t\t end else begin\t
\t\t\tif( recover == 1'b1) begin
\t\t\t\tif( i == flush_index || i>flush_index) begin
\t\t\t\t\tif( i < alloc_index-1) prf_rt[i] <= prf_rt[i+1];
\t\t\t\t\telse prf_rt[i] <= 6'd0;
\t\t\t\tend else prf_rt[i] <= prf_rt[i];
\t\t\tend \t
\t\t\telse if( ((i == issue_index || i > issue_index) && i < alloc_index) && issue_en == 1'b1) begin
\t\t\t\tif( i == alloc_index-1 || i==7) //Last entry of the Array
\t\t\t\t\tif( alloc_RS_en) prf_rt[i] <= p_rt_in; //value;
\t\t\t\t\telse prf_rt[i] <= 6'd0;
\t\t\t\telse
\t\t\t\t\tprf_rt[i] <= prf_rt[i+1];
\t\t\tend else if( i == alloc_index_3b && alloc_index[3] == 1'b0 && alloc_RS_en == 1'b1 && issue_en == 1'b0)
\t\t\t\tprf_rt[i] <= p_rt_in; //value;
\t\t\telse
\t\t\t\tprf_rt[i] <= prf_rt[i];
\t\t end
\t \tend //for
\tend //always\t
///////////////////////
// PRF_RD
///////////////////////
\talways@( posedge clk or negedge rst) begin
\t\t\tprf_rd[8] <= 6'd00; //The 9th and unused\t
\t
\t \tfor( i=0; i<8; i=i+1) begin\t\t
\t\t if( ~rst) begin
\t\t\tprf_rd[i] <= 4'd0;
\t\t end else begin\t
\t\t\tif( recover == 1'b1) begin
\t\t\t\tif( i == flush_index || i>flush_index) begin
\t\t\t\t\tif( i < alloc_index-1) prf_rd[i] <= prf_rd[i+1];
\t\t\t\t\telse prf_rd[i] <= 4'd0;
\t\t\t\tend else prf_rd[i] <= prf_rd[i];
\t\t\tend \t
\t\t\telse if( ((i == issue_index || i > issue_index) && i < alloc_index) && issue_en == 1'b1) begin
\t\t\t\tif( i == alloc_index-1 || i==7) //Last entry of the Array
\t\t\t\t\tif( alloc_RS_en) prf_rd[i] <= p_rd_new;
\t\t\t\t\telse prf_rd[i] <= 4'd0;
\t\t\t\telse
\t\t\t\t\tprf_rd[i] <= prf_rd[i+1];
\t\t\tend else if( i == alloc_index_3b && alloc_index[3] == 1'b0 && alloc_RS_en == 1'b1 && issue_en == 1'b0)
\t\t\t\tprf_rd[i] <= p_rd_new;
\t\t\telse
\t\t\t\tprf_rd[i] <= prf_rd[i];
\t\t end
\t \tend //for
\tend //always\t\t
///////////////////////
// IMMEDIATE BITS
///////////////////////
\talways@( posedge clk or negedge rst) begin
\t\t\timm_bits[8] <= 6'd00; //The 9th and unused\t
\t
\t \tfor( i=0; i<8; i=i+1) begin\t\t
\t\t if( ~rst) begin
\t\t\timm_bits[i] <= 4'd0;
\t\t end else begin\t
\t\t\tif( recover == 1'b1) begin
\t\t\t\tif( i == flush_index || i>flush_index) begin
\t\t\t\t\tif( i < alloc_index-1) imm_bits[i] <= imm_bits[i+1];
\t\t\t\t\telse imm_bits[i] <= 4'd0;
\t\t\t\tend else imm_bits[i] <= imm_bits[i];
\t\t\tend \t
\t\t\telse if( ((i == issue_index || i > issue_index) && i < alloc_index) && issue_en == 1'b1) begin
\t\t\t\tif( i == alloc_index-1 || i==7) //Last entry of the Array
\t\t\t\t\tif( alloc_RS_en) imm_bits[i] <= imm_bits_in;
\t\t\t\t\telse imm_bits[i] <= 4'd0;
\t\t\t\telse
\t\t\t\t\timm_bits[i] <= imm_bits[i+1];
\t\t\tend else if( i == alloc_index_3b && alloc_index[3] == 1'b0 && alloc_RS_en == 1'b1 && issue_en == 1'b0)
\t\t\t\timm_bits[i] <= imm_bits_in;
\t\t\telse
\t\t\t\timm_bits[i] <= imm_bits[i];
\t\t end
\t \tend //for
\tend //always\t
///////////////////////
// EX CTRL BITS
///////////////////////
\talways@( posedge clk or negedge rst) begin
\t\t\tex_ctrl[8] <= 17'd0; //9th and unused
\t
\t \tfor( i=0; i<8; i=i+1) begin\t\t
\t\t if( ~rst) begin
\t\t\tex_ctrl[i] <= 17'd0;
\t\t end else begin\t
\t\t\tif( recover == 1'b1) begin
\t\t\t\tif( i == flush_index || i>flush_index) begin
\t\t\t\t\tif( i < alloc_index-1) ex_ctrl[i] <= ex_ctrl[i+1];
\t\t\t\t\telse ex_ctrl[i] <= 17'd0;
\t\t\t\tend else ex_ctrl[i] <= ex_ctrl[i];
\t\t\tend \t
\t\t\telse if( ((i == issue_index || i > issue_index) && i < alloc_index) && issue_en == 1'b1) begin
\t\t\t\tif( i == alloc_index-1 || i==7) //Last entry of the Array
\t\t\t\t\tif( alloc_RS_en) ex_ctrl[i] <= EX_ctrl_in;
\t\t\t\t\telse ex_ctrl[i] <= 17'd0;
\t\t\t\telse
\t\t\t\t\tex_ctrl[i] <= ex_ctrl[i+1];
\t\t\tend else if( i == alloc_index_3b && alloc_index[3] == 1'b0 && alloc_RS_en == 1'b1 && issue_en == 1'b0)
\t\t\t\tex_ctrl[i] <= EX_ctrl_in;
\t\t\telse
\t\t\t\tex_ctrl[i] <= ex_ctrl[i];
\t\t end
\t \tend //for
\tend //always\t
///////////////////////
// Program Counter
///////////////////////
\talways@( posedge clk or negedge rst) begin
\t\t\tPC[8] <= 32'd0; //9th and unused
\t\t\t
\t \tfor( i=0; i<8; i=i+1) begin\t\t
\t\t if( ~rst) begin
\t\t\tPC[i] <= 32'd0;
\t\t end else begin\t
\t\t\tif( recover == 1'b1) begin
\t\t\t\tif( i == flush_index || i>flush_index) begin
\t\t\t\t\tif( i < alloc_index-1) PC[i] <= PC[i+1];
\t\t\t\t\telse PC[i] <= 32'd0;
\t\t\t\tend else PC[i] <= PC[i];
\t\t\tend \t
\t\t\telse if( ((i == issue_index || i > issue_index) && i < alloc_index) && issue_en == 1'b1) begin
\t\t\t\tif( i == alloc_index-1 || i==7) //Last entry of the Array
\t\t\t\t\tif( alloc_RS_en) PC[i] <= PC_in;
\t\t\t\t\telse PC[i] <= 32'd0;
\t\t\t\telse
\t\t\t\t\tPC[i] <= PC[i+1];
\t\t\tend else if( i == alloc_index_3b && alloc_index[3] == 1'b0 && alloc_RS_en == 1'b1 && issue_en == 1'b0)
\t\t\t\tPC[i] <= PC_in;
\t\t\telse
\t\t\t\tPC[i] <= PC[i];
\t\t end
\t \tend //for
\tend //always\t
///////////////////////
// PRF RS READY BIT
///////////////////////
\t//Ready bit arrays: prf_rs_rdy[]
\t//Allocation: Dispatch
\t//Issue and Deallocation: Issue
\t//CDB Tag match: Complete
\talways@( posedge clk or negedge rst) begin
\t\t\tprf_rs_rdy[8] <= 1'b0; //The 9th and un-used flip-flop\t
\t
\t \tfor( i=0; i<8; i=i+1) begin\t\t
\t\t if( ~rst)
\t\t\tprf_rs_rdy[i] <= 1'b0;\t
\t\t else begin
\t\t\tif( recover == 1'b1) begin
\t\t\t\tif( i == flush_index || i>flush_index) begin
\t\t\t\t\tif( i < alloc_index-1) prf_rs_rdy[i] <= prf_rs_rdy[i+1];
\t\t\t\t\telse prf_rs_rdy[i] <= 1'b0;
\t\t\t\tend else prf_rs_rdy[i] <= prf_rs_rdy[i];
\t\t\tend
\t\t\telse if( issue_en == 1'b1) begin\t
\t\t\t if( i >= issue_index && i < alloc_index) begin
\t\t\t\tif( bus_en==1'b1) begin
\t\t\t\t\tif( i != alloc_index-1) begin
\t\t\t\t\t\tif( tag == prf_rs[i+1]) prf_rs_rdy[i] <= 1'b1; //CDB Tag Match
\t\t\t\t\t\telse prf_rs_rdy[i] <= prf_rs_rdy[i+1]; //Shifting up\t\t
\t\t\t\t\tend else begin
\t\t\t\t\t\tif( alloc_RS_en==1'b1) begin
\t\t\t\t\t\t\tif( tag == p_rs_in) prf_rs_rdy[i] <= 1'b1; //Forwarding
\t\t\t\t\t\t\telse prf_rs_rdy[i] <= p_rs_rdy_in | (~rs_read);
\t\t\t\t\t\tend else\t
\t\t\t\t\t\t\tprf_rs_rdy[i] <= 1'b0;
\t\t\t\t\tend
\t\t\t\tend else begin
\t\t\t\t\tif( i != alloc_index-1)
\t\t\t\t\t\tprf_rs_rdy[i] <= prf_rs_rdy[i+1]; //Shifting up\t\t
\t\t\t\t\telse begin
\t\t\t\t\t\tif( alloc_RS_en==1'b1) prf_rs_rdy[i] <= p_rs_rdy_in | (~rs_read); //Allocation
\t\t\t\t\t\telse prf_rs_rdy[i] <= 1'b0;
\t\t\t\t\tend
\t\t\t\tend
\t\t\t end else if( i < issue_index) begin
\t\t\t\t//if(i==alloc_index-1 && alloc_RS_en==1'b1) prf_rs_rdy[i] <= //Not possible: alloc_index IS ALWAYS GREATER THAN issue_index
\t\t\t\tif(bus_en==1'b1 && tag == prf_rs[i]) prf_rs_rdy[i] <= 1'b1;
\t\t\t\telse prf_rs_rdy[i] <= prf_rs_rdy[i]; \t\t\t\t\t\t\t\t
\t\t\t end else begin
\t\t\t\tprf_rs_rdy[i] <= prf_rs_rdy[i]; \t\t
\t\t\t end \t
\t\t\tend else begin //issue_en = 0
\t\t\t\tif( bus_en==1'b1) begin
\t\t\t\t\tif( i < alloc_index)
\t\t\t\t\t\tif( tag == prf_rs[i]) prf_rs_rdy[i] <= 1'b1; //CDB Tag match
\t\t\t\t\t\telse prf_rs_rdy[i] <= prf_rs_rdy[i];
\t\t\t\t\telse if( i==alloc_index && alloc_RS_en == 1'b1)
\t\t\t\t\t\tif( tag == p_rs_in) prf_rs_rdy[i] <= 1'b1;
\t\t\t\t\t\telse prf_rs_rdy[i] <= p_rs_rdy_in | (~rs_read); //Allocation
\t\t\t\t\telse //(i>alloc_index)
\t\t\t\t\t\tprf_rs_rdy[i] <= prf_rs_rdy[i];\t//Do nothing\t\t
\t\t\t\tend else begin
\t\t\t\t\tif( i==alloc_index && alloc_RS_en == 1'b1)
\t\t\t\t\t\tprf_rs_rdy[i] <= p_rs_rdy_in | (~rs_read); //Allocation
\t\t\t\t\telse
\t\t\t\t\t\tprf_rs_rdy[i] <= prf_rs_rdy[i];\t//Do nothing\t\t\t\t\t\t\t
\t\t\t\tend
\t\t\tend
\t\t end
\t\tend
\tend
///////////////////////
// PRF RT READY BIT
///////////////////////
\t//Ready bit arrays: prf_rt_rdy[]
\t//Allocation: Dispatch
\t//Issue and Deallocation: Issue
\t//CDB Tag match: Complete
\talways@( posedge clk or negedge rst) begin
\t\t\tprf_rt_rdy[8] <= 1'b0; //The 9th and un-used flip-flop
\t\t
\t \tfor( i=0; i<8; i=i+1) begin\t\t
\t\t if( ~rst)
\t\t\tprf_rt_rdy[i] <= 1'b0;\t
\t\t else begin
\t\t\tif( recover == 1'b1) begin
\t\t\t\tif( i == flush_index || i>flush_index) begin
\t\t\t\t\tif( i < alloc_index-1) prf_rt_rdy[i] <= prf_rt_rdy[i+1];
\t\t\t\t\telse prf_rt_rdy[i] <= 1'b0;
\t\t\t\tend else prf_rt_rdy[i] <= prf_rt_rdy[i];
\t\t\tend
\t\t\telse if( issue_en == 1'b1) begin\t
\t\t\t if( i >= issue_index && i < alloc_index) begin
\t\t\t\tif( bus_en==1'b1) begin
\t\t\t\t\tif( i != alloc_index-1) begin
\t\t\t\t\t\tif( tag == prf_rt[i+1]) prf_rt_rdy[i] <= 1'b1; //CDB Tag Match
\t\t\t\t\t\telse prf_rt_rdy[i] <= prf_rt_rdy[i+1]; //Shifting up\t\t
\t\t\t\t\tend else begin
\t\t\t\t\t\tif( alloc_RS_en==1'b1) begin
\t\t\t\t\t\t\tif( tag == p_rt_in) prf_rt_rdy[i] <= 1'b1; //Forwarding
\t\t\t\t\t\t\telse prf_rt_rdy[i] <= p_rt_rdy_in | (~rt_read);
\t\t\t\t\t\tend else\t
\t\t\t\t\t\t\tprf_rt_rdy[i] <= 1'b0;
\t\t\t\t\tend
\t\t\t\tend else begin
\t\t\t\t\tif( i != alloc_index-1)
\t\t\t\t\t\tprf_rt_rdy[i] <= prf_rt_rdy[i+1]; //Shifting up\t\t
\t\t\t\t\telse begin
\t\t\t\t\t\tif( alloc_RS_en==1'b1) prf_rt_rdy[i] <= p_rt_rdy_in | (~rt_read); //Allocation
\t\t\t\t\t\telse prf_rt_rdy[i] <= 1'b0;
\t\t\t\t\tend
\t\t\t\tend
\t\t\t end else if( i < issue_index) begin
\t\t\t\t//if(i==alloc_index-1 && alloc_RS_en==1'b1) prf_rt_rdy[i] <= //Not possible: alloc_index IS ALWAYS GREATER THAN issue_index
\t\t\t\tif(bus_en==1'b1 && tag == prf_rt[i]) prf_rt_rdy[i] <= 1'b1;
\t\t\t\telse prf_rt_rdy[i] <= prf_rt_rdy[i]; \t\t\t\t\t\t\t\t
\t\t\t end else begin
\t\t\t\tprf_rt_rdy[i] <= prf_rt_rdy[i]; \t\t
\t\t\t end \t
\t\t\tend else begin //issue_en = 0
\t\t\t\tif( bus_en==1'b1) begin
\t\t\t\t\tif( i < alloc_index)
\t\t\t\t\t\tif( tag == prf_rt[i]) prf_rt_rdy[i] <= 1'b1; //CDB Tag match
\t\t\t\t\t\telse prf_rt_rdy[i] <= prf_rt_rdy[i];
\t\t\t\t\telse if( i==alloc_index && alloc_RS_en == 1'b1)
\t\t\t\t\t\tif( tag == p_rt_in) prf_rt_rdy[i] <= 1'b1;
\t\t\t\t\t\telse prf_rt_rdy[i] <= p_rt_rdy_in | (~rt_read); //Allocation
\t\t\t\t\telse //(i>alloc_index)
\t\t\t\t\t\tprf_rt_rdy[i] <= prf_rt_rdy[i];\t//Do nothing\t\t
\t\t\t\tend else begin
\t\t\t\t\tif( i==alloc_index && alloc_RS_en == 1'b1)
\t\t\t\t\t\tprf_rt_rdy[i] <= p_rt_rdy_in | (~rt_read); //Allocation
\t\t\t\t\telse
\t\t\t\t\t\tprf_rt_rdy[i] <= prf_rt_rdy[i];\t//Do nothing\t\t\t\t\t\t\t
\t\t\t\tend
\t\t\tend
\t\t end
\t\tend
\tend
\t//Enable/Disable Issue
\treg inst_rdy[0:7]; //Indicates if the source operands are ready\t
\twire is_inst_rdy;
\tgenvar k;
\tgenerate for( k=0; k<8; k=k+1) begin : inst_rdy_block
\t\talways@( valid[k], prf_rs_rdy[k], prf_rt_rdy[k]) begin
\t\t\tinst_rdy[k] = valid[k] & prf_rs_rdy[k] & prf_rt_rdy[k];
\t\tend
\tend
\tendgenerate
\tassign is_inst_rdy = inst_rdy[0] | inst_rdy[1] | inst_rdy[2] | inst_rdy[3] | inst_rdy[4] | inst_rdy[5] | inst_rdy[6] | inst_rdy[7] ;
\tassign issue_en = (recover | stall_hazard | stall_issue) ? (1'b0) : ( is_inst_rdy);
\t//Calculate Issue Index
\talways@( inst_rdy[0], inst_rdy[1], inst_rdy[2], inst_rdy[3], inst_rdy[4], inst_rdy[5], inst_rdy[6], inst_rdy[7]) begin
\t\tif( inst_rdy[0]) issue_index = 3'b000;
\t\telse if( inst_rdy[1]) issue_index = 3'b001;
\t\telse if( inst_rdy[2]) issue_index = 3'b010;
\t\telse if( inst_rdy[3]) issue_index = 3'b011;
\t\telse if( inst_rdy[4]) issue_index = 3'b100;
\t\telse if( inst_rdy[5]) issue_index = 3'b101;
\t\telse if( inst_rdy[6]) issue_index = 3'b110;
\t\telse if( inst_rdy[7]) issue_index = 3'b111;
\t\telse issue_index = 3'b000;
\tend
\t//Issue the Instruction/Drive the outputs of RS
\tassign p_rs_out = prf_rs[issue_index];
\tassign p_rt_out = prf_rt[issue_index];
\tassign p_rd_out = prf_rd[issue_index];
\tassign EX_ctrl_out = ex_ctrl[issue_index];
\tassign imm_bits_out = imm_bits[issue_index];
\tassign rob_id_out = rob_id[issue_index];
\tassign PC_out = PC[issue_index];\t
\tassign stl_dec_rs_alu_full = valid[0] & valid[1] & valid[2] & valid[3] & valid[4] & valid[5] & valid[6] & valid[7];
endmodule
|
/////////now have changed this to
module physical_register(
input [5:0] raddr0, raddr1,
input we,
input [5:0] waddr,
input [31:0] din,
input clk,
output reg [31:0] dout0,
output reg [31:0] dout1
);
reg [31:0] mem [0:63];
wire [31:0] dout0_int, dout1_int;
initial begin
$readmemh("prf_value.txt", mem);
end
always @(posedge clk) begin //the reset is not used
if (we)
mem[waddr] <= din;
//the IS/EX pipeline register
dout0 <= dout0_int;
dout1 <= dout1_int;
end
assign dout0_int = ((raddr0 == waddr) && we) ? din : mem[raddr0];
assign dout1_int = ((raddr1 == waddr) && we) ? din : mem[raddr1];
endmodule
|
module branch_gen(
output reg isBranch,
input [5:0] opcode,
input flag_z, flag_n, flag_v
);
localparam B = 6'b010011;
localparam BEQ = 6'b010100;
localparam BGT = 6'b010101;
localparam BGE = 6'b010110;
localparam BLE = 6'b010111;
localparam BLT = 6'b011000;
localparam BNE = 6'b011001;
always @(opcode or flag_n or flag_z or flag_v) begin
case (opcode)
B: isBranch = 1;
BEQ: isBranch = flag_z;
BGT: isBranch = (~flag_z) && (~flag_n); //greater than, not 0 or negative
BGE: isBranch = (~flag_n);
BLE: isBranch = flag_z | flag_n;
BLT: isBranch = flag_n;
BNE: isBranch = ~flag_z;
default: isBranch = 0;
endcase
end
endmodule
|
module IF_stage(
input clk, rst,
input changeFlow,
input [31:0] jb_addr,
input stall_PC,
input stall_IF_DP,
input flush_IF_DP,
output reg [31:0] instr_IF_DP,
output reg [31:0] pc_1_IF_DP
);
reg [31:0] pc;
wire [31:0] nxt_pc;
wire clk_n;
wire [31:0] pc_1;
wire [31:0] instr;
always @(posedge clk or negedge rst) begin
if (!rst)
pc <= 32'h00000000;
else if (!stall_PC)
pc <= nxt_pc;
end
assign pc_1 = pc + 1;
assign nxt_pc = changeFlow ? jb_addr : pc_1;
assign clk_n = ~clk;
inst_mem i_inst_mem(.clk(clk_n), .addr(pc[9:0]), .dout(instr));
always @(posedge clk or negedge rst) begin
if (!rst)
{instr_IF_DP, pc_1_IF_DP} <= {32'h00000000, 32'h00000000};
else if (flush_IF_DP)
instr_IF_DP <= 0; //flushing instr_IF_ID is enough
else if (!stall_IF_DP)
{instr_IF_DP, pc_1_IF_DP} <= {instr, pc_1};
end
endmodule
|
//issue stage: if the instruction is a store, store in the head
//execute: if the instruction is a load, check if there's store in the store queue that has address match, if yes forwarding
//store will complete in the same stage as the load and other instructions to make the ROB design easier
//if a load and a store in the same time, load goes first, head store goes in next cycle
//retire: set the store queue entry ready bit using ROB# to match
module store_queue(
input clk, rst,
input issue, mem_wen,
input mem_ren, //this is a load, don't release a store at this cycle, since d-mem is single port
input [31:0] rs_data, //used to calculating load/store address
input [31:0] rt_data, //data for store
//from the load-store station
input [15:0] immed,
input [3:0] rob_in,
input [5:0] p_rd_in,
input stall_hazard,
//from ROB, for retire stage, set the ready bit in
input retire_ST,
input [3:0] retire_rob,
input recover,
input [3:0] rec_rob,
output sq_full,
//////////////these five signals go to the arbiter,
output reg isLS,
output [31:0] load_result,
output reg [5:0] ls_p_rd,
output reg [3:0] ls_rob,
output reg ls_RegDest
//this signal is the write enable signal for store queue, it indicates the complete of the store instruction
);
///////////////***************************store queue logic********************************//////////////////////
reg [3:0] head, tail;
reg [1:0] head_addr;
reg [2:0] counter;
wire read, write;
wire head_retired;
//issue head store to data memory when the head is ready, and no load executed
assign read = !stall_hazard && !recover && head_retired && !mem_ren;
//get instruction from the reservation station if it is a store and it is issued
assign write = issue && mem_wen && !stall_hazard && !recover && !sq_full;
//counter recording full or empty status
always @(posedge clk or negedge rst) begin
if (!rst)
counter <= 3'b000;
else if (write && read)
counter <= counter;
else if (write)
counter <= counter + 1;
else if (read)
counter <= counter - 1;
end
assign sq_full = (counter == 3'b100);
//increase head when read, increase tail when write
always @(posedge clk or negedge rst) begin
if (!rst) begin
head <= 4'b0001;
head_addr <= 2'b00;
tail <= 4'b0001; \t\t
end
else begin
if (write) begin
tail <= {tail[2:0], tail[3]};
\t\tend
if (read) begin
head <= {head[2:0], head[3]};
head_addr <= head_addr + 1;
end\t\t\t
end
end
reg [31:0] value_queue [0:3];
reg [15:0] addr_queue [0:3];
reg [3:0] rob_queue [0:3];
reg [2:0] control_queue [0:3]; //[0]:valid, [1]:mem_wen [2]: ready
//reg [1:0] priority_queue [0:3]; //recoding priority, deciding which store is the youngest
////////////////////////memory address generator
wire [31:0] address_in;
assign address_in = rs_data + {{16{immed[15]}}, immed};
/////////////////combinational logic, comparators////////////////////////////
wire [3:0] rt_rob_match_array, rec_rob_match_array, addr_match_array;
genvar i;
generate for(i = 0; i < 4; i = i + 1) begin : combinational
//for retire stage, set the ready bit
assign rt_rob_match_array[i] = (rob_queue[i] == retire_rob) && retire_ST && control_queue[i][0] && control_queue[i][1];
//for recovery, flush the entry if rob number matches, and recover is high
assign rec_rob_match_array[i] = (rob_queue[i] == rec_rob) && recover && control_queue[i][0] && control_queue[i][1];
//for incoming load instruction, address match when valid, mem_ren is 1,
assign addr_match_array[i] = (addr_queue[i] == address_in[15:0]) && control_queue[i][0] && control_queue[i][1] && mem_ren;
end
endgenerate
////////////////////////sequential logic/////////////////////////////////////////
genvar j;
generate for (j = 0; j < 4; j = j + 1) begin : sequential
always @(posedge clk or negedge rst) begin
if (!rst) begin
value_queue[j] <= 0;
addr_queue[j] <= 0;
rob_queue[j] <= 0;
control_queue[j] <= 0;
end
else if (write && tail[j]) begin //this is the tail, match cannot happen on tail,
value_queue[j] <= rt_data;
addr_queue[j] <= address_in[15:0]; //the memory will only use 16 bit memory address
rob_queue[j] <= rob_in;
control_queue[j] <= {1'b0, mem_wen, 1'b1};
end else begin
if (rt_rob_match_array[j]) begin //set ready bit
control_queue[j][2] <= 1'b1;
end
if (rec_rob_match_array[j]) begin //flush this entry
control_queue[j][1] <= 1'b0; //only need to flush mem_wen, thus it cannot write to D-Mem, and cannot
end //match with incoming load, retired rob
if (read && head[j]) begin
control_queue[j][0] <= 1'b0; //set to invalid
end
end
end
end
endgenerate
assign head_retired = control_queue[head_addr][2] && control_queue[head_addr][0];
///////////////***************************end of store queue logic********************************//////////////////////
//////////////////////////////////////////data memory and load forwarding logic/////////////////////////
//////////////signals from store queue (load instruction will also use this address) to the memory
wire [31:0] store_data;
wire [15:0] mem_addr; //can be store addr or load addr
wire mem_wen_out;
wire mem_ren_out;
wire [31:0] load_data_from_mem;
wire [31:0] fwd_data_int;
wire isFwd;
assign store_data = value_queue[head_addr];
assign mem_addr = mem_ren_out ? address_in : addr_queue[head_addr];
assign mem_wen_out = (& control_queue[head_addr]) && !mem_ren;
assign mem_ren_out = mem_ren && issue;
////////////this may lead to errors if one stores to same address twice within 4 stores
assign fwd_data_int = addr_match_array[0] ? value_queue[0] :
addr_match_array[1] ? value_queue[1] :
addr_match_array[2] ? value_queue[2] :
addr_match_array[3] ? value_queue[3] : 32'h00000000;
assign isFwd = |addr_match_array; //if any of the entry matches, forwarding the data to load
/////////////////////////////data memory, data available at next clock edge////////////////////
data_mem i_data_mem(.clk(clk), .en(mem_ren_out), .we(mem_wen_out), .wdata(store_data), .addr(mem_addr[13:0]), .rdata(load_data_from_mem));
reg isFwd_reg;
reg [31:0] fwd_data_reg;
//////delay forwarding data by 1 cycle, because the load data from another path(memory) has 1 cycle delay
always @(posedge clk or negedge rst) begin
if (!rst) begin
fwd_data_reg <= 0;
isFwd_reg <= 0;
isLS <= 0;
ls_p_rd <= 0;
ls_rob <= 0;
ls_RegDest <= 0;
end
else begin
fwd_data_reg <= fwd_data_int;
isFwd_reg <= isFwd;
isLS <= mem_ren_out | write;
ls_p_rd <= p_rd_in;
ls_rob <= rob_in;
ls_RegDest <= mem_ren && issue;
end
end
assign load_result = isFwd_reg ? fwd_data_reg : load_data_from_mem;
endmodule
|
//Instruction memory model\r
//Initializes from file\r
//Read only\r
//Reads on posedge clk\r
\r
\r
module inst_mem(clk, addr, dout);\r
\r
\tinput clk;\r
\tinput [9:0] addr;\r
\toutput reg [31:0] dout;\r
\r
\treg [31:0] mem [1023:0];\r
\r
\t\r
\tinitial begin\r
\t\t$readmemh("../test/BinaryInst", mem);\r
//$readmemh("jb_test01_machine.txt", mem);\r
\tend\r
\t\r
\talways@(posedge clk) begin\r
\t\tdout <= mem[addr];\r
\tend \r
\r
\r
endmodule\r
|
//Two units: ALU, branch reslover, memory address generator in LSQ
//LSQ is kind of in parallel with this unit
module EX_stage_OoO(
//from performance counters
input [15:0] instr_cnt, cycle_cnt,
//from reservation station, data signals
input [31:0] rs_data, rt_data,
input [31:0] pc_1,
input [15:0] immed_value,
input [5:0] opcode,
//from reservation station, control signals
////*****writeRd: which is for write whether rd or rt, moved to ID/DP stage, before indexing Map Table
input ldic, isSignEx, immed,
input alu_ctrl0, alu_ctrl1, alu_ctrl2, alu_ctrl3,
input isJump, isJR,
input link,
output [31:0] alu_result, //to CDB arbiter
output changeFlow,
output [31:0] jb_addr //changeFlow and jb_addr, to complete stage, then to ROB
);
wire [31:0] alu_out;
wire flag_z, flag_n, flag_v;
wire [31:0] in0, in1;
wire [15:0] perf_cnt;
wire [4:0] shamt;
assign in0 = rs_data;
assign in1 = immed ? (isSignEx ? {{16{immed_value[15]}}, immed_value[15:0]} : {16'h0000, immed_value[15:0]}) : rt_data;
assign perf_cnt = ldic ? instr_cnt : cycle_cnt;
assign shamt = immed_value[10:6];
assign alu_result = link ? pc_1 : alu_out;
//ALU
ALU i_ALU(
.in0(in0),
.in1(in1),
.shamt(shamt),
.perf_cnt(perf_cnt),
.alu_ctrl0(alu_ctrl0),
.alu_ctrl1(alu_ctrl1),
.alu_ctrl2(alu_ctrl2),
.alu_ctrl3(alu_ctrl3),
.alu_out(alu_out),
.flag_z(flag_z),
.flag_v(flag_v),
.flag_n(flag_n));
wire isBranch; //if branch taken, set to 1
wire [31:0] branch_addr;
//branch resolver
branch_gen ibranch_gen(.isBranch(isBranch), .opcode(opcode), .flag_n(flag_n), .flag_z(flag_z), .flag_v(flag_v));
assign branch_addr = pc_1 + {{16{immed_value[15]}}, immed_value[15:0]};
assign changeFlow = isBranch | isJump; //first assume branch untaken
assign jb_addr = isBranch ? branch_addr : (isJR ? rs_data : {pc_1[31:16], immed_value});
endmodule
|
//64 registers, 32-bits each
module phy_reg_file (
\tinput clk,
\tinput rst,\t
\t//Read interface
\tinput [5:0] p_rs, //Read Address 1
\tinput [5:0] p_rt, //Read Address 2
\toutput reg [31:0] rd_data_rs, //Read Data out1
\toutput reg [31:0] rd_data_rt, //Read Data out2
\t//Write interface
\tinput [5:0] p_rd,\t\t\t //From CDB.Tag (complete stage)
\tinput [31:0] wr_data_in, //From CDB.Value (complete stage)
\tinput RegDest_compl //RegDest from complete stage, it is 1 if this instruction writes register
);
wire clk2x, clk_buf;
reg [5:0] clked_rs;
reg [5:0] clked_rt;
wire [31:0] rd_data_a, rd_data_b;
wire [5:0] addra, addrb;
wire we;
assign we = RegDest_compl&~clk_buf;\t\t// only write if clk is high (second 1/2 of clk cycle)
assign addra = we?p_rd:clked_rs;\t//if write enabled, addr change to rd
assign addrb = we?p_rd:clked_rt;
//read on second clk edge of 2x clk
always@(posedge clk2x, negedge rst) begin
\tif(!rst) begin
\t\tclked_rs <= 6'h0;
\t\tclked_rt <= 6'h0;
\tend else begin
\t\tclked_rs <= p_rs;
\t\tclked_rt <= p_rt;
\tend
end
//clk the mem read outputs, keep same on clk high (when writing)
always@(posedge clk_buf, negedge rst) begin
\tif(!rst) begin
\t\trd_data_rs <= 32'h0;
\t\trd_data_rt <= 32'h0;
\tend else begin
\t\trd_data_rs <= rd_data_a;
\t\trd_data_rt <= rd_data_b;
\tend
end
clk_mult cm(.CLKIN_IN(clk),
.RST_IN(rst),
.CLKIN_IBUFG_OUT(),
.CLK0_OUT(clk_buf),
.CLK2X_OUT(clk2x),
.LOCKED_OUT());
blockram br_prf(
.clka(clk2x),\t\t//clock A
.wea(we),\t\t//write enable A
.addra(addra),\t\t//addr A (first phase write, second phase read)
.dina(wr_data_in),\t\t//data in A
.douta(rd_data_a),\t\t//data out A
.clkb(clk2x),\t\t//clock B
.web(we),\t\t//write enable B
.addrb(addrb),\t\t//addr B (first phase write, second phase read)
.dinb(wr_data_in),\t\t//data in B
.doutb(rd_data_b)\t\t//data out B
);
//we also need register bypass. When read address equals to write address, output after next clock edge will be the value to be written instead
//of the value from block RAM entry.
endmodule
|
////////////////////////////////////////////////////////
////Author:
////Date:
////////////////////////////////////////////////////////
module decoder(
input [5:0] opcode,
output reg writeRd,
output reg RegDest,
output reg isDispatch,
output reg mem_wen,
output reg mem_ren,
output reg read_rs,
output reg read_rt,
output reg alloc_RS_en,
output reg ldic,
output reg isSignEx,
output reg isImmed,
output reg alu_ctrl0,
output reg alu_ctrl1,
output reg alu_ctrl2,
output reg alu_ctrl3,
output reg isJump,
output reg isJR,
output reg link
);
localparam NOP = 6'b000000;
localparam ADD = 6'b000001;
localparam ADDI = 6'b000010;
localparam SUB = 6'b000011;
localparam LUI = 6'b000100;
localparam MOV = 6'b000101;
localparam SLL = 6'b000110;
localparam SRA = 6'b000111;
localparam SRL = 6'b001000;
localparam AND = 6'b001001;
localparam ANDI = 6'b001010;
localparam NOT = 6'b001011;
localparam OR = 6'b001100;
localparam ORI = 6'b001101;
localparam XOR = 6'b001110;
localparam XORI = 6'b001111;
localparam LW = 6'b010001;
localparam SW = 6'b010010;
localparam B = 6'b010011;
localparam BEQ = 6'b010100;
localparam BGT = 6'b010101;
localparam BGE = 6'b010110;
localparam BLE = 6'b010111;
localparam BLT = 6'b011000;
localparam BNE = 6'b011001;
localparam J = 6'b011010;
localparam JAL = 6'b011011;
localparam JALR = 6'b011100;
localparam JR = 6'b011101;
localparam STRCNT = 6'b100000;
localparam STPCNT = 6'b100001;
localparam LDCC = 6'b100010;
localparam LDIC = 6'b100011;
localparam TX = 6'b110000;
localparam HALT = 6'b110001;
localparam ADDB = 6'b010100;
localparam ADDBI = 6'b010101;
localparam SUBB = 6'b010110;
localparam SUBBI = 6'b010111;
wire [5:0] ctrl_codes = opcode;
always @(ctrl_codes) begin
case(ctrl_codes)
NOP: begin
writeRd = 0;
RegDest = 0;
isDispatch = 0;
mem_wen = 0;
mem_ren = 0;
read_rs = 0;
read_rt = 0;
alloc_RS_en = 0;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
ADD: begin
writeRd = 1;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
ADDI: begin
writeRd = 0;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 1;
isImmed = 1;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
SUB: begin
writeRd = 1;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
LUI: begin
writeRd = 0;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 0;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 1;
alu_ctrl0 = 0;
alu_ctrl1 = 1;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
MOV: begin
writeRd = 0;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 1;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
SLL: begin
writeRd = 1;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 0;
alu_ctrl2 = 1;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
SRA: begin
writeRd = 1;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 1;
alu_ctrl2 = 1;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
SRL: begin
writeRd = 1;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 1;
alu_ctrl2 = 1;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
AND: begin
writeRd = 1;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 1;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
ANDI: begin
writeRd = 0;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 1;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 1;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
NOT: begin
writeRd = 0;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 1;
isJump = 0;
isJR = 0;
link = 0;
end
OR: begin
writeRd = 1;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 1;
isJump = 0;
isJR = 0;
link = 0;
end
ORI: begin
writeRd = 0;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 1;
alu_ctrl0 = 1;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 1;
isJump = 0;
isJR = 0;
link = 0;
end
XOR: begin
writeRd = 1;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 1;
alu_ctrl2 = 0;
alu_ctrl3 = 1;
isJump = 0;
isJR = 0;
link = 0;
end
XORI: begin
writeRd = 0;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 1;
alu_ctrl0 = 0;
alu_ctrl1 = 1;
alu_ctrl2 = 0;
alu_ctrl3 = 1;
isJump = 0;
isJR = 0;
link = 0;
end
LW: begin
writeRd = 0;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 1;
read_rs = 1;
read_rt = 0;
alloc_RS_en = 0;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
SW: begin
writeRd = 0;
RegDest = 0;
isDispatch = 1;
mem_wen = 1;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 0;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
B: begin
writeRd = 0;
RegDest = 0;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
BEQ: begin
writeRd = 0;
RegDest = 0;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
BGT: begin
writeRd = 0;
RegDest = 0;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
BGE: begin
writeRd = 0;
RegDest = 0;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
BLE: begin
writeRd = 0;
RegDest = 0;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
BLT: begin
writeRd = 0;
RegDest = 0;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
BNE: begin
writeRd = 0;
RegDest = 0;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
J: begin
writeRd = 0;
RegDest = 0;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 0;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 1;
isJR = 0;
link = 0;
end
JAL: begin
writeRd = 0;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 0;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 1;
isJR = 0;
link = 1;
end
JALR: begin
writeRd = 0;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 1;
isJR = 1;
link = 1;
end
JR: begin
writeRd = 0;
RegDest = 0;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 1;
isJR = 1;
link = 0;
end
STRCNT: begin
writeRd = 0;
RegDest = 0;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 0;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
STPCNT: begin
writeRd = 0;
RegDest = 0;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 0;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
LDCC: begin
writeRd = 0;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 0;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 1;
alu_ctrl2 = 1;
alu_ctrl3 = 1;
isJump = 0;
isJR = 0;
link = 0;
end
LDIC: begin
writeRd = 0;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 0;
read_rt = 0;
alloc_RS_en = 1;
ldic = 1;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 1;
alu_ctrl2 = 1;
alu_ctrl3 = 1;
isJump = 0;
isJR = 0;
link = 0;
end
TX: begin
writeRd = 0;
RegDest = 0;
isDispatch = 0;
mem_wen = 0;
mem_ren = 0;
read_rs = 0;
read_rt = 0;
alloc_RS_en = 0;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
HALT: begin
writeRd = 0;
RegDest = 0;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 0;
read_rt = 0;
alloc_RS_en = 0;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
ADDB: begin
writeRd = 1;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 1;
alu_ctrl2 = 0;
alu_ctrl3 = 1;
isJump = 0;
isJR = 0;
link = 0;
end
ADDBI: begin
writeRd = 0;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 1;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 1;
alu_ctrl3 = 1;
isJump = 0;
isJR = 0;
link = 0;
end
SUBB: begin
writeRd = 1;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 0;
alu_ctrl2 = 1;
alu_ctrl3 = 1;
isJump = 0;
isJR = 0;
link = 0;
end
SUBBI: begin
writeRd = 0;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 1;
alu_ctrl0 = 0;
alu_ctrl1 = 1;
alu_ctrl2 = 1;
alu_ctrl3 = 1;
isJump = 0;
isJR = 0;
link = 0;
end
default: begin
writeRd = 0;
RegDest = 0;
isDispatch = 0;
mem_wen = 0;
mem_ren = 0;
read_rs = 0;
read_rt = 0;
alloc_RS_en = 0;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
endcase
end
endmodule
|
module map_table_tb();
reg clk;
reg rst;
//dispatch
reg [4:0] l_rs;
reg [4:0] l_rt;
reg [4:0] l_rd;
reg [5:0] p_rd_new;
reg RegDest;
reg isDispatch;
//recovery
reg [4:0] recover_rd;
reg [5:0] p_rd_flush;
reg recover;
reg RegDest_ROB;
reg hazard_stall;
reg [5:0] p_rd_compl;
reg complete;
reg RegDest_compl;
wire [5:0] p_rs;
wire [5:0] p_rt;
wire p_rs_v;
wire p_rt_v;
wire [5:0] PR_old_rd;
map_table i_map_table(
.clk(clk),
.rst(rst),
.l_rs(l_rs),
.l_rt(l_rt),
.l_rd(l_rd),
.recover_rd(recover_rd),
.p_rd_new(p_rd_new),
.p_rd_flush(p_rd_flush),
.recover(recover),
.hazard_stall(hazard_stall),
.RegDest(RegDest),
.p_rd_compl(p_rd_compl),
.complete(complete),
.RegDest_ROB(RegDest_ROB),
.RegDest_compl(RegDest_compl),
.p_rs(p_rs),
.p_rt(p_rt),
.p_rs_v(p_rs_v),
.p_rt_v(p_rt_v),
.PR_old_rd(PR_old_rd));
initial begin
clk = 0;
rst = 0;
hazard_stall = 0;
set_dispatch(0, 5'h00, 5'h00, 5'h00, 6'h00, 0);
set_recovery(5'h00, 6'h00, 0, 0);
set_complete(6'h00, 0, 0);
#2 rst = 1;
////////////////////dispatch tests/////////////////////////
@(posedge clk);
set_dispatch(1, 5'h01, 5'h02, 5'h03, 6'h20, 1); //ADD $r3, $r1, $r2 [3] = 20
set_recovery(5'h00, 6'h00, 0, 0);
set_complete(6'h00, 0, 1);
@(posedge clk);
set_dispatch(1, 5'h04, 5'h05, 5'h06, 6'h21, 1); //SUB $r6, $r4, $r5 [6] = 21
set_recovery(5'h00, 6'h00, 0, 0);
set_complete(6'h00, 0, 1);
@(posedge clk);
set_dispatch(1, 5'h07, 5'h08, 5'h00, 6'h22, 0); //B $r7 $r8 there's no rd
set_recovery(5'h00, 6'h00, 0, 0);
set_complete(6'h00, 0, 1);
/////////////////////////complete test//////////////////////////
@(posedge clk);
set_dispatch(1, 5'h03, 5'h02, 5'h07, 6'h22, 1); //ADD $r7, $r3, $r2 ,$r3 should have new map, [7] = 22
set_recovery(5'h00, 6'h00, 0, 0);
set_complete(6'h20, 1, 1);
@(posedge clk);
set_dispatch(1, 5'h01, 5'h02, 5'h07, 6'h23, 1); //SUB $r7, $r1, $r2 WAW with ADD [7] = 23
set_recovery(5'h00, 6'h00, 0, 0);
set_complete(6'h21, 1, 1);
@(posedge clk);
set_dispatch(1, 5'h01, 5'h02, 5'h09, 6'h24, 1); //ADD $r9, $r1, $r2 [9] = 24
set_recovery(5'h00, 6'h00, 0, 0);
set_complete(6'h22, 0, 0); //should not set valid[22]
@(posedge clk);
set_dispatch(1, 5'h09, 5'h0a, 5'h0b, 6'h25, 1); //ADD $r11, $r9, $r10
set_recovery(5'h06, 6'h06, 1, 1); //[6] = 06
set_complete(6'h22, 1, 1);
@(posedge clk);
set_dispatch(1, 5'h00, 5'h00, 5'h00, 6'h23, 0); //NOP
set_recovery(5'h07, 6'h22, 1, 0);
set_complete(6'h22, 1, 0); //during recovery, the CDB will also be stalled, value pair will be kept in EX/CMP
@(posedge clk);
set_dispatch(1, 5'h00, 5'h00, 5'h00, 6'h23, 0); //NOP
set_recovery(5'h09, 6'h24, 0, 0); //will be not written
set_complete(6'h23, 1, 1); //
repeat (3) @(posedge clk);
$stop;
end
always
#5 clk = ~clk;
task set_dispatch(input isDis, input [4:0] Lrs, input [4:0] Lrt, input [4:0] Lrd, input [5:0] PR_new, input regdst);
begin
isDispatch = isDis; l_rs = Lrs; l_rt = Lrt; l_rd = Lrd; p_rd_new = PR_new; RegDest = regdst;
end
endtask
task set_recovery(input [4:0] rec_rd, input [5:0] PR_flush, input rec, input regdst_rob);
begin
recover_rd = rec_rd; p_rd_flush = PR_flush; recover = rec; RegDest_ROB = regdst_rob;
end
endtask
task set_complete(input [5:0] rd_compl, input compl, input regdst_compl);
begin
p_rd_compl = rd_compl; complete = compl; RegDest_compl = regdst_compl;
end
endtask
endmodule
|
//re-order buffer did three things
//In dispatch, unless ROB is full, allocate new ROB entry for incoming instruction at tail, increase the tail
//during the recovery time (when dec_tail|recover is 1), the ROB will not allocate new entry for instructions in dispatch stage
//In complete, if the completed instruction is not a branch. The ROB entry indexed by rob_number will be marked as complete.
//if it is a branch misprediction or jump, stall all things (flush IF/DP) in the first cycle (when stall_recover is high),
//decrease the tail by 1 (since the tail points to next allocated instr, cannot recover from tail entry). Then,
//assert the recover signal, all data(PR_old, PR_new, rd) are ready, during the time recover is high, flush RS entry (ROB# match),
//flush MT, FL, LSQ (all for ROB# match), flush IS/EX(if ROB# match), EX/CMP(ROB# match). If ROB# doesn't match, stall that block.
//after recover becomes low, the changeFlow_out becomes 1 for 1 cycle, thus PC changes to correct PC, changeFlow also flush the IF/DP
//when recover is low, other parts are allowed to go (MT,RS,FL will not allocate since the IF/DP is NOP, however some instructions
//might still in IS/EX or EX/CMP, let them go
module reorder_buffer(
input rst, clk,
input isDispatch, //serve as the write enable of FIFO
input isSW, //
input RegDest, //stored for roll back, if it is 1, MT and FL need to be restored
input [5:0] PR_old_DP, //from map table, the previous PR#
input [5:0] PR_new_DP,
input [4:0] rd_DP, //architectural destinatioMn register
input complete, //from complete stage, if there is intruction completes
input [3:0] rob_number, //from the complete stage, used to set complete bit
input [31:0] jb_addr, //from complete stage
input changeFlow, //asserted if branch-misprediction or jump, from complete, start the state machine
input hazard_stall, //stall because of structure hazard, won't allocate new entry
output [3:0] rob_num_dp, //rob number in dispatch stage
output [5:0] PR_old_RT, //PR_old to be retired
output RegDest_retire, //only if the instruction write register, the PR_old is returned to MT and FL
output retire_reg, //read enable signal of FIFO
output retire_ST,
output [3:0] retire_rob, //for load/store queue, indicate which ROB entry is retired
output full, empty,
output RegDest_out,
output [5:0] PR_old_flush,
output [5:0] PR_new_flush,
output [4:0] rd_flush,
output [3:0] out_rob_num, //for recovery, provide the current ROB number for FL, MT, RS
output reg changeFlow_out, //asserted for one cycle after all recovery works done
output reg [31:0] changeFlow_addr,
output reg recover //recover signal, inform RS, MT, FL, LSQ, IS/EX, EX/CMP to flush(ROB# match) or stall (ROB# not match)
);
reg [18:0] rob [0:15]; //[18]: RegDest, (whether bet PR back to MT and FL) [17]: isSW, [16:12]rd, [11:6] pr_old, [5:0] pr_new
reg [15:0] complete_array;
/////////////////////////////////////////////Synch FIFO structure///////////////////////////////////////////
reg [3:0] head, tail;
reg dec_tail; //for recovery
assign rob_num_dp = tail;
wire read, write;
//no read or write of ROB during recovery
assign write = isDispatch && !full && !recover && !hazard_stall;
assign read = retire_reg && !empty && !recover && !hazard_stall;
//head logic
always @(posedge clk or negedge rst) begin
if (!rst) begin
head <= 4'h0;
end
else if (read) begin
head <= head + 1;
end
end
assign retire_reg = complete_array[head]; //if the head is complete, retire it
assign PR_old_RT = rob[head][11:6]; //the PR returned to free list
assign retire_ST = rob[head][17]; //tell SQ now a load/store is retired
assign RegDest_retire = rob[head][18];
assign retire_rob = head;
//tail logic
always @(posedge clk or negedge rst) begin
if (!rst)
tail <= 4'h0;
else if (dec_tail)
tail <= tail - 1; //when decreasing tail, the ROB will not accept new instructions
else if (write) begin
tail <= tail + 1;
rob[tail] <= {RegDest, isSW, rd_DP, PR_old_DP, PR_new_DP};
end
end
//Synch FIFO counter
reg [4:0] status_cnt;
always @(posedge clk or negedge rst) begin
if (!rst)
status_cnt <= 4'h0;
else if (write && !read) //write but not read
status_cnt <= status_cnt + 1;
else if (read && !write) //read but not write
status_cnt <= status_cnt - 1;
else if (dec_tail)
status_cnt <= status_cnt - 1;
end
assign full = status_cnt[4]; //if counter = 16, the FIFO is full
assign empty = ~(|status_cnt);
///////////////////////////////////////////////////end of synch FIFO///////////////////////////////////////////////////
//////////////////////////////complete part////////////////////////////////////
reg [3:0] branch_rob;
reg store_jb_addr;
genvar i;
generate for (i = 0; i < 16; i = i + 1) begin : complete_part
always @(posedge clk or negedge rst) begin
if (!rst)
complete_array[i] <= 0;
else if (rob_number == i && complete)
complete_array[i] <= 1'b1; //ROB# cannot equal to tail
else if (tail == i && write)
complete_array[i] <= 1'b0; //reset complete bit when allocate a new entry
end
end
endgenerate
//changeFlow address and ROB number for branch/jump
always @(posedge clk or negedge rst) begin
if (!rst) begin
changeFlow_addr <= 0;
branch_rob <= 0;
end
else if (store_jb_addr) begin
changeFlow_addr <= jb_addr;
branch_rob <= rob_number; //store the ROB# of branch when here comes a branch
end
end
//////////////////////////////end of complete part/////////////////////////////////////
assign out_rob_num = tail; //may need to store ROB number in RS, when completing instructions can index the ROB to set
//during recovery, this number is also used for indexing the flush entry
localparam IDLE = 1'b0;
localparam REC = 1'b1;
reg state, nstate;
always @(posedge clk or negedge rst) begin
if (!rst)
state <= IDLE;
else
state <= nstate;
end
wire recover_end = (branch_rob + 1 == tail);
always @(*) begin
nstate = IDLE;
dec_tail = 0;
recover = 0;
store_jb_addr = 0;
changeFlow_out = 0;
case (state)
IDLE: begin
if(complete && changeFlow) begin
nstate = REC;
dec_tail = 1;
recover = 1;
store_jb_addr = 1;
end
else
nstate = IDLE;
end
default: begin //recover
if(recover_end) begin
nstate = IDLE;
changeFlow_out = 1;
end
else begin
nstate = REC;
dec_tail = 1;
recover = 1;
end
end
endcase
end
//[16:12]rd, [11:6] t_old, [5:0] t_new
assign rd_flush = rob[tail-1][16:12];
assign PR_old_flush = rob[tail-1][11:6];
assign PR_new_flush = rob[tail-1][5:0];
assign RegDest_out = rob[tail-1][18];
//out_rob_tail assigned before, since it is used both in recovery and normal dispatch
endmodule
|
LIBAVFORMAT_$MAJOR {
global: *;
};
|
LIBAVUTIL_$MAJOR {
global: av_*; ff_*; avutil_*;
local: *;
};
|
LIBAVFILTER_$MAJOR {
global: avfilter_*; av_*;
local: *;
};
|
LIBPOSTPROC_$MAJOR {
global: postproc_*; pp_*;
local: *;
};
|
LIBAVCODEC_$MAJOR {
global: *;
};
|
LIBAVDEVICE_$MAJOR {
global: avdevice_*;
local: *;
};
|
LIBSWSCALE_$MAJOR {
global: swscale_*; sws_*; ff_*;
local: *;
};
|
//---------------------------------------------------------------------\r
// Design : Counter verilog top module, SPEC (Simple PCIe Carrier)\r
// Author : Javier D. Garcia-Lasheras\r
//---------------------------------------------------------------------\r
\r
module spec_top (\r
clear_i,\r
count_i,\r
clock_i,\r
led_o\r
);\r
\r
input clear_i, count_i, clock_i;\r
output [3:0] led_o;\r
\r
wire s_clock, s_clear, s_count; \r
wire [7:0] s_Q;\r
\r
counter u1(\r
.clock(s_clock),\r
.clear(s_clear),\r
.count(s_count),\r
.Q(s_Q)\r
);\r
\r
assign s_clock = clock_i;\r
assign s_clear = ~clear_i;\r
assign s_count = ~count_i;\r
assign led_o[3:0] = ~s_Q[7:4];\r
\r
endmodule\r
|
//--------------------------------------------------------\r
// Design : Counter verilog top module, Lattice Brevia2\r
// Author : Javier D. Garcia-Lasheras\r
//--------------------------------------------------------\r
\r
module brevia2_top (\r
clear_i,\r
count_i,\r
clock_i,\r
clken_o,\r
led_o\r
);\r
\r
input clear_i, count_i, clock_i;\r
output clken_o; \r
output [7:0] led_o;\r
\r
wire s_clock, s_clear, s_count; \r
wire [7:0] s_Q;\r
\r
counter u1(\r
.clock(s_clock),\r
.clear(s_clear),\r
.count(s_count),\r
.Q(s_Q)\r
);\r
\r
assign s_clock = clock_i;\r
assign clken_o = 1;\r
assign s_clear = ~clear_i;\r
assign s_count = ~count_i;\r
assign led_o[7:0] = ~s_Q[7:0];\r
\r
endmodule\r
|
//--------------------------------------------------------\r
// Design : Simple testbench for an 8-bit verilog counter\r
// Author : Javier D. Garcia-Lasheras\r
//--------------------------------------------------------\r
\r
module counter_tb();\r
// Declare inputs as regs and outputs as wires\r
reg clock, clear, count;\r
wire [7:0] Q;\r
\r
// Initialize all variables\r
initial begin \r
$dumpfile("counter_tb.vcd");\r
$dumpvars(0,counter_tb); \r
$display ("time\\t clock clear count Q");\t\r
$monitor ("%g\\t %b %b %b %b", \r
\t $time, clock, clear, count, Q);\t\r
clock = 1; // initial value of clock\r
clear = 0; // initial value of clear\r
count = 0; // initial value of count enable\r
#5 clear = 1; // Assert the clear signal\r
#10 clear = 0; // De-assert clear signal\r
#10 count = 1; // Start count \r
#2000 count = 0; // De-assert count enable\r
#5 $finish; // Terminate simulation\r
end\r
\r
// Clock generator\r
always begin\r
#5 clock = ~clock; // Toggle clock every 5 ticks\r
end\r
\r
// Connect DUT to test bench\r
counter U_counter (\r
clock,\r
clear,\r
count,\r
Q\r
);\r
\r
endmodule\r
|
//--------------------------------------------------------------------\r
// Design : Counter verilog top module, Altera CycloneIII Starter Kit\r
// Author : Javier D. Garcia-Lasheras\r
//--------------------------------------------------------------------\r
\r
module cyclone3_top (\r
clear_i,\r
count_i,\r
clock_i,\r
led_o\r
);\r
\r
input clear_i, count_i, clock_i;\r
output [3:0] led_o;\r
\r
wire s_clock, s_clear, s_count; \r
wire [7:0] s_Q;\r
\r
counter u1(\r
.clock(s_clock),\r
.clear(s_clear),\r
.count(s_count),\r
.Q(s_Q)\r
);\r
\r
assign s_clock = clock_i;\r
assign s_clear = ~clear_i;\r
assign s_count = ~count_i;\r
assign led_o[3:0] = ~s_Q[7:4];\r
\r
endmodule\r
|
//-----------------------------------------------------\r
// Design : Simple 8-bit verilog counter\r
// Author : Javier D. Garcia-Lasheras\r
//-----------------------------------------------------\r
\r
module counter (\r
clock,\r
clear,\r
count,\r
Q\r
);\r
\r
//--------- Output Ports ------------------------------\r
output [7:0] Q;\r
\r
//--------- Input Ports -------------------------------\r
input clock, clear, count;\r
\r
//--------- Internal Variables ------------------------\r
reg [7:0] Q;\r
\r
//--------- Code Starts Here --------------------------\r
always @(posedge clock)\r
if (clear) begin\r
Q <= 8'b0 ;\r
end else if (count) begin\r
Q <= Q + 1;\r
end\r
\r
endmodule \r
|
//---------------------------------------------------------------------\r
// Design : Counter verilog top module, Microsemi ProASIC3 Starter Kit\r
// Author : Javier D. Garcia-Lasheras\r
//---------------------------------------------------------------------\r
\r
module proasic3_top (\r
clear_i,\r
count_i,\r
clock_i,\r
led_o\r
);\r
\r
input clear_i, count_i, clock_i;\r
output [7:0] led_o;\r
\r
wire s_clock, s_clear, s_count; \r
wire [7:0] s_Q;\r
\r
counter u1(\r
.clock(s_clock),\r
.clear(s_clear),\r
.count(s_count),\r
.Q(s_Q)\r
);\r
\r
assign s_clock = clock_i;\r
assign s_clear = clear_i;\r
assign s_count = count_i;\r
assign led_o[7:0] = s_Q[7:0];\r
\r
endmodule\r
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
* Copyright (C) 2007 Das Labor
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module uart_transceiver(
\tinput sys_rst,
\tinput sys_clk,
\tinput uart_rx,
\toutput reg uart_tx,
\tinput [15:0] divisor,
\toutput reg [7:0] rx_data,
\toutput reg rx_done,
\tinput [7:0] tx_data,
\tinput tx_wr,
\toutput reg tx_done
);
//-----------------------------------------------------------------
// enable16 generator
//-----------------------------------------------------------------
reg [15:0] enable16_counter;
wire enable16;
assign enable16 = (enable16_counter == 16\'d0);
always @(posedge sys_clk) begin
\tif(sys_rst)
\t\tenable16_counter <= divisor - 16\'b1;
\telse begin
\t\tenable16_counter <= enable16_counter - 16\'d1;
\t\tif(enable16)
\t\t\tenable16_counter <= divisor - 16\'b1;
\tend
end
//-----------------------------------------------------------------
// Synchronize uart_rx
//-----------------------------------------------------------------
reg uart_rx1;
reg uart_rx2;
always @(posedge sys_clk) begin
\tuart_rx1 <= uart_rx;
\tuart_rx2 <= uart_rx1;
end
//-----------------------------------------------------------------
// UART RX Logic
//-----------------------------------------------------------------
reg rx_busy;
reg [3:0] rx_count16;
reg [3:0] rx_bitcount;
reg [7:0] rx_reg;
always @(posedge sys_clk) begin
\tif(sys_rst) begin
\t\trx_done <= 1\'b0;
\t\trx_busy <= 1\'b0;
\t\trx_count16 <= 4\'d0;
\t\trx_bitcount <= 4\'d0;
\tend else begin
\t\trx_done <= 1\'b0;
\t\tif(enable16) begin
\t\t\tif(~rx_busy) begin // look for start bit
\t\t\t\tif(~uart_rx2) begin // start bit found
\t\t\t\t\trx_busy <= 1\'b1;
\t\t\t\t\trx_count16 <= 4\'d7;
\t\t\t\t\trx_bitcount <= 4\'d0;
\t\t\t\tend
\t\t\tend else begin
\t\t\t\trx_count16 <= rx_count16 + 4\'d1;
\t\t\t\tif(rx_count16 == 4\'d0) begin // sample
\t\t\t\t\trx_bitcount <= rx_bitcount + 4\'d1;
\t\t\t\t\tif(rx_bitcount == 4\'d0) begin // verify startbit
\t\t\t\t\t\tif(uart_rx2)
\t\t\t\t\t\t\trx_busy <= 1\'b0;
\t\t\t\t\tend else if(rx_bitcount == 4\'d9) begin
\t\t\t\t\t\trx_busy <= 1\'b0;
\t\t\t\t\t\tif(uart_rx2) begin // stop bit ok
\t\t\t\t\t\t\trx_data <= rx_reg;
\t\t\t\t\t\t\trx_done <= 1\'b1;
\t\t\t\t\t\tend // ignore RX error
\t\t\t\t\tend else
\t\t\t\t\t\trx_reg <= {uart_rx2, rx_reg[7:1]};
\t\t\t\tend
\t\t\tend
\t\tend
\tend
end
//-----------------------------------------------------------------
// UART TX Logic
//-----------------------------------------------------------------
reg tx_busy;
reg [3:0] tx_bitcount;
reg [3:0] tx_count16;
reg [7:0] tx_reg;
always @(posedge sys_clk) begin
\tif(sys_rst) begin
\t\ttx_done <= 1\'b0;
\t\ttx_busy <= 1\'b0;
\t\tuart_tx <= 1\'b1;
\tend else begin
\t\ttx_done <= 1\'b0;
\t\tif(tx_wr) begin
\t\t\ttx_reg <= tx_data;
\t\t\ttx_bitcount <= 4\'d0;
\t\t\ttx_count16 <= 4\'d1;
\t\t\ttx_busy <= 1\'b1;
\t\t\tuart_tx <= 1\'b0;
`ifdef SIMULATION
\t\t\t$display("UART:\xc2\xa0%c", tx_data);
`endif
\t\tend else if(enable16 && tx_busy) begin
\t\t\ttx_count16 <= tx_count16 + 4\'d1;
\t\t\tif(tx_count16 == 4\'d0) begin
\t\t\t\ttx_bitcount <= tx_bitcount + 4\'d1;
\t\t\t\t
\t\t\t\tif(tx_bitcount == 4\'d8) begin
\t\t\t\t\tuart_tx <= 1\'b1;
\t\t\t\tend else if(tx_bitcount == 4\'d9) begin
\t\t\t\t\tuart_tx <= 1\'b1;
\t\t\t\t\ttx_busy <= 1\'b0;
\t\t\t\t\ttx_done <= 1\'b1;
\t\t\t\tend else begin
\t\t\t\t\tuart_tx <= tx_reg[0];
\t\t\t\t\ttx_reg <= {1\'b0, tx_reg[7:1]};
\t\t\t\tend
\t\t\tend
\t\tend
\tend
end
endmodule
|
module data_receiver(iClock, iReset, iRxDone, iReceivedData, oResultData, oDoneReceiving);
\tparameter IDLE = 3'b000,
\t\tFETCH_FIRST_VALUE = 3'b001,
\t\tCHECK_VALUE = 3'b010,
\t\tRECEIVE_DATA = 3'b011,
\t\tEMIT_DONE_RECEIVING = 3'b100,
\t\tRECEIVING_DATA = 3'b101,
\t\tFETCH_VALUE_INC_COUNTER = 3'b110,
\t\tINPUT_MESSAGE = 2'b00,
\t\tCIRCUIT_MESSAGE = 2'b01;
\tinput iClock;
\tinput iReset;
\tinput iRxDone;
\tinput [7:0] iReceivedData;
\toutput reg [7:0] oResultData[199:0];
\toutput oDoneReceiving;
\treg [2:0] state = IDLE;
\treg [7:0] receive_counter = 8'b0;
\treg [7:0] incoming_message_size = 8'b0;
\twire [2:0] next_state;
\t
\tassign next_state = next_state_fun(state, iRxDone,
\t\treceive_counter, incoming_message_size);
\t
\tfunction [2:0] next_state_fun(input [2:0] current_state, input rx_done,
\t\tinput [7:0] counter, input [7:0] message_size);
\t\tcase(current_state)
\t\tIDLE:
\t\t\tif (rx_done) begin
\t\t\t\tnext_state_fun = FETCH_FIRST_VALUE;
\t\t\tend else begin
\t\t\t\tnext_state_fun = IDLE;
\t\t\tend
\t\tFETCH_FIRST_VALUE:
\t\t\tnext_state_fun = CHECK_VALUE;
\t\tCHECK_VALUE:
\t\t\tnext_state_fun = RECEIVE_DATA;
\t\tRECEIVE_DATA:
\t\t\tif (counter < message_size) begin
\t\t\t\tnext_state_fun = RECEIVING_DATA;
\t\t\tend else begin
\t\t\t\tnext_state_fun = EMIT_DONE_RECEIVING;
\t\t\tend
\t\tRECEIVING_DATA:
\t\t\tif (rx_done) begin
\t\t\t\tnext_state_fun = FETCH_VALUE_INC_COUNTER;
\t\t\tend else begin
\t\t\t\tnext_state_fun = RECEIVING_DATA;
\t\t\tend
\t\tFETCH_VALUE_INC_COUNTER:
\t\t\tnext_state_fun = RECEIVE_DATA;
\t\tEMIT_DONE_RECEIVING:
\t\t\tnext_state_fun = IDLE;
\t\tdefault:
\t\t\tnext_state_fun = IDLE;
\t\tendcase
\tendfunction
\t
always@ (posedge iClock) begin
\tif (iReset) begin
\t\tstate <= IDLE;
\tend else begin
\t\tstate <= next_state;
\tend
end
always@ (posedge iClock) begin
\toDoneReceiving <= 0;
\tif (iReset) begin
\tend else begin
\t\tcase(state)
\t\tIDLE: begin
\t\t\treceive_counter <= 0;
\t\tend
\t\tFETCH_FIRST_VALUE: begin
\t\t\toResultData[receive_counter] <= iReceivedData;
\t\t\treceive_counter <= receive_counter + 8'b1;
\t\tend
\t\tCHECK_VALUE: begin
\t\t\tif (oResultData[0] == INPUT_MESSAGE) begin
\t\t\t\tincoming_message_size = 8'b1 + 8'b1;
\t\t\tend else begin
\t\t\t\tincoming_message_size = 8'd29 + 8'b1;
\t\t\tend
\t\tend
\t\tFETCH_VALUE_INC_COUNTER: begin
\t\t\toResultData[receive_counter] <= iReceivedData;
\t\t\treceive_counter <= receive_counter + 8'b1;
\t\tend
\t\tEMIT_DONE_RECEIVING: begin
\t\t\toDoneReceiving <= 1;
\t\tend
\t\tdefault: begin
\t\tend
\t\tendcase
\tend
end
endmodule
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: memoria.v
// Megafunction Name(s):
// \t\t\taltsyncram
//
// Simulation Library Files(s):
// \t\t\taltera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation\'s design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module memoria (
\taddress,
\tclock,
\tdata,
\twren,
\tq);
\tinput\t[15:0] address;
\tinput\t clock;
\tinput\t[7:0] data;
\tinput\t wren;
\toutput\t[7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
\ttri1\t clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
\twire [7:0] sub_wire0;
\twire [7:0] q = sub_wire0[7:0];
\taltsyncram\taltsyncram_component (
\t\t\t\t.address_a (address),
\t\t\t\t.clock0 (clock),
\t\t\t\t.data_a (data),
\t\t\t\t.wren_a (wren),
\t\t\t\t.q_a (sub_wire0),
\t\t\t\t.aclr0 (1\'b0),
\t\t\t\t.aclr1 (1\'b0),
\t\t\t\t.address_b (1\'b1),
\t\t\t\t.addressstall_a (1\'b0),
\t\t\t\t.addressstall_b (1\'b0),
\t\t\t\t.byteena_a (1\'b1),
\t\t\t\t.byteena_b (1\'b1),
\t\t\t\t.clock1 (1\'b1),
\t\t\t\t.clocken0 (1\'b1),
\t\t\t\t.clocken1 (1\'b1),
\t\t\t\t.clocken2 (1\'b1),
\t\t\t\t.clocken3 (1\'b1),
\t\t\t\t.data_b (1\'b1),
\t\t\t\t.eccstatus (),
\t\t\t\t.q_b (),
\t\t\t\t.rden_a (1\'b1),
\t\t\t\t.rden_b (1\'b1),
\t\t\t\t.wren_b (1\'b0));
\tdefparam
\t\taltsyncram_component.clock_enable_input_a = "BYPASS",
\t\taltsyncram_component.clock_enable_output_a = "BYPASS",
\t\taltsyncram_component.intended_device_family = "Cyclone IV E",
\t\taltsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
\t\taltsyncram_component.lpm_type = "altsyncram",
\t\taltsyncram_component.numwords_a = 65536,
\t\taltsyncram_component.operation_mode = "SINGLE_PORT",
\t\taltsyncram_component.outdata_aclr_a = "NONE",
\t\taltsyncram_component.outdata_reg_a = "CLOCK0",
\t\taltsyncram_component.power_up_uninitialized = "FALSE",
\t\taltsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
\t\taltsyncram_component.widthad_a = 16,
\t\taltsyncram_component.width_a = 8,
\t\taltsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "65536"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "16"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "65536"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 16 0 INPUT NODEFVAL "address[15..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 16 0 address 0 0 16 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL memoria.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL memoria.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL memoria.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL memoria.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL memoria_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL memoria_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
module logic_e(conf_func, conf_ins, all_inputs, out);
\tinput [2:0] conf_func;
\tinput [7:0] conf_ins;
\tinput [11:0] all_inputs;
\toutput out;
\t
\twire all_funcs[6:0];
\t
\tand func0(all_funcs[0], all_inputs[conf_ins[7:4]], all_inputs[conf_ins[3:0]]);
\tor func1(all_funcs[1], all_inputs[conf_ins[7:4]], all_inputs[conf_ins[3:0]]);
\txor func2(all_funcs[2], all_inputs[conf_ins[7:4]], all_inputs[conf_ins[3:0]]);
\tnot func3(all_funcs[3], all_inputs[conf_ins[7:4]]);
\tnand func4(all_funcs[4], all_inputs[conf_ins[7:4]], all_inputs[conf_ins[3:0]]);
\txnor func5(all_funcs[5], all_inputs[conf_ins[7:4]], all_inputs[conf_ins[3:0]]);
\tnor func6(all_funcs[6], all_inputs[conf_ins[7:4]], all_inputs[conf_ins[3:0]]);
\t
\tassign out = all_funcs[conf_func];
endmodule
|
// megafunction wizard: %RAM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: memoria.v
// Megafunction Name(s):
// \t\t\taltsyncram
//
// Simulation Library Files(s):
// \t\t\taltera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation\'s design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module memoria (
\taddress,
\tclock,
\tdata,
\twren,
\tq);
\tinput\t[15:0] address;
\tinput\t clock;
\tinput\t[7:0] data;
\tinput\t wren;
\toutput\t[7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
\ttri1\t clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "65536"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "16"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "65536"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 16 0 INPUT NODEFVAL "address[15..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 16 0 address 0 0 16 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL memoria.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL memoria.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL memoria.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL memoria.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL memoria_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL memoria_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
module main_fsm(iClock, iReset, iDoneReceiving, iReceivedData, iSamplingDone, iSendingDone,
\toMemWrite, oMemAddr, oStartSampling, oStartSending, oFetchValue, oSetCurrentCircuit,
\toInsertValue, oResetSerial);
\tparameter IDLE = 3'b000,
\t\tSAMPLING = 3'b001,
\t\tSENDING = 3'b010,
\t\tSTART_SAMPLING = 3'b011,
\t\tSTART_SENDING = 3'b100,
\t\tFETCH_VALUE = 3'b101,
\t\tSET_CURRENT_CIRCUIT = 3'b110,
\t\tINPUT_MESSAGE = 2'b00,
\t\tCIRCUIT_MESSAGE = 2'b01;
\tinput iClock;
\tinput iReset;
\tinput iDoneReceiving;
\tinput iSamplingDone;
\tinput iSendingDone;
\tinput [7:0] iReceivedData[199:0];
\t
\toutput oMemWrite;
\toutput oMemAddr;
\toutput oStartSampling;
\toutput oStartSending;
\toutput oFetchValue;
\toutput oResetSerial;
\toutput oInsertValue;
\toutput oSetCurrentCircuit;
\t
\treg [2:0] state = IDLE;
\twire [2:0] next_state;
\t
\tassign next_state = next_state_fun(state, iReceivedData, iDoneReceiving,
\t\tiSamplingDone, iSendingDone);
\t
\tfunction [2:0] next_state_fun(input [2:0] current_state, input [7:0] received_data[199:0],
\t\tinput iDoneReceiving, input iSamplingDone, input iSendingDone);
\t\tcase(current_state)
\t\tIDLE:
\t\t\tif (iDoneReceiving) begin
\t\t\t\tif (received_data[0] == INPUT_MESSAGE) begin
\t\t\t\t\tnext_state_fun = FETCH_VALUE;
\t\t\t\tend else begin
\t\t\t\t\tnext_state_fun = SET_CURRENT_CIRCUIT;
\t\t\t\tend
\t\t\tend else begin
\t\t\t\tnext_state_fun = IDLE;
\t\t\tend
\t\tSET_CURRENT_CIRCUIT:
\t\t\tnext_state_fun = IDLE;
\t\tFETCH_VALUE:
\t\t\tnext_state_fun = START_SAMPLING;
\t\tSAMPLING:
\t\t\tif (iSamplingDone) begin
\t\t\t\tnext_state_fun = START_SENDING;
\t\t\tend else begin
\t\t\t\tnext_state_fun = SAMPLING;
\t\t\tend
\t\tSENDING:
\t\t\tif (iSendingDone) begin
\t\t\t\tnext_state_fun = IDLE;
\t\t\tend else begin
\t\t\t\tnext_state_fun = SENDING;
\t\t\tend
\t\tSTART_SAMPLING:
\t\t\tnext_state_fun = SAMPLING;
\t\tSTART_SENDING:
\t\t\tnext_state_fun = SENDING;
\t\tdefault:
\t\t\tnext_state_fun = IDLE;
\t\tendcase
\t\t
\tendfunction
\t
always@ (posedge iClock) begin
\tif (iReset) begin
\t\tstate <= IDLE;
\tend else begin
\t\tstate <= next_state;
\tend
end
always@ (posedge iClock) begin
\toMemAddr <= 0;
\toMemWrite <= 0;
\toStartSampling <= 0;
\toStartSending <= 0;
\toFetchValue <= 0;
\toInsertValue <= 0;
\toResetSerial <= 0;
\toSetCurrentCircuit <= 0;
\tif (iReset) begin
\tend else begin
\t\tcase (state)
\t\tIDLE: begin
\t\tend
\t\tSET_CURRENT_CIRCUIT: begin
\t\t\toSetCurrentCircuit <= 1;
\t\tend
\t\tFETCH_VALUE: begin
\t\t\toFetchValue <= 1;
\t\tend
\t\tSAMPLING: begin
\t\t\toMemWrite <= 1;
\t\tend
\t\tSENDING: begin
\t\t\toMemAddr <= 1;
\t\tend
\t\tSTART_SAMPLING: begin
\t\t\toStartSampling <= 1;
\t\t\toResetSerial <= 1;
\t\t\toInsertValue <= 1;
\t\tend
\t\tSTART_SENDING: begin
\t\t\toStartSending <= 1;
\t\tend
\t\tendcase
\tend
end
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module uart #(
\tparameter csr_addr = 4'h0,
\tparameter clk_freq = 50000000,
\tparameter baud = 115200
) (
\tinput sys_clk,
\tinput sys_rst,
\t
\tinput [13:0] csr_a,
\tinput csr_we,
\tinput [31:0] csr_di,
\toutput reg [31:0] csr_do,
\toutput rx_irq,
\toutput tx_irq,
\tinput uart_rx,
\toutput uart_tx
);
reg [15:0] divisor;
wire [7:0] rx_data;
wire [7:0] tx_data;
wire tx_wr;
reg thru;
wire uart_tx_transceiver;
uart_transceiver transceiver(
\t.sys_clk(sys_clk),
\t.sys_rst(sys_rst),
\t.uart_rx(uart_rx),
\t.uart_tx(uart_tx_transceiver),
\t.divisor(divisor),
\t.rx_data(rx_data),
\t.rx_done(rx_irq),
\t.tx_data(tx_data),
\t.tx_wr(tx_wr),
\t.tx_done(tx_irq)
);
assign uart_tx = thru ? uart_rx : uart_tx_transceiver;
/* CSR interface */
wire csr_selected = csr_a[13:10] == csr_addr;
assign tx_data = csr_di[7:0];
assign tx_wr = csr_selected & csr_we & (csr_a[1:0] == 2'b00);
parameter default_divisor = clk_freq/baud/16;
always @(posedge sys_clk) begin
\tif(sys_rst) begin
\t\tdivisor <= default_divisor;
\t\tcsr_do <= 32'd0;
\tend else begin
\t\tcsr_do <= 32'd0;
\t\tif(csr_selected) begin
\t\t\tcase(csr_a[1:0])
\t\t\t\t2'b00: csr_do <= rx_data;
\t\t\t\t2'b01: csr_do <= divisor;
\t\t\t\t2'b10: csr_do <= thru;
\t\t\tendcase
\t\t\tif(csr_we) begin
\t\t\t\tcase(csr_a[1:0])
\t\t\t\t\t2'b00:; /* handled by transceiver */
\t\t\t\t\t2'b01: divisor <= csr_di[15:0];
\t\t\t\t\t2'b10: thru <= csr_di[0];
\t\t\t\tendcase
\t\t\tend
\t\tend
\tend
end
endmodule
|
module sampler(iClock, iReset, iStartSignal, oAddress, oFinished);
\tparameter IDLE = 2'b00,
\t\tSAMPLING = 2'b01,
\t\tINCREMENTING_ADDR = 2'b10,
\t\tFINISHED_SAMPLING = 2'b11;
\tinput iClock;
\tinput iReset;
\tinput iStartSignal;
\toutput reg [15:0] oAddress;
\toutput oFinished;
\t
\treg [1:0] state = IDLE;
\twire [1:0] next_state;
\t
\tassign next_state = next_state_fun(state, iStartSignal, oAddress);
\tfunction [1:0] next_state_fun(input [1:0] state, input start_signal, input [15:0] address);
\t\tcase(state)
\t\tIDLE:
\t\t\tif (start_signal) begin
\t\t\t\tnext_state_fun = SAMPLING;
\t\t\tend else begin
\t\t\t\tnext_state_fun = IDLE;
\t\t\tend
\t\tSAMPLING:
\t\t\tif (address < 16'hFFFF) begin
\t\t\t\tnext_state_fun = INCREMENTING_ADDR;
\t\t\tend else begin
\t\t\t\tnext_state_fun = FINISHED_SAMPLING;
\t\t\tend
\t\tINCREMENTING_ADDR:
\t\t\tnext_state_fun = SAMPLING;
\t\tFINISHED_SAMPLING:
\t\t\tnext_state_fun = IDLE;
\t\tdefault:
\t\t\tnext_state_fun = IDLE;
\t\tendcase
\t
\tendfunction
\t
always@(posedge iClock) begin
\tif (iReset) begin
\t\tstate <= IDLE;
\tend else begin
\t\tstate <= next_state;
\tend
end
always@(posedge iClock) begin
\toFinished <= 0;
\tcase(state)
\tIDLE: begin
\t\toAddress <= 16'b0;
\tend
\tSAMPLING: begin
\tend
\tINCREMENTING_ADDR: begin
\t\toAddress <= oAddress + 16'b1;
\tend
\tFINISHED_SAMPLING: begin
\t\toFinished <= 1;
\tend
\tendcase
end
endmodule
|
module genetico(conf_les, conf_outs, in, out);
\tinput [10:0] conf_les[8:0];
\tinput [3:0] conf_outs[1:0];
\tinput [2:0] in;
\toutput [1:0] out;
\t
\twire [8:0] le_out;
\twire [11:0] all_inputs;
\t
\tassign all_inputs = {le_out, in};
\t
\tassign out = {all_inputs[conf_outs[1]], all_inputs[conf_outs[0]]};
\t
logic_e le00(
\t.conf_func(conf_les[0][10:8]),
\t.conf_ins(conf_les[0][7:0]),
\t.all_inputs(all_inputs),
\t.out(le_out[0])
);
logic_e le10(
\t.conf_func(conf_les[1][10:8]),
\t.conf_ins(conf_les[1][7:0]),
\t.all_inputs(all_inputs),
\t.out(le_out[1])
);
logic_e le20(
\t.conf_func(conf_les[2][10:8]),
\t.conf_ins(conf_les[2][7:0]),
\t.all_inputs(all_inputs),
\t.out(le_out[2])
);
logic_e le01(
\t.conf_func(conf_les[3][10:8]),
\t.conf_ins(conf_les[3][7:0]),
\t.all_inputs(all_inputs),
\t.out(le_out[3])
);
logic_e le11(
\t.conf_func(conf_les[4][10:8]),
\t.conf_ins(conf_les[4][7:0]),
\t.all_inputs(all_inputs),
\t.out(le_out[4])
);
logic_e le21(
\t.conf_func(conf_les[5][10:8]),
\t.conf_ins(conf_les[5][7:0]),
\t.all_inputs(all_inputs),
\t.out(le_out[5])
);
logic_e le02(
\t.conf_func(conf_les[6][10:8]),
\t.conf_ins(conf_les[6][7:0]),
\t.all_inputs(all_inputs),
\t.out(le_out[6])
);
logic_e le12(
\t.conf_func(conf_les[7][10:8]),
\t.conf_ins(conf_les[7][7:0]),
\t.all_inputs(all_inputs),
\t.out(le_out[7])
);
logic_e le22(
\t.conf_func(conf_les[8][10:8]),
\t.conf_ins(conf_les[8][7:0]),
\t.all_inputs(all_inputs),
\t.out(le_out[8])
);
endmodule
|
module main(CLOCK_50, KEY, LEDR, SW, UART_RXD, UART_TXD);
\tinput CLOCK_50;
\tinput KEY[3:0];
\toutput [17:0] LEDR;
\tinput [17:0] SW;
\tinput UART_RXD;
\toutput UART_TXD;
\t
\tinteger i;
\t
\t// Regs
\treg [7:0] current_value, value_into_genetico;
\treg [10:0] current_circuit_les[8:0];
\treg [3:0] current_circuit_outs[1:0];
\t
\t// Wires
\twire [31:0] data_to_send, rs232_received_data;
\twire [7:0] mem_out, genetico_out;
\twire rx_done, tx_done, tx_send, start_sampling, start_sending, mem_write,
\t\tfinished_sampling, finished_sending, mem_addr, fetch_value, serial_reset,
\t\tinsert_value, done_receiving, set_current_circuit;
\twire [15:0] sampler_mem_addr, sender_mem_addr;
\twire [7:0] received_data[199:0];
\t
\tassign LEDR[7:0] = current_value;
\tassign LEDR[17:10] = genetico_out;
\tassign data_to_send = {24'b0, mem_out};
always @(posedge CLOCK_50) begin
\tif (fetch_value)
\t\tcurrent_value <= received_data[1];
\tif (insert_value)
\t\tvalue_into_genetico <= current_value;
\tif (set_current_circuit) begin
\t\tfor (i = 0; i < 9; i = i + 1) begin
\t\t\tcurrent_circuit_les[i][10:8] <= received_data[(i * 3) + 1][2:0];
\t\t\tcurrent_circuit_les[i][7:4] <= received_data[(i * 3) + 2][3:0];
\t\t\tcurrent_circuit_les[i][3:0] <= received_data[(i * 3) + 3][3:0];
\t\tend
\t\tfor (i = 0; i < 2; i = i + 1) begin
\t\t\tcurrent_circuit_outs[i] <= received_data[i + 27 + 1][3:0];
\t\tend
\tend
end\t
sampler sampler(
\t.iClock(CLOCK_50),
\t.iReset(~KEY[1]),
\t.iStartSignal(start_sampling),
\t.oAddress(sampler_mem_addr),
\t.oFinished(finished_sampling)
);
sender sender(
\t.iClock(CLOCK_50),
\t.iReset(~KEY[1]),
\t.iTxDone(tx_done),
\t.iStartSignal(start_sending),
\t.oAddress(sender_mem_addr),
\t.oFinished(finished_sending),
\t.oTxSend(tx_send)
);
main_fsm fsm(
\t.iClock(CLOCK_50),
\t.iReset(~KEY[1]),
\t.iDoneReceiving(done_receiving),
\t.iReceivedData(received_data),
\t.iSamplingDone(finished_sampling),
\t.iSendingDone(finished_sending),
\t.oMemWrite(mem_write),
\t.oMemAddr(mem_addr),
\t.oStartSampling(start_sampling),
\t.oStartSending(start_sending),
\t.oFetchValue(fetch_value),
\t.oSetCurrentCircuit(set_current_circuit),
\t.oInsertValue(insert_value),
\t.oResetSerial(serial_reset)
);
memoria memoria(
\t.address(mem_addr ? sender_mem_addr : sampler_mem_addr),
\t.clock(CLOCK_50),
\t.data(genetico_out),
\t.wren(mem_write),
\t.q(mem_out)
);
data_receiver data_receiver(
\t.iClock(CLOCK_50),
\t.iReset(~KEY[1]),
\t.iRxDone(rx_done),
\t.iReceivedData(rs232_received_data),
\t.oResultData(received_data),
\t.oDoneReceiving(done_receiving)
);
uart rs232(
\t.sys_clk(CLOCK_50),
\t.sys_rst(~KEY[1] | serial_reset),
\t
\t.csr_a(14'b0),
\t.csr_we(tx_send),
\t.csr_di(data_to_send),
\t.csr_do(rs232_received_data),
\t
\t.rx_irq(rx_done),
\t.tx_irq(tx_done),
\t
\t.uart_rx(UART_RXD),
\t.uart_tx(UART_TXD)
);
genetico genetico(
\t.conf_les(current_circuit_les),
\t.conf_outs(current_circuit_outs),
\t.in(value_into_genetico),
\t.out(genetico_out)
);
endmodule
|
module sender(iClock, iReset, iTxDone, iStartSignal, oAddress, oFinished, oTxSend);
\tparameter IDLE = 3'b000,
\t\tSENDING = 3'b001,
\t\tSEND_PACKET = 3'b010, // So serve para fazer o pulso de envio.
\t\tSENDING_PACKET = 3'b011,
\t\tINCREMENTING_ADDR = 3'b100,
\t\tFINISHED_SENDING = 3'b101;
\t
\tinput iClock;
\tinput iReset;
\tinput iTxDone;
\tinput iStartSignal;
\toutput oTxSend;
\toutput oFinished;
\toutput [15:0] oAddress;
\t
\treg [2:0] state = IDLE;
\twire [2:0] next_state;
\t
\tassign next_state = fsm_function(state, oAddress, iTxDone, iStartSignal);
\t
\tfunction [2:0] fsm_function(input [2:0] state, input [15:0] current_address,
\t\tinput tx_done, input sampling_finished);
\t\tcase (state)
\t\tIDLE:
\t\t\tif (sampling_finished) begin
\t\t\t\tfsm_function = SENDING;
\t\t\tend else begin
\t\t\t\tfsm_function = IDLE;
\t\t\tend
\t\tSENDING:
\t\t\tif (current_address < 16'd100) begin
\t\t\t\tfsm_function = SEND_PACKET;
\t\t\tend else begin
\t\t\t\tfsm_function = FINISHED_SENDING; // Acabou de enviar os dados.
\t\t\tend
\t\tSEND_PACKET:
\t\t\tfsm_function = SENDING_PACKET;
\t\tSENDING_PACKET:
\t\t\tif (tx_done) begin
\t\t\t\tfsm_function = INCREMENTING_ADDR;
\t\t\tend else begin
\t\t\t\tfsm_function = SENDING_PACKET;
\t\t\tend
\t\tINCREMENTING_ADDR:
\t\t\tfsm_function = SENDING;
\t\tFINISHED_SENDING:
\t\t\tfsm_function = IDLE;
\t\tdefault:
\t\t\tfsm_function = IDLE;
\t\tendcase
\t\t
\tendfunction
always@ (posedge iClock) begin
\tif (iReset) begin
\t\tstate <= IDLE;
\tend else begin
\t\tstate <= next_state;
\tend
end
always@ (posedge iClock) begin
\toTxSend <= 0;
\toFinished <= 0;
\tcase (state)
\tIDLE: begin
\t\toAddress <= 16'h0;
\tend
\tSENDING: begin
\tend
\tSEND_PACKET: begin
\t\toTxSend <= 1;
\tend
\tSENDING_PACKET: begin
\tend
\tINCREMENTING_ADDR: begin
\t\toAddress <= oAddress + 16'b1;
\tend
\tFINISHED_SENDING: begin
\t\toFinished <= 1;
\tend
\tdefault: begin
\tend
\tendcase
end
\t
endmodule
|
LIBPOSTPROC_$MAJOR {
global: postproc_*; pp_*;
local: *;
};
|
LIBAVDEVICE_$MAJOR {
global: avdevice_*;
local: *;
};
|
LIBAVFORMAT_$MAJOR {
global: av*;
#FIXME those are for ffserver
ff_inet_aton;
ff_socket_nonblock;
ffm_set_write_index;
ffm_read_write_index;
ffm_write_write_index;
ff_mpegts_parse_close;
ff_mpegts_parse_open;
ff_mpegts_parse_packet;
ff_rtsp_parse_line;
ff_rtp_get_local_rtp_port;
ff_rtp_get_local_rtcp_port;
ffio_open_dyn_packet_buf;
ffio_set_buf_size;
ffurl_close;
ffurl_open;
ffurl_read_complete;
ffurl_seek;
ffurl_size;
ffurl_write;
ffurl_protocol_next;
url_open;
url_close;
url_write;
#those are deprecated, remove on next bump
url_*;
ff_timefilter_destroy;
ff_timefilter_new;
ff_timefilter_update;
ff_timefilter_reset;
get_*;
put_*;
ff_codec_get_id;
local: *;
};
|
LIBSWSCALE_$MAJOR {
global: swscale_*; sws_*;
local: *;
};
|
LIBAVCODEC_$MAJOR {
global: av*;
#deprecated, remove after next bump
audio_resample;
audio_resample_close;
dsputil_init;
ff_dsputil_init;
ff_find_pix_fmt;
ff_framenum_to_drop_timecode;
ff_framenum_to_smtpe_timecode;
ff_raw_pix_fmt_tags;
ff_init_smtpe_timecode;
ff_fft*;
ff_mdct*;
ff_dct*;
ff_rdft*;
ff_prores_idct_put_10_sse2;
ff_simple_idct*;
ff_aanscales;
ff_faan*;
ff_mmx_idct;
ff_fdct*;
fdct_ifast;
j_rev_dct;
ff_mmxext_idct;
ff_idct_xvid*;
ff_jpeg_fdct*;
#XBMC's configure checks for ff_vdpau_vc1_decode_picture()
ff_vdpau_vc1_decode_picture;
ff_dnxhd_get_cid_table;
ff_dnxhd_cid_table;
local: *;
};
|
LIBSWRESAMPLE_$MAJOR {
global: swr_*; ff_*; swresample_*;
local: *;
};
|
LIBAVUTIL_$MAJOR {
global: av*; ff_*;
local: *;
};
|
LIBAVFILTER_$MAJOR {
global: avfilter_*; av_*;
ff_default_query_formats;
local: *;
};
|
LIBAVRESAMPLE_$MAJOR {
global: av*;
local: *;
};
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
\tinput [31:0] x;
\toutput [31:0] y;
\tassign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
\tinput [31:0] x;
\toutput [31:0] y;
\tassign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
\tinput [31:0] x, y, z;
\toutput [31:0] o;
\tassign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
\tinput [31:0] x, y, z;
\toutput [31:0] o;
\tassign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
\tinput [31:0] x;
\toutput [31:0] y;
\tassign y[31:29] = x[6:4] ^ x[17:15];
\tassign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
\tinput [31:0] x;
\toutput [31:0] y;
\tassign y[31:22] = x[16:7] ^ x[18:9];
\tassign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
// A quick define to help index 32-bit words inside a larger register.
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
// Perform a SHA-256 transformation on the given 512-bit data, and 256-bit
// initial state,
// Outputs one 256-bit hash every LOOP cycle(s).
//
// The LOOP parameter determines both the size and speed of this module.
// A value of 1 implies a fully unrolled SHA-256 calculation spanning 64 round
// modules and calculating a full SHA-256 hash every clock cycle. A value of
// 2 implies a half-unrolled loop, with 32 round modules and calculating
// a full hash in 2 clock cycles. And so forth.
module sha256_transform #(
\tparameter LOOP = 6'd4
) (
\tinput clk,
\tinput feedback,
\tinput [5:0] cnt,
\tinput [255:0] rx_state,
\tinput [511:0] rx_input,
\toutput reg [255:0] tx_hash
);
\t// Constants defined by the SHA-2 standard.
\tlocalparam Ks = {
\t\t32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
\t\t32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
\t\t32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
\t\t32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
\t\t32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
\t\t32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
\t\t32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
\t\t32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
\t\t32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
\t\t32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
\t\t32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
\t\t32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
\t\t32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
\t\t32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
\t\t32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
\t\t32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2};
\tgenvar i;
\tgenerate
\t\tfor (i = 0; i < 64/LOOP; i = i + 1) begin : HASHERS
\t\t\twire [511:0] W;
\t\t\twire [255:0] state;
\t\t\tif(i == 0)
\t\t\t\tsha256_digester U (
\t\t\t\t\t.clk(clk),
\t\t\t\t\t.k(Ks[32*(63-cnt) +: 32]),
\t\t\t\t\t.rx_w(feedback ? W : rx_input),
\t\t\t\t\t.rx_state(feedback ? state : rx_state),
\t\t\t\t\t.tx_w(W),
\t\t\t\t\t.tx_state(state)
\t\t\t\t);
\t\t\telse
\t\t\t\tsha256_digester U (
\t\t\t\t\t.clk(clk),
\t\t\t\t\t.k(Ks[32*(63-LOOP*i-cnt) +: 32]),
\t\t\t\t\t.rx_w(feedback ? W : HASHERS[i-1].W),
\t\t\t\t\t.rx_state(feedback ? state : HASHERS[i-1].state),
\t\t\t\t\t.tx_w(W),
\t\t\t\t\t.tx_state(state)
\t\t\t\t);
\t\tend
\tendgenerate
\talways @ (posedge clk)
\tbegin
\t\tif (!feedback)
\t\tbegin
\t\t\ttx_hash[`IDX(0)] <= rx_state[`IDX(0)] + HASHERS[64/LOOP-6'd1].state[`IDX(0)];
\t\t\ttx_hash[`IDX(1)] <= rx_state[`IDX(1)] + HASHERS[64/LOOP-6'd1].state[`IDX(1)];
\t\t\ttx_hash[`IDX(2)] <= rx_state[`IDX(2)] + HASHERS[64/LOOP-6'd1].state[`IDX(2)];
\t\t\ttx_hash[`IDX(3)] <= rx_state[`IDX(3)] + HASHERS[64/LOOP-6'd1].state[`IDX(3)];
\t\t\ttx_hash[`IDX(4)] <= rx_state[`IDX(4)] + HASHERS[64/LOOP-6'd1].state[`IDX(4)];
\t\t\ttx_hash[`IDX(5)] <= rx_state[`IDX(5)] + HASHERS[64/LOOP-6'd1].state[`IDX(5)];
\t\t\ttx_hash[`IDX(6)] <= rx_state[`IDX(6)] + HASHERS[64/LOOP-6'd1].state[`IDX(6)];
\t\t\ttx_hash[`IDX(7)] <= rx_state[`IDX(7)] + HASHERS[64/LOOP-6'd1].state[`IDX(7)];
\t\tend
\tend
endmodule
module sha256_digester (clk, k, rx_w, rx_state, tx_w, tx_state);
\tinput clk;
\tinput [31:0] k;
\tinput [511:0] rx_w;
\tinput [255:0] rx_state;
\toutput reg [511:0] tx_w;
\toutput reg [255:0] tx_state;
\twire [31:0] e0_w, e1_w, ch_w, maj_w, s0_w, s1_w;
\te0\te0_blk\t(rx_state[`IDX(0)], e0_w);
\te1\te1_blk\t(rx_state[`IDX(4)], e1_w);
\tch\tch_blk\t(rx_state[`IDX(4)], rx_state[`IDX(5)], rx_state[`IDX(6)], ch_w);
\tmaj\tmaj_blk\t(rx_state[`IDX(0)], rx_state[`IDX(1)], rx_state[`IDX(2)], maj_w);
\ts0\ts0_blk\t(rx_w[63:32], s0_w);
\ts1\ts1_blk\t(rx_w[479:448], s1_w);
\twire [31:0] t1 = rx_state[`IDX(7)] + e1_w + ch_w + rx_w[31:0] + k;
\twire [31:0] t2 = e0_w + maj_w;
\twire [31:0] new_w = s1_w + rx_w[319:288] + s0_w + rx_w[31:0];
\t
\talways @ (posedge clk)
\tbegin
\t\ttx_w[511:480] <= new_w;
\t\ttx_w[479:0] <= rx_w[511:32];
\t\ttx_state[`IDX(7)] <= rx_state[`IDX(6)];
\t\ttx_state[`IDX(6)] <= rx_state[`IDX(5)];
\t\ttx_state[`IDX(5)] <= rx_state[`IDX(4)];
\t\ttx_state[`IDX(4)] <= rx_state[`IDX(3)] + t1;
\t\ttx_state[`IDX(3)] <= rx_state[`IDX(2)];
\t\ttx_state[`IDX(2)] <= rx_state[`IDX(1)];
\t\ttx_state[`IDX(1)] <= rx_state[`IDX(0)];
\t\ttx_state[`IDX(0)] <= t1 + t2;
\tend
endmodule
|
//`include "async_receiver.v"
//`include "async_transmitter.v"
// by teknohog, replaces virtual_wire by rs232
module serial_receive(clk, RxD, midstate, data2);
input clk;
input RxD;
wire RxD_data_ready;
wire [7:0] RxD_data;
async_receiver deserializer(.clk(clk), .RxD(RxD), .RxD_data_ready(RxD_data_ready), .RxD_data(RxD_data));
output [255:0] midstate;
output [255:0] data2;
// 256 bits midstate + 256 bits data at the same time = 64 bytes
// Might be a good idea to add some fixed start and stop sequences,
// so we really know we got all the data and nothing more. If a
// test for these fails, should ask for new data, so it needs more
// logic on the return side too. The check bits could be legible
// 7seg for quick feedback :)
reg [511:0] input_buffer;
reg [511:0] input_copy;
reg [6:0] demux_state = 7\'b0000000;
assign midstate = input_copy[511:256];
assign data2 = input_copy[255:0];
// we probably don\'t need a busy signal here, just read the latest
// complete input that is available.
always @(posedge clk)
case (demux_state)
7\'b1000000:
\t begin
\t input_copy <= input_buffer;
\t demux_state <= 0;
\t end
default:
\t if(RxD_data_ready)
\t begin
\t input_buffer <= input_buffer << 8;
\t input_buffer[7:0] <= RxD_data;
\t demux_state <= demux_state + 1;
\t end
endcase // case (demux_state)
endmodule // serial_receive
module serial_transmit (clk, TxD, busy, send, word);
// split 4-byte output into bytes
wire TxD_start;
wire TxD_busy;
reg [7:0] out_byte;
reg serial_start;
reg [3:0] mux_state = 4\'b0000;
assign TxD_start = serial_start;
input clk;
output TxD;
input [31:0] word;
input \tsend;
output \tbusy;
reg [31:0] \tword_copy;
assign busy = (|mux_state);
always @(posedge clk)
begin
\t/*
\tcase (mux_state)
\t 4\'b0000:
\t if (send)
\t begin
\t\t mux_state <= 4\'b1000;
\t\t word_copy <= word;
\t end
\t 4\'b1000: out_byte <= word_copy[31:24];
\t 4\'b1010: out_byte <= word_copy[23:16];
\t 4\'b1100: out_byte <= word_copy[15:8];
\t 4\'b1110: out_byte <= word_copy[7:0];
\t default: mux_state <= 4\'b0000;
\tendcase // case (mux_state)
\t */
\t// Testing for busy is problematic if we are keeping the
\t// module busy all the time :-/ So we need some wait stages
\t// between the bytes.
\tif (!busy && send)
\t begin
\t mux_state <= 4\'b1000;
\t word_copy <= word;
\t end
\telse if (mux_state[3] && ~mux_state[0] && !TxD_busy)
\t begin
\t serial_start <= 1;
\t mux_state <= mux_state + 1;
\t out_byte <= word_copy[31:24];
\t word_copy <= (word_copy << 8);
\t end
\t
\t// wait stages
\telse if (mux_state[3] && mux_state[0])
\t begin
\t serial_start <= 0;
\t if (!TxD_busy) mux_state <= mux_state + 1;
\t end
end
async_transmitter serializer(.clk(clk), .TxD(TxD), .TxD_start(TxD_start), .TxD_data(out_byte), .TxD_busy(TxD_busy));
endmodule // serial_send
|
// RS-232 RX module
// (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006
module async_receiver(clk, RxD, RxD_data_ready, RxD_data, RxD_endofpacket, RxD_idle);
input clk, RxD;
output RxD_data_ready; // onc clock pulse when RxD_data is valid
output [7:0] RxD_data;
parameter ClkFrequency = 80000000; // 25MHz
//parameter ClkFrequency = 25000000; // 25MHz
parameter Baud = 115200;
// We also detect if a gap occurs in the received stream of characters
// That can be useful if multiple characters are sent in burst
// so that multiple characters can be treated as a "packet"
output RxD_endofpacket; // one clock pulse, when no more data is received (RxD_idle is going high)
output RxD_idle; // no data is being received
// Baud generator (we use 8 times oversampling)
parameter Baud8 = Baud*8;
parameter Baud8GeneratorAccWidth = 16;
wire [Baud8GeneratorAccWidth:0] Baud8GeneratorInc = ((Baud8<<(Baud8GeneratorAccWidth-7))+(ClkFrequency>>8))/(ClkFrequency>>7);
reg [Baud8GeneratorAccWidth:0] Baud8GeneratorAcc;
always @(posedge clk) Baud8GeneratorAcc <= Baud8GeneratorAcc[Baud8GeneratorAccWidth-1:0] + Baud8GeneratorInc;
wire Baud8Tick = Baud8GeneratorAcc[Baud8GeneratorAccWidth];
////////////////////////////
reg [1:0] RxD_sync_inv;
always @(posedge clk) if(Baud8Tick) RxD_sync_inv <= {RxD_sync_inv[0], ~RxD};
// we invert RxD, so that the idle becomes "0", to prevent a phantom character to be received at startup
reg [1:0] RxD_cnt_inv;
reg RxD_bit_inv;
always @(posedge clk)
if(Baud8Tick)
begin
\tif( RxD_sync_inv[1] && RxD_cnt_inv!=2\'b11) RxD_cnt_inv <= RxD_cnt_inv + 2\'h1;
\telse
\tif(~RxD_sync_inv[1] && RxD_cnt_inv!=2\'b00) RxD_cnt_inv <= RxD_cnt_inv - 2\'h1;
\tif(RxD_cnt_inv==2\'b00) RxD_bit_inv <= 1\'b0;
\telse
\tif(RxD_cnt_inv==2\'b11) RxD_bit_inv <= 1\'b1;
end
reg [3:0] state;
reg [3:0] bit_spacing;
// "next_bit" controls when the data sampling occurs
// depending on how noisy the RxD is, different values might work better
// with a clean connection, values from 8 to 11 work
wire next_bit = (bit_spacing==4\'d10);
always @(posedge clk)
if(state==0)
\tbit_spacing <= 4\'b0000;
else
if(Baud8Tick)
\tbit_spacing <= {bit_spacing[2:0] + 4\'b0001} | {bit_spacing[3], 3\'b000};
always @(posedge clk)
if(Baud8Tick)
case(state)
\t4\'b0000: if(RxD_bit_inv) state <= 4\'b1000; // start bit found?
\t4\'b1000: if(next_bit) state <= 4\'b1001; // bit 0
\t4\'b1001: if(next_bit) state <= 4\'b1010; // bit 1
\t4\'b1010: if(next_bit) state <= 4\'b1011; // bit 2
\t4\'b1011: if(next_bit) state <= 4\'b1100; // bit 3
\t4\'b1100: if(next_bit) state <= 4\'b1101; // bit 4
\t4\'b1101: if(next_bit) state <= 4\'b1110; // bit 5
\t4\'b1110: if(next_bit) state <= 4\'b1111; // bit 6
\t4\'b1111: if(next_bit) state <= 4\'b0001; // bit 7
\t4\'b0001: if(next_bit) state <= 4\'b0000; // stop bit
\tdefault: state <= 4\'b0000;
endcase
reg [7:0] RxD_data;
always @(posedge clk)
if(Baud8Tick && next_bit && state[3]) RxD_data <= {~RxD_bit_inv, RxD_data[7:1]};
reg RxD_data_ready, RxD_data_error;
always @(posedge clk)
begin
\tRxD_data_ready <= (Baud8Tick && next_bit && state==4\'b0001 && ~RxD_bit_inv); // ready only if the stop bit is received
\tRxD_data_error <= (Baud8Tick && next_bit && state==4\'b0001 && RxD_bit_inv); // error if the stop bit is not received
end
reg [4:0] gap_count;
always @(posedge clk) if (state!=0) gap_count<=5\'h00; else if(Baud8Tick & ~gap_count[4]) gap_count <= gap_count + 5\'h01;
assign RxD_idle = gap_count[4];
reg RxD_endofpacket; always @(posedge clk) RxD_endofpacket <= Baud8Tick & (gap_count==5\'h0F);
endmodule
|
/*
* Milkyminer
*
* Copyright (c) 2011 [email protected]
* Copyleft 2012 [email protected]
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/1ps
module system(
\tinput clk50,
\t// UART
\tinput uart_rx,
\toutput uart_tx,
\t// GPIO
//\tinput btn1,
//\tinput btn2,
//\tinput btn3,
\toutput led1,
\toutput led2
\t// Exp miner
\t//output [EXT_PORTS-1:0] extminer_txd,
\t//input [EXT_PORTS-1:0] extminer_rxd,
\t// Expansion connector
//\tinput [11:0] exp
\t
\t//DIP
);
\t// The LOOP_LOG2 parameter determines how unrolled the SHA-256
\t// calculations are. For example, a setting of 1 will completely
\t// unroll the calculations, resulting in 128 rounds and a large, fast
\t// design.
\t//
\t// A setting of 2 will result in 64 rounds, with half the size and
\t// half the speed. 3 will be 32 rounds, with 1/4th the size and speed.
\t// And so on.
\t//
\t// Valid range: [0, 5]
`ifdef CONFIG_LOOP_LOG2
\tparameter LOOP_LOG2 = `CONFIG_LOOP_LOG2;
`else
\tparameter LOOP_LOG2 = 5;
`endif
\t// No need to adjust these parameters
\tlocalparam [5:0] LOOP = (6\'d1 << LOOP_LOG2);
\t// The nonce will always be larger at the time we discover a valid
\t// hash. This is its offset from the nonce that gave rise to the valid
\t// hash (except when LOOP_LOG2 == 0 or 1, where the offset is 131 or
\t// 66 respectively).
\tlocalparam [31:0] GOLDEN_NONCE_OFFSET = (32\'d1 << (7 - LOOP_LOG2)) + 32\'d1;
\t////
\treg [255:0] state = 0;
\treg [511:0] data = 0;
\treg [31:0] nonce = 32\'h00000000;
\t//// DCM
\twire hash_clk;
\twire hash_clk_dcm;
// \t50/5*8 = 80Mhz
\tDCM_SP #(
\t.CLKDV_DIVIDE(2.0),\t\t// 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
\t.CLKFX_DIVIDE(5),\t\t// 1 to 32
\t.CLKFX_MULTIPLY(8),\t\t// 2 to 32
\t.CLKIN_DIVIDE_BY_2("FALSE"),
\t.CLKIN_PERIOD(20.0),
\t.CLKOUT_PHASE_SHIFT("NONE"),
\t.CLK_FEEDBACK("NONE"),
\t.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
\t.DUTY_CYCLE_CORRECTION("TRUE"),
\t.PHASE_SHIFT(0),
\t.STARTUP_WAIT("TRUE")
) clkgen_hash (
\t.CLK0(),
\t.CLK90(),
\t.CLK180(),
\t.CLK270(),
\t.CLK2X(),
\t.CLK2X180(),
\t.CLKDV(),
\t.CLKFX(hash_clk_dcm),
\t.CLKFX180(),
\t.LOCKED(),
\t.CLKFB(),
\t.CLKIN(clk50),
\t.RST(1\'b0),
\t.PSEN(1\'b0)
);
BUFG b1(
\t.I(hash_clk_dcm),
\t.O(hash_clk)
);
\t//// Hashers
\twire [255:0] hash, hash2;
\treg [5:0] cnt = 6\'d0;
\treg feedback = 1\'b0;
\tsha256_transform #(.LOOP(LOOP)) uut (
\t\t.clk(hash_clk),
\t\t.feedback(feedback),
\t\t.cnt(cnt),
\t\t.rx_state(state),
\t\t.rx_input(data),
\t\t.tx_hash(hash)
\t);
\tsha256_transform #(.LOOP(LOOP)) uut2 (
\t\t.clk(hash_clk),
\t\t.feedback(feedback),
\t\t.cnt(cnt),
\t\t.rx_state(256\'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667),
\t\t.rx_input({256\'h0000010000000000000000000000000000000000000000000000000080000000, hash}),
\t\t.tx_hash(hash2)
\t);
\t//// Virtual Wire Control
\treg [255:0] midstate_buf = 0, data_buf = 0;
\twire [255:0] midstate_vw, data2_vw;
serial_receive serrx (.clk(hash_clk), .RxD(uart_rx), .midstate(midstate_vw), .data2(data2_vw));
\t//// Virtual Wire Output
\treg [31:0] golden_nonce = 0;
reg \t\t serial_send;
wire \t serial_busy;
serial_transmit sertx (.clk(hash_clk), .TxD(uart_tx), .send(serial_send), .busy(serial_busy), .word(golden_nonce));
\t//// Control Unit
\treg is_golden_ticket = 1\'b0;
\treg feedback_d1 = 1\'b1;
\twire [5:0] cnt_next;
\twire [31:0] nonce_next;
\twire feedback_next;
\twire reset;
\tassign reset = 1\'b0;
\tassign cnt_next = reset ? 6\'d0 : (LOOP == 1) ? 6\'d0 : (cnt + 6\'d1) & (LOOP-1);
\t// On the first count (cnt==0), load data from previous stage (no feedback)
\t// on 1..LOOP-1, take feedback from current stage
\t// This reduces the throughput by a factor of (LOOP), but also reduces the design size by the same amount
\tassign feedback_next = (LOOP == 1) ? 1\'b0 : (cnt_next != {(LOOP_LOG2){1\'b0}});
\tassign nonce_next =
\t\treset ? 32\'d0 :
\t\tfeedback_next ? nonce : (nonce + 32\'d1);
\t
\talways @ (posedge hash_clk)
\tbegin
\t\tmidstate_buf <= midstate_vw;
\t\tdata_buf <= data2_vw;
\t\tcnt <= cnt_next;
\t\tfeedback <= feedback_next;
\t\tfeedback_d1 <= feedback;
\t\t// Give new data to the hasher
\t\tstate <= midstate_buf;
\t\tdata <= {384\'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, nonce_next, data_buf[95:0]};
\t\tnonce <= nonce_next;
\t\t// Check to see if the last hash generated is valid.
\t\tis_golden_ticket <= (hash2[255:224] == 32\'h00000000) && !feedback_d1;
\t\tif(is_golden_ticket)
\t\tbegin
\t\t\t// TODO: Find a more compact calculation for this
\t\t\tif (LOOP == 1)
\t\t\t\tgolden_nonce <= nonce - 32\'d131;
\t\t\telse if (LOOP == 2)
\t\t\t\tgolden_nonce <= nonce - 32\'d66;
\t\t\telse
\t\t\t\tgolden_nonce <= nonce - GOLDEN_NONCE_OFFSET;
\t\t if (!serial_busy) serial_send <= 1;
\t\tend // if (is_golden_ticket)
\t\telse
\t\tserial_send <= 0;
\tend
/* debug led serial */
//assign led1 = ~uart_rx;
assign led1 = |golden_nonce;
assign led2 = ~uart_tx;
endmodule
|
// RS-232 TX module
// (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006
//`define DEBUG // in DEBUG mode, we output one bit per clock cycle (useful for faster simulations)
module async_transmitter(clk, TxD_start, TxD_data, TxD, TxD_busy);
input clk, TxD_start;
input [7:0] TxD_data;
output TxD, TxD_busy;
parameter ClkFrequency = 80000000;\t// 25MHz
parameter Baud = 115200;
parameter RegisterInputData = 1;\t// in RegisterInputData mode, the input doesn't have to stay valid while the character is been transmitted
// Baud generator
parameter BaudGeneratorAccWidth = 16;
reg [BaudGeneratorAccWidth:0] BaudGeneratorAcc;
`ifdef DEBUG
wire [BaudGeneratorAccWidth:0] BaudGeneratorInc = 17'h10000;
`else
wire [BaudGeneratorAccWidth:0] BaudGeneratorInc = ((Baud<<(BaudGeneratorAccWidth-4))+(ClkFrequency>>5))/(ClkFrequency>>4);
`endif
wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth];
wire TxD_busy;
always @(posedge clk) if(TxD_busy) BaudGeneratorAcc <= BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc;
// Transmitter state machine
reg [3:0] state;
wire TxD_ready = (state==0);
assign TxD_busy = ~TxD_ready;
reg [7:0] TxD_dataReg;
always @(posedge clk) if(TxD_ready & TxD_start) TxD_dataReg <= TxD_data;
wire [7:0] TxD_dataD = RegisterInputData ? TxD_dataReg : TxD_data;
always @(posedge clk)
case(state)
\t4'b0000: if(TxD_start) state <= 4'b0001;
\t4'b0001: if(BaudTick) state <= 4'b0100;
\t4'b0100: if(BaudTick) state <= 4'b1000; // start
\t4'b1000: if(BaudTick) state <= 4'b1001; // bit 0
\t4'b1001: if(BaudTick) state <= 4'b1010; // bit 1
\t4'b1010: if(BaudTick) state <= 4'b1011; // bit 2
\t4'b1011: if(BaudTick) state <= 4'b1100; // bit 3
\t4'b1100: if(BaudTick) state <= 4'b1101; // bit 4
\t4'b1101: if(BaudTick) state <= 4'b1110; // bit 5
\t4'b1110: if(BaudTick) state <= 4'b1111; // bit 6
\t4'b1111: if(BaudTick) state <= 4'b0010; // bit 7
\t4'b0010: if(BaudTick) state <= 4'b0011; // stop1
\t4'b0011: if(BaudTick) state <= 4'b0000; // stop2
\tdefault: if(BaudTick) state <= 4'b0000;
endcase
// Output mux
reg muxbit;
always @( * )
case(state[2:0])
\t3'd0: muxbit <= TxD_dataD[0];
\t3'd1: muxbit <= TxD_dataD[1];
\t3'd2: muxbit <= TxD_dataD[2];
\t3'd3: muxbit <= TxD_dataD[3];
\t3'd4: muxbit <= TxD_dataD[4];
\t3'd5: muxbit <= TxD_dataD[5];
\t3'd6: muxbit <= TxD_dataD[6];
\t3'd7: muxbit <= TxD_dataD[7];
endcase
// Put together the start, data and stop bits
reg TxD;
always @(posedge clk) TxD <= (state<4) | (state[3] & muxbit); // register the output to make it glitch free
endmodule
|
module main;
initial
begin
$display("Hello, World");
$finish ;
end
endmodule
|
module top (
\tinput clk,
\toutput LED0,
\toutput LED1,
\toutput LED2,
\toutput LED3,
\toutput LED4,
\toutput LED5,
\toutput LED6,
\toutput LED7
);
\tlocalparam BITS = 5;
\tlocalparam LOG2DELAY = 22;
\treg [BITS+LOG2DELAY-1:0] counter = 0;
\treg out_led = 0;
\talways@(posedge clk) begin
\t\tif (counter == 1000000) begin
\t\t\tout_led <= out_led ^ 1;
\t\t\tcounter <= 0;
\t\tend
\t\telse
\t\tbegin
\t\t\tcounter <= counter + 1;
\t\tend
\tend
\tassign {LED0, LED1, LED2, LED3, LED4, LED5, LED6} = ~0;
\tassign LED7 = out_led;
endmodule
|
module top (
\tinput clk,
\toutput LED1,
\toutput LED2,
\toutput LED3,
\toutput LED4,
\toutput LED5
);
\tlocalparam BITS = 5;
\tlocalparam LOG2DELAY = 22;
\treg [BITS+LOG2DELAY-1:0] counter = 0;
\treg out_led = 0;
\talways@(posedge clk) begin
\t\tif (counter == 1000000) begin
\t\t\tout_led <= out_led ^ 1;
\t\t\tcounter <= 0;
\t\tend
\t\telse
\t\tbegin
\t\t\tcounter <= counter + 1;
\t\tend
\tend
\tassign {LED1, LED2, LED3, LED4} = 15;
\tassign LED5 = out_led;
endmodule
|
module simple(A, B);
input [3:0] A;
output [3:0] B;
// mix up the input bits
assign B = { A[0], A[2], A[1], A[3] };
endmodule
|
module simple_tb;
reg [3:0] A = 4\'b1010;
wire [3:0] B;
initial
begin
$dumpfile("waveform.vcd");
$dumpvars(0, s);
$monitor("A is %b, B is %b.", A, B);
#50 A = 4\'b1100;
#50 $finish;
end
simple s(A, B);
endmodule
|
module algo (clock, in1, in2, in3, past_data, out);
input wire in1, in2, in3;
input wire [31:0] past_data;
output reg out;
reg result;
always @(posedge clock) begin
// use a complex algorithm to set reg result based on in1, in2, in3, and past_data
out = result;
end
endmodule
|
module d_latch (e, d, q, q_not);
// Since we didn't specify widths, each of these registers is 1 bit wide
input wire e, d; // e and d are input wires (nets)
output reg q, q_not; // q and q_not are output registers
always @(posedge e) begin // On each positive edge of the input e,
q = d; // set q to the value of d
q_not = ~d; // and d to the bitwise negation of d
end
endmodule
|
module triple_and (clock, in1, in2, in3, out);
input wire in1, in2, in3;
output reg out;
assign out = in1 & in2 & in3;
endmodule
|
always @(negedge reset or posedge clk) begin
if (reset == 0) begin
d_out <= 16'h0000;
d_out_mem[resetcount] <= d_out;
laststoredvalue <= d_out;
end else begin
d_out <= d_out + 1'b1;
end
end
always @(bufreadaddr)
bufreadval = d_out_mem[bufreadaddr];
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_comparator_sel #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] V,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}};
assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = V;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1\'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1\'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: wdata_router.v
//
// Description:
// Contains SI-side write command queue.
// Target MI-slot index is pushed onto queue when S_AVALID transfer is received.
// Queue is popped when WLAST data beat is transferred.
// W-channel input is transferred to MI-slot output selected by queue output.
//--------------------------------------------------------------------------
//
// Structure:
// wdata_router
// axic_reg_srl_fifo
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_wdata_router #
(
parameter C_FAMILY = "none", // FPGA Family.
parameter integer C_WMESG_WIDTH = 1, // Width of all data signals
parameter integer C_NUM_MASTER_SLOTS = 1, // Number of M_* ports.
parameter integer C_SELECT_WIDTH = 1, // Width of S_ASELECT.
parameter integer C_FIFO_DEPTH_LOG = 0 // Queue depth = 2**C_FIFO_DEPTH_LOG.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave Data Ports
input wire [C_WMESG_WIDTH-1:0] S_WMESG,
input wire S_WLAST,
input wire S_WVALID,
output wire S_WREADY,
// Master Data Ports
output wire [C_WMESG_WIDTH-1:0] M_WMESG, // Broadcast to all MI-slots
output wire M_WLAST, // Broadcast to all MI-slots
output wire [C_NUM_MASTER_SLOTS-1:0] M_WVALID, // Per MI-slot
input wire [C_NUM_MASTER_SLOTS-1:0] M_WREADY, // Per MI-slot
// Address Arbiter Ports
input wire [C_SELECT_WIDTH-1:0] S_ASELECT, // Target MI-slot index from SI-side AW command
input wire S_AVALID,
output wire S_AREADY
);
localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5; // Max depth = 32
// Decode select input to 1-hot
function [C_NUM_MASTER_SLOTS-1:0] f_decoder (
input [C_SELECT_WIDTH-1:0] sel
);
integer i;
begin
for (i=0; i<C_NUM_MASTER_SLOTS; i=i+1) begin
f_decoder[i] = (sel == i);
end
end
endfunction
//---------------------------------------------------------------------------
// Internal signal declarations
//---------------------------------------------------------------------------
wire [C_NUM_MASTER_SLOTS-1:0] m_select_hot;
wire [C_SELECT_WIDTH-1:0] m_select_enc;
wire m_avalid;
wire m_aready;
//---------------------------------------------------------------------------
// Router
//---------------------------------------------------------------------------
// SI-side write command queue
axi_data_fifo_v2_1_axic_reg_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (C_SELECT_WIDTH),
.C_FIFO_DEPTH_LOG (P_FIFO_DEPTH_LOG),
.C_USE_FULL (1)
)
wrouter_aw_fifo
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (S_ASELECT),
.S_VALID (S_AVALID),
.S_READY (S_AREADY),
.M_MESG (m_select_enc),
.M_VALID (m_avalid),
.M_READY (m_aready)
);
assign m_select_hot = f_decoder(m_select_enc);
// W-channel payload and LAST are broadcast to all MI-slot\'s W-mux
assign M_WMESG = S_WMESG;
assign M_WLAST = S_WLAST;
// Assert m_aready when last beat acknowledged by slave
assign m_aready = m_avalid & S_WVALID & S_WLAST & (|(M_WREADY & m_select_hot));
// M_WVALID is generated per MI-slot (including error handler at slot C_NUM_MASTER_SLOTS).
// The slot selected by the head of the queue (m_select_enc) is enabled.
assign M_WVALID = {C_NUM_MASTER_SLOTS{S_WVALID & m_avalid}} & m_select_hot;
// S_WREADY is muxed from the MI slot selected by the head of the queue (m_select_enc).
assign S_WREADY = m_avalid & (|(M_WREADY & m_select_hot));
endmodule
`default_nettype wire
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Data AXI3 Slave Converter
// Forward and split transactions as required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// w_axi3_conv
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_w_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_SUPPORT_SPLITTING = 1,
// Implement transaction splitting logic.
// Disabled whan all connected masters are AXI3 and have same or narrower data width.
parameter integer C_SUPPORT_BURSTS = 1
// Disabled when all connected masters are AxiLite,
// allowing logic to be simplified.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Command Interface
input wire cmd_valid,
input wire [C_AXI_ID_WIDTH-1:0] cmd_id,
input wire [4-1:0] cmd_length,
output wire cmd_ready,
// Slave Interface Write Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Burst length handling.
reg first_mi_word;
reg [8-1:0] length_counter_1;
reg [8-1:0] length_counter;
wire [8-1:0] next_length_counter;
wire last_beat;
wire last_word;
// Throttling help signals.
wire cmd_ready_i;
wire pop_mi_data;
wire mi_stalling;
// Internal SI side control signals.
wire S_AXI_WREADY_I;
// Internal signals for MI-side.
wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID_I;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_I;
wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_I;
wire M_AXI_WLAST_I;
wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER_I;
wire M_AXI_WVALID_I;
wire M_AXI_WREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// Forward data from SI-Side to MI-Side while a command is available. When
// the transaction has completed the command is popped from the Command FIFO.
//
/////////////////////////////////////////////////////////////////////////////
// Pop word from SI-side.
assign S_AXI_WREADY_I = S_AXI_WVALID & cmd_valid & ~mi_stalling;
assign S_AXI_WREADY = S_AXI_WREADY_I;
// Indicate when there is data available @ MI-side.
assign M_AXI_WVALID_I = S_AXI_WVALID & cmd_valid;
// Get MI-side data.
assign pop_mi_data = M_AXI_WVALID_I & M_AXI_WREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_mi_data & last_word;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign mi_stalling = M_AXI_WVALID_I & ~M_AXI_WREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Keep track of data forwarding:
//
// On the first cycle of the transaction is the length taken from the Command
// FIFO. The length is decreased until 0 is reached which indicates last data
// word.
//
// If bursts are unsupported will all data words be the last word, each one
// from a separate transaction.
//
/////////////////////////////////////////////////////////////////////////////
// Select command length or counted length.
always @ *
begin
if ( first_mi_word )
length_counter = cmd_length;
else
length_counter = length_counter_1;
end
// Calculate next length counter value.
assign next_length_counter = length_counter - 1\'b1;
// Keep track of burst length.
always @ (posedge ACLK) begin
if (ARESET) begin
first_mi_word <= 1\'b1;
length_counter_1 <= 4\'b0;
end else begin
if ( pop_mi_data ) begin
if ( M_AXI_WLAST_I ) begin
first_mi_word <= 1\'b1;
end else begin
first_mi_word <= 1\'b0;
end
length_counter_1 <= next_length_counter;
end
end
end
// Detect last beat in a burst.
assign last_beat = ( length_counter == 4\'b0 );
// Determine if this last word that shall be extracted from this SI-side word.
assign last_word = ( last_beat ) |
( C_SUPPORT_BURSTS == 0 );
/////////////////////////////////////////////////////////////////////////////
// Select the SI-side word to write.
//
// Most information can be reused directly (DATA, STRB, ID and USER).
// ID is taken from the Command FIFO.
//
// Split transactions needs to insert new LAST transactions. So to simplify
// is the LAST signal always generated.
//
/////////////////////////////////////////////////////////////////////////////
// ID and USER is copied from the SI word to all MI word transactions.
assign M_AXI_WUSER_I = ( C_AXI_SUPPORTS_USER_SIGNALS ) ? S_AXI_WUSER : {C_AXI_WUSER_WIDTH{1\'b0}};
// Data has to be multiplexed.
assign M_AXI_WDATA_I = S_AXI_WDATA;
assign M_AXI_WSTRB_I = S_AXI_WSTRB;
// ID is taken directly from the command queue.
assign M_AXI_WID_I = cmd_id;
// Handle last flag, i.e. set for MI-side last word.
assign M_AXI_WLAST_I = last_word;
/////////////////////////////////////////////////////////////////////////////
// MI-side output handling
//
/////////////////////////////////////////////////////////////////////////////
// TODO: registered?
assign M_AXI_WID = M_AXI_WID_I;
assign M_AXI_WDATA = M_AXI_WDATA_I;
assign M_AXI_WSTRB = M_AXI_WSTRB_I;
assign M_AXI_WLAST = M_AXI_WLAST_I;
assign M_AXI_WUSER = M_AXI_WUSER_I;
assign M_AXI_WVALID = M_AXI_WVALID_I;
assign M_AXI_WREADY_I = M_AXI_WREADY;
endmodule
|
// -- (c) Copyright 2012 -2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: axi_protocol_converter.v
//
// Description:
// This module is a bank of AXI4-Lite and AXI3 protocol converters for a vectored AXI interface.
// The interface of this module consists of a vectored slave and master interface
// which are each concatenations of upper-level AXI pathways,
// plus various vectored parameters.
// This module instantiates a set of individual protocol converter modules.
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_axi_protocol_converter #(
parameter C_FAMILY = "virtex6",
parameter integer C_M_AXI_PROTOCOL = 0,
parameter integer C_S_AXI_PROTOCOL = 0,
parameter integer C_IGNORE_ID = 0,
// 0 = RID/BID are stored by axilite_conv.
// 1 = RID/BID have already been stored in an upstream device, like SASD crossbar.
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
// 1 = Propagate all USER signals, 0 = Don\x92t propagate.
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_TRANSLATION_MODE = 1
// 0 (Unprotected) = Disable all error checking; master is well-behaved.
// 1 (Protection) = Detect SI transaction violations, but perform no splitting.
// AXI4 -> AXI3 must be <= 16 beats; AXI4/3 -> AXI4LITE must be single.
// 2 (Conversion) = Include transaction splitting logic
) (
// Global Signals
input wire aclk,
input wire aresetn,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [((C_S_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [((C_S_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_M_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_M_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_M_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_M_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input wire m_axi_rvalid,
output wire m_axi_rready
);
localparam P_AXI4 = 32\'h0;
localparam P_AXI3 = 32\'h1;
localparam P_AXILITE = 32\'h2;
localparam P_AXILITE_SIZE = (C_AXI_DATA_WIDTH == 32) ? 3\'b010 : 3\'b011;
localparam P_INCR = 2\'b01;
localparam P_DECERR = 2\'b11;
localparam P_SLVERR = 2\'b10;
localparam integer P_PROTECTION = 1;
localparam integer P_CONVERSION = 2;
wire s_awvalid_i;
wire s_arvalid_i;
wire s_wvalid_i ;
wire s_bready_i ;
wire s_rready_i ;
wire s_awready_i;
wire s_wready_i;
wire s_bvalid_i;
wire [C_AXI_ID_WIDTH-1:0] s_bid_i;
wire [1:0] s_bresp_i;
wire [C_AXI_BUSER_WIDTH-1:0] s_buser_i;
wire s_arready_i;
wire s_rvalid_i;
wire [C_AXI_ID_WIDTH-1:0] s_rid_i;
wire [1:0] s_rresp_i;
wire [C_AXI_RUSER_WIDTH-1:0] s_ruser_i;
wire [C_AXI_DATA_WIDTH-1:0] s_rdata_i;
wire s_rlast_i;
generate
if ((C_M_AXI_PROTOCOL == P_AXILITE) || (C_S_AXI_PROTOCOL == P_AXILITE)) begin : gen_axilite
assign m_axi_awid = 0;
assign m_axi_awlen = 0;
assign m_axi_awsize = P_AXILITE_SIZE;
assign m_axi_awburst = P_INCR;
assign m_axi_awlock = 0;
assign m_axi_awcache = 0;
assign m_axi_awregion = 0;
assign m_axi_awqos = 0;
assign m_axi_awuser = 0;
assign m_axi_wid = 0;
assign m_axi_wlast = 1\'b1;
assign m_axi_wuser = 0;
assign m_axi_arid = 0;
assign m_axi_arlen = 0;
assign m_axi_arsize = P_AXILITE_SIZE;
assign m_axi_arburst = P_INCR;
assign m_axi_arlock = 0;
assign m_axi_arcache = 0;
assign m_axi_arregion = 0;
assign m_axi_arqos = 0;
assign m_axi_aruser = 0;
if (((C_IGNORE_ID == 1) && (C_TRANSLATION_MODE != P_CONVERSION)) || (C_S_AXI_PROTOCOL == P_AXILITE)) begin : gen_axilite_passthru
assign m_axi_awaddr = s_axi_awaddr;
assign m_axi_awprot = s_axi_awprot;
assign m_axi_awvalid = s_awvalid_i;
assign s_awready_i = m_axi_awready;
assign m_axi_wdata = s_axi_wdata;
assign m_axi_wstrb = s_axi_wstrb;
assign m_axi_wvalid = s_wvalid_i;
assign s_wready_i = m_axi_wready;
assign s_bid_i = 0;
assign s_bresp_i = m_axi_bresp;
assign s_buser_i = 0;
assign s_bvalid_i = m_axi_bvalid;
assign m_axi_bready = s_bready_i;
assign m_axi_araddr = s_axi_araddr;
assign m_axi_arprot = s_axi_arprot;
assign m_axi_arvalid = s_arvalid_i;
assign s_arready_i = m_axi_arready;
assign s_rid_i = 0;
assign s_rdata_i = m_axi_rdata;
assign s_rresp_i = m_axi_rresp;
assign s_rlast_i = 1\'b1;
assign s_ruser_i = 0;
assign s_rvalid_i = m_axi_rvalid;
assign m_axi_rready = s_rready_i;
end else if (C_TRANSLATION_MODE == P_CONVERSION) begin : gen_b2s_conv
assign s_buser_i = {C_AXI_BUSER_WIDTH{1\'b0}};
assign s_ruser_i = {C_AXI_RUSER_WIDTH{1\'b0}};
axi_protocol_converter_v2_1_b2s #(
.C_S_AXI_PROTOCOL (C_S_AXI_PROTOCOL),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_WRITE (C_AXI_SUPPORTS_WRITE),
.C_AXI_SUPPORTS_READ (C_AXI_SUPPORTS_READ)
) axilite_b2s (
.aresetn (aresetn),
.aclk (aclk),
.s_axi_awid (s_axi_awid),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awlen (s_axi_awlen),
.s_axi_awsize (s_axi_awsize),
.s_axi_awburst (s_axi_awburst),
.s_axi_awprot (s_axi_awprot),
.s_axi_awvalid (s_awvalid_i),
.s_axi_awready (s_awready_i),
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wlast (s_axi_wlast),
.s_axi_wvalid (s_wvalid_i),
.s_axi_wready (s_wready_i),
.s_axi_bid (s_bid_i),
.s_axi_bresp (s_bresp_i),
.s_axi_bvalid (s_bvalid_i),
.s_axi_bready (s_bready_i),
.s_axi_arid (s_axi_arid),
.s_axi_araddr (s_axi_araddr),
.s_axi_arlen (s_axi_arlen),
.s_axi_arsize (s_axi_arsize),
.s_axi_arburst (s_axi_arburst),
.s_axi_arprot (s_axi_arprot),
.s_axi_arvalid (s_arvalid_i),
.s_axi_arready (s_arready_i),
.s_axi_rid (s_rid_i),
.s_axi_rdata (s_rdata_i),
.s_axi_rresp (s_rresp_i),
.s_axi_rlast (s_rlast_i),
.s_axi_rvalid (s_rvalid_i),
.s_axi_rready (s_rready_i),
.m_axi_awaddr (m_axi_awaddr),
.m_axi_awprot (m_axi_awprot),
.m_axi_awvalid (m_axi_awvalid),
.m_axi_awready (m_axi_awready),
.m_axi_wdata (m_axi_wdata),
.m_axi_wstrb (m_axi_wstrb),
.m_axi_wvalid (m_axi_wvalid),
.m_axi_wready (m_axi_wready),
.m_axi_bresp (m_axi_bresp),
.m_axi_bvalid (m_axi_bvalid),
.m_axi_bready (m_axi_bready),
.m_axi_araddr (m_axi_araddr),
.m_axi_arprot (m_axi_arprot),
.m_axi_arvalid (m_axi_arvalid),
.m_axi_arready (m_axi_arready),
.m_axi_rdata (m_axi_rdata),
.m_axi_rresp (m_axi_rresp),
.m_axi_rvalid (m_axi_rvalid),
.m_axi_rready (m_axi_rready)
);
end else begin : gen_axilite_conv
axi_protocol_converter_v2_1_axilite_conv #(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_WRITE (C_AXI_SUPPORTS_WRITE),
.C_AXI_SUPPORTS_READ (C_AXI_SUPPORTS_READ),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH)
) axilite_conv_inst (
.ARESETN (aresetn),
.ACLK (aclk),
.S_AXI_AWID (s_axi_awid),
.S_AXI_AWADDR (s_axi_awaddr),
.S_AXI_AWPROT (s_axi_awprot),
.S_AXI_AWVALID (s_awvalid_i),
.S_AXI_AWREADY (s_awready_i),
.S_AXI_WDATA (s_axi_wdata),
.S_AXI_WSTRB (s_axi_wstrb),
.S_AXI_WVALID (s_wvalid_i),
.S_AXI_WREADY (s_wready_i),
.S_AXI_BID (s_bid_i),
.S_AXI_BRESP (s_bresp_i),
.S_AXI_BUSER (s_buser_i),
.S_AXI_BVALID (s_bvalid_i),
.S_AXI_BREADY (s_bready_i),
.S_AXI_ARID (s_axi_arid),
.S_AXI_ARADDR (s_axi_araddr),
.S_AXI_ARPROT (s_axi_arprot),
.S_AXI_ARVALID (s_arvalid_i),
.S_AXI_ARREADY (s_arready_i),
.S_AXI_RID (s_rid_i),
.S_AXI_RDATA (s_rdata_i),
.S_AXI_RRESP (s_rresp_i),
.S_AXI_RLAST (s_rlast_i),
.S_AXI_RUSER (s_ruser_i),
.S_AXI_RVALID (s_rvalid_i),
.S_AXI_RREADY (s_rready_i),
.M_AXI_AWADDR (m_axi_awaddr),
.M_AXI_AWPROT (m_axi_awprot),
.M_AXI_AWVALID (m_axi_awvalid),
.M_AXI_AWREADY (m_axi_awready),
.M_AXI_WDATA (m_axi_wdata),
.M_AXI_WSTRB (m_axi_wstrb),
.M_AXI_WVALID (m_axi_wvalid),
.M_AXI_WREADY (m_axi_wready),
.M_AXI_BRESP (m_axi_bresp),
.M_AXI_BVALID (m_axi_bvalid),
.M_AXI_BREADY (m_axi_bready),
.M_AXI_ARADDR (m_axi_araddr),
.M_AXI_ARPROT (m_axi_arprot),
.M_AXI_ARVALID (m_axi_arvalid),
.M_AXI_ARREADY (m_axi_arready),
.M_AXI_RDATA (m_axi_rdata),
.M_AXI_RRESP (m_axi_rresp),
.M_AXI_RVALID (m_axi_rvalid),
.M_AXI_RREADY (m_axi_rready)
);
end
end else if ((C_M_AXI_PROTOCOL == P_AXI3) && (C_S_AXI_PROTOCOL == P_AXI4)) begin : gen_axi4_axi3
axi_protocol_converter_v2_1_axi3_conv #(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_AXI_SUPPORTS_WRITE (C_AXI_SUPPORTS_WRITE),
.C_AXI_SUPPORTS_READ (C_AXI_SUPPORTS_READ),
.C_SUPPORT_SPLITTING ((C_TRANSLATION_MODE == P_CONVERSION) ? 1 : 0)
) axi3_conv_inst (
.ARESETN (aresetn),
.ACLK (aclk),
.S_AXI_AWID (s_axi_awid),
.S_AXI_AWADDR (s_axi_awaddr),
.S_AXI_AWLEN (s_axi_awlen),
.S_AXI_AWSIZE (s_axi_awsize),
.S_AXI_AWBURST (s_axi_awburst),
.S_AXI_AWLOCK (s_axi_awlock),
.S_AXI_AWCACHE (s_axi_awcache),
.S_AXI_AWPROT (s_axi_awprot),
.S_AXI_AWQOS (s_axi_awqos),
.S_AXI_AWUSER (s_axi_awuser),
.S_AXI_AWVALID (s_awvalid_i),
.S_AXI_AWREADY (s_awready_i),
.S_AXI_WDATA (s_axi_wdata),
.S_AXI_WSTRB (s_axi_wstrb),
.S_AXI_WLAST (s_axi_wlast),
.S_AXI_WUSER (s_axi_wuser),
.S_AXI_WVALID (s_wvalid_i),
.S_AXI_WREADY (s_wready_i),
.S_AXI_BID (s_bid_i),
.S_AXI_BRESP (s_bresp_i),
.S_AXI_BUSER (s_buser_i),
.S_AXI_BVALID (s_bvalid_i),
.S_AXI_BREADY (s_bready_i),
.S_AXI_ARID (s_axi_arid),
.S_AXI_ARADDR (s_axi_araddr),
.S_AXI_ARLEN (s_axi_arlen),
.S_AXI_ARSIZE (s_axi_arsize),
.S_AXI_ARBURST (s_axi_arburst),
.S_AXI_ARLOCK (s_axi_arlock),
.S_AXI_ARCACHE (s_axi_arcache),
.S_AXI_ARPROT (s_axi_arprot),
.S_AXI_ARQOS (s_axi_arqos),
.S_AXI_ARUSER (s_axi_aruser),
.S_AXI_ARVALID (s_arvalid_i),
.S_AXI_ARREADY (s_arready_i),
.S_AXI_RID (s_rid_i),
.S_AXI_RDATA (s_rdata_i),
.S_AXI_RRESP (s_rresp_i),
.S_AXI_RLAST (s_rlast_i),
.S_AXI_RUSER (s_ruser_i),
.S_AXI_RVALID (s_rvalid_i),
.S_AXI_RREADY (s_rready_i),
.M_AXI_AWID (m_axi_awid),
.M_AXI_AWADDR (m_axi_awaddr),
.M_AXI_AWLEN (m_axi_awlen),
.M_AXI_AWSIZE (m_axi_awsize),
.M_AXI_AWBURST (m_axi_awburst),
.M_AXI_AWLOCK (m_axi_awlock),
.M_AXI_AWCACHE (m_axi_awcache),
.M_AXI_AWPROT (m_axi_awprot),
.M_AXI_AWQOS (m_axi_awqos),
.M_AXI_AWUSER (m_axi_awuser),
.M_AXI_AWVALID (m_axi_awvalid),
.M_AXI_AWREADY (m_axi_awready),
.M_AXI_WID (m_axi_wid),
.M_AXI_WDATA (m_axi_wdata),
.M_AXI_WSTRB (m_axi_wstrb),
.M_AXI_WLAST (m_axi_wlast),
.M_AXI_WUSER (m_axi_wuser),
.M_AXI_WVALID (m_axi_wvalid),
.M_AXI_WREADY (m_axi_wready),
.M_AXI_BID (m_axi_bid),
.M_AXI_BRESP (m_axi_bresp),
.M_AXI_BUSER (m_axi_buser),
.M_AXI_BVALID (m_axi_bvalid),
.M_AXI_BREADY (m_axi_bready),
.M_AXI_ARID (m_axi_arid),
.M_AXI_ARADDR (m_axi_araddr),
.M_AXI_ARLEN (m_axi_arlen),
.M_AXI_ARSIZE (m_axi_arsize),
.M_AXI_ARBURST (m_axi_arburst),
.M_AXI_ARLOCK (m_axi_arlock),
.M_AXI_ARCACHE (m_axi_arcache),
.M_AXI_ARPROT (m_axi_arprot),
.M_AXI_ARQOS (m_axi_arqos),
.M_AXI_ARUSER (m_axi_aruser),
.M_AXI_ARVALID (m_axi_arvalid),
.M_AXI_ARREADY (m_axi_arready),
.M_AXI_RID (m_axi_rid),
.M_AXI_RDATA (m_axi_rdata),
.M_AXI_RRESP (m_axi_rresp),
.M_AXI_RLAST (m_axi_rlast),
.M_AXI_RUSER (m_axi_ruser),
.M_AXI_RVALID (m_axi_rvalid),
.M_AXI_RREADY (m_axi_rready)
);
assign m_axi_awregion = 0;
assign m_axi_arregion = 0;
end else if ((C_S_AXI_PROTOCOL == P_AXI3) && (C_M_AXI_PROTOCOL == P_AXI4)) begin : gen_axi3_axi4
assign m_axi_awid = s_axi_awid;
assign m_axi_awaddr = s_axi_awaddr;
assign m_axi_awlen = {4\'h0, s_axi_awlen[3:0]};
assign m_axi_awsize = s_axi_awsize;
assign m_axi_awburst = s_axi_awburst;
assign m_axi_awlock = s_axi_awlock[0];
assign m_axi_awcache = s_axi_awcache;
assign m_axi_awprot = s_axi_awprot;
assign m_axi_awregion = 4\'h0;
assign m_axi_awqos = s_axi_awqos;
assign m_axi_awuser = s_axi_awuser;
assign m_axi_awvalid = s_awvalid_i;
assign s_awready_i = m_axi_awready;
assign m_axi_wid = {C_AXI_ID_WIDTH{1\'b0}} ;
assign m_axi_wdata = s_axi_wdata;
assign m_axi_wstrb = s_axi_wstrb;
assign m_axi_wlast = s_axi_wlast;
assign m_axi_wuser = s_axi_wuser;
assign m_axi_wvalid = s_wvalid_i;
assign s_wready_i = m_axi_wready;
assign s_bid_i = m_axi_bid;
assign s_bresp_i = m_axi_bresp;
assign s_buser_i = m_axi_buser;
assign s_bvalid_i = m_axi_bvalid;
assign m_axi_bready = s_bready_i;
assign m_axi_arid = s_axi_arid;
assign m_axi_araddr = s_axi_araddr;
assign m_axi_arlen = {4\'h0, s_axi_arlen[3:0]};
assign m_axi_arsize = s_axi_arsize;
assign m_axi_arburst = s_axi_arburst;
assign m_axi_arlock = s_axi_arlock[0];
assign m_axi_arcache = s_axi_arcache;
assign m_axi_arprot = s_axi_arprot;
assign m_axi_arregion = 4\'h0;
assign m_axi_arqos = s_axi_arqos;
assign m_axi_aruser = s_axi_aruser;
assign m_axi_arvalid = s_arvalid_i;
assign s_arready_i = m_axi_arready;
assign s_rid_i = m_axi_rid;
assign s_rdata_i = m_axi_rdata;
assign s_rresp_i = m_axi_rresp;
assign s_rlast_i = m_axi_rlast;
assign s_ruser_i = m_axi_ruser;
assign s_rvalid_i = m_axi_rvalid;
assign m_axi_rready = s_rready_i;
end else begin :gen_no_conv
assign m_axi_awid = s_axi_awid;
assign m_axi_awaddr = s_axi_awaddr;
assign m_axi_awlen = s_axi_awlen;
assign m_axi_awsize = s_axi_awsize;
assign m_axi_awburst = s_axi_awburst;
assign m_axi_awlock = s_axi_awlock;
assign m_axi_awcache = s_axi_awcache;
assign m_axi_awprot = s_axi_awprot;
assign m_axi_awregion = s_axi_awregion;
assign m_axi_awqos = s_axi_awqos;
assign m_axi_awuser = s_axi_awuser;
assign m_axi_awvalid = s_awvalid_i;
assign s_awready_i = m_axi_awready;
assign m_axi_wid = s_axi_wid;
assign m_axi_wdata = s_axi_wdata;
assign m_axi_wstrb = s_axi_wstrb;
assign m_axi_wlast = s_axi_wlast;
assign m_axi_wuser = s_axi_wuser;
assign m_axi_wvalid = s_wvalid_i;
assign s_wready_i = m_axi_wready;
assign s_bid_i = m_axi_bid;
assign s_bresp_i = m_axi_bresp;
assign s_buser_i = m_axi_buser;
assign s_bvalid_i = m_axi_bvalid;
assign m_axi_bready = s_bready_i;
assign m_axi_arid = s_axi_arid;
assign m_axi_araddr = s_axi_araddr;
assign m_axi_arlen = s_axi_arlen;
assign m_axi_arsize = s_axi_arsize;
assign m_axi_arburst = s_axi_arburst;
assign m_axi_arlock = s_axi_arlock;
assign m_axi_arcache = s_axi_arcache;
assign m_axi_arprot = s_axi_arprot;
assign m_axi_arregion = s_axi_arregion;
assign m_axi_arqos = s_axi_arqos;
assign m_axi_aruser = s_axi_aruser;
assign m_axi_arvalid = s_arvalid_i;
assign s_arready_i = m_axi_arready;
assign s_rid_i = m_axi_rid;
assign s_rdata_i = m_axi_rdata;
assign s_rresp_i = m_axi_rresp;
assign s_rlast_i = m_axi_rlast;
assign s_ruser_i = m_axi_ruser;
assign s_rvalid_i = m_axi_rvalid;
assign m_axi_rready = s_rready_i;
end
if ((C_TRANSLATION_MODE == P_PROTECTION) &&
(((C_S_AXI_PROTOCOL != P_AXILITE) && (C_M_AXI_PROTOCOL == P_AXILITE)) ||
((C_S_AXI_PROTOCOL == P_AXI4) && (C_M_AXI_PROTOCOL == P_AXI3)))) begin : gen_err_detect
wire e_awvalid;
reg e_awvalid_r;
wire e_arvalid;
reg e_arvalid_r;
wire e_wvalid;
wire e_bvalid;
wire e_rvalid;
reg e_awready;
reg e_arready;
wire e_wready;
reg [C_AXI_ID_WIDTH-1:0] e_awid;
reg [C_AXI_ID_WIDTH-1:0] e_arid;
reg [8-1:0] e_arlen;
wire [C_AXI_ID_WIDTH-1:0] e_bid;
wire [C_AXI_ID_WIDTH-1:0] e_rid;
wire e_rlast;
wire w_err;
wire r_err;
wire busy_aw;
wire busy_w;
wire busy_ar;
wire aw_push;
wire aw_pop;
wire w_pop;
wire ar_push;
wire ar_pop;
reg s_awvalid_pending;
reg s_awvalid_en;
reg s_arvalid_en;
reg s_awready_en;
reg s_arready_en;
reg [4:0] aw_cnt;
reg [4:0] ar_cnt;
reg [4:0] w_cnt;
reg w_borrow;
reg err_busy_w;
reg err_busy_r;
assign w_err = (C_M_AXI_PROTOCOL == P_AXILITE) ? (s_axi_awlen != 0) : ((s_axi_awlen>>4) != 0);
assign r_err = (C_M_AXI_PROTOCOL == P_AXILITE) ? (s_axi_arlen != 0) : ((s_axi_arlen>>4) != 0);
assign s_awvalid_i = s_axi_awvalid & s_awvalid_en & ~w_err;
assign e_awvalid = e_awvalid_r & ~busy_aw & ~busy_w;
assign s_arvalid_i = s_axi_arvalid & s_arvalid_en & ~r_err;
assign e_arvalid = e_arvalid_r & ~busy_ar ;
assign s_wvalid_i = s_axi_wvalid & (busy_w | (s_awvalid_pending & ~w_borrow));
assign e_wvalid = s_axi_wvalid & err_busy_w;
assign s_bready_i = s_axi_bready & busy_aw;
assign s_rready_i = s_axi_rready & busy_ar;
assign s_axi_awready = (s_awready_i & s_awready_en) | e_awready;
assign s_axi_wready = (s_wready_i & (busy_w | (s_awvalid_pending & ~w_borrow))) | e_wready;
assign s_axi_bvalid = (s_bvalid_i & busy_aw) | e_bvalid;
assign s_axi_bid = err_busy_w ? e_bid : s_bid_i;
assign s_axi_bresp = err_busy_w ? P_SLVERR : s_bresp_i;
assign s_axi_buser = err_busy_w ? {C_AXI_BUSER_WIDTH{1\'b0}} : s_buser_i;
assign s_axi_arready = (s_arready_i & s_arready_en) | e_arready;
assign s_axi_rvalid = (s_rvalid_i & busy_ar) | e_rvalid;
assign s_axi_rid = err_busy_r ? e_rid : s_rid_i;
assign s_axi_rresp = err_busy_r ? P_SLVERR : s_rresp_i;
assign s_axi_ruser = err_busy_r ? {C_AXI_RUSER_WIDTH{1\'b0}} : s_ruser_i;
assign s_axi_rdata = err_busy_r ? {C_AXI_DATA_WIDTH{1\'b0}} : s_rdata_i;
assign s_axi_rlast = err_busy_r ? e_rlast : s_rlast_i;
assign busy_aw = (aw_cnt != 0);
assign busy_w = (w_cnt != 0);
assign busy_ar = (ar_cnt != 0);
assign aw_push = s_awvalid_i & s_awready_i & s_awready_en;
assign aw_pop = s_bvalid_i & s_bready_i;
assign w_pop = s_wvalid_i & s_wready_i & s_axi_wlast;
assign ar_push = s_arvalid_i & s_arready_i & s_arready_en;
assign ar_pop = s_rvalid_i & s_rready_i & s_rlast_i;
always @(posedge aclk) begin
if (~aresetn) begin
s_awvalid_en <= 1\'b0;
s_arvalid_en <= 1\'b0;
s_awready_en <= 1\'b0;
s_arready_en <= 1\'b0;
e_awvalid_r <= 1\'b0;
e_arvalid_r <= 1\'b0;
e_awready <= 1\'b0;
e_arready <= 1\'b0;
aw_cnt <= 0;
w_cnt <= 0;
ar_cnt <= 0;
err_busy_w <= 1\'b0;
err_busy_r <= 1\'b0;
w_borrow <= 1\'b0;
s_awvalid_pending <= 1\'b0;
end else begin
e_awready <= 1\'b0; // One-cycle pulse
if (e_bvalid & s_axi_bready) begin
s_awvalid_en <= 1\'b1;
s_awready_en <= 1\'b1;
err_busy_w <= 1\'b0;
end else if (e_awvalid) begin
e_awvalid_r <= 1\'b0;
err_busy_w <= 1\'b1;
end else if (s_axi_awvalid & w_err & ~e_awvalid_r & ~err_busy_w) begin
e_awvalid_r <= 1\'b1;
e_awready <= ~(s_awready_i & s_awvalid_en); // 1-cycle pulse if awready not already asserted
s_awvalid_en <= 1\'b0;
s_awready_en <= 1\'b0;
end else if ((&aw_cnt) | (&w_cnt) | aw_push) begin
s_awvalid_en <= 1\'b0;
s_awready_en <= 1\'b0;
end else if (~err_busy_w & ~e_awvalid_r & ~(s_axi_awvalid & w_err)) begin
s_awvalid_en <= 1\'b1;
s_awready_en <= 1\'b1;
end
if (aw_push & ~aw_pop) begin
aw_cnt <= aw_cnt + 1;
end else if (~aw_push & aw_pop & (|aw_cnt)) begin
aw_cnt <= aw_cnt - 1;
end
if (aw_push) begin
if (~w_pop & ~w_borrow) begin
w_cnt <= w_cnt + 1;
end
w_borrow <= 1\'b0;
end else if (~aw_push & w_pop) begin
if (|w_cnt) begin
w_cnt <= w_cnt - 1;
end else begin
w_borrow <= 1\'b1;
end
end
s_awvalid_pending <= s_awvalid_i & ~s_awready_i;
e_arready <= 1\'b0; // One-cycle pulse
if (e_rvalid & s_axi_rready & e_rlast) begin
s_arvalid_en <= 1\'b1;
s_arready_en <= 1\'b1;
err_busy_r <= 1\'b0;
end else if (e_arvalid) begin
e_arvalid_r <= 1\'b0;
err_busy_r <= 1\'b1;
end else if (s_axi_arvalid & r_err & ~e_arvalid_r & ~err_busy_r) begin
e_arvalid_r <= 1\'b1;
e_arready <= ~(s_arready_i & s_arvalid_en); // 1-cycle pulse if arready not already asserted
s_arvalid_en <= 1\'b0;
s_arready_en <= 1\'b0;
end else if ((&ar_cnt) | ar_push) begin
s_arvalid_en <= 1\'b0;
s_arready_en <= 1\'b0;
end else if (~err_busy_r & ~e_arvalid_r & ~(s_axi_arvalid & r_err)) begin
s_arvalid_en <= 1\'b1;
s_arready_en <= 1\'b1;
end
if (ar_push & ~ar_pop) begin
ar_cnt <= ar_cnt + 1;
end else if (~ar_push & ar_pop & (|ar_cnt)) begin
ar_cnt <= ar_cnt - 1;
end
end
end
always @(posedge aclk) begin
if (s_axi_awvalid & ~err_busy_w & ~e_awvalid_r ) begin
e_awid <= s_axi_awid;
end
if (s_axi_arvalid & ~err_busy_r & ~e_arvalid_r ) begin
e_arid <= s_axi_arid;
e_arlen <= s_axi_arlen;
end
end
axi_protocol_converter_v2_1_decerr_slave #
(
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_AXI_PROTOCOL (C_S_AXI_PROTOCOL),
.C_RESP (P_SLVERR),
.C_IGNORE_ID (C_IGNORE_ID)
)
decerr_slave_inst
(
.ACLK (aclk),
.ARESETN (aresetn),
.S_AXI_AWID (e_awid),
.S_AXI_AWVALID (e_awvalid),
.S_AXI_AWREADY (),
.S_AXI_WLAST (s_axi_wlast),
.S_AXI_WVALID (e_wvalid),
.S_AXI_WREADY (e_wready),
.S_AXI_BID (e_bid),
.S_AXI_BRESP (),
.S_AXI_BUSER (),
.S_AXI_BVALID (e_bvalid),
.S_AXI_BREADY (s_axi_bready),
.S_AXI_ARID (e_arid),
.S_AXI_ARLEN (e_arlen),
.S_AXI_ARVALID (e_arvalid),
.S_AXI_ARREADY (),
.S_AXI_RID (e_rid),
.S_AXI_RDATA (),
.S_AXI_RRESP (),
.S_AXI_RUSER (),
.S_AXI_RLAST (e_rlast),
.S_AXI_RVALID (e_rvalid),
.S_AXI_RREADY (s_axi_rready)
);
end else begin : gen_no_err_detect
assign s_awvalid_i = s_axi_awvalid;
assign s_arvalid_i = s_axi_arvalid;
assign s_wvalid_i = s_axi_wvalid;
assign s_bready_i = s_axi_bready;
assign s_rready_i = s_axi_rready;
assign s_axi_awready = s_awready_i;
assign s_axi_wready = s_wready_i;
assign s_axi_bvalid = s_bvalid_i;
assign s_axi_bid = s_bid_i;
assign s_axi_bresp = s_bresp_i;
assign s_axi_buser = s_buser_i;
assign s_axi_arready = s_arready_i;
assign s_axi_rvalid = s_rvalid_i;
assign s_axi_rid = s_rid_i;
assign s_axi_rresp = s_rresp_i;
assign s_axi_ruser = s_ruser_i;
assign s_axi_rdata = s_rdata_i;
assign s_axi_rlast = s_rlast_i;
end // gen_err_detect
endgenerate
endmodule
`default_nettype wire
|
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_aw_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4,
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
// Slave Interface Write Address Ports
input wire [C_ID_WIDTH-1:0] s_awid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_awaddr ,
input wire [7:0] s_awlen ,
input wire [2:0] s_awsize ,
input wire [1:0] s_awburst ,
input wire s_awvalid ,
output wire s_awready ,
output wire m_awvalid ,
output wire [C_AXI_ADDR_WIDTH-1:0] m_awaddr ,
input wire m_awready ,
// Connections to/from axi_protocol_converter_v2_1_b2s_b_channel module
output wire b_push ,
output wire [C_ID_WIDTH-1:0] b_awid ,
output wire [7:0] b_awlen ,
input wire b_full
);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire next ;
wire next_pending ;
wire a_push;
wire incr_burst;
reg [C_ID_WIDTH-1:0] s_awid_r;
reg [7:0] s_awlen_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// Translate the AXI transaction to the MC transaction(s)
axi_protocol_converter_v2_1_b2s_cmd_translator #
(
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
cmd_translator_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_axaddr ( s_awaddr ) ,
.s_axlen ( s_awlen ) ,
.s_axsize ( s_awsize ) ,
.s_axburst ( s_awburst ) ,
.s_axhandshake ( s_awvalid & a_push ) ,
.m_axaddr ( m_awaddr ) ,
.incr_burst ( incr_burst ) ,
.next ( next ) ,
.next_pending ( next_pending )
);
axi_protocol_converter_v2_1_b2s_wr_cmd_fsm aw_cmd_fsm_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_awready ( s_awready ) ,
.s_awvalid ( s_awvalid ) ,
.m_awvalid ( m_awvalid ) ,
.m_awready ( m_awready ) ,
.next ( next ) ,
.next_pending ( next_pending ) ,
.b_push ( b_push ) ,
.b_full ( b_full ) ,
.a_push ( a_push )
);
assign b_awid = s_awid_r;
assign b_awlen = s_awlen_r;
always @(posedge clk) begin
s_awid_r <= s_awid ;
s_awlen_r <= s_awlen ;
end
endmodule
`default_nettype wire
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Register Slice
// Generic single-channel AXI pipeline register on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axic_register_slice
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_register_slice_v2_1_axic_register_slice #
(
parameter C_FAMILY = "virtex6",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32\'h00000000
// C_REG_CONFIG:
// 0 => BYPASS = The channel is just wired through the module.
// 1 => FWD_REV = Both FWD and REV (fully-registered)
// 2 => FWD = The master VALID and payload signals are registrated.
// 3 => REV = The slave ready signal is registrated
// 4 => RESERVED (all outputs driven to 0).
// 5 => RESERVED (all outputs driven to 0).
// 6 => INPUTS = Slave and Master side inputs are registrated.
// 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
(* use_clock_enable = "yes" *)
generate
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 0
// Bypass mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32\'h00000000) begin
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 1 (or 8)
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
else if ((C_REG_CONFIG == 32\'h00000001) || (C_REG_CONFIG == 32\'h00000008)) begin
reg [C_DATA_WIDTH-1:0] m_payload_i;
reg [C_DATA_WIDTH-1:0] skid_buffer;
reg s_ready_i;
reg m_valid_i;
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign M_PAYLOAD_DATA = m_payload_i;
reg [1:0] aresetn_d = 2\'b00; // Reset delay shifter
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2\'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
always @(posedge ACLK) begin
if (~aresetn_d[0]) begin
s_ready_i <= 1\'b0;
end else begin
s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);
end
if (~aresetn_d[1]) begin
m_valid_i <= 1\'b0;
end else begin
m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);
end
if (M_READY | ~m_valid_i) begin
m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;
end
if (s_ready_i) begin
skid_buffer <= S_PAYLOAD_DATA;
end
end
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 2
// Only FWD mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32\'h00000002)
begin
reg [C_DATA_WIDTH-1:0] storage_data;
wire s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg aresetn_d = 1\'b0; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 1\'b0;
end else begin
aresetn_d <= ~ARESET;
end
end
// Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK)
begin
if (S_VALID & s_ready_i)
storage_data <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data;
// M_Valid set to high when we have a completed transfer on slave side
// Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK)
begin
if (~aresetn_d)
m_valid_i <= 1\'b0;
else
if (S_VALID) // Always set m_valid_i when slave side is valid
m_valid_i <= 1\'b1;
else
if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready
m_valid_i <= 1\'b0;
end // always @ (posedge ACLK)
// Slave Ready is either when Master side drives M_Ready or we have space in our storage data
assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;
end // if (C_REG_CONFIG == 2)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 3
// Only REV mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32\'h00000003)
begin
reg [C_DATA_WIDTH-1:0] storage_data;
reg s_ready_i; //local signal of output
reg has_valid_storage_i;
reg has_valid_storage;
reg [1:0] aresetn_d = 2\'b00; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2\'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
// Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK)
begin
if (S_VALID & s_ready_i)
storage_data <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;
// Need to determine when we need to save a payload
// Need a combinatorial signals since it will also effect S_READY
always @ *
begin
// Set the value if we have a slave transaction but master side is not ready
if (S_VALID & s_ready_i & ~M_READY)
has_valid_storage_i = 1\'b1;
// Clear the value if it\'s set and Master side completes the transaction but we don\'t have a new slave side
// transaction
else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))
has_valid_storage_i = 1\'b0;
else
has_valid_storage_i = has_valid_storage;
end // always @ *
always @(posedge ACLK)
begin
if (~aresetn_d[0])
has_valid_storage <= 1\'b0;
else
has_valid_storage <= has_valid_storage_i;
end
// S_READY is either clocked M_READY or that we have room in local storage
always @(posedge ACLK)
begin
if (~aresetn_d[0])
s_ready_i <= 1\'b0;
else
s_ready_i <= M_READY | ~has_valid_storage_i;
end
// assign local signal to its output signal
assign S_READY = s_ready_i;
// M_READY is either combinatorial S_READY or that we have valid data in local storage
assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];
end // if (C_REG_CONFIG == 3)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED
//
////////////////////////////////////////////////////////////////////
else if ((C_REG_CONFIG == 32\'h00000004) || (C_REG_CONFIG == 32\'h00000005))
begin
// synthesis translate_off
initial begin
$display ("ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.");
end
// synthesis translate_on
assign M_PAYLOAD_DATA = 0;
assign M_VALID = 1\'b0;
assign S_READY = 1\'b0;
end
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 6
// INPUTS mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32\'h00000006)
begin
reg [1:0] state;
reg [1:0] next_state;
localparam [1:0]
ZERO = 2\'b00,
ONE = 2\'b01,
TWO = 2\'b11;
reg [C_DATA_WIDTH-1:0] storage_data1;
reg [C_DATA_WIDTH-1:0] storage_data2;
reg s_valid_d;
reg s_ready_d;
reg m_ready_d;
reg m_valid_d;
reg load_s2;
reg sel_s2;
wire new_access;
wire access_done;
wire s_ready_i; //local signal of output
reg s_ready_ii;
reg m_valid_i; //local signal of output
reg [1:0] aresetn_d = 2\'b00; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2\'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign s_ready_i = s_ready_ii & aresetn_d[1];
// Registrate input control signals
always @(posedge ACLK)
begin
if (~aresetn_d[0]) begin
s_valid_d <= 1\'b0;
s_ready_d <= 1\'b0;
m_ready_d <= 1\'b0;
end else begin
s_valid_d <= S_VALID;
s_ready_d <= s_ready_i;
m_ready_d <= M_READY;
end
end // always @ (posedge ACLK)
// Load storage1 with slave side payload data when slave side ready is high
always @(posedge ACLK)
begin
if (s_ready_i)
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with storage data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= storage_data1;
end
always @(posedge ACLK)
begin
if (~aresetn_d[0])
m_valid_d <= 1\'b0;
else
m_valid_d <= m_valid_i;
end
// Local help signals
assign new_access = s_ready_d & s_valid_d;
assign access_done = m_ready_d & m_valid_d;
// State Machine for handling output signals
always @*
begin
next_state = state; // Stay in the same state unless we need to move to another state
load_s2 = 0;
sel_s2 = 0;
m_valid_i = 0;
s_ready_ii = 0;
case (state)
// No transaction stored locally
ZERO: begin
load_s2 = 0;
sel_s2 = 0;
m_valid_i = 0;
s_ready_ii = 1;
if (new_access) begin
next_state = ONE; // Got one so move to ONE
load_s2 = 1;
m_valid_i = 0;
end
else begin
next_state = next_state;
load_s2 = load_s2;
m_valid_i = m_valid_i;
end
end // case: ZERO
// One transaction stored locally
ONE: begin
load_s2 = 0;
sel_s2 = 1;
m_valid_i = 1;
s_ready_ii = 1;
if (~new_access & access_done) begin
next_state = ZERO; // Read out one so move to ZERO
m_valid_i = 0;
end
else if (new_access & ~access_done) begin
next_state = TWO; // Got another one so move to TWO
s_ready_ii = 0;
end
else if (new_access & access_done) begin
load_s2 = 1;
sel_s2 = 0;
end
else begin
load_s2 = load_s2;
sel_s2 = sel_s2;
end
end // case: ONE
// TWO transaction stored locally
TWO: begin
load_s2 = 0;
sel_s2 = 1;
m_valid_i = 1;
s_ready_ii = 0;
if (access_done) begin
next_state = ONE; // Read out one so move to ONE
s_ready_ii = 1;
load_s2 = 1;
sel_s2 = 0;
end
else begin
next_state = next_state;
s_ready_ii = s_ready_ii;
load_s2 = load_s2;
sel_s2 = sel_s2;
end
end // case: TWO
endcase // case (state)
end // always @ *
// State Machine for handling output signals
always @(posedge ACLK)
begin
if (~aresetn_d[0])
state <= ZERO;
else
state <= next_state; // Stay in the same state unless we need to move to another state
end
// Master Payload mux
assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;
end // if (C_REG_CONFIG == 6)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 7
// Light-weight mode.
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32\'h00000007) begin
reg [C_DATA_WIDTH-1:0] m_payload_i;
reg s_ready_i;
reg m_valid_i;
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign M_PAYLOAD_DATA = m_payload_i;
reg [1:0] aresetn_d = 2\'b00; // Reset delay shifter
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2\'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
always @(posedge ACLK) begin
if (~aresetn_d[0]) begin
s_ready_i <= 1\'b0;
end else if (~aresetn_d[1]) begin
s_ready_i <= 1\'b1;
end else begin
s_ready_i <= m_valid_i ? M_READY : ~S_VALID;
end
if (~aresetn_d[1]) begin
m_valid_i <= 1\'b0;
end else begin
m_valid_i <= s_ready_i ? S_VALID : ~M_READY;
end
if (~m_valid_i) begin
m_payload_i <= S_PAYLOAD_DATA;
end
end
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule // reg_slice
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_ocmc.v
*
* Date : 2012-11
*
* Description : Controller for OCM model
*
*****************************************************************************/
module processing_system7_bfm_v2_0_ocmc(
rstn,
sw_clk,
/* Goes to port 0 of OCM */
ocm_wr_ack_port0,
ocm_wr_dv_port0,
ocm_rd_req_port0,
ocm_rd_dv_port0,
ocm_wr_addr_port0,
ocm_wr_data_port0,
ocm_wr_bytes_port0,
ocm_rd_addr_port0,
ocm_rd_data_port0,
ocm_rd_bytes_port0,
ocm_wr_qos_port0,
ocm_rd_qos_port0,
/* Goes to port 1 of OCM */
ocm_wr_ack_port1,
ocm_wr_dv_port1,
ocm_rd_req_port1,
ocm_rd_dv_port1,
ocm_wr_addr_port1,
ocm_wr_data_port1,
ocm_wr_bytes_port1,
ocm_rd_addr_port1,
ocm_rd_data_port1,
ocm_rd_bytes_port1,
ocm_wr_qos_port1,
ocm_rd_qos_port1
);
`include "processing_system7_bfm_v2_0_local_params.v"
input rstn;
input sw_clk;
output ocm_wr_ack_port0;
input ocm_wr_dv_port0;
input ocm_rd_req_port0;
output ocm_rd_dv_port0;
input[addr_width-1:0] ocm_wr_addr_port0;
input[max_burst_bits-1:0] ocm_wr_data_port0;
input[max_burst_bytes_width:0] ocm_wr_bytes_port0;
input[addr_width-1:0] ocm_rd_addr_port0;
output[max_burst_bits-1:0] ocm_rd_data_port0;
input[max_burst_bytes_width:0] ocm_rd_bytes_port0;
input [axi_qos_width-1:0] ocm_wr_qos_port0;
input [axi_qos_width-1:0] ocm_rd_qos_port0;
output ocm_wr_ack_port1;
input ocm_wr_dv_port1;
input ocm_rd_req_port1;
output ocm_rd_dv_port1;
input[addr_width-1:0] ocm_wr_addr_port1;
input[max_burst_bits-1:0] ocm_wr_data_port1;
input[max_burst_bytes_width:0] ocm_wr_bytes_port1;
input[addr_width-1:0] ocm_rd_addr_port1;
output[max_burst_bits-1:0] ocm_rd_data_port1;
input[max_burst_bytes_width:0] ocm_rd_bytes_port1;
input[axi_qos_width-1:0] ocm_wr_qos_port1;
input[axi_qos_width-1:0] ocm_rd_qos_port1;
wire [axi_qos_width-1:0] wr_qos;
wire wr_req;
wire [max_burst_bits-1:0] wr_data;
wire [addr_width-1:0] wr_addr;
wire [max_burst_bytes_width:0] wr_bytes;
reg wr_ack;
wire [axi_qos_width-1:0] rd_qos;
reg [max_burst_bits-1:0] rd_data;
wire [addr_width-1:0] rd_addr;
wire [max_burst_bytes_width:0] rd_bytes;
reg rd_dv;
wire rd_req;
processing_system7_bfm_v2_0_arb_wr ocm_write_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ocm_wr_qos_port0),
.qos2(ocm_wr_qos_port1),
.prt_dv1(ocm_wr_dv_port0),
.prt_dv2(ocm_wr_dv_port1),
.prt_data1(ocm_wr_data_port0),
.prt_data2(ocm_wr_data_port1),
.prt_addr1(ocm_wr_addr_port0),
.prt_addr2(ocm_wr_addr_port1),
.prt_bytes1(ocm_wr_bytes_port0),
.prt_bytes2(ocm_wr_bytes_port1),
.prt_ack1(ocm_wr_ack_port0),
.prt_ack2(ocm_wr_ack_port1),
.prt_qos(wr_qos),
.prt_req(wr_req),
.prt_data(wr_data),
.prt_addr(wr_addr),
.prt_bytes(wr_bytes),
.prt_ack(wr_ack)
);
processing_system7_bfm_v2_0_arb_rd ocm_read_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ocm_rd_qos_port0),
.qos2(ocm_rd_qos_port1),
.prt_req1(ocm_rd_req_port0),
.prt_req2(ocm_rd_req_port1),
.prt_data1(ocm_rd_data_port0),
.prt_data2(ocm_rd_data_port1),
.prt_addr1(ocm_rd_addr_port0),
.prt_addr2(ocm_rd_addr_port1),
.prt_bytes1(ocm_rd_bytes_port0),
.prt_bytes2(ocm_rd_bytes_port1),
.prt_dv1(ocm_rd_dv_port0),
.prt_dv2(ocm_rd_dv_port1),
.prt_qos(rd_qos),
.prt_req(rd_req),
.prt_data(rd_data),
.prt_addr(rd_addr),
.prt_bytes(rd_bytes),
.prt_dv(rd_dv)
);
processing_system7_bfm_v2_0_ocm_mem ocm();
reg [1:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
wr_ack <= 0;
rd_dv <= 0;
state <= 2\'d0;
end else begin
case(state)
0:begin
state <= 0;
wr_ack <= 0;
rd_dv <= 0;
if(wr_req) begin
ocm.write_mem(wr_data , wr_addr, wr_bytes);
wr_ack <= 1;
state <= 1;
end
if(rd_req) begin
ocm.read_mem(rd_data,rd_addr, rd_bytes);
rd_dv <= 1;
state <= 1;
end
end
1:begin
wr_ack <= 0;
rd_dv <= 0;
state <= 0;
end
endcase
end /// if
end// always
endmodule
|
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_bfm:2.0
// IP Revision: 1
`timescale 1ns/1ps
module base_zynq_design_processing_system7_0_0 (
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
IRQ_F2P,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA0_DRTYPE,
DMA2_DRTYPE,
FCLK_CLK0,
FCLK_CLK1,
FCLK_CLK2,
FCLK_RESET0_N,
FCLK_RESET1_N,
FCLK_RESET2_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1 : 0] USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11 : 0] M_AXI_GP0_ARID;
output [11 : 0] M_AXI_GP0_AWID;
output [11 : 0] M_AXI_GP0_WID;
output [1 : 0] M_AXI_GP0_ARBURST;
output [1 : 0] M_AXI_GP0_ARLOCK;
output [2 : 0] M_AXI_GP0_ARSIZE;
output [1 : 0] M_AXI_GP0_AWBURST;
output [1 : 0] M_AXI_GP0_AWLOCK;
output [2 : 0] M_AXI_GP0_AWSIZE;
output [2 : 0] M_AXI_GP0_ARPROT;
output [2 : 0] M_AXI_GP0_AWPROT;
output [31 : 0] M_AXI_GP0_ARADDR;
output [31 : 0] M_AXI_GP0_AWADDR;
output [31 : 0] M_AXI_GP0_WDATA;
output [3 : 0] M_AXI_GP0_ARCACHE;
output [3 : 0] M_AXI_GP0_ARLEN;
output [3 : 0] M_AXI_GP0_ARQOS;
output [3 : 0] M_AXI_GP0_AWCACHE;
output [3 : 0] M_AXI_GP0_AWLEN;
output [3 : 0] M_AXI_GP0_AWQOS;
output [3 : 0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11 : 0] M_AXI_GP0_BID;
input [11 : 0] M_AXI_GP0_RID;
input [1 : 0] M_AXI_GP0_BRESP;
input [1 : 0] M_AXI_GP0_RRESP;
input [31 : 0] M_AXI_GP0_RDATA;
input [0 : 0] IRQ_F2P;
output [1 : 0] DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
output [1 : 0] DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input [1 : 0] DMA0_DRTYPE;
input [1 : 0] DMA2_DRTYPE;
output FCLK_CLK0;
output FCLK_CLK1;
output FCLK_CLK2;
output FCLK_RESET0_N;
output FCLK_RESET1_N;
output FCLK_RESET2_N;
input [53 : 0] MIO;
input DDR_CAS_n;
input DDR_CKE;
input DDR_Clk_n;
input DDR_Clk;
input DDR_CS_n;
input DDR_DRSTB;
input DDR_ODT;
input DDR_RAS_n;
input DDR_WEB;
input [2 : 0] DDR_BankAddr;
input [14 : 0] DDR_Addr;
input DDR_VRN;
input DDR_VRP;
input [3 : 0] DDR_DM;
input [31 : 0] DDR_DQ;
input [3 : 0] DDR_DQS_n;
input [3 : 0] DDR_DQS;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
processing_system7_bfm_v2_0_processing_system7_bfm #(
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_ACP(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(0),
.C_FCLK_CLK0_FREQ(50),
.C_FCLK_CLK1_FREQ(152),
.C_FCLK_CLK2_FREQ(142),
.C_FCLK_CLK3_FREQ(50),
\t.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
\t.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
\t.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
\t.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
) inst (
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1\'B0),
.M_AXI_GP1_ARREADY(1\'B0),
.M_AXI_GP1_AWREADY(1\'B0),
.M_AXI_GP1_BVALID(1\'B0),
.M_AXI_GP1_RLAST(1\'B0),
.M_AXI_GP1_RVALID(1\'B0),
.M_AXI_GP1_WREADY(1\'B0),
.M_AXI_GP1_BID(12\'B0),
.M_AXI_GP1_RID(12\'B0),
.M_AXI_GP1_BRESP(2\'B0),
.M_AXI_GP1_RRESP(2\'B0),
.M_AXI_GP1_RDATA(32\'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1\'B0),
.S_AXI_GP0_ARVALID(1\'B0),
.S_AXI_GP0_AWVALID(1\'B0),
.S_AXI_GP0_BREADY(1\'B0),
.S_AXI_GP0_RREADY(1\'B0),
.S_AXI_GP0_WLAST(1\'B0),
.S_AXI_GP0_WVALID(1\'B0),
.S_AXI_GP0_ARBURST(2\'B0),
.S_AXI_GP0_ARLOCK(2\'B0),
.S_AXI_GP0_ARSIZE(3\'B0),
.S_AXI_GP0_AWBURST(2\'B0),
.S_AXI_GP0_AWLOCK(2\'B0),
.S_AXI_GP0_AWSIZE(3\'B0),
.S_AXI_GP0_ARPROT(3\'B0),
.S_AXI_GP0_AWPROT(3\'B0),
.S_AXI_GP0_ARADDR(32\'B0),
.S_AXI_GP0_AWADDR(32\'B0),
.S_AXI_GP0_WDATA(32\'B0),
.S_AXI_GP0_ARCACHE(4\'B0),
.S_AXI_GP0_ARLEN(4\'B0),
.S_AXI_GP0_ARQOS(4\'B0),
.S_AXI_GP0_AWCACHE(4\'B0),
.S_AXI_GP0_AWLEN(4\'B0),
.S_AXI_GP0_AWQOS(4\'B0),
.S_AXI_GP0_WSTRB(4\'B0),
.S_AXI_GP0_ARID(6\'B0),
.S_AXI_GP0_AWID(6\'B0),
.S_AXI_GP0_WID(6\'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1\'B0),
.S_AXI_GP1_ARVALID(1\'B0),
.S_AXI_GP1_AWVALID(1\'B0),
.S_AXI_GP1_BREADY(1\'B0),
.S_AXI_GP1_RREADY(1\'B0),
.S_AXI_GP1_WLAST(1\'B0),
.S_AXI_GP1_WVALID(1\'B0),
.S_AXI_GP1_ARBURST(2\'B0),
.S_AXI_GP1_ARLOCK(2\'B0),
.S_AXI_GP1_ARSIZE(3\'B0),
.S_AXI_GP1_AWBURST(2\'B0),
.S_AXI_GP1_AWLOCK(2\'B0),
.S_AXI_GP1_AWSIZE(3\'B0),
.S_AXI_GP1_ARPROT(3\'B0),
.S_AXI_GP1_AWPROT(3\'B0),
.S_AXI_GP1_ARADDR(32\'B0),
.S_AXI_GP1_AWADDR(32\'B0),
.S_AXI_GP1_WDATA(32\'B0),
.S_AXI_GP1_ARCACHE(4\'B0),
.S_AXI_GP1_ARLEN(4\'B0),
.S_AXI_GP1_ARQOS(4\'B0),
.S_AXI_GP1_AWCACHE(4\'B0),
.S_AXI_GP1_AWLEN(4\'B0),
.S_AXI_GP1_AWQOS(4\'B0),
.S_AXI_GP1_WSTRB(4\'B0),
.S_AXI_GP1_ARID(6\'B0),
.S_AXI_GP1_AWID(6\'B0),
.S_AXI_GP1_WID(6\'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1\'B0),
.S_AXI_ACP_ARVALID(1\'B0),
.S_AXI_ACP_AWVALID(1\'B0),
.S_AXI_ACP_BREADY(1\'B0),
.S_AXI_ACP_RREADY(1\'B0),
.S_AXI_ACP_WLAST(1\'B0),
.S_AXI_ACP_WVALID(1\'B0),
.S_AXI_ACP_ARID(3\'B0),
.S_AXI_ACP_ARPROT(3\'B0),
.S_AXI_ACP_AWID(3\'B0),
.S_AXI_ACP_AWPROT(3\'B0),
.S_AXI_ACP_WID(3\'B0),
.S_AXI_ACP_ARADDR(32\'B0),
.S_AXI_ACP_AWADDR(32\'B0),
.S_AXI_ACP_ARCACHE(4\'B0),
.S_AXI_ACP_ARLEN(4\'B0),
.S_AXI_ACP_ARQOS(4\'B0),
.S_AXI_ACP_AWCACHE(4\'B0),
.S_AXI_ACP_AWLEN(4\'B0),
.S_AXI_ACP_AWQOS(4\'B0),
.S_AXI_ACP_ARBURST(2\'B0),
.S_AXI_ACP_ARLOCK(2\'B0),
.S_AXI_ACP_ARSIZE(3\'B0),
.S_AXI_ACP_AWBURST(2\'B0),
.S_AXI_ACP_AWLOCK(2\'B0),
.S_AXI_ACP_AWSIZE(3\'B0),
.S_AXI_ACP_ARUSER(5\'B0),
.S_AXI_ACP_AWUSER(5\'B0),
.S_AXI_ACP_WDATA(64\'B0),
.S_AXI_ACP_WSTRB(8\'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_ACLK(1\'B0),
.S_AXI_HP0_ARVALID(1\'B0),
.S_AXI_HP0_AWVALID(1\'B0),
.S_AXI_HP0_BREADY(1\'B0),
.S_AXI_HP0_RREADY(1\'B0),
.S_AXI_HP0_WLAST(1\'B0),
.S_AXI_HP0_WVALID(1\'B0),
.S_AXI_HP0_ARBURST(2\'B0),
.S_AXI_HP0_ARLOCK(2\'B0),
.S_AXI_HP0_ARSIZE(3\'B0),
.S_AXI_HP0_AWBURST(2\'B0),
.S_AXI_HP0_AWLOCK(2\'B0),
.S_AXI_HP0_AWSIZE(3\'B0),
.S_AXI_HP0_ARPROT(3\'B0),
.S_AXI_HP0_AWPROT(3\'B0),
.S_AXI_HP0_ARADDR(32\'B0),
.S_AXI_HP0_AWADDR(32\'B0),
.S_AXI_HP0_ARCACHE(4\'B0),
.S_AXI_HP0_ARLEN(4\'B0),
.S_AXI_HP0_ARQOS(4\'B0),
.S_AXI_HP0_AWCACHE(4\'B0),
.S_AXI_HP0_AWLEN(4\'B0),
.S_AXI_HP0_AWQOS(4\'B0),
.S_AXI_HP0_ARID(6\'B0),
.S_AXI_HP0_AWID(6\'B0),
.S_AXI_HP0_WID(6\'B0),
.S_AXI_HP0_WDATA(64\'B0),
.S_AXI_HP0_WSTRB(8\'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_ACLK(1\'B0),
.S_AXI_HP1_ARVALID(1\'B0),
.S_AXI_HP1_AWVALID(1\'B0),
.S_AXI_HP1_BREADY(1\'B0),
.S_AXI_HP1_RREADY(1\'B0),
.S_AXI_HP1_WLAST(1\'B0),
.S_AXI_HP1_WVALID(1\'B0),
.S_AXI_HP1_ARBURST(2\'B0),
.S_AXI_HP1_ARLOCK(2\'B0),
.S_AXI_HP1_ARSIZE(3\'B0),
.S_AXI_HP1_AWBURST(2\'B0),
.S_AXI_HP1_AWLOCK(2\'B0),
.S_AXI_HP1_AWSIZE(3\'B0),
.S_AXI_HP1_ARPROT(3\'B0),
.S_AXI_HP1_AWPROT(3\'B0),
.S_AXI_HP1_ARADDR(32\'B0),
.S_AXI_HP1_AWADDR(32\'B0),
.S_AXI_HP1_ARCACHE(4\'B0),
.S_AXI_HP1_ARLEN(4\'B0),
.S_AXI_HP1_ARQOS(4\'B0),
.S_AXI_HP1_AWCACHE(4\'B0),
.S_AXI_HP1_AWLEN(4\'B0),
.S_AXI_HP1_AWQOS(4\'B0),
.S_AXI_HP1_ARID(6\'B0),
.S_AXI_HP1_AWID(6\'B0),
.S_AXI_HP1_WID(6\'B0),
.S_AXI_HP1_WDATA(64\'B0),
.S_AXI_HP1_WSTRB(8\'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_ACLK(1\'B0),
.S_AXI_HP2_ARVALID(1\'B0),
.S_AXI_HP2_AWVALID(1\'B0),
.S_AXI_HP2_BREADY(1\'B0),
.S_AXI_HP2_RREADY(1\'B0),
.S_AXI_HP2_WLAST(1\'B0),
.S_AXI_HP2_WVALID(1\'B0),
.S_AXI_HP2_ARBURST(2\'B0),
.S_AXI_HP2_ARLOCK(2\'B0),
.S_AXI_HP2_ARSIZE(3\'B0),
.S_AXI_HP2_AWBURST(2\'B0),
.S_AXI_HP2_AWLOCK(2\'B0),
.S_AXI_HP2_AWSIZE(3\'B0),
.S_AXI_HP2_ARPROT(3\'B0),
.S_AXI_HP2_AWPROT(3\'B0),
.S_AXI_HP2_ARADDR(32\'B0),
.S_AXI_HP2_AWADDR(32\'B0),
.S_AXI_HP2_ARCACHE(4\'B0),
.S_AXI_HP2_ARLEN(4\'B0),
.S_AXI_HP2_ARQOS(4\'B0),
.S_AXI_HP2_AWCACHE(4\'B0),
.S_AXI_HP2_AWLEN(4\'B0),
.S_AXI_HP2_AWQOS(4\'B0),
.S_AXI_HP2_ARID(6\'B0),
.S_AXI_HP2_AWID(6\'B0),
.S_AXI_HP2_WID(6\'B0),
.S_AXI_HP2_WDATA(64\'B0),
.S_AXI_HP2_WSTRB(8\'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_ACLK(1\'B0),
.S_AXI_HP3_ARVALID(1\'B0),
.S_AXI_HP3_AWVALID(1\'B0),
.S_AXI_HP3_BREADY(1\'B0),
.S_AXI_HP3_RREADY(1\'B0),
.S_AXI_HP3_WLAST(1\'B0),
.S_AXI_HP3_WVALID(1\'B0),
.S_AXI_HP3_ARBURST(2\'B0),
.S_AXI_HP3_ARLOCK(2\'B0),
.S_AXI_HP3_ARSIZE(3\'B0),
.S_AXI_HP3_AWBURST(2\'B0),
.S_AXI_HP3_AWLOCK(2\'B0),
.S_AXI_HP3_AWSIZE(3\'B0),
.S_AXI_HP3_ARPROT(3\'B0),
.S_AXI_HP3_AWPROT(3\'B0),
.S_AXI_HP3_ARADDR(32\'B0),
.S_AXI_HP3_AWADDR(32\'B0),
.S_AXI_HP3_ARCACHE(4\'B0),
.S_AXI_HP3_ARLEN(4\'B0),
.S_AXI_HP3_ARQOS(4\'B0),
.S_AXI_HP3_AWCACHE(4\'B0),
.S_AXI_HP3_AWLEN(4\'B0),
.S_AXI_HP3_AWQOS(4\'B0),
.S_AXI_HP3_ARID(6\'B0),
.S_AXI_HP3_AWID(6\'B0),
.S_AXI_HP3_WID(6\'B0),
.S_AXI_HP3_WDATA(64\'B0),
.S_AXI_HP3_WSTRB(8\'B0),
.FCLK_CLK0(FCLK_CLK0),
\t
.FCLK_CLK1(FCLK_CLK1),
\t
.FCLK_CLK2(FCLK_CLK2),
\t
.FCLK_CLK3(),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(FCLK_RESET1_N),
.FCLK_RESET2_N(FCLK_RESET2_N),
.FCLK_RESET3_N(),
.IRQ_F2P(IRQ_F2P),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized OR with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_carry_latch_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign O = CIN | I;
end else begin : USE_FPGA
OR2L or2l_inst1
(
.O(O),
.DI(CIN),
.SRI(I)
);
end
endgenerate
endmodule
|
// (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// AXI Register Slice
// Register selected channels on the forward and/or reverse signal paths.
// 5-channel memory-mapped AXI4 interfaces.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axi_register_slice
// axic_register_slice
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_register_slice_v2_1_axi_register_slice #
(
parameter C_FAMILY = "virtex6",
parameter C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
// C_REG_CONFIG_*:
// 0 => BYPASS = The channel is just wired through the module.
// 1 => FWD_REV = Both FWD and REV (fully-registered)
// 2 => FWD = The master VALID and payload signals are registrated.
// 3 => REV = The slave ready signal is registrated
// 4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.
// 5 => SLAVE_RDY = All slave side signals and master READY are registrated.
// 6 => INPUTS = Slave and Master side inputs are registrated.
// 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
parameter integer C_REG_CONFIG_AW = 0,
parameter integer C_REG_CONFIG_W = 0,
parameter integer C_REG_CONFIG_B = 0,
parameter integer C_REG_CONFIG_AR = 0,
parameter integer C_REG_CONFIG_R = 0
)
(
// System Signals
input wire aclk,
input wire aresetn,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input wire m_axi_rvalid,
output wire m_axi_rready
);
wire reset;
localparam C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;
`include "axi_infrastructure_v1_1_header.vh"
wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;
wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;
wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;
wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;
wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;
wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;
wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;
wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;
wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;
wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;
assign reset = ~aresetn;
axi_infrastructure_v1_1_axi2vector #(
.C_AXI_PROTOCOL ( C_AXI_PROTOCOL ) ,
.C_AXI_ID_WIDTH ( C_AXI_ID_WIDTH ) ,
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_AXI_DATA_WIDTH ( C_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_USER_SIGNALS ( C_AXI_SUPPORTS_USER_SIGNALS ) ,
.C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,
.C_AXI_AWUSER_WIDTH ( C_AXI_AWUSER_WIDTH ) ,
.C_AXI_ARUSER_WIDTH ( C_AXI_ARUSER_WIDTH ) ,
.C_AXI_WUSER_WIDTH ( C_AXI_WUSER_WIDTH ) ,
.C_AXI_RUSER_WIDTH ( C_AXI_RUSER_WIDTH ) ,
.C_AXI_BUSER_WIDTH ( C_AXI_BUSER_WIDTH ) ,
.C_AWPAYLOAD_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,
.C_WPAYLOAD_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,
.C_BPAYLOAD_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,
.C_ARPAYLOAD_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,
.C_RPAYLOAD_WIDTH ( G_AXI_RPAYLOAD_WIDTH )
)
axi_infrastructure_v1_1_axi2vector_0 (
.s_axi_awid ( s_axi_awid ) ,
.s_axi_awaddr ( s_axi_awaddr ) ,
.s_axi_awlen ( s_axi_awlen ) ,
.s_axi_awsize ( s_axi_awsize ) ,
.s_axi_awburst ( s_axi_awburst ) ,
.s_axi_awlock ( s_axi_awlock ) ,
.s_axi_awcache ( s_axi_awcache ) ,
.s_axi_awprot ( s_axi_awprot ) ,
.s_axi_awqos ( s_axi_awqos ) ,
.s_axi_awuser ( s_axi_awuser ) ,
.s_axi_awregion ( s_axi_awregion ) ,
.s_axi_wid ( s_axi_wid ) ,
.s_axi_wdata ( s_axi_wdata ) ,
.s_axi_wstrb ( s_axi_wstrb ) ,
.s_axi_wlast ( s_axi_wlast ) ,
.s_axi_wuser ( s_axi_wuser ) ,
.s_axi_bid ( s_axi_bid ) ,
.s_axi_bresp ( s_axi_bresp ) ,
.s_axi_buser ( s_axi_buser ) ,
.s_axi_arid ( s_axi_arid ) ,
.s_axi_araddr ( s_axi_araddr ) ,
.s_axi_arlen ( s_axi_arlen ) ,
.s_axi_arsize ( s_axi_arsize ) ,
.s_axi_arburst ( s_axi_arburst ) ,
.s_axi_arlock ( s_axi_arlock ) ,
.s_axi_arcache ( s_axi_arcache ) ,
.s_axi_arprot ( s_axi_arprot ) ,
.s_axi_arqos ( s_axi_arqos ) ,
.s_axi_aruser ( s_axi_aruser ) ,
.s_axi_arregion ( s_axi_arregion ) ,
.s_axi_rid ( s_axi_rid ) ,
.s_axi_rdata ( s_axi_rdata ) ,
.s_axi_rresp ( s_axi_rresp ) ,
.s_axi_rlast ( s_axi_rlast ) ,
.s_axi_ruser ( s_axi_ruser ) ,
.s_awpayload ( s_awpayload ) ,
.s_wpayload ( s_wpayload ) ,
.s_bpayload ( s_bpayload ) ,
.s_arpayload ( s_arpayload ) ,
.s_rpayload ( s_rpayload )
);
axi_register_slice_v2_1_axic_register_slice # (
.C_FAMILY ( C_FAMILY ) ,
.C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,
.C_REG_CONFIG ( C_REG_CONFIG_AW )
)
aw_pipe (
// System Signals
.ACLK(aclk),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(s_awpayload),
.S_VALID(s_axi_awvalid),
.S_READY(s_axi_awready),
// Master side
.M_PAYLOAD_DATA(m_awpayload),
.M_VALID(m_axi_awvalid),
.M_READY(m_axi_awready)
);
axi_register_slice_v2_1_axic_register_slice # (
.C_FAMILY ( C_FAMILY ) ,
.C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,
.C_REG_CONFIG ( C_REG_CONFIG_W )
)
w_pipe (
// System Signals
.ACLK(aclk),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(s_wpayload),
.S_VALID(s_axi_wvalid),
.S_READY(s_axi_wready),
// Master side
.M_PAYLOAD_DATA(m_wpayload),
.M_VALID(m_axi_wvalid),
.M_READY(m_axi_wready)
);
axi_register_slice_v2_1_axic_register_slice # (
.C_FAMILY ( C_FAMILY ) ,
.C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,
.C_REG_CONFIG ( C_REG_CONFIG_B )
)
b_pipe (
// System Signals
.ACLK(aclk),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(m_bpayload),
.S_VALID(m_axi_bvalid),
.S_READY(m_axi_bready),
// Master side
.M_PAYLOAD_DATA(s_bpayload),
.M_VALID(s_axi_bvalid),
.M_READY(s_axi_bready)
);
axi_register_slice_v2_1_axic_register_slice # (
.C_FAMILY ( C_FAMILY ) ,
.C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,
.C_REG_CONFIG ( C_REG_CONFIG_AR )
)
ar_pipe (
// System Signals
.ACLK(aclk),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(s_arpayload),
.S_VALID(s_axi_arvalid),
.S_READY(s_axi_arready),
// Master side
.M_PAYLOAD_DATA(m_arpayload),
.M_VALID(m_axi_arvalid),
.M_READY(m_axi_arready)
);
axi_register_slice_v2_1_axic_register_slice # (
.C_FAMILY ( C_FAMILY ) ,
.C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,
.C_REG_CONFIG ( C_REG_CONFIG_R )
)
r_pipe (
// System Signals
.ACLK(aclk),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(m_rpayload),
.S_VALID(m_axi_rvalid),
.S_READY(m_axi_rready),
// Master side
.M_PAYLOAD_DATA(s_rpayload),
.M_VALID(s_axi_rvalid),
.M_READY(s_axi_rready)
);
axi_infrastructure_v1_1_vector2axi #(
.C_AXI_PROTOCOL ( C_AXI_PROTOCOL ) ,
.C_AXI_ID_WIDTH ( C_AXI_ID_WIDTH ) ,
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_AXI_DATA_WIDTH ( C_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_USER_SIGNALS ( C_AXI_SUPPORTS_USER_SIGNALS ) ,
.C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,
.C_AXI_AWUSER_WIDTH ( C_AXI_AWUSER_WIDTH ) ,
.C_AXI_ARUSER_WIDTH ( C_AXI_ARUSER_WIDTH ) ,
.C_AXI_WUSER_WIDTH ( C_AXI_WUSER_WIDTH ) ,
.C_AXI_RUSER_WIDTH ( C_AXI_RUSER_WIDTH ) ,
.C_AXI_BUSER_WIDTH ( C_AXI_BUSER_WIDTH ) ,
.C_AWPAYLOAD_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,
.C_WPAYLOAD_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,
.C_BPAYLOAD_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,
.C_ARPAYLOAD_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,
.C_RPAYLOAD_WIDTH ( G_AXI_RPAYLOAD_WIDTH )
)
axi_infrastructure_v1_1_vector2axi_0 (
.m_awpayload ( m_awpayload ) ,
.m_wpayload ( m_wpayload ) ,
.m_bpayload ( m_bpayload ) ,
.m_arpayload ( m_arpayload ) ,
.m_rpayload ( m_rpayload ) ,
.m_axi_awid ( m_axi_awid ) ,
.m_axi_awaddr ( m_axi_awaddr ) ,
.m_axi_awlen ( m_axi_awlen ) ,
.m_axi_awsize ( m_axi_awsize ) ,
.m_axi_awburst ( m_axi_awburst ) ,
.m_axi_awlock ( m_axi_awlock ) ,
.m_axi_awcache ( m_axi_awcache ) ,
.m_axi_awprot ( m_axi_awprot ) ,
.m_axi_awqos ( m_axi_awqos ) ,
.m_axi_awuser ( m_axi_awuser ) ,
.m_axi_awregion ( m_axi_awregion ) ,
.m_axi_wid ( m_axi_wid ) ,
.m_axi_wdata ( m_axi_wdata ) ,
.m_axi_wstrb ( m_axi_wstrb ) ,
.m_axi_wlast ( m_axi_wlast ) ,
.m_axi_wuser ( m_axi_wuser ) ,
.m_axi_bid ( m_axi_bid ) ,
.m_axi_bresp ( m_axi_bresp ) ,
.m_axi_buser ( m_axi_buser ) ,
.m_axi_arid ( m_axi_arid ) ,
.m_axi_araddr ( m_axi_araddr ) ,
.m_axi_arlen ( m_axi_arlen ) ,
.m_axi_arsize ( m_axi_arsize ) ,
.m_axi_arburst ( m_axi_arburst ) ,
.m_axi_arlock ( m_axi_arlock ) ,
.m_axi_arcache ( m_axi_arcache ) ,
.m_axi_arprot ( m_axi_arprot ) ,
.m_axi_arqos ( m_axi_arqos ) ,
.m_axi_aruser ( m_axi_aruser ) ,
.m_axi_arregion ( m_axi_arregion ) ,
.m_axi_rid ( m_axi_rid ) ,
.m_axi_rdata ( m_axi_rdata ) ,
.m_axi_rresp ( m_axi_rresp ) ,
.m_axi_rlast ( m_axi_rlast ) ,
.m_axi_ruser ( m_axi_ruser )
);
endmodule // axi_register_slice
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Round-Robin Arbiter for R and B channel responses
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// arbiter_resp
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_arbiter_resp #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_S = 4, // Number of requesting Slave ports = [2:16]
parameter integer C_NUM_S_LOG = 2, // Log2(C_NUM_S)
parameter integer C_GRANT_ENC = 0, // Enable encoded grant output
parameter integer C_GRANT_HOT = 1 // Enable 1-hot grant output
)
(
// Global Inputs
input wire ACLK,
input wire ARESET,
// Slave Ports
input wire [C_NUM_S-1:0] S_VALID, // Request from each slave
output wire [C_NUM_S-1:0] S_READY, // Grant response to each slave
// Master Ports
output wire [C_NUM_S_LOG-1:0] M_GRANT_ENC, // Granted slave index (encoded)
output wire [C_NUM_S-1:0] M_GRANT_HOT, // Granted slave index (1-hot)
output wire M_VALID, // Grant event
input wire M_READY
);
// Generates a binary coded from onehotone encoded
function [4:0] f_hot2enc
(
input [16:0] one_hot
);
begin
f_hot2enc[0] = |(one_hot & 17\'b01010101010101010);
f_hot2enc[1] = |(one_hot & 17\'b01100110011001100);
f_hot2enc[2] = |(one_hot & 17\'b01111000011110000);
f_hot2enc[3] = |(one_hot & 17\'b01111111100000000);
f_hot2enc[4] = |(one_hot & 17\'b10000000000000000);
end
endfunction
(* use_clock_enable = "yes" *)
reg [C_NUM_S-1:0] chosen;
wire [C_NUM_S-1:0] grant_hot;
wire master_selected;
wire active_master;
wire need_arbitration;
wire m_valid_i;
wire [C_NUM_S-1:0] s_ready_i;
wire access_done;
reg [C_NUM_S-1:0] last_rr_hot;
wire [C_NUM_S-1:0] valid_rr;
reg [C_NUM_S-1:0] next_rr_hot;
reg [C_NUM_S*C_NUM_S-1:0] carry_rr;
reg [C_NUM_S*C_NUM_S-1:0] mask_rr;
integer i;
integer j;
integer n;
/////////////////////////////////////////////////////////////////////////////
//
// Implementation of the arbiter outputs independant of arbitration
//
/////////////////////////////////////////////////////////////////////////////
// Mask the current requests with the chosen master
assign grant_hot = chosen & S_VALID;
// See if we have a selected master
assign master_selected = |grant_hot[0+:C_NUM_S];
// See if we have current requests
assign active_master = |S_VALID;
// Access is completed
assign access_done = m_valid_i & M_READY;
// Need to handle if we drive S_ready combinatorial and without an IDLE state
// Drive S_READY on the master who has been chosen when we get a M_READY
assign s_ready_i = {C_NUM_S{M_READY}} & grant_hot[0+:C_NUM_S];
// Drive M_VALID if we have a selected master
assign m_valid_i = master_selected;
// If we have request and not a selected master, we need to arbitrate a new chosen
assign need_arbitration = (active_master & ~master_selected) | access_done;
// need internal signals of the output signals
assign M_VALID = m_valid_i;
assign S_READY = s_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Assign conditional onehot target output signal.
assign M_GRANT_HOT = (C_GRANT_HOT == 1) ? grant_hot[0+:C_NUM_S] : {C_NUM_S{1\'b0}};
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded target output signal.
assign M_GRANT_ENC = (C_GRANT_ENC == 1) ? f_hot2enc(grant_hot) : {C_NUM_S_LOG{1\'b0}};
/////////////////////////////////////////////////////////////////////////////
// Select a new chosen when we need to arbitrate
// If we don\'t have a new chosen, keep the old one since it\'s a good chance
// that it will do another request
always @(posedge ACLK)
begin
if (ARESET) begin
chosen <= {C_NUM_S{1\'b0}};
last_rr_hot <= {1\'b1, {C_NUM_S-1{1\'b0}}};
end else if (need_arbitration) begin
chosen <= next_rr_hot;
if (|next_rr_hot) last_rr_hot <= next_rr_hot;
end
end
assign valid_rr = S_VALID;
/////////////////////////////////////////////////////////////////////////////
// Round-robin arbiter
// Selects next request to grant from among inputs with PRIO = 0, if any.
/////////////////////////////////////////////////////////////////////////////
always @ * begin
next_rr_hot = 0;
for (i=0;i<C_NUM_S;i=i+1) begin
n = (i>0) ? (i-1) : (C_NUM_S-1);
carry_rr[i*C_NUM_S] = last_rr_hot[n];
mask_rr[i*C_NUM_S] = ~valid_rr[n];
for (j=1;j<C_NUM_S;j=j+1) begin
n = (i-j > 0) ? (i-j-1) : (C_NUM_S+i-j-1);
carry_rr[i*C_NUM_S+j] = carry_rr[i*C_NUM_S+j-1] | (last_rr_hot[n] & mask_rr[i*C_NUM_S+j-1]);
if (j < C_NUM_S-1) begin
mask_rr[i*C_NUM_S+j] = mask_rr[i*C_NUM_S+j-1] & ~valid_rr[n];
end
end
next_rr_hot[i] = valid_rr[i] & carry_rr[(i+1)*C_NUM_S-1];
end
end
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_axi_acp.v
*
* Date : 2012-11
*
* Description : Connections for ACP port
*
*****************************************************************************/
/* AXI Slave ACP */
processing_system7_bfm_v2_0_axi_slave #( C_USE_S_AXI_ACP, // enable
axi_acp_name, // name
axi_acp_data_width, // data width
addr_width, /// address width
axi_acp_id_width, // ID width
C_S_AXI_ACP_BASEADDR, // slave base address
C_S_AXI_ACP_HIGHADDR,// slave size
axi_acp_outstanding, // outstanding transactions // 7 Reads and 3 Writes
axi_slv_excl_support, // Exclusive access support
axi_acp_wr_outstanding,
axi_acp_rd_outstanding)
S_AXI_ACP(.S_RESETN (net_axi_acp_rstn),
.S_ACLK (S_AXI_ACP_ACLK),
// Write Address Channel
.S_AWID (S_AXI_ACP_AWID),
.S_AWADDR (S_AXI_ACP_AWADDR),
.S_AWLEN (S_AXI_ACP_AWLEN),
.S_AWSIZE (S_AXI_ACP_AWSIZE),
.S_AWBURST (S_AXI_ACP_AWBURST),
.S_AWLOCK (S_AXI_ACP_AWLOCK),
.S_AWCACHE (S_AXI_ACP_AWCACHE),
.S_AWPROT (S_AXI_ACP_AWPROT),
.S_AWVALID (S_AXI_ACP_AWVALID),
.S_AWREADY (S_AXI_ACP_AWREADY),
// Write Data Channel Signals.
.S_WID (S_AXI_ACP_WID),
.S_WDATA (S_AXI_ACP_WDATA),
.S_WSTRB (S_AXI_ACP_WSTRB),
.S_WLAST (S_AXI_ACP_WLAST),
.S_WVALID (S_AXI_ACP_WVALID),
.S_WREADY (S_AXI_ACP_WREADY),
// Write Response Channel Signals.
.S_BID (S_AXI_ACP_BID),
.S_BRESP (S_AXI_ACP_BRESP),
.S_BVALID (S_AXI_ACP_BVALID),
.S_BREADY (S_AXI_ACP_BREADY),
// Read Address Channel Signals.
.S_ARID (S_AXI_ACP_ARID),
.S_ARADDR (S_AXI_ACP_ARADDR),
.S_ARLEN (S_AXI_ACP_ARLEN),
.S_ARSIZE (S_AXI_ACP_ARSIZE),
.S_ARBURST (S_AXI_ACP_ARBURST),
.S_ARLOCK (S_AXI_ACP_ARLOCK),
.S_ARCACHE (S_AXI_ACP_ARCACHE),
.S_ARPROT (S_AXI_ACP_ARPROT),
.S_ARVALID (S_AXI_ACP_ARVALID),
.S_ARREADY (S_AXI_ACP_ARREADY),
// Read Data Channel Signals.
.S_RID (S_AXI_ACP_RID),
.S_RDATA (S_AXI_ACP_RDATA),
.S_RRESP (S_AXI_ACP_RRESP),
.S_RLAST (S_AXI_ACP_RLAST),
.S_RVALID (S_AXI_ACP_RVALID),
.S_RREADY (S_AXI_ACP_RREADY),
// Side band signals
.S_AWQOS (S_AXI_ACP_AWQOS),
.S_ARQOS (S_AXI_ACP_ARQOS), // Side band signals
.SW_CLK (net_sw_clk),
/* This goes to port 0 of DDR and port 0 of OCM , port 0 of REG*/
.WR_DATA_ACK_DDR (ddr_wr_ack_port0),
.WR_DATA_ACK_OCM (ocm_wr_ack_port0),
.WR_DATA (net_wr_data_acp),
.WR_ADDR (net_wr_addr_acp),
.WR_BYTES (net_wr_bytes_acp),
.WR_DATA_VALID_DDR (ddr_wr_dv_port0),
.WR_DATA_VALID_OCM (ocm_wr_dv_port0),
.WR_QOS (net_wr_qos_acp),
.RD_REQ_DDR (ddr_rd_req_port0),
.RD_REQ_OCM (ocm_rd_req_port0),
.RD_REQ_REG (reg_rd_req_port0),
.RD_ADDR (net_rd_addr_acp),
.RD_DATA_DDR (ddr_rd_data_port0),
.RD_DATA_OCM (ocm_rd_data_port0),
.RD_DATA_REG (reg_rd_data_port0),
.RD_BYTES (net_rd_bytes_acp),
.RD_DATA_VALID_DDR (ddr_rd_dv_port0),
.RD_DATA_VALID_OCM (ocm_rd_dv_port0),
.RD_DATA_VALID_REG (reg_rd_dv_port0),
.RD_QOS (net_rd_qos_acp)
);
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_ddrc.v
*
* Date : 2012-11
*
* Description : Module that acts as controller for sparse memory (DDR).
*
*****************************************************************************/
module processing_system7_bfm_v2_0_ddrc(
rstn,
sw_clk,
/* Goes to port 0 of DDR */
ddr_wr_ack_port0,
ddr_wr_dv_port0,
ddr_rd_req_port0,
ddr_rd_dv_port0,
ddr_wr_addr_port0,
ddr_wr_data_port0,
ddr_wr_bytes_port0,
ddr_rd_addr_port0,
ddr_rd_data_port0,
ddr_rd_bytes_port0,
ddr_wr_qos_port0,
ddr_rd_qos_port0,
/* Goes to port 1 of DDR */
ddr_wr_ack_port1,
ddr_wr_dv_port1,
ddr_rd_req_port1,
ddr_rd_dv_port1,
ddr_wr_addr_port1,
ddr_wr_data_port1,
ddr_wr_bytes_port1,
ddr_rd_addr_port1,
ddr_rd_data_port1,
ddr_rd_bytes_port1,
ddr_wr_qos_port1,
ddr_rd_qos_port1,
/* Goes to port2 of DDR */
ddr_wr_ack_port2,
ddr_wr_dv_port2,
ddr_rd_req_port2,
ddr_rd_dv_port2,
ddr_wr_addr_port2,
ddr_wr_data_port2,
ddr_wr_bytes_port2,
ddr_rd_addr_port2,
ddr_rd_data_port2,
ddr_rd_bytes_port2,
ddr_wr_qos_port2,
ddr_rd_qos_port2,
/* Goes to port3 of DDR */
ddr_wr_ack_port3,
ddr_wr_dv_port3,
ddr_rd_req_port3,
ddr_rd_dv_port3,
ddr_wr_addr_port3,
ddr_wr_data_port3,
ddr_wr_bytes_port3,
ddr_rd_addr_port3,
ddr_rd_data_port3,
ddr_rd_bytes_port3,
ddr_wr_qos_port3,
ddr_rd_qos_port3
);
`include "processing_system7_bfm_v2_0_local_params.v"
input rstn;
input sw_clk;
output ddr_wr_ack_port0;
input ddr_wr_dv_port0;
input ddr_rd_req_port0;
output ddr_rd_dv_port0;
input[addr_width-1:0] ddr_wr_addr_port0;
input[max_burst_bits-1:0] ddr_wr_data_port0;
input[max_burst_bytes_width:0] ddr_wr_bytes_port0;
input[addr_width-1:0] ddr_rd_addr_port0;
output[max_burst_bits-1:0] ddr_rd_data_port0;
input[max_burst_bytes_width:0] ddr_rd_bytes_port0;
input [axi_qos_width-1:0] ddr_wr_qos_port0;
input [axi_qos_width-1:0] ddr_rd_qos_port0;
output ddr_wr_ack_port1;
input ddr_wr_dv_port1;
input ddr_rd_req_port1;
output ddr_rd_dv_port1;
input[addr_width-1:0] ddr_wr_addr_port1;
input[max_burst_bits-1:0] ddr_wr_data_port1;
input[max_burst_bytes_width:0] ddr_wr_bytes_port1;
input[addr_width-1:0] ddr_rd_addr_port1;
output[max_burst_bits-1:0] ddr_rd_data_port1;
input[max_burst_bytes_width:0] ddr_rd_bytes_port1;
input[axi_qos_width-1:0] ddr_wr_qos_port1;
input[axi_qos_width-1:0] ddr_rd_qos_port1;
output ddr_wr_ack_port2;
input ddr_wr_dv_port2;
input ddr_rd_req_port2;
output ddr_rd_dv_port2;
input[addr_width-1:0] ddr_wr_addr_port2;
input[max_burst_bits-1:0] ddr_wr_data_port2;
input[max_burst_bytes_width:0] ddr_wr_bytes_port2;
input[addr_width-1:0] ddr_rd_addr_port2;
output[max_burst_bits-1:0] ddr_rd_data_port2;
input[max_burst_bytes_width:0] ddr_rd_bytes_port2;
input[axi_qos_width-1:0] ddr_wr_qos_port2;
input[axi_qos_width-1:0] ddr_rd_qos_port2;
output ddr_wr_ack_port3;
input ddr_wr_dv_port3;
input ddr_rd_req_port3;
output ddr_rd_dv_port3;
input[addr_width-1:0] ddr_wr_addr_port3;
input[max_burst_bits-1:0] ddr_wr_data_port3;
input[max_burst_bytes_width:0] ddr_wr_bytes_port3;
input[addr_width-1:0] ddr_rd_addr_port3;
output[max_burst_bits-1:0] ddr_rd_data_port3;
input[max_burst_bytes_width:0] ddr_rd_bytes_port3;
input[axi_qos_width-1:0] ddr_wr_qos_port3;
input[axi_qos_width-1:0] ddr_rd_qos_port3;
wire [axi_qos_width-1:0] wr_qos;
wire wr_req;
wire [max_burst_bits-1:0] wr_data;
wire [addr_width-1:0] wr_addr;
wire [max_burst_bytes_width:0] wr_bytes;
reg wr_ack;
wire [axi_qos_width-1:0] rd_qos;
reg [max_burst_bits-1:0] rd_data;
wire [addr_width-1:0] rd_addr;
wire [max_burst_bytes_width:0] rd_bytes;
reg rd_dv;
wire rd_req;
processing_system7_bfm_v2_0_arb_wr_4 ddr_write_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ddr_wr_qos_port0),
.qos2(ddr_wr_qos_port1),
.qos3(ddr_wr_qos_port2),
.qos4(ddr_wr_qos_port3),
.prt_dv1(ddr_wr_dv_port0),
.prt_dv2(ddr_wr_dv_port1),
.prt_dv3(ddr_wr_dv_port2),
.prt_dv4(ddr_wr_dv_port3),
.prt_data1(ddr_wr_data_port0),
.prt_data2(ddr_wr_data_port1),
.prt_data3(ddr_wr_data_port2),
.prt_data4(ddr_wr_data_port3),
.prt_addr1(ddr_wr_addr_port0),
.prt_addr2(ddr_wr_addr_port1),
.prt_addr3(ddr_wr_addr_port2),
.prt_addr4(ddr_wr_addr_port3),
.prt_bytes1(ddr_wr_bytes_port0),
.prt_bytes2(ddr_wr_bytes_port1),
.prt_bytes3(ddr_wr_bytes_port2),
.prt_bytes4(ddr_wr_bytes_port3),
.prt_ack1(ddr_wr_ack_port0),
.prt_ack2(ddr_wr_ack_port1),
.prt_ack3(ddr_wr_ack_port2),
.prt_ack4(ddr_wr_ack_port3),
.prt_qos(wr_qos),
.prt_req(wr_req),
.prt_data(wr_data),
.prt_addr(wr_addr),
.prt_bytes(wr_bytes),
.prt_ack(wr_ack)
);
processing_system7_bfm_v2_0_arb_rd_4 ddr_read_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ddr_rd_qos_port0),
.qos2(ddr_rd_qos_port1),
.qos3(ddr_rd_qos_port2),
.qos4(ddr_rd_qos_port3),
.prt_req1(ddr_rd_req_port0),
.prt_req2(ddr_rd_req_port1),
.prt_req3(ddr_rd_req_port2),
.prt_req4(ddr_rd_req_port3),
.prt_data1(ddr_rd_data_port0),
.prt_data2(ddr_rd_data_port1),
.prt_data3(ddr_rd_data_port2),
.prt_data4(ddr_rd_data_port3),
.prt_addr1(ddr_rd_addr_port0),
.prt_addr2(ddr_rd_addr_port1),
.prt_addr3(ddr_rd_addr_port2),
.prt_addr4(ddr_rd_addr_port3),
.prt_bytes1(ddr_rd_bytes_port0),
.prt_bytes2(ddr_rd_bytes_port1),
.prt_bytes3(ddr_rd_bytes_port2),
.prt_bytes4(ddr_rd_bytes_port3),
.prt_dv1(ddr_rd_dv_port0),
.prt_dv2(ddr_rd_dv_port1),
.prt_dv3(ddr_rd_dv_port2),
.prt_dv4(ddr_rd_dv_port3),
.prt_qos(rd_qos),
.prt_req(rd_req),
.prt_data(rd_data),
.prt_addr(rd_addr),
.prt_bytes(rd_bytes),
.prt_dv(rd_dv)
);
processing_system7_bfm_v2_0_sparse_mem ddr();
reg [1:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
wr_ack <= 0;
rd_dv <= 0;
state <= 2\'d0;
end else begin
case(state)
0:begin
state <= 0;
wr_ack <= 0;
rd_dv <= 0;
if(wr_req) begin
ddr.write_mem(wr_data , wr_addr, wr_bytes);
wr_ack <= 1;
state <= 1;
end
if(rd_req) begin
ddr.read_mem(rd_data,rd_addr, rd_bytes);
rd_dv <= 1;
state <= 1;
end
end
1:begin
wr_ack <= 0;
rd_dv <= 0;
state <= 0;
end
endcase
end /// if
end// always
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 4
(* X_CORE_INFO = "axi_protocol_converter_v2_1_axi_protocol_converter,Vivado 2014.4" *)
(* CHECK_LICENSE_TYPE = "base_zynq_design_auto_pc_0,axi_protocol_converter_v2_1_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "base_zynq_design_auto_pc_0,axi_protocol_converter_v2_1_axi_protocol_converter,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=0,C_IGNORE_ID=1,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module base_zynq_design_auto_pc_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(0),
.C_IGNORE_ID(1),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1\'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1\'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1\'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1\'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1\'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1\'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(1\'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1\'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(1\'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1\'H1),
.m_axi_ruser(1\'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_arb_rd_4.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between 4 read requests from 4 ports.
*
*****************************************************************************/
module processing_system7_bfm_v2_0_arb_rd_4(
rstn,
sw_clk,
qos1,
qos2,
qos3,
qos4,
prt_req1,
prt_req2,
prt_req3,
prt_req4,
prt_data1,
prt_data2,
prt_data3,
prt_data4,
prt_addr1,
prt_addr2,
prt_addr3,
prt_addr4,
prt_bytes1,
prt_bytes2,
prt_bytes3,
prt_bytes4,
prt_dv1,
prt_dv2,
prt_dv3,
prt_dv4,
prt_qos,
prt_req,
prt_data,
prt_addr,
prt_bytes,
prt_dv
);
`include "processing_system7_bfm_v2_0_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2,qos3,qos4;
input prt_req1, prt_req2,prt_req3, prt_req4, prt_dv;
output reg [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4;
input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4;
input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4;
output reg prt_dv1,prt_dv2,prt_dv3,prt_dv4,prt_req;
input [max_burst_bits-1:0] prt_data;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
output reg [axi_qos_width-1:0] prt_qos;
parameter wait_req = 3\'b000, serv_req1 = 3\'b001, serv_req2 = 3\'b010, serv_req3 = 3\'b011, serv_req4 = 3\'b100, wait_dv_low=3\'b101;
reg [2:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1\'b0;
prt_dv1 = 1\'b0;
prt_dv2 = 1\'b0;
prt_dv3 = 1\'b0;
prt_dv4 = 1\'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_dv1 = 1\'b0;
prt_dv2 = 1\'b0;
prt_dv3 = 1\'b0;
prt_dv4 = 1\'b0;
prt_req = 1\'b0;
if(prt_req1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_req2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_req4) begin
prt_req = 1;
prt_addr = prt_addr4;
prt_qos = qos4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
serv_req1:begin
state = serv_req1;
prt_dv2 = 1\'b0;
prt_dv3 = 1\'b0;
prt_dv4 = 1\'b0;
if(prt_dv)begin
prt_dv1 = 1\'b1;
prt_data1 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1\'b0;
if(prt_req2) begin
state = serv_req2;
prt_qos = qos2;
prt_req = 1;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req3) begin
state = serv_req3;
prt_qos = qos3;
prt_req = 1;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_req4) begin
prt_req = 1;
prt_qos = qos4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
end
serv_req2:begin
state = serv_req2;
prt_dv1 = 1\'b0;
prt_dv3 = 1\'b0;
prt_dv4 = 1\'b0;
if(prt_dv)begin
prt_dv2 = 1\'b1;
prt_data2 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1\'b0;
if(prt_req3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_req4) begin
state = serv_req4;
prt_req = 1;
prt_qos = qos4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_req1) begin
prt_req = 1;
prt_addr = prt_addr1;
prt_qos = qos1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req3:begin
state = serv_req3;
prt_dv1 = 1\'b0;
prt_dv2 = 1\'b0;
prt_dv4 = 1\'b0;
if(prt_dv)begin
prt_dv3 = 1\'b1;
prt_data3 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1\'b0;
if(prt_req4) begin
state = serv_req4;
prt_qos = qos4;
prt_req = 1;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_req1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_req2) begin
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end
end
end
serv_req4:begin
state = serv_req4;
prt_dv1 = 1\'b0;
prt_dv2 = 1\'b0;
prt_dv3 = 1\'b0;
if(prt_dv)begin
prt_dv4 = 1\'b1;
prt_data4 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1\'b0;
if(prt_req1) begin
state = serv_req1;
prt_qos = qos1;
prt_req = 1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_req2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req3) begin
prt_req = 1;
prt_addr = prt_addr3;
prt_qos = qos3;
prt_bytes = prt_bytes3;
state = serv_req3;
end
end
end
wait_dv_low:begin
state = wait_dv_low;
prt_dv1 = 1\'b0;
prt_dv2 = 1\'b0;
prt_dv3 = 1\'b0;
prt_dv4 = 1\'b0;
if(!prt_dv)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: AxiLite Slave Conversion
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axilite_conv
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_axilite_conv #
(
parameter C_FAMILY = "virtex6",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1
)
(
// System Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [3-1:0] S_AXI_AWPROT,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, // Constant =0
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [3-1:0] S_AXI_ARPROT,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST, // Constant =1
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, // Constant =0
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [3-1:0] M_AXI_AWPROT,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [2-1:0] M_AXI_BRESP,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [3-1:0] M_AXI_ARPROT,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
wire s_awvalid_i;
wire s_arvalid_i;
wire [C_AXI_ADDR_WIDTH-1:0] m_axaddr;
// Arbiter
reg read_active;
reg write_active;
reg busy;
wire read_req;
wire write_req;
wire read_complete;
wire write_complete;
reg [1:0] areset_d; // Reset delay register
always @(posedge ACLK) begin
areset_d <= {areset_d[0], ~ARESETN};
end
assign s_awvalid_i = S_AXI_AWVALID & (C_AXI_SUPPORTS_WRITE != 0);
assign s_arvalid_i = S_AXI_ARVALID & (C_AXI_SUPPORTS_READ != 0);
assign read_req = s_arvalid_i & ~busy & ~|areset_d & ~write_active;
assign write_req = s_awvalid_i & ~busy & ~|areset_d & ((~read_active & ~s_arvalid_i) | write_active);
assign read_complete = M_AXI_RVALID & S_AXI_RREADY;
assign write_complete = M_AXI_BVALID & S_AXI_BREADY;
always @(posedge ACLK) begin : arbiter_read_ff
if (|areset_d)
read_active <= 1\'b0;
else if (read_complete)
read_active <= 1\'b0;
else if (read_req)
read_active <= 1\'b1;
end
always @(posedge ACLK) begin : arbiter_write_ff
if (|areset_d)
write_active <= 1\'b0;
else if (write_complete)
write_active <= 1\'b0;
else if (write_req)
write_active <= 1\'b1;
end
always @(posedge ACLK) begin : arbiter_busy_ff
if (|areset_d)
busy <= 1\'b0;
else if (read_complete | write_complete)
busy <= 1\'b0;
else if ((write_req & M_AXI_AWREADY) | (read_req & M_AXI_ARREADY))
busy <= 1\'b1;
end
assign M_AXI_ARVALID = read_req;
assign S_AXI_ARREADY = M_AXI_ARREADY & read_req;
assign M_AXI_AWVALID = write_req;
assign S_AXI_AWREADY = M_AXI_AWREADY & write_req;
assign M_AXI_RREADY = S_AXI_RREADY & read_active;
assign S_AXI_RVALID = M_AXI_RVALID & read_active;
assign M_AXI_BREADY = S_AXI_BREADY & write_active;
assign S_AXI_BVALID = M_AXI_BVALID & write_active;
// Address multiplexer
assign m_axaddr = (read_req | (C_AXI_SUPPORTS_WRITE == 0)) ? S_AXI_ARADDR : S_AXI_AWADDR;
// Id multiplexer and flip-flop
reg [C_AXI_ID_WIDTH-1:0] s_axid;
always @(posedge ACLK) begin : axid
if (read_req) s_axid <= S_AXI_ARID;
else if (write_req) s_axid <= S_AXI_AWID;
end
assign S_AXI_BID = s_axid;
assign S_AXI_RID = s_axid;
assign M_AXI_AWADDR = m_axaddr;
assign M_AXI_ARADDR = m_axaddr;
// Feed-through signals
assign S_AXI_WREADY = M_AXI_WREADY & ~|areset_d;
assign S_AXI_BRESP = M_AXI_BRESP;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = 1\'b1;
assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1\'b0}};
assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1\'b0}};
assign M_AXI_AWPROT = S_AXI_AWPROT;
assign M_AXI_WVALID = S_AXI_WVALID & ~|areset_d;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_ARPROT = S_AXI_ARPROT;
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_arb_wr_4.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between 4 write requests from 4 ports.
*
*****************************************************************************/
module processing_system7_bfm_v2_0_arb_wr_4(
rstn,
sw_clk,
qos1,
qos2,
qos3,
qos4,
prt_dv1,
prt_dv2,
prt_dv3,
prt_dv4,
prt_data1,
prt_data2,
prt_data3,
prt_data4,
prt_addr1,
prt_addr2,
prt_addr3,
prt_addr4,
prt_bytes1,
prt_bytes2,
prt_bytes3,
prt_bytes4,
prt_ack1,
prt_ack2,
prt_ack3,
prt_ack4,
prt_qos,
prt_req,
prt_data,
prt_addr,
prt_bytes,
prt_ack
);
`include "processing_system7_bfm_v2_0_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2,qos3,qos4;
input [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4;
input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4;
input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4;
input prt_dv1, prt_dv2,prt_dv3, prt_dv4, prt_ack;
output reg prt_ack1,prt_ack2,prt_ack3,prt_ack4,prt_req;
output reg [max_burst_bits-1:0] prt_data;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
output reg [axi_qos_width-1:0] prt_qos;
parameter wait_req = 3\'b000, serv_req1 = 3\'b001, serv_req2 = 3\'b010, serv_req3 = 3\'b011, serv_req4 = 4\'b100,wait_ack_low = 3\'b101;
reg [2:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1\'b0;
prt_ack1 = 1\'b0;
prt_ack2 = 1\'b0;
prt_ack3 = 1\'b0;
prt_ack4 = 1\'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_ack1 = 1\'b0;
prt_ack2 = 1\'b0;
prt_ack3 = 1\'b0;
prt_ack4 = 1\'b0;
prt_req = 0;
if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
serv_req1:begin
state = serv_req1;
prt_ack2 = 1\'b0;
prt_ack3 = 1\'b0;
prt_ack4 = 1\'b0;
if(prt_ack)begin
prt_ack1 = 1\'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv2) begin
state = serv_req2;
prt_qos = qos2;
prt_req = 1;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
end
serv_req2:begin
state = serv_req2;
prt_ack1 = 1\'b0;
prt_ack3 = 1\'b0;
prt_ack4 = 1\'b0;
if(prt_ack)begin
prt_ack2 = 1\'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv3) begin
state = serv_req3;
prt_qos = qos3;
prt_req = 1;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
state = serv_req4;
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_dv1) begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req3:begin
state = serv_req3;
prt_ack1 = 1\'b0;
prt_ack2 = 1\'b0;
prt_ack4 = 1\'b0;
if(prt_ack)begin
prt_ack3 = 1\'b1;
// state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv4) begin
state = serv_req4;
prt_qos = qos4;
prt_req = 1;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end
end
end
serv_req4:begin
state = serv_req4;
prt_ack1 = 1\'b0;
prt_ack2 = 1\'b0;
prt_ack3 = 1\'b0;
if(prt_ack)begin
prt_ack4 = 1\'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
state = serv_req3;
end
end
end
wait_ack_low:begin
state = wait_ack_low;
prt_ack1 = 1\'b0;
prt_ack2 = 1\'b0;
prt_ack3 = 1\'b0;
prt_ack4 = 1\'b0;
if(!prt_ack)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_axi_slave.v
*
* Date : 2012-11
*
* Description : Model that acts as PS AXI Slave port interface.
* It uses AXI3 Slave BFM
*****************************************************************************/
module processing_system7_bfm_v2_0_axi_slave (
S_RESETN,
S_ARREADY,
S_AWREADY,
S_BVALID,
S_RLAST,
S_RVALID,
S_WREADY,
S_BRESP,
S_RRESP,
S_RDATA,
S_BID,
S_RID,
S_ACLK,
S_ARVALID,
S_AWVALID,
S_BREADY,
S_RREADY,
S_WLAST,
S_WVALID,
S_ARBURST,
S_ARLOCK,
S_ARSIZE,
S_AWBURST,
S_AWLOCK,
S_AWSIZE,
S_ARPROT,
S_AWPROT,
S_ARADDR,
S_AWADDR,
S_WDATA,
S_ARCACHE,
S_ARLEN,
S_AWCACHE,
S_AWLEN,
S_WSTRB,
S_ARID,
S_AWID,
S_WID,
S_AWQOS,
S_ARQOS,
SW_CLK,
WR_DATA_ACK_OCM,
WR_DATA_ACK_DDR,
WR_ADDR,
WR_DATA,
WR_BYTES,
WR_DATA_VALID_OCM,
WR_DATA_VALID_DDR,
WR_QOS,
RD_QOS,
RD_REQ_DDR,
RD_REQ_OCM,
RD_REQ_REG,
RD_ADDR,
RD_DATA_OCM,
RD_DATA_DDR,
RD_DATA_REG,
RD_BYTES,
RD_DATA_VALID_OCM,
RD_DATA_VALID_DDR,
RD_DATA_VALID_REG
);
parameter enable_this_port = 0;
parameter slave_name = "Slave";
parameter data_bus_width = 32;
parameter address_bus_width = 32;
parameter id_bus_width = 6;
parameter slave_base_address = 0;
parameter slave_high_address = 4;
parameter max_outstanding_transactions = 8;
parameter exclusive_access_supported = 0;
parameter max_wr_outstanding_transactions = 8;
parameter max_rd_outstanding_transactions = 8;
`include "processing_system7_bfm_v2_0_local_params.v"
/* Local parameters only for this module */
/* Internal counters that are used as Read/Write pointers to the fifo\'s that store all the transaction info on all channles.
This parameter is used to define the width of these pointers --> depending on Maximum outstanding transactions supported.
1-bit extra width than the no.of.bits needed to represent the outstanding transactions
Extra bit helps in generating the empty and full flags
*/
parameter int_wr_cntr_width = clogb2(max_wr_outstanding_transactions)+1;
parameter int_rd_cntr_width = clogb2(max_rd_outstanding_transactions)+1;
/* RESP data */
parameter rsp_fifo_bits = axi_rsp_width+id_bus_width;
parameter rsp_lsb = 0;
parameter rsp_msb = axi_rsp_width-1;
parameter rsp_id_lsb = rsp_msb + 1;
parameter rsp_id_msb = rsp_id_lsb + id_bus_width-1;
input S_RESETN;
output S_ARREADY;
output S_AWREADY;
output S_BVALID;
output S_RLAST;
output S_RVALID;
output S_WREADY;
output [axi_rsp_width-1:0] S_BRESP;
output [axi_rsp_width-1:0] S_RRESP;
output [data_bus_width-1:0] S_RDATA;
output [id_bus_width-1:0] S_BID;
output [id_bus_width-1:0] S_RID;
input S_ACLK;
input S_ARVALID;
input S_AWVALID;
input S_BREADY;
input S_RREADY;
input S_WLAST;
input S_WVALID;
input [axi_brst_type_width-1:0] S_ARBURST;
input [axi_lock_width-1:0] S_ARLOCK;
input [axi_size_width-1:0] S_ARSIZE;
input [axi_brst_type_width-1:0] S_AWBURST;
input [axi_lock_width-1:0] S_AWLOCK;
input [axi_size_width-1:0] S_AWSIZE;
input [axi_prot_width-1:0] S_ARPROT;
input [axi_prot_width-1:0] S_AWPROT;
input [address_bus_width-1:0] S_ARADDR;
input [address_bus_width-1:0] S_AWADDR;
input [data_bus_width-1:0] S_WDATA;
input [axi_cache_width-1:0] S_ARCACHE;
input [axi_cache_width-1:0] S_ARLEN;
input [axi_qos_width-1:0] S_ARQOS;
input [axi_cache_width-1:0] S_AWCACHE;
input [axi_len_width-1:0] S_AWLEN;
input [axi_qos_width-1:0] S_AWQOS;
input [(data_bus_width/8)-1:0] S_WSTRB;
input [id_bus_width-1:0] S_ARID;
input [id_bus_width-1:0] S_AWID;
input [id_bus_width-1:0] S_WID;
input SW_CLK;
input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM;
output reg WR_DATA_VALID_DDR, WR_DATA_VALID_OCM;
output reg [max_burst_bits-1:0] WR_DATA;
output reg [addr_width-1:0] WR_ADDR;
output reg [max_burst_bytes_width:0] WR_BYTES;
output reg RD_REQ_OCM, RD_REQ_DDR, RD_REQ_REG;
output reg [addr_width-1:0] RD_ADDR;
input [max_burst_bits-1:0] RD_DATA_DDR,RD_DATA_OCM, RD_DATA_REG;
output reg[max_burst_bytes_width:0] RD_BYTES;
input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR, RD_DATA_VALID_REG;
output reg [axi_qos_width-1:0] WR_QOS, RD_QOS;
wire net_ARVALID;
wire net_AWVALID;
wire net_WVALID;
real s_aclk_period;
cdn_axi3_slave_bfm #(slave_name,
data_bus_width,
address_bus_width,
id_bus_width,
slave_base_address,
(slave_high_address- slave_base_address),
max_outstanding_transactions,
0, ///MEMORY_MODEL_MODE,
exclusive_access_supported)
slave (.ACLK (S_ACLK),
.ARESETn (S_RESETN), /// confirm this
// Write Address Channel
.AWID (S_AWID),
.AWADDR (S_AWADDR),
.AWLEN (S_AWLEN),
.AWSIZE (S_AWSIZE),
.AWBURST (S_AWBURST),
.AWLOCK (S_AWLOCK),
.AWCACHE (S_AWCACHE),
.AWPROT (S_AWPROT),
.AWVALID (net_AWVALID),
.AWREADY (S_AWREADY),
// Write Data Channel Signals.
.WID (S_WID),
.WDATA (S_WDATA),
.WSTRB (S_WSTRB),
.WLAST (S_WLAST),
.WVALID (net_WVALID),
.WREADY (S_WREADY),
// Write Response Channel Signals.
.BID (S_BID),
.BRESP (S_BRESP),
.BVALID (S_BVALID),
.BREADY (S_BREADY),
// Read Address Channel Signals.
.ARID (S_ARID),
.ARADDR (S_ARADDR),
.ARLEN (S_ARLEN),
.ARSIZE (S_ARSIZE),
.ARBURST (S_ARBURST),
.ARLOCK (S_ARLOCK),
.ARCACHE (S_ARCACHE),
.ARPROT (S_ARPROT),
.ARVALID (net_ARVALID),
.ARREADY (S_ARREADY),
// Read Data Channel Signals.
.RID (S_RID),
.RDATA (S_RDATA),
.RRESP (S_RRESP),
.RLAST (S_RLAST),
.RVALID (S_RVALID),
.RREADY (S_RREADY));
/* Latency type and Debug/Error Control */
reg[1:0] latency_type = RANDOM_CASE;
reg DEBUG_INFO = 1;
reg STOP_ON_ERROR = 1\'b1;
/* WR_FIFO stores 32-bit address, valid data and valid bytes for each AXI Write burst transaction */
reg [wr_fifo_data_bits-1:0] wr_fifo [0:max_wr_outstanding_transactions-1];
reg [int_wr_cntr_width-1:0] wr_fifo_wr_ptr = 0, wr_fifo_rd_ptr = 0;
wire wr_fifo_empty;
/* Store the awvalid receive time --- necessary for calculating the latency in sending the bresp*/
reg [7:0] aw_time_cnt = 0, bresp_time_cnt = 0;
real awvalid_receive_time[0:max_wr_outstanding_transactions]; // store the time when a new awvalid is received
reg awvalid_flag[0:max_wr_outstanding_transactions]; // indicates awvalid is received
/* Address Write Channel handshake*/
reg[int_wr_cntr_width-1:0] aw_cnt = 0;// count of awvalid
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] awsize [0:max_wr_outstanding_transactions-1];
reg [axi_prot_width-1:0] awprot [0:max_wr_outstanding_transactions-1];
reg [axi_lock_width-1:0] awlock [0:max_wr_outstanding_transactions-1];
reg [axi_cache_width-1:0] awcache [0:max_wr_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] awbrst [0:max_wr_outstanding_transactions-1];
reg [axi_len_width-1:0] awlen [0:max_wr_outstanding_transactions-1];
reg aw_flag [0:max_wr_outstanding_transactions-1];
reg [addr_width-1:0] awaddr [0:max_wr_outstanding_transactions-1];
reg [id_bus_width-1:0] awid [0:max_wr_outstanding_transactions-1];
reg [axi_qos_width-1:0] awqos [0:max_wr_outstanding_transactions-1];
wire aw_fifo_full; // indicates awvalid_fifo is full (max outstanding transactions reached)
/* internal fifos to store burst write data, ID & strobes*/
reg [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_wr_outstanding_transactions-1];
reg [max_burst_bytes_width:0] burst_valid_bytes [0:max_wr_outstanding_transactions-1]; /// total valid bytes received in a complete burst transfer
reg wlast_flag [0:max_wr_outstanding_transactions-1]; // flag to indicate WLAST received
wire wd_fifo_full;
/* Write Data Channel and Write Response handshake signals*/
reg [int_wr_cntr_width-1:0] wd_cnt = 0;
reg [(data_bus_width*axi_burst_len)-1:0] aligned_wr_data;
reg [addr_width-1:0] aligned_wr_addr;
reg [max_burst_bytes_width:0] valid_data_bytes;
reg [int_wr_cntr_width-1:0] wr_bresp_cnt = 0;
reg [axi_rsp_width-1:0] bresp;
reg [rsp_fifo_bits-1:0] fifo_bresp [0:max_wr_outstanding_transactions-1]; // store the ID and its corresponding response
reg enable_write_bresp;
reg [int_wr_cntr_width-1:0] rd_bresp_cnt = 0;
integer wr_latency_count;
reg wr_delayed;
wire bresp_fifo_empty;
/* states for managing read/write to WR_FIFO */
parameter SEND_DATA = 0, WAIT_ACK = 1;
reg state;
/* Qos*/
reg [axi_qos_width-1:0] ar_qos, aw_qos;
initial begin
if(DEBUG_INFO) begin
if(enable_this_port)
$display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, slave_name);
else
$display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, slave_name);
end
end
initial slave.set_disable_reset_value_checks(1);
initial begin
repeat(2) @(posedge S_ACLK);
if(!enable_this_port) begin
slave.set_channel_level_info(0);
slave.set_function_level_info(0);
end
slave.RESPONSE_TIMEOUT = 0;
end
/*--------------------------------------------------------------------------------*/
/* Set Latency type to be used */
task set_latency_type;
input[1:0] lat;
begin
if(enable_this_port)
latency_type = lat;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. \'Latency Profile\' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set ARQoS to be used */
task set_arqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
ar_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. \'ARQOS\' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set AWQoS to be used */
task set_awqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
aw_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. \'AWQOS\' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* get the wr latency number */
function [31:0] get_wr_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_min; else get_wr_lat_number = gp_wr_min;
AVG_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_avg; else get_wr_lat_number = gp_wr_avg;
WORST_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_max; else get_wr_lat_number = gp_wr_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2\'b00 : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%10+ acp_wr_min); else get_wr_lat_number = ($random()%10+ gp_wr_min);
2\'b01 : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%40+ acp_wr_avg); else get_wr_lat_number = ($random()%40+ gp_wr_avg);
default : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%60+ acp_wr_max); else get_wr_lat_number = ($random()%60+ gp_wr_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* get the rd latency number */
function [31:0] get_rd_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_min; else get_rd_lat_number = gp_rd_min;
AVG_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_avg; else get_rd_lat_number = gp_rd_avg;
WORST_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_max; else get_rd_lat_number = gp_rd_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2\'b00 : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%10+ acp_rd_min); else get_rd_lat_number = ($random()%10+ gp_rd_min);
2\'b01 : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%40+ acp_rd_avg); else get_rd_lat_number = ($random()%40+ gp_rd_avg);
default : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%60+ acp_rd_max); else get_rd_lat_number = ($random()%60+ gp_rd_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Store the Clock cycle time period */
always@(S_RESETN)
begin
if(S_RESETN) begin
@(posedge S_ACLK);
s_aclk_period = $time;
@(posedge S_ACLK);
s_aclk_period = $time - s_aclk_period;
end
end
/*--------------------------------------------------------------------------------*/
/* Check for any WRITE/READs when this port is disabled */
always@(S_AWVALID or S_WVALID or S_ARVALID)
begin
if((S_AWVALID | S_WVALID | S_ARVALID) && !enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. AXI transaction is initiated on this port ...\
Simulation will halt ..",$time, DISP_ERR, slave_name);
$stop;
end
end
/*--------------------------------------------------------------------------------*/
assign net_ARVALID = enable_this_port ? S_ARVALID : 1\'b0;
assign net_AWVALID = enable_this_port ? S_AWVALID : 1\'b0;
assign net_WVALID = enable_this_port ? S_WVALID : 1\'b0;
assign wr_fifo_empty = (wr_fifo_wr_ptr === wr_fifo_rd_ptr)?1\'b1: 1\'b0;
assign aw_fifo_full = ((aw_cnt[int_wr_cntr_width-1] !== rd_bresp_cnt[int_wr_cntr_width-1]) && (aw_cnt[int_wr_cntr_width-2:0] === rd_bresp_cnt[int_wr_cntr_width-2:0]))?1\'b1 :1\'b0; /// complete this
assign wd_fifo_full = ((wd_cnt[int_wr_cntr_width-1] !== rd_bresp_cnt[int_wr_cntr_width-1]) && (wd_cnt[int_wr_cntr_width-2:0] === rd_bresp_cnt[int_wr_cntr_width-2:0]))?1\'b1 :1\'b0; /// complete this
assign bresp_fifo_empty = (wr_bresp_cnt === rd_bresp_cnt)?1\'b1:1\'b0;
/* Store the awvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or S_AWID or S_AWADDR or S_AWVALID )
begin
if(!S_RESETN)
aw_time_cnt <= 0;
else begin
if(S_AWVALID) begin
awvalid_receive_time[aw_time_cnt] <= $time;
awvalid_flag[aw_time_cnt] <= 1\'b1;
aw_time_cnt <= aw_time_cnt + 1;
if(aw_time_cnt === max_wr_outstanding_transactions) aw_time_cnt <= 0;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_AWVALID && S_AWREADY) begin
if(S_AWQOS === 0) awqos[aw_cnt[int_wr_cntr_width-2:0]] = aw_qos;
else awqos[aw_cnt[int_wr_cntr_width-2:0]] = S_AWQOS;
end
end
/*--------------------------------------------------------------------------------*/
always@(aw_fifo_full)
begin
if(aw_fifo_full && DEBUG_INFO)
$display("[%0d] : %0s : %0s : Reached the maximum outstanding Write transactions limit (%0d). Blocking all future Write transactions until at least 1 of the outstanding Write transaction has completed.",$time, DISP_INFO, slave_name,max_wr_outstanding_transactions);
end
/*--------------------------------------------------------------------------------*/
/* Address Write Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
aw_cnt <= 0;
end else begin
if(!aw_fifo_full) begin
slave.RECEIVE_WRITE_ADDRESS(0,
id_invalid,
awaddr[aw_cnt[int_wr_cntr_width-2:0]],
awlen[aw_cnt[int_wr_cntr_width-2:0]],
awsize[aw_cnt[int_wr_cntr_width-2:0]],
awbrst[aw_cnt[int_wr_cntr_width-2:0]],
awlock[aw_cnt[int_wr_cntr_width-2:0]],
awcache[aw_cnt[int_wr_cntr_width-2:0]],
awprot[aw_cnt[int_wr_cntr_width-2:0]],
awid[aw_cnt[int_wr_cntr_width-2:0]]); /// sampled valid ID.
aw_flag[aw_cnt[int_wr_cntr_width-2:0]] <= 1;
aw_cnt <= aw_cnt + 1;
if(aw_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
aw_cnt[int_wr_cntr_width-1] <= ~aw_cnt[int_wr_cntr_width-1];
aw_cnt[int_wr_cntr_width-2:0] <= 0;
end
end // if (!aw_fifo_full)
end /// if else
end /// always
/*--------------------------------------------------------------------------------*/
/* Write Data Channel Handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wd_cnt <= 0;
end else begin
if(!wd_fifo_full && S_WVALID) begin
slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID,
burst_data[wd_cnt[int_wr_cntr_width-2:0]],
burst_valid_bytes[wd_cnt[int_wr_cntr_width-2:0]]);
wlast_flag[wd_cnt[int_wr_cntr_width-2:0]] <= 1\'b1;
wd_cnt <= wd_cnt + 1;
if(wd_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
wd_cnt[int_wr_cntr_width-1] <= ~wd_cnt[int_wr_cntr_width-1];
wd_cnt[int_wr_cntr_width-2:0] <= 0;
end
end /// if
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
/* Align the wrap data for write transaction */
task automatic get_wrap_aligned_wr_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
output [addr_width-1:0] start_addr; /// aligned start address
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
wrp_data = wrp_data << ((data_bus_width*axi_burst_len) - (v_bytes*8));
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data << 8;
temp_data[7:0] = wrp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8];
wrp_data = wrp_data << 8;
wrp_bytes = wrp_bytes - 1;
end
wrp_bytes = addr - start_addr;
wrp_data = b_data << (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
/* Calculate the Response for each read/write transaction */
function [axi_rsp_width-1:0] calculate_resp;
input rd_wr; // indicates Read(1) or Write(0) transaction
input [addr_width-1:0] awaddr;
input [axi_prot_width-1:0] awprot;
reg [axi_rsp_width-1:0] rsp;
begin
rsp = AXI_OK;
/* Address Decode */
if(decode_address(awaddr) === INVALID_MEM_TYPE) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) ",$time, DISP_ERR, slave_name, awaddr);
end
if(!rd_wr && decode_address(awaddr) === REG_MEM) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Write to Register Map(0x%0h) is not supported ",$time, DISP_ERR, slave_name, awaddr);
end
if(secure_access_enabled && awprot[1])
rsp = AXI_DEC_ERR; // decode error
calculate_resp = rsp;
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Store the Write response for each write transaction */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wr_bresp_cnt <= 0;
wr_fifo_wr_ptr <= 0;
end else begin
enable_write_bresp = aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] && wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]];
/* calculate bresp only when AWVALID && WLAST is received */
if(enable_write_bresp) begin
aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] <= 0;
wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] <= 0;
bresp = calculate_resp(1\'b0, awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]],awprot[wr_bresp_cnt[int_wr_cntr_width-2:0]]);
fifo_bresp[wr_bresp_cnt[int_wr_cntr_width-2:0]] <= {awid[wr_bresp_cnt[int_wr_cntr_width-2:0]],bresp};
/* Fill WR data FIFO */
if(bresp === AXI_OK) begin
if(awbrst[wr_bresp_cnt[int_wr_cntr_width-2:0]] === AXI_WRAP) begin /// wrap type? then align the data
get_wrap_aligned_wr_data(aligned_wr_data,aligned_wr_addr, awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_data[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-2:0]]); /// gives wrapped start address
end else begin
aligned_wr_data = burst_data[wr_bresp_cnt[int_wr_cntr_width-2:0]];
aligned_wr_addr = awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]] ;
end
valid_data_bytes = burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-2:0]];
end else
valid_data_bytes = 0;
wr_fifo[wr_fifo_wr_ptr[int_wr_cntr_width-2:0]] = {awqos[wr_bresp_cnt[int_wr_cntr_width-2:0]], aligned_wr_data, aligned_wr_addr, valid_data_bytes};
wr_fifo_wr_ptr = wr_fifo_wr_ptr + 1;
wr_bresp_cnt <= wr_bresp_cnt+1;
if(wr_bresp_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
wr_bresp_cnt[int_wr_cntr_width-1] <= ~ wr_bresp_cnt[int_wr_cntr_width-1];
wr_bresp_cnt[int_wr_cntr_width-2:0] <= 0;
end
end
end // else
end // always
/*--------------------------------------------------------------------------------*/
/* Send Write Response Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
rd_bresp_cnt <= 0;
wr_latency_count = get_wr_lat_number(1);
wr_delayed = 0;
bresp_time_cnt <= 0;
end else begin
wr_delayed = 1\'b0;
if(awvalid_flag[bresp_time_cnt] && (($time - awvalid_receive_time[bresp_time_cnt])/s_aclk_period >= wr_latency_count))
wr_delayed = 1;
if(!bresp_fifo_empty && wr_delayed) begin
slave.SEND_WRITE_RESPONSE(fifo_bresp[rd_bresp_cnt[int_wr_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb], // ID
fifo_bresp[rd_bresp_cnt[int_wr_cntr_width-2:0]][rsp_msb : rsp_lsb] // Response
);
wr_delayed = 0;
awvalid_flag[bresp_time_cnt] = 1\'b0;
bresp_time_cnt <= bresp_time_cnt+1;
rd_bresp_cnt <= rd_bresp_cnt + 1;
if(rd_bresp_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
rd_bresp_cnt[int_wr_cntr_width-1] <= ~ rd_bresp_cnt[int_wr_cntr_width-1];
rd_bresp_cnt[int_wr_cntr_width-2:0] <= 0;
end
if(bresp_time_cnt === max_wr_outstanding_transactions) begin
bresp_time_cnt <= 0;
end
wr_latency_count = get_wr_lat_number(1);
end
end // else
end//always
/*--------------------------------------------------------------------------------*/
/* Reading from the wr_fifo */
always@(negedge S_RESETN or posedge SW_CLK) begin
if(!S_RESETN) begin
WR_DATA_VALID_DDR = 1\'b0;
WR_DATA_VALID_OCM = 1\'b0;
wr_fifo_rd_ptr = 0;
state = SEND_DATA;
WR_QOS = 0;
end else begin
case(state)
SEND_DATA :begin
state = SEND_DATA;
WR_DATA_VALID_OCM = 0;
WR_DATA_VALID_DDR = 0;
if(!wr_fifo_empty) begin
WR_DATA = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_data_msb : wr_data_lsb];
WR_ADDR = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_addr_msb : wr_addr_lsb];
WR_BYTES = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_bytes_msb : wr_bytes_lsb];
WR_QOS = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_qos_msb : wr_qos_lsb];
state = WAIT_ACK;
case (decode_address(wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_addr_msb : wr_addr_lsb]))
OCM_MEM : WR_DATA_VALID_OCM = 1;
DDR_MEM : WR_DATA_VALID_DDR = 1;
default : state = SEND_DATA;
endcase
wr_fifo_rd_ptr = wr_fifo_rd_ptr+1;
end
end
WAIT_ACK :begin
state = WAIT_ACK;
if(WR_DATA_ACK_OCM | WR_DATA_ACK_DDR) begin
WR_DATA_VALID_OCM = 1\'b0;
WR_DATA_VALID_DDR = 1\'b0;
state = SEND_DATA;
end
end
endcase
end
end
/*--------------------------------------------------------------------------------*/
/*-------------------------------- WRITE HANDSHAKE END ----------------------------------------*/
/*-------------------------------- READ HANDSHAKE ---------------------------------------------*/
/* READ CHANNELS */
/* Store the arvalid receive time --- necessary for calculating latency in sending the rresp latency */
reg [7:0] ar_time_cnt = 0,rresp_time_cnt = 0;
real arvalid_receive_time[0:max_rd_outstanding_transactions]; // store the time when a new arvalid is received
reg arvalid_flag[0:max_rd_outstanding_transactions]; // store the time when a new arvalid is received
reg [int_rd_cntr_width-1:0] ar_cnt = 0; // counter for arvalid info
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] arsize [0:max_rd_outstanding_transactions-1];
reg [axi_prot_width-1:0] arprot [0:max_rd_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] arbrst [0:max_rd_outstanding_transactions-1];
reg [axi_len_width-1:0] arlen [0:max_rd_outstanding_transactions-1];
reg [axi_cache_width-1:0] arcache [0:max_rd_outstanding_transactions-1];
reg [axi_lock_width-1:0] arlock [0:max_rd_outstanding_transactions-1];
reg ar_flag [0:max_rd_outstanding_transactions-1];
reg [addr_width-1:0] araddr [0:max_rd_outstanding_transactions-1];
reg [id_bus_width-1:0] arid [0:max_rd_outstanding_transactions-1];
reg [axi_qos_width-1:0] arqos [0:max_rd_outstanding_transactions-1];
wire ar_fifo_full; // indicates arvalid_fifo is full (max outstanding transactions reached)
reg [int_rd_cntr_width-1:0] rd_cnt = 0;
reg [int_rd_cntr_width-1:0] wr_rresp_cnt = 0;
reg [axi_rsp_width-1:0] rresp;
reg [rsp_fifo_bits-1:0] fifo_rresp [0:max_rd_outstanding_transactions-1]; // store the ID and its corresponding response
/* Send Read Response & Data Channel handshake */
integer rd_latency_count;
reg rd_delayed;
reg [max_burst_bits-1:0] read_fifo [0:max_rd_outstanding_transactions-1]; /// Store only AXI Burst Data ..
reg [int_rd_cntr_width-1:0] rd_fifo_wr_ptr = 0, rd_fifo_rd_ptr = 0;
wire read_fifo_full;
assign read_fifo_full = (rd_fifo_wr_ptr[int_rd_cntr_width-1] !== rd_fifo_rd_ptr[int_rd_cntr_width-1] && rd_fifo_wr_ptr[int_rd_cntr_width-2:0] === rd_fifo_rd_ptr[int_rd_cntr_width-2:0])?1\'b1: 1\'b0;
assign read_fifo_empty = (rd_fifo_wr_ptr === rd_fifo_rd_ptr)?1\'b1: 1\'b0;
assign ar_fifo_full = ((ar_cnt[int_rd_cntr_width-1] !== rd_cnt[int_rd_cntr_width-1]) && (ar_cnt[int_rd_cntr_width-2:0] === rd_cnt[int_rd_cntr_width-2:0]))?1\'b1 :1\'b0;
/* Store the arvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or S_ARID or S_ARADDR or S_ARVALID )
begin
if(!S_RESETN)
ar_time_cnt <= 0;
else begin
if(S_ARVALID) begin
arvalid_receive_time[ar_time_cnt] <= $time;
arvalid_flag[ar_time_cnt] <= 1\'b1;
ar_time_cnt <= ar_time_cnt + 1;
if(ar_time_cnt === max_rd_outstanding_transactions)
ar_time_cnt <= 0;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_ARVALID && S_ARREADY) begin
if(S_ARQOS === 0) arqos[aw_cnt[int_rd_cntr_width-2:0]] = ar_qos;
else arqos[aw_cnt[int_rd_cntr_width-2:0]] = S_ARQOS;
end
end
/*--------------------------------------------------------------------------------*/
always@(ar_fifo_full)
begin
if(ar_fifo_full && DEBUG_INFO)
$display("[%0d] : %0s : %0s : Reached the maximum outstanding Read transactions limit (%0d). Blocking all future Read transactions until at least 1 of the outstanding Read transaction has completed.",$time, DISP_INFO, slave_name,max_rd_outstanding_transactions);
end
/*--------------------------------------------------------------------------------*/
/* Address Read Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
ar_cnt <= 0;
end else begin
if(!ar_fifo_full) begin
slave.RECEIVE_READ_ADDRESS(0,
id_invalid,
araddr[ar_cnt[int_rd_cntr_width-2:0]],
arlen[ar_cnt[int_rd_cntr_width-2:0]],
arsize[ar_cnt[int_rd_cntr_width-2:0]],
arbrst[ar_cnt[int_rd_cntr_width-2:0]],
arlock[ar_cnt[int_rd_cntr_width-2:0]],
arcache[ar_cnt[int_rd_cntr_width-2:0]],
arprot[ar_cnt[int_rd_cntr_width-2:0]],
arid[ar_cnt[int_rd_cntr_width-2:0]]); /// sampled valid ID.
ar_flag[ar_cnt[int_rd_cntr_width-2:0]] <= 1\'b1;
ar_cnt <= ar_cnt+1;
if(ar_cnt[int_rd_cntr_width-2:0] === max_rd_outstanding_transactions-1) begin
ar_cnt[int_rd_cntr_width-1] <= ~ ar_cnt[int_rd_cntr_width-1];
ar_cnt[int_rd_cntr_width-2:0] <= 0;
end
end /// if(!ar_fifo_full)
end /// if else
end /// always*/
/*--------------------------------------------------------------------------------*/
/* Align Wrap data for read transaction*/
task automatic get_wrap_aligned_rd_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [addr_width-1:0] start_addr;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data >> 8;
temp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8] = wrp_data[7:0];
wrp_data = wrp_data >> 8;
wrp_bytes = wrp_bytes - 1;
end
temp_data = temp_data >> ((data_bus_width*axi_burst_len) - (v_bytes*8));
wrp_bytes = addr - start_addr;
wrp_data = b_data >> (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
parameter RD_DATA_REQ = 1\'b0, WAIT_RD_VALID = 1\'b1;
reg [addr_width-1:0] temp_read_address;
reg [max_burst_bytes_width:0] temp_rd_valid_bytes;
reg rd_fifo_state;
reg invalid_rd_req;
/* get the data from memory && also calculate the rresp*/
always@(negedge S_RESETN or posedge SW_CLK)
begin
if(!S_RESETN)begin
rd_fifo_wr_ptr <= 0;
wr_rresp_cnt <=0;
rd_fifo_state <= RD_DATA_REQ;
temp_rd_valid_bytes = 0;
temp_read_address <= 0;
RD_REQ_DDR <= 0;
RD_REQ_OCM <= 0;
RD_REQ_REG <= 0;
RD_QOS <= 0;
invalid_rd_req <= 0;
end else begin
case(rd_fifo_state)
RD_DATA_REQ : begin
rd_fifo_state <= RD_DATA_REQ;
RD_REQ_DDR <= 0;
RD_REQ_OCM <= 0;
RD_REQ_REG <= 0;
RD_QOS <= 0;
if(ar_flag[wr_rresp_cnt[int_rd_cntr_width-2:0]] && !read_fifo_full) begin
ar_flag[wr_rresp_cnt[int_rd_cntr_width-2:0]] <= 0;
rresp = calculate_resp(1\'b1, araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]],arprot[wr_rresp_cnt[int_rd_cntr_width-2:0]]);
fifo_rresp[wr_rresp_cnt[int_rd_cntr_width-2:0]] <= {arid[wr_rresp_cnt[int_rd_cntr_width-2:0]],rresp};
temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_rd_cntr_width-2:0]]+1)*(2**arsize[wr_rresp_cnt[int_rd_cntr_width-2:0]]);//data_bus_width/8;
if(arbrst[wr_rresp_cnt[int_rd_cntr_width-2:0]] === AXI_WRAP) /// wrap begin
temp_read_address = (araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes;
else
temp_read_address = araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]];
if(rresp === AXI_OK) begin
case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]);
OCM_MEM : RD_REQ_OCM <= 1;
DDR_MEM : RD_REQ_DDR <= 1;
REG_MEM : RD_REQ_REG <= 1;
default : invalid_rd_req <= 1;
endcase
end else
invalid_rd_req <= 1;
RD_QOS <= arqos[wr_rresp_cnt[int_rd_cntr_width-2:0]];
RD_ADDR <= temp_read_address; ///araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]];
RD_BYTES <= temp_rd_valid_bytes;
rd_fifo_state <= WAIT_RD_VALID;
wr_rresp_cnt <= wr_rresp_cnt + 1;
if(wr_rresp_cnt[int_rd_cntr_width-2:0] === max_rd_outstanding_transactions-1) begin
wr_rresp_cnt[int_rd_cntr_width-1] <= ~ wr_rresp_cnt[int_rd_cntr_width-1];
wr_rresp_cnt[int_rd_cntr_width-2:0] <= 0;
end
end
end
WAIT_RD_VALID : begin
rd_fifo_state <= WAIT_RD_VALID;
if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | RD_DATA_VALID_REG | invalid_rd_req) begin ///temp_dec == 2\'b11) begin
if(RD_DATA_VALID_DDR)
read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] <= RD_DATA_DDR;
else if(RD_DATA_VALID_OCM)
read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] <= RD_DATA_OCM;
else if(RD_DATA_VALID_REG)
read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] <= RD_DATA_REG;
else
read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] <= 0;
rd_fifo_wr_ptr <= rd_fifo_wr_ptr + 1;
RD_REQ_DDR <= 0;
RD_REQ_OCM <= 0;
RD_REQ_REG <= 0;
RD_QOS <= 0;
invalid_rd_req <= 0;
rd_fifo_state <= RD_DATA_REQ;
end
end
endcase
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
reg[max_burst_bytes_width:0] rd_v_b;
reg [(data_bus_width*axi_burst_len)-1:0] temp_read_data;
reg [(data_bus_width*axi_burst_len)-1:0] temp_wrap_data;
reg[(axi_rsp_width*axi_burst_len)-1:0] temp_read_rsp;
/* Read Data Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN)begin
rd_fifo_rd_ptr <= 0;
rd_cnt <= 0;
rd_latency_count <= get_rd_lat_number(1);
rd_delayed = 0;
rresp_time_cnt <= 0;
rd_v_b = 0;
end else begin
if(arvalid_flag[rresp_time_cnt] && ((($time - arvalid_receive_time[rresp_time_cnt])/s_aclk_period) >= rd_latency_count))
rd_delayed = 1;
if(!read_fifo_empty && rd_delayed)begin
rd_delayed = 0;
arvalid_flag[rresp_time_cnt] = 1\'b0;
rd_v_b = ((arlen[rd_cnt[int_rd_cntr_width-2:0]]+1)*(2**arsize[rd_cnt[int_rd_cntr_width-2:0]]));
temp_read_data = read_fifo[rd_fifo_rd_ptr[int_rd_cntr_width-2:0]];
rd_fifo_rd_ptr <= rd_fifo_rd_ptr+1;
if(arbrst[rd_cnt[int_rd_cntr_width-2:0]]=== AXI_WRAP) begin
get_wrap_aligned_rd_data(temp_wrap_data, araddr[rd_cnt[int_rd_cntr_width-2:0]], temp_read_data, rd_v_b);
temp_read_data = temp_wrap_data;
end
temp_read_rsp = 0;
repeat(axi_burst_len) begin
temp_read_rsp = temp_read_rsp >> axi_rsp_width;
temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = fifo_rresp[rd_cnt[int_rd_cntr_width-2:0]][rsp_msb : rsp_lsb];
end
slave.SEND_READ_BURST_RESP_CTRL(arid[rd_cnt[int_rd_cntr_width-2:0]],
araddr[rd_cnt[int_rd_cntr_width-2:0]],
arlen[rd_cnt[int_rd_cntr_width-2:0]],
arsize[rd_cnt[int_rd_cntr_width-2:0]],
arbrst[rd_cnt[int_rd_cntr_width-2:0]],
temp_read_data,
temp_read_rsp);
rd_cnt <= rd_cnt + 1;
rresp_time_cnt <= rresp_time_cnt+1;
if(rresp_time_cnt === max_rd_outstanding_transactions) rresp_time_cnt <= 0;
if(rd_cnt[int_rd_cntr_width-2:0] === (max_rd_outstanding_transactions-1)) begin
rd_cnt[int_rd_cntr_width-1] <= ~ rd_cnt[int_rd_cntr_width-1];
rd_cnt[int_rd_cntr_width-2:0] <= 0;
end
rd_latency_count <= get_rd_lat_number(1);
end
end /// else
end /// always
endmodule
|
// -- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Description: N-deep SRL pipeline element with generic single-channel AXI interfaces.
// Interface outputs are synchronized using ordinary flops for improved timing.
//--------------------------------------------------------------------------
// Structure:
// axic_reg_srl_fifo
// ndeep_srl
// nto1_mux
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_axic_reg_srl_fifo #
(
parameter C_FAMILY = "none", // FPGA Family
parameter integer C_FIFO_WIDTH = 1, // Width of S_MESG/M_MESG.
parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits
// the control logic can be used
// on before the control logic
// needs to be replicated.
parameter integer C_FIFO_DEPTH_LOG = 2, // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.
// The minimum size fifo generated is 4-deep.
parameter C_USE_FULL = 1 // Prevent overwrite by throttling S_READY.
)
(
input wire ACLK, // Clock
input wire ARESET, // Reset
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Input data
input wire S_VALID, // Input data valid
output wire S_READY, // Input data ready
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Output data
output wire M_VALID, // Output data valid
input wire M_READY // Output data ready
);
localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;
localparam P_EMPTY = {P_FIFO_DEPTH_LOG{1\'b1}};
localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1\'b0}};
localparam P_ALMOSTFULL_TEMP = {P_EMPTY, 1\'b0};
localparam P_ALMOSTFULL = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];
localparam P_NUM_REPS = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?
(C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :
((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;
(* syn_keep = "1" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr;
(* syn_keep = "1" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;
genvar i;
genvar j;
reg m_valid_i;
reg s_ready_i;
wire push; // FIFO push
wire pop; // FIFO pop
reg areset_d1; // Reset delay register
reg [C_FIFO_WIDTH-1:0] storage_data1;
wire [C_FIFO_WIDTH-1:0] storage_data2; // Intermediate SRL data
reg load_s1;
wire load_s1_from_s2;
reg [1:0] state;
localparam [1:0]
ZERO = 2\'b10,
ONE = 2\'b11,
TWO = 2\'b01;
assign M_VALID = m_valid_i;
assign S_READY = C_USE_FULL ? s_ready_i : 1\'b1;
assign push = (S_VALID & (C_USE_FULL ? s_ready_i : 1\'b1) & (state == TWO)) | (~M_READY & S_VALID & (state == ONE));
assign pop = M_READY & (state == TWO);
assign M_MESG = storage_data1;
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_MESG;
end
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1\'b1;
else
load_s1 = 1\'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK)
begin
if (areset_d1) begin
state <= ZERO;
m_valid_i <= 1\'b0;
end else begin
case (state)
// No transaction stored locally
ZERO: begin
if (S_VALID) begin
state <= ONE; // Got one so move to ONE
m_valid_i <= 1\'b1;
end
end
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) begin
state <= ZERO; // Read out one so move to ZERO
m_valid_i <= 1\'b0;
end else if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
m_valid_i <= 1\'b1;
end
end
// TWO transaction stored locally
TWO: begin
if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTEMPTY) && pop && ~push) begin
state <= ONE; // Read out one so move to ONE
m_valid_i <= 1\'b1;
end
end
endcase // case (state)
end
end // always @ (posedge ACLK)
generate
//---------------------------------------------------------------------------
// Create count of number of elements in FIFOs
//---------------------------------------------------------------------------
for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep
assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] =
push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;
always @(posedge ACLK) begin
if (ARESET)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
{P_FIFO_DEPTH_LOG{1\'b1}};
else if (push ^ pop)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];
end
end
always @(posedge ACLK) begin
if (ARESET) begin
s_ready_i <= 1\'b0;
end else if (areset_d1) begin
s_ready_i <= 1\'b1;
end else if (C_USE_FULL &&
((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTFULL) && push && ~pop)) begin
s_ready_i <= 1\'b0;
end else if (C_USE_FULL && pop) begin
s_ready_i <= 1\'b1;
end
end
//---------------------------------------------------------------------------
// Instantiate SRLs
//---------------------------------------------------------------------------
for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls
for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep
axi_data_fifo_v2_1_ndeep_srl #
(
.C_FAMILY (C_FAMILY),
.C_A_WIDTH (P_FIFO_DEPTH_LOG)
)
srl_nx1
(
.CLK (ACLK),
.A (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:
P_FIFO_DEPTH_LOG*(i)]),
.CE (push),
.D (S_MESG[i*C_MAX_CTRL_FANOUT+j]),
.Q (storage_data2[i*C_MAX_CTRL_FANOUT+j])
);
end
end
endgenerate
endmodule
`default_nettype wire
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: decerr_slave.v
//
// Description:
// Phantom slave interface used to complete W, R and B channel transfers when an
// erroneous transaction is trapped in the crossbar.
//--------------------------------------------------------------------------
//
// Structure:
// decerr_slave
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_decerr_slave #
(
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_RESP = 2\'b11
)
(
input wire S_AXI_ACLK,
input wire S_AXI_ARESET,
input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_AWID,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
input wire S_AXI_WLAST,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_BID,
output wire [1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_ARID,
input wire [7:0] S_AXI_ARLEN,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_RID,
output wire [(C_AXI_DATA_WIDTH-1):0] S_AXI_RDATA,
output wire [1:0] S_AXI_RRESP,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RLAST,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY
);
reg s_axi_awready_i;
reg s_axi_wready_i;
reg s_axi_bvalid_i;
reg s_axi_arready_i;
reg s_axi_rvalid_i;
localparam P_WRITE_IDLE = 2\'b00;
localparam P_WRITE_DATA = 2\'b01;
localparam P_WRITE_RESP = 2\'b10;
localparam P_READ_IDLE = 1\'b0;
localparam P_READ_DATA = 1\'b1;
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
assign S_AXI_BRESP = C_RESP;
assign S_AXI_RRESP = C_RESP;
assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1\'b0}};
assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1\'b0}};
assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1\'b0}};
assign S_AXI_AWREADY = s_axi_awready_i;
assign S_AXI_WREADY = s_axi_wready_i;
assign S_AXI_BVALID = s_axi_bvalid_i;
assign S_AXI_ARREADY = s_axi_arready_i;
assign S_AXI_RVALID = s_axi_rvalid_i;
generate
if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_axilite
assign S_AXI_RLAST = 1\'b1;
assign S_AXI_BID = 0;
assign S_AXI_RID = 0;
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESET) begin
s_axi_awready_i <= 1\'b0;
s_axi_wready_i <= 1\'b0;
s_axi_bvalid_i <= 1\'b0;
end else begin
if (s_axi_bvalid_i) begin
if (S_AXI_BREADY) begin
s_axi_bvalid_i <= 1\'b0;
end
end else if (S_AXI_AWVALID & S_AXI_WVALID) begin
if (s_axi_awready_i) begin
s_axi_awready_i <= 1\'b0;
s_axi_wready_i <= 1\'b0;
s_axi_bvalid_i <= 1\'b1;
end else begin
s_axi_awready_i <= 1\'b1;
s_axi_wready_i <= 1\'b1;
end
end
end
end
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESET) begin
s_axi_arready_i <= 1\'b0;
s_axi_rvalid_i <= 1\'b0;
end else begin
if (s_axi_rvalid_i) begin
if (S_AXI_RREADY) begin
s_axi_rvalid_i <= 1\'b0;
end
end else if (S_AXI_ARVALID & s_axi_arready_i) begin
s_axi_arready_i <= 1\'b0;
s_axi_rvalid_i <= 1\'b1;
end else begin
s_axi_arready_i <= 1\'b1;
end
end
end
end else begin : gen_axi
reg s_axi_rlast_i;
reg [(C_AXI_ID_WIDTH-1):0] s_axi_bid_i;
reg [(C_AXI_ID_WIDTH-1):0] s_axi_rid_i;
reg [7:0] read_cnt;
reg [1:0] write_cs;
reg [0:0] read_cs;
assign S_AXI_RLAST = s_axi_rlast_i;
assign S_AXI_BID = s_axi_bid_i;
assign S_AXI_RID = s_axi_rid_i;
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESET) begin
write_cs <= P_WRITE_IDLE;
s_axi_awready_i <= 1\'b0;
s_axi_wready_i <= 1\'b0;
s_axi_bvalid_i <= 1\'b0;
s_axi_bid_i <= 0;
end else begin
case (write_cs)
P_WRITE_IDLE:
begin
if (S_AXI_AWVALID & s_axi_awready_i) begin
s_axi_awready_i <= 1\'b0;
s_axi_bid_i <= S_AXI_AWID;
s_axi_wready_i <= 1\'b1;
write_cs <= P_WRITE_DATA;
end else begin
s_axi_awready_i <= 1\'b1;
end
end
P_WRITE_DATA:
begin
if (S_AXI_WVALID & S_AXI_WLAST) begin
s_axi_wready_i <= 1\'b0;
s_axi_bvalid_i <= 1\'b1;
write_cs <= P_WRITE_RESP;
end
end
P_WRITE_RESP:
begin
if (S_AXI_BREADY) begin
s_axi_bvalid_i <= 1\'b0;
s_axi_awready_i <= 1\'b1;
write_cs <= P_WRITE_IDLE;
end
end
endcase
end
end
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESET) begin
read_cs <= P_READ_IDLE;
s_axi_arready_i <= 1\'b0;
s_axi_rvalid_i <= 1\'b0;
s_axi_rlast_i <= 1\'b0;
s_axi_rid_i <= 0;
read_cnt <= 0;
end else begin
case (read_cs)
P_READ_IDLE:
begin
if (S_AXI_ARVALID & s_axi_arready_i) begin
s_axi_arready_i <= 1\'b0;
s_axi_rid_i <= S_AXI_ARID;
read_cnt <= S_AXI_ARLEN;
s_axi_rvalid_i <= 1\'b1;
if (S_AXI_ARLEN == 0) begin
s_axi_rlast_i <= 1\'b1;
end else begin
s_axi_rlast_i <= 1\'b0;
end
read_cs <= P_READ_DATA;
end else begin
s_axi_arready_i <= 1\'b1;
end
end
P_READ_DATA:
begin
if (S_AXI_RREADY) begin
if (read_cnt == 0) begin
s_axi_rvalid_i <= 1\'b0;
s_axi_rlast_i <= 1\'b0;
s_axi_arready_i <= 1\'b1;
read_cs <= P_READ_IDLE;
end else begin
if (read_cnt == 1) begin
s_axi_rlast_i <= 1\'b1;
end
read_cnt <= read_cnt - 1;
end
end
end
endcase
end
end
end
endgenerate
endmodule
`default_nettype wire
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized Mux from 2:1 upto 16:1.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_mux #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_SEL_WIDTH = 4,
// Data width for comparator.
parameter integer C_DATA_WIDTH = 2
// Data width for comparator.
)
(
input wire [C_SEL_WIDTH-1:0] S,
input wire [(2**C_SEL_WIDTH)*C_DATA_WIDTH-1:0] A,
output wire [C_DATA_WIDTH-1:0] O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" || C_SEL_WIDTH < 3 ) begin : USE_RTL
assign O = A[(S)*C_DATA_WIDTH +: C_DATA_WIDTH];
end else begin : USE_FPGA
wire [C_DATA_WIDTH-1:0] C;
wire [C_DATA_WIDTH-1:0] D;
// Lower half recursively.
generic_baseblocks_v2_1_mux #
(
.C_FAMILY (C_FAMILY),
.C_SEL_WIDTH (C_SEL_WIDTH-1),
.C_DATA_WIDTH (C_DATA_WIDTH)
) mux_c_inst
(
.S (S[C_SEL_WIDTH-2:0]),
.A (A[(2**(C_SEL_WIDTH-1))*C_DATA_WIDTH-1 : 0]),
.O (C)
);
// Upper half recursively.
generic_baseblocks_v2_1_mux #
(
.C_FAMILY (C_FAMILY),
.C_SEL_WIDTH (C_SEL_WIDTH-1),
.C_DATA_WIDTH (C_DATA_WIDTH)
) mux_d_inst
(
.S (S[C_SEL_WIDTH-2:0]),
.A (A[(2**C_SEL_WIDTH)*C_DATA_WIDTH-1 : (2**(C_SEL_WIDTH-1))*C_DATA_WIDTH]),
.O (D)
);
// Generate instantiated generic_baseblocks_v2_1_mux components as required.
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : NUM
if ( C_SEL_WIDTH == 4 ) begin : USE_F8
MUXF8 muxf8_inst
(
.I0 (C[bit_cnt]),
.I1 (D[bit_cnt]),
.S (S[C_SEL_WIDTH-1]),
.O (O[bit_cnt])
);
end else if ( C_SEL_WIDTH == 3 ) begin : USE_F7
MUXF7 muxf7_inst
(
.I0 (C[bit_cnt]),
.I1 (D[bit_cnt]),
.S (S[C_SEL_WIDTH-1]),
.O (O[bit_cnt])
);
end // C_SEL_WIDTH
end // end for bit_cnt
end
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Address AXI3 Slave Converter
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// a_axi3_conv
// axic_fifo
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_a_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_AUSER_WIDTH = 1,
parameter integer C_AXI_CHANNEL = 0,
// 0 = AXI AW Channel.
// 1 = AXI AR Channel.
parameter integer C_SUPPORT_SPLITTING = 1,
// Implement transaction splitting logic.
// Disabled whan all connected masters are AXI3 and have same or narrower data width.
parameter integer C_SUPPORT_BURSTS = 1,
// Disabled when all connected masters are AxiLite,
// allowing logic to be simplified.
parameter integer C_SINGLE_THREAD = 1
// 0 = Ignore ID when propagating transactions (assume all responses are in order).
// 1 = Enforce single-threading (one ID at a time) when any outstanding or
// requested transaction requires splitting.
// While no split is ongoing any new non-split transaction will pass immediately regardless
// off ID.
// A split transaction will stall if there are multiple ID (non-split) transactions
// ongoing, once it has been forwarded only transactions with the same ID is allowed
// (split or not) until all ongoing split transactios has been completed.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Command Interface (W/R)
output wire cmd_valid,
output wire cmd_split,
output wire [C_AXI_ID_WIDTH-1:0] cmd_id,
output wire [4-1:0] cmd_length,
input wire cmd_ready,
// Command Interface (B)
output wire cmd_b_valid,
output wire cmd_b_split,
output wire [4-1:0] cmd_b_repeat,
input wire cmd_b_ready,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AADDR,
input wire [8-1:0] S_AXI_ALEN,
input wire [3-1:0] S_AXI_ASIZE,
input wire [2-1:0] S_AXI_ABURST,
input wire [1-1:0] S_AXI_ALOCK,
input wire [4-1:0] S_AXI_ACACHE,
input wire [3-1:0] S_AXI_APROT,
input wire [4-1:0] S_AXI_AQOS,
input wire [C_AXI_AUSER_WIDTH-1:0] S_AXI_AUSER,
input wire S_AXI_AVALID,
output wire S_AXI_AREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AADDR,
output wire [4-1:0] M_AXI_ALEN,
output wire [3-1:0] M_AXI_ASIZE,
output wire [2-1:0] M_AXI_ABURST,
output wire [2-1:0] M_AXI_ALOCK,
output wire [4-1:0] M_AXI_ACACHE,
output wire [3-1:0] M_AXI_APROT,
output wire [4-1:0] M_AXI_AQOS,
output wire [C_AXI_AUSER_WIDTH-1:0] M_AXI_AUSER,
output wire M_AXI_AVALID,
input wire M_AXI_AREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for burst types.
localparam [2-1:0] C_FIX_BURST = 2\'b00;
localparam [2-1:0] C_INCR_BURST = 2\'b01;
localparam [2-1:0] C_WRAP_BURST = 2\'b10;
// Depth for command FIFO.
localparam integer C_FIFO_DEPTH_LOG = 5;
// Constants used to generate size mask.
localparam [C_AXI_ADDR_WIDTH+8-1:0] C_SIZE_MASK = {{C_AXI_ADDR_WIDTH{1\'b1}}, 8\'b0000_0000};
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Access decoding related signals.
wire access_is_incr;
wire [4-1:0] num_transactions;
wire incr_need_to_split;
reg [C_AXI_ADDR_WIDTH-1:0] next_mi_addr;
reg split_ongoing;
reg [4-1:0] pushed_commands;
reg [16-1:0] addr_step;
reg [16-1:0] first_step;
wire [8-1:0] first_beats;
reg [C_AXI_ADDR_WIDTH-1:0] size_mask;
// Access decoding related signals for internal pipestage.
reg access_is_incr_q;
reg incr_need_to_split_q;
wire need_to_split_q;
reg [4-1:0] num_transactions_q;
reg [16-1:0] addr_step_q;
reg [16-1:0] first_step_q;
reg [C_AXI_ADDR_WIDTH-1:0] size_mask_q;
// Command buffer help signals.
reg [C_FIFO_DEPTH_LOG:0] cmd_depth;
reg cmd_empty;
reg [C_AXI_ID_WIDTH-1:0] queue_id;
wire id_match;
wire cmd_id_check;
wire s_ready;
wire cmd_full;
wire allow_this_cmd;
wire allow_new_cmd;
wire cmd_push;
reg cmd_push_block;
reg [C_FIFO_DEPTH_LOG:0] cmd_b_depth;
reg cmd_b_empty;
wire cmd_b_full;
wire cmd_b_push;
reg cmd_b_push_block;
wire pushed_new_cmd;
wire last_incr_split;
wire last_split;
wire first_split;
wire no_cmd;
wire allow_split_cmd;
wire almost_empty;
wire no_b_cmd;
wire allow_non_split_cmd;
wire almost_b_empty;
reg multiple_id_non_split;
reg split_in_progress;
// Internal Command Interface signals (W/R).
wire cmd_split_i;
wire [C_AXI_ID_WIDTH-1:0] cmd_id_i;
reg [4-1:0] cmd_length_i;
// Internal Command Interface signals (B).
wire cmd_b_split_i;
wire [4-1:0] cmd_b_repeat_i;
// Throttling help signals.
wire mi_stalling;
reg command_ongoing;
// Internal SI-side signals.
reg [C_AXI_ID_WIDTH-1:0] S_AXI_AID_Q;
reg [C_AXI_ADDR_WIDTH-1:0] S_AXI_AADDR_Q;
reg [8-1:0] S_AXI_ALEN_Q;
reg [3-1:0] S_AXI_ASIZE_Q;
reg [2-1:0] S_AXI_ABURST_Q;
reg [2-1:0] S_AXI_ALOCK_Q;
reg [4-1:0] S_AXI_ACACHE_Q;
reg [3-1:0] S_AXI_APROT_Q;
reg [4-1:0] S_AXI_AQOS_Q;
reg [C_AXI_AUSER_WIDTH-1:0] S_AXI_AUSER_Q;
reg S_AXI_AREADY_I;
// Internal MI-side signals.
wire [C_AXI_ID_WIDTH-1:0] M_AXI_AID_I;
reg [C_AXI_ADDR_WIDTH-1:0] M_AXI_AADDR_I;
reg [8-1:0] M_AXI_ALEN_I;
wire [3-1:0] M_AXI_ASIZE_I;
wire [2-1:0] M_AXI_ABURST_I;
reg [2-1:0] M_AXI_ALOCK_I;
wire [4-1:0] M_AXI_ACACHE_I;
wire [3-1:0] M_AXI_APROT_I;
wire [4-1:0] M_AXI_AQOS_I;
wire [C_AXI_AUSER_WIDTH-1:0] M_AXI_AUSER_I;
wire M_AXI_AVALID_I;
wire M_AXI_AREADY_I;
reg [1:0] areset_d; // Reset delay register
always @(posedge ACLK) begin
areset_d <= {areset_d[0], ARESET};
end
/////////////////////////////////////////////////////////////////////////////
// Capture SI-Side signals.
//
/////////////////////////////////////////////////////////////////////////////
// Register SI-Side signals.
always @ (posedge ACLK) begin
if ( ARESET ) begin
S_AXI_AID_Q <= {C_AXI_ID_WIDTH{1\'b0}};
S_AXI_AADDR_Q <= {C_AXI_ADDR_WIDTH{1\'b0}};
S_AXI_ALEN_Q <= 8\'b0;
S_AXI_ASIZE_Q <= 3\'b0;
S_AXI_ABURST_Q <= 2\'b0;
S_AXI_ALOCK_Q <= 2\'b0;
S_AXI_ACACHE_Q <= 4\'b0;
S_AXI_APROT_Q <= 3\'b0;
S_AXI_AQOS_Q <= 4\'b0;
S_AXI_AUSER_Q <= {C_AXI_AUSER_WIDTH{1\'b0}};
end else begin
if ( S_AXI_AREADY_I ) begin
S_AXI_AID_Q <= S_AXI_AID;
S_AXI_AADDR_Q <= S_AXI_AADDR;
S_AXI_ALEN_Q <= S_AXI_ALEN;
S_AXI_ASIZE_Q <= S_AXI_ASIZE;
S_AXI_ABURST_Q <= S_AXI_ABURST;
S_AXI_ALOCK_Q <= S_AXI_ALOCK;
S_AXI_ACACHE_Q <= S_AXI_ACACHE;
S_AXI_APROT_Q <= S_AXI_APROT;
S_AXI_AQOS_Q <= S_AXI_AQOS;
S_AXI_AUSER_Q <= S_AXI_AUSER;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Decode the Incoming Transaction.
//
// Extract transaction type and the number of splits that may be needed.
//
// Calculate the step size so that the address for each part of a split can
// can be calculated.
//
/////////////////////////////////////////////////////////////////////////////
// Transaction burst type.
assign access_is_incr = ( S_AXI_ABURST == C_INCR_BURST );
// Get number of transactions for split INCR.
assign num_transactions = S_AXI_ALEN[4 +: 4];
assign first_beats = {3\'b0, S_AXI_ALEN[0 +: 4]} + 7\'b01;
// Generate address increment of first split transaction.
always @ *
begin
case (S_AXI_ASIZE)
3\'b000: first_step = first_beats << 0;
3\'b001: first_step = first_beats << 1;
3\'b010: first_step = first_beats << 2;
3\'b011: first_step = first_beats << 3;
3\'b100: first_step = first_beats << 4;
3\'b101: first_step = first_beats << 5;
3\'b110: first_step = first_beats << 6;
3\'b111: first_step = first_beats << 7;
endcase
end
// Generate address increment for remaining split transactions.
always @ *
begin
case (S_AXI_ASIZE)
3\'b000: addr_step = 16\'h0010;
3\'b001: addr_step = 16\'h0020;
3\'b010: addr_step = 16\'h0040;
3\'b011: addr_step = 16\'h0080;
3\'b100: addr_step = 16\'h0100;
3\'b101: addr_step = 16\'h0200;
3\'b110: addr_step = 16\'h0400;
3\'b111: addr_step = 16\'h0800;
endcase
end
// Generate address mask bits to remove split transaction unalignment.
always @ *
begin
case (S_AXI_ASIZE)
3\'b000: size_mask = C_SIZE_MASK[8 +: C_AXI_ADDR_WIDTH];
3\'b001: size_mask = C_SIZE_MASK[7 +: C_AXI_ADDR_WIDTH];
3\'b010: size_mask = C_SIZE_MASK[6 +: C_AXI_ADDR_WIDTH];
3\'b011: size_mask = C_SIZE_MASK[5 +: C_AXI_ADDR_WIDTH];
3\'b100: size_mask = C_SIZE_MASK[4 +: C_AXI_ADDR_WIDTH];
3\'b101: size_mask = C_SIZE_MASK[3 +: C_AXI_ADDR_WIDTH];
3\'b110: size_mask = C_SIZE_MASK[2 +: C_AXI_ADDR_WIDTH];
3\'b111: size_mask = C_SIZE_MASK[1 +: C_AXI_ADDR_WIDTH];
endcase
end
/////////////////////////////////////////////////////////////////////////////
// Transfer SI-Side signals to internal Pipeline Stage.
//
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
if ( ARESET ) begin
access_is_incr_q <= 1\'b0;
incr_need_to_split_q <= 1\'b0;
num_transactions_q <= 4\'b0;
addr_step_q <= 16\'b0;
first_step_q <= 16\'b0;
size_mask_q <= {C_AXI_ADDR_WIDTH{1\'b0}};
end else begin
if ( S_AXI_AREADY_I ) begin
access_is_incr_q <= access_is_incr;
incr_need_to_split_q <= incr_need_to_split;
num_transactions_q <= num_transactions;
addr_step_q <= addr_step;
first_step_q <= first_step;
size_mask_q <= size_mask;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Generate Command Information.
//
// Detect if current transation needs to be split, and keep track of all
// the generated split transactions.
//
//
/////////////////////////////////////////////////////////////////////////////
// Detect when INCR must be split.
assign incr_need_to_split = access_is_incr & ( num_transactions != 0 ) &
( C_SUPPORT_SPLITTING == 1 ) &
( C_SUPPORT_BURSTS == 1 );
// Detect when a command has to be split.
assign need_to_split_q = incr_need_to_split_q;
// Handle progress of split transactions.
always @ (posedge ACLK) begin
if ( ARESET ) begin
split_ongoing <= 1\'b0;
end else begin
if ( pushed_new_cmd ) begin
split_ongoing <= need_to_split_q & ~last_split;
end
end
end
// Keep track of number of transactions generated.
always @ (posedge ACLK) begin
if ( ARESET ) begin
pushed_commands <= 4\'b0;
end else begin
if ( S_AXI_AREADY_I ) begin
pushed_commands <= 4\'b0;
end else if ( pushed_new_cmd ) begin
pushed_commands <= pushed_commands + 4\'b1;
end
end
end
// Detect last part of a command, split or not.
assign last_incr_split = access_is_incr_q & ( num_transactions_q == pushed_commands );
assign last_split = last_incr_split | ~access_is_incr_q |
( C_SUPPORT_SPLITTING == 0 ) |
( C_SUPPORT_BURSTS == 0 );
assign first_split = (pushed_commands == 4\'b0);
// Calculate base for next address.
always @ (posedge ACLK) begin
if ( ARESET ) begin
next_mi_addr = {C_AXI_ADDR_WIDTH{1\'b0}};
end else if ( pushed_new_cmd ) begin
next_mi_addr = M_AXI_AADDR_I + (first_split ? first_step_q : addr_step_q);
end
end
/////////////////////////////////////////////////////////////////////////////
// Translating Transaction.
//
// Set Split transaction information on all part except last for a transaction
// that needs splitting.
// The B Channel will only get one command for a Split transaction and in
// the Split bflag will be set in that case.
//
// The AWID is extracted and applied to all commands generated for the current
// incomming SI-Side transaction.
//
// The address is increased for each part of a Split transaction, the amount
// depends on the siSIZE for the transaction.
//
// The length has to be changed for Split transactions. All part except tha
// last one will have 0xF, the last one uses the 4 lsb bits from the SI-side
// transaction as length.
//
// Non-Split has untouched address and length information.
//
// Exclusive access are diasabled for a Split transaction because it is not
// possible to guarantee concistency between all the parts.
//
/////////////////////////////////////////////////////////////////////////////
// Assign Split signals.
assign cmd_split_i = need_to_split_q & ~last_split;
assign cmd_b_split_i = need_to_split_q & ~last_split;
// Copy AW ID to W.
assign cmd_id_i = S_AXI_AID_Q;
// Set B Responses to merge.
assign cmd_b_repeat_i = num_transactions_q;
// Select new size or remaining size.
always @ *
begin
if ( split_ongoing & access_is_incr_q ) begin
M_AXI_AADDR_I = next_mi_addr & size_mask_q;
end else begin
M_AXI_AADDR_I = S_AXI_AADDR_Q;
end
end
// Generate the base length for each transaction.
always @ *
begin
if ( first_split | ~need_to_split_q ) begin
M_AXI_ALEN_I = S_AXI_ALEN_Q[0 +: 4];
cmd_length_i = S_AXI_ALEN_Q[0 +: 4];
end else begin
M_AXI_ALEN_I = 4\'hF;
cmd_length_i = 4\'hF;
end
end
// Kill Exclusive for Split transactions.
always @ *
begin
if ( need_to_split_q ) begin
M_AXI_ALOCK_I = 2\'b00;
end else begin
M_AXI_ALOCK_I = {1\'b0, S_AXI_ALOCK_Q};
end
end
/////////////////////////////////////////////////////////////////////////////
// Forward the command to the MI-side interface.
//
// It is determined that this is an allowed command/access when there is
// room in the command queue (and it passes ID and Split checks as required).
//
/////////////////////////////////////////////////////////////////////////////
// Move SI-side transaction to internal pipe stage.
always @ (posedge ACLK) begin
if (ARESET) begin
command_ongoing <= 1\'b0;
S_AXI_AREADY_I <= 1\'b0;
end else begin
if (areset_d == 2\'b10) begin
S_AXI_AREADY_I <= 1\'b1;
end else begin
if ( S_AXI_AVALID & S_AXI_AREADY_I ) begin
command_ongoing <= 1\'b1;
S_AXI_AREADY_I <= 1\'b0;
end else if ( pushed_new_cmd & last_split ) begin
command_ongoing <= 1\'b0;
S_AXI_AREADY_I <= 1\'b1;
end
end
end
end
// Generate ready signal.
assign S_AXI_AREADY = S_AXI_AREADY_I;
// Only allowed to forward translated command when command queue is ok with it.
assign M_AXI_AVALID_I = allow_new_cmd & command_ongoing;
// Detect when MI-side is stalling.
assign mi_stalling = M_AXI_AVALID_I & ~M_AXI_AREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Simple transfer of paramters that doesn\'t need to be adjusted.
//
// ID - Transaction still recognized with the same ID.
// CACHE - No need to change the chache features. Even if the modyfiable
// bit is overridden (forcefully) there is no need to let downstream
// component beleive it is ok to modify it further.
// PROT - Security level of access is not changed when upsizing.
// QOS - Quality of Service is static 0.
// USER - User bits remains the same.
//
/////////////////////////////////////////////////////////////////////////////
assign M_AXI_AID_I = S_AXI_AID_Q;
assign M_AXI_ASIZE_I = S_AXI_ASIZE_Q;
assign M_AXI_ABURST_I = S_AXI_ABURST_Q;
assign M_AXI_ACACHE_I = S_AXI_ACACHE_Q;
assign M_AXI_APROT_I = S_AXI_APROT_Q;
assign M_AXI_AQOS_I = S_AXI_AQOS_Q;
assign M_AXI_AUSER_I = ( C_AXI_SUPPORTS_USER_SIGNALS ) ? S_AXI_AUSER_Q : {C_AXI_AUSER_WIDTH{1\'b0}};
/////////////////////////////////////////////////////////////////////////////
// Control command queue to W/R channel.
//
// Commands can be pushed into the Cmd FIFO even if MI-side is stalling.
// A flag is set if MI-side is stalling when Command is pushed to the
// Cmd FIFO. This will prevent multiple push of the same Command as well as
// keeping the MI-side Valid signal if the Allow Cmd requirement has been
// updated to disable furter Commands (I.e. it is made sure that the SI-side
// Command has been forwarded to both Cmd FIFO and MI-side).
//
// It is allowed to continue pushing new commands as long as
// * There is room in the queue(s)
// * The ID is the same as previously queued. Since data is not reordered
// for the same ID it is always OK to let them proceed.
// Or, if no split transaction is ongoing any ID can be allowed.
//
/////////////////////////////////////////////////////////////////////////////
// Keep track of current ID in queue.
always @ (posedge ACLK) begin
if (ARESET) begin
queue_id <= {C_AXI_ID_WIDTH{1\'b0}};
multiple_id_non_split <= 1\'b0;
split_in_progress <= 1\'b0;
end else begin
if ( cmd_push ) begin
// Store ID (it will be matching ID or a "new beginning").
queue_id <= S_AXI_AID_Q;
end
if ( no_cmd & no_b_cmd ) begin
multiple_id_non_split <= 1\'b0;
end else if ( cmd_push & allow_non_split_cmd & ~id_match ) begin
multiple_id_non_split <= 1\'b1;
end
if ( no_cmd & no_b_cmd ) begin
split_in_progress <= 1\'b0;
end else if ( cmd_push & allow_split_cmd ) begin
split_in_progress <= 1\'b1;
end
end
end
// Determine if the command FIFOs are empty.
assign no_cmd = almost_empty & cmd_ready | cmd_empty;
assign no_b_cmd = almost_b_empty & cmd_b_ready | cmd_b_empty;
// Check ID to make sure this command is allowed.
assign id_match = ( C_SINGLE_THREAD == 0 ) | ( queue_id == S_AXI_AID_Q);
assign cmd_id_check = (cmd_empty & cmd_b_empty) | ( id_match & (~cmd_empty | ~cmd_b_empty) );
// Command type affects possibility to push immediately or wait.
assign allow_split_cmd = need_to_split_q & cmd_id_check & ~multiple_id_non_split;
assign allow_non_split_cmd = ~need_to_split_q & (cmd_id_check | ~split_in_progress);
assign allow_this_cmd = allow_split_cmd | allow_non_split_cmd | ( C_SINGLE_THREAD == 0 );
// Check if it is allowed to push more commands.
assign allow_new_cmd = (~cmd_full & ~cmd_b_full & allow_this_cmd) |
cmd_push_block;
// Push new command when allowed and MI-side is able to receive the command.
assign cmd_push = M_AXI_AVALID_I & ~cmd_push_block;
assign cmd_b_push = M_AXI_AVALID_I & ~cmd_b_push_block & (C_AXI_CHANNEL == 0);
// Block furter push until command has been forwarded to MI-side.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_push_block <= 1\'b0;
end else begin
if ( pushed_new_cmd ) begin
cmd_push_block <= 1\'b0;
end else if ( cmd_push & mi_stalling ) begin
cmd_push_block <= 1\'b1;
end
end
end
// Block furter push until command has been forwarded to MI-side.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_push_block <= 1\'b0;
end else begin
if ( S_AXI_AREADY_I ) begin
cmd_b_push_block <= 1\'b0;
end else if ( cmd_b_push ) begin
cmd_b_push_block <= 1\'b1;
end
end
end
// Acknowledge command when we can push it into queue (and forward it).
assign pushed_new_cmd = M_AXI_AVALID_I & M_AXI_AREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue (W/R):
//
// Instantiate a FIFO as the queue and adjust the control signals.
//
// The features from Command FIFO can be reduced depending on configuration:
// Read Channel only need the split information.
// Write Channel always require ID information. When bursts are supported
// Split and Length information is also used.
//
/////////////////////////////////////////////////////////////////////////////
// Instantiated queue.
generate
if ( C_AXI_CHANNEL == 1 && C_SUPPORT_SPLITTING == 1 && C_SUPPORT_BURSTS == 1 ) begin : USE_R_CHANNEL
axi_data_fifo_v2_1_axic_fifo #
(
.C_FAMILY(C_FAMILY),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(1),
.C_FIFO_TYPE("lut")
)
cmd_queue
(
.ACLK(ACLK),
.ARESET(ARESET),
.S_MESG({cmd_split_i}),
.S_VALID(cmd_push),
.S_READY(s_ready),
.M_MESG({cmd_split}),
.M_VALID(cmd_valid),
.M_READY(cmd_ready)
);
assign cmd_id = {C_AXI_ID_WIDTH{1\'b0}};
assign cmd_length = 4\'b0;
end else if (C_SUPPORT_BURSTS == 1) begin : USE_BURSTS
axi_data_fifo_v2_1_axic_fifo #
(
.C_FAMILY(C_FAMILY),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(C_AXI_ID_WIDTH+4),
.C_FIFO_TYPE("lut")
)
cmd_queue
(
.ACLK(ACLK),
.ARESET(ARESET),
.S_MESG({cmd_id_i, cmd_length_i}),
.S_VALID(cmd_push),
.S_READY(s_ready),
.M_MESG({cmd_id, cmd_length}),
.M_VALID(cmd_valid),
.M_READY(cmd_ready)
);
assign cmd_split = 1\'b0;
end else begin : NO_BURSTS
axi_data_fifo_v2_1_axic_fifo #
(
.C_FAMILY(C_FAMILY),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(C_AXI_ID_WIDTH),
.C_FIFO_TYPE("lut")
)
cmd_queue
(
.ACLK(ACLK),
.ARESET(ARESET),
.S_MESG({cmd_id_i}),
.S_VALID(cmd_push),
.S_READY(s_ready),
.M_MESG({cmd_id}),
.M_VALID(cmd_valid),
.M_READY(cmd_ready)
);
assign cmd_split = 1\'b0;
assign cmd_length = 4\'b0;
end
endgenerate
// Queue is concidered full when not ready.
assign cmd_full = ~s_ready;
// Queue is empty when no data at output port.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_empty <= 1\'b1;
cmd_depth <= {C_FIFO_DEPTH_LOG+1{1\'b0}};
end else begin
if ( cmd_push & ~cmd_ready ) begin
// Push only => Increase depth.
cmd_depth <= cmd_depth + 1\'b1;
cmd_empty <= 1\'b0;
end else if ( ~cmd_push & cmd_ready ) begin
// Pop only => Decrease depth.
cmd_depth <= cmd_depth - 1\'b1;
cmd_empty <= almost_empty;
end
end
end
assign almost_empty = ( cmd_depth == 1 );
/////////////////////////////////////////////////////////////////////////////
// Command Queue (B):
//
// Add command queue for B channel only when it is AW channel and both burst
// and splitting is supported.
//
// When turned off the command appears always empty.
//
/////////////////////////////////////////////////////////////////////////////
// Instantiated queue.
generate
if ( C_AXI_CHANNEL == 0 && C_SUPPORT_SPLITTING == 1 && C_SUPPORT_BURSTS == 1 ) begin : USE_B_CHANNEL
wire cmd_b_valid_i;
wire s_b_ready;
axi_data_fifo_v2_1_axic_fifo #
(
.C_FAMILY(C_FAMILY),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(1+4),
.C_FIFO_TYPE("lut")
)
cmd_b_queue
(
.ACLK(ACLK),
.ARESET(ARESET),
.S_MESG({cmd_b_split_i, cmd_b_repeat_i}),
.S_VALID(cmd_b_push),
.S_READY(s_b_ready),
.M_MESG({cmd_b_split, cmd_b_repeat}),
.M_VALID(cmd_b_valid_i),
.M_READY(cmd_b_ready)
);
// Queue is concidered full when not ready.
assign cmd_b_full = ~s_b_ready;
// Queue is empty when no data at output port.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_empty <= 1\'b1;
cmd_b_depth <= {C_FIFO_DEPTH_LOG+1{1\'b0}};
end else begin
if ( cmd_b_push & ~cmd_b_ready ) begin
// Push only => Increase depth.
cmd_b_depth <= cmd_b_depth + 1\'b1;
cmd_b_empty <= 1\'b0;
end else if ( ~cmd_b_push & cmd_b_ready ) begin
// Pop only => Decrease depth.
cmd_b_depth <= cmd_b_depth - 1\'b1;
cmd_b_empty <= ( cmd_b_depth == 1 );
end
end
end
assign almost_b_empty = ( cmd_b_depth == 1 );
// Assign external signal.
assign cmd_b_valid = cmd_b_valid_i;
end else begin : NO_B_CHANNEL
// Assign external command signals.
assign cmd_b_valid = 1\'b0;
assign cmd_b_split = 1\'b0;
assign cmd_b_repeat = 4\'b0;
// Assign internal command FIFO signals.
assign cmd_b_full = 1\'b0;
assign almost_b_empty = 1\'b0;
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_empty <= 1\'b1;
cmd_b_depth <= {C_FIFO_DEPTH_LOG+1{1\'b0}};
end else begin
// Constant FF due to ModelSim behavior.
cmd_b_empty <= 1\'b1;
cmd_b_depth <= {C_FIFO_DEPTH_LOG+1{1\'b0}};
end
end
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// MI-side output handling
//
/////////////////////////////////////////////////////////////////////////////
assign M_AXI_AID = M_AXI_AID_I;
assign M_AXI_AADDR = M_AXI_AADDR_I;
assign M_AXI_ALEN = M_AXI_ALEN_I;
assign M_AXI_ASIZE = M_AXI_ASIZE_I;
assign M_AXI_ABURST = M_AXI_ABURST_I;
assign M_AXI_ALOCK = M_AXI_ALOCK_I;
assign M_AXI_ACACHE = M_AXI_ACACHE_I;
assign M_AXI_APROT = M_AXI_APROT_I;
assign M_AXI_AQOS = M_AXI_AQOS_I;
assign M_AXI_AUSER = M_AXI_AUSER_I;
assign M_AXI_AVALID = M_AXI_AVALID_I;
assign M_AXI_AREADY_I = M_AXI_AREADY;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: AXI3 Slave Converter
// This module instantiates Address, Write Data and Read Data AXI3 Converter
// modules, each one taking care of the channel specific tasks.
// The Address AXI3 converter can handle both AR and AW channels.
// The Write Respons Channel is reused from the Down-Sizer.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axi3_conv
// a_axi3_conv
// axic_fifo
// w_axi3_conv
// b_downsizer
// r_axi3_conv
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1,
parameter integer C_SUPPORT_SPLITTING = 1,
// Implement transaction splitting logic.
// Disabled whan all connected masters are AXI3 and have same or narrower data width.
parameter integer C_SUPPORT_BURSTS = 1,
// Disabled when all connected masters are AxiLite,
// allowing logic to be simplified.
parameter integer C_SINGLE_THREAD = 1
// 0 = Ignore ID when propagating transactions (assume all responses are in order).
// 1 = Enforce single-threading (one ID at a time) when any outstanding or
// requested transaction requires splitting.
// While no split is ongoing any new non-split transaction will pass immediately regardless
// off ID.
// A split transaction will stall if there are multiple ID (non-split) transactions
// ongoing, once it has been forwarded only transactions with the same ID is allowed
// (split or not) until all ongoing split transactios has been completed.
)
(
// System Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [8-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [1-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [4-1:0] S_AXI_AWQOS,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [8-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [1-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [4-1:0] S_AXI_ARQOS,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [4-1:0] M_AXI_AWQOS,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [4-1:0] M_AXI_ARQOS,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
generate
if (C_AXI_SUPPORTS_WRITE == 1) begin : USE_WRITE
// Write Channel Signals for Commands Queue Interface.
wire wr_cmd_valid;
wire [C_AXI_ID_WIDTH-1:0] wr_cmd_id;
wire [4-1:0] wr_cmd_length;
wire wr_cmd_ready;
wire wr_cmd_b_valid;
wire wr_cmd_b_split;
wire [4-1:0] wr_cmd_b_repeat;
wire wr_cmd_b_ready;
// Write Address Channel.
axi_protocol_converter_v2_1_a_axi3_conv #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_AXI_CHANNEL (0),
.C_SUPPORT_SPLITTING (C_SUPPORT_SPLITTING),
.C_SUPPORT_BURSTS (C_SUPPORT_BURSTS),
.C_SINGLE_THREAD (C_SINGLE_THREAD)
) write_addr_inst
(
// Global Signals
.ARESET (~ARESETN),
.ACLK (ACLK),
// Command Interface (W)
.cmd_valid (wr_cmd_valid),
.cmd_split (),
.cmd_id (wr_cmd_id),
.cmd_length (wr_cmd_length),
.cmd_ready (wr_cmd_ready),
// Command Interface (B)
.cmd_b_valid (wr_cmd_b_valid),
.cmd_b_split (wr_cmd_b_split),
.cmd_b_repeat (wr_cmd_b_repeat),
.cmd_b_ready (wr_cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AID (S_AXI_AWID),
.S_AXI_AADDR (S_AXI_AWADDR),
.S_AXI_ALEN (S_AXI_AWLEN),
.S_AXI_ASIZE (S_AXI_AWSIZE),
.S_AXI_ABURST (S_AXI_AWBURST),
.S_AXI_ALOCK (S_AXI_AWLOCK),
.S_AXI_ACACHE (S_AXI_AWCACHE),
.S_AXI_APROT (S_AXI_AWPROT),
.S_AXI_AQOS (S_AXI_AWQOS),
.S_AXI_AUSER (S_AXI_AWUSER),
.S_AXI_AVALID (S_AXI_AWVALID),
.S_AXI_AREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AID (M_AXI_AWID),
.M_AXI_AADDR (M_AXI_AWADDR),
.M_AXI_ALEN (M_AXI_AWLEN),
.M_AXI_ASIZE (M_AXI_AWSIZE),
.M_AXI_ABURST (M_AXI_AWBURST),
.M_AXI_ALOCK (M_AXI_AWLOCK),
.M_AXI_ACACHE (M_AXI_AWCACHE),
.M_AXI_APROT (M_AXI_AWPROT),
.M_AXI_AQOS (M_AXI_AWQOS),
.M_AXI_AUSER (M_AXI_AWUSER),
.M_AXI_AVALID (M_AXI_AWVALID),
.M_AXI_AREADY (M_AXI_AWREADY)
);
// Write Data Channel.
axi_protocol_converter_v2_1_w_axi3_conv #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH),
.C_SUPPORT_SPLITTING (C_SUPPORT_SPLITTING),
.C_SUPPORT_BURSTS (C_SUPPORT_BURSTS)
) write_data_inst
(
// Global Signals
.ARESET (~ARESETN),
.ACLK (ACLK),
// Command Interface
.cmd_valid (wr_cmd_valid),
.cmd_id (wr_cmd_id),
.cmd_length (wr_cmd_length),
.cmd_ready (wr_cmd_ready),
// Slave Interface Write Data Ports
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
if ( C_SUPPORT_SPLITTING == 1 && C_SUPPORT_BURSTS == 1 ) begin : USE_SPLIT_W
// Write Data Response Channel.
axi_protocol_converter_v2_1_b_downsizer #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH)
) write_resp_inst
(
// Global Signals
.ARESET (~ARESETN),
.ACLK (ACLK),
// Command Interface
.cmd_valid (wr_cmd_b_valid),
.cmd_split (wr_cmd_b_split),
.cmd_repeat (wr_cmd_b_repeat),
.cmd_ready (wr_cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY)
);
end else begin : NO_SPLIT_W
// MI -> SI Interface Write Response Ports
assign S_AXI_BID = M_AXI_BID;
assign S_AXI_BRESP = M_AXI_BRESP;
assign S_AXI_BUSER = M_AXI_BUSER;
assign S_AXI_BVALID = M_AXI_BVALID;
assign M_AXI_BREADY = S_AXI_BREADY;
end
end else begin : NO_WRITE
// Slave Interface Write Address Ports
assign S_AXI_AWREADY = 1\'b0;
// Slave Interface Write Data Ports
assign S_AXI_WREADY = 1\'b0;
// Slave Interface Write Response Ports
assign S_AXI_BID = {C_AXI_ID_WIDTH{1\'b0}};
assign S_AXI_BRESP = 2\'b0;
assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1\'b0}};
assign S_AXI_BVALID = 1\'b0;
// Master Interface Write Address Port
assign M_AXI_AWID = {C_AXI_ID_WIDTH{1\'b0}};
assign M_AXI_AWADDR = {C_AXI_ADDR_WIDTH{1\'b0}};
assign M_AXI_AWLEN = 4\'b0;
assign M_AXI_AWSIZE = 3\'b0;
assign M_AXI_AWBURST = 2\'b0;
assign M_AXI_AWLOCK = 2\'b0;
assign M_AXI_AWCACHE = 4\'b0;
assign M_AXI_AWPROT = 3\'b0;
assign M_AXI_AWQOS = 4\'b0;
assign M_AXI_AWUSER = {C_AXI_AWUSER_WIDTH{1\'b0}};
assign M_AXI_AWVALID = 1\'b0;
// Master Interface Write Data Ports
assign M_AXI_WDATA = {C_AXI_DATA_WIDTH{1\'b0}};
assign M_AXI_WSTRB = {C_AXI_DATA_WIDTH/8{1\'b0}};
assign M_AXI_WLAST = 1\'b0;
assign M_AXI_WUSER = {C_AXI_WUSER_WIDTH{1\'b0}};
assign M_AXI_WVALID = 1\'b0;
// Master Interface Write Response Ports
assign M_AXI_BREADY = 1\'b0;
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
generate
if (C_AXI_SUPPORTS_READ == 1) begin : USE_READ
// Write Response channel.
if ( C_SUPPORT_SPLITTING == 1 && C_SUPPORT_BURSTS == 1 ) begin : USE_SPLIT_R
// Read Channel Signals for Commands Queue Interface.
wire rd_cmd_valid;
wire rd_cmd_split;
wire rd_cmd_ready;
// Write Address Channel.
axi_protocol_converter_v2_1_a_axi3_conv #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AUSER_WIDTH (C_AXI_ARUSER_WIDTH),
.C_AXI_CHANNEL (1),
.C_SUPPORT_SPLITTING (C_SUPPORT_SPLITTING),
.C_SUPPORT_BURSTS (C_SUPPORT_BURSTS),
.C_SINGLE_THREAD (C_SINGLE_THREAD)
) read_addr_inst
(
// Global Signals
.ARESET (~ARESETN),
.ACLK (ACLK),
// Command Interface (R)
.cmd_valid (rd_cmd_valid),
.cmd_split (rd_cmd_split),
.cmd_id (),
.cmd_length (),
.cmd_ready (rd_cmd_ready),
// Command Interface (B)
.cmd_b_valid (),
.cmd_b_split (),
.cmd_b_repeat (),
.cmd_b_ready (1\'b0),
// Slave Interface Write Address Ports
.S_AXI_AID (S_AXI_ARID),
.S_AXI_AADDR (S_AXI_ARADDR),
.S_AXI_ALEN (S_AXI_ARLEN),
.S_AXI_ASIZE (S_AXI_ARSIZE),
.S_AXI_ABURST (S_AXI_ARBURST),
.S_AXI_ALOCK (S_AXI_ARLOCK),
.S_AXI_ACACHE (S_AXI_ARCACHE),
.S_AXI_APROT (S_AXI_ARPROT),
.S_AXI_AQOS (S_AXI_ARQOS),
.S_AXI_AUSER (S_AXI_ARUSER),
.S_AXI_AVALID (S_AXI_ARVALID),
.S_AXI_AREADY (S_AXI_ARREADY),
// Master Interface Write Address Port
.M_AXI_AID (M_AXI_ARID),
.M_AXI_AADDR (M_AXI_ARADDR),
.M_AXI_ALEN (M_AXI_ARLEN),
.M_AXI_ASIZE (M_AXI_ARSIZE),
.M_AXI_ABURST (M_AXI_ARBURST),
.M_AXI_ALOCK (M_AXI_ARLOCK),
.M_AXI_ACACHE (M_AXI_ARCACHE),
.M_AXI_APROT (M_AXI_ARPROT),
.M_AXI_AQOS (M_AXI_ARQOS),
.M_AXI_AUSER (M_AXI_ARUSER),
.M_AXI_AVALID (M_AXI_ARVALID),
.M_AXI_AREADY (M_AXI_ARREADY)
);
// Read Data Channel.
axi_protocol_converter_v2_1_r_axi3_conv #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_SUPPORT_SPLITTING (C_SUPPORT_SPLITTING),
.C_SUPPORT_BURSTS (C_SUPPORT_BURSTS)
) read_data_inst
(
// Global Signals
.ARESET (~ARESETN),
.ACLK (ACLK),
// Command Interface
.cmd_valid (rd_cmd_valid),
.cmd_split (rd_cmd_split),
.cmd_ready (rd_cmd_ready),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_RID),
.S_AXI_RDATA (S_AXI_RDATA),
.S_AXI_RRESP (S_AXI_RRESP),
.S_AXI_RLAST (S_AXI_RLAST),
.S_AXI_RUSER (S_AXI_RUSER),
.S_AXI_RVALID (S_AXI_RVALID),
.S_AXI_RREADY (S_AXI_RREADY),
// Master Interface Read Data Ports
.M_AXI_RID (M_AXI_RID),
.M_AXI_RDATA (M_AXI_RDATA),
.M_AXI_RRESP (M_AXI_RRESP),
.M_AXI_RLAST (M_AXI_RLAST),
.M_AXI_RUSER (M_AXI_RUSER),
.M_AXI_RVALID (M_AXI_RVALID),
.M_AXI_RREADY (M_AXI_RREADY)
);
end else begin : NO_SPLIT_R
// SI -> MI Interface Write Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARQOS = S_AXI_ARQOS;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// MI -> SI Interface Read Data Ports
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
end
end else begin : NO_READ
// Slave Interface Read Address Ports
assign S_AXI_ARREADY = 1\'b0;
// Slave Interface Read Data Ports
assign S_AXI_RID = {C_AXI_ID_WIDTH{1\'b0}};
assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1\'b0}};
assign S_AXI_RRESP = 2\'b0;
assign S_AXI_RLAST = 1\'b0;
assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1\'b0}};
assign S_AXI_RVALID = 1\'b0;
// Master Interface Read Address Port
assign M_AXI_ARID = {C_AXI_ID_WIDTH{1\'b0}};
assign M_AXI_ARADDR = {C_AXI_ADDR_WIDTH{1\'b0}};
assign M_AXI_ARLEN = 4\'b0;
assign M_AXI_ARSIZE = 3\'b0;
assign M_AXI_ARBURST = 2\'b0;
assign M_AXI_ARLOCK = 2\'b0;
assign M_AXI_ARCACHE = 4\'b0;
assign M_AXI_ARPROT = 3\'b0;
assign M_AXI_ARQOS = 4\'b0;
assign M_AXI_ARUSER = {C_AXI_ARUSER_WIDTH{1\'b0}};
assign M_AXI_ARVALID = 1\'b0;
// Master Interface Read Data Ports
assign M_AXI_RREADY = 1\'b0;
end
endgenerate
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_b2s_incr_cmd.v
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_incr_cmd #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
input wire [C_AXI_ADDR_WIDTH-1:0] axaddr ,
input wire [7:0] axlen ,
input wire [2:0] axsize ,
// axhandshake = axvalid & axready
input wire axhandshake ,
output wire [C_AXI_ADDR_WIDTH-1:0] cmd_byte_addr ,
// Connections to/from fsm module
// signal to increment to the next mc transaction
input wire next ,
// signal to the fsm there is another transaction required
output reg next_pending
);
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
reg sel_first;
reg [11:0] axaddr_incr;
reg [8:0] axlen_cnt;
reg next_pending_r;
wire [3:0] axsize_shift;
wire [11:0] axsize_mask;
localparam L_AXI_ADDR_LOW_BIT = (C_AXI_ADDR_WIDTH >= 12) ? 12 : 11;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// calculate cmd_byte_addr
generate
if (C_AXI_ADDR_WIDTH > 12) begin : ADDR_GT_4K
assign cmd_byte_addr = (sel_first) ? axaddr : {axaddr[C_AXI_ADDR_WIDTH-1:L_AXI_ADDR_LOW_BIT],axaddr_incr[11:0]};
end else begin : ADDR_4K
assign cmd_byte_addr = (sel_first) ? axaddr : axaddr_incr[11:0];
end
endgenerate
assign axsize_shift = (1 << axsize[1:0]);
assign axsize_mask = ~(axsize_shift - 1\'b1);
// Incremented version of axaddr
always @(posedge clk) begin
if (sel_first) begin
if(~next) begin
axaddr_incr <= axaddr[11:0] & axsize_mask;
end else begin
axaddr_incr <= (axaddr[11:0] & axsize_mask) + axsize_shift;
end
end else if (next) begin
axaddr_incr <= axaddr_incr + axsize_shift;
end
end
always @(posedge clk) begin
if (axhandshake)begin
axlen_cnt <= axlen;
next_pending_r <= (axlen >= 1);
end else if (next) begin
if (axlen_cnt > 1) begin
axlen_cnt <= axlen_cnt - 1;
next_pending_r <= ((axlen_cnt - 1) >= 1);
end else begin
axlen_cnt <= 9\'d0;
next_pending_r <= 1\'b0;
end
end
end
always @( * ) begin
if (axhandshake)begin
next_pending = (axlen >= 1);
end else if (next) begin
if (axlen_cnt > 1) begin
next_pending = ((axlen_cnt - 1) >= 1);
end else begin
next_pending = 1\'b0;
end
end else begin
next_pending = next_pending_r;
end
end
// last and ignore signals to data channel. These signals are used for
// BL8 to ignore and insert data for even len transactions with offset
// and odd len transactions
// For odd len transactions with no offset the last read is ignored and
// last write is masked
// For odd len transactions with offset the first read is ignored and
// first write is masked
// For even len transactions with offset the last & first read is ignored and
// last& first write is masked
// For even len transactions no ingnores or masks.
// Indicates if we are on the first transaction of a mc translation with more
// than 1 transaction.
always @(posedge clk) begin
if (reset | axhandshake) begin
sel_first <= 1\'b1;
end else if (next) begin
sel_first <= 1\'b0;
end
end
endmodule
`default_nettype wire
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_unused_ports.v
*
* Date : 2012-11
*
* Description : Semantic checks for unused ports.
*
*****************************************************************************/
/* CAN */
assign CAN0_PHY_TX = 0;
assign CAN1_PHY_TX = 0;
always @(CAN0_PHY_RX or CAN1_PHY_RX)
begin
if(CAN0_PHY_RX | CAN1_PHY_RX)
$display("[%0d] : %0s : CAN Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* ETHERNET */
/* ------------------------------------------- */
assign ENET0_GMII_TX_EN = 0;
assign ENET0_GMII_TX_ER = 0;
assign ENET0_MDIO_MDC = 0;
assign ENET0_MDIO_O = 0; /// confirm
assign ENET0_MDIO_T = 0;
assign ENET0_PTP_DELAY_REQ_RX = 0;
assign ENET0_PTP_DELAY_REQ_TX = 0;
assign ENET0_PTP_PDELAY_REQ_RX = 0;
assign ENET0_PTP_PDELAY_REQ_TX = 0;
assign ENET0_PTP_PDELAY_RESP_RX = 0;
assign ENET0_PTP_PDELAY_RESP_TX = 0;
assign ENET0_PTP_SYNC_FRAME_RX = 0;
assign ENET0_PTP_SYNC_FRAME_TX = 0;
assign ENET0_SOF_RX = 0;
assign ENET0_SOF_TX = 0;
assign ENET0_GMII_TXD = 0;
always@(ENET0_GMII_COL or ENET0_GMII_CRS or ENET0_EXT_INTIN or
ENET0_GMII_RX_CLK or ENET0_GMII_RX_DV or ENET0_GMII_RX_ER or
ENET0_GMII_TX_CLK or ENET0_MDIO_I or ENET0_GMII_RXD)
begin
if(ENET0_GMII_COL | ENET0_GMII_CRS | ENET0_EXT_INTIN |
ENET0_GMII_RX_CLK | ENET0_GMII_RX_DV | ENET0_GMII_RX_ER |
ENET0_GMII_TX_CLK | ENET0_MDIO_I )
$display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR);
end
assign ENET1_GMII_TX_EN = 0;
assign ENET1_GMII_TX_ER = 0;
assign ENET1_MDIO_MDC = 0;
assign ENET1_MDIO_O = 0;/// confirm
assign ENET1_MDIO_T = 0;
assign ENET1_PTP_DELAY_REQ_RX = 0;
assign ENET1_PTP_DELAY_REQ_TX = 0;
assign ENET1_PTP_PDELAY_REQ_RX = 0;
assign ENET1_PTP_PDELAY_REQ_TX = 0;
assign ENET1_PTP_PDELAY_RESP_RX = 0;
assign ENET1_PTP_PDELAY_RESP_TX = 0;
assign ENET1_PTP_SYNC_FRAME_RX = 0;
assign ENET1_PTP_SYNC_FRAME_TX = 0;
assign ENET1_SOF_RX = 0;
assign ENET1_SOF_TX = 0;
assign ENET1_GMII_TXD = 0;
always@(ENET1_GMII_COL or ENET1_GMII_CRS or ENET1_EXT_INTIN or
ENET1_GMII_RX_CLK or ENET1_GMII_RX_DV or ENET1_GMII_RX_ER or
ENET1_GMII_TX_CLK or ENET1_MDIO_I or ENET1_GMII_RXD)
begin
if(ENET1_GMII_COL | ENET1_GMII_CRS | ENET1_EXT_INTIN |
ENET1_GMII_RX_CLK | ENET1_GMII_RX_DV | ENET1_GMII_RX_ER |
ENET1_GMII_TX_CLK | ENET1_MDIO_I )
$display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* GPIO */
/* ------------------------------------------- */
assign GPIO_O = 0;
assign GPIO_T = 0;
always@(GPIO_I)
begin
if(GPIO_I !== 0)
$display("[%0d] : %0s : GPIO Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* I2C */
/* ------------------------------------------- */
assign I2C0_SDA_O = 0;
assign I2C0_SDA_T = 0;
assign I2C0_SCL_O = 0;
assign I2C0_SCL_T = 0;
assign I2C1_SDA_O = 0;
assign I2C1_SDA_T = 0;
assign I2C1_SCL_O = 0;
assign I2C1_SCL_T = 0;
always@(I2C0_SDA_I or I2C0_SCL_I or I2C1_SDA_I or I2C1_SCL_I )
begin
if(I2C0_SDA_I | I2C0_SCL_I | I2C1_SDA_I | I2C1_SCL_I)
$display("[%0d] : %0s : I2C Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* JTAG */
/* ------------------------------------------- */
assign PJTAG_TD_T = 0;
assign PJTAG_TD_O = 0;
always@(PJTAG_TCK or PJTAG_TMS or PJTAG_TD_I)
begin
if(PJTAG_TCK | PJTAG_TMS | PJTAG_TD_I)
$display("[%0d] : %0s : JTAG Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* SDIO */
/* ------------------------------------------- */
assign SDIO0_CLK = 0;
assign SDIO0_CMD_O = 0;
assign SDIO0_CMD_T = 0;
assign SDIO0_DATA_O = 0;
assign SDIO0_DATA_T = 0;
assign SDIO0_LED = 0;
assign SDIO0_BUSPOW = 0;
assign SDIO0_BUSVOLT = 0;
always@(SDIO0_CLK_FB or SDIO0_CMD_I or SDIO0_DATA_I or SDIO0_CDN or SDIO0_WP )
begin
if(SDIO0_CLK_FB | SDIO0_CMD_I | SDIO0_CDN | SDIO0_WP )
$display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR);
end
assign SDIO1_CLK = 0;
assign SDIO1_CMD_O = 0;
assign SDIO1_CMD_T = 0;
assign SDIO1_DATA_O = 0;
assign SDIO1_DATA_T = 0;
assign SDIO1_LED = 0;
assign SDIO1_BUSPOW = 0;
assign SDIO1_BUSVOLT = 0;
always@(SDIO1_CLK_FB or SDIO1_CMD_I or SDIO1_DATA_I or SDIO1_CDN or SDIO1_WP )
begin
if(SDIO1_CLK_FB | SDIO1_CMD_I | SDIO1_CDN | SDIO1_WP )
$display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* SPI */
/* ------------------------------------------- */
assign SPI0_SCLK_O = 0;
assign SPI0_SCLK_T = 0;
assign SPI0_MOSI_O = 0;
assign SPI0_MOSI_T = 0;
assign SPI0_MISO_O = 0;
assign SPI0_MISO_T = 0;
assign SPI0_SS_O = 0; /// confirm
assign SPI0_SS1_O = 0;/// confirm
assign SPI0_SS2_O = 0;/// confirm
assign SPI0_SS_T = 0;
always@(SPI0_SCLK_I or SPI0_MOSI_I or SPI0_MISO_I or SPI0_SS_I)
begin
if(SPI0_SCLK_I | SPI0_MOSI_I | SPI0_MISO_I | SPI0_SS_I)
$display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR);
end
assign SPI1_SCLK_O = 0;
assign SPI1_SCLK_T = 0;
assign SPI1_MOSI_O = 0;
assign SPI1_MOSI_T = 0;
assign SPI1_MISO_O = 0;
assign SPI1_MISO_T = 0;
assign SPI1_SS_O = 0;
assign SPI1_SS1_O = 0;
assign SPI1_SS2_O = 0;
assign SPI1_SS_T = 0;
always@(SPI1_SCLK_I or SPI1_MOSI_I or SPI1_MISO_I or SPI1_SS_I)
begin
if(SPI1_SCLK_I | SPI1_MOSI_I | SPI1_MISO_I | SPI1_SS_I)
$display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* UART */
/* ------------------------------------------- */
/// confirm
assign UART0_DTRN = 0;
assign UART0_RTSN = 0;
assign UART0_TX = 0;
always@(UART0_CTSN or UART0_DCDN or UART0_DSRN or UART0_RIN or UART0_RX)
begin
if(UART0_CTSN | UART0_DCDN | UART0_DSRN | UART0_RIN | UART0_RX)
$display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR);
end
assign UART1_DTRN = 0;
assign UART1_RTSN = 0;
assign UART1_TX = 0;
always@(UART1_CTSN or UART1_DCDN or UART1_DSRN or UART1_RIN or UART1_RX)
begin
if(UART1_CTSN | UART1_DCDN | UART1_DSRN | UART1_RIN | UART1_RX)
$display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* TTC */
/* ------------------------------------------- */
assign TTC0_WAVE0_OUT = 0;
assign TTC0_WAVE1_OUT = 0;
assign TTC0_WAVE2_OUT = 0;
always@(TTC0_CLK0_IN or TTC0_CLK1_IN or TTC0_CLK2_IN)
begin
if(TTC0_CLK0_IN | TTC0_CLK1_IN | TTC0_CLK2_IN)
$display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR);
end
assign TTC1_WAVE0_OUT = 0;
assign TTC1_WAVE1_OUT = 0;
assign TTC1_WAVE2_OUT = 0;
always@(TTC1_CLK0_IN or TTC1_CLK1_IN or TTC1_CLK2_IN)
begin
if(TTC1_CLK0_IN | TTC1_CLK1_IN | TTC1_CLK2_IN)
$display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* WDT */
/* ------------------------------------------- */
assign WDT_RST_OUT = 0;
always@(WDT_CLK_IN)
begin
if(WDT_CLK_IN)
$display("[%0d] : %0s : WDT Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* TRACE */
/* ------------------------------------------- */
assign TRACE_CTL = 0;
assign TRACE_DATA = 0;
always@(TRACE_CLK)
begin
if(TRACE_CLK)
$display("[%0d] : %0s : TRACE Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* USB */
/* ------------------------------------------- */
assign USB0_PORT_INDCTL = 0;
assign USB0_VBUS_PWRSELECT = 0;
always@(USB0_VBUS_PWRFAULT)
begin
if(USB0_VBUS_PWRFAULT)
$display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR);
end
assign USB1_PORT_INDCTL = 0;
assign USB1_VBUS_PWRSELECT = 0;
always@(USB1_VBUS_PWRFAULT)
begin
if(USB1_VBUS_PWRFAULT)
$display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR);
end
always@(SRAM_INTIN)
begin
if(SRAM_INTIN)
$display("[%0d] : %0s : SRAM_INTIN is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* DMA */
/* ------------------------------------------- */
assign DMA0_DATYPE = 0;
assign DMA0_DAVALID = 0;
assign DMA0_DRREADY = 0;
assign DMA0_RSTN = 0;
always@(DMA0_ACLK or DMA0_DAREADY or DMA0_DRLAST or DMA0_DRVALID or DMA0_DRTYPE)
begin
if(DMA0_ACLK | DMA0_DAREADY | DMA0_DRLAST | DMA0_DRVALID | DMA0_DRTYPE)
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
end
assign DMA1_DATYPE = 0;
assign DMA1_DAVALID = 0;
assign DMA1_DRREADY = 0;
assign DMA1_RSTN = 0;
always@(DMA1_ACLK or DMA1_DAREADY or DMA1_DRLAST or DMA1_DRVALID or DMA1_DRTYPE)
begin
if(DMA1_ACLK | DMA1_DAREADY | DMA1_DRLAST | DMA1_DRVALID | DMA1_DRTYPE)
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
end
assign DMA2_DATYPE = 0;
assign DMA2_DAVALID = 0;
assign DMA2_DRREADY = 0;
assign DMA2_RSTN = 0;
always@(DMA2_ACLK or DMA2_DAREADY or DMA2_DRLAST or DMA2_DRVALID or DMA2_DRTYPE)
begin
if(DMA2_ACLK | DMA2_DAREADY | DMA2_DRLAST | DMA2_DRVALID | DMA2_DRTYPE)
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
end
assign DMA3_DATYPE = 0;
assign DMA3_DAVALID = 0;
assign DMA3_DRREADY = 0;
assign DMA3_RSTN = 0;
always@(DMA3_ACLK or DMA3_DAREADY or DMA3_DRLAST or DMA3_DRVALID or DMA3_DRTYPE)
begin
if(DMA3_ACLK | DMA3_DAREADY | DMA3_DRLAST | DMA3_DRVALID | DMA3_DRTYPE)
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* FTM */
/* ------------------------------------------- */
assign FTMT_F2P_TRIGACK = 0;
assign FTMT_P2F_TRIG = 0;
assign FTMT_P2F_DEBUG = 0;
always@(FTMD_TRACEIN_DATA or FTMD_TRACEIN_VALID or FTMD_TRACEIN_CLK or
FTMD_TRACEIN_ATID or FTMT_F2P_TRIG or FTMT_F2P_DEBUG or FTMT_P2F_TRIGACK)
begin
if(FTMD_TRACEIN_DATA | FTMD_TRACEIN_VALID | FTMD_TRACEIN_CLK | FTMD_TRACEIN_ATID | FTMT_F2P_TRIG | FTMT_F2P_DEBUG | FTMT_P2F_TRIGACK)
$display("[%0d] : %0s : FTM Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* EVENT */
/* ------------------------------------------- */
assign EVENT_EVENTO = 0;
assign EVENT_STANDBYWFE = 0;
assign EVENT_STANDBYWFI = 0;
always@(EVENT_EVENTI)
begin
if(EVENT_EVENTI)
$display("[%0d] : %0s : EVENT Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* MIO */
/* ------------------------------------------- */
always@(MIO)
begin
if(MIO !== 0)
$display("[%0d] : %0s : MIO is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* FCLK_TRIG */
/* ------------------------------------------- */
always@(FCLK_CLKTRIG3_N or FCLK_CLKTRIG2_N or FCLK_CLKTRIG1_N or FCLK_CLKTRIG0_N )
begin
if(FCLK_CLKTRIG3_N | FCLK_CLKTRIG2_N | FCLK_CLKTRIG1_N | FCLK_CLKTRIG0_N )
$display("[%0d] : %0s : FCLK_TRIG is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* MISC */
/* ------------------------------------------- */
always@(FPGA_IDLE_N)
begin
if(FPGA_IDLE_N)
$display("[%0d] : %0s : FPGA_IDLE_N is not supported.",$time, DISP_ERR);
end
always@(DDR_ARB)
begin
if(DDR_ARB !== 0)
$display("[%0d] : %0s : DDR_ARB is not supported.",$time, DISP_ERR);
end
always@(Core0_nFIQ or Core0_nIRQ or Core1_nFIQ or Core1_nIRQ )
begin
if(Core0_nFIQ | Core0_nIRQ | Core1_nFIQ | Core1_nIRQ)
$display("[%0d] : %0s : CORE FIQ,IRQ is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* DDR */
/* ------------------------------------------- */
assign DDR_WEB = 0;
always@(DDR_Clk or DDR_CS_n)
begin
if(!DDR_CS_n)
$display("[%0d] : %0s : EXTERNAL DDR is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* IRQ_P2F */
/* ------------------------------------------- */
assign IRQ_P2F_DMAC_ABORT = 0;
assign IRQ_P2F_DMAC0 = 0;
assign IRQ_P2F_DMAC1 = 0;
assign IRQ_P2F_DMAC2 = 0;
assign IRQ_P2F_DMAC3 = 0;
assign IRQ_P2F_DMAC4 = 0;
assign IRQ_P2F_DMAC5 = 0;
assign IRQ_P2F_DMAC6 = 0;
assign IRQ_P2F_DMAC7 = 0;
assign IRQ_P2F_SMC = 0;
assign IRQ_P2F_QSPI = 0;
assign IRQ_P2F_CTI = 0;
assign IRQ_P2F_GPIO = 0;
assign IRQ_P2F_USB0 = 0;
assign IRQ_P2F_ENET0 = 0;
assign IRQ_P2F_ENET_WAKE0 = 0;
assign IRQ_P2F_SDIO0 = 0;
assign IRQ_P2F_I2C0 = 0;
assign IRQ_P2F_SPI0 = 0;
assign IRQ_P2F_UART0 = 0;
assign IRQ_P2F_CAN0 = 0;
assign IRQ_P2F_USB1 = 0;
assign IRQ_P2F_ENET1 = 0;
assign IRQ_P2F_ENET_WAKE1 = 0;
assign IRQ_P2F_SDIO1 = 0;
assign IRQ_P2F_I2C1 = 0;
assign IRQ_P2F_SPI1 = 0;
assign IRQ_P2F_UART1 = 0;
assign IRQ_P2F_CAN1 = 0;
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: AXI Splitter
// Each transfer received on the AXI handshake slave port is replicated onto
// each of the master ports, and is completed back to the slave (S_READY)
// once all master ports have completed.
//
// M_VALID is asserted combinatorially from S_VALID assertion.
// Each M_VALID is masked off beginning the cycle after each M_READY is
// received (if S_READY remains low) until the cycle after both S_VALID
// and S_READY are asserted.
// S_READY is asserted combinatorially when the last (or all) of the M_READY
// inputs have been received.
// If all M_READYs are asserted when S_VALID is asserted, back-to-back
// handshakes can occur without bubble cycles.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// splitter
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_splitter #
(
parameter integer C_NUM_M = 2 // Number of master ports = [2:16]
)
(
// Global Signals
input wire ACLK,
input wire ARESET,
// Slave Port
input wire S_VALID,
output wire S_READY,
// Master Ports
output wire [C_NUM_M-1:0] M_VALID,
input wire [C_NUM_M-1:0] M_READY
);
reg [C_NUM_M-1:0] m_ready_d;
wire s_ready_i;
wire [C_NUM_M-1:0] m_valid_i;
always @(posedge ACLK) begin
if (ARESET | s_ready_i) m_ready_d <= {C_NUM_M{1\'b0}};
else m_ready_d <= m_ready_d | (m_valid_i & M_READY);
end
assign s_ready_i = &(m_ready_d | M_READY);
assign m_valid_i = {C_NUM_M{S_VALID}} & ~m_ready_d;
assign M_VALID = m_valid_i;
assign S_READY = s_ready_i;
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_fmsw_gp.v
*
* Date : 2012-11
*
* Description : Mimics FMSW switch.
*
*****************************************************************************/
module processing_system7_bfm_v2_0_fmsw_gp(
sw_clk,
rstn,
w_qos_gp0,
r_qos_gp0,
wr_ack_ocm_gp0,
wr_ack_ddr_gp0,
wr_data_gp0,
wr_addr_gp0,
wr_bytes_gp0,
wr_dv_ocm_gp0,
wr_dv_ddr_gp0,
rd_req_ocm_gp0,
rd_req_ddr_gp0,
rd_req_reg_gp0,
rd_addr_gp0,
rd_bytes_gp0,
rd_data_ocm_gp0,
rd_data_ddr_gp0,
rd_data_reg_gp0,
rd_dv_ocm_gp0,
rd_dv_ddr_gp0,
rd_dv_reg_gp0,
w_qos_gp1,
r_qos_gp1,
wr_ack_ocm_gp1,
wr_ack_ddr_gp1,
wr_data_gp1,
wr_addr_gp1,
wr_bytes_gp1,
wr_dv_ocm_gp1,
wr_dv_ddr_gp1,
rd_req_ocm_gp1,
rd_req_ddr_gp1,
rd_req_reg_gp1,
rd_addr_gp1,
rd_bytes_gp1,
rd_data_ocm_gp1,
rd_data_ddr_gp1,
rd_data_reg_gp1,
rd_dv_ocm_gp1,
rd_dv_ddr_gp1,
rd_dv_reg_gp1,
ocm_wr_ack,
ocm_wr_dv,
ocm_rd_req,
ocm_rd_dv,
ddr_wr_ack,
ddr_wr_dv,
ddr_rd_req,
ddr_rd_dv,
reg_rd_req,
reg_rd_dv,
ocm_wr_qos,
ddr_wr_qos,
ocm_rd_qos,
ddr_rd_qos,
reg_rd_qos,
ocm_wr_addr,
ocm_wr_data,
ocm_wr_bytes,
ocm_rd_addr,
ocm_rd_data,
ocm_rd_bytes,
ddr_wr_addr,
ddr_wr_data,
ddr_wr_bytes,
ddr_rd_addr,
ddr_rd_data,
ddr_rd_bytes,
reg_rd_addr,
reg_rd_data,
reg_rd_bytes
);
`include "processing_system7_bfm_v2_0_local_params.v"
input sw_clk;
input rstn;
input [axi_qos_width-1:0]w_qos_gp0;
input [axi_qos_width-1:0]r_qos_gp0;
input [axi_qos_width-1:0]w_qos_gp1;
input [axi_qos_width-1:0]r_qos_gp1;
output [axi_qos_width-1:0]ocm_wr_qos;
output [axi_qos_width-1:0]ocm_rd_qos;
output [axi_qos_width-1:0]ddr_wr_qos;
output [axi_qos_width-1:0]ddr_rd_qos;
output [axi_qos_width-1:0]reg_rd_qos;
output wr_ack_ocm_gp0;
output wr_ack_ddr_gp0;
input [max_burst_bits-1:0] wr_data_gp0;
input [addr_width-1:0] wr_addr_gp0;
input [max_burst_bytes_width:0] wr_bytes_gp0;
output wr_dv_ocm_gp0;
output wr_dv_ddr_gp0;
input rd_req_ocm_gp0;
input rd_req_ddr_gp0;
input rd_req_reg_gp0;
input [addr_width-1:0] rd_addr_gp0;
input [max_burst_bytes_width:0] rd_bytes_gp0;
output [max_burst_bits-1:0] rd_data_ocm_gp0;
output [max_burst_bits-1:0] rd_data_ddr_gp0;
output [max_burst_bits-1:0] rd_data_reg_gp0;
output rd_dv_ocm_gp0;
output rd_dv_ddr_gp0;
output rd_dv_reg_gp0;
output wr_ack_ocm_gp1;
output wr_ack_ddr_gp1;
input [max_burst_bits-1:0] wr_data_gp1;
input [addr_width-1:0] wr_addr_gp1;
input [max_burst_bytes_width:0] wr_bytes_gp1;
output wr_dv_ocm_gp1;
output wr_dv_ddr_gp1;
input rd_req_ocm_gp1;
input rd_req_ddr_gp1;
input rd_req_reg_gp1;
input [addr_width-1:0] rd_addr_gp1;
input [max_burst_bytes_width:0] rd_bytes_gp1;
output [max_burst_bits-1:0] rd_data_ocm_gp1;
output [max_burst_bits-1:0] rd_data_ddr_gp1;
output [max_burst_bits-1:0] rd_data_reg_gp1;
output rd_dv_ocm_gp1;
output rd_dv_ddr_gp1;
output rd_dv_reg_gp1;
input ocm_wr_ack;
output ocm_wr_dv;
output [addr_width-1:0]ocm_wr_addr;
output [max_burst_bits-1:0]ocm_wr_data;
output [max_burst_bytes_width:0]ocm_wr_bytes;
input ocm_rd_dv;
input [max_burst_bits-1:0] ocm_rd_data;
output ocm_rd_req;
output [addr_width-1:0] ocm_rd_addr;
output [max_burst_bytes_width:0] ocm_rd_bytes;
input ddr_wr_ack;
output ddr_wr_dv;
output [addr_width-1:0]ddr_wr_addr;
output [max_burst_bits-1:0]ddr_wr_data;
output [max_burst_bytes_width:0]ddr_wr_bytes;
input ddr_rd_dv;
input [max_burst_bits-1:0] ddr_rd_data;
output ddr_rd_req;
output [addr_width-1:0] ddr_rd_addr;
output [max_burst_bytes_width:0] ddr_rd_bytes;
input reg_rd_dv;
input [max_burst_bits-1:0] reg_rd_data;
output reg_rd_req;
output [addr_width-1:0] reg_rd_addr;
output [max_burst_bytes_width:0] reg_rd_bytes;
processing_system7_bfm_v2_0_arb_wr ocm_gp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_gp0),
.qos2(w_qos_gp1),
.prt_dv1(wr_dv_ocm_gp0),
.prt_dv2(wr_dv_ocm_gp1),
.prt_data1(wr_data_gp0),
.prt_data2(wr_data_gp1),
.prt_addr1(wr_addr_gp0),
.prt_addr2(wr_addr_gp1),
.prt_bytes1(wr_bytes_gp0),
.prt_bytes2(wr_bytes_gp1),
.prt_ack1(wr_ack_ocm_gp0),
.prt_ack2(wr_ack_ocm_gp1),
.prt_req(ocm_wr_dv),
.prt_qos(ocm_wr_qos),
.prt_data(ocm_wr_data),
.prt_addr(ocm_wr_addr),
.prt_bytes(ocm_wr_bytes),
.prt_ack(ocm_wr_ack)
);
processing_system7_bfm_v2_0_arb_wr ddr_gp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_gp0),
.qos2(w_qos_gp1),
.prt_dv1(wr_dv_ddr_gp0),
.prt_dv2(wr_dv_ddr_gp1),
.prt_data1(wr_data_gp0),
.prt_data2(wr_data_gp1),
.prt_addr1(wr_addr_gp0),
.prt_addr2(wr_addr_gp1),
.prt_bytes1(wr_bytes_gp0),
.prt_bytes2(wr_bytes_gp1),
.prt_ack1(wr_ack_ddr_gp0),
.prt_ack2(wr_ack_ddr_gp1),
.prt_req(ddr_wr_dv),
.prt_qos(ddr_wr_qos),
.prt_data(ddr_wr_data),
.prt_addr(ddr_wr_addr),
.prt_bytes(ddr_wr_bytes),
.prt_ack(ddr_wr_ack)
);
processing_system7_bfm_v2_0_arb_rd ocm_gp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_gp0),
.qos2(r_qos_gp1),
.prt_req1(rd_req_ocm_gp0),
.prt_req2(rd_req_ocm_gp1),
.prt_data1(rd_data_ocm_gp0),
.prt_data2(rd_data_ocm_gp1),
.prt_addr1(rd_addr_gp0),
.prt_addr2(rd_addr_gp1),
.prt_bytes1(rd_bytes_gp0),
.prt_bytes2(rd_bytes_gp1),
.prt_dv1(rd_dv_ocm_gp0),
.prt_dv2(rd_dv_ocm_gp1),
.prt_req(ocm_rd_req),
.prt_qos(ocm_rd_qos),
.prt_data(ocm_rd_data),
.prt_addr(ocm_rd_addr),
.prt_bytes(ocm_rd_bytes),
.prt_dv(ocm_rd_dv)
);
processing_system7_bfm_v2_0_arb_rd ddr_gp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_gp0),
.qos2(r_qos_gp1),
.prt_req1(rd_req_ddr_gp0),
.prt_req2(rd_req_ddr_gp1),
.prt_data1(rd_data_ddr_gp0),
.prt_data2(rd_data_ddr_gp1),
.prt_addr1(rd_addr_gp0),
.prt_addr2(rd_addr_gp1),
.prt_bytes1(rd_bytes_gp0),
.prt_bytes2(rd_bytes_gp1),
.prt_dv1(rd_dv_ddr_gp0),
.prt_dv2(rd_dv_ddr_gp1),
.prt_req(ddr_rd_req),
.prt_qos(ddr_rd_qos),
.prt_data(ddr_rd_data),
.prt_addr(ddr_rd_addr),
.prt_bytes(ddr_rd_bytes),
.prt_dv(ddr_rd_dv)
);
processing_system7_bfm_v2_0_arb_rd reg_gp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_gp0),
.qos2(r_qos_gp1),
.prt_req1(rd_req_reg_gp0),
.prt_req2(rd_req_reg_gp1),
.prt_data1(rd_data_reg_gp0),
.prt_data2(rd_data_reg_gp1),
.prt_addr1(rd_addr_gp0),
.prt_addr2(rd_addr_gp1),
.prt_bytes1(rd_bytes_gp0),
.prt_bytes2(rd_bytes_gp1),
.prt_dv1(rd_dv_reg_gp0),
.prt_dv2(rd_dv_reg_gp1),
.prt_req(reg_rd_req),
.prt_qos(reg_rd_qos),
.prt_data(reg_rd_data),
.prt_addr(reg_rd_addr),
.prt_bytes(reg_rd_bytes),
.prt_dv(reg_rd_dv)
);
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 4
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module base_zynq_design_auto_pc_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(0),
.C_IGNORE_ID(1),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1\'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1\'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1\'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1\'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1\'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1\'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(1\'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1\'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(1\'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1\'H1),
.m_axi_ruser(1\'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_arb_rd.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between 2 read requests from 2 ports.
*
*****************************************************************************/
module processing_system7_bfm_v2_0_arb_rd(
rstn,
sw_clk,
qos1,
qos2,
prt_req1,
prt_req2,
prt_bytes1,
prt_bytes2,
prt_addr1,
prt_addr2,
prt_data1,
prt_data2,
prt_dv1,
prt_dv2,
prt_req,
prt_qos,
prt_addr,
prt_bytes,
prt_data,
prt_dv
);
`include "processing_system7_bfm_v2_0_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2;
input prt_req1, prt_req2;
input [addr_width-1:0] prt_addr1, prt_addr2;
input [max_burst_bytes_width:0] prt_bytes1, prt_bytes2;
output reg prt_dv1, prt_dv2;
output reg [max_burst_bits-1:0] prt_data1,prt_data2;
output reg prt_req;
output reg [axi_qos_width-1:0] prt_qos;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
input [max_burst_bits-1:0] prt_data;
input prt_dv;
parameter wait_req = 2\'b00, serv_req1 = 2\'b01, serv_req2 = 2\'b10,wait_dv_low = 2\'b11;
reg [1:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1\'b0;
prt_dv1 = 1\'b0;
prt_dv2 = 1\'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_dv1 = 1\'b0;
prt_dv2 = 1\'b0;
prt_req = 0;
if(prt_req1 && !prt_req2) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(!prt_req1 && prt_req2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req1 && prt_req2) begin
if(qos1 > qos2) begin
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else if(qos1 < qos2) begin
prt_req = 1;
prt_addr = prt_addr2;
prt_qos = qos2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req1:begin
state = serv_req1;
prt_dv2 = 1\'b0;
if(prt_dv) begin
prt_dv1 = 1\'b1;
prt_data1 = prt_data;
prt_req = 0;
if(prt_req2) begin
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
state = wait_dv_low;
//state = wait_req;
end
end
end
serv_req2:begin
state = serv_req2;
prt_dv1 = 1\'b0;
if(prt_dv) begin
prt_dv2 = 1\'b1;
prt_data2 = prt_data;
prt_req = 0;
if(prt_req1) begin
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else begin
state = wait_dv_low;
//state = wait_req;
end
end
end
wait_dv_low:begin
prt_dv1 = 1\'b0;
prt_dv2 = 1\'b0;
state = wait_dv_low;
if(!prt_dv)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule
|
//-----------------------------------------------------------------------------
// processing_system7
// processor sub system wrapper
//-----------------------------------------------------------------------------
//
// ************************************************************************
// ** DISCLAIMER OF LIABILITY **
// ** **
// ** This file contains proprietary and confidential information of **
// ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
// ** from Xilinx, and may be used, copied and/or diSCLosed only **
// ** pursuant to the terms of a valid license agreement with Xilinx. **
// ** **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
// ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
// ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
// ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
// ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
// ** does not warrant that functions included in the Materials will **
// ** meet the requirements of Licensee, or that the operation of the **
// ** Materials will be uninterrupted or error-free, or that defects **
// ** in the Materials will be corrected. Furthermore, Xilinx does **
// ** not warrant or make any representations regarding use, or the **
// ** results of the use, of the Materials in terms of correctness, **
// ** accuracy, reliability or otherwise. **
// ** **
// ** Xilinx products are not designed or intended to be fail-safe, **
// ** or for use in any application requiring fail-safe performance, **
// ** such as life-support or safety devices or systems, Class III **
// ** medical devices, nuclear facilities, applications related to **
// ** the deployment of airbags, or any other applications that could **
// ** lead to death, personal injury or severe property or **
// ** environmental damage (individually and collectively, "critical **
// ** applications"). Customer assumes the sole risk and liability **
// ** of any use of Xilinx products in critical applications, **
// ** subject only to applicable laws and regulations governing **
// ** limitations on product liability. **
// ** **
// ** Copyright 2010 Xilinx, Inc. **
// ** All rights reserved. **
// ** **
// ** This disclaimer and copyright notice must be retained as part **
// ** of this file at all times. **
// ************************************************************************
//
//-----------------------------------------------------------------------------
// Filename: processing_system7_v5_5_processing_system7.v
// Version: v1.00.a
// Description: This is the wrapper file for PSS.
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of
// pss_wrapper.
//
// --processing_system7_v5_5_processing_system7.v
// --PS7.v - Unisim component
//-----------------------------------------------------------------------------
// Author: SD
//
// History:
//
// SD 09/20/11 -- First version
// ~~~~~~
// Created the first version v2.00.a
// ^^^^^^
//------------------------------------------------------------------------------
// ^^^^^^
// SR 11/25/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// 1. Changed all clock, reset and clktrig ports to be individual
// signals instead of vectors. This is required for modeling of tools.
// 2. Interrupts are now defined as individual signals as well.
// 3. Added Clk buffer logic for FCLK_CLK
// 4. Includes the ACP related changes done
//
// TODO:
// 1. C_NUM_F2P_INTR_INPUTS needs to have control on the
// number of interrupt ports connected for IRQ_F2P.
//
//------------------------------------------------------------------------------
// ^^^^^^
// KP 12/07/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_NUM_F2P_INTR_INPUTS taken into account for IRQ_F2P
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/09/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_FCLK_CLK0_BUF to C_FCLK_CLK3_BUF parameters were updated
// to STRING and fix for CR 640523
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/13/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// Updated IRQ_F2P logic to address CR 641523.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/01/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Updated SDIO logic to address CR 636210.
// |
// Added C_PS7_SI_REV parameter to track SI Rev
// Removed compress/decompress logic to address CR 642527.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/27/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// TTC(0,1)_WAVE_OUT and TTC(0,1)_CLK_IN vector signals are made as individual
// ports as fix for CR 646379
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/05/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Added/updated compress/decompress logic to address 648393
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/14/12 -- v4.00.a version
// ~~~~~~~
// Unused parameters deleted CR 651120
// Addressed CR 651751
//------------------------------------------------------------------------------
// ^^^^^^
// NR 04/17/12 -- v4.01.a version
// ~~~~~~~
// Added FTM trace buffer functionality
// Added support for ACP AxUSER ports local update
//------------------------------------------------------------------------------
// ^^^^^^
// VR 05/18/12 -- v4.01.a version
// ~~~~~~~
// Fixed CR#659157
//------------------------------------------------------------------------------
// ^^^^^^
// VR 07/25/12 -- v4.01.a version
// ~~~~~~~
// Changed S_AXI_HP{1,2}_WACOUNT port\'s width to 6 from 8 to match unisim model
// Changed fclk_clktrig_gnd width to 4 from 16 to match unisim model
//------------------------------------------------------------------------------
// ^^^^^^
// VR 11/06/12 -- v5.00 version
// ~~~~~~~
// CR #682573
// Added BIBUF to fixed IO ports and IBUF to fixed input ports
//------------------------------------------------------------------------------
(*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={8} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={I2C} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={I2C} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={50} usageRate={0.5} />/>" *)
(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=533.333313, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=14, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=49.5, PCW_UIPARAM_DDR_T_RAS_MIN=36.0, PCW_UIPARAM_DDR_T_FAW=45.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.025, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.028, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=-0.009, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=-0.061, PCW_UIPARAM_DDR_BOARD_DELAY0=0.41, PCW_UIPARAM_DDR_BOARD_DELAY1=0.411, PCW_UIPARAM_DDR_BOARD_DELAY2=0.341, PCW_UIPARAM_DDR_BOARD_DELAY3=0.358, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=68.4725, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=71.086, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=66.794, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=108.7385, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=64.1705, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=63.686, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=68.46, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=105.4895, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=666.666667, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=50, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=50, PCW_FPGA1_PERIPHERAL_FREQMHZ=150.000000, PCW_FPGA2_PERIPHERAL_FREQMHZ=148.5, PCW_FPGA3_PERIPHERAL_FREQMHZ=50, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=40, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=32, PCW_CPU_CPU_PLL_FREQMHZ=1333.333, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1066.667, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=50, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=10, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_FTM_CTI_IN0=DISABLED, PCW_FTM_CTI_IN1=DISABLED, PCW_FTM_CTI_IN2=DISABLED, PCW_FTM_CTI_IN3=DISABLED, PCW_FTM_CTI_OUT0=DISABLED, PCW_FTM_CTI_OUT1=DISABLED, PCW_FTM_CTI_OUT2=DISABLED, PCW_FTM_CTI_OUT3=DISABLED, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3, PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41J128M16 HA-15E, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=2048 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=1, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=0, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=1, PCW_SD0_SD0_IO=MIO 40 .. 45, PCW_SD0_GRP_CD_ENABLE=1, PCW_SD0_GRP_CD_IO=MIO 47, PCW_SD0_GRP_WP_ENABLE=1, PCW_SD0_GRP_WP_IO=MIO 46, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 48 .. 49, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=1, PCW_TTC0_TTC0_IO=EMIO, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=0, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=1, PCW_I2C0_I2C0_IO=MIO 10 .. 11, PCW_I2C0_GRP_INT_ENABLE=0, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=1, PCW_I2C1_I2C1_IO=EMIO, PCW_I2C1_GRP_INT_ENABLE=1, PCW_I2C1_GRP_INT_IO=EMIO, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=DDR PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=1, PCW_FPGA_FCLK2_ENABLE=1, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=2, PCW_NOR_SRAM_CS0_T_RC=2, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=2, PCW_NOR_SRAM_CS1_T_RC=2, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=2, PCW_NOR_CS0_T_RC=2, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=2, PCW_NOR_CS1_T_RC=2, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=2, PCW_NAND_CYCLES_T_RC=2 }" *)
module processing_system7_v5_5_processing_system7
#(
parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
parameter integer C_NUM_F2P_INTR_INPUTS = 1,
parameter C_FCLK_CLK0_BUF = "TRUE",
parameter C_FCLK_CLK1_BUF = "TRUE",
parameter C_FCLK_CLK2_BUF = "TRUE",
parameter C_FCLK_CLK3_BUF = "TRUE",
parameter integer C_EMIO_GPIO_WIDTH = 64,
parameter integer C_INCLUDE_TRACE_BUFFER = 0,
parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_TRACE_PIPELINE_WIDTH = 8,
parameter C_PS7_SI_REV = "PRODUCTION",
parameter integer C_EN_EMIO_ENET0 = 0,
parameter integer C_EN_EMIO_ENET1 = 0,
parameter integer C_EN_EMIO_TRACE = 0,
parameter integer C_DQ_WIDTH = 32,
parameter integer C_DQS_WIDTH = 4,
parameter integer C_DM_WIDTH = 4,
parameter integer C_MIO_PRIMITIVE = 54,
parameter\t C_PACKAGE_NAME = "clg484",
parameter C_IRQ_F2P_MODE = "DIRECT",
parameter C_TRACE_INTERNAL_WIDTH = 32,
parameter integer C_EN_EMIO_PJTAG = 0
)
(
//FMIO =========================================
//FMIO CAN0
output CAN0_PHY_TX,
input CAN0_PHY_RX,
//FMIO CAN1
output CAN1_PHY_TX,
input CAN1_PHY_RX,
//FMIO ENET0
output reg ENET0_GMII_TX_EN,
output reg ENET0_GMII_TX_ER,
output ENET0_MDIO_MDC,
output ENET0_MDIO_O,
output ENET0_MDIO_T,
output ENET0_PTP_DELAY_REQ_RX,
output ENET0_PTP_DELAY_REQ_TX,
output ENET0_PTP_PDELAY_REQ_RX,
output ENET0_PTP_PDELAY_REQ_TX,
output ENET0_PTP_PDELAY_RESP_RX,
output ENET0_PTP_PDELAY_RESP_TX,
output ENET0_PTP_SYNC_FRAME_RX,
output ENET0_PTP_SYNC_FRAME_TX,
output ENET0_SOF_RX,
output ENET0_SOF_TX,
output reg [7:0] ENET0_GMII_TXD,
input ENET0_GMII_COL,
input ENET0_GMII_CRS,
input ENET0_GMII_RX_CLK,
input ENET0_GMII_RX_DV,
input ENET0_GMII_RX_ER,
input ENET0_GMII_TX_CLK,
input ENET0_MDIO_I,
input ENET0_EXT_INTIN,
input [7:0] ENET0_GMII_RXD,
//FMIO ENET1
output reg ENET1_GMII_TX_EN,
output reg ENET1_GMII_TX_ER,
output ENET1_MDIO_MDC,
output ENET1_MDIO_O,
output ENET1_MDIO_T,
output ENET1_PTP_DELAY_REQ_RX,
output ENET1_PTP_DELAY_REQ_TX,
output ENET1_PTP_PDELAY_REQ_RX,
output ENET1_PTP_PDELAY_REQ_TX,
output ENET1_PTP_PDELAY_RESP_RX,
output ENET1_PTP_PDELAY_RESP_TX,
output ENET1_PTP_SYNC_FRAME_RX,
output ENET1_PTP_SYNC_FRAME_TX,
output ENET1_SOF_RX,
output ENET1_SOF_TX,
output reg [7:0] ENET1_GMII_TXD,
input ENET1_GMII_COL,
input ENET1_GMII_CRS,
input ENET1_GMII_RX_CLK,
input ENET1_GMII_RX_DV,
input ENET1_GMII_RX_ER,
input ENET1_GMII_TX_CLK,
input ENET1_MDIO_I,
input ENET1_EXT_INTIN,
input [7:0] ENET1_GMII_RXD,
//FMIO GPIO
input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,
//FMIO I2C0
input I2C0_SDA_I,
output I2C0_SDA_O,
output I2C0_SDA_T,
input I2C0_SCL_I,
output I2C0_SCL_O,
output I2C0_SCL_T,
//FMIO I2C1
input I2C1_SDA_I,
output I2C1_SDA_O,
output I2C1_SDA_T,
input I2C1_SCL_I,
output I2C1_SCL_O,
output I2C1_SCL_T,
//FMIO PJTAG
input PJTAG_TCK,
input PJTAG_TMS,
input PJTAG_TDI,
output PJTAG_TDO,
//FMIO SDIO0
output SDIO0_CLK,
input SDIO0_CLK_FB,
output SDIO0_CMD_O,
input SDIO0_CMD_I,
output SDIO0_CMD_T,
input [3:0] SDIO0_DATA_I,
output [3:0] SDIO0_DATA_O,
output [3:0] SDIO0_DATA_T,
output SDIO0_LED,
input SDIO0_CDN,
input SDIO0_WP,
output SDIO0_BUSPOW,
output [2:0] SDIO0_BUSVOLT,
//FMIO SDIO1
output SDIO1_CLK,
input SDIO1_CLK_FB,
output SDIO1_CMD_O,
input SDIO1_CMD_I,
output SDIO1_CMD_T,
input [3:0] SDIO1_DATA_I,
output [3:0] SDIO1_DATA_O,
output [3:0] SDIO1_DATA_T,
output SDIO1_LED,
input SDIO1_CDN,
input SDIO1_WP,
output SDIO1_BUSPOW,
output [2:0] SDIO1_BUSVOLT,
//FMIO SPI0
input SPI0_SCLK_I,
output SPI0_SCLK_O,
output SPI0_SCLK_T,
input SPI0_MOSI_I,
output SPI0_MOSI_O,
output SPI0_MOSI_T,
input SPI0_MISO_I,
output SPI0_MISO_O,
output SPI0_MISO_T,
input SPI0_SS_I,
output SPI0_SS_O,
output SPI0_SS1_O,
output SPI0_SS2_O,
output SPI0_SS_T,
//FMIO SPI1
input SPI1_SCLK_I,
output SPI1_SCLK_O,
output SPI1_SCLK_T,
input SPI1_MOSI_I,
output SPI1_MOSI_O,
output SPI1_MOSI_T,
input SPI1_MISO_I,
output SPI1_MISO_O,
output SPI1_MISO_T,
input SPI1_SS_I,
output SPI1_SS_O,
output SPI1_SS1_O,
output SPI1_SS2_O,
output SPI1_SS_T,
//FMIO UART0
output UART0_DTRN,
output UART0_RTSN,
output UART0_TX,
input UART0_CTSN,
input UART0_DCDN,
input UART0_DSRN,
input UART0_RIN,
input UART0_RX,
//FMIO UART1
output UART1_DTRN,
output UART1_RTSN,
output UART1_TX,
input UART1_CTSN,
input UART1_DCDN,
input UART1_DSRN,
input UART1_RIN,
input UART1_RX,
//FMIO TTC0
output \t\tTTC0_WAVE0_OUT,
output \t\tTTC0_WAVE1_OUT,
output \t\tTTC0_WAVE2_OUT,
input \t\tTTC0_CLK0_IN,
input \t\tTTC0_CLK1_IN,
input \t\tTTC0_CLK2_IN,
//FMIO TTC1
output \t\tTTC1_WAVE0_OUT,
output \t\tTTC1_WAVE1_OUT,
output \t\tTTC1_WAVE2_OUT,
input \t\tTTC1_CLK0_IN,
input \t\tTTC1_CLK1_IN,
input \t\tTTC1_CLK2_IN,
//WDT
input WDT_CLK_IN,
output WDT_RST_OUT,
//FTPORT
input TRACE_CLK,
output TRACE_CTL,
output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA,
output reg\t\t TRACE_CLK_OUT,
// USB
output [1:0] USB0_PORT_INDCTL,
output USB0_VBUS_PWRSELECT,
input USB0_VBUS_PWRFAULT,
output [1:0] USB1_PORT_INDCTL,
output USB1_VBUS_PWRSELECT,
input USB1_VBUS_PWRFAULT,
input SRAM_INTIN,
//AIO ===================================================
//M_AXI_GP0
// -- Output
output M_AXI_GP0_ARESETN,
output M_AXI_GP0_ARVALID,
output M_AXI_GP0_AWVALID,
output M_AXI_GP0_BREADY,
output M_AXI_GP0_RREADY,
output M_AXI_GP0_WLAST,
output M_AXI_GP0_WVALID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
output [1:0] M_AXI_GP0_ARBURST,
output [1:0] M_AXI_GP0_ARLOCK,
output [2:0] M_AXI_GP0_ARSIZE,
output [1:0] M_AXI_GP0_AWBURST,
output [1:0] M_AXI_GP0_AWLOCK,
output [2:0] M_AXI_GP0_AWSIZE,
output [2:0] M_AXI_GP0_ARPROT,
output [2:0] M_AXI_GP0_AWPROT,
output [31:0] M_AXI_GP0_ARADDR,
output [31:0] M_AXI_GP0_AWADDR,
output [31:0] M_AXI_GP0_WDATA,
output [3:0] M_AXI_GP0_ARCACHE,
output [3:0] M_AXI_GP0_ARLEN,
output [3:0] M_AXI_GP0_ARQOS,
output [3:0] M_AXI_GP0_AWCACHE,
output [3:0] M_AXI_GP0_AWLEN,
output [3:0] M_AXI_GP0_AWQOS,
output [3:0] M_AXI_GP0_WSTRB,
// -- Input
input M_AXI_GP0_ACLK,
input M_AXI_GP0_ARREADY,
input M_AXI_GP0_AWREADY,
input M_AXI_GP0_BVALID,
input M_AXI_GP0_RLAST,
input M_AXI_GP0_RVALID,
input M_AXI_GP0_WREADY,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
input [1:0] M_AXI_GP0_BRESP,
input [1:0] M_AXI_GP0_RRESP,
input [31:0] M_AXI_GP0_RDATA,
//M_AXI_GP1
// -- Output
output M_AXI_GP1_ARESETN,
output M_AXI_GP1_ARVALID,
output M_AXI_GP1_AWVALID,
output M_AXI_GP1_BREADY,
output M_AXI_GP1_RREADY,
output M_AXI_GP1_WLAST,
output M_AXI_GP1_WVALID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
output [1:0] M_AXI_GP1_ARBURST,
output [1:0] M_AXI_GP1_ARLOCK,
output [2:0] M_AXI_GP1_ARSIZE,
output [1:0] M_AXI_GP1_AWBURST,
output [1:0] M_AXI_GP1_AWLOCK,
output [2:0] M_AXI_GP1_AWSIZE,
output [2:0] M_AXI_GP1_ARPROT,
output [2:0] M_AXI_GP1_AWPROT,
output [31:0] M_AXI_GP1_ARADDR,
output [31:0] M_AXI_GP1_AWADDR,
output [31:0] M_AXI_GP1_WDATA,
output [3:0] M_AXI_GP1_ARCACHE,
output [3:0] M_AXI_GP1_ARLEN,
output [3:0] M_AXI_GP1_ARQOS,
output [3:0] M_AXI_GP1_AWCACHE,
output [3:0] M_AXI_GP1_AWLEN,
output [3:0] M_AXI_GP1_AWQOS,
output [3:0] M_AXI_GP1_WSTRB,
// -- Input
input M_AXI_GP1_ACLK,
input M_AXI_GP1_ARREADY,
input M_AXI_GP1_AWREADY,
input M_AXI_GP1_BVALID,
input M_AXI_GP1_RLAST,
input M_AXI_GP1_RVALID,
input M_AXI_GP1_WREADY,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
input [1:0] M_AXI_GP1_BRESP,
input [1:0] M_AXI_GP1_RRESP,
input [31:0] M_AXI_GP1_RDATA,
// S_AXI_GP0
// -- Output
output S_AXI_GP0_ARESETN,
output S_AXI_GP0_ARREADY,
output S_AXI_GP0_AWREADY,
output S_AXI_GP0_BVALID,
output S_AXI_GP0_RLAST,
output S_AXI_GP0_RVALID,
output S_AXI_GP0_WREADY,
output [1:0] S_AXI_GP0_BRESP,
output [1:0] S_AXI_GP0_RRESP,
output [31:0] S_AXI_GP0_RDATA,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
// -- Input
input S_AXI_GP0_ACLK,
input S_AXI_GP0_ARVALID,
input S_AXI_GP0_AWVALID,
input S_AXI_GP0_BREADY,
input S_AXI_GP0_RREADY,
input S_AXI_GP0_WLAST,
input S_AXI_GP0_WVALID,
input [1:0] S_AXI_GP0_ARBURST,
input [1:0] S_AXI_GP0_ARLOCK,
input [2:0] S_AXI_GP0_ARSIZE,
input [1:0] S_AXI_GP0_AWBURST,
input [1:0] S_AXI_GP0_AWLOCK,
input [2:0] S_AXI_GP0_AWSIZE,
input [2:0] S_AXI_GP0_ARPROT,
input [2:0] S_AXI_GP0_AWPROT,
input [31:0] S_AXI_GP0_ARADDR,
input [31:0] S_AXI_GP0_AWADDR,
input [31:0] S_AXI_GP0_WDATA,
input [3:0] S_AXI_GP0_ARCACHE,
input [3:0] S_AXI_GP0_ARLEN,
input [3:0] S_AXI_GP0_ARQOS,
input [3:0] S_AXI_GP0_AWCACHE,
input [3:0] S_AXI_GP0_AWLEN,
input [3:0] S_AXI_GP0_AWQOS,
input [3:0] S_AXI_GP0_WSTRB,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,
// S_AXI_GP1
// -- Output
output S_AXI_GP1_ARESETN,
output S_AXI_GP1_ARREADY,
output S_AXI_GP1_AWREADY,
output S_AXI_GP1_BVALID,
output S_AXI_GP1_RLAST,
output S_AXI_GP1_RVALID,
output S_AXI_GP1_WREADY,
output [1:0] S_AXI_GP1_BRESP,
output [1:0] S_AXI_GP1_RRESP,
output [31:0] S_AXI_GP1_RDATA,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
// -- Input
input S_AXI_GP1_ACLK,
input S_AXI_GP1_ARVALID,
input S_AXI_GP1_AWVALID,
input S_AXI_GP1_BREADY,
input S_AXI_GP1_RREADY,
input S_AXI_GP1_WLAST,
input S_AXI_GP1_WVALID,
input [1:0] S_AXI_GP1_ARBURST,
input [1:0] S_AXI_GP1_ARLOCK,
input [2:0] S_AXI_GP1_ARSIZE,
input [1:0] S_AXI_GP1_AWBURST,
input [1:0] S_AXI_GP1_AWLOCK,
input [2:0] S_AXI_GP1_AWSIZE,
input [2:0] S_AXI_GP1_ARPROT,
input [2:0] S_AXI_GP1_AWPROT,
input [31:0] S_AXI_GP1_ARADDR,
input [31:0] S_AXI_GP1_AWADDR,
input [31:0] S_AXI_GP1_WDATA,
input [3:0] S_AXI_GP1_ARCACHE,
input [3:0] S_AXI_GP1_ARLEN,
input [3:0] S_AXI_GP1_ARQOS,
input [3:0] S_AXI_GP1_AWCACHE,
input [3:0] S_AXI_GP1_AWLEN,
input [3:0] S_AXI_GP1_AWQOS,
input [3:0] S_AXI_GP1_WSTRB,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,
//S_AXI_ACP
// -- Output
output S_AXI_ACP_ARESETN,
output S_AXI_ACP_ARREADY,
output S_AXI_ACP_AWREADY,
output S_AXI_ACP_BVALID,
output S_AXI_ACP_RLAST,
output S_AXI_ACP_RVALID,
output S_AXI_ACP_WREADY,
output [1:0] S_AXI_ACP_BRESP,
output [1:0] S_AXI_ACP_RRESP,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
output [63:0] S_AXI_ACP_RDATA,
// -- Input
input S_AXI_ACP_ACLK,
input S_AXI_ACP_ARVALID,
input S_AXI_ACP_AWVALID,
input S_AXI_ACP_BREADY,
input S_AXI_ACP_RREADY,
input S_AXI_ACP_WLAST,
input S_AXI_ACP_WVALID,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
input [2:0] S_AXI_ACP_ARPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
input [2:0] S_AXI_ACP_AWPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
input [31:0] S_AXI_ACP_ARADDR,
input [31:0] S_AXI_ACP_AWADDR,
input [3:0] S_AXI_ACP_ARCACHE,
input [3:0] S_AXI_ACP_ARLEN,
input [3:0] S_AXI_ACP_ARQOS,
input [3:0] S_AXI_ACP_AWCACHE,
input [3:0] S_AXI_ACP_AWLEN,
input [3:0] S_AXI_ACP_AWQOS,
input [1:0] S_AXI_ACP_ARBURST,
input [1:0] S_AXI_ACP_ARLOCK,
input [2:0] S_AXI_ACP_ARSIZE,
input [1:0] S_AXI_ACP_AWBURST,
input [1:0] S_AXI_ACP_AWLOCK,
input [2:0] S_AXI_ACP_AWSIZE,
input [4:0] S_AXI_ACP_ARUSER,
input [4:0] S_AXI_ACP_AWUSER,
input [63:0] S_AXI_ACP_WDATA,
input [7:0] S_AXI_ACP_WSTRB,
// S_AXI_HP_0
// -- Output
output S_AXI_HP0_ARESETN,
output S_AXI_HP0_ARREADY,
output S_AXI_HP0_AWREADY,
output S_AXI_HP0_BVALID,
output S_AXI_HP0_RLAST,
output S_AXI_HP0_RVALID,
output S_AXI_HP0_WREADY,
output [1:0] S_AXI_HP0_BRESP,
output [1:0] S_AXI_HP0_RRESP,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
output [7:0] S_AXI_HP0_RCOUNT,
output [7:0] S_AXI_HP0_WCOUNT,
output [2:0] S_AXI_HP0_RACOUNT,
output [5:0] S_AXI_HP0_WACOUNT,
// -- Input
input S_AXI_HP0_ACLK,
input S_AXI_HP0_ARVALID,
input S_AXI_HP0_AWVALID,
input S_AXI_HP0_BREADY,
input S_AXI_HP0_RDISSUECAP1_EN,
input S_AXI_HP0_RREADY,
input S_AXI_HP0_WLAST,
input S_AXI_HP0_WRISSUECAP1_EN,
input S_AXI_HP0_WVALID,
input [1:0] S_AXI_HP0_ARBURST,
input [1:0] S_AXI_HP0_ARLOCK,
input [2:0] S_AXI_HP0_ARSIZE,
input [1:0] S_AXI_HP0_AWBURST,
input [1:0] S_AXI_HP0_AWLOCK,
input [2:0] S_AXI_HP0_AWSIZE,
input [2:0] S_AXI_HP0_ARPROT,
input [2:0] S_AXI_HP0_AWPROT,
input [31:0] S_AXI_HP0_ARADDR,
input [31:0] S_AXI_HP0_AWADDR,
input [3:0] S_AXI_HP0_ARCACHE,
input [3:0] S_AXI_HP0_ARLEN,
input [3:0] S_AXI_HP0_ARQOS,
input [3:0] S_AXI_HP0_AWCACHE,
input [3:0] S_AXI_HP0_AWLEN,
input [3:0] S_AXI_HP0_AWQOS,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,
// S_AXI_HP1
// -- Output
output S_AXI_HP1_ARESETN,
output S_AXI_HP1_ARREADY,
output S_AXI_HP1_AWREADY,
output S_AXI_HP1_BVALID,
output S_AXI_HP1_RLAST,
output S_AXI_HP1_RVALID,
output S_AXI_HP1_WREADY,
output [1:0] S_AXI_HP1_BRESP,
output [1:0] S_AXI_HP1_RRESP,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
output [7:0] S_AXI_HP1_RCOUNT,
output [7:0] S_AXI_HP1_WCOUNT,
output [2:0] S_AXI_HP1_RACOUNT,
output [5:0] S_AXI_HP1_WACOUNT,
// -- Input
input S_AXI_HP1_ACLK,
input S_AXI_HP1_ARVALID,
input S_AXI_HP1_AWVALID,
input S_AXI_HP1_BREADY,
input S_AXI_HP1_RDISSUECAP1_EN,
input S_AXI_HP1_RREADY,
input S_AXI_HP1_WLAST,
input S_AXI_HP1_WRISSUECAP1_EN,
input S_AXI_HP1_WVALID,
input [1:0] S_AXI_HP1_ARBURST,
input [1:0] S_AXI_HP1_ARLOCK,
input [2:0] S_AXI_HP1_ARSIZE,
input [1:0] S_AXI_HP1_AWBURST,
input [1:0] S_AXI_HP1_AWLOCK,
input [2:0] S_AXI_HP1_AWSIZE,
input [2:0] S_AXI_HP1_ARPROT,
input [2:0] S_AXI_HP1_AWPROT,
input [31:0] S_AXI_HP1_ARADDR,
input [31:0] S_AXI_HP1_AWADDR,
input [3:0] S_AXI_HP1_ARCACHE,
input [3:0] S_AXI_HP1_ARLEN,
input [3:0] S_AXI_HP1_ARQOS,
input [3:0] S_AXI_HP1_AWCACHE,
input [3:0] S_AXI_HP1_AWLEN,
input [3:0] S_AXI_HP1_AWQOS,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,
// S_AXI_HP2
// -- Output
output S_AXI_HP2_ARESETN,
output S_AXI_HP2_ARREADY,
output S_AXI_HP2_AWREADY,
output S_AXI_HP2_BVALID,
output S_AXI_HP2_RLAST,
output S_AXI_HP2_RVALID,
output S_AXI_HP2_WREADY,
output [1:0] S_AXI_HP2_BRESP,
output [1:0] S_AXI_HP2_RRESP,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
output [7:0] S_AXI_HP2_RCOUNT,
output [7:0] S_AXI_HP2_WCOUNT,
output [2:0] S_AXI_HP2_RACOUNT,
output [5:0] S_AXI_HP2_WACOUNT,
// -- Input
input S_AXI_HP2_ACLK,
input S_AXI_HP2_ARVALID,
input S_AXI_HP2_AWVALID,
input S_AXI_HP2_BREADY,
input S_AXI_HP2_RDISSUECAP1_EN,
input S_AXI_HP2_RREADY,
input S_AXI_HP2_WLAST,
input S_AXI_HP2_WRISSUECAP1_EN,
input S_AXI_HP2_WVALID,
input [1:0] S_AXI_HP2_ARBURST,
input [1:0] S_AXI_HP2_ARLOCK,
input [2:0] S_AXI_HP2_ARSIZE,
input [1:0] S_AXI_HP2_AWBURST,
input [1:0] S_AXI_HP2_AWLOCK,
input [2:0] S_AXI_HP2_AWSIZE,
input [2:0] S_AXI_HP2_ARPROT,
input [2:0] S_AXI_HP2_AWPROT,
input [31:0] S_AXI_HP2_ARADDR,
input [31:0] S_AXI_HP2_AWADDR,
input [3:0] S_AXI_HP2_ARCACHE,
input [3:0] S_AXI_HP2_ARLEN,
input [3:0] S_AXI_HP2_ARQOS,
input [3:0] S_AXI_HP2_AWCACHE,
input [3:0] S_AXI_HP2_AWLEN,
input [3:0] S_AXI_HP2_AWQOS,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,
// S_AXI_HP_3
// -- Output
output S_AXI_HP3_ARESETN,
output S_AXI_HP3_ARREADY,
output S_AXI_HP3_AWREADY,
output S_AXI_HP3_BVALID,
output S_AXI_HP3_RLAST,
output S_AXI_HP3_RVALID,
output S_AXI_HP3_WREADY,
output [1:0] S_AXI_HP3_BRESP,
output [1:0] S_AXI_HP3_RRESP,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
output [7:0] S_AXI_HP3_RCOUNT,
output [7:0] S_AXI_HP3_WCOUNT,
output [2:0] S_AXI_HP3_RACOUNT,
output [5:0] S_AXI_HP3_WACOUNT,
// -- Input
input S_AXI_HP3_ACLK,
input S_AXI_HP3_ARVALID,
input S_AXI_HP3_AWVALID,
input S_AXI_HP3_BREADY,
input S_AXI_HP3_RDISSUECAP1_EN,
input S_AXI_HP3_RREADY,
input S_AXI_HP3_WLAST,
input S_AXI_HP3_WRISSUECAP1_EN,
input S_AXI_HP3_WVALID,
input [1:0] S_AXI_HP3_ARBURST,
input [1:0] S_AXI_HP3_ARLOCK,
input [2:0] S_AXI_HP3_ARSIZE,
input [1:0] S_AXI_HP3_AWBURST,
input [1:0] S_AXI_HP3_AWLOCK,
input [2:0] S_AXI_HP3_AWSIZE,
input [2:0] S_AXI_HP3_ARPROT,
input [2:0] S_AXI_HP3_AWPROT,
input [31:0] S_AXI_HP3_ARADDR,
input [31:0] S_AXI_HP3_AWADDR,
input [3:0] S_AXI_HP3_ARCACHE,
input [3:0] S_AXI_HP3_ARLEN,
input [3:0] S_AXI_HP3_ARQOS,
input [3:0] S_AXI_HP3_AWCACHE,
input [3:0] S_AXI_HP3_AWLEN,
input [3:0] S_AXI_HP3_AWQOS,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,
//FIO ========================================
//IRQ
//output [28:0] IRQ_P2F,
output IRQ_P2F_DMAC_ABORT ,
output IRQ_P2F_DMAC0,
output IRQ_P2F_DMAC1,
output IRQ_P2F_DMAC2,
output IRQ_P2F_DMAC3,
output IRQ_P2F_DMAC4,
output IRQ_P2F_DMAC5,
output IRQ_P2F_DMAC6,
output IRQ_P2F_DMAC7,
output IRQ_P2F_SMC,
output IRQ_P2F_QSPI,
output IRQ_P2F_CTI,
output IRQ_P2F_GPIO,
output IRQ_P2F_USB0,
output IRQ_P2F_ENET0,
output IRQ_P2F_ENET_WAKE0,
output IRQ_P2F_SDIO0,
output IRQ_P2F_I2C0,
output IRQ_P2F_SPI0,
output IRQ_P2F_UART0,
output IRQ_P2F_CAN0,
output IRQ_P2F_USB1,
output IRQ_P2F_ENET1,
output IRQ_P2F_ENET_WAKE1,
output IRQ_P2F_SDIO1,
output IRQ_P2F_I2C1,
output IRQ_P2F_SPI1,
output IRQ_P2F_UART1,
output IRQ_P2F_CAN1,
input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
input Core0_nFIQ,
input Core0_nIRQ,
input Core1_nFIQ,
input Core1_nIRQ,
//DMA
output [1:0] DMA0_DATYPE,
output DMA0_DAVALID,
output DMA0_DRREADY,
output DMA0_RSTN,
output [1:0] DMA1_DATYPE,
output DMA1_DAVALID,
output DMA1_DRREADY,
output DMA1_RSTN,
output [1:0] DMA2_DATYPE,
output DMA2_DAVALID,
output DMA2_DRREADY,
output DMA2_RSTN,
output [1:0] DMA3_DATYPE,
output DMA3_DAVALID,
output DMA3_DRREADY,
output DMA3_RSTN,
input DMA0_ACLK,
input DMA0_DAREADY,
input DMA0_DRLAST,
input DMA0_DRVALID,
input DMA1_ACLK,
input DMA1_DAREADY,
input DMA1_DRLAST,
input DMA1_DRVALID,
input DMA2_ACLK,
input DMA2_DAREADY,
input DMA2_DRLAST,
input DMA2_DRVALID,
input DMA3_ACLK,
input DMA3_DAREADY,
input DMA3_DRLAST,
input DMA3_DRVALID,
input [1:0] DMA0_DRTYPE,
input [1:0] DMA1_DRTYPE,
input [1:0] DMA2_DRTYPE,
input [1:0] DMA3_DRTYPE,
//FCLK
output FCLK_CLK3,
output FCLK_CLK2,
output FCLK_CLK1,
output FCLK_CLK0,
input FCLK_CLKTRIG3_N,
input FCLK_CLKTRIG2_N,
input FCLK_CLKTRIG1_N,
input FCLK_CLKTRIG0_N,
output FCLK_RESET3_N,
output FCLK_RESET2_N,
output FCLK_RESET1_N,
output FCLK_RESET0_N,
//FTMD
input [31:0] FTMD_TRACEIN_DATA,
input FTMD_TRACEIN_VALID,
input FTMD_TRACEIN_CLK,
input [3:0] FTMD_TRACEIN_ATID,
//FTMT
input FTMT_F2P_TRIG_0,
output FTMT_F2P_TRIGACK_0,
input FTMT_F2P_TRIG_1,
output FTMT_F2P_TRIGACK_1,
input FTMT_F2P_TRIG_2,
output FTMT_F2P_TRIGACK_2,
input FTMT_F2P_TRIG_3,
output FTMT_F2P_TRIGACK_3,
input [31:0] FTMT_F2P_DEBUG,
input FTMT_P2F_TRIGACK_0,
output FTMT_P2F_TRIG_0,
input FTMT_P2F_TRIGACK_1,
output FTMT_P2F_TRIG_1,
input FTMT_P2F_TRIGACK_2,
output FTMT_P2F_TRIG_2,
input FTMT_P2F_TRIGACK_3,
output FTMT_P2F_TRIG_3,
output [31:0] FTMT_P2F_DEBUG,
//FIDLE
input FPGA_IDLE_N,
//EVENT
output EVENT_EVENTO,
output [1:0] EVENT_STANDBYWFE,
output [1:0] EVENT_STANDBYWFI,
input EVENT_EVENTI,
//DARB
input [3:0] DDR_ARB,
inout [C_MIO_PRIMITIVE - 1:0] MIO,
//DDR
inout DDR_CAS_n, // CASB
inout DDR_CKE, // CKE
inout DDR_Clk_n, // CKN
inout DDR_Clk, // CKP'b'
inout DDR_CS_n, // CSB
inout DDR_DRSTB, // DDR_DRSTB
inout DDR_ODT, // ODT
inout DDR_RAS_n, // RASB
inout DDR_WEB,
inout [2:0] DDR_BankAddr, // BA
inout [14:0] DDR_Addr, // A
inout DDR_VRN,
inout DDR_VRP,
inout [C_DM_WIDTH - 1:0] DDR_DM, // DM
inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ
inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN
inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP
inout PS_SRSTB, // SRSTB
inout PS_CLK, // CLK
inout PS_PORB // PORB
);
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
wire ENET0_GMII_TX_EN_i;
wire ENET0_GMII_TX_ER_i;
reg ENET0_GMII_COL_i;
reg ENET0_GMII_CRS_i;
reg ENET0_GMII_RX_DV_i;
reg ENET0_GMII_RX_ER_i;
reg [7:0] ENET0_GMII_RXD_i;
wire [7:0] ENET0_GMII_TXD_i;
wire ENET1_GMII_TX_EN_i;
wire ENET1_GMII_TX_ER_i;
reg ENET1_GMII_COL_i;
reg ENET1_GMII_CRS_i;
reg ENET1_GMII_RX_DV_i;
reg ENET1_GMII_RX_ER_i;
reg [7:0] ENET1_GMII_RXD_i;
wire [7:0] ENET1_GMII_TXD_i;
reg [31:0] FTMD_TRACEIN_DATA_notracebuf;
reg FTMD_TRACEIN_VALID_notracebuf;
reg [3:0] FTMD_TRACEIN_ATID_notracebuf;
wire [31:0] FTMD_TRACEIN_DATA_i;
wire FTMD_TRACEIN_VALID_i;
wire [3:0] FTMD_TRACEIN_ATID_i;
wire [31:0] FTMD_TRACEIN_DATA_tracebuf;
wire FTMD_TRACEIN_VALID_tracebuf;
wire [3:0] FTMD_TRACEIN_ATID_tracebuf;
wire [5:0] S_AXI_GP0_BID_out;
wire [5:0] S_AXI_GP0_RID_out;
wire [5:0] S_AXI_GP0_ARID_in;
wire [5:0] S_AXI_GP0_AWID_in;
wire [5:0] S_AXI_GP0_WID_in;
wire [5:0] S_AXI_GP1_BID_out;
wire [5:0] S_AXI_GP1_RID_out;
wire [5:0] S_AXI_GP1_ARID_in;
wire [5:0] S_AXI_GP1_AWID_in;
wire [5:0] S_AXI_GP1_WID_in;
wire [5:0] S_AXI_HP0_BID_out;
wire [5:0] S_AXI_HP0_RID_out;
wire [5:0] S_AXI_HP0_ARID_in;
wire [5:0] S_AXI_HP0_AWID_in;
wire [5:0] S_AXI_HP0_WID_in;
wire [5:0] S_AXI_HP1_BID_out;
wire [5:0] S_AXI_HP1_RID_out;
wire [5:0] S_AXI_HP1_ARID_in;
wire [5:0] S_AXI_HP1_AWID_in;
wire [5:0] S_AXI_HP1_WID_in;
wire [5:0] S_AXI_HP2_BID_out;
wire [5:0] S_AXI_HP2_RID_out;
wire [5:0] S_AXI_HP2_ARID_in;
wire [5:0] S_AXI_HP2_AWID_in;
wire [5:0] S_AXI_HP2_WID_in;
wire [5:0] S_AXI_HP3_BID_out;
wire [5:0] S_AXI_HP3_RID_out;
wire [5:0] S_AXI_HP3_ARID_in;
wire [5:0] S_AXI_HP3_AWID_in;
wire [5:0] S_AXI_HP3_WID_in;
wire [2:0] S_AXI_ACP_BID_out;
wire [2:0] S_AXI_ACP_RID_out;
wire [2:0] S_AXI_ACP_ARID_in;
wire [2:0] S_AXI_ACP_AWID_in;
wire [2:0] S_AXI_ACP_WID_in;
wire [63:0] S_AXI_HP0_WDATA_in;
wire [7:0] S_AXI_HP0_WSTRB_in;
wire [63:0] S_AXI_HP0_RDATA_out;
wire [63:0] S_AXI_HP1_WDATA_in;
wire [7:0] S_AXI_HP1_WSTRB_in;
wire [63:0] S_AXI_HP1_RDATA_out;
wire [63:0] S_AXI_HP2_WDATA_in;
wire [7:0] S_AXI_HP2_WSTRB_in;
wire [63:0] S_AXI_HP2_RDATA_out;
wire [63:0] S_AXI_HP3_WDATA_in;
wire [7:0] S_AXI_HP3_WSTRB_in;
wire [63:0] S_AXI_HP3_RDATA_out;
wire [1:0] M_AXI_GP0_ARSIZE_i;
wire [1:0] M_AXI_GP0_AWSIZE_i;
wire [1:0] M_AXI_GP1_ARSIZE_i;
wire [1:0] M_AXI_GP1_AWSIZE_i;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W;
wire SAXIACPARREADY_W;
wire SAXIACPAWREADY_W;
wire SAXIACPBVALID_W;
wire SAXIACPRLAST_W;
wire SAXIACPRVALID_W;
wire SAXIACPWREADY_W;
wire [1:0] SAXIACPBRESP_W;
wire [1:0] SAXIACPRRESP_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
wire [63:0] SAXIACPRDATA_W;
wire S_AXI_ATC_ARVALID;
wire S_AXI_ATC_AWVALID;
wire S_AXI_ATC_BREADY;
wire S_AXI_ATC_RREADY;
wire S_AXI_ATC_WLAST;
wire S_AXI_ATC_WVALID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
wire [2:0] S_AXI_ATC_ARPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
wire [2:0] S_AXI_ATC_AWPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
wire [31:0] S_AXI_ATC_ARADDR;
wire [31:0] S_AXI_ATC_AWADDR;
wire [3:0] S_AXI_ATC_ARCACHE;
wire [3:0] S_AXI_ATC_ARLEN;
wire [3:0] S_AXI_ATC_ARQOS;
wire [3:0] S_AXI_ATC_AWCACHE;
wire [3:0] S_AXI_ATC_AWLEN;
wire [3:0] S_AXI_ATC_AWQOS;
wire [1:0] S_AXI_ATC_ARBURST;
wire [1:0] S_AXI_ATC_ARLOCK;
wire [2:0] S_AXI_ATC_ARSIZE;
wire [1:0] S_AXI_ATC_AWBURST;
wire [1:0] S_AXI_ATC_AWLOCK;
wire [2:0] S_AXI_ATC_AWSIZE;
wire [4:0] S_AXI_ATC_ARUSER;
wire [4:0] S_AXI_ATC_AWUSER;
wire [63:0] S_AXI_ATC_WDATA;
wire [7:0] S_AXI_ATC_WSTRB;
wire SAXIACPARVALID_W;
wire SAXIACPAWVALID_W;
wire SAXIACPBREADY_W;
wire SAXIACPRREADY_W;
wire SAXIACPWLAST_W;
wire SAXIACPWVALID_W;
wire [2:0] SAXIACPARPROT_W;
wire [2:0] SAXIACPAWPROT_W;
wire [31:0] SAXIACPARADDR_W;
wire [31:0] SAXIACPAWADDR_W;
wire [3:0] SAXIACPARCACHE_W;
wire [3:0] SAXIACPARLEN_W;
wire [3:0] SAXIACPARQOS_W;
wire [3:0] SAXIACPAWCACHE_W;
wire [3:0] SAXIACPAWLEN_W;
wire [3:0] SAXIACPAWQOS_W;
wire [1:0] SAXIACPARBURST_W;
wire [1:0] SAXIACPARLOCK_W;
wire [2:0] SAXIACPARSIZE_W;
wire [1:0] SAXIACPAWBURST_W;
wire [1:0] SAXIACPAWLOCK_W;
wire [2:0] SAXIACPAWSIZE_W;
wire [4:0] SAXIACPARUSER_W;
wire [4:0] SAXIACPAWUSER_W;
wire [63:0] SAXIACPWDATA_W;
wire [7:0] SAXIACPWSTRB_W;
// AxUSER signal update
wire [4:0] param_aruser;
wire [4:0] param_awuser;
// Added to address CR 651751
wire [3:0] fclk_clktrig_gnd = 4\'h0;
wire [19:0] irq_f2p_i;
wire [15:0] irq_f2p_null = 16\'h0000;
// EMIO I2C0
wire I2C0_SDA_T_n;
wire I2C0_SCL_T_n;
// EMIO I2C1
wire I2C1_SDA_T_n;
wire I2C1_SCL_T_n;
// EMIO SPI0
wire SPI0_SCLK_T_n;
wire SPI0_MOSI_T_n;
wire SPI0_MISO_T_n;
wire SPI0_SS_T_n;
// EMIO SPI1
wire SPI1_SCLK_T_n;
wire SPI1_MOSI_T_n;
wire SPI1_MISO_T_n;
wire SPI1_SS_T_n;
// EMIO GEM0
wire ENET0_MDIO_T_n;
// EMIO GEM1
wire ENET1_MDIO_T_n;
// EMIO GPIO
wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n;
wire [63:0] gpio_out_t_n;
wire [63:0] gpio_out;
wire [63:0] gpio_in63_0;
//For Clock buffering
wire [3:0] FCLK_CLK_unbuffered;
wire [3:0] FCLK_CLK_buffered;
// EMIO PJTAG
wire PJTAG_TDO_O;
wire PJTAG_TDO_T;
wire PJTAG_TDO_T_n;
// EMIO SDIO0
wire SDIO0_CMD_T_n;
wire [3:0] SDIO0_DATA_T_n;
// EMIO SDIO1
wire SDIO1_CMD_T_n;
wire [3:0] SDIO1_DATA_T_n;
// buffered IO
wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO;
wire buffered_DDR_WEB;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_Clk_n;
wire buffered_DDR_Clk;
wire buffered_DDR_CS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire [2:0] buffered_DDR_BankAddr;
wire [14:0] buffered_DDR_Addr;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire [C_DM_WIDTH - 1:0] buffered_DDR_DM;
wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ;
wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n;
wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS;
wire buffered_PS_SRSTB;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire [31:0] TRACE_DATA_i;
wire TRACE_CTL_i;
reg TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
reg [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
// fixed CR #665394
integer j;
generate
if (C_EN_EMIO_TRACE == 1) begin
always @(posedge TRACE_CLK)
begin
\t TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i;
\t TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0];
\t for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
\t\tTRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j];
\t\tTRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j];
end
\t TRACE_CLK_OUT <= ~TRACE_CLK_OUT;
\tend
end\t\t
endgenerate
assign TRACE_CTL = TRACE_CTL_PIPE[0];
assign TRACE_DATA = TRACE_DATA_PIPE[0];
//irq_p2f
// Updated IRQ_F2P logic to address CR 641523
generate
if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
end else begin : irq_f2p_select
\tif (C_IRQ_F2P_MODE == "DIRECT") begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
\t\t\t\tirq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0],
\t\t\t\tIRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]};
\tend else begin
\tassign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
\t\t\t\tIRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
\t\t\t\tirq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
\tend
end
endgenerate
assign M_AXI_GP0_ARSIZE[2:0] = {1\'b0, M_AXI_GP0_ARSIZE_i[1:0]};
assign M_AXI_GP0_AWSIZE[2:0] = {1\'b0, M_AXI_GP0_AWSIZE_i[1:0]};
assign M_AXI_GP1_ARSIZE[2:0] = {1\'b0, M_AXI_GP1_ARSIZE_i[1:0]};
assign M_AXI_GP1_AWSIZE[2:0] = {1\'b0, M_AXI_GP1_AWSIZE_i[1:0]};
// Compress Function
// Modified as per CR 631955
//function [11:0] uncompress_id;
// input [5:0] id;
// begin
// case (id[5:0])
// // dmac0
// 6\'d1 : uncompress_id = 12\'b010000_1000_00 ;
// 6\'d2 : uncompress_id = 12\'b010000_0000_00 ;
// 6\'d3 : uncompress_id = 12\'b010000_0001_00 ;
// 6\'d4 : uncompress_id = 12\'b010000_0010_00 ;
// 6\'d5 : uncompress_id = 12\'b010000_0011_00 ;
// 6\'d6 : uncompress_id = 12\'b010000_0100_00 ;
// 6\'d7 : uncompress_id = 12\'b010000_0101_00 ;
// 6\'d8 : uncompress_id = 12\'b010000_0110_00 ;
// 6\'d9 : uncompress_id = 12\'b010000_0111_00 ;
// // ioum
// 6\'d10 : uncompress_id = 12\'b0100000_000_01 ;
// 6\'d11 : uncompress_id = 12\'b0100000_001_01 ;
// 6\'d12 : uncompress_id = 12\'b0100000_010_01 ;
// 6\'d13 : uncompress_id = 12\'b0100000_011_01 ;
// 6\'d14 : uncompress_id = 12\'b0100000_100_01 ;
// 6\'d15 : uncompress_id = 12\'b0100000_101_01 ;
// // devci
// 6\'d16 : uncompress_id = 12\'b1000_0000_0000 ;
// // dap
// 6\'d17 : uncompress_id = 12\'b1000_0000_0001 ;
// // l2m1 (CPU000)
// 6\'d18 : uncompress_id = 12\'b11_000_000_00_00 ;
// 6\'d19 : uncompress_id = 12\'b11_010_000_00_00 ;
// 6\'d20 : uncompress_id = 12\'b11_011_000_00_00 ;
// 6\'d21 : uncompress_id = 12\'b11_100_000_00_00 ;
// 6\'d22 : uncompress_id = 12\'b11_101_000_00_00 ;
// 6\'d23 : uncompress_id = 12\'b11_110_000_00_00 ;
// 6\'d24 : uncompress_id = 12\'b11_111_000_00_00 ;
// // l2m1 (CPU001)
// 6\'d25 : uncompress_id = 12\'b11_000_001_00_00 ;
// 6\'d26 : uncompress_id = 12\'b11_010_001_00_00 ;
// 6\'d27 : uncompress_id = 12\'b11_011_001_00_00 ;
// 6\'d28 : uncompress_id = 12\'b11_100_001_00_00 ;
// 6\'d29 : uncompress_id = 12\'b11_101_001_00_00 ;
// 6\'d30 : uncompress_id = 12\'b11_110_001_00_00 ;
// 6\'d31 : uncompress_id = 12\'b11_111_001_00_00 ;
// // l2m1 (L2CC)
// 6\'d32 : uncompress_id = 12\'b11_000_00101_00 ;
// 6\'d33 : uncompress_id = 12\'b11_000_01001_00 ;
// 6\'d34 : uncompress_id = 12\'b11_000_01101_00 ;
// 6\'d35 : uncompress_id = 12\'b11_000_10011_00 ;
// 6\'d36 : uncompress_id = 12\'b11_000_10111_00 ;
// 6\'d37 : uncompress_id = 12\'b11_000_11011_00 ;
// 6\'d38 : uncompress_id = 12\'b11_000_11111_00 ;
// 6\'d39 : uncompress_id = 12\'b11_000_00011_00 ;
// 6\'d40 : uncompress_id = 12\'b11_000_00111_00 ;
// 6\'d41 : uncompress_id = 12\'b11_000_01011_00 ;
// 6\'d42 : uncompress_id = 12\'b11_000_01111_00 ;
// 6\'d43 : uncompress_id = 12\'b11_000_00001_00 ;
// // l2m1 (ACP)
// 6\'d44 : uncompress_id = 12\'b11_000_10000_00 ;
// 6\'d45 : uncompress_id = 12\'b11_001_10000_00 ;
// 6\'d46 : uncompress_id = 12\'b11_010_10000_00 ;
// 6\'d47 : uncompress_id = 12\'b11_011_10000_00 ;
// 6\'d48 : uncompress_id = 12\'b11_100_10000_00 ;
// 6\'d49 : uncompress_id = 12\'b11_101_10000_00 ;
// 6\'d50 : uncompress_id = 12\'b11_110_10000_00 ;
// 6\'d51 : uncompress_id = 12\'b11_111_10000_00 ;
// default : uncompress_id = ~0;
// endcase
// end
//endfunction
//
//function [5:0] compress_id;
// input [11:0] id;
// begin
// case (id[11:0])
// // dmac0
// 12\'b010000_1000_00 : compress_id = \'d1 ;
// 12\'b010000_0000_00 : compress_id = \'d2 ;
// 12\'b010000_0001_00 : compress_id = \'d3 ;
// 12\'b010000_0010_00 : compress_id = \'d4 ;
// 12\'b010000_0011_00 : compress_id = \'d5 ;
// 12\'b010000_0100_00 : compress_id = \'d6 ;
// 12\'b010000_0101_00 : compress_id = \'d7 ;
// 12\'b010000_0110_00 : compress_id = \'d8 ;
// 12\'b010000_0111_00 : compress_id = \'d9 ;
// // ioum
// 12\'b0100000_000_01 : compress_id = \'d10 ;
// 12\'b0100000_001_01 : compress_id = \'d11 ;
// 12\'b0100000_010_01 : compress_id = \'d12 ;
// 12\'b0100000_011_01 : compress_id = \'d13 ;
// 12\'b0100000_100_01 : compress_id = \'d14 ;
// 12\'b0100000_101_01 : compress_id = \'d15 ;
// // devci
// 12\'b1000_0000_0000 : compress_id = \'d16 ;
// // dap
// 12\'b1000_0000_0001 : compress_id = \'d17 ;
// // l2m1 (CPU000)
// 12\'b11_000_000_00_00 : compress_id = \'d18 ;
// 12\'b11_010_000_00_00 : compress_id = \'d19 ;
// 12\'b11_011_000_00_00 : compress_id = \'d20 ;
// 12\'b11_100_000_00_00 : compress_id = \'d21 ;
// 12\'b11_101_000_00_00 : compress_id = \'d22 ;
// 12\'b11_110_000_00_00 : compress_id = \'d23 ;
// 12\'b11_111_000_00_00 : compress_id = \'d24 ;
// // l2m1 (CPU001)
// 12\'b11_000_001_00_00 : compress_id = \'d25 ;
// 12\'b11_010_001_00_00 : compress_id = \'d26 ;
// 12\'b11_011_001_00_00 : compress_id = \'d27 ;
// 12\'b11_100_001_00_00 : compress_id = \'d28 ;
// 12\'b11_101_001_00_00 : compress_id = \'d29 ;
// 12\'b11_110_001_00_00 : compress_id = \'d30 ;
// 12\'b11_111_001_00_00 : compress_id = \'d31 ;
// // l2m1 (L2CC)
// 12\'b11_000_00101_00 : compress_id = \'d32 ;
// 12\'b11_000_01001_00 : compress_id = \'d33 ;
// 12\'b11_000_01101_00 : compress_id = \'d34 ;
// 12\'b11_000_10011_00 : compress_id = \'d35 ;
// 12\'b11_000_10111_00 : compress_id = \'d36 ;
// 12\'b11_000_11011_00 : compress_id = \'d37 ;
// 12\'b11_000_11111_00 : compress_id = \'d38 ;
// 12\'b11_000_00011_00 : compress_id = \'d39 ;
// 12\'b11_000_00111_00 : compress_id = \'d40 ;
// 12\'b11_000_01011_00 : compress_id = \'d41 ;
// 12\'b11_000_01111_00 : compress_id = \'d42 ;
// 12\'b11_000_00001_00 : compress_id = \'d43 ;
// // l2m1 (ACP)
// 12\'b11_000_10000_00 : compress_id = \'d44 ;
// 12\'b11_001_10000_00 : compress_id = \'d45 ;
// 12\'b11_010_10000_00 : compress_id = \'d46 ;
// 12\'b11_011_10000_00 : compress_id = \'d47 ;
// 12\'b11_100_10000_00 : compress_id = \'d48 ;
// 12\'b11_101_10000_00 : compress_id = \'d49 ;
// 12\'b11_110_10000_00 : compress_id = \'d50 ;
// 12\'b11_111_10000_00 : compress_id = \'d51 ;
// default: compress_id = ~0;
// endcase
// end
//endfunction
// Modified as per CR 648393
\tfunction [5:0] compress_id;
\t\tinput [11:0] id;
\t\t\tbegin
\t\t\t\tcompress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]);
\t\t\t\tcompress_id[1] = id[8] | id[5] | (~id[11] & id[3]);
\t\t\t\tcompress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]);
\t\t\t\tcompress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]);
\t\t\t\tcompress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]);
\t\t\t\tcompress_id[5] = id[11] & id[10] & ~id[3];
\t\t\tend
\tendfunction
\tfunction [11:0] uncompress_id;
\t\tinput [5:0] id;
\t\t\tbegin
\t\t\t\tcase (id[5:0])
\t\t\t\t\t// dmac0
\t\t\t\t\t6\'b000_010 : uncompress_id = 12\'b010000_1000_00 ;
\t\t\t\t\t6\'b001_000 : uncompress_id = 12\'b010000_0000_00 ;
\t\t\t\t\t6\'b001_001 : uncompress_id = 12\'b010000_0001_00 ;
\t\t\t\t\t6\'b001_010 : uncompress_id = 12\'b010000_0010_00 ;
\t\t\t\t\t6\'b001_011 : uncompress_id = 12\'b010000_0011_00 ;
\t\t\t\t\t6\'b001_100 : uncompress_id = 12\'b010000_0100_00 ;
\t\t\t\t\t6\'b001_101 : uncompress_id = 12\'b010000_0101_00 ;
\t\t\t\t\t6\'b001_110 : uncompress_id = 12\'b010000_0110_00 ;
\t\t\t\t\t6\'b001_111 : uncompress_id = 12\'b010000_0111_00 ;
\t\t\t\t\t// ioum
\t\t\t\t\t6\'b010_000 : uncompress_id = 12\'b0100000_000_01 ;
\t\t\t\t\t6\'b010_001 : uncompress_id = 12\'b0100000_001_01 ;
\t\t\t\t\t6\'b010_010 : uncompress_id = 12\'b0100000_010_01 ;
\t\t\t\t\t6\'b010_011 : uncompress_id = 12\'b0100000_011_01 ;
\t\t\t\t\t6\'b010_100 : uncompress_id = 12\'b0100000_100_01 ;
\t\t\t\t\t6\'b010_101 : uncompress_id = 12\'b0100000_101_01 ;
\t\t\t\t\t// devci
\t\t\t\t\t6\'b000_000 : uncompress_id = 12\'b1000_0000_0000 ;
\t\t\t\t\t// dap
\t\t\t\t\t6\'b000_001 : uncompress_id = 12\'b1000_0000_0001 ;
\t\t\t\t\t// l2m1 (CPU000)
\t\t\t\t\t6\'b110_000 : uncompress_id = 12\'b11_000_000_00_00 ;
\t\t\t\t\t6\'b110_010 : uncompress_id = 12\'b11_010_000_00_00 ;
\t\t\t\t\t6\'b110_011 : uncompress_id = 12\'b11_011_000_00_00 ;
\t\t\t\t\t6\'b110_100 : uncompress_id = 12\'b11_100_000_00_00 ;
\t\t\t\t\t6\'b110_101 : uncompress_id = 12\'b11_101_000_00_00 ;
\t\t\t\t\t6\'b110_110 : uncompress_id = 12\'b11_110_000_00_00 ;
\t\t\t\t\t6\'b110_111 : uncompress_id = 12\'b11_111_000_00_00 ;
\t\t\t\t\t// l2m1 (CPU001)
\t\t\t\t\t6\'b111_000 : uncompress_id = 12\'b11_000_001_00_00 ;
\t\t\t\t\t6\'b111_010 : uncompress_id = 12\'b11_010_001_00_00 ;
\t\t\t\t\t6\'b111_011 : uncompress_id = 12\'b11_011_001_00_00 ;
\t\t\t\t\t6\'b111_100 : uncompress_id = 12\'b11_100_001_00_00 ;
\t\t\t\t\t6\'b111_101 : uncompress_id = 12\'b11_101_001_00_00 ;
\t\t\t\t\t6\'b111_110 : uncompress_id = 12\'b11_110_001_00_00 ;
\t\t\t\t\t6\'b111_111 : uncompress_id = 12\'b11_111_001_00_00 ;
\t\t\t\t\t// l2m1 (L2CC)
\t\t\t\t\t6\'b101_001 : uncompress_id = 12\'b11_000_00101_00 ;
\t\t\t\t\t6\'b101_010 : uncompress_id = 12\'b11_000_01001_00 ;
\t\t\t\t\t6\'b101_011 : uncompress_id = 12\'b11_000_01101_00 ;
\t\t\t\t\t6\'b011_100 : uncompress_id = 12\'b11_000_10011_00 ;
\t\t\t\t\t6\'b011_101 : uncompress_id = 12\'b11_000_10111_00 ;
\t\t\t\t\t6\'b011_110 : uncompress_id = 12\'b11_000_11011_00 ;
\t\t\t\t\t6\'b011_111 : uncompress_id = 12\'b11_000_11111_00 ;
\t\t\t\t\t6\'b011_000 : uncompress_id = 12\'b11_000_00011_00 ;
\t\t\t\t\t6\'b011_001 : uncompress_id = 12\'b11_000_00111_00 ;
\t\t\t\t\t6\'b011_010 : uncompress_id = 12\'b11_000_01011_00 ;
\t\t\t\t\t6\'b011_011 : uncompress_id = 12\'b11_000_01111_00 ;
\t\t\t\t\t6\'b101_000 : uncompress_id = 12\'b11_000_00001_00 ;
\t\t\t\t\t// l2m1 (ACP)
\t\t\t\t\t6\'b100_000 : uncompress_id = 12\'b11_000_10000_00 ;
\t\t\t\t\t6\'b100_001 : uncompress_id = 12\'b11_001_10000_00 ;
\t\t\t\t\t6\'b100_010 : uncompress_id = 12\'b11_010_10000_00 ;
\t\t\t\t\t6\'b100_011 : uncompress_id = 12\'b11_011_10000_00 ;
\t\t\t\t\t6\'b100_100 : uncompress_id = 12\'b11_100_10000_00 ;
\t\t\t\t\t6\'b100_101 : uncompress_id = 12\'b11_101_10000_00 ;
\t\t\t\t\t6\'b100_110 : uncompress_id = 12\'b11_110_10000_00 ;
\t\t\t\t\t6\'b100_111 : uncompress_id = 12\'b11_111_10000_00 ;
\t\t\t\t\tdefault : uncompress_id = 12\'hx ;
\t\t\t\tendcase
\t\t\tend
\tendfunction
// Static Remap logic Enablement and Disablement for C_M_AXI0 port
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
// Static Remap logic Enablement and Disablement for C_M_AXI1 port
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
//// Compress_id and uncompress_id has been removed to address CR 642527
//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL;
// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL;
// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL;
// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID;
// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID;
//
// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL;
// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL;
// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL;
// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID;
// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID;
\t\t\t\t\t\t
// Pipeline Stage for ENET0
\t
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_TX_CLK)
begin
ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= ENET0_GMII_COL;
ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
end
end\t\t
endgenerate
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_RX_CLK)
begin
ENET0_GMII_RXD_i <= ENET0_GMII_RXD;
ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV;
ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER;
end
end\t\t
endgenerate
// Pipeline Stage for ENET1
\t
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_TX_CLK)
begin
ENET1_GMII_TXD <= ENET1_GMII_TXD_i;
ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i;
ENET1_GMII_COL_i <= ENET1_GMII_COL;
ENET1_GMII_CRS_i <= ENET1_GMII_CRS;
end
end\t\t
endgenerate
generate\t
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_RX_CLK)
begin
ENET1_GMII_RXD_i <= ENET1_GMII_RXD;
ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV;
ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER;
end
end\t\t
endgenerate
// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
generate
if (C_EN_EMIO_TRACE == 1) begin
if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
// Pipeline Stage for Traceport ATID
always @(posedge FTMD_TRACEIN_CLK)
begin
\tFTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA;
FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID;
\tFTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID;
end
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf;
end else begin : gen_trace_buffer
processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
.USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
.C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
)
trace_buffer_i (
.TRACE_CLK(FTMD_TRACEIN_CLK),
.RST(~FCLK_RESET0_N),
.TRACE_VALID_IN(FTMD_TRACEIN_VALID),
.TRACE_DATA_IN(FTMD_TRACEIN_DATA),
.TRACE_ATID_IN(FTMD_TRACEIN_ATID),
.TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf),
.TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf),
.TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
);
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf;
end
end
endgenerate
// ID Width Control on AXI Slave ports
// S_AXI_GP0
function [5:0] id_in_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_in_gp0 = {5\'b0, axi_id_gp0_in};
2: id_in_gp0 = {4\'b0, axi_id_gp0_in};
3: id_in_gp0 = {3\'b0, axi_id_gp0_in};
4: id_in_gp0 = {2\'b0, axi_id_gp0_in};
5: id_in_gp0 = {1\'b0, axi_id_gp0_in};
6: id_in_gp0 = axi_id_gp0_in;
default : id_in_gp0 = axi_id_gp0_in;
endcase
end
endfunction
assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID);
function [5:0] id_out_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_out_gp0 = axi_id_gp0_out[0];
2: id_out_gp0 = axi_id_gp0_out[1:0];
3: id_out_gp0 = axi_id_gp0_out[2:0];
4: id_out_gp0 = axi_id_gp0_out[3:0];
5: id_out_gp0 = axi_id_gp0_out[4:0];
6: id_out_gp0 = axi_id_gp0_out;
default : id_out_gp0 = axi_id_gp0_out;
endcase
end
endfunction
assign S_AXI_GP0_BID = id_out_gp0(S_AXI_GP0_BID_out);
assign S_AXI_GP0_RID = id_out_gp0(S_AXI_GP0_RID_out);
// S_AXI_GP1
function [5:0] id_in_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_in_gp1 = {5\'b0, axi_id_gp1_in};
2: id_in_gp1 = {4\'b0, axi_id_gp1_in};
3: id_in_gp1 = {3\'b0, axi_id_gp1_in};
4: id_in_gp1 = {2\'b0, axi_id_gp1_in};
5: id_in_gp1 = {1\'b0, axi_id_gp1_in};
6: id_in_gp1 = axi_id_gp1_in;
default : id_in_gp1 = axi_id_gp1_in;
endcase
end
endfunction
assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID);
function [5:0] id_out_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_out_gp1 = axi_id_gp1_out[0];
2: id_out_gp1 = axi_id_gp1_out[1:0];
3: id_out_gp1 = axi_id_gp1_out[2:0];
4: id_out_gp1 = axi_id_gp1_out[3:0];
5: id_out_gp1 = axi_id_gp1_out[4:0];
6: id_out_gp1 = axi_id_gp1_out;
default : id_out_gp1 = axi_id_gp1_out;
endcase
end
endfunction
assign S_AXI_GP1_BID = id_out_gp1(S_AXI_GP1_BID_out);
assign S_AXI_GP1_RID = id_out_gp1(S_AXI_GP1_RID_out);
// S_AXI_HP0
function [5:0] id_in_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_in_hp0 = {5\'b0, axi_id_hp0_in};
2: id_in_hp0 = {4\'b0, axi_id_hp0_in};
3: id_in_hp0 = {3\'b0, axi_id_hp0_in};
4: id_in_hp0 = {2\'b0, axi_id_hp0_in};
5: id_in_hp0 = {1\'b0, axi_id_hp0_in};
6: id_in_hp0 = axi_id_hp0_in;
default : id_in_hp0 = axi_id_hp0_in;
endcase
end
endfunction
assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID);
function [5:0] id_out_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_out_hp0 = axi_id_hp0_out[0];
2: id_out_hp0 = axi_id_hp0_out[1:0];
3: id_out_hp0 = axi_id_hp0_out[2:0];
4: id_out_hp0 = axi_id_hp0_out[3:0];
5: id_out_hp0 = axi_id_hp0_out[4:0];
6: id_out_hp0 = axi_id_hp0_out;
default : id_out_hp0 = axi_id_hp0_out;
endcase
end
endfunction
assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out);
assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out);
assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32\'b0,S_AXI_HP0_WDATA};
assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4\'b0,S_AXI_HP0_WSTRB};
assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
// S_AXI_HP1
function [5:0] id_in_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_in_hp1 = {5\'b0, axi_id_hp1_in};
2: id_in_hp1 = {4\'b0, axi_id_hp1_in};
3: id_in_hp1 = {3\'b0, axi_id_hp1_in};
4: id_in_hp1 = {2\'b0, axi_id_hp1_in};
5: id_in_hp1 = {1\'b0, axi_id_hp1_in};
6: id_in_hp1 = axi_id_hp1_in;
default : id_in_hp1 = axi_id_hp1_in;
endcase
end
endfunction
assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID);
function [5:0] id_out_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_out_hp1 = axi_id_hp1_out[0];
2: id_out_hp1 = axi_id_hp1_out[1:0];
3: id_out_hp1 = axi_id_hp1_out[2:0];
4: id_out_hp1 = axi_id_hp1_out[3:0];
5: id_out_hp1 = axi_id_hp1_out[4:0];
6: id_out_hp1 = axi_id_hp1_out;
default : id_out_hp1 = axi_id_hp1_out;
endcase
end
endfunction
assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out);
assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out);
assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32\'b0,S_AXI_HP1_WDATA};
assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4\'b0,S_AXI_HP1_WSTRB};
assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
// S_AXI_HP2
function [5:0] id_in_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_in_hp2 = {5\'b0, axi_id_hp2_in};
2: id_in_hp2 = {4\'b0, axi_id_hp2_in};
3: id_in_hp2 = {3\'b0, axi_id_hp2_in};
4: id_in_hp2 = {2\'b0, axi_id_hp2_in};
5: id_in_hp2 = {1\'b0, axi_id_hp2_in};
6: id_in_hp2 = axi_id_hp2_in;
default : id_in_hp2 = axi_id_hp2_in;
endcase
end
endfunction
assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID);
function [5:0] id_out_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_out_hp2 = axi_id_hp2_out[0];
2: id_out_hp2 = axi_id_hp2_out[1:0];
3: id_out_hp2 = axi_id_hp2_out[2:0];
4: id_out_hp2 = axi_id_hp2_out[3:0];
5: id_out_hp2 = axi_id_hp2_out[4:0];
6: id_out_hp2 = axi_id_hp2_out;
default : id_out_hp2 = axi_id_hp2_out;
endcase
end
endfunction
assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out);
assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out);
assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32\'b0,S_AXI_HP2_WDATA};
assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4\'b0,S_AXI_HP2_WSTRB};
assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
// S_AXI_HP3
function [5:0] id_in_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_in_hp3 = {5\'b0, axi_id_hp3_in};
2: id_in_hp3 = {4\'b0, axi_id_hp3_in};
3: id_in_hp3 = {3\'b0, axi_id_hp3_in};
4: id_in_hp3 = {2\'b0, axi_id_hp3_in};
5: id_in_hp3 = {1\'b0, axi_id_hp3_in};
6: id_in_hp3 = axi_id_hp3_in;
default : id_in_hp3 = axi_id_hp3_in;
endcase
end
endfunction
assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID);
function [5:0] id_out_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_out_hp3 = axi_id_hp3_out[0];
2: id_out_hp3 = axi_id_hp3_out[1:0];
3: id_out_hp3 = axi_id_hp3_out[2:0];
4: id_out_hp3 = axi_id_hp3_out[3:0];
5: id_out_hp3 = axi_id_hp3_out[4:0];
6: id_out_hp3 = axi_id_hp3_out;
default : id_out_hp3 = axi_id_hp3_out;
endcase
end
endfunction
assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out);
assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out);
assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32\'b0,S_AXI_HP3_WDATA};
assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4\'b0,S_AXI_HP3_WSTRB};
assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
// S_AXI_ACP
function [2:0] id_in_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_in_acp = {2\'b0, axi_id_acp_in};
2: id_in_acp = {1\'b0, axi_id_acp_in};
3: id_in_acp = axi_id_acp_in;
default : id_in_acp = axi_id_acp_in;
endcase
end
endfunction
assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W);
function [2:0] id_out_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_out_acp = axi_id_acp_out[0];
2: id_out_acp = axi_id_acp_out[1:0];
3: id_out_acp = axi_id_acp_out;
default : id_out_acp = axi_id_acp_out;
endcase
end
endfunction
assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out);
assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out);
// FMIO Tristate Inversion logic
//FMIO I2C0
assign I2C0_SDA_T = ~ I2C0_SDA_T_n;
assign I2C0_SCL_T = ~ I2C0_SCL_T_n;
//FMIO I2C1
assign I2C1_SDA_T = ~ I2C1_SDA_T_n;
assign I2C1_SCL_T = ~ I2C1_SCL_T_n;
//FMIO SPI0
assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
assign SPI0_MISO_T = ~ SPI0_MISO_T_n;
assign SPI0_SS_T = ~ SPI0_SS_T_n;
//FMIO SPI1
assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
assign SPI1_MISO_T = ~ SPI1_MISO_T_n;
assign SPI1_SS_T = ~ SPI1_SS_T_n;
// EMIO GEM0 MDIO
assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
// EMIO GEM1 MDIO
assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
// EMIO GPIO
assign GPIO_T = ~ GPIO_T_n;
// EMIO GPIO Width Control
function [63:0] gpio_width_adjust_in;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_in = {63\'b0, gpio_in};
2: gpio_width_adjust_in = {62\'b0, gpio_in};
3: gpio_width_adjust_in = {61\'b0, gpio_in};
4: gpio_width_adjust_in = {60\'b0, gpio_in};
5: gpio_width_adjust_in = {59\'b0, gpio_in};
6: gpio_width_adjust_in = {58\'b0, gpio_in};
7: gpio_width_adjust_in = {57\'b0, gpio_in};
8: gpio_width_adjust_in = {56\'b0, gpio_in};
9: gpio_width_adjust_in = {55\'b0, gpio_in};
10: gpio_width_adjust_in = {54\'b0, gpio_in};
11: gpio_width_adjust_in = {53\'b0, gpio_in};
12: gpio_width_adjust_in = {52\'b0, gpio_in};
13: gpio_width_adjust_in = {51\'b0, gpio_in};
14: gpio_width_adjust_in = {50\'b0, gpio_in};
15: gpio_width_adjust_in = {49\'b0, gpio_in};
16: gpio_width_adjust_in = {48\'b0, gpio_in};
17: gpio_width_adjust_in = {47\'b0, gpio_in};
18: gpio_width_adjust_in = {46\'b0, gpio_in};
19: gpio_width_adjust_in = {45\'b0, gpio_in};
20: gpio_width_adjust_in = {44\'b0, gpio_in};
21: gpio_width_adjust_in = {43\'b0, gpio_in};
22: gpio_width_adjust_in = {42\'b0, gpio_in};
23: gpio_width_adjust_in = {41\'b0, gpio_in};
24: gpio_width_adjust_in = {40\'b0, gpio_in};
25: gpio_width_adjust_in = {39\'b0, gpio_in};
26: gpio_width_adjust_in = {38\'b0, gpio_in};
27: gpio_width_adjust_in = {37\'b0, gpio_in};
28: gpio_width_adjust_in = {36\'b0, gpio_in};
29: gpio_width_adjust_in = {35\'b0, gpio_in};
30: gpio_width_adjust_in = {34\'b0, gpio_in};
31: gpio_width_adjust_in = {33\'b0, gpio_in};
32: gpio_width_adjust_in = {32\'b0, gpio_in};
33: gpio_width_adjust_in = {31\'b0, gpio_in};
34: gpio_width_adjust_in = {30\'b0, gpio_in};
35: gpio_width_adjust_in = {29\'b0, gpio_in};
36: gpio_width_adjust_in = {28\'b0, gpio_in};
37: gpio_width_adjust_in = {27\'b0, gpio_in};
38: gpio_width_adjust_in = {26\'b0, gpio_in};
39: gpio_width_adjust_in = {25\'b0, gpio_in};
40: gpio_width_adjust_in = {24\'b0, gpio_in};
41: gpio_width_adjust_in = {23\'b0, gpio_in};
42: gpio_width_adjust_in = {22\'b0, gpio_in};
43: gpio_width_adjust_in = {21\'b0, gpio_in};
44: gpio_width_adjust_in = {20\'b0, gpio_in};
45: gpio_width_adjust_in = {19\'b0, gpio_in};
46: gpio_width_adjust_in = {18\'b0, gpio_in};
47: gpio_width_adjust_in = {17\'b0, gpio_in};
48: gpio_width_adjust_in = {16\'b0, gpio_in};
49: gpio_width_adjust_in = {15\'b0, gpio_in};
50: gpio_width_adjust_in = {14\'b0, gpio_in};
51: gpio_width_adjust_in = {13\'b0, gpio_in};
52: gpio_width_adjust_in = {12\'b0, gpio_in};
53: gpio_width_adjust_in = {11\'b0, gpio_in};
54: gpio_width_adjust_in = {10\'b0, gpio_in};
55: gpio_width_adjust_in = {9\'b0, gpio_in};
56: gpio_width_adjust_in = {8\'b0, gpio_in};
57: gpio_width_adjust_in = {7\'b0, gpio_in};
58: gpio_width_adjust_in = {6\'b0, gpio_in};
59: gpio_width_adjust_in = {5\'b0, gpio_in};
60: gpio_width_adjust_in = {4\'b0, gpio_in};
61: gpio_width_adjust_in = {3\'b0, gpio_in};
62: gpio_width_adjust_in = {2\'b0, gpio_in};
63: gpio_width_adjust_in = {1\'b0, gpio_in};
64: gpio_width_adjust_in = gpio_in;
default : gpio_width_adjust_in = gpio_in;
endcase
end
endfunction
assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
function [63:0] gpio_width_adjust_out;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_out = gpio_o[0];
2: gpio_width_adjust_out = gpio_o[1:0];
3: gpio_width_adjust_out = gpio_o[2:0];
4: gpio_width_adjust_out = gpio_o[3:0];
5: gpio_width_adjust_out = gpio_o[4:0];
6: gpio_width_adjust_out = gpio_o[5:0];
7: gpio_width_adjust_out = gpio_o[6:0];
8: gpio_width_adjust_out = gpio_o[7:0];
9: gpio_width_adjust_out = gpio_o[8:0];
10: gpio_width_adjust_out = gpio_o[9:0];
11: gpio_width_adjust_out = gpio_o[10:0];
12: gpio_width_adjust_out = gpio_o[11:0];
13: gpio_width_adjust_out = gpio_o[12:0];
14: gpio_width_adjust_out = gpio_o[13:0];
15: gpio_width_adjust_out = gpio_o[14:0];
16: gpio_width_adjust_out = gpio_o[15:0];
17: gpio_width_adjust_out = gpio_o[16:0];
18: gpio_width_adjust_out = gpio_o[17:0];
19: gpio_width_adjust_out = gpio_o[18:0];
20: gpio_width_adjust_out = gpio_o[19:0];
21: gpio_width_adjust_out = gpio_o[20:0];
22: gpio_width_adjust_out = gpio_o[21:0];
23: gpio_width_adjust_out = gpio_o[22:0];
24: gpio_width_adjust_out = gpio_o[23:0];
25: gpio_width_adjust_out = gpio_o[24:0];
26: gpio_width_adjust_out = gpio_o[25:0];
27: gpio_width_adjust_out = gpio_o[26:0];
28: gpio_width_adjust_out = gpio_o[27:0];
29: gpio_width_adjust_out = gpio_o[28:0];
30: gpio_width_adjust_out = gpio_o[29:0];
31: gpio_width_adjust_out = gpio_o[30:0];
32: gpio_width_adjust_out = gpio_o[31:0];
33: gpio_width_adjust_out = gpio_o[32:0];
34: gpio_width_adjust_out = gpio_o[33:0];
35: gpio_width_adjust_out = gpio_o[34:0];
36: gpio_width_adjust_out = gpio_o[35:0];
37: gpio_width_adjust_out = gpio_o[36:0];
38: gpio_width_adjust_out = gpio_o[37:0];
39: gpio_width_adjust_out = gpio_o[38:0];
40: gpio_width_adjust_out = gpio_o[39:0];
41: gpio_width_adjust_out = gpio_o[40:0];
42: gpio_width_adjust_out = gpio_o[41:0];
43: gpio_width_adjust_out = gpio_o[42:0];
44: gpio_width_adjust_out = gpio_o[43:0];
45: gpio_width_adjust_out = gpio_o[44:0];
46: gpio_width_adjust_out = gpio_o[45:0];
47: gpio_width_adjust_out = gpio_o[46:0];
48: gpio_width_adjust_out = gpio_o[47:0];
49: gpio_width_adjust_out = gpio_o[48:0];
50: gpio_width_adjust_out = gpio_o[49:0];
51: gpio_width_adjust_out = gpio_o[50:0];
52: gpio_width_adjust_out = gpio_o[51:0];
53: gpio_width_adjust_out = gpio_o[52:0];
54: gpio_width_adjust_out = gpio_o[53:0];
55: gpio_width_adjust_out = gpio_o[54:0];
56: gpio_width_adjust_out = gpio_o[55:0];
57: gpio_width_adjust_out = gpio_o[56:0];
58: gpio_width_adjust_out = gpio_o[57:0];
59: gpio_width_adjust_out = gpio_o[58:0];
60: gpio_width_adjust_out = gpio_o[59:0];
61: gpio_width_adjust_out = gpio_o[60:0];
62: gpio_width_adjust_out = gpio_o[61:0];
63: gpio_width_adjust_out = gpio_o[62:0];
64: gpio_width_adjust_out = gpio_o;
default : gpio_width_adjust_out = gpio_o;
endcase
end
endfunction
assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out);
assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
// Adding OBUFT to JTAG out port
generate
if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE
\tOBUFT jtag_obuft_inst (
\t.O(PJTAG_TDO),
\t.I(PJTAG_TDO_O),
\t.T(PJTAG_TDO_T)
\t);
end
endgenerate
// -------
// EMIO PJTAG
assign PJTAG_TDO_T = ~ PJTAG_TDO_T_n;
// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
// FCLK_CLK optional clock buffers
generate
if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0
BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
end
if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1
BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
end
if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2
BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
end
if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3
BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
end
endgenerate
assign FCLK_CLK0 = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
genvar i;
generate
\tfor (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
\t\tBIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
\tend
endgenerate
generate
\tfor (i=0; i < 3; i=i+1) begin
\t\tBIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
\tend
endgenerate
generate
\tfor (i=0; i < 15; i=i+1) begin
\t\tBIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
\tend
endgenerate
generate
\tfor (i=0; i < C_DM_WIDTH; i=i+1) begin
\t\tBIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
\tend
endgenerate
generate
\tfor (i=0; i < C_DQ_WIDTH; i=i+1) begin
\t\tBIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
\tend
endgenerate
generate
\tfor (i=0; i < C_DQS_WIDTH; i=i+1) begin
\t\tBIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
\tend
endgenerate
generate
\tfor (i=0; i < C_DQS_WIDTH; i=i+1) begin
\t\tBIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
\tend
endgenerate
//====================
//PSS TOP
//====================
generate
if (C_PACKAGE_NAME == "clg225" ) begin
\twire [21:0] dummy;
\tPS7 PS7_i (
\t .DMA0DATYPE\t\t (DMA0_DATYPE ),
\t .DMA0DAVALID\t\t (DMA0_DAVALID),
\t .DMA0DRREADY\t\t (DMA0_DRREADY),
\t .DMA0RSTN\t\t (DMA0_RSTN ),
\t .DMA1DATYPE\t\t (DMA1_DATYPE ),
\t .DMA1DAVALID\t\t (DMA1_DAVALID),
\t .DMA1DRREADY\t\t (DMA1_DRREADY),
\t .DMA1RSTN\t\t (DMA1_RSTN ),
\t .DMA2DATYPE\t\t (DMA2_DATYPE ),
\t .DMA2DAVALID\t\t (DMA2_DAVALID),
\t .DMA2DRREADY\t\t (DMA2_DRREADY),
\t .DMA2RSTN\t\t (DMA2_RSTN ),
\t .DMA3DATYPE\t\t (DMA3_DATYPE ),
\t .DMA3DAVALID\t\t (DMA3_DAVALID),
\t .DMA3DRREADY\t\t (DMA3_DRREADY),
\t .DMA3RSTN\t\t (DMA3_RSTN ),
\t .EMIOCAN0PHYTX\t (CAN0_PHY_TX ),
\t .EMIOCAN1PHYTX\t (CAN1_PHY_TX ),
\t .EMIOENET0GMIITXD\t (ENET0_GMII_TXD_i ),
\t .EMIOENET0GMIITXEN\t (ENET0_GMII_TX_EN_i),
\t .EMIOENET0GMIITXER\t (ENET0_GMII_TX_ER_i),
\t .EMIOENET0MDIOMDC\t (ENET0_MDIO_MDC),
\t .EMIOENET0MDIOO\t (ENET0_MDIO_O ),
\t .EMIOENET0MDIOTN\t (ENET0_MDIO_T_n ),
\t .EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
\t .EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
\t .EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
\t .EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
\t .EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
\t .EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
\t .EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
\t .EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
\t .EMIOENET0SOFRX (ENET0_SOF_RX),
\t .EMIOENET0SOFTX (ENET0_SOF_TX),
\t .EMIOENET1GMIITXD\t (ENET1_GMII_TXD_i),
\t .EMIOENET1GMIITXEN\t (ENET1_GMII_TX_EN_i),
\t .EMIOENET1GMIITXER\t (ENET1_GMII_TX_ER_i),
\t .EMIOENET1MDIOMDC\t (ENET1_MDIO_MDC),
\t .EMIOENET1MDIOO\t (ENET1_MDIO_O ),
\t .EMIOENET1MDIOTN\t (ENET1_MDIO_T_n),
\t .EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
\t .EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
\t .EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
\t .EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
\t .EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
\t .EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
\t .EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
\t .EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
\t .EMIOENET1SOFRX (ENET1_SOF_RX),
\t .EMIOENET1SOFTX (ENET1_SOF_TX),
\t .EMIOGPIOO\t (gpio_out),
\t .EMIOGPIOTN\t (gpio_out_t_n),
\t .EMIOI2C0SCLO (I2C0_SCL_O),
\t .EMIOI2C0SCLTN (I2C0_SCL_T_n),
\t .EMIOI2C0SDAO\t (I2C0_SDA_O),
\t .EMIOI2C0SDATN\t (I2C0_SDA_T_n),
\t .EMIOI2C1SCLO\t (I2C1_SCL_O),
\t .EMIOI2C1SCLTN (I2C1_SCL_T_n),
\t .EMIOI2C1SDAO\t (I2C1_SDA_O),
\t .EMIOI2C1SDATN\t (I2C1_SDA_T_n),
\t .EMIOPJTAGTDO \t (PJTAG_TDO_O),
\t .EMIOPJTAGTDTN\t (PJTAG_TDO_T_n),
\t .EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
\t .EMIOSDIO0CLK\t\t (SDIO0_CLK ),
\t .EMIOSDIO0CMDO\t (SDIO0_CMD_O ),
\t .EMIOSDIO0CMDTN\t (SDIO0_CMD_T_n ),
\t .EMIOSDIO0DATAO\t (SDIO0_DATA_O),
\t .EMIOSDIO0DATATN\t (SDIO0_DATA_T_n),
\t .EMIOSDIO0LED (SDIO0_LED),
\t .EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
\t .EMIOSDIO1CLK (SDIO1_CLK ),
\t .EMIOSDIO1CMDO (SDIO1_CMD_O ),
\t .EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
\t .EMIOSDIO1DATAO (SDIO1_DATA_O),
\t .EMIOSDIO1DATATN (SDIO1_DATA_T_n),
\t .EMIOSDIO1LED (SDIO1_LED),
\t .EMIOSPI0MO\t\t (SPI0_MOSI_O),
\t .EMIOSPI0MOTN\t (SPI0_MOSI_T_n),
\t .EMIOSPI0SCLKO\t (SPI0_SCLK_O),
\t .EMIOSPI0SCLKTN\t (SPI0_SCLK_T_n),
\t .EMIOSPI0SO\t\t (SPI0_MISO_O),
\t .EMIOSPI0STN\t (SPI0_MISO_T_n),
\t .EMIOSPI0SSON\t ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
\t .EMIOSPI0SSNTN\t (SPI0_SS_T_n),
\t .EMIOSPI1MO\t\t (SPI1_MOSI_O),
\t .EMIOSPI1MOTN\t (SPI1_MOSI_T_n),
\t .EMIOSPI1SCLKO\t (SPI1_SCLK_O),
\t .EMIOSPI1SCLKTN\t (SPI1_SCLK_T_n),
\t .EMIOSPI1SO\t\t (SPI1_MISO_O),
\t .EMIOSPI1STN\t (SPI1_MISO_T_n),
\t .EMIOSPI1SSON\t ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
\t .EMIOSPI1SSNTN\t (SPI1_SS_T_n),
\t .EMIOTRACECTL\t\t (TRACE_CTL'b'_i),
\t .EMIOTRACEDATA\t (TRACE_DATA_i),
\t .EMIOTTC0WAVEO\t ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
\t .EMIOTTC1WAVEO\t ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
\t .EMIOUART0DTRN\t (UART0_DTRN),
\t .EMIOUART0RTSN\t (UART0_RTSN),
\t .EMIOUART0TX\t\t (UART0_TX ),
\t .EMIOUART1DTRN\t (UART1_DTRN),
\t .EMIOUART1RTSN\t (UART1_RTSN),
\t .EMIOUART1TX\t\t (UART1_TX ),
\t .EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
\t .EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
\t .EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
\t .EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
\t .EMIOWDTRSTO \t (WDT_RST_OUT),
\t .EVENTEVENTO (EVENT_EVENTO),
\t .EVENTSTANDBYWFE (EVENT_STANDBYWFE),
\t .EVENTSTANDBYWFI (EVENT_STANDBYWFI),
\t .FCLKCLK\t\t (FCLK_CLK_unbuffered),
\t .FCLKRESETN\t\t ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
\t .EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
\t .EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
\t .FTMTF2PTRIGACK\t ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
\t .FTMTP2FDEBUG\t\t (FTMT_P2F_DEBUG ),
\t .FTMTP2FTRIG\t\t ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
\t .IRQP2F\t\t ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
\t .MAXIGP0ARADDR\t (M_AXI_GP0_ARADDR),
\t .MAXIGP0ARBURST\t (M_AXI_GP0_ARBURST),
\t .MAXIGP0ARCACHE\t (M_AXI_GP0_ARCACHE),
\t .MAXIGP0ARESETN\t (M_AXI_GP0_ARESETN),
\t .MAXIGP0ARID\t (M_AXI_GP0_ARID_FULL ),
\t .MAXIGP0ARLEN\t (M_AXI_GP0_ARLEN ),
\t .MAXIGP0ARLOCK\t (M_AXI_GP0_ARLOCK ),
\t .MAXIGP0ARPROT\t (M_AXI_GP0_ARPROT ),
\t .MAXIGP0ARQOS\t (M_AXI_GP0_ARQOS ),
\t .MAXIGP0ARSIZE\t (M_AXI_GP0_ARSIZE_i ),
\t .MAXIGP0ARVALID\t (M_AXI_GP0_ARVALID),
\t .MAXIGP0AWADDR\t (M_AXI_GP0_AWADDR ),
\t .MAXIGP0AWBURST\t (M_AXI_GP0_AWBURST),
\t .MAXIGP0AWCACHE\t (M_AXI_GP0_AWCACHE),
\t .MAXIGP0AWID\t (M_AXI_GP0_AWID_FULL ),
\t .MAXIGP0AWLEN\t (M_AXI_GP0_AWLEN ),
\t .MAXIGP0AWLOCK\t (M_AXI_GP0_AWLOCK ),
\t .MAXIGP0AWPROT\t (M_AXI_GP0_AWPROT ),
\t .MAXIGP0AWQOS\t (M_AXI_GP0_AWQOS ),
\t .MAXIGP0AWSIZE\t (M_AXI_GP0_AWSIZE_i ),
\t .MAXIGP0AWVALID\t (M_AXI_GP0_AWVALID),
\t .MAXIGP0BREADY\t (M_AXI_GP0_BREADY ),
\t .MAXIGP0RREADY\t (M_AXI_GP0_RREADY ),
\t .MAXIGP0WDATA\t (M_AXI_GP0_WDATA ),
\t .MAXIGP0WID\t (M_AXI_GP0_WID_FULL ),
\t .MAXIGP0WLAST\t (M_AXI_GP0_WLAST ),
\t .MAXIGP0WSTRB\t (M_AXI_GP0_WSTRB ),
\t .MAXIGP0WVALID\t (M_AXI_GP0_WVALID ),
\t .MAXIGP1ARADDR\t (M_AXI_GP1_ARADDR ),
\t .MAXIGP1ARBURST\t (M_AXI_GP1_ARBURST),
\t .MAXIGP1ARCACHE\t (M_AXI_GP1_ARCACHE),
\t .MAXIGP1ARESETN\t (M_AXI_GP1_ARESETN),
\t .MAXIGP1ARID\t (M_AXI_GP1_ARID_FULL ),
\t .MAXIGP1ARLEN\t (M_AXI_GP1_ARLEN ),
\t .MAXIGP1ARLOCK\t (M_AXI_GP1_ARLOCK ),
\t .MAXIGP1ARPROT\t (M_AXI_GP1_ARPROT ),
\t .MAXIGP1ARQOS\t (M_AXI_GP1_ARQOS ),
\t .MAXIGP1ARSIZE\t (M_AXI_GP1_ARSIZE_i ),
\t .MAXIGP1ARVALID\t (M_AXI_GP1_ARVALID),
\t .MAXIGP1AWADDR\t (M_AXI_GP1_AWADDR ),
\t .MAXIGP1AWBURST\t (M_AXI_GP1_AWBURST),
\t .MAXIGP1AWCACHE\t (M_AXI_GP1_AWCACHE),
\t .MAXIGP1AWID\t (M_AXI_GP1_AWID_FULL ),
\t .MAXIGP1AWLEN\t (M_AXI_GP1_AWLEN ),
\t .MAXIGP1AWLOCK\t (M_AXI_GP1_AWLOCK ),
\t .MAXIGP1AWPROT\t (M_AXI_GP1_AWPROT ),
\t .MAXIGP1AWQOS\t (M_AXI_GP1_AWQOS ),
\t .MAXIGP1AWSIZE\t (M_AXI_GP1_AWSIZE_i ),
\t .MAXIGP1AWVALID\t (M_AXI_GP1_AWVALID),
\t .MAXIGP1BREADY\t (M_AXI_GP1_BREADY ),
\t .MAXIGP1RREADY\t (M_AXI_GP1_RREADY ),
\t .MAXIGP1WDATA\t (M_AXI_GP1_WDATA ),
\t .MAXIGP1WID\t (M_AXI_GP1_WID_FULL ),
\t .MAXIGP1WLAST\t (M_AXI_GP1_WLAST ),
\t .MAXIGP1WSTRB\t (M_AXI_GP1_WSTRB ),
\t .MAXIGP1WVALID\t (M_AXI_GP1_WVALID ),
\t .SAXIACPARESETN\t (S_AXI_ACP_ARESETN),
\t .SAXIACPARREADY\t (SAXIACPARREADY_W),
\t .SAXIACPAWREADY\t (SAXIACPAWREADY_W),
\t .SAXIACPBID\t (S_AXI_ACP_BID_out ),
\t .SAXIACPBRESP\t (SAXIACPBRESP_W ),
\t .SAXIACPBVALID\t (SAXIACPBVALID_W ),
\t .SAXIACPRDATA\t (SAXIACPRDATA_W ),
\t .SAXIACPRID\t (S_AXI_ACP_RID_out),
\t .SAXIACPRLAST\t (SAXIACPRLAST_W ),
\t .SAXIACPRRESP\t (SAXIACPRRESP_W ),
\t .SAXIACPRVALID\t (SAXIACPRVALID_W ),
\t .SAXIACPWREADY\t (SAXIACPWREADY_W ),
\t .SAXIGP0ARESETN\t (S_AXI_GP0_ARESETN),
\t .SAXIGP0ARREADY\t (S_AXI_GP0_ARREADY),
\t .SAXIGP0AWREADY\t (S_AXI_GP0_AWREADY),
\t .SAXIGP0BID\t (S_AXI_GP0_BID_out),
\t .SAXIGP0BRESP\t (S_AXI_GP0_BRESP ),
\t .SAXIGP0BVALID\t (S_AXI_GP0_BVALID ),
\t .SAXIGP0RDATA\t (S_AXI_GP0_RDATA ),
\t .SAXIGP0RID\t (S_AXI_GP0_RID_out ),
\t .SAXIGP0RLAST\t (S_AXI_GP0_RLAST ),
\t .SAXIGP0RRESP\t (S_AXI_GP0_RRESP ),
\t .SAXIGP0RVALID\t (S_AXI_GP0_RVALID ),
\t .SAXIGP0WREADY\t (S_AXI_GP0_WREADY ),
\t .SAXIGP1ARESETN\t (S_AXI_GP1_ARESETN),
\t .SAXIGP1ARREADY\t (S_AXI_GP1_ARREADY),
\t .SAXIGP1AWREADY\t (S_AXI_GP1_AWREADY),
\t .SAXIGP1BID\t (S_AXI_GP1_BID_out ),
\t .SAXIGP1BRESP\t (S_AXI_GP1_BRESP ),
\t .SAXIGP1BVALID\t (S_AXI_GP1_BVALID ),
\t .SAXIGP1RDATA\t (S_AXI_GP1_RDATA ),
\t .SAXIGP1RID\t (S_AXI_GP1_RID_out ),
\t .SAXIGP1RLAST\t (S_AXI_GP1_RLAST ),
\t .SAXIGP1RRESP\t (S_AXI_GP1_RRESP ),
\t .SAXIGP1RVALID\t (S_AXI_GP1_RVALID ),
\t .SAXIGP1WREADY\t (S_AXI_GP1_WREADY ),
\t .SAXIHP0ARESETN\t (S_AXI_HP0_ARESETN),
\t .SAXIHP0ARREADY\t (S_AXI_HP0_ARREADY),
\t .SAXIHP0AWREADY\t (S_AXI_HP0_AWREADY),
\t .SAXIHP0BID\t (S_AXI_HP0_BID_out ),
\t .SAXIHP0BRESP\t (S_AXI_HP0_BRESP ),
\t .SAXIHP0BVALID\t (S_AXI_HP0_BVALID ),
\t .SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
\t .SAXIHP0RCOUNT\t (S_AXI_HP0_RCOUNT),
\t .SAXIHP0RDATA\t (S_AXI_HP0_RDATA_out),
\t .SAXIHP0RID\t (S_AXI_HP0_RID_out ),
\t .SAXIHP0RLAST\t (S_AXI_HP0_RLAST),
\t .SAXIHP0RRESP\t (S_AXI_HP0_RRESP),
\t .SAXIHP0RVALID\t (S_AXI_HP0_RVALID),
\t .SAXIHP0WCOUNT\t (S_AXI_HP0_WCOUNT),
\t .SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
\t .SAXIHP0WREADY\t (S_AXI_HP0_WREADY),
\t .SAXIHP1ARESETN\t (S_AXI_HP1_ARESETN),
\t .SAXIHP1ARREADY\t (S_AXI_HP1_ARREADY),
\t .SAXIHP1AWREADY\t (S_AXI_HP1_AWREADY),
\t .SAXIHP1BID\t (S_AXI_HP1_BID_out ),
\t .SAXIHP1BRESP\t (S_AXI_HP1_BRESP ),
\t .SAXIHP1BVALID\t (S_AXI_HP1_BVALID ),
\t .SAXIHP1RACOUNT\t (S_AXI_HP1_RACOUNT ),
\t .SAXIHP1RCOUNT\t (S_AXI_HP1_RCOUNT ),
\t .SAXIHP1RDATA\t (S_AXI_HP1_RDATA_out),
\t .SAXIHP1RID\t (S_AXI_HP1_RID_out ),
\t .SAXIHP1RLAST\t (S_AXI_HP1_RLAST ),
\t .SAXIHP1RRESP\t (S_AXI_HP1_RRESP ),
\t .SAXIHP1RVALID\t (S_AXI_HP1_RVALID),
\t .SAXIHP1WACOUNT\t (S_AXI_HP1_WACOUNT),
\t .SAXIHP1WCOUNT\t (S_AXI_HP1_WCOUNT),
\t .SAXIHP1WREADY\t (S_AXI_HP1_WREADY),
\t .SAXIHP2ARESETN\t (S_AXI_HP2_ARESETN),
\t .SAXIHP2ARREADY\t (S_AXI_HP2_ARREADY),
\t .SAXIHP2AWREADY\t (S_AXI_HP2_AWREADY),
\t .SAXIHP2BID\t (S_AXI_HP2_BID_out ),
\t .SAXIHP2BRESP\t (S_AXI_HP2_BRESP),
\t .SAXIHP2BVALID\t (S_AXI_HP2_BVALID),
\t .SAXIHP2RACOUNT\t (S_AXI_HP2_RACOUNT),
\t .SAXIHP2RCOUNT\t (S_AXI_HP2_RCOUNT),
\t .SAXIHP2RDATA\t (S_AXI_HP2_RDATA_out),
\t .SAXIHP2RID\t (S_AXI_HP2_RID_out ),
\t .SAXIHP2RLAST\t (S_AXI_HP2_RLAST),
\t .SAXIHP2RRESP\t (S_AXI_HP2_RRESP),
\t .SAXIHP2RVALID\t (S_AXI_HP2_RVALID),
\t .SAXIHP2WACOUNT\t (S_AXI_HP2_WACOUNT),
\t .SAXIHP2WCOUNT\t (S_AXI_HP2_WCOUNT),
\t .SAXIHP2WREADY\t (S_AXI_HP2_WREADY),
\t .SAXIHP3ARESETN\t (S_AXI_HP3_ARESETN),
\t .SAXIHP3ARREADY\t (S_AXI_HP3_ARREADY),
\t .SAXIHP3AWREADY\t (S_AXI_HP3_AWREADY),
\t .SAXIHP3BID\t (S_AXI_HP3_BID_out),
\t .SAXIHP3BRESP\t (S_AXI_HP3_BRESP),
\t .SAXIHP3BVALID\t (S_AXI_HP3_BVALID),
\t .SAXIHP3RACOUNT\t (S_AXI_HP3_RACOUNT),
\t .SAXIHP3RCOUNT\t (S_AXI_HP3_RCOUNT),
\t .SAXIHP3RDATA\t (S_AXI_HP3_RDATA_out),
\t .SAXIHP3RID\t (S_AXI_HP3_RID_out),
\t .SAXIHP3RLAST\t (S_AXI_HP3_RLAST),
\t .SAXIHP3RRESP\t (S_AXI_HP3_RRESP),
\t .SAXIHP3RVALID\t (S_AXI_HP3_RVALID),
\t .SAXIHP3WCOUNT\t (S_AXI_HP3_WCOUNT),
\t .SAXIHP3WACOUNT\t (S_AXI_HP3_WACOUNT),
\t .SAXIHP3WREADY\t (S_AXI_HP3_WREADY),
\t .DDRARB (DDR_ARB),
\t .DMA0ACLK\t\t (DMA0_ACLK ),
\t .DMA0DAREADY\t\t (DMA0_DAREADY),
\t .DMA0DRLAST\t\t (DMA0_DRLAST ),
\t .DMA0DRTYPE (DMA0_DRTYPE),
\t .DMA0DRVALID\t\t (DMA0_DRVALID),
\t .DMA1ACLK\t\t (DMA1_ACLK ),
\t .DMA1DAREADY\t\t (DMA1_DAREADY),
\t .DMA1DRLAST\t\t (DMA1_DRLAST ),
\t .DMA1DRTYPE (DMA1_DRTYPE),
\t .DMA1DRVALID\t\t (DMA1_DRVALID),
\t .DMA2ACLK\t\t (DMA2_ACLK ),
\t .DMA2DAREADY\t\t (DMA2_DAREADY),
\t .DMA2DRLAST\t\t (DMA2_DRLAST ),
\t .DMA2DRTYPE (DMA2_DRTYPE),
\t .DMA2DRVALID\t\t (DMA2_DRVALID),
\t .DMA3ACLK\t\t (DMA3_ACLK ),
\t .DMA3DAREADY\t\t (DMA3_DAREADY),
\t .DMA3DRLAST\t\t (DMA3_DRLAST ),
\t .DMA3DRTYPE (DMA3_DRTYPE),
\t .DMA3DRVALID\t\t (DMA3_DRVALID),
\t .EMIOCAN0PHYRX\t (CAN0_PHY_RX),
\t .EMIOCAN1PHYRX\t (CAN1_PHY_RX),
\t .EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
\t .EMIOENET0GMIICOL (ENET0_GMII_COL_i),
\t .EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
\t .EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
\t .EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
\t .EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
\t .EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
\t .EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
\t .EMIOENET0MDIOI (ENET0_MDIO_I),
\t .EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
\t .EMIOENET1GMIICOL (ENET1_GMII_COL_i),
\t .EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
\t .EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
\t .EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
\t .EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
\t .EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
\t .EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
\t .EMIOENET1MDIOI (ENET1_MDIO_I),
\t .EMIOGPIOI\t (gpio_in63_0 ),
\t .EMIOI2C0SCLI\t (I2C0_SCL_I),
\t .EMIOI2C0SDAI\t (I2C0_SDA_I),
\t .EMIOI2C1SCLI\t (I2C1_SCL_I),
\t .EMIOI2C1SDAI\t (I2C1_SDA_I),
\t .EMIOPJTAGTCK\t\t (PJTAG_TCK),
\t .EMIOPJTAGTDI\t\t (PJTAG_TDI),
\t .EMIOPJTAGTMS\t\t (PJTAG_TMS),
\t .EMIOSDIO0CDN (SDIO0_CDN),
\t .EMIOSDIO0CLKFB\t (SDIO0_CLK_FB ),
\t .EMIOSDIO0CMDI\t (SDIO0_CMD_I ),
\t .EMIOSDIO0DATAI\t (SDIO0_DATA_I ),
\t .EMIOSDIO0WP (SDIO0_WP),
\t .EMIOSDIO1CDN (SDIO1_CDN),
\t .EMIOSDIO1CLKFB\t (SDIO1_CLK_FB ),
\t .EMIOSDIO1CMDI\t (SDIO1_CMD_I ),
\t .EMIOSDIO1DATAI\t (SDIO1_DATA_I ),
\t .EMIOSDIO1WP (SDIO1_WP),
\t .EMIOSPI0MI\t\t (SPI0_MISO_I),
\t .EMIOSPI0SCLKI\t (SPI0_SCLK_I),
\t .EMIOSPI0SI\t\t (SPI0_MOSI_I),
\t .EMIOSPI0SSIN \t (SPI0_SS_I),
\t .EMIOSPI1MI\t\t (SPI1_MISO_I),
\t .EMIOSPI1SCLKI\t (SPI1_SCLK_I),
\t .EMIOSPI1SI\t\t (SPI1_MOSI_I),
\t .EMIOSPI1SSIN\t (SPI1_SS_I),
\t .EMIOSRAMINTIN (SRAM_INTIN),
\t .EMIOTRACECLK\t\t (TRACE_CLK),
\t .EMIOTTC0CLKI\t ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
\t .EMIOTTC1CLKI\t ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
\t .EMIOUART0CTSN\t (UART0_CTSN),
\t .EMIOUART0DCDN\t (UART0_DCDN),
\t .EMIOUART0DSRN\t (UART0_DSRN),
\t .EMIOUART0RIN\t\t (UART0_RIN ),
\t .EMIOUART0RX\t\t (UART0_RX ),
\t .EMIOUART1CTSN\t (UART1_CTSN),
\t .EMIOUART1DCDN\t (UART1_DCDN),
\t .EMIOUART1DSRN\t (UART1_DSRN),
\t .EMIOUART1RIN\t\t (UART1_RIN ),
\t .EMIOUART1RX\t\t (UART1_RX ),
\t .EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
\t .EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
\t .EMIOWDTCLKI\t\t (WDT_CLK_IN),
\t .EVENTEVENTI (EVENT_EVENTI),
\t .FCLKCLKTRIGN\t\t (fclk_clktrig_gnd),
\t .FPGAIDLEN\t\t (FPGA_IDLE_N),
\t .FTMDTRACEINATID\t (FTMD_TRACEIN_ATID_i),
\t .FTMDTRACEINCLOCK\t (FTMD_TRACEIN_CLK),
\t .FTMDTRACEINDATA\t (FTMD_TRACEIN_DATA_i),
\t .FTMDTRACEINVALID\t (FTMD_TRACEIN_VALID_i),
\t .FTMTF2PDEBUG\t\t (FTMT_F2P_DEBUG ),
\t .FTMTF2PTRIG\t\t ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
\t .FTMTP2FTRIGACK\t ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
\t .IRQF2P\t\t (irq_f2p_i),
\t .MAXIGP0ACLK\t (M_AXI_GP0_ACLK),
\t .MAXIGP0ARREADY\t (M_AXI_GP0_ARREADY),
\t .MAXIGP0AWREADY\t (M_AXI_GP0_AWREADY),
\t .MAXIGP0BID\t (M_AXI_GP0_BID_FULL ),
\t .MAXIGP0BRESP\t (M_AXI_GP0_BRESP ),
\t .MAXIGP0BVALID\t (M_AXI_GP0_BVALID ),
\t .MAXIGP0RDATA\t (M_AXI_GP0_RDATA ),
\t .MAXIGP0RID\t (M_AXI_GP0_RID_FULL ),
\t .MAXIGP0RLAST\t (M_AXI_GP0_RLAST ),
\t .MAXIGP0RRESP\t (M_AXI_GP0_RRESP ),
\t .MAXIGP0RVALID\t (M_AXI_GP0_RVALID ),
\t .MAXIGP0WREADY\t (M_AXI_GP0_WREADY ),
\t .MAXIGP1ACLK\t (M_AXI_GP1_ACLK ),
\t .MAXIGP1ARREADY\t (M_AXI_GP1_ARREADY),
\t .MAXIGP1AWREADY\t (M_AXI_GP1_AWREADY),
\t .MAXIGP1BID\t (M_AXI_GP1_BID_FULL ),
\t .MAXIGP1BRESP\t (M_AXI_GP1_BRESP ),
\t .MAXIGP1BVALID\t (M_AXI_GP1_BVALID ),
\t .MAXIGP1RDATA\t (M_AXI_GP1_RDATA ),
\t .MAXIGP1RID\t (M_AXI_GP1_RID_FULL ),
\t .MAXIGP1RLAST\t (M_AXI_GP1_RLAST ),
\t .MAXIGP1RRESP\t (M_AXI_GP1_RRESP ),
\t .MAXIGP1RVALID\t (M_AXI_GP1_RVALID ),
\t .MAXIGP1WREADY\t (M_AXI_GP1_WREADY ),
\t .SAXIACPACLK\t (S_AXI_ACP_ACLK ),
\t .SAXIACPARADDR\t (SAXIACPARADDR_W ),
\t .SAXIACPARBURST\t (SAXIACPARBURST_W),
\t .SAXIACPARCACHE\t (SAXIACPARCACHE_W),
\t .SAXIACPARID\t (S_AXI_ACP_ARID_in ),
\t .SAXIACPARLEN\t (SAXIACPARLEN_W ),
\t .SAXIACPARLOCK\t (SAXIACPARLOCK_W ),
\t .SAXIACPARPROT\t (SAXIACPARPROT_W ),
\t .SAXIACPARQOS\t (S_AXI_ACP_ARQOS ),
\t .SAXIACPARSIZE\t (SAXIACPARSIZE_W[1:0] ),
\t .SAXIACPARUSER\t (SAXIACPARUSER_W ),
\t .SAXIACPARVALID\t (SAXIACPARVALID_W),
\t .SAXIACPAWADDR\t (SAXIACPAWADDR_W ),
\t .SAXIACPAWBURST\t (SAXIACPAWBURST_W),
\t .SAXIACPAWCACHE\t (SAXIACPAWCACHE_W),
\t .SAXIACPAWID\t (S_AXI_ACP_AWID_in ),
\t .SAXIACPAWLEN\t (SAXIACPAWLEN_W ),
\t .SAXIACPAWLOCK\t (SAXIACPAWLOCK_W ),
\t .SAXIACPAWPROT\t (SAXIACPAWPROT_W ),
\t .SAXIACPAWQOS\t (S_AXI_ACP_AWQOS ),
\t .SAXIACPAWSIZE\t (SAXIACPAWSIZE_W[1:0] ),
\t .SAXIACPAWUSER\t (SAXIACPAWUSER_W ),
\t .SAXIACPAWVALID\t (SAXIACPAWVALID_W),
\t .SAXIACPBREADY\t (SAXIACPBREADY_W ),
\t .SAXIACPRREADY\t (SAXIACPRREADY_W ),
\t .SAXIACPWDATA\t (SAXIACPWDATA_W ),
\t .SAXIACPWID\t (S_AXI_ACP_WID_in ),
\t .SAXIACPWLAST\t (SAXIACPWLAST_W ),
\t .SAXIACPWSTRB\t (SAXIACPWSTRB_W ),
\t .SAXIACPWVALID\t (SAXIACPWVALID_W ),
\t .SAXIGP0ACLK (S_AXI_GP0_ACLK ),
\t .SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
\t .SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
\t .SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
\t .SAXIGP0ARID (S_AXI_GP0_ARID_in ),
\t .SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
\t .SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
\t .SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
\t .SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
\t .SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
\t .SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
\t .SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
\t .SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
\t .SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
\t .SAXIGP0AWID (S_AXI_GP0_AWID_in ),
\t .SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
\t .SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
\t .SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
\t .SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
\t .SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
\t .SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
\t .SAXIGP0BREADY (S_AXI_GP0_BREADY ),
\t .SAXIGP0RREADY (S_AXI_GP0_RREADY ),
\t .SAXIGP0WDATA (S_AXI_GP0_WDATA ),
\t .SAXIGP0WID (S_AXI_GP0_WID_in ),
\t .SAXIGP0WLAST (S_AXI_GP0_WLAST ),
\t .SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
\t .SAXIGP0WVALID (S_AXI_GP0_WVALID ),
\t .SAXIGP1ACLK\t (S_AXI_GP1_ACLK ),
\t .SAXIGP1ARADDR\t (S_AXI_GP1_ARADDR ),
\t .SAXIGP1ARBURST\t (S_AXI_GP1_ARBURST),
\t .SAXIGP1ARCACHE\t (S_AXI_GP1_ARCACHE),
\t .SAXIGP1ARID\t (S_AXI_GP1_ARID_in ),
\t .SAXIGP1ARLEN\t (S_AXI_GP1_ARLEN ),
\t .SAXIGP1ARLOCK\t (S_AXI_GP1_ARLOCK ),
\t .SAXIGP1ARPROT\t (S_AXI_GP1_ARPROT ),
\t .SAXIGP1ARQOS\t (S_AXI_GP1_ARQOS ),
\t .SAXIGP1ARSIZE\t (S_AXI_GP1_ARSIZE[1:0] ),
\t .SAXIGP1ARVALID\t (S_AXI_GP1_ARVALID),
\t .SAXIGP1AWADDR\t (S_AXI_GP1_AWADDR ),
\t .SAXIGP1AWBURST\t (S_AXI_GP1_AWBURST),
\t .SAXIGP1AWCACHE\t (S_AXI_GP1_AWCACHE),
\t .SAXIGP1AWID\t (S_AXI_GP1_AWID_in ),
\t .SAXIGP1AWLEN\t (S_AXI_GP1_AWLEN ),
\t .SAXIGP1AWLOCK\t (S_AXI_GP1_AWLOCK ),
\t .SAXIGP1AWPROT\t (S_AXI_GP1_AWPROT ),
\t .SAXIGP1AWQOS\t (S_AXI_GP1_AWQOS ),
\t .SAXIGP1AWSIZE\t (S_AXI_GP1_AWSIZE[1:0] ),
\t .SAXIGP1AWVALID\t (S_AXI_GP1_AWVALID),
\t .SAXIGP1BREADY\t (S_AXI_GP1_BREADY ),
\t .SAXIGP1RREADY\t (S_AXI_GP1_RREADY ),
\t .SAXIGP1WDATA\t (S_AXI_GP1_WDATA ),
\t .SAXIGP1WID\t (S_AXI_GP1_WID_in ),
\t .SAXIGP1WLAST\t (S_AXI_GP1_WLAST ),
\t .SAXIGP1WSTRB\t (S_AXI_GP1_WSTRB ),
\t .SAXIGP1WVALID\t (S_AXI_GP1_WVALID ),
\t .SAXIHP0ACLK (S_AXI_HP0_ACLK ),
\t .SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
\t .SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
\t .SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
\t .SAXIHP0ARID (S_AXI_HP0_ARID_in),
\t .SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
\t .SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
\t .SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
\t .SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
\t .SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
\t .SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
\t .SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
\t .SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
\t .SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
\t .SAXIHP0AWID (S_AXI_HP0_AWID_in),
\t .SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
\t .SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
\t .SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
\t .SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
\t .SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
\t .SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
\t .SAXIHP0BREADY (S_AXI_HP0_BREADY),
\t .SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
\t .SAXIHP0RREADY (S_AXI_HP0_RREADY),
\t .SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
\t .SAXIHP0WID (S_AXI_HP0_WID_in),
\t .SAXIHP0WLAST (S_AXI_HP0_WLAST),
\t .SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
\t .SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
\t .SAXIHP0WVALID (S_AXI_HP0_WVALID),
\t .SAXIHP1ACLK (S_AXI_HP1_ACLK),
\t .SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
\t .SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
\t .SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
\t .SAXIHP1ARID (S_AXI_HP1_ARID_in),
\t .SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
\t .SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
\t .SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
\t .SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
\t .SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
\t .SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
\t .SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
\t .SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
\t .SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
\t .SAXIHP1AWID (S_AXI_HP1_AWID_in),
\t .SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
\t .SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
\t .SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
\t .SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
\t .SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
\t .SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
\t .SAXIHP1BREADY (S_AXI_HP1_BREADY),
\t .SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
\t .SAXIHP1RREADY (S_AXI_HP1_RREADY),
\t .SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
\t .SAXIHP1WID (S_AXI_HP1_WID_in),
\t .SAXIHP1WLAST (S_AXI_HP1_WLAST),
\t .SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
\t .SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
\t .SAXIHP1WVALID (S_AXI_HP1_WVALID),
\t .SAXIHP2ACLK (S_AXI_HP2_ACLK),
\t .SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
\t .SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
\t .SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
\t .SAXIHP2ARID (S_AXI_HP2_ARID_in),
\t .SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
\t .SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
\t .SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
\t .SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
\t .SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
\t .SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
\t .SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
\t .SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
\t .SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
\t .SAXIHP2AWID (S_AXI_HP2_AWID_in),
\t .SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
\t .SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
\t .SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
\t .SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
\t .SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
\t .SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
\t .SAXIHP2BREADY (S_AXI_HP2_BREADY),
\t .SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
\t .SAXIHP2RREADY (S_AXI_HP2_RREADY),
\t .SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
\t .SAXIHP2WID (S_AXI_HP2_WID_in),
\t .SAXIHP2WLAST (S_AXI_HP2_WLAST),
\t .SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
\t .SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
\t .SAXIHP2WVALID (S_AXI_HP2_WVALID),
\t .SAXIHP3ACLK (S_AXI_HP3_ACLK),
\t .SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
\t .SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
\t .SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
\t .SAXIHP3ARID (S_AXI_HP3_ARID_in ),
\t .SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
\t .SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
\t .SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
\t .SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
\t .SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
\t .SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
\t .SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
\t .SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
\t .SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
\t .SAXIHP3AWID (S_AXI_HP3_AWID_in),
\t .SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
\t .SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
\t .SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
\t .SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
\t .SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
\t .SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
\t .SAXIHP3BREADY (S_AXI_HP3_BREADY),
\t .SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
\t .SAXIHP3RREADY (S_AXI_HP3_RREADY),
\t .SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
\t .SAXIHP3WID (S_AXI_HP3_WID_in),
\t .SAXIHP3WLAST (S_AXI_HP3_WLAST),
\t .SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
\t .SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
\t .SAXIHP3WVALID (S_AXI_HP3_WVALID),
\t .DDRA\t\t (buffered_DDR_Addr),
\t .DDRBA\t\t (buffered_DDR_BankAddr),
\t .DDRCASB\t\t (buffered_DDR_CAS_n),
\t .DDRCKE\t\t (buffered_DDR_CKE),
\t .DDRCKN\t\t (buffered_DDR_Clk_n),
\t .DDRCKP\t\t (buffered_DDR_Clk),
\t .DDRCSB\t\t (buffered_DDR_CS_n),
\t .DDRDM\t\t (buffered_DDR_DM),
\t .DDRDQ\t\t (buffered_DDR_DQ),
\t .DDRDQSN\t\t (buffered_DDR_DQS_n),
\t .DDRDQSP\t\t (buffered_DDR_DQS),
\t .DDRDRSTB (buffered_DDR_DRSTB),
\t .DDRODT\t\t (buffered_DDR_ODT),
\t .DDRRASB\t\t (buffered_DDR_RAS_n),
\t .DDRVRN (buffered_DDR_VRN),
\t .DDRVRP (buffered_DDR_VRP),
\t .DDRWEB (buffered_DDR_WEB),
\t .MIO\t\t\t ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
\t .PSCLK\t\t (buffered_PS_CLK),
\t .PSPORB\t\t (buffered_PS_PORB),
\t .PSSRSTB\t\t (buffered_PS_SRSTB)
);
end
else begin
\tPS7 PS7_i (
\t .DMA0DATYPE\t\t (DMA0_DATYPE ),
\t .DMA0DAVALID\t\t (DMA0_DAVALID),
\t .DMA0DRREADY\t\t (DMA0_DRREADY),
\t .DMA0RSTN\t\t (DMA0_RSTN ),
\t .DMA1DATYPE\t\t (DMA1_DATYPE ),
\t .DMA1DAVALID\t\t (DMA1_DAVALID),
\t .DMA1DRREADY\t\t (DMA1_DRREADY),
\t .DMA1RSTN\t\t (DMA1_RSTN ),
\t .DMA2DATYPE\t\t (DMA2_DATYPE ),
\t .DMA2DAVALID\t\t (DMA2_DAVALID),
\t .DMA2DRREADY\t\t (DMA2_DRREADY),
\t .DMA2RSTN\t\t (DMA2_RSTN ),
\t .DMA3DATYPE\t\t (DMA3_DATYPE ),
\t .DMA3DAVALID\t\t (DMA3_DAVALID),
\t .DMA3DRREADY\t\t (DMA3_DRREADY),
\t .DMA3RSTN\t\t (DMA3_RSTN ),
\t .EMIOCAN0PHYTX\t (CAN0_PHY_TX ),
\t .EMIOCAN1PHYTX\t (CAN1_PHY_TX ),
\t .EMIOENET0GMIITXD\t (ENET0_GMII_TXD_i ),
\t .EMIOENET0GMIITXEN\t (ENET0_GMII_TX_EN_i),
\t .EMIOENET0GMIITXER\t (ENET0_GMII_TX_ER_i),
\t .EMIOENET0MDIOMDC\t (ENET0_MDIO_MDC),
\t .EMIOENET0MDIOO\t (ENET0_MDIO_O ),
\t .EMIOENET0MDIOTN\t (ENET0_MDIO_T_n ),
\t .EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
\t .EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
\t .EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
\t .EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
\t .EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
\t .EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
\t .EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
\t .EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
\t .EMIOENET0SOFRX (ENET0_SOF_RX),
\t .EMIOENET0SOFTX (ENET0_SOF_TX),
\t .EMIOENET1GMIITXD\t (ENET1_GMII_TXD_i),
\t .EMIOENET1GMIITXEN\t (ENET1_GMII_TX_EN_i),
\t .EMIOENET1GMIITXER\t (ENET1_GMII_TX_ER_i),
\t .EMIOENET1MDIOMDC\t (ENET1_MDIO_MDC),
\t .EMIOENET1MDIOO\t (ENET1_MDIO_O ),
\t .EMIOENET1MDIOTN\t (ENET1_MDIO_T_n),
\t .EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
\t .EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
\t .EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
\t .EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
\t .EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
\t .EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
\t .EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
\t .EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
\t .EMIOENET1SOFRX (ENET1_SOF_RX),
\t .EMIOENET1SOFTX (ENET1_SOF_TX),
\t .EMIOGPIOO\t (gpio_out),
\t .EMIOGPIOTN\t (gpio_out_t_n),
\t .EMIOI2C0SCLO (I2C0_SCL_O),
\t .EMIOI2C0SCLTN (I2C0_SCL_T_n),
\t .EMIOI2C0SDAO\t (I2C0_SDA_O),
\t .EMIOI2C0SDATN\t (I2C0_SDA_T_n),
\t .EMIOI2C1SCLO\t (I2C1_SCL_O),
\t .EMIOI2C1SCLTN (I2C1_SCL_T_n),
\t .EMIOI2C1SDAO\t (I2C1_SDA_O),
\t .EMIOI2C1SDATN\t (I2C1_SDA_T_n),
\t .EMIOPJTAGTDO \t (PJTAG_TDO_O),
\t .EMIOPJTAGTDTN\t (PJTAG_TDO_T_n),
\t .EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
\t .EMIOSDIO0CLK\t\t (SDIO0_CLK ),
\t .EMIOSDIO0CMDO\t (SDIO0_CMD_O ),
\t .EMIOSDIO0CMDTN\t (SDIO0_CMD_T_n ),
\t .EMIOSDIO0DATAO\t (SDIO0_DATA_O),
\t .EMIOSDIO0DATATN\t (SDIO0_DATA_T_n),
\t .EMIOSDIO0LED (SDIO0_LED),
\t .EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
\t .EMIOSDIO1CLK (SDIO1_CLK ),
\t .EMIOSDIO1CMDO (SDIO1_CMD_O ),
\t .EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
\t .EMIOSDIO1DATAO (SDIO1_DATA_O),
\t .EMIOSDIO1DATATN (SDIO1_DATA_T_n),
\t .EMIOSDIO1LED (SDIO1_LED),
\t .EMIOSPI0MO\t\t (SPI0_MOSI_O),
\t .EMIOSPI0MOTN\t (SPI0_MOSI_T_n),
\t .EMIOSPI0SCLKO\t (SPI0_SCLK_O),
\t .EMIOSPI0SCLKTN\t (SPI0_SCLK_T_n),
\t .EMIOSPI0SO\t\t (SPI0_MISO_O),
\t .EMIOSPI0STN\t (SPI0_MISO_T_n),
\t .EMIOSPI0SSON\t ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
\t .EMIOSPI0SSNTN\t (SPI0_SS_T_n),
\t .EMIOSPI1MO\t\t (SPI1_MOSI_O),
\t .EMIOSPI1MOTN\t (SPI1_MOSI_T_n),
\t .EMIOSPI1SCLKO\t (SPI1_SCLK_O),
\t .EMIOSPI1SCLKTN\t (SPI1_SCLK_T_n),
\t .EMIOSPI1SO\t\t (SPI1_MISO_O),
\t .EMIOSPI1STN\t (SPI1_MISO_T_n),
\t .EMIOSPI1SSON\t ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
\t .EMIOSPI1SSNTN\t (SPI1_SS_T_n),
\t .EMIOTRACECTL\t\t (TRACE_CTL_i),
\t .EMIOTRACEDATA\t (TRACE_DATA_i),
\t .EMIOTTC0WAVEO\t ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
\t .EMIOTTC1WAVEO\t ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
\t .EMIOUART0DTRN\t (UART0_DTRN),
\t .EMIOUART0RTSN\t (UART0_RTSN),
\t .EMIOUART0TX\t\t (UART0_TX ),
\t .EMIOUART1DTRN\t (UART1_DTRN),
\t .EMIOUART1RTSN\t (UART1_RTSN),
\t .EMIOUART1TX\t\t (UART1_TX ),
\t .EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
\t .EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
\t .EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
\t .EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
\t .EMIOWDTRSTO \t (WDT_RST_OUT),
\t .EVENTEVENTO (EVENT_EVENTO),
\t .EVENTSTANDBYWFE (EVENT_STANDBYWFE),
\t .EVENTSTANDBYWFI (EVENT_STANDBYWFI),
\t .FCLKCLK\t\t (FCLK_CLK_unbuffered),
\t .FCLKRESETN\t\t ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
\t .EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
\t .EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
\t .FTMTF2PTRIGACK\t ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
\t .FTMTP2FDEBUG\t\t (FTMT_P2F_DEBUG ),
\t .FTMTP2FTRIG\t\t ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
\t .IRQP2F\t\t ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
\t .MAXIGP0ARADDR\t (M_AXI_GP0_ARADDR),
\t .MAXIGP0ARBURST\t (M_AXI_GP0_ARBURST),
\t .MAXIGP0ARCACHE\t (M_AXI_GP0_ARCACHE),
\t .MAXIGP0ARESETN\t (M_AXI_GP0_ARESETN),
\t .MAXIGP0ARID\t (M_AXI_GP0_ARID_FULL ),
\t .MAXIGP0ARLEN\t (M_AXI_GP0_ARLEN ),
\t .MAXIGP0ARLOCK\t (M_AXI_GP0_ARLOCK ),
\t .MAXIGP0ARPROT\t (M_AXI_GP0_ARPROT ),
\t .MAXIGP0ARQOS\t (M_AXI_GP0_ARQOS ),
\t .MAXIGP0ARSIZE\t (M_AXI_GP0_ARSIZE_i ),
\t .MAXIGP0ARVALID\t (M_AXI_GP0_ARVALID),
\t .MAXIGP0AWADDR\t (M_AXI_GP0_AWADDR ),
\t .MAXIGP0AWBURST\t (M_AXI_GP0_AWBURST),
\t .MAXIGP0AWCACHE\t (M_AXI_GP0_AWCACHE),
\t .MAXIGP0AWID\t (M_AXI_GP0_AWID_FULL ),
\t .MAXIGP0AWLEN\t (M_AXI_GP0_AWLEN ),
\t .MAXIGP0AWLOCK\t (M_AXI_GP0_AWLOCK ),
\t .MAXIGP0AWPROT\t (M_AXI_GP0_AWPROT ),
\t .MAXIGP0AWQOS\t (M_AXI_GP0_AWQOS ),
\t .MAXIGP0AWSIZE\t (M_AXI_GP0_AWSIZE_i ),
\t .MAXIGP0AWVALID\t (M_AXI_GP0_AWVALID),
\t .MAXIGP0BREADY\t (M_AXI_GP0_BREADY ),
\t .MAXIGP0RREADY\t (M_AXI_GP0_RREADY ),
\t .MAXIGP0WDATA\t (M_AXI_GP0_WDATA ),
\t .MAXIGP0WID\t (M_AXI_GP0_WID_FULL ),
\t .MAXIGP0WLAST\t (M_AXI_GP0_WLAST ),
\t .MAXIGP0WSTRB\t (M_AXI_GP0_WSTRB ),
\t .MAXIGP0WVALID\t (M_AXI_GP0_WVALID ),
\t .MAXIGP1ARADDR\t (M_AXI_GP1_ARADDR ),
\t .MAXIGP1ARBURST\t (M_AXI_GP1_ARBURST),
\t .MAXIGP1ARCACHE\t (M_AXI_GP1_ARCACHE),
\t .MAXIGP1ARESETN\t (M_AXI_GP1_ARESETN),
\t .MAXIGP1ARID\t (M_AXI_GP1_ARID_FULL ),
\t .MAXIGP1ARLEN\t (M_AXI_GP1_ARLEN ),
\t .MAXIGP1ARLOCK\t (M_AXI_GP1_ARLOCK ),
\t .MAXIGP1ARPROT\t (M_AXI_GP1_ARPROT ),
\t .MAXIGP1ARQOS\t (M_AXI_GP1_ARQOS ),
\t .MAXIGP1ARSIZE\t (M_AXI_GP1_ARSIZE_i ),
\t .MAXIGP1ARVALID\t (M_AXI_GP1_ARVALID),
\t .MAXIGP1AWADDR\t (M_AXI_GP1_AWADDR ),
\t .MAXIGP1AWBURST\t (M_AXI_GP1_AWBURST),
\t .MAXIGP1AWCACHE\t (M_AXI_GP1_AWCACHE),
\t .MAXIGP1AWID\t (M_AXI_GP1_AWID_FULL ),
\t .MAXIGP1AWLEN\t (M_AXI_GP1_AWLEN ),
\t .MAXIGP1AWLOCK\t (M_AXI_GP1_AWLOCK ),
\t .MAXIGP1AWPROT\t (M_AXI_GP1_AWPROT ),
\t .MAXIGP1AWQOS\t (M_AXI_GP1_AWQOS ),
\t .MAXIGP1AWSIZE\t (M_AXI_GP1_AWSIZE_i ),
\t .MAXIGP1AWVALID\t (M_AXI_GP1_AWVALID),
\t .MAXIGP1BREADY\t (M_AXI_GP1_BREADY ),
\t .MAXIGP1RREADY\t (M_AXI_GP1_RREADY ),
\t .MAXIGP1WDATA\t (M_AXI_GP1_WDATA ),
\t .MAXIGP1WID\t (M_AXI_GP1_WID_FULL ),
\t .MAXIGP1WLAST\t (M_AXI_GP1_WLAST ),
\t .MAXIGP1WSTRB\t (M_AXI_GP1_WSTRB ),
\t .MAXIGP1WVALID\t (M_AXI_GP1_WVALID ),
\t .SAXIACPARESETN\t (S_AXI_ACP_ARESETN),
\t .SAXIACPARREADY\t (SAXIACPARREADY_W),
\t .SAXIACPAWREADY\t (SAXIACPAWREADY_W),
\t .SAXIACPBID\t (S_AXI_ACP_BID_out ),
\t .SAXIACPBRESP\t (SAXIACPBRESP_W ),
\t .SAXIACPBVALID\t (SAXIACPBVALID_W ),
\t .SAXIACPRDATA\t (SAXIACPRDATA_W ),
\t .SAXIACPRID\t (S_AXI_ACP_RID_out),
\t .SAXIACPRLAST\t (SAXIACPRLAST_W ),
\t .SAXIACPRRESP\t (SAXIACPRRESP_W ),
\t .SAXIACPRVALID\t (SAXIACPRVALID_W ),
\t .SAXIACPWREADY\t (SAXIACPWREADY_W ),
\t .SAXIGP0ARESETN\t (S_AXI_GP0_ARESETN),
\t .SAXIGP0ARREADY\t (S_AXI_GP0_ARREADY),
\t .SAXIGP0AWREADY\t (S_AXI_GP0_AWREADY),
\t .SAXIGP0BID\t (S_AXI_GP0_BID_out),
\t .SAXIGP0BRESP\t (S_AXI_GP0_BRESP ),
\t .SAXIGP0BVALID\t (S_AXI_GP0_BVALID ),
\t .SAXIGP0RDATA\t (S_AXI_GP0_RDATA ),
\t .SAXIGP0RID\t (S_AXI_GP0_RID_out ),
\t .SAXIGP0RLAST\t (S_AXI_GP0_RLAST ),
\t .SAXIGP0RRESP\t (S_AXI_GP0_RRESP ),
\t .SAXIGP0RVALID\t (S_AXI_GP0_RVALID ),
\t .SAXIGP0WREADY\t (S_AXI_GP0_WREADY ),
\t .SAXIGP1ARESETN\t (S_AXI_GP1_ARESETN),
\t .SAXIGP1ARREADY\t (S_AXI_GP1_ARREADY),
\t .SAXIGP1AWREADY\t (S_AXI_GP1_AWREADY),
\t .SAXIGP1BID\t (S_AXI_GP1_BID_out ),
\t .SAXIGP1BRESP\t (S_AXI_GP1_BRESP ),
\t .SAXIGP1BVALID\t (S_AXI_GP1_BVALID ),
\t .SAXIGP1RDATA\t (S_AXI_GP1_RDATA ),
\t .SAXIGP1RID\t (S_AXI_GP1_RID_out ),
\t .SAXIGP1RLAST\t (S_AXI_GP1_RLAST ),
\t .SAXIGP1RRESP\t (S_AXI_GP1_RRESP ),
\t .SAXIGP1RVALID\t (S_AXI_GP1_RVALID ),
\t .SAXIGP1WREADY\t (S_AXI_GP1_WREADY ),
\t .SAXIHP0ARESETN\t (S_AXI_HP0_ARESETN),
\t .SAXIHP0ARREADY\t (S_AXI_HP0_ARREADY),
\t .SAXIHP0AWREADY\t (S_AXI_HP0_AWREADY),
\t .SAXIHP0BID\t (S_AXI_HP0_BID_out ),
\t .SAXIHP0BRESP\t (S_AXI_HP0_BRESP ),
\t .SAXIHP0BVALID\t (S_AXI_HP0_BVALID ),
\t .SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
\t .SAXIHP0RCOUNT\t (S_AXI_HP0_RCOUNT),
\t .SAXIHP0RDATA\t (S_AXI_HP0_RDATA_out),
\t .SAXIHP0RID\t (S_AXI_HP0_RID_out ),
\t .SAXIHP0RLAST\t (S_AXI_HP0_RLAST),
\t .SAXIHP0RRESP\t (S_AXI_HP0_RRESP),
\t .SAXIHP0RVALID\t (S_AXI_HP0_RVALID),
\t .SAXIHP0WCOUNT\t (S_AXI_HP0_WCOUNT),
\t .SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
\t .SAXIHP0WREADY\t (S_AXI_HP0_WREADY),
\t .SAXIHP1ARESETN\t (S_AXI_HP1_ARESETN),
\t .SAXIHP1ARREADY\t (S_AXI_HP1_ARREADY),
\t .SAXIHP1AWREADY\t (S_AXI_HP1_AWREADY),
\t .SAXIHP1BID\t (S_AXI_HP1_BID_out ),
\t .SAXIHP1BRESP\t (S_AXI_HP1_BRESP ),
\t .SAXIHP1BVALID\t (S_AXI_HP1_BVALID ),
\t .SAXIHP1RACOUNT\t (S_AXI_HP1_RACOUNT ),
\t .SAXIHP1RCOUNT\t (S_AXI_HP1_RCOUNT ),
\t .SAXIHP1RDATA\t (S_AXI_HP1_RDATA_out),
\t .SAXIHP1RID\t (S_AXI_HP1_RID_out ),
\t .SAXIHP1RLAST\t (S_AXI_HP1_RLAST ),
\t .SAXIHP1RRESP\t (S_AXI_HP1_RRESP ),
\t .SAXIHP1RVALID\t (S_AXI_HP1_RVALID),
\t .SAXIHP1WACOUNT\t (S_AXI_HP1_WACOUNT),
\t .SAXIHP1WCOUNT\t (S_AXI_HP1_WCOUNT),
\t .SAXIHP1WREADY\t (S_AXI_HP1_WREADY),
\t .SAXIHP2ARESETN\t (S_AXI_HP2_ARESETN),
\t .SAXIHP2ARREADY\t (S_AXI_HP2_ARREADY),
\t .SAXIHP2AWREADY\t (S_AXI_HP2_AWREADY),
\t .SAXIHP2BID\t (S_AXI_HP2_BID_out ),
\t .SAXIHP2BRESP\t (S_AXI_HP2_BRESP),
\t .SAXIHP2BVALID\t (S_AXI_HP2_BVALID),
\t .SAXIHP2RACOUNT\t (S_AXI_HP2_RACOUNT),
\t .SAXIHP2RCOUNT\t (S_AXI_HP2_RCOUNT),
\t .SAXIHP2RDATA\t (S_AXI_HP2_RDATA_out),
\t .SAXIHP2RID\t (S_AXI_HP2_RID_out ),
\t .SAXIHP2RLAST\t (S_AXI_HP2_RLAST),
\t .SAXIHP2RRESP\t (S_AXI_HP2_RRESP),
\t .SAXIHP2RVALID\t (S_AXI_HP2_RVALID),
\t .SAXIHP2WACOUNT\t (S_AXI_HP2_WACOUNT),
\t .SAXIHP2WCOUNT\t (S_AXI_HP2_WCOUNT),
\t .SAXIHP2WREADY\t (S_AXI_HP2_WREADY),
\t .SAXIHP3ARESETN\t (S_AXI_HP3_ARESETN),
\t .SAXIHP3ARREADY\t (S_AXI_HP3_ARREADY),
\t .SAXIHP3AWREADY\t (S_AXI_HP3_AWREADY),
\t .SAXIHP3BID\t (S_AXI_HP3_BID_out),
\t .SAXIHP3BRESP\t (S_AXI_HP3_BRESP),
\t .SAXIHP3BVALID\t (S_AXI_HP3_BVALID),
\t .SAXIHP3RACOUNT\t (S_AXI_HP3_RACOUNT),
\t .SAXIHP3RCOUNT\t (S_AXI_HP3_RCOUNT),
\t .SAXIHP3RDATA\t (S_AXI_HP3_RDATA_out),
\t .SAXIHP3RID\t (S_AXI_HP3_RID_out),
\t .SAXIHP3RLAST\t (S_AXI_HP3_RLAST),
\t .SAXIHP3RRESP\t (S_AXI_HP3_RRESP),
\t .SAXIHP3RVALID\t (S_AXI_HP3_RVALID),
\t .SAXIHP3WCOUNT\t (S_AXI_HP3_WCOUNT),
\t .SAXIHP3WACOUNT\t (S_AXI_HP3_WACOUNT),
\t .SAXIHP3WREADY\t (S_AXI_HP3_WREADY),
\t .DDRARB (DDR_ARB),
\t .DMA0ACLK\t\t (DMA0_ACLK ),
\t .DMA0DAREADY\t\t (DMA0_DAREADY),
\t .DMA0DRLAST\t\t (DMA0_DRLAST ),
\t .DMA0DRTYPE (DMA0_DRTYPE),
\t .DMA0DRVALID\t\t (DMA0_DRVALID),
\t .DMA1ACLK\t\t (DMA1_ACLK ),
\t .DMA1DAREADY\t\t (DMA1_DAREADY),
\t .DMA1DRLAST\t\t (DMA1_DRLAST ),
\t .DMA1DRTYPE (DMA1_DRTYPE),
\t .DMA1DRVALID\t\t (DMA1_DRVALID),
\t .DMA2ACLK\t\t (DMA2_ACLK ),
\t .DMA2DAREADY\t\t (DMA2_DAREADY),
\t .DMA2DRLAST\t\t (DMA2_DRLAST ),
\t .DMA2DRTYPE (DMA2_DRTYPE),
\t .DMA2DRVALID\t\t (DMA2_DRVALID),
\t .DMA3ACLK\t\t (DMA3_ACLK ),
\t .DMA3DAREADY\t\t (DMA3_DAREADY),
\t .DMA3DRLAST\t\t (DMA3_DRLAST ),
\t .DMA3DRTYPE (DMA3_DRTYPE),
\t .DMA3DRVALID\t\t (DMA3_DRVALID),
\t .EMIOCAN0PHYRX\t (CAN0_PHY_RX),
\t .EMIOCAN1PHYRX\t (CAN1_PHY_RX),
\t .EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
\t .EMIOENET0GMIICOL (ENET0_GMII_COL_i),
\t .EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
\t .EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
\t .EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
\t .EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
\t .EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
\t .EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
\t .EMIOENET0MDIOI (ENET0_MDIO_I),
\t .EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
\t .EMIOENET1GMIICOL (ENET1_GMII_COL_i),
\t .EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
\t .EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
\t .EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
\t .EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
\t .EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
\t .EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
\t .EMIOENET1MDIOI (ENET1_MDIO_I),
\t .EMIOGPIOI\t (gpio_in63_0 ),
\t .EMIOI2C0SCLI\t (I2C0_SCL_I),
\t .EMIOI2C0SDAI\t (I2C0_SDA_I),
\t .EMIOI2C1SCLI\t (I2C1_SCL_I),
\t .EMIOI2C1SDAI\t (I2C1_SDA_I),
\t .EMIOPJTAGTCK\t\t (PJTAG_TCK),
\t .EMIOPJTAGTDI\t\t (PJTAG_TDI),
\t .EMIOPJTAGTMS\t\t (PJTAG_TMS),
\t .EMIOSDIO0CDN (SDIO0_CDN),
\t .EMIOSDIO0CLKFB\t (SDIO0_CLK_FB ),
\t .EMIOSDIO0CMDI\t (SDIO0_CMD_I ),
\t .EMIOSDIO0DATAI\t (SDIO0_DATA_I ),
\t .EMIOSDIO0WP (SDIO0_WP),
\t .EMIOSDIO1CDN (SDIO1_CDN),
\t .EMIOSDIO1CLKFB\t (SDIO1_CLK_FB ),
\t .EMIOSDIO1CMDI\t (SDIO1_CMD_I ),
\t .EMIOSDIO1DATAI\t (SDIO1_DATA_I ),
\t .EMIOSDIO1WP (SDIO1_WP),
\t .EMIOSPI0MI\t\t (SPI0_MISO_I),
\t .EMIOSPI0SCLKI\t (SPI0_SCLK_I),
\t .EMIOSPI0SI\t\t (SPI0_MOSI_I),
\t .EMIOSPI0SSIN \t (SPI0_SS_I),
\t .EMIOSPI1MI\t\t (SPI1_MISO_I),
\t .EMIOSPI1SCLKI\t (SPI1_SCLK_I),
\t .EMIOSPI1SI\t\t (SPI1_MOSI_I),
\t .EMIOSPI1SSIN\t (SPI1_SS_I),
\t .EMIOSRAMINTIN (SRAM_INTIN),
\t .EMIOTRACECLK\t\t (TRACE_CLK),
\t .EMIOTTC0CLKI\t ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
\t .EMIOTTC1CLKI\t ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
\t .EMIOUART0CTSN\t (UART0_CTSN),
\t .EMIOUART0DCDN\t (UART0_DCDN),
\t .EMIOUART0DSRN\t (UART0_DSRN),
\t .EMIOUART0RIN\t\t (UART0_RIN ),
\t .EMIOUART0RX\t\t (UART0_RX ),
\t .EMIOUART1CTSN\t (UART1_CTSN),
\t .EMIOUART1DCDN\t (UART1_DCDN),
\t .EMIOUART1DSRN\t (UART1_DSRN),
\t .EMIOUART1RIN\t\t (UART1_RIN ),
\t .EMIOUART1RX\t\t (UART1_RX ),
\t .EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
\t .EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
\t .EMIOWDTCLKI\t\t (WDT_CLK_IN),
\t .EVENTEVENTI (EVENT_EVENTI),
\t .FCLKCLKTRIGN\t\t (fclk_clktrig_gnd),
\t .FPGAIDLEN\t\t (FPGA_IDLE_N),
\t .FTMDTRACEINATID\t (FTMD_TRACEIN_ATID_i),
\t .FTMDTRACEINCLOCK\t (FTMD_TRACEIN_CLK),
\t .FTMDTRACEINDATA\t (FTMD_TRACEIN_DATA_i),
\t .FTMDTRACEINVALID\t (FTMD_TRACEIN_VALID_i),
\t .FTMTF2PDEBUG\t\t (FTMT_F2P_DEBUG ),
\t .FTMTF2PTRIG\t\t ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
\t .FTMTP2FTRIGACK\t ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
\t .IRQF2P\t\t (irq_f2p_i),
\t .MAXIGP0ACLK\t (M_AXI_GP0_ACLK),
\t .MAXIGP0ARREADY\t (M_AXI_GP0_ARREADY),
\t .MAXIGP0AWREADY\t (M_AXI_GP0_AWREADY),
\t .MAXIGP0BID\t (M_AXI_GP0_BID_FULL ),
\t .MAXIGP0BRESP\t (M_AXI_GP0_BRESP ),
\t .MAXIGP0BVALID\t (M_AXI_GP0_BVALID ),
\t .MAXIGP0RDATA\t (M_AXI_GP0_RDATA ),
\t .MAXIGP0RID\t (M_AXI_GP0_RID_FULL ),
\t .MAXIGP0RLAST\t (M_AXI_GP0_RLAST ),
\t .MAXIGP0RRESP\t (M_AXI_GP0_RRESP ),
\t .MAXIGP0RVALID\t (M_AXI_GP0_RVALID ),
\t .MAXIGP0WREADY\t (M_AXI_GP0_WREADY ),
\t .MAXIGP1ACLK\t (M_AXI_GP1_ACLK ),
\t .MAXIGP1ARREADY\t (M_AXI_GP1_ARREADY),
\t .MAXIGP1AWREADY\t (M_AXI_GP1_AWREADY),
\t .MAXIGP1BID\t (M_AXI_GP1_BID_FULL ),
\t .MAXIGP1BRESP\t (M_AXI_GP1_BRESP ),
\t .MAXIGP1BVALID\t (M_AXI_GP1_BVALID ),
\t .MAXIGP1RDATA\t (M_AXI_GP1_RDATA ),
\t .MAXIGP1RID\t (M_AXI_GP1_RID_FULL ),
\t .MAXIGP1RLAST\t (M_AXI_GP1_RLAST ),
\t .MAXIGP1RRESP\t (M_AXI_GP1_RRESP ),
\t .MAXIGP1RVALID\t (M_AXI_GP1_RVALID ),
\t .MAXIGP1WREADY\t (M_AXI_GP1_WREADY ),
\t .SAXIACPACLK\t (S_AXI_ACP_ACLK ),
\t .SAXIACPARADDR\t (SAXIACPARADDR_W ),
\t .SAXIACPARBURST\t (SAXIACPARBURST_W),
\t .SAXIACPARCACHE\t (SAXIACPARCACHE_W),
\t .SAXIACPARID\t (S_AXI_ACP_ARID_in ),
\t .SAXIACPARLEN\t (SAXIACPARLEN_W ),
\t .SAXIACPARLOCK\t (SAXIACPARLOCK_W ),
\t .SAXIACPARPROT\t (SAXIACPARPROT_W ),
\t .SAXIACPARQOS\t (S_AXI_ACP_ARQOS ),
\t .SAXIACPARSIZE\t (SAXIACPARSIZE_W[1:0] ),
\t .SAXIACPARUSER\t (SAXIACPARUSER_W ),
\t .SAXIACPARVALID\t (SAXIACPARVALID_W),
\t .SAXIACPAWADDR\t (SAXIACPAWADDR_W ),
\t .SAXIACPAWBURST\t (SAXIACPAWBURST_W),
\t .SAXIACPAWCACHE\t (SAXIACPAWCACHE_W),
\t .SAXIACPAWID\t (S_AXI_ACP_AWID_in ),
\t .SAXIACPAWLEN\t (SAXIACPAWLEN_W ),
\t .SAXIACPAWLOCK\t (SAXIACPAWLOCK_W ),
\t .SAXIACPAWPROT\t (SAXIACPAWPROT_W ),
\t .SAXIACPAWQOS\t (S_AXI_ACP_AWQOS ),
\t .SAXIACPAWSIZE\t (SAXIACPAWSIZE_W[1:0] ),
\t .SAXIACPAWUSER\t (SAXIACPAWUSER_W ),
\t .SAXIACPAWVALID\t (SAXIACPAWVALID_W),
\t .SAXIACPBREADY\t (SAXIACPBREADY_W ),
\t .SAXIACPRREADY\t (SAXIACPRREADY_W ),
\t .SAXIACPWDATA\t (SAXIACPWDATA_W ),
\t .SAXIACPWID\t (S_AXI_ACP_WID_in ),
\t .SAXIACPWLAST\t (SAXIACPWLAST_W ),
\t .SAXIACPWSTRB\t (SAXIACPWSTRB_W ),
\t .SAXIACPWVALID\t (SAXIACPWVALID_W ),
\t .SAXIGP0ACLK (S_AXI_GP0_ACLK ),
\t .SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
\t .SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
\t .SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
\t .SAXIGP0ARID (S_AXI_GP0_ARID_in ),
\t .SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
\t .SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
\t .SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
\t .SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
\t .SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
\t .SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
\t .SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
\t .SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
\t .SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
\t .SAXIGP0AWID (S_AXI_GP0_AWID_in ),
\t .SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
\t .SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
\t .SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
\t .SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
\t .SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
\t .SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
\t .SAXIGP0BREADY (S_AXI_GP0_BREADY ),
\t .SAXIGP0RREADY (S_AXI_GP0_RREADY ),
\t .SAXIGP0WDATA (S_AXI_GP0_WDATA ),
\t .SAXIGP0WID (S_AXI_GP0_WID_in ),
\t .SAXIGP0WLAST (S_AXI_GP0_WLAST ),
\t .SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
\t .SAXIGP0WVALID (S_AXI_GP0_WVALID ),
\t .SAXIGP1ACLK\t (S_AXI_GP1_ACLK ),
\t .SAXIGP1ARADDR\t (S_AXI_GP1_ARADDR ),
\t .SAXIGP1ARBURST\t (S_AXI_GP1_ARBURST),
\t .SAXIGP1ARCACHE\t (S_AXI_GP1_ARCACHE),
\t .SAXIGP1ARID\t (S_AXI_GP1_ARID_in ),
\t .SAXIGP1ARLEN\t (S_AXI_GP1_ARLEN ),
\t .SAXIGP1ARLOCK\t (S_AXI_GP1_ARLOCK ),
\t .SAXIGP1ARPROT\t (S_AXI_GP1_ARPROT ),
\t .SAXIGP1ARQOS\t (S_AXI_GP1_ARQOS ),
\t .SAXIGP1ARSIZE\t (S_AXI_GP1_ARSIZE[1:0] ),
\t .SAXIGP1ARVALID\t (S_AXI_GP1_ARVALID),
\t .SAXIGP1AWADDR\t (S_AXI_GP1_AWADDR ),
\t .SAXIGP1AWBURST\t (S_AXI_GP1_AWBURST),
\t .SAXIGP1AWCACHE\t (S_AXI_GP1_AWCACHE),
\t .SAXIGP1AWID\t (S_AXI_GP1_AWID_in ),
\t .SAXIGP1AWLEN\t (S_AXI_GP1_AWLEN ),
\t .SAXIGP1AWLOCK\t (S_AXI_GP1_AWLOCK ),
\t .SAXIGP1AWPROT\t (S_AXI_GP1_AWPROT ),
\t .SAXIGP1AWQOS\t (S_AXI_GP1_AWQOS ),
\t .SAXIGP1AWSIZE\t (S_AXI_GP1_AWSIZE[1:0] ),
\t .SAXIGP1AWVALID\t (S_AXI_GP1_AWVALID),
\t .SAXIGP1BREADY\t (S_AXI_GP1_BREADY ),
\t .SAXIGP1RREADY\t (S_AXI_GP1_RREADY ),
\t .SAXIGP1WDATA\t (S_AXI_GP1_WDATA ),
\t .SAXIGP1WID\t (S_AXI_GP1_WID_in ),
\t .SAXIGP1WLAST\t (S_AXI_GP1_WLAST ),
\t .SAXIGP1WSTRB\t (S_AXI_GP1_WSTRB ),
\t .SAXIGP1WVALID\t (S_AXI_GP1_WVALID ),
\t .SAXIHP0ACLK (S_AXI_HP0_ACLK ),
\t .SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
\t .SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
\t .SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
\t .SAXIHP0ARID (S_AXI_HP0_ARID_in),
\t .SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
\t .SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
\t .SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
\t .SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
\t .SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
\t .SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
\t .SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
\t .SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
\t .SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
\t .SAXIHP0AWID (S_AXI_HP0_AWID_in),
\t .SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
\t .SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
\t .SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
\t .SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
\t .SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
\t .SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
\t .SAXIHP0BREADY (S_AXI_HP0_BREADY),
\t .SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
\t .SAXIHP0RREADY (S_AXI_HP0_RREADY),
\t .SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
\t .SAXIHP0WID (S_AXI_HP0_WID_in),
\t .SAXIHP0WLAST (S_AXI_HP0_WLAST),
\t .SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
\t .SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
\t .SAXIHP0WVALID (S_AXI_HP0_WVALID),
\t .SAXIHP1ACLK (S_AXI_HP1_ACLK),
\t .SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
\t .SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
\t .SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
\t .SAXIHP1ARID (S_AXI_HP1_ARID_in),
\t .SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
\t .SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
\t .SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
\t .SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
\t .SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
\t .SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
\t .SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
\t .SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
\t .SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
\t .SAXIHP1AWID (S_AXI_HP1_AWID_in),
\t .SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
\t .SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
\t .SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
\t .SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
\t .SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
\t .SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
\t .SAXIHP1BREADY (S_AXI_HP1_BREADY),
\t .SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
\t .SAXIHP1RREADY (S_AXI_HP1_RREADY),
\t .SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
\t .SAXIHP1WID (S_AXI_HP1_WID_in),
\t .SAXIHP1WLAST (S_AXI_HP1_WLAST),
\t .SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
\t .SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
\t .SAXIHP1WVALID (S_AXI_HP1_WVALID),
\t .SAXIHP2ACLK (S_AXI_HP2_ACLK),
\t .SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
\t .SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
\t .SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
\t .SAXIHP2ARID (S_AXI_HP2_ARID_in),
\t .SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
\t .SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
\t .SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
\t .SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
\t .SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
\t .SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
\t .SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
\t .SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
\t .SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
\t .SAXIHP2AWID (S_AXI_HP2_AWID_in),
\t .SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
\t .SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
\t .SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
\t .SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
\t .SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
\t .SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
\t .SAXIHP2BREADY (S_AXI_HP2_BREADY),
\t .SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
\t .SAXIHP2RREADY (S_AXI_HP2_RREADY),
\t .SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
\t .SAXIHP2WID (S_AXI_HP2_WID_in),
\t .SAXIHP2WLAST (S_AXI_HP2_WLAST),
\t .SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
\t .SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
\t .SAXIHP2WVALID (S_AXI_HP2_WVALID),
\t .SAXIHP3ACLK (S_AXI_HP3_ACLK),
\t .SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
\t .SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
\t .SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
\t .SAXIHP3ARID (S_AXI_HP3_ARID_in ),
\t .SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
\t .SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
\t .SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
\t .SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
\t .SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
\t .SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
\t .SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
\t .SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
\t .SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
\t .SAXIHP3AWID (S_AXI_HP3_AWID_in),
\t .SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
\t .SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
\t .SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
\t .SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
\t .SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
\t .SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
\t .SAXIHP3BREADY (S_AXI_HP3_BREADY),
\t .SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
\t .SAXIHP3RREADY (S_AXI_HP3_RREADY),
\t .SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
\t .SAXIHP3WID (S_AXI_HP3_WID_in),
\t .SAXIHP3WLAST (S_AXI_HP3_WLAST),
\t .SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
\t .SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
\t .SAXIHP3WVALID (S_AXI_HP3_WVALID),
\t .DDRA\t\t (buffered_DDR_Addr),
\t .DDRBA\t\t (buffered_DDR_BankAddr),
\t .DDRCASB\t\t (buffered_DDR_CAS_n),
\t .DDRCKE\t\t (buffered_DDR_CKE),
\t .DDRCKN\t\t (buffered_DDR_Clk_n),
\t .DDRCKP\t\t (buffered_DDR_Clk),
\t .DDRCSB\t\t (buffered_DDR_CS_n),
\t .DDRDM\t\t (buffered_DDR_DM),
\t .DDRDQ\t\t (buffered_DDR_DQ),
\t .DDRDQSN\t\t (buffered_DDR_DQS_n),
\t .DDRDQSP\t\t (buffered_DDR_DQS),
\t .DDRDRSTB (buffered_DDR_DRSTB),
\t .DDRODT\t\t (buffered_DDR_ODT),
\t .DDRRASB\t\t (buffered_DDR_RAS_n),
\t .DDRVRN (buffered_DDR_VRN),
\t .DDRVRP (buffered_DDR_VRP),
\t .DDRWEB (buffered_DDR_WEB),
\t .MIO\t\t\t (buffered_MIO),
\t .PSCLK\t\t (buffered_PS_CLK),
\t .PSPORB\t\t (buffered_PS_PORB),
\t .PSSRSTB\t\t (buffered_PS_SRSTB)
\t
\t);
\t
end
endgenerate
// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
// Otherwise a master connected to the ACP port will drive the AxUSER Ports
assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR;
assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN;
assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK;
assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT;
assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE;
//assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER;
assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser;
assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR;
assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN;
assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK;
assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT;
assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE;
//assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER;
assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser;
assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY;
assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY;
assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA;
assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST;
assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB;
assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID;
assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID;
assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID;
assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID;
generate
if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W;
assign S_AXI_ACP_WREADY = SAXIACPWREADY_W;
assign S_AXI_ACP_BID = SAXIACPBID_W;
assign S_AXI_ACP_BRESP = SAXIACPBRESP_W;
assign S_AXI_ACP_BVALID = SAXIACPBVALID_W;
assign S_AXI_ACP_RDATA =\t SAXIACPRDATA_W;
assign S_AXI_ACP_RID =\t SAXIACPRID_W;
assign S_AXI_ACP_RLAST =\t SAXIACPRLAST_W;
assign S_AXI_ACP_RRESP =\t SAXIACPRRESP_W;
assign S_AXI_ACP_RVALID =\t SAXIACPRVALID_W;
assign S_AXI_ACP_ARREADY =\t SAXIACPARREADY_W;
end else begin : gen_atc
processing_system7_v5_5_atc #(
.C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH),
.C_AXI_AWUSER_WIDTH (5),
.C_AXI_ARUSER_WIDTH (5)
)
atc_i (
// Global Signals
.ACLK (S_AXI_ACP_ACLK),
.ARESETN (S_AXI_ACP_ARESETN),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_ACP_AWID),
.S_AXI_AWADDR (S_AXI_ACP_AWADDR),
.S_AXI_AWLEN (S_AXI_ACP_AWLEN),
.S_AXI_AWSIZE (S_AXI_ACP_AWSIZE),
.S_AXI_AWBURST (S_AXI_ACP_AWBURST),
.S_AXI_AWLOCK (S_AXI_ACP_AWLOCK),
.S_AXI_AWCACHE (S_AXI_ACP_AWCACHE),
.S_AXI_AWPROT (S_AXI_ACP_AWPROT),
//.S_AXI_AWUSER (S_AXI_ACP_AWUSER),
.S_AXI_AWUSER (param_awuser),
.S_AXI_AWVALID (S_AXI_ACP_AWVALID),
.S_AXI_AWREADY (S_AXI_ACP_AWREADY),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_ACP_WID),
.S_AXI_WDATA (S_AXI_ACP_WDATA),
.S_AXI_WSTRB (S_AXI_ACP_WSTRB),
.S_AXI_WLAST (S_AXI_ACP_WLAST),
.S_AXI_WUSER (),
.S_AXI_WVALID (S_AXI_ACP_WVALID),
.S_AXI_WREADY (S_AXI_ACP_WREADY),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_ACP_BID),
.S_AXI_BRESP (S_AXI_ACP_BRESP),
.S_AXI_BUSER (),
.S_AXI_BVALID (S_AXI_ACP_BVALID),
.S_AXI_BREADY (S_AXI_ACP_BREADY),
// Slave Interface Read Address Ports
.S_AXI_ARID (S_AXI_ACP_ARID),
.S_AXI_ARADDR (S_AXI_ACP_ARADDR),
.S_AXI_ARLEN (S_AXI_ACP_ARLEN),
.S_AXI_ARSIZE (S_AXI_ACP_ARSIZE),
.S_AXI_ARBURST (S_AXI_ACP_ARBURST),
.S_AXI_ARLOCK (S_AXI_ACP_ARLOCK),
.S_AXI_ARCACHE (S_AXI_ACP_ARCACHE),
.S_AXI_ARPROT (S_AXI_ACP_ARPROT),
//.S_AXI_ARUSER (S_AXI_ACP_ARUSER),
.S_AXI_ARUSER (param_aruser),
.S_AXI_ARVALID (S_AXI_ACP_ARVALID),
.S_AXI_ARREADY (S_AXI_ACP_ARREADY),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_ACP_RID),
.S_AXI_RDATA (S_AXI_ACP_RDATA),
.S_AXI_RRESP (S_AXI_ACP_RRESP),
.S_AXI_RLAST (S_AXI_ACP_RLAST),
.S_AXI_RUSER (),
.S_AXI_RVALID (S_AXI_ACP_RVALID),
.S_AXI_RREADY (S_AXI_ACP_RREADY),
// Slave Interface Write Address Ports
.M_AXI_AWID (S_AXI_ATC_AWID),
.M_AXI_AWADDR (S_AXI_ATC_AWADDR),
.M_AXI_AWLEN (S_AXI_ATC_AWLEN),
.M_AXI_AWSIZE (S_AXI_ATC_AWSIZE),
.M_AXI_AWBURST (S_AXI_ATC_AWBURST),
.M_AXI_AWLOCK (S_AXI_ATC_AWLOCK),
.M_AXI_AWCACHE (S_AXI_ATC_AWCACHE),
.M_AXI_AWPROT (S_AXI_ATC_AWPROT),
.M_AXI_AWUSER (S_AXI_ATC_AWUSER),
.M_AXI_AWVALID (S_AXI_ATC_AWVALID),
.M_AXI_AWREADY (SAXIACPAWREADY_W),
// Slave Interface Write Data Ports
.M_AXI_WID (S_AXI_ATC_WID),
.M_AXI_WDATA (S_AXI_ATC_WDATA),
.M_AXI_WSTRB (S_AXI_ATC_WSTRB),
.M_AXI_WLAST (S_AXI_ATC_WLAST),
.M_AXI_WUSER (),
.M_AXI_WVALID (S_AXI_ATC_WVALID),
.M_AXI_WREADY (SAXIACPWREADY_W),
// Slave Interface Write Response Ports
.M_AXI_BID (SAXIACPBID_W),
.M_AXI_BRESP (SAXIACPBRESP_W),
.M_AXI_BUSER (),
.M_AXI_BVALID (SAXIACPBVALID_W),
.M_AXI_BREADY (S_AXI_ATC_BREADY),
// Slave Interface Read Address Ports
.M_AXI_ARID (S_AXI_ATC_ARID),
.M_AXI_ARADDR (S_AXI_ATC_ARADDR),
.M_AXI_ARLEN (S_AXI_ATC_ARLEN),
.M_AXI_ARSIZE (S_AXI_ATC_ARSIZE),
.M_AXI_ARBURST (S_AXI_ATC_ARBURST),
.M_AXI_ARLOCK (S_AXI_ATC_ARLOCK),
.M_AXI_ARCACHE (S_AXI_ATC_ARCACHE),
.M_AXI_ARPROT (S_AXI_ATC_ARPROT),
.M_AXI_ARUSER (S_AXI_ATC_ARUSER),
.M_AXI_ARVALID (S_AXI_ATC_ARVALID),
.M_AXI_ARREADY (SAXIACPARREADY_W),
// Slave Interface Read Data Ports
.M_AXI_RID (SAXIACPRID_W),
.M_AXI_RDATA (SAXIACPRDATA_W),
.M_AXI_RRESP (SAXIACPRRESP_W),
.M_AXI_RLAST (SAXIACPRLAST_W),
.M_AXI_RUSER (),
.M_AXI_RVALID (SAXIACPRVALID_W),
.M_AXI_RREADY (S_AXI_ATC_RREADY),
.ERROR_TRIGGER(),
.ERROR_TRANSACTION_ID()
);
end
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized AND with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_carry_latch_and #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign O = CIN & ~I;
end else begin : USE_FPGA
wire I_n;
assign I_n = ~I;
AND2B1L and2b1l_inst
(
.O(O),
.DI(CIN),
.SRI(I_n)
);
end
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2\'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2\'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2\'b10;
localparam [2-1:0] C_RESP_DECERR = 2\'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1\'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1\'b0;
cmd_b_valid <= 1\'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1\'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1\'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1\'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1\'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1\'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1\'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1\'b0}};
M_AXI_BRESP_I <= 2\'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1\'b0}};
M_AXI_BVALID_I <= 1\'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1\'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1\'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1\'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1\'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1\'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1\'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_arb_wr.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between 2 write requests from 2 ports.
*
*****************************************************************************/
module processing_system7_bfm_v2_0_arb_wr(
rstn,
sw_clk,
qos1,
qos2,
prt_dv1,
prt_dv2,
prt_data1,
prt_data2,
prt_addr1,
prt_addr2,
prt_bytes1,
prt_bytes2,
prt_ack1,
prt_ack2,
prt_qos,
prt_req,
prt_data,
prt_addr,
prt_bytes,
prt_ack
);
`include "processing_system7_bfm_v2_0_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2;
input [max_burst_bits-1:0] prt_data1,prt_data2;
input [addr_width-1:0] prt_addr1,prt_addr2;
input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2;
input prt_dv1, prt_dv2, prt_ack;
output reg prt_ack1,prt_ack2,prt_req;
output reg [max_burst_bits-1:0] prt_data;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
output reg [axi_qos_width-1:0] prt_qos;
parameter wait_req = 2\'b00, serv_req1 = 2\'b01, serv_req2 = 2\'b10,wait_ack_low = 2\'b11;
reg [1:0] state,temp_state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1\'b0;
prt_ack1 = 1\'b0;
prt_ack2 = 1\'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_ack1 = 1\'b0;
prt_ack2 = 1\'b0;
prt_req = 1\'b0;
if(prt_dv1 && !prt_dv2) begin
state = serv_req1;
prt_req = 1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
prt_qos = qos1;
end else if(!prt_dv1 && prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv1 && prt_dv2) begin
if(qos1 > qos2) begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else if(qos1 < qos2) begin
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req1:begin
state = serv_req1;
prt_ack2 = 1\'b0;
if(prt_ack) begin
prt_ack1 = 1\'b1;
prt_req = 0;
if(prt_dv2) begin
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
// state = wait_req;
state = wait_ack_low;
end
end
end
serv_req2:begin
state = serv_req2;
prt_ack1 = 1\'b0;
if(prt_ack) begin
prt_ack2 = 1\'b1;
prt_req = 0;
if(prt_dv1) begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else begin
state = wait_ack_low;
// state = wait_req;
end
end
end
wait_ack_low:begin
prt_ack1 = 1\'b0;
prt_ack2 = 1\'b0;
state = wait_ack_low;
if(!prt_ack)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: addr_arbiter.v
//
// Description:
// Instantiates generic priority encoder.
// Each request is qualified if its target has not reached its issuing limit.
// Muxes mesg and target inputs based on arbitration results.
//-----------------------------------------------------------------------------
//
// Structure:
// addr_arbiter
// mux_enc
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_addr_arbiter #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_S = 1,
parameter integer C_NUM_S_LOG = 1,
parameter integer C_NUM_M = 1,
parameter integer C_MESG_WIDTH = 1,
parameter [C_NUM_S*32-1:0] C_ARB_PRIORITY = {C_NUM_S{32\'h00000000}}
// Arbitration priority among each SI slot.
// Higher values indicate higher priority.
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: \'h0-\'hF.
)
(
// Global Signals
input wire ACLK,
input wire ARESET,
// Slave Ports
input wire [C_NUM_S*C_MESG_WIDTH-1:0] S_MESG,
input wire [C_NUM_S*C_NUM_M-1:0] S_TARGET_HOT,
input wire [C_NUM_S-1:0] S_VALID,
input wire [C_NUM_S-1:0] S_VALID_QUAL,
output wire [C_NUM_S-1:0] S_READY,
// Master Ports
output wire [C_MESG_WIDTH-1:0] M_MESG,
output wire [C_NUM_M-1:0] M_TARGET_HOT,
output wire [C_NUM_S_LOG-1:0] M_GRANT_ENC,
output wire M_VALID,
input wire M_READY,
// Sideband input
input wire [C_NUM_M-1:0] ISSUING_LIMIT
);
// Generates a mask for all input slots that are priority based
function [C_NUM_S-1:0] f_prio_mask
(
input integer null_arg
);
reg [C_NUM_S-1:0] mask;
integer i;
begin
mask = 0;
for (i=0; i < C_NUM_S; i=i+1) begin
mask[i] = (C_ARB_PRIORITY[i*32+:32] != 0);
end
f_prio_mask = mask;
end
endfunction
// Convert 16-bit one-hot to 4-bit binary
function [3:0] f_hot2enc
(
input [15:0] one_hot
);
begin
f_hot2enc[0] = |(one_hot & 16\'b1010101010101010);
f_hot2enc[1] = |(one_hot & 16\'b1100110011001100);
f_hot2enc[2] = |(one_hot & 16\'b1111000011110000);
f_hot2enc[3] = |(one_hot & 16\'b1111111100000000);
end
endfunction
localparam [C_NUM_S-1:0] P_PRIO_MASK = f_prio_mask(0);
reg m_valid_i;
reg [C_NUM_S-1:0] s_ready_i;
reg [C_NUM_S-1:0] qual_reg;
reg [C_NUM_S-1:0] grant_hot;
reg [C_NUM_S-1:0] last_rr_hot;
reg any_grant;
reg any_prio;
reg found_prio;
reg [C_NUM_S-1:0] which_prio_hot;
reg [C_NUM_S-1:0] next_prio_hot;
reg [C_NUM_S_LOG-1:0] which_prio_enc;
reg [C_NUM_S_LOG-1:0] next_prio_enc;
reg [4:0] current_highest;
wire [C_NUM_S-1:0] valid_rr;
reg [15:0] next_rr_hot;
reg [C_NUM_S_LOG-1:0] next_rr_enc;
reg [C_NUM_S*C_NUM_S-1:0] carry_rr;
reg [C_NUM_S*C_NUM_S-1:0] mask_rr;
reg found_rr;
wire [C_NUM_S-1:0] next_hot;
wire [C_NUM_S_LOG-1:0] next_enc;
reg prio_stall;
integer i;
wire [C_NUM_S-1:0] valid_qual_i;
reg [C_NUM_S_LOG-1:0] m_grant_enc_i;
reg [C_NUM_M-1:0] m_target_hot_i;
wire [C_NUM_M-1:0] m_target_hot_mux;
reg [C_MESG_WIDTH-1:0] m_mesg_i;
wire [C_MESG_WIDTH-1:0] m_mesg_mux;
genvar gen_si;
assign M_VALID = m_valid_i;
assign S_READY = s_ready_i;
assign M_GRANT_ENC = m_grant_enc_i;
assign M_MESG = m_mesg_i;
assign M_TARGET_HOT = m_target_hot_i;
generate
if (C_NUM_S>1) begin : gen_arbiter
always @(posedge ACLK) begin
if (ARESET) begin
qual_reg <= 0;
end else begin
qual_reg <= valid_qual_i | ~S_VALID; // Don\'t disqualify when bus not VALID (valid_qual_i would be garbage)
end
end
for (gen_si=0; gen_si<C_NUM_S; gen_si=gen_si+1) begin : gen_req_qual
assign valid_qual_i[gen_si] = S_VALID_QUAL[gen_si] & (|(S_TARGET_HOT[gen_si*C_NUM_M+:C_NUM_M] & ~ISSUING_LIMIT));
end
/////////////////////////////////////////////////////////////////////////////
// Grant a new request when there is none still pending.
// If no qualified requests found, de-assert M_VALID.
/////////////////////////////////////////////////////////////////////////////
assign next_hot = found_prio ? next_prio_hot : next_rr_hot;
assign next_enc = found_prio ? next_prio_enc : next_rr_enc;
always @(posedge ACLK) begin
if (ARESET) begin
m_valid_i <= 0;
s_ready_i <= 0;
grant_hot <= 0;
any_grant <= 1\'b0;
m_grant_enc_i <= 0;
last_rr_hot <= {1\'b1, {C_NUM_S-1{1\'b0}}};
m_target_hot_i <= 0;
end else begin
s_ready_i <= 0;
if (m_valid_i) begin
// Stall 1 cycle after each master-side completion.
if (M_READY) begin // Master-side completion
m_valid_i <= 1\'b0;
grant_hot <= 0;
any_grant <= 1\'b0;
end
end else if (any_grant) begin
m_valid_i <= 1\'b1;
s_ready_i <= grant_hot; // Assert S_AW/READY for 1 cycle to complete SI address transfer (regardless of M_AREADY)
end else begin
if ((found_prio | found_rr) & ~prio_stall) begin
// Waste 1 cycle and re-arbitrate if target of highest prio hit issuing limit in previous cycle (valid_qual_i).
if (|(next_hot & valid_qual_i)) begin
grant_hot <= next_hot;
m_grant_enc_i <= next_enc;
any_grant <= 1\'b1;
if (~found_prio) begin
last_rr_hot <= next_rr_hot;
end
m_target_hot_i <= m_target_hot_mux;
end
end
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Fixed Priority arbiter
// Selects next request to grant from among inputs with PRIO > 0, if any.
/////////////////////////////////////////////////////////////////////////////
always @ * begin : ALG_PRIO
integer ip;
any_prio = 1\'b0;
prio_stall = 1\'b0;
which_prio_hot = 0;
which_prio_enc = 0;
current_highest = 0;
for (ip=0; ip < C_NUM_S; ip=ip+1) begin
// Disqualify slot if target hit issuing limit (pass to lower prio slot).
if (P_PRIO_MASK[ip] & S_VALID[ip] & qual_reg[ip]) begin
if ({1\'b0, C_ARB_PRIORITY[ip*32+:4]} > current_highest) begin
current_highest[0+:4] = C_ARB_PRIORITY[ip*32+:4];
// Stall 1 cycle when highest prio is recovering from SI-side handshake.
// (Do not allow lower-prio slot to win arbitration.)
if (s_ready_i[ip]) begin
any_prio = 1\'b0;
prio_stall = 1\'b1;
which_prio_hot = 0;
which_prio_enc = 0;
end else begin
any_prio = 1\'b1;
which_prio_hot = 1\'b1 << ip;
which_prio_enc = ip;
end
end
end
end
found_prio = any_prio;
next_prio_hot = which_prio_hot;
next_prio_enc = which_prio_enc;
end
/////////////////////////////////////////////////////////////////////////////
// Round-robin arbiter
// Selects next request to grant from among inputs with PRIO = 0, if any.
/////////////////////////////////////////////////////////////////////////////
// Disqualify slot if target hit issuing limit 2 or more cycles earlier (pass to next RR slot).
// Disqualify for 1 cycle a slot that is recovering from SI-side handshake (s_ready_i),
// and allow arbitration to pass to any other RR requester.
assign valid_rr = ~P_PRIO_MASK & S_VALID & ~s_ready_i & qual_reg;
always @ * begin : ALG_RR
integer ir, jr, nr;
next_rr_hot = 0;
for (ir=0;ir<C_NUM_S;ir=ir+1) begin
nr = (ir>0) ? (ir-1) : (C_NUM_S-1);
carry_rr[ir*C_NUM_S] = last_rr_hot[nr];
mask_rr[ir*C_NUM_S] = ~valid_rr[nr];
for (jr=1;jr<C_NUM_S;jr=jr+1) begin
nr = (ir-jr > 0) ? (ir-jr-1) : (C_NUM_S+ir-jr-1);
carry_rr[ir*C_NUM_S+jr] = carry_rr[ir*C_NUM_S+jr-1] | (last_rr_hot[nr] & mask_rr[ir*C_NUM_S+jr-1]);
if (jr < C_NUM_S-1) begin
mask_rr[ir*C_NUM_S+jr] = mask_rr[ir*C_NUM_S+jr-1] & ~valid_rr[nr];
end
end
next_rr_hot[ir] = valid_rr[ir] & carry_rr[(ir+1)*C_NUM_S-1];
end
next_rr_enc = f_hot2enc(next_rr_hot);
found_rr = |(next_rr_hot);
end
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (C_NUM_S),
.C_SEL_WIDTH (C_NUM_S_LOG),
.C_DATA_WIDTH (C_MESG_WIDTH)
) mux_mesg
(
.S (m_grant_enc_i),
.A (S_MESG),
.O (m_mesg_mux),
.OE (1\'b1)
);
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (C_NUM_S),
.C_SEL_WIDTH (C_NUM_S_LOG),
.C_DATA_WIDTH (C_NUM_M)
) si_amesg_mux_inst
(
.S (next_enc),
.A (S_TARGET_HOT),
.O (m_target_hot_mux),
.OE (1\'b1)
);
always @(posedge ACLK) begin
if (ARESET) begin
m_mesg_i <= 0;
end else if (~m_valid_i) begin
m_mesg_i <= m_mesg_mux;
end
end
end else begin : gen_no_arbiter
assign valid_qual_i = S_VALID_QUAL & |(S_TARGET_HOT & ~ISSUING_LIMIT);
always @ (posedge ACLK) begin
if (ARESET) begin
m_valid_i <= 1\'b0;
s_ready_i <= 1\'b0;
m_grant_enc_i <= 0;
end else begin
s_ready_i <= 1\'b0;
if (m_valid_i) begin
if (M_READY) begin
m_valid_i <= 1\'b0;
end
end else if (S_VALID[0] & valid_qual_i[0] & ~s_ready_i) begin
m_valid_i <= 1\'b1;
s_ready_i <= 1\'b1;
m_target_hot_i <= S_TARGET_HOT;
end
end
end
always @(posedge ACLK) begin
if (ARESET) begin
m_mesg_i <= 0;
end else if (~m_valid_i) begin
m_mesg_i <= S_MESG;
end
end
end // gen_arbiter
endgenerate
endmodule
`default_nettype wire
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: ACP Transaction Checker
//
// Check for optimized ACP transactions and flag if they are broken.
//
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// atc
// aw_atc
// w_atc
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule
`default_nettype wire
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: nto1_mux.v
//
// Description: N:1 MUX based on either binary-encoded or one-hot select input
// One-hot mode does not protect against multiple active SEL_ONEHOT inputs.
// Note: All port signals changed to all-upper-case (w.r.t. prior version).
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_nto1_mux #
(
parameter integer C_RATIO = 1, // Range: >=1
parameter integer C_SEL_WIDTH = 1, // Range: >=1; recommended: ceil_log2(C_RATIO)
parameter integer C_DATAOUT_WIDTH = 1, // Range: >=1
parameter integer C_ONEHOT = 0 // Values: 0 = binary-encoded (use SEL); 1 = one-hot (use SEL_ONEHOT)
)
(
input wire [C_RATIO-1:0] SEL_ONEHOT, // One-hot generic_baseblocks_v2_1_mux select (only used if C_ONEHOT=1)
input wire [C_SEL_WIDTH-1:0] SEL, // Binary-encoded generic_baseblocks_v2_1_mux select (only used if C_ONEHOT=0)
input wire [C_RATIO*C_DATAOUT_WIDTH-1:0] IN, // Data input array (num_selections x data_width)
output wire [C_DATAOUT_WIDTH-1:0] OUT // Data output vector
);
wire [C_DATAOUT_WIDTH*C_RATIO-1:0] carry;
genvar i;
generate
if (C_ONEHOT == 0) begin : gen_encoded
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{(SEL==0)?1\'b1:1\'b0}} & IN[C_DATAOUT_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{(SEL==i)?1\'b1:1\'b0}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end else begin : gen_onehot
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{SEL_ONEHOT[0]}} & IN[C_DATAOUT_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_hot
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{SEL_ONEHOT[i]}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end
endgenerate
assign OUT = carry[C_DATAOUT_WIDTH*C_RATIO-1:
C_DATAOUT_WIDTH*(C_RATIO-1)];
endmodule
`default_nettype wire
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_arb_hp2_3.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between RD/WR requests from 2 ports.
* Used for modelling the Top_Interconnect switch.
*****************************************************************************/
module processing_system7_bfm_v2_0_arb_hp2_3(
sw_clk,
rstn,
w_qos_hp2,
r_qos_hp2,
w_qos_hp3,
r_qos_hp3,
wr_ack_ddr_hp2,
wr_data_hp2,
wr_addr_hp2,
wr_bytes_hp2,
wr_dv_ddr_hp2,
rd_req_ddr_hp2,
rd_addr_hp2,
rd_bytes_hp2,
rd_data_ddr_hp2,
rd_dv_ddr_hp2,
wr_ack_ddr_hp3,
wr_data_hp3,
wr_addr_hp3,
wr_bytes_hp3,
wr_dv_ddr_hp3,
rd_req_ddr_hp3,
rd_addr_hp3,
rd_bytes_hp3,
rd_data_ddr_hp3,
rd_dv_ddr_hp3,
ddr_wr_ack,
ddr_wr_dv,
ddr_rd_req,
ddr_rd_dv,
ddr_rd_qos,
ddr_wr_qos,
ddr_wr_addr,
ddr_wr_data,
ddr_wr_bytes,
ddr_rd_addr,
ddr_rd_data,
ddr_rd_bytes
);
`include "processing_system7_bfm_v2_0_local_params.v"
input sw_clk;
input rstn;
input [axi_qos_width-1:0] w_qos_hp2;
input [axi_qos_width-1:0] r_qos_hp2;
input [axi_qos_width-1:0] w_qos_hp3;
input [axi_qos_width-1:0] r_qos_hp3;
input [axi_qos_width-1:0] ddr_rd_qos;
input [axi_qos_width-1:0] ddr_wr_qos;
output wr_ack_ddr_hp2;
input [max_burst_bits-1:0] wr_data_hp2;
input [addr_width-1:0] wr_addr_hp2;
input [max_burst_bytes_width:0] wr_bytes_hp2;
output wr_dv_ddr_hp2;
input rd_req_ddr_hp2;
input [addr_width-1:0] rd_addr_hp2;
input [max_burst_bytes_width:0] rd_bytes_hp2;
output [max_burst_bits-1:0] rd_data_ddr_hp2;
output rd_dv_ddr_hp2;
output wr_ack_ddr_hp3;
input [max_burst_bits-1:0] wr_data_hp3;
input [addr_width-1:0] wr_addr_hp3;
input [max_burst_bytes_width:0] wr_bytes_hp3;
output wr_dv_ddr_hp3;
input rd_req_ddr_hp3;
input [addr_width-1:0] rd_addr_hp3;
input [max_burst_bytes_width:0] rd_bytes_hp3;
output [max_burst_bits-1:0] rd_data_ddr_hp3;
output rd_dv_ddr_hp3;
input ddr_wr_ack;
output ddr_wr_dv;
output [addr_width-1:0]ddr_wr_addr;
output [max_burst_bits-1:0]ddr_wr_data;
output [max_burst_bytes_width:0]ddr_wr_bytes;
input ddr_rd_dv;
input [max_burst_bits-1:0] ddr_rd_data;
output ddr_rd_req;
output [addr_width-1:0] ddr_rd_addr;
output [max_burst_bytes_width:0] ddr_rd_bytes;
processing_system7_bfm_v2_0_arb_wr ddr_hp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_hp2),
.qos2(w_qos_hp3),
.prt_dv1(wr_dv_ddr_hp2),
.prt_dv2(wr_dv_ddr_hp3),
.prt_data1(wr_data_hp2),
.prt_data2(wr_data_hp3),
.prt_addr1(wr_addr_hp2),
.prt_addr2(wr_addr_hp3),
.prt_bytes1(wr_bytes_hp2),
.prt_bytes2(wr_bytes_hp3),
.prt_ack1(wr_ack_ddr_hp2),
.prt_ack2(wr_ack_ddr_hp3),
.prt_req(ddr_wr_dv),
.prt_qos(ddr_wr_qos),
.prt_data(ddr_wr_data),
.prt_addr(ddr_wr_addr),
.prt_bytes(ddr_wr_bytes),
.prt_ack(ddr_wr_ack)
);
processing_system7_bfm_v2_0_arb_rd ddr_hp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_hp2),
.qos2(r_qos_hp3),
.prt_req1(rd_req_ddr_hp2),
.prt_req2(rd_req_ddr_hp3),
.prt_data1(rd_data_ddr_hp2),
.prt_data2(rd_data_ddr_hp3),
.prt_addr1(rd_addr_hp2),
.prt_addr2(rd_addr_hp3),
.prt_bytes1(rd_bytes_hp2),
.prt_bytes2(rd_bytes_hp3),
.prt_dv1(rd_dv_ddr_hp2),
.prt_dv2(rd_dv_ddr_hp3),
.prt_req(ddr_rd_req),
.prt_qos(ddr_rd_qos),
.prt_data(ddr_rd_data),
.prt_addr(ddr_rd_addr),
.prt_bytes(ddr_rd_bytes),
.prt_dv(ddr_rd_dv)
);
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_interconnect_model.v
*
* Date : 2012-11
*
* Description : Mimics Top_interconnect Switch.
*
*****************************************************************************/
module processing_system7_bfm_v2_0_interconnect_model (
rstn,
sw_clk,
w_qos_gp0,
w_qos_gp1,
w_qos_hp0,
w_qos_hp1,
w_qos_hp2,
w_qos_hp3,
r_qos_gp0,
r_qos_gp1,
r_qos_hp0,
r_qos_hp1,
r_qos_hp2,
r_qos_hp3,
wr_ack_ddr_gp0,
wr_ack_ocm_gp0,
wr_data_gp0,
wr_addr_gp0,
wr_bytes_gp0,
wr_dv_ddr_gp0,
wr_dv_ocm_gp0,
rd_req_ddr_gp0,
rd_req_ocm_gp0,
rd_req_reg_gp0,
rd_addr_gp0,
rd_bytes_gp0,
rd_data_ddr_gp0,
rd_data_ocm_gp0,
rd_data_reg_gp0,
rd_dv_ddr_gp0,
rd_dv_ocm_gp0,
rd_dv_reg_gp0,
wr_ack_ddr_gp1,
wr_ack_ocm_gp1,
wr_data_gp1,
wr_addr_gp1,
wr_bytes_gp1,
wr_dv_ddr_gp1,
wr_dv_ocm_gp1,
rd_req_ddr_gp1,
rd_req_ocm_gp1,
rd_req_reg_gp1,
rd_addr_gp1,
rd_bytes_gp1,
rd_data_ddr_gp1,
rd_data_ocm_gp1,
rd_data_reg_gp1,
rd_dv_ddr_gp1,
rd_dv_ocm_gp1,
rd_dv_reg_gp1,
wr_ack_ddr_hp0,
wr_ack_ocm_hp0,
wr_data_hp0,
wr_addr_hp0,
wr_bytes_hp0,
wr_dv_ddr_hp0,
wr_dv_ocm_hp0,
rd_req_ddr_hp0,
rd_req_ocm_hp0,
rd_addr_hp0,
rd_bytes_hp0,
rd_data_ddr_hp0,
rd_data_ocm_hp0,
rd_dv_ddr_hp0,
rd_dv_ocm_hp0,
wr_ack_ddr_hp1,
wr_ack_ocm_hp1,
wr_data_hp1,
wr_addr_hp1,
wr_bytes_hp1,
wr_dv_ddr_hp1,
wr_dv_ocm_hp1,
rd_req_ddr_hp1,
rd_req_ocm_hp1,
rd_addr_hp1,
rd_bytes_hp1,
rd_data_ddr_hp1,
rd_data_ocm_hp1,
rd_dv_ddr_hp1,
rd_dv_ocm_hp1,
wr_ack_ddr_hp2,
wr_ack_ocm_hp2,
wr_data_hp2,
wr_addr_hp2,
wr_bytes_hp2,
wr_dv_ddr_hp2,
wr_dv_ocm_hp2,
rd_req_ddr_hp2,
rd_req_ocm_hp2,
rd_addr_hp2,
rd_bytes_hp2,
rd_data_ddr_hp2,
rd_data_ocm_hp2,
rd_dv_ddr_hp2,
rd_dv_ocm_hp2,
wr_ack_ddr_hp3,
wr_ack_ocm_hp3,
wr_data_hp3,
wr_addr_hp3,
wr_bytes_hp3,
wr_dv_ddr_hp3,
wr_dv_ocm_hp3,
rd_req_ddr_hp3,
rd_req_ocm_hp3,
rd_addr_hp3,
rd_bytes_hp3,
rd_data_ddr_hp3,
rd_data_ocm_hp3,
rd_dv_ddr_hp3,
rd_dv_ocm_hp3,
/* Goes to port 1 of DDR */
ddr_wr_ack_port1,
ddr_wr_dv_port1,
ddr_rd_req_port1,
ddr_rd_dv_port1,
ddr_wr_addr_port1,
ddr_wr_data_port1,
ddr_wr_bytes_port1,
ddr_rd_addr_port1,
ddr_rd_data_port1,
ddr_rd_bytes_port1,
ddr_wr_qos_port1,
ddr_rd_qos_port1,
/* Goes to port2 of DDR */
ddr_wr_ack_port2,
ddr_wr_dv_port2,
ddr_rd_req_port2,
ddr_rd_dv_port2,
ddr_wr_addr_port2,
ddr_wr_data_port2,
ddr_wr_bytes_port2,
ddr_rd_addr_port2,
ddr_rd_data_port2,
ddr_rd_bytes_port2,
ddr_wr_qos_port2,
ddr_rd_qos_port2,
/* Goes to port3 of DDR */
ddr_wr_ack_port3,
ddr_wr_dv_port3,
ddr_rd_req_port3,
ddr_rd_dv_port3,
ddr_wr_addr_port3,
ddr_wr_data_port3,
ddr_wr_bytes_port3,
ddr_rd_addr_port3,
ddr_rd_data_port3,
ddr_rd_bytes_port3,
ddr_wr_qos_port3,
ddr_rd_qos_port3,
/* Goes to port1 of OCM */
ocm_wr_qos_port1,
ocm_rd_qos_port1,
ocm_wr_dv_port1,
ocm_wr_data_port1,
ocm_wr_addr_port1,
ocm_wr_bytes_port1,
ocm_wr_ack_port1,
ocm_rd_req_port1,
ocm_rd_data_port1,
ocm_rd_addr_port1,
ocm_rd_bytes_port1,
ocm_rd_dv_port1,
/* Goes to port1 for RegMap */
reg_rd_qos_port1,
reg_rd_req_port1,
reg_rd_data_port1,
reg_rd_addr_port1,
reg_rd_bytes_port1,
reg_rd_dv_port1
);
`include "processing_system7_bfm_v2_0_local_params.v"
input rstn;
input sw_clk;
input [axi_qos_width-1:0] w_qos_gp0;
input [axi_qos_width-1:0] w_qos_gp1;
input [axi_qos_width-1:0] w_qos_hp0;
input [axi_qos_width-1:0] w_qos_hp1;
input [axi_qos_width-1:0] w_qos_hp2;
input [axi_qos_width-1:0] w_qos_hp3;
input [axi_qos_width-1:0] r_qos_gp0;
input [axi_qos_width-1:0] r_qos_gp1;
input [axi_qos_width-1:0] r_qos_hp0;
input [axi_qos_width-1:0] r_qos_hp1;
input [axi_qos_width-1:0] r_qos_hp2;
input [axi_qos_width-1:0] r_qos_hp3;
output [axi_qos_width-1:0] ocm_wr_qos_port1;
output [axi_qos_width-1:0] ocm_rd_qos_port1;
output wr_ack_ddr_gp0;
output wr_ack_ocm_gp0;
input[max_burst_bits-1:0] wr_data_gp0;
input[addr_width-1:0] wr_addr_gp0;
input[max_burst_bytes_width:0] wr_bytes_gp0;
input wr_dv_ddr_gp0;
input wr_dv_ocm_gp0;
input rd_req_ddr_gp0;
input rd_req_ocm_gp0;
input rd_req_reg_gp0;
input[addr_width-1:0] rd_addr_gp0;
input[max_burst_bytes_width:0] rd_bytes_gp0;
output[max_burst_bits-1:0] rd_data_ddr_gp0;
output[max_burst_bits-1:0] rd_data_ocm_gp0;
output[max_burst_bits-1:0] rd_data_reg_gp0;
output rd_dv_ddr_gp0;
output rd_dv_ocm_gp0;
output rd_dv_reg_gp0;
output wr_ack_ddr_gp1;
output wr_ack_ocm_gp1;
input[max_burst_bits-1:0] wr_data_gp1;
input[addr_width-1:0] wr_addr_gp1;
input[max_burst_bytes_width:0] wr_bytes_gp1;
input wr_dv_ddr_gp1;
input wr_dv_ocm_gp1;
input rd_req_ddr_gp1;
input rd_req_ocm_gp1;
input rd_req_reg_gp1;
input[addr_width-1:0] rd_addr_gp1;
input[max_burst_bytes_width:0] rd_bytes_gp1;
output[max_burst_bits-1:0] rd_data_ddr_gp1;
output[max_burst_bits-1:0] rd_data_ocm_gp1;
output[max_burst_bits-1:0] rd_data_reg_gp1;
output rd_dv_ddr_gp1;
output rd_dv_ocm_gp1;
output rd_dv_reg_gp1;
output wr_ack_ddr_hp0;
output wr_ack_ocm_hp0;
input[max_burst_bits-1:0] wr_data_hp0;
input[addr_width-1:0] wr_addr_hp0;
input[max_burst_bytes_width:0] wr_bytes_hp0;
input wr_dv_ddr_hp0;
input wr_dv_ocm_hp0;
input rd_req_ddr_hp0;
input rd_req_ocm_hp0;
input[addr_width-1:0] rd_addr_hp0;
input[max_burst_bytes_width:0] rd_bytes_hp0;
output[max_burst_bits-1:0] rd_data_ddr_hp0;
output[max_burst_bits-1:0] rd_data_ocm_hp0;
output rd_dv_ddr_hp0;
output rd_dv_ocm_hp0;
output wr_ack_ddr_hp1;
output wr_ack_ocm_hp1;
input[max_burst_bits-1:0] wr_data_hp1;
input[addr_width-1:0] wr_addr_hp1;
input[max_burst_bytes_width:0] wr_bytes_hp1;
input wr_dv_ddr_hp1;
input wr_dv_ocm_hp1;
input rd_req_ddr_hp1;
input rd_req_ocm_hp1;
input[addr_width-1:0] rd_addr_hp1;
input[max_burst_bytes_width:0] rd_bytes_hp1;
output[max_burst_bits-1:0] rd_data_ddr_hp1;
output[max_burst_bits-1:0] rd_data_ocm_hp1;
output rd_dv_ddr_hp1;
output rd_dv_ocm_hp1;
output wr_ack_ddr_hp2;
output wr_ack_ocm_hp2;
input[max_burst_bits-1:0] wr_data_hp2;
input[addr_width-1:0] wr_addr_hp2;
input[max_burst_bytes_width:0] wr_bytes_hp2;
input wr_dv_ddr_hp2;
input wr_dv_ocm_hp2;
input rd_req_ddr_hp2;
input rd_req_ocm_hp2;
input[addr_width-1:0] rd_addr_hp2;
input[max_burst_bytes_width:0] rd_bytes_hp2;
output[max_burst_bits-1:0] rd_data_ddr_hp2;
output[max_burst_bits-1:0] rd_data_ocm_hp2;
output rd_dv_ddr_hp2;
output rd_dv_ocm_hp2;
output wr_ack_ddr_hp3;
output wr_ack_ocm_hp3;
input[max_burst_bits-1:0] wr_data_hp3;
input[addr_width-1:0] wr_addr_hp3;
input[max_burst_bytes_width:0] wr_bytes_hp3;
input wr_dv_ddr_hp3;
input wr_dv_ocm_hp3;
input rd_req_ddr_hp3;
input rd_req_ocm_hp3;
input[addr_width-1:0] rd_addr_hp3;
input[max_burst_bytes_width:0] rd_bytes_hp3;
output[max_burst_bits-1:0] rd_data_ddr_hp3;
output[max_burst_bits-1:0] rd_data_ocm_hp3;
output rd_dv_ddr_hp3;
output rd_dv_ocm_hp3;
/* Goes to port 1 of DDR */
input ddr_wr_ack_port1;
output ddr_wr_dv_port1;
output ddr_rd_req_port1;
input ddr_rd_dv_port1;
output[addr_width-1:0] ddr_wr_addr_port1;
output[max_burst_bits-1:0] ddr_wr_data_port1;
output[max_burst_bytes_width:0] ddr_wr_bytes_port1;
output[addr_width-1:0] ddr_rd_addr_port1;
input[max_burst_bits-1:0] ddr_rd_data_port1;
output[max_burst_bytes_width:0] ddr_rd_bytes_port1;
output [axi_qos_width-1:0] ddr_wr_qos_port1;
output [axi_qos_width-1:0] ddr_rd_qos_port1;
/* Goes to port2 of DDR */
input ddr_wr_ack_port2;
output ddr_wr_dv_port2;
output ddr_rd_req_port2;
input ddr_rd_dv_port2;
output[addr_width-1:0] ddr_wr_addr_port2;
output[max_burst_bits-1:0] ddr_wr_data_port2;
output[max_burst_bytes_width:0] ddr_wr_bytes_port2;
output[addr_width-1:0] ddr_rd_addr_port2;
input[max_burst_bits-1:0] ddr_rd_data_port2;
output[max_burst_bytes_width:0] ddr_rd_bytes_port2;
output [axi_qos_width-1:0] ddr_wr_qos_port2;
output [axi_qos_width-1:0] ddr_rd_qos_port2;
/* Goes to port3 of DDR */
input ddr_wr_ack_port3;
output ddr_wr_dv_port3;
output ddr_rd_req_port3;
input ddr_rd_dv_port3;
output[addr_width-1:0] ddr_wr_addr_port3;
output[max_burst_bits-1:0] ddr_wr_data_port3;
output[max_burst_bytes_width:0] ddr_wr_bytes_port3;
output[addr_width-1:0] ddr_rd_addr_port3;
input[max_burst_bits-1:0] ddr_rd_data_port3;
output[max_burst_bytes_width:0] ddr_rd_bytes_port3;
output [axi_qos_width-1:0] ddr_wr_qos_port3;
output [axi_qos_width-1:0] ddr_rd_qos_port3;
/* Goes to port1 of OCM */
input ocm_wr_ack_port1;
output ocm_wr_dv_port1;
output ocm_rd_req_port1;
input ocm_rd_dv_port1;
output[max_burst_bits-1:0] ocm_wr_data_port1;
output[addr_width-1:0] ocm_wr_addr_port1;
output[max_burst_bytes_width:0] ocm_wr_bytes_port1;
input[max_burst_bits-1:0] ocm_rd_data_port1;
output[addr_width-1:0] ocm_rd_addr_port1;
output[max_burst_bytes_width:0] ocm_rd_bytes_port1;
/* Goes to port1 of REG */
output [axi_qos_width-1:0] reg_rd_qos_port1;
output reg_rd_req_port1;
input reg_rd_dv_port1;
input[max_burst_bits-1:0] reg_rd_data_port1;
output[addr_width-1:0] reg_rd_addr_port1;
output[max_burst_bytes_width:0] reg_rd_bytes_port1;
wire ocm_wr_dv_osw0;
wire ocm_wr_dv_osw1;
wire[max_burst_bits-1:0] ocm_wr_data_osw0;
wire[max_burst_bits-1:0] ocm_wr_data_osw1;
wire[addr_width-1:0] ocm_wr_addr_osw0;
wire[addr_width-1:0] ocm_wr_addr_osw1;
wire[max_burst_bytes_width:0] ocm_wr_bytes_osw0;
wire[max_burst_bytes_width:0] ocm_wr_bytes_osw1;
wire ocm_wr_ack_osw0;
wire ocm_wr_ack_osw1;
wire ocm_rd_req_osw0;
wire ocm_rd_req_osw1;
wire[max_burst_bits-1:0] ocm_rd_data_osw0;
wire[max_burst_bits-1:0] ocm_rd_data_osw1;
wire[addr_width-1:0] ocm_rd_addr_osw0;
wire[addr_width-1:0] ocm_rd_addr_osw1;
wire[max_burst_bytes_width:0] ocm_rd_bytes_osw0;
wire[max_burst_bytes_width:0] ocm_rd_bytes_osw1;
wire ocm_rd_dv_osw0;
wire ocm_rd_dv_osw1;
wire [axi_qos_width-1:0] ocm_wr_qos_osw0;
wire [axi_qos_width-1:0] ocm_wr_qos_osw1;
wire [axi_qos_width-1:0] ocm_rd_qos_osw0;
wire [axi_qos_width-1:0] ocm_rd_qos_osw1;
processing_system7_bfm_v2_0_fmsw_gp fmsw (
.sw_clk(sw_clk),
.rstn(rstn),
.w_qos_gp0(w_qos_gp0),
.r_qos_gp0(r_qos_gp0),
.wr_ack_ocm_gp0(wr_ack_ocm_gp0),
.wr_ack_ddr_gp0(wr_ack_ddr_gp0),
.wr_data_gp0(wr_data_gp0),
.wr_addr_gp0(wr_addr_gp0),
.wr_bytes_gp0(wr_bytes_gp0),
.wr_dv_ocm_gp0(wr_dv_ocm_gp0),
.wr_dv_ddr_gp0(wr_dv_ddr_gp0),
.rd_req_ocm_gp0(rd_req_ocm_gp0),
.rd_req_ddr_gp0(rd_req_ddr_gp0),
.rd_req_reg_gp0(rd_req_reg_gp0),
.rd_addr_gp0(rd_addr_gp0),
.rd_bytes_gp0(rd_bytes_gp0),
.rd_data_ddr_gp0(rd_data_ddr_gp0),
.rd_data_ocm_gp0(rd_data_ocm_gp0),
.rd_data_reg_gp0(rd_data_reg_gp0),
.rd_dv_ocm_gp0(rd_dv_ocm_gp0),
.rd_dv_ddr_gp0(rd_dv_ddr_gp0),
.rd_dv_reg_gp0(rd_dv_reg_gp0),
.w_qos_gp1(w_qos_gp1),
.r_qos_gp1(r_qos_gp1),
.wr_ack_ocm_gp1(wr_ack_ocm_gp1),
.wr_ack_ddr_gp1(wr_ack_ddr_gp1),
.wr_data_gp1(wr_data_gp1),
.wr_addr_gp1(wr_addr_gp1),
.wr_bytes_gp1(wr_bytes_gp1),
.wr_dv_ocm_gp1(wr_dv_ocm_gp1),
.wr_dv_ddr_gp1(wr_dv_ddr_gp1),
.rd_req_ocm_gp1(rd_req_ocm_gp1),
.rd_req_ddr_gp1(rd_req_ddr_gp1),
.rd_req_reg_gp1(rd_req_reg_gp1),
.rd_addr_gp1(rd_addr_gp1),
.rd_bytes_gp1(rd_bytes_gp1),
.rd_data_ddr_gp1(rd_data_ddr_gp1),
.rd_data_ocm_gp1(rd_data_ocm_gp1),
.rd_data_reg_gp1(rd_data_reg_gp1),
.rd_dv_ocm_gp1(rd_dv_ocm_gp1),
.rd_dv_ddr_gp1(rd_dv_ddr_gp1),
.rd_dv_reg_gp1(rd_dv_reg_gp1),
.ocm_wr_ack (ocm_wr_ack_osw0),
.ocm_wr_dv (ocm_wr_dv_osw0),
.ocm_rd_req (ocm_rd_req_osw0),
.ocm_rd_dv (ocm_rd_dv_osw0),
.ocm_wr_addr(ocm_wr_addr_osw0),
.ocm_wr_data(ocm_wr_data_osw0),
.ocm_wr_bytes(ocm_wr_bytes_osw0),
.ocm_rd_addr(ocm_rd_addr_osw0),
.ocm_rd_data(ocm_rd_data_osw0),
.ocm_rd_bytes(ocm_rd_bytes_osw0),
.ocm_wr_qos(ocm_wr_qos_osw0),
.ocm_rd_qos(ocm_rd_qos_osw0),
.ddr_wr_qos(ddr_wr_qos_port1),
.ddr_rd_qos(ddr_rd_qos_port1),
.reg_rd_qos(reg_rd_qos_port1),
.ddr_wr_ack(ddr_wr_ack_port1),
.ddr_wr_dv(ddr_wr_dv_port1),
.ddr_rd_req(ddr_rd_req_port1),
.ddr_rd_dv(ddr_rd_dv_port1),
.ddr_wr_addr(ddr_wr_addr_port1),
.ddr_wr_data(ddr_wr_data_port1),
.ddr_wr_bytes(ddr_wr_bytes_port1),
.ddr_rd_addr(ddr_rd_addr_port1),
.ddr_rd_data(ddr_rd_data_port1),
.ddr_rd_bytes(ddr_rd_bytes_port1),
.reg_rd_req(reg_rd_req_port1),
.reg_rd_dv(reg_rd_dv_port1),
.reg_rd_addr(reg_rd_addr_port1),
.reg_rd_data(reg_rd_data_port1),
.reg_rd_bytes(reg_rd_bytes_port1)
);
processing_system7_bfm_v2_0_ssw_hp ssw(
.sw_clk(sw_clk),
.rstn(rstn),
.w_qos_hp0(w_qos_hp0),
.r_qos_hp0(r_qos_hp0),
.w_qos_hp1(w_qos_hp1),
.r_qos_hp1(r_qos_hp1),
.w_qos_hp2(w_qos_hp2),
.r_qos_hp2(r_qos_hp2),
.w_qos_hp3(w_qos_hp3),
.r_qos_hp3(r_qos_hp3),
.wr_ack_ddr_hp0(wr_ack_ddr_hp0),
.wr_data_hp0(wr_data_hp0),
.wr_addr_hp0(wr_addr_hp0),
.wr_bytes_hp0(wr_bytes_hp0),
.wr_dv_ddr_hp0(wr_dv_ddr_hp0),
.rd_req_ddr_hp0(rd_req_ddr_hp0),
.rd_addr_hp0(rd_addr_hp0),
.rd_bytes_hp0(rd_bytes_hp0),
.rd_data_ddr_hp0(rd_data_ddr_hp0),
.rd_data_ocm_hp0(rd_data_ocm_hp0),
.rd_dv_ddr_hp0(rd_dv_ddr_hp0),
.wr_ack_ocm_hp0(wr_ack_ocm_hp0),
.wr_dv_ocm_hp0(wr_dv_ocm_hp0),
.rd_req_ocm_hp0(rd_req_ocm_hp0),
.rd_dv_ocm_hp0(rd_dv_ocm_hp0),
.wr_ack_ddr_hp1(wr_ack_ddr_hp1),
.wr_data_hp1(wr_data_hp1),
.wr_addr_hp1(wr_addr_hp1),
.wr_bytes_hp1(wr_bytes_hp1),
.wr_dv_ddr_hp1(wr_dv_ddr_hp1),
.rd_req_ddr_hp1(rd_req_ddr_hp1),
.rd_addr_hp1(rd_addr_hp1),
.rd_bytes_hp1(rd_bytes_hp1),
.rd_data_ddr_hp1(rd_data_ddr_hp1),
.rd_data_ocm_hp1(rd_data_ocm_hp1),
.rd_dv_ddr_hp1(rd_dv_ddr_hp1),
.wr_ack_ocm_hp1(wr_ack_ocm_hp1),
.wr_dv_ocm_hp1(wr_dv_ocm_hp1),
.rd_req_ocm_hp1(rd_req_ocm_hp1),
.rd_dv_ocm_hp1(rd_dv_ocm_hp1),
.wr_ack_ddr_hp2(wr_ack_ddr_hp2),
.wr_data_hp2(wr_data_hp2),
.wr_addr_hp2(wr_addr_hp2),
.wr_bytes_hp2(wr_bytes_hp2),
.wr_dv_ddr_hp2(wr_dv_ddr_hp2),
.rd_req_ddr_hp2(rd_req_ddr_hp2),
.rd_addr_hp2(rd_addr_hp2),
.rd_bytes_hp2(rd_bytes_hp2),
.rd_data_ddr_hp2(rd_data_ddr_hp2),
.rd_data_ocm_hp2(rd_data_ocm_hp2),
.rd_dv_ddr_hp2(rd_dv_ddr_hp2),
.wr_ack_ocm_hp2(wr_ack_ocm_hp2),
.wr_dv_ocm_hp2(wr_dv_ocm_hp2),
.rd_req_ocm_hp2(rd_req_ocm_hp2),
.rd_dv_ocm_hp2(rd_dv_ocm_hp2),
.wr_ack_ddr_hp3(wr_ack_ddr_hp3),
.wr_data_hp3(wr_data_hp3),
.wr_addr_hp3(wr_addr_hp3),
.wr_bytes_hp3(wr_bytes_hp3),
.wr_dv_ddr_hp3(wr_dv_ddr_hp3),
.rd_req_ddr_hp3(rd_req_ddr_hp3),
.rd_addr_hp3(rd_addr_hp3),
.rd_bytes_hp3(rd_bytes_hp3),
.rd_data_ddr_hp3(rd_data_ddr_hp3),
.rd_data_ocm_hp3(rd_data_ocm_hp3),
.rd_dv_ddr_hp3(rd_dv_ddr_hp3),
.wr_ack_ocm_hp3(wr_ack_ocm_hp3),
.wr_dv_ocm_hp3(wr_dv_ocm_hp3),
.rd_req_ocm_hp3(rd_req_ocm_hp3),
.rd_dv_ocm_hp3(rd_dv_ocm_hp3),
.ddr_wr_ack0(ddr_wr_ack_port2),
.ddr_wr_dv0(ddr_wr_dv_port2),
.ddr_rd_req0(ddr_rd_req_port2),
.ddr_rd_dv0(ddr_rd_dv_port2),
.ddr_wr_addr0(ddr_wr_addr_port2),
.ddr_wr_data0(ddr_wr_data_port2),
.ddr_wr_bytes0(ddr_wr_bytes_port2),
.ddr_rd_addr0(ddr_rd_addr_port2),
.ddr_rd_data0(ddr_rd_data_port2),
.ddr_rd_bytes0(ddr_rd_bytes_port2),
.ddr_wr_qos0(ddr_wr_qos_port2),
.ddr_rd_qos0(ddr_rd_qos_port2),
.ddr_wr_ack1(ddr_wr_ack_port3),
.ddr_wr_dv1(ddr_wr_dv_port3),
.ddr_rd_req1(ddr_rd_req_port3),
.ddr_rd_dv1(ddr_rd_dv_port3),
.ddr_wr_addr1(ddr_wr_addr_port3),
.ddr_wr_data1(ddr_wr_data_port3),
.ddr_wr_bytes1(ddr_wr_bytes_port3),
.ddr_rd_addr1(ddr_rd_addr_port3),
.ddr_rd_data1(ddr_rd_data_port3),
.ddr_rd_bytes1(ddr_rd_bytes_port3),
.ddr_wr_qos1(ddr_wr_qos_port3),
.ddr_rd_qos1(ddr_rd_qos_port3),
.ocm_wr_qos(ocm_wr_qos_osw1),
.ocm_rd_qos(ocm_rd_qos_osw1),
.ocm_wr_ack (ocm_wr_ack_osw1),
.ocm_wr_dv (ocm_wr_dv_osw1),
.ocm_rd_req (ocm_rd_req_osw1),
.ocm_rd_dv (ocm_rd_dv_osw1),
.ocm_wr_addr(ocm_wr_addr_osw1),
.ocm_wr_data(ocm_wr_data_osw1),
.ocm_wr_bytes(ocm_wr_bytes_osw1),
.ocm_rd_addr(ocm_rd_addr_osw1),
.ocm_rd_data(ocm_rd_data_osw1),
.ocm_rd_bytes(ocm_rd_bytes_osw1)
);
processing_system7_bfm_v2_0_arb_wr osw_wr (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ocm_wr_qos_osw0), /// chk
.qos2(ocm_wr_qos_osw1), /// chk
.prt_dv1(ocm_wr_dv_osw0),
.prt_dv2(ocm_wr_dv_osw1),
.prt_data1(ocm_wr_data_osw0),
.prt_data2(ocm_wr_data_osw1),
.prt_addr1(ocm_wr_addr_osw0),
.prt_addr2(ocm_wr_addr_osw1),
.prt_bytes1(ocm_wr_bytes_osw0),
.prt_bytes2(ocm_wr_bytes_osw1),
.prt_ack1(ocm_wr_ack_osw0),
.prt_ack2(ocm_wr_ack_osw1),
.prt_req(ocm_wr_dv_port1),
.prt_qos(ocm_wr_qos_port1),
.prt_data(ocm_wr_data_port1),
.prt_addr(ocm_wr_addr_port1),
.prt_bytes(ocm_wr_bytes_port1),
.prt_ack(ocm_wr_ack_port1)
);
processing_system7_bfm_v2_0_arb_rd osw_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ocm_rd_qos_osw0), // chk
.qos2(ocm_rd_qos_osw1), // chk
.prt_req1(ocm_rd_req_osw0),
.prt_req2(ocm_rd_req_osw1),
.prt_data1(ocm_rd_data_osw0),
.prt_data2(ocm_rd_data_osw1),
.prt_addr1(ocm_rd_addr_osw0),
.prt_addr2(ocm_rd_addr_osw1),
.prt_bytes1(ocm_rd_bytes_osw0),
.prt_bytes2(ocm_rd_bytes_osw1),
.prt_dv1(ocm_rd_dv_osw0),
.prt_dv2(ocm_rd_dv_osw1),
.prt_req(ocm_rd_req_port1),
.prt_qos(ocm_rd_qos_port1),
.prt_data(ocm_rd_data_port1),
.prt_addr(ocm_rd_addr_port1),
.prt_bytes(ocm_rd_bytes_port1),
.prt_dv(ocm_rd_dv_port1)
);
endmodule
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.