text
stringlengths
1
2.1M
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: // Carry logic. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module generic_baseblocks_v2_1_carry # ( parameter C_FAMILY = "virtex6" // FPGA Family. Current version: virtex6 or spartan6. ) ( input wire CIN, input wire S, input wire DI, output wire COUT ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Instantiate or use RTL code ///////////////////////////////////////////////////////////////////////////// generate if ( C_FAMILY == "rtl" ) begin : USE_RTL assign COUT = (CIN & S) | (DI & ~S); end else begin : USE_FPGA MUXCY and_inst ( .O (COUT), .CI (CIN), .DI (DI), .S (S) ); end endgenerate endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Generic single-channel AXI FIFO // Synchronous FIFO is implemented using either LUTs (SRL) or BRAM. // Transfers received on the AXI slave port are pushed onto the FIFO. // FIFO output, when available, is presented on the AXI master port and // popped when the master port responds (M_READY). // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // Structure: // axic_fifo // fifo_gen //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module axi_data_fifo_v2_1_axic_fifo # ( parameter C_FAMILY = "virtex6", parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG // Range = [5:9] when TYPE="lut", // Range = [5:12] when TYPE="bram", parameter integer C_FIFO_WIDTH = 64, // Width of payload [1:512] parameter C_FIFO_TYPE = "lut" // "lut" = LUT (SRL) based, // "bram" = BRAM based ) ( // Global inputs input wire ACLK, // Clock input wire ARESET, // Reset // Slave Port input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals) input wire S_VALID, // FIFO push output wire S_READY, // FIFO not full // Master Port output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload output wire M_VALID, // FIFO not empty input wire M_READY // FIFO pop ); axi_data_fifo_v2_1_fifo_gen #( .C_FAMILY(C_FAMILY), .C_COMMON_CLOCK(1), .C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG), .C_FIFO_WIDTH(C_FIFO_WIDTH), .C_FIFO_TYPE(C_FIFO_TYPE)) inst ( .clk(ACLK), .rst(ARESET), .wr_clk(1\'b0), .wr_en(S_VALID), .wr_ready(S_READY), .wr_data(S_MESG), .rd_clk(1\'b0), .rd_en(M_READY), .rd_valid(M_VALID), .rd_data(M_MESG)); endmodule
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // File name: addr_arbiter_sasd.v // // Description: // Hybrid priority + round-robin arbiter. // Read & write requests combined (read preferred) at each slot // Muxes AR and AW channel payload inputs based on arbitration results. //----------------------------------------------------------------------------- // // Structure: // addr_arbiter_sasd // mux_enc //----------------------------------------------------------------------------- `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_crossbar_v2_1_addr_arbiter_sasd # ( parameter C_FAMILY = "none", parameter integer C_NUM_S = 1, parameter integer C_NUM_S_LOG = 1, parameter integer C_AMESG_WIDTH = 1, parameter C_GRANT_ENC = 0, parameter [C_NUM_S*32-1:0] C_ARB_PRIORITY = {C_NUM_S{32\'h00000000}} // Arbitration priority among each SI slot. // Higher values indicate higher priority. // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: \'h0-\'hF. ) ( // Global Signals input wire ACLK, input wire ARESET, // Slave Ports input wire [C_NUM_S*C_AMESG_WIDTH-1:0] S_AWMESG, input wire [C_NUM_S*C_AMESG_WIDTH-1:0] S_ARMESG, input wire [C_NUM_S-1:0] S_AWVALID, output wire [C_NUM_S-1:0] S_AWREADY, input wire [C_NUM_S-1:0] S_ARVALID, output wire [C_NUM_S-1:0] S_ARREADY, // Master Ports output wire [C_AMESG_WIDTH-1:0] M_AMESG, output wire [C_NUM_S_LOG-1:0] M_GRANT_ENC, output wire [C_NUM_S-1:0] M_GRANT_HOT, output wire M_GRANT_RNW, output wire M_GRANT_ANY, output wire M_AWVALID, input wire M_AWREADY, output wire M_ARVALID, input wire M_ARREADY ); // Generates a mask for all input slots that are priority based function [C_NUM_S-1:0] f_prio_mask ( input integer null_arg ); reg [C_NUM_S-1:0] mask; integer i; begin mask = 0; for (i=0; i < C_NUM_S; i=i+1) begin mask[i] = (C_ARB_PRIORITY[i*32+:32] != 0); end f_prio_mask = mask; end endfunction // Convert 16-bit one-hot to 4-bit binary function [3:0] f_hot2enc ( input [15:0] one_hot ); begin f_hot2enc[0] = |(one_hot & 16\'b1010101010101010); f_hot2enc[1] = |(one_hot & 16\'b1100110011001100); f_hot2enc[2] = |(one_hot & 16\'b1111000011110000); f_hot2enc[3] = |(one_hot & 16\'b1111111100000000); end endfunction localparam [C_NUM_S-1:0] P_PRIO_MASK = f_prio_mask(0); reg m_valid_i; reg [C_NUM_S-1:0] s_ready_i; reg [C_NUM_S-1:0] s_awvalid_reg; reg [C_NUM_S-1:0] s_arvalid_reg; wire [15:0] s_avalid; wire m_aready; wire [C_NUM_S-1:0] rnw; reg grant_rnw; reg [C_NUM_S_LOG-1:0] m_grant_enc_i; reg [C_NUM_S-1:0] m_grant_hot_i; reg [C_NUM_S-1:0] last_rr_hot; reg any_grant; reg any_prio; reg [C_NUM_S-1:0] which_prio_hot; reg [C_NUM_S_LOG-1:0] which_prio_enc; reg [4:0] current_highest; reg [15:0] next_prio_hot; reg [C_NUM_S_LOG-1:0] next_prio_enc; reg found_prio; wire [C_NUM_S-1:0] valid_rr; reg [15:0] next_rr_hot; reg [C_NUM_S_LOG-1:0] next_rr_enc; reg [C_NUM_S*C_NUM_S-1:0] carry_rr; reg [C_NUM_S*C_NUM_S-1:0] mask_rr; reg found_rr; wire [C_NUM_S-1:0] next_hot; wire [C_NUM_S_LOG-1:0] next_enc; integer i; wire [C_AMESG_WIDTH-1:0] amesg_mux; reg [C_AMESG_WIDTH-1:0] m_amesg_i; wire [C_NUM_S*C_AMESG_WIDTH-1:0] s_amesg; genvar gen_si; always @(posedge ACLK) begin if (ARESET) begin s_awvalid_reg <= 0; s_arvalid_reg <= 0; end else if (|s_ready_i) begin s_awvalid_reg <= 0; s_arvalid_reg <= 0; end else begin s_arvalid_reg <= S_ARVALID & ~s_awvalid_reg; s_awvalid_reg <= S_AWVALID & ~s_arvalid_reg & (~S_ARVALID | s_awvalid_reg); end end assign s_avalid = S_AWVALID | S_ARVALID; assign M_AWVALID = m_valid_i & ~grant_rnw; assign M_ARVALID = m_valid_i & grant_rnw; assign S_AWREADY = s_ready_i & {C_NUM_S{~grant_rnw}}; assign S_ARREADY = s_ready_i & {C_NUM_S{grant_rnw}}; assign M_GRANT_ENC = C_GRANT_ENC ? m_grant_enc_i : 0; assign M_GRANT_HOT = m_grant_hot_i; assign M_GRANT_RNW = grant_rnw; assign rnw = S_ARVALID & ~s_awvalid_reg; assign M_AMESG = m_amesg_i; assign m_aready = grant_rnw ? M_ARREADY : M_AWREADY; generate for (gen_si=0; gen_si<C_NUM_S; gen_si=gen_si+1) begin : gen_mesg_mux assign s_amesg[C_AMESG_WIDTH*gen_si +: C_AMESG_WIDTH] = rnw[gen_si] ? S_ARMESG[C_AMESG_WIDTH*gen_si +: C_AMESG_WIDTH] : S_AWMESG[C_AMESG_WIDTH*gen_si +: C_AMESG_WIDTH]; end // gen_mesg_mux if (C_NUM_S>1) begin : gen_arbiter ///////////////////////////////////////////////////////////////////////////// // Grant a new request when there is none still pending. // If no qualified requests found, de-assert M_VALID. ///////////////////////////////////////////////////////////////////////////// assign M_GRANT_ANY = any_grant; assign next_hot = found_prio ? next_prio_hot : next_rr_hot; assign next_enc = found_prio ? next_prio_enc : next_rr_enc; always @(posedge ACLK) begin if (ARESET) begin m_valid_i <= 0; s_ready_i <= 0; m_grant_hot_i <= 0; m_grant_enc_i <= 0; any_grant <= 1\'b0; last_rr_hot <= {1\'b1, {C_NUM_S-1{1\'b0}}}; grant_rnw <= 1\'b0; end else begin s_ready_i <= 0; if (m_valid_i) begin // Stall 1 cycle after each master-side completion. if (m_aready) begin // Master-side completion m_valid_i <= 1\'b0; m_grant_hot_i <= 0; any_grant <= 1\'b0; end end else if (any_grant) begin m_valid_i <= 1\'b1; s_ready_i <= m_grant_hot_i; // Assert S_AW/READY for 1 cycle to complete SI address transfer end else begin if (found_prio | found_rr) begin m_grant_hot_i <= next_hot; m_grant_enc_i <= next_enc; any_grant <= 1\'b1; grant_rnw <= |(rnw & next_hot); if (~found_prio) begin last_rr_hot <= next_rr_hot; end end end end end ///////////////////////////////////////////////////////////////////////////// // Fixed Priority arbiter // Selects next request to grant from among inputs with PRIO > 0, if any. ///////////////////////////////////////////////////////////////////////////// always @ * begin : ALG_PRIO integer ip; any_prio = 1\'b0; which_prio_hot = 0; which_prio_enc = 0; current_highest = 0; for (ip=0; ip < C_NUM_S; ip=ip+1) begin if (P_PRIO_MASK[ip] & ({1\'b0, C_ARB_PRIORITY[ip*32+:4]} > current_highest)) begin if (s_avalid[ip]) begin current_highest[0+:4] = C_ARB_PRIORITY[ip*32+:4]; any_prio = 1\'b1; which_prio_hot = 1\'b1 << ip; which_prio_enc = ip; end end end found_prio = any_prio; next_prio_hot = which_prio_hot; next_prio_enc = which_prio_enc; end ///////////////////////////////////////////////////////////////////////////// // Round-robin arbiter // Selects next request to grant from among inputs with PRIO = 0, if any. ///////////////////////////////////////////////////////////////////////////// assign valid_rr = ~P_PRIO_MASK & s_avalid; always @ * begin : ALG_RR integer ir, jr, nr; next_rr_hot = 0; for (ir=0;ir<C_NUM_S;ir=ir+1) begin nr = (ir>0) ? (ir-1) : (C_NUM_S-1); carry_rr[ir*C_NUM_S] = last_rr_hot[nr]; mask_rr[ir*C_NUM_S] = ~valid_rr[nr]; for (jr=1;jr<C_NUM_S;jr=jr+1) begin nr = (ir-jr > 0) ? (ir-jr-1) : (C_NUM_S+ir-jr-1); carry_rr[ir*C_NUM_S+jr] = carry_rr[ir*C_NUM_S+jr-1] | (last_rr_hot[nr] & mask_rr[ir*C_NUM_S+jr-1]); if (jr < C_NUM_S-1) begin mask_rr[ir*C_NUM_S+jr] = mask_rr[ir*C_NUM_S+jr-1] & ~valid_rr[nr]; end end next_rr_hot[ir] = valid_rr[ir] & carry_rr[(ir+1)*C_NUM_S-1]; end next_rr_enc = f_hot2enc(next_rr_hot); found_rr = |(next_rr_hot); end generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (C_NUM_S), .C_SEL_WIDTH (C_NUM_S_LOG), .C_DATA_WIDTH (C_AMESG_WIDTH) ) si_amesg_mux_inst ( .S (next_enc), .A (s_amesg), .O (amesg_mux), .OE (1\'b1) ); always @(posedge ACLK) begin if (ARESET) begin m_amesg_i <= 0; end else if (~any_grant) begin m_amesg_i <= amesg_mux; end end end else begin : gen_no_arbiter assign M_GRANT_ANY = m_grant_hot_i; always @ (posedge ACLK) begin if (ARESET) begin m_valid_i <= 1\'b0; s_ready_i <= 1\'b0; m_grant_enc_i <= 0; m_grant_hot_i <= 1\'b0; grant_rnw <= 1\'b0; end else begin s_ready_i <= 1\'b0; if (m_valid_i) begin if (m_aready) begin m_valid_i <= 1\'b0; m_grant_hot_i <= 1\'b0; end end else if (m_grant_hot_i) begin m_valid_i <= 1\'b1; s_ready_i[0] <= 1\'b1; // Assert S_AW/READY for 1 cycle to complete SI address transfer end else if (s_avalid[0]) begin m_grant_hot_i <= 1\'b1; grant_rnw <= rnw[0]; end end end always @ (posedge ACLK) begin if (ARESET) begin m_amesg_i <= 0; end else if (~m_grant_hot_i) begin m_amesg_i <= s_amesg; end end end // gen_arbiter endgenerate endmodule `default_nettype wire
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: // Optimized OR with generic_baseblocks_v2_1_carry logic. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module generic_baseblocks_v2_1_carry_or # ( parameter C_FAMILY = "virtex6" // FPGA Family. Current version: virtex6 or spartan6. ) ( input wire CIN, input wire S, output wire COUT ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Instantiate or use RTL code ///////////////////////////////////////////////////////////////////////////// generate if ( C_FAMILY == "rtl" ) begin : USE_RTL assign COUT = CIN | S; end else begin : USE_FPGA wire S_n; assign S_n = ~S; MUXCY and_inst ( .O (COUT), .CI (CIN), .DI (1\'b1), .S (S_n) ); end endgenerate endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: // Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_carry logic. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module generic_baseblocks_v2_1_comparator_sel_mask_static # ( parameter C_FAMILY = "virtex6", // FPGA Family. Current version: virtex6 or spartan6. parameter C_VALUE = 4\'b0, // Static value to compare against. parameter integer C_DATA_WIDTH = 4 // Data width for comparator. ) ( input wire CIN, input wire S, input wire [C_DATA_WIDTH-1:0] A, input wire [C_DATA_WIDTH-1:0] B, input wire [C_DATA_WIDTH-1:0] M, output wire COUT ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// // Generate variable for bit vector. genvar lut_cnt; ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Bits per LUT for this architecture. localparam integer C_BITS_PER_LUT = 1; // Constants for packing levels. localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT; // localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT : C_DATA_WIDTH; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// wire [C_FIX_DATA_WIDTH-1:0] a_local; wire [C_FIX_DATA_WIDTH-1:0] b_local; wire [C_FIX_DATA_WIDTH-1:0] m_local; wire [C_FIX_DATA_WIDTH-1:0] v_local; wire [C_NUM_LUT-1:0] sel; wire [C_NUM_LUT:0] carry_local; ///////////////////////////////////////////////////////////////////////////// // ///////////////////////////////////////////////////////////////////////////// generate // Assign input to local vectors. assign carry_local[0] = CIN; // Extend input data to fit. if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}}; assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}}; assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}}; assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}}; end else begin : NO_EXTENDED_DATA assign a_local = A; assign b_local = B; assign m_local = M; assign v_local = C_VALUE; end // Instantiate one generic_baseblocks_v2_1_carry and per level. for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL // Create the local select signal assign sel[lut_cnt] = ( ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) == ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1\'b0 ) ) | ( ( ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) == ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1\'b1 ) ); // Instantiate each LUT level. generic_baseblocks_v2_1_carry_and # ( .C_FAMILY(C_FAMILY) ) compare_inst ( .COUT (carry_local[lut_cnt+1]), .CIN (carry_local[lut_cnt]), .S (sel[lut_cnt]) ); end // end for lut_cnt // Assign output from local vector. assign COUT = carry_local[C_NUM_LUT]; endgenerate endmodule
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // File name: decerr_slave.v // // Description: // Phantom slave interface used to complete W, R and B channel transfers when an // erroneous transaction is trapped in the crossbar. //-------------------------------------------------------------------------- // // Structure: // decerr_slave // //----------------------------------------------------------------------------- `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_protocol_converter_v2_1_decerr_slave # ( parameter integer C_AXI_ID_WIDTH = 1, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_BUSER_WIDTH = 1, parameter integer C_AXI_RUSER_WIDTH = 1, parameter integer C_AXI_PROTOCOL = 0, parameter integer C_RESP = 2\'b11, parameter integer C_IGNORE_ID = 0 ) ( input wire ACLK, input wire ARESETN, input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_AWID, input wire S_AXI_AWVALID, output wire S_AXI_AWREADY, input wire S_AXI_WLAST, input wire S_AXI_WVALID, output wire S_AXI_WREADY, output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_BID, output wire [1:0] S_AXI_BRESP, output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, output wire S_AXI_BVALID, input wire S_AXI_BREADY, input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_ARID, input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] S_AXI_ARLEN, input wire S_AXI_ARVALID, output wire S_AXI_ARREADY, output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_RID, output wire [(C_AXI_DATA_WIDTH-1):0] S_AXI_RDATA, output wire [1:0] S_AXI_RRESP, output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, output wire S_AXI_RLAST, output wire S_AXI_RVALID, input wire S_AXI_RREADY ); reg s_axi_awready_i; reg s_axi_wready_i; reg s_axi_bvalid_i; reg s_axi_arready_i; reg s_axi_rvalid_i; localparam P_WRITE_IDLE = 2\'b00; localparam P_WRITE_DATA = 2\'b01; localparam P_WRITE_RESP = 2\'b10; localparam P_READ_IDLE = 2\'b00; localparam P_READ_START = 2\'b01; localparam P_READ_DATA = 2\'b10; localparam integer P_AXI4 = 0; localparam integer P_AXI3 = 1; localparam integer P_AXILITE = 2; assign S_AXI_BRESP = C_RESP; assign S_AXI_RRESP = C_RESP; assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1\'b0}}; assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1\'b0}}; assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1\'b0}}; assign S_AXI_AWREADY = s_axi_awready_i; assign S_AXI_WREADY = s_axi_wready_i; assign S_AXI_BVALID = s_axi_bvalid_i; assign S_AXI_ARREADY = s_axi_arready_i; assign S_AXI_RVALID = s_axi_rvalid_i; generate if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_axilite reg s_axi_rvalid_en; assign S_AXI_RLAST = 1\'b1; assign S_AXI_BID = 0; assign S_AXI_RID = 0; always @(posedge ACLK) begin if (~ARESETN) begin s_axi_awready_i <= 1\'b0; s_axi_wready_i <= 1\'b0; s_axi_bvalid_i <= 1\'b0; end else begin if (s_axi_bvalid_i) begin if (S_AXI_BREADY) begin s_axi_bvalid_i <= 1\'b0; s_axi_awready_i <= 1\'b1; end end else if (S_AXI_WVALID & s_axi_wready_i) begin s_axi_wready_i <= 1\'b0; s_axi_bvalid_i <= 1\'b1; end else if (S_AXI_AWVALID & s_axi_awready_i) begin s_axi_awready_i <= 1\'b0; s_axi_wready_i <= 1\'b1; end else begin s_axi_awready_i <= 1\'b1; end end end always @(posedge ACLK) begin if (~ARESETN) begin s_axi_arready_i <= 1\'b0; s_axi_rvalid_i <= 1\'b0; s_axi_rvalid_en <= 1\'b0; end else begin if (s_axi_rvalid_i) begin if (S_AXI_RREADY) begin s_axi_rvalid_i <= 1\'b0; s_axi_arready_i <= 1\'b1; end end else if (s_axi_rvalid_en) begin s_axi_rvalid_en <= 1\'b0; s_axi_rvalid_i <= 1\'b1; end else if (S_AXI_ARVALID & s_axi_arready_i) begin s_axi_arready_i <= 1\'b0; s_axi_rvalid_en <= 1\'b1; end else begin s_axi_arready_i <= 1\'b1; end end end end else begin : gen_axi reg s_axi_rlast_i; reg [(C_AXI_ID_WIDTH-1):0] s_axi_bid_i; reg [(C_AXI_ID_WIDTH-1):0] s_axi_rid_i; reg [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] read_cnt; reg [1:0] write_cs; reg [1:0] read_cs; assign S_AXI_RLAST = s_axi_rlast_i; assign S_AXI_BID = C_IGNORE_ID ? 0 : s_axi_bid_i; assign S_AXI_RID = C_IGNORE_ID ? 0 : s_axi_rid_i; always @(posedge ACLK) begin if (~ARESETN) begin write_cs <= P_WRITE_IDLE; s_axi_awready_i <= 1\'b0; s_axi_wready_i <= 1\'b0; s_axi_bvalid_i <= 1\'b0; s_axi_bid_i <= 0; end else begin case (write_cs) P_WRITE_IDLE: begin if (S_AXI_AWVALID & s_axi_awready_i) begin s_axi_awready_i <= 1\'b0; if (C_IGNORE_ID == 0) s_axi_bid_i <= S_AXI_AWID; s_axi_wready_i <= 1\'b1; write_cs <= P_WRITE_DATA; end else begin s_axi_awready_i <= 1\'b1; end end P_WRITE_DATA: begin if (S_AXI_WVALID & S_AXI_WLAST) begin s_axi_wready_i <= 1\'b0; s_axi_bvalid_i <= 1\'b1; write_cs <= P_WRITE_RESP; end end P_WRITE_RESP: begin if (S_AXI_BREADY) begin s_axi_bvalid_i <= 1\'b0; s_axi_awready_i <= 1\'b1; write_cs <= P_WRITE_IDLE; end end endcase end end always @(posedge ACLK) begin if (~ARESETN) begin read_cs <= P_READ_IDLE; s_axi_arready_i <= 1\'b0; s_axi_rvalid_i <= 1\'b0; s_axi_rlast_i <= 1\'b0; s_axi_rid_i <= 0; read_cnt <= 0; end else begin case (read_cs) P_READ_IDLE: begin if (S_AXI_ARVALID & s_axi_arready_i) begin s_axi_arready_i <= 1\'b0; if (C_IGNORE_ID == 0) s_axi_rid_i <= S_AXI_ARID; read_cnt <= S_AXI_ARLEN; s_axi_rlast_i <= (S_AXI_ARLEN == 0); read_cs <= P_READ_START; end else begin s_axi_arready_i <= 1\'b1; end end P_READ_START: begin s_axi_rvalid_i <= 1\'b1; read_cs <= P_READ_DATA; end P_READ_DATA: begin if (S_AXI_RREADY) begin if (read_cnt == 0) begin s_axi_rvalid_i <= 1\'b0; s_axi_rlast_i <= 1\'b0; s_axi_arready_i <= 1\'b1; read_cs <= P_READ_IDLE; end else begin if (read_cnt == 1) begin s_axi_rlast_i <= 1\'b1; end read_cnt <= read_cnt - 1; end end end endcase end end end endgenerate endmodule `default_nettype wire
/***************************************************************************** * File : processing_system7_bfm_v2_0_axi_master.v * * Date : 2012-11 * * Description : Model that acts as PS AXI Master port interface. * It uses AXI3 Master BFM *****************************************************************************/ module processing_system7_bfm_v2_0_axi_master ( M_RESETN, M_ARVALID, M_AWVALID, M_BREADY, M_RREADY, M_WLAST, M_WVALID, M_ARID, M_AWID, M_WID, M_ARBURST, M_ARLOCK, M_ARSIZE, M_AWBURST, M_AWLOCK, M_AWSIZE, M_ARPROT, M_AWPROT, M_ARADDR, M_AWADDR, M_WDATA, M_ARCACHE, M_ARLEN, M_AWCACHE, M_AWLEN, M_ARQOS, // not connected to AXI BFM M_AWQOS, // not connected to AXI BFM M_WSTRB, M_ACLK, M_ARREADY, M_AWREADY, M_BVALID, M_RLAST, M_RVALID, M_WREADY, M_BID, M_RID, M_BRESP, M_RRESP, M_RDATA ); parameter enable_this_port = 0; parameter master_name = "Master"; parameter data_bus_width = 32; parameter address_bus_width = 32; parameter id_bus_width = 6; parameter max_outstanding_transactions = 8; parameter exclusive_access_supported = 0; parameter EXCL_ID = 12\'hC00; `include "processing_system7_bfm_v2_0_local_params.v" /* IDs for Masters // l2m1 (CPU000) 12\'b11_000_000_00_00 12\'b11_010_000_00_00 12\'b11_011_000_00_00 12\'b11_100_000_00_00 12\'b11_101_000_00_00 12\'b11_110_000_00_00 12\'b11_111_000_00_00 // l2m1 (CPU001) 12\'b11_000_001_00_00 12\'b11_010_001_00_00 12\'b11_011_001_00_00 12\'b11_100_001_00_00 12\'b11_101_001_00_00 12\'b11_110_001_00_00 12\'b11_111_001_00_00 */ input M_RESETN; output M_ARVALID; output M_AWVALID; output M_BREADY; output M_RREADY; output M_WLAST; output M_WVALID; output [id_bus_width-1:0] M_ARID; output [id_bus_width-1:0] M_AWID; output [id_bus_width-1:0] M_WID; output [axi_brst_type_width-1:0] M_ARBURST; output [axi_lock_width-1:0] M_ARLOCK; output [axi_size_width-1:0] M_ARSIZE; output [axi_brst_type_width-1:0] M_AWBURST; output [axi_lock_width-1:0] M_AWLOCK; output [axi_size_width-1:0] M_AWSIZE; output [axi_prot_width-1:0] M_ARPROT; output [axi_prot_width-1:0] M_AWPROT; output [address_bus_width-1:0] M_ARADDR; output [address_bus_width-1:0] M_AWADDR; output [data_bus_width-1:0] M_WDATA; output [axi_cache_width-1:0] M_ARCACHE; output [axi_len_width-1:0] M_ARLEN; output [axi_qos_width-1:0] M_ARQOS; // not connected to AXI BFM output [axi_cache_width-1:0] M_AWCACHE; output [axi_len_width-1:0] M_AWLEN; output [axi_qos_width-1:0] M_AWQOS; // not connected to AXI BFM output [(data_bus_width/8)-1:0] M_WSTRB; input M_ACLK; input M_ARREADY; input M_AWREADY; input M_BVALID; input M_RLAST; input M_RVALID; input M_WREADY; input [id_bus_width-1:0] M_BID; input [id_bus_width-1:0] M_RID; input [axi_rsp_width-1:0] M_BRESP; input [axi_rsp_width-1:0] M_RRESP; input [data_bus_width-1:0] M_RDATA; wire net_RESETN; wire net_RVALID; wire net_BVALID; reg DEBUG_INFO = 1\'b1; reg STOP_ON_ERROR = 1\'b1; integer use_id_no = 0; assign M_ARQOS = \'b0; assign M_AWQOS = \'b0; assign net_RESETN = M_RESETN; //ENABLE_THIS_PORT ? M_RESETN : 1\'b0; assign net_RVALID = enable_this_port ? M_RVALID : 1\'b0; assign net_BVALID = enable_this_port ? M_BVALID : 1\'b0; initial begin if(DEBUG_INFO) begin if(enable_this_port) $display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, master_name); else $display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, master_name); end end initial master.set_disable_reset_value_checks(1); initial begin repeat(2) @(posedge M_ACLK); if(!enable_this_port) begin master.set_channel_level_info(0); master.set_function_level_info(0); end master.RESPONSE_TIMEOUT = 0; end cdn_axi3_master_bfm #(master_name, data_bus_width, address_bus_width, id_bus_width, max_outstanding_transactions, exclusive_access_supported) master (.ACLK (M_ACLK), .ARESETn (net_RESETN), /// confirm this // Write Address Channel .AWID (M_AWID), .AWADDR (M_AWADDR), .AWLEN (M_AWLEN), .AWSIZE (M_AWSIZE), .AWBURST (M_AWBURST), .AWLOCK (M_AWLOCK), .AWCACHE (M_AWCACHE), .AWPROT (M_AWPROT), .AWVALID (M_AWVALID), .AWREADY (M_AWREADY), // Write Data Channel Signals. .WID (M_WID), .WDATA (M_WDATA), .WSTRB (M_WSTRB), .WLAST (M_WLAST), .WVALID (M_WVALID), .WREADY (M_WREADY), // Write Response Channel Signals. .BID (M_BID), .BRESP (M_BRESP), .BVALID (net_BVALID), .BREADY (M_BREADY), // Read Address Channel Signals. .ARID (M_ARID), .ARADDR (M_ARADDR), .ARLEN (M_ARLEN), .ARSIZE (M_ARSIZE), .ARBURST (M_ARBURST), .ARLOCK (M_ARLOCK), .ARCACHE (M_ARCACHE), .ARPROT (M_ARPROT), .ARVALID (M_ARVALID), .ARREADY (M_ARREADY), // Read Data Channel Signals. .RID (M_RID), .RDATA (M_RDATA), .RRESP (M_RRESP), .RLAST (M_RLAST), .RVALID (net_RVALID), .RREADY (M_RREADY)); /* Call to BFM APIs */ task automatic read_burst(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,output [(axi_mgp_data_width*axi_burst_len)-1:0] data, output [(axi_rsp_width*axi_burst_len)-1:0] response); if(enable_this_port)begin if(lck !== AXI_NRML) master.READ_BURST(EXCL_ID,addr,len,siz,burst,lck,cache,prot,data,response); else master.READ_BURST(get_id(1),addr,len,siz,burst,lck,cache,prot,data,response); end else begin $display("[%0d] : %0s : %0s : Port is disabled. \'read_burst\' will not be executed...",$time, DISP_ERR, master_name); if(STOP_ON_ERROR) $stop; end endtask task automatic write_burst(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response); if(enable_this_port)begin if(lck !== AXI_NRML) master.WRITE_BURST(EXCL_ID,addr,len,siz,burst,lck,cache,prot,data,datasize,response); else master.WRITE_BURST(get_id(1),addr,len,siz,burst,lck,cache,prot,data,datasize,response); end else begin $display("[%0d] : %0s : %0s : Port is disabled. \'write_burst\' will not be executed...",$time, DISP_ERR, master_name); if(STOP_ON_ERROR) $stop; end endtask task automatic write_burst_concurrent(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response); if(enable_this_port)begin if(lck !== AXI_NRML) master.WRITE_BURST_CONCURRENT(EXCL_ID,addr,len,siz,burst,lck,cache,prot,data,datasize,response); else master.WRITE_BURST_CONCURRENT(get_id(1),addr,len,siz,burst,lck,cache,prot,data,datasize,response); end else begin $display("[%0d] : %0s : %0s : Port is disabled. \'write_burst_concurrent\' will not be executed...",$time, DISP_ERR, master_name); if(STOP_ON_ERROR) $stop; end endtask /* local */ function automatic[id_bus_width-1:0] get_id; input dummy; begin case(use_id_no) // l2m1 (CPU000) 0 : get_id = 12\'b11_000_000_00_00; 1 : get_id = 12\'b11_010_000_00_00; 2 : get_id = 12\'b11_011_000_00_00; 3 : get_id = 12\'b11_100_000_00_00; 4 : get_id = 12\'b11_101_000_00_00; 5 : get_id = 12\'b11_110_000_00_00; 6 : get_id = 12\'b11_111_000_00_00; // l2m1 (CPU001) 7 : get_id = 12\'b11_000_001_00_00; 8 : get_id = 12\'b11_010_001_00_00; 9 : get_id = 12\'b11_011_001_00_00; 10 : get_id = 12\'b11_100_001_00_00; 11 : get_id = 12\'b11_101_001_00_00; 12 : get_id = 12\'b11_110_001_00_00; 13 : get_id = 12\'b11_111_001_00_00; endcase if(use_id_no == 13) use_id_no = 0; else use_id_no = use_id_no+1; end endfunction /* Write data from file */ task automatic write_from_file; input [(max_chars*8)-1:0] file_name; input [addr_width-1:0] start_addr; input [int_width-1:0] wr_size; output [axi_rsp_width-1:0] response; reg [axi_rsp_width-1:0] wresp,rwrsp; reg [addr_width-1:0] addr; reg [(axi_burst_len*data_bus_width)-1 : 0] wr_data; integer bytes; integer trnsfr_bytes; integer wr_fd; integer succ; integer trnsfr_lngth; reg concurrent; reg [id_bus_width-1:0] wr_id; reg [axi_size_width-1:0] siz; reg [axi_brst_type_width-1:0] burst; reg [axi_lock_width-1:0] lck; reg [axi_cache_width-1:0] cache; reg [axi_prot_width-1:0] prot; begin if(!enable_this_port) begin $display("[%0d] : %0s : %0s : Port is disabled. \'write_from_file\' will not be executed...",$time, DISP_ERR, master_name); if(STOP_ON_ERROR) $stop; end else begin siz = 2; burst = 1; lck = 0; cache = 0; prot = 0; addr = start_addr; bytes = wr_size; wresp = 0; concurrent = $random; if(bytes > (axi_burst_len * data_bus_width/8)) trnsfr_bytes = (axi_burst_len * data_bus_width/8); else trnsfr_bytes = bytes; if(bytes > (axi_burst_len * data_bus_width/8)) trnsfr_lngth = axi_burst_len-1; else if(bytes%(data_bus_width/8) == 0) trnsfr_lngth = bytes/(data_bus_width/8) - 1; else trnsfr_lngth = bytes/(data_bus_width/8); wr_id = get_id(1); wr_fd = $fopen(file_name,"r"); while (bytes > 0) begin repeat(axi_burst_len) begin /// get the data for 1 AXI burst transaction wr_data = wr_data >> data_bus_width; succ = $fscanf(wr_fd,"%h",wr_data[(axi_burst_len*data_bus_width)-1 :(axi_burst_len*data_bus_width)-data_bus_width ]); /// write as 4 bytes (data_bus_width) .. end if(concurrent) master.WRITE_BURST_CONCURRENT(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data, trnsfr_bytes, rwrsp); else master.WRITE_BURST(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data, trnsfr_bytes, rwrsp); bytes = bytes - trnsfr_bytes; addr = addr + trnsfr_bytes; if(bytes >= (axi_burst_len * data_bus_width/8) ) trnsfr_bytes = (axi_burst_len * data_bus_width/8); // else trnsfr_bytes = bytes; if(bytes > (axi_burst_len * data_bus_width/8)) trnsfr_lngth = axi_burst_len-1; else if(bytes%(data_bus_width/8) == 0) trnsfr_lngth = bytes/(data_bus_width/8) - 1; else trnsfr_lngth = bytes/(data_bus_width/8); wresp = wresp | rwrsp; end /// while response = wresp; end end endtask /* Read data to file */ task automatic read_to_file; input [(max_chars*8)-1:0] file_name; input [addr_width-1:0] start_addr; input [int_width-1:0] rd_size; output [axi_rsp_width-1:0] response; reg [axi_rsp_width-1:0] rresp, rrrsp; reg [addr_width-1:0] addr; integer bytes; integer trnsfr_lngth; reg [(axi_burst_len*data_bus_width)-1 :0] rd_data; integer rd_fd; reg [id_bus_width-1:0] rd_id; reg [axi_size_width-1:0] siz; reg [axi_brst_type_width-1:0] burst; reg [axi_lock_width-1:0] lck; reg [axi_cache_width-1:0] cache; reg [axi_prot_width-1:0] prot; begin if(!enable_this_port) begin $display("[%0d] : %0s : %0s : Port is disabled. \'read_to_file\' will not be executed...",$time, DISP_ERR, master_name); if(STOP_ON_ERROR) $stop; end else begin siz = 2; burst = 1; lck = 0; cache = 0; prot = 0; addr = start_addr; rresp = 0; bytes = rd_size; rd_id = get_id(1\'b1); if(bytes > (axi_burst_len * data_bus_width/8)) trnsfr_lngth = axi_burst_len-1; else if(bytes%(data_bus_width/8) == 0) trnsfr_lngth = bytes/(data_bus_width/8) - 1; else trnsfr_lngth = bytes/(data_bus_width/8); rd_fd = $fopen(file_name,"w"); while (bytes > 0) begin master.READ_BURST(rd_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, rd_data, rrrsp); repeat(trnsfr_lngth+1) begin $fdisplayh(rd_fd,rd_data[data_bus_width-1:0]); rd_data = rd_data >> data_bus_width; end addr = addr + (trnsfr_lngth+1)*4; if(bytes >= (axi_burst_len * data_bus_width/8) ) bytes = bytes - (axi_burst_len * data_bus_width/8); // else bytes = 0; if(bytes > (axi_burst_len * data_bus_width/8)) trnsfr_lngth = axi_burst_len-1; else if(bytes%(data_bus_width/8) == 0) trnsfr_lngth = bytes/(data_bus_width/8) - 1; else trnsfr_lngth = bytes/(data_bus_width/8); rresp = rresp | rrrsp; end /// while response = rresp; end end endtask /* Write data (used for transfer size <= 128 Bytes */ task automatic write_data; input [addr_width-1:0] start_addr; input [max_transfer_bytes_width:0] wr_size; input [(max_transfer_bytes*8)-1:0] w_data; output [axi_rsp_width-1:0] response; reg [axi_rsp_width-1:0] wresp,rwrsp; reg [addr_width-1:0] addr; reg [7:0] bytes,tmp_bytes; integer trnsfr_bytes; reg [(max_transfer_bytes*8)-1:0] wr_data; integer trnsfr_lngth; reg concurrent; reg [id_bus_width-1:0] wr_id; reg [axi_size_width-1:0] siz; reg [axi_brst_type_width-1:0] burst; reg [axi_lock_width-1:0] lck; reg [axi_cache_width-1:0] cache; reg [axi_prot_width-1:0] prot; integer pad_bytes; begin if(!enable_this_port) begin $display("[%0d] : %0s : %0s : Port is disabled. \'write_data\' will not be executed...",$time, DISP_ERR, master_name); if(STOP_ON_ERROR) $stop; end else begin addr = start_addr; bytes = wr_size; wresp = 0; wr_data = w_data; concurrent = $random; siz = 2; burst = 1; lck = 0; cache = 0; prot = 0; pad_bytes = start_addr[clogb2(data_bus_width/8)-1:0]; wr_id = get_id(1); if(bytes+pad_bytes > (data_bus_width/8*axi_burst_len)) begin /// for unaligned address trnsfr_bytes = (data_bus_width*axi_burst_len)/8 - pad_bytes;//start_addr[1:0]; trnsfr_lngth = axi_burst_len-1; end else begin trnsfr_bytes = bytes; tmp_bytes = bytes + pad_bytes;//start_addr[1:0]; if(tmp_bytes%(data_bus_width/8) == 0) trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1; else trnsfr_lngth = tmp_bytes/(data_bus_width/8); end while (bytes > 0) begin if(concurrent) master.WRITE_BURST_CONCURRENT(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data[(axi_burst_len*data_bus_width)-1:0], trnsfr_bytes, rwrsp); else master.WRITE_BURST(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data[(axi_burst_len*data_bus_width)-1:0], trnsfr_bytes, rwrsp); wr_data = wr_data >> (trnsfr_bytes*8); bytes = bytes - trnsfr_bytes; addr = addr + trnsfr_bytes; if(bytes > (axi_burst_len * data_bus_width/8)) begin trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0]; trnsfr_lngth = axi_burst_len-1; end else begin trnsfr_bytes = bytes; tmp_bytes = bytes + pad_bytes;//start_addr[1:0]; if(tmp_bytes%(data_bus_width/8) == 0) trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1; else trnsfr_lngth = tmp_bytes/(data_bus_width/8); end wresp = wresp | rwrsp; end /// while response = wresp; end end endtask /* Read data (used for transfer size <= 128 Bytes */ task automatic read_data; input [addr_width-1:0] start_addr; input [max_transfer_bytes_width:0] rd_size; output [(max_transfer_bytes*8)-1:0] r_data; output [axi_rsp_width-1:0] response; reg [axi_rsp_width-1:0] rresp,rdrsp; reg [addr_width-1:0] addr; reg [max_transfer_bytes_width:0] bytes,tmp_bytes; integer trnsfr_bytes; reg [(max_transfer_bytes*8)-1 : 0] rd_data; reg [(axi_burst_len*data_bus_width)-1:0] rcv_rd_data; integer total_rcvd_bytes; integer trnsfr_lngth; integer i; reg [id_bus_width-1:0] rd_id; reg [axi_size_width-1:0] siz; reg [axi_brst_type_width-1:0] burst; reg [axi_lock_width-1:0] lck; reg [axi_cache_width-1:0] cache; reg [axi_prot_width-1:0] prot; integer pad_bytes; begin if(!enable_this_port) begin $display("[%0d] : %0s : %0s : Port is disabled. \'read_data\' will not be executed...",$time, DISP_ERR, master_name); if(STOP_ON_ERROR) $stop; end else begin addr = start_addr; bytes = rd_size; rresp = 0; total_rcvd_bytes = 0; rd_data = 0; rd_id = get_id(1\'b1); siz = 2; burst = 1; lck = 0; cache = 0; prot = 0; pad_bytes = start_addr[clogb2(data_bus_width/8)-1:0]; if(bytes+ pad_bytes > (axi_burst_len * data_bus_width/8)) begin /// for unaligned address trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0]; trnsfr_lngth = axi_burst_len-1; end else begin trnsfr_bytes = bytes; tmp_bytes = bytes + pad_bytes;//start_addr[1:0]; if(tmp_bytes%(data_bus_width/8) == 0) trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1; else trnsfr_lngth = tmp_bytes/(data_bus_width/8); end while (bytes > 0) begin master.READ_BURST(rd_id,addr, trnsfr_lngth, siz, burst, lck, cache, prot, rcv_rd_data, rdrsp); for(i = 0; i < trnsfr_bytes; i = i+1) begin rd_data = rd_data >> 8; rd_data[(max_transfer_bytes*8)-1 : (max_transfer_bytes*8)-8] = rcv_rd_data[7:0]; rcv_rd_data = rcv_rd_data >> 8; total_rcvd_bytes = total_rcvd_bytes+1; end bytes = bytes - trnsfr_bytes; addr = addr + trnsfr_bytes; if(bytes > (axi_burst_len * data_bus_width/8)) begin trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0]; trnsfr_lngth = 15; end else begin trnsfr_bytes = bytes; tmp_bytes = bytes + pad_bytes;//start_addr[1:0]; if(tmp_bytes%(data_bus_width/8) == 0) trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1; else trnsfr_lngth = tmp_bytes/(data_bus_width/8); end rresp = rresp | rdrsp; end /// while rd_data = rd_data >> (max_transfer_bytes - total_rcvd_bytes)*8; r_data = rd_data; response = rresp; end end endtask /* Wait Register Update in PL */ /* Issue a series of 1 burst length reads until the expected data pattern is received */ task automatic wait_reg_update; input [addr_width-1:0] addri; input [data_width-1:0] datai; input [data_width-1:0] maski; input [int_width-1:0] time_interval; input [int_width-1:0] time_out; output [data_width-1:0] data_o; output upd_done; reg [addr_width-1:0] addr; reg [data_width-1:0] data_i; reg [data_width-1:0] mask_i; integer time_int; integer timeout; reg [axi_rsp_width-1:0] rdrsp; reg [id_bus_width-1:0] rd_id; reg [axi_size_width-1:0] siz; reg [axi_brst_type_width-1:0] burst; reg [axi_lock_width-1:0] lck; reg [axi_cache_width-1:0] cache; reg [axi_prot_width-1:0] prot; reg [data_width-1:0] rcv_data; integer trnsfr_lngth; reg rd_loop; reg timed_out; integer i; integer cycle_cnt; begin addr = addri; data_i = datai; mask_i = maski; time_int = time_interval; timeout = time_out; timed_out = 0; cycle_cnt = 0; if(!enable_this_port) begin $display("[%0d] : %0s : %0s : Port is disabled. \'wait_reg_update\' will not be executed...",$time, DISP_ERR, master_name); upd_done = 0; if(STOP_ON_ERROR) $stop; end else begin rd_id = get_id(1\'b1); siz = 2; burst = 1; lck = 0; cache = 0; prot = 0; trnsfr_lngth = 0; rd_loop = 1; fork begin while(!timed_out) begin cycle_cnt = cycle_cnt + 1; if(cycle_cnt >= timeout) timed_out = 1; @(posedge M_ACLK); end end begin while (rd_loop) begin if(DEBUG_INFO) $display("[%0d] : %0s : %0s : Reading Register mapped at Address(0x%0h) ",$time, master_name, DISP_INFO, addr); master.READ_BURST(rd_id,addr, trnsfr_lngth, siz, burst, lck, cache, prot, rcv_data, rdrsp); if(DEBUG_INFO) $display("[%0d] : %0s : %0s : Reading Register returned (0x%0h) ",$time, master_name, DISP_INFO, rcv_data); if(((rcv_data & !mask_i) === (data_i & !mask_i)) | timed_out) rd_loop = 0; else repeat(time_int) @(posedge M_ACLK); end /// while end join data_o = rcv_data & !mask_i; if(timed_out) begin $display("[%0d] : %0s : %0s : \'wait_reg_update\' timed out ... Register is not updated ",$time, DISP_ERR, master_name); if(STOP_ON_ERROR) $stop; end else upd_done = 1; end end endtask endmodule
/////////////////////////////////////////////////////////////////////////////// // // File name: axi_protocol_converter_v2_1_b2s_b_channel.v // /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_protocol_converter_v2_1_b2s_b_channel # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // Width of ID signals. // Range: >= 1. parameter integer C_ID_WIDTH = 4 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire clk, input wire reset, // AXI signals output wire [C_ID_WIDTH-1:0] s_bid, output wire [1:0] s_bresp, output wire s_bvalid, input wire s_bready, input wire [1:0] m_bresp, input wire m_bvalid, output wire m_bready, // Signals to/from the axi_protocol_converter_v2_1_b2s_aw_channel modules input wire b_push, input wire [C_ID_WIDTH-1:0] b_awid, input wire [7:0] b_awlen, input wire b_resp_rdy, output wire b_full ); //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// // AXI protocol responses: localparam [1:0] LP_RESP_OKAY = 2\'b00; localparam [1:0] LP_RESP_EXOKAY = 2\'b01; localparam [1:0] LP_RESP_SLVERROR = 2\'b10; localparam [1:0] LP_RESP_DECERR = 2\'b11; // FIFO settings localparam P_WIDTH = C_ID_WIDTH + 8; localparam P_DEPTH = 4; localparam P_AWIDTH = 2; localparam P_RWIDTH = 2; localparam P_RDEPTH = 4; localparam P_RAWIDTH = 2; //////////////////////////////////////////////////////////////////////////////// // Wire and register declarations //////////////////////////////////////////////////////////////////////////////// reg bvalid_i; wire [C_ID_WIDTH-1:0] bid_i; wire shandshake; reg shandshake_r; wire mhandshake; reg mhandshake_r; wire b_empty; wire bresp_full; wire bresp_empty; wire [7:0] b_awlen_i; reg [7:0] bresp_cnt; reg [1:0] s_bresp_acc; wire [1:0] s_bresp_acc_r; reg [1:0] s_bresp_i; wire need_to_update_bresp; wire bresp_push; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// // assign AXI outputs assign s_bid = bid_i; assign s_bresp = s_bresp_acc_r; assign s_bvalid = bvalid_i; assign shandshake = s_bvalid & s_bready; assign mhandshake = m_bvalid & m_bready; always @(posedge clk) begin if (reset | shandshake) begin bvalid_i <= 1\'b0; end else if (~b_empty & ~shandshake_r & ~bresp_empty) begin bvalid_i <= 1\'b1; end end always @(posedge clk) begin shandshake_r <= shandshake; mhandshake_r <= mhandshake; end axi_protocol_converter_v2_1_b2s_simple_fifo #( .C_WIDTH (P_WIDTH), .C_AWIDTH (P_AWIDTH), .C_DEPTH (P_DEPTH) ) bid_fifo_0 ( .clk ( clk ) , .rst ( reset ) , .wr_en ( b_push ) , .rd_en ( shandshake_r ) , .din ( {b_awid, b_awlen} ) , .dout ( {bid_i, b_awlen_i}) , .a_full ( ) , .full ( b_full ) , .a_empty ( ) , .empty ( b_empty ) ); assign m_bready = ~mhandshake_r & bresp_empty; ///////////////////////////////////////////////////////////////////////////// // Update if more critical. assign need_to_update_bresp = ( m_bresp > s_bresp_acc ); // Select accumultated or direct depending on setting. always @( * ) begin if ( need_to_update_bresp ) begin s_bresp_i = m_bresp; end else begin s_bresp_i = s_bresp_acc; end end ///////////////////////////////////////////////////////////////////////////// // Accumulate MI-side BRESP. always @ (posedge clk) begin if (reset | bresp_push ) begin s_bresp_acc <= LP_RESP_OKAY; end else if ( mhandshake ) begin s_bresp_acc <= s_bresp_i; end end assign bresp_push = ( mhandshake_r ) & (bresp_cnt == b_awlen_i) & ~b_empty; always @ (posedge clk) begin if (reset | bresp_push ) begin bresp_cnt <= 8\'h00; end else if ( mhandshake_r ) begin bresp_cnt <= bresp_cnt + 1\'b1; end end axi_protocol_converter_v2_1_b2s_simple_fifo #( .C_WIDTH (P_RWIDTH), .C_AWIDTH (P_RAWIDTH), .C_DEPTH (P_RDEPTH) ) bresp_fifo_0 ( .clk ( clk ) , .rst ( reset ) , .wr_en ( bresp_push ) , .rd_en ( shandshake_r ) , .din ( s_bresp_acc ) , .dout ( s_bresp_acc_r) , .a_full ( ) , .full ( bresp_full ) , .a_empty ( ) , .empty ( bresp_empty ) ); endmodule `default_nettype wire
/////////////////////////////////////////////////////////////////////////////// // // File name: axi_protocol_converter_v2_1_b2s_cmd_translator.v // // Description: // INCR and WRAP burst modes are decoded in parallel and then the output is // chosen based on the AxBURST value. FIXED burst mode is not supported and // is mapped to the INCR command instead. // // Specifications: // /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_protocol_converter_v2_1_b2s_cmd_translator # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // Width of AxADDR // Range: 32. parameter integer C_AXI_ADDR_WIDTH = 32 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire clk , input wire reset , input wire [C_AXI_ADDR_WIDTH-1:0] s_axaddr , input wire [7:0] s_axlen , input wire [2:0] s_axsize , input wire [1:0] s_axburst , input wire s_axhandshake , output wire [C_AXI_ADDR_WIDTH-1:0] m_axaddr , output wire incr_burst , // Connections to/from fsm module // signal to increment to the next mc transaction input wire next , // signal to the fsm there is another transaction required output wire next_pending ); //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// // AXBURST decodes localparam P_AXBURST_FIXED = 2\'b00; localparam P_AXBURST_INCR = 2\'b01; localparam P_AXBURST_WRAP = 2\'b10; //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// wire [C_AXI_ADDR_WIDTH-1:0] incr_cmd_byte_addr; wire incr_next_pending; wire [C_AXI_ADDR_WIDTH-1:0] wrap_cmd_byte_addr; wire wrap_next_pending; reg sel_first; reg s_axburst_eq1; reg s_axburst_eq0; reg sel_first_i; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// // INCR and WRAP translations are calcuated in independently, select the one // for our transactions // right shift by the UI width to the DRAM width ratio assign m_axaddr = (s_axburst == P_AXBURST_FIXED) ? s_axaddr : (s_axburst == P_AXBURST_INCR) ? incr_cmd_byte_addr : wrap_cmd_byte_addr; assign incr_burst = (s_axburst[1]) ? 1\'b0 : 1\'b1; // Indicates if we are on the first transaction of a mc translation with more // than 1 transaction. always @(posedge clk) begin if (reset | s_axhandshake) begin sel_first <= 1\'b1; end else if (next) begin sel_first <= 1\'b0; end end always @( * ) begin if (reset | s_axhandshake) begin sel_first_i = 1\'b1; end else if (next) begin sel_first_i = 1\'b0; end else begin sel_first_i = sel_first; end end assign next_pending = s_axburst[1] ? s_axburst_eq1 : s_axburst_eq0; always @(posedge clk) begin if (sel_first_i || s_axburst[1]) begin s_axburst_eq1 <= wrap_next_pending; end else begin s_axburst_eq1 <= incr_next_pending; end if (sel_first_i || !s_axburst[1]) begin s_axburst_eq0 <= incr_next_pending; end else begin s_axburst_eq0 <= wrap_next_pending; end end axi_protocol_converter_v2_1_b2s_incr_cmd #( .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH) ) incr_cmd_0 ( .clk ( clk ) , .reset ( reset ) , .axaddr ( s_axaddr ) , .axlen ( s_axlen ) , .axsize ( s_axsize ) , .axhandshake ( s_axhandshake ) , .cmd_byte_addr ( incr_cmd_byte_addr ) , .next ( next ) , .next_pending ( incr_next_pending ) ); axi_protocol_converter_v2_1_b2s_wrap_cmd #( .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH) ) wrap_cmd_0 ( .clk ( clk ) , .reset ( reset ) , .axaddr ( s_axaddr ) , .axlen ( s_axlen ) , .axsize ( s_axsize ) , .axhandshake ( s_axhandshake ) , .cmd_byte_addr ( wrap_cmd_byte_addr ) , .next ( next ) , .next_pending ( wrap_next_pending ) ); endmodule `default_nettype wire
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: // Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_carry logic. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module generic_baseblocks_v2_1_comparator_sel_static # ( parameter C_FAMILY = "virtex6", // FPGA Family. Current version: virtex6 or spartan6. parameter C_VALUE = 4\'b0, // Static value to compare against. parameter integer C_DATA_WIDTH = 4 // Data width for comparator. ) ( input wire CIN, input wire S, input wire [C_DATA_WIDTH-1:0] A, input wire [C_DATA_WIDTH-1:0] B, output wire COUT ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// // Generate variable for bit vector. genvar bit_cnt; ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Bits per LUT for this architecture. localparam integer C_BITS_PER_LUT = 2; // Constants for packing levels. localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT; // localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT : C_DATA_WIDTH; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// wire [C_FIX_DATA_WIDTH-1:0] a_local; wire [C_FIX_DATA_WIDTH-1:0] b_local; wire [C_FIX_DATA_WIDTH-1:0] v_local; wire [C_NUM_LUT-1:0] sel; wire [C_NUM_LUT:0] carry_local; ///////////////////////////////////////////////////////////////////////////// // ///////////////////////////////////////////////////////////////////////////// generate // Assign input to local vectors. assign carry_local[0] = CIN; // Extend input data to fit. if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}}; assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}}; assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}}; end else begin : NO_EXTENDED_DATA assign a_local = A; assign b_local = B; assign v_local = C_VALUE; end // Instantiate one generic_baseblocks_v2_1_carry and per level. for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL // Create the local select signal assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1\'b0 ) ) | ( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1\'b1 ) ); // Instantiate each LUT level. generic_baseblocks_v2_1_carry_and # ( .C_FAMILY(C_FAMILY) ) compare_inst ( .COUT (carry_local[bit_cnt+1]), .CIN (carry_local[bit_cnt]), .S (sel[bit_cnt]) ); end // end for bit_cnt // Assign output from local vector. assign COUT = carry_local[C_NUM_LUT]; endgenerate endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_axi_hp.v * * Date : 2012-11 * * Description : Connections for AXI HP ports * *****************************************************************************/ /* AXI Slave HP0 */ processing_system7_bfm_v2_0_afi_slave #( C_USE_S_AXI_HP0, // enable axi_hp0_name, // name C_S_AXI_HP0_DATA_WIDTH, // data width addr_width, /// address width axi_hp_id_width, // ID width C_S_AXI_HP0_BASEADDR, // slave base address C_S_AXI_HP0_HIGHADDR, // slave size axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports axi_slv_excl_support) // Exclusive access support S_AXI_HP0(.S_RESETN (net_axi_hp0_rstn), .S_ACLK (S_AXI_HP0_ACLK), // Write Address channel .S_AWID (S_AXI_HP0_AWID), .S_AWADDR (S_AXI_HP0_AWADDR), .S_AWLEN (S_AXI_HP0_AWLEN), .S_AWSIZE (S_AXI_HP0_AWSIZE), .S_AWBURST (S_AXI_HP0_AWBURST), .S_AWLOCK (S_AXI_HP0_AWLOCK), .S_AWCACHE (S_AXI_HP0_AWCACHE), .S_AWPROT (S_AXI_HP0_AWPROT), .S_AWVALID (S_AXI_HP0_AWVALID), .S_AWREADY (S_AXI_HP0_AWREADY), // Write Data channel signals. .S_WID (S_AXI_HP0_WID), .S_WDATA (S_AXI_HP0_WDATA), .S_WSTRB (S_AXI_HP0_WSTRB), .S_WLAST (S_AXI_HP0_WLAST), .S_WVALID (S_AXI_HP0_WVALID), .S_WREADY (S_AXI_HP0_WREADY), // Write Response channel signals. .S_BID (S_AXI_HP0_BID), .S_BRESP (S_AXI_HP0_BRESP), .S_BVALID (S_AXI_HP0_BVALID), .S_BREADY (S_AXI_HP0_BREADY), // Read Address channel signals. .S_ARID (S_AXI_HP0_ARID), .S_ARADDR (S_AXI_HP0_ARADDR), .S_ARLEN (S_AXI_HP0_ARLEN), .S_ARSIZE (S_AXI_HP0_ARSIZE), .S_ARBURST (S_AXI_HP0_ARBURST), .S_ARLOCK (S_AXI_HP0_ARLOCK), .S_ARCACHE (S_AXI_HP0_ARCACHE), .S_ARPROT (S_AXI_HP0_ARPROT), .S_ARVALID (S_AXI_HP0_ARVALID), .S_ARREADY (S_AXI_HP0_ARREADY), // Read Data channel signals. .S_RID (S_AXI_HP0_RID), .S_RDATA (S_AXI_HP0_RDATA), .S_RRESP (S_AXI_HP0_RRESP), .S_RLAST (S_AXI_HP0_RLAST), .S_RVALID (S_AXI_HP0_RVALID), .S_RREADY (S_AXI_HP0_RREADY), // Side band signals .S_AWQOS (S_AXI_HP0_AWQOS), .S_ARQOS (S_AXI_HP0_ARQOS), // these are needed only for HP ports .S_RDISSUECAP1_EN (S_AXI_HP0_RDISSUECAP1_EN), .S_WRISSUECAP1_EN (S_AXI_HP0_WRISSUECAP1_EN), .S_RCOUNT (S_AXI_HP0_RCOUNT), .S_WCOUNT (S_AXI_HP0_WCOUNT), .S_RACOUNT (S_AXI_HP0_RACOUNT), .S_WACOUNT (S_AXI_HP0_WACOUNT), .SW_CLK (net_sw_clk), .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp0), .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp0), .WR_DATA (net_wr_data_hp0), .WR_ADDR (net_wr_addr_hp0), .WR_BYTES (net_wr_bytes_hp0), .WR_DATA_VALID_DDR (net_wr_dv_ddr_hp0), .WR_DATA_VALID_OCM (net_wr_dv_ocm_hp0), .WR_QOS (net_wr_qos_hp0), .RD_REQ_DDR (net_rd_req_ddr_hp0), .RD_REQ_OCM (net_rd_req_ocm_hp0), .RD_ADDR (net_rd_addr_hp0), .RD_DATA_DDR (net_rd_data_ddr_hp0), .RD_DATA_OCM (net_rd_data_ocm_hp0), .RD_BYTES (net_rd_bytes_hp0), .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp0), .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp0), .RD_QOS (net_rd_qos_hp0) ); /* AXI Slave HP1 */ processing_system7_bfm_v2_0_afi_slave #( C_USE_S_AXI_HP1, // enable axi_hp1_name, // name C_S_AXI_HP1_DATA_WIDTH, // data width addr_width, /// address width axi_hp_id_width, // ID width C_S_AXI_HP1_BASEADDR, // slave base address C_S_AXI_HP1_HIGHADDR, // Slave size axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports axi_slv_excl_support) // Exclusive access support S_AXI_HP1(.S_RESETN (net_axi_hp1_rstn), .S_ACLK (S_AXI_HP1_ACLK), // Write Address channel .S_AWID (S_AXI_HP1_AWID), .S_AWADDR (S_AXI_HP1_AWADDR), .S_AWLEN (S_AXI_HP1_AWLEN), .S_AWSIZE (S_AXI_HP1_AWSIZE), .S_AWBURST (S_AXI_HP1_AWBURST), .S_AWLOCK (S_AXI_HP1_AWLOCK), .S_AWCACHE (S_AXI_HP1_AWCACHE), .S_AWPROT (S_AXI_HP1_AWPROT), .S_AWVALID (S_AXI_HP1_AWVALID), .S_AWREADY (S_AXI_HP1_AWREADY), // Write Data channel signals. .S_WID (S_AXI_HP1_WID), .S_WDATA (S_AXI_HP1_WDATA), .S_WSTRB (S_AXI_HP1_WSTRB), .S_WLAST (S_AXI_HP1_WLAST), .S_WVALID (S_AXI_HP1_WVALID), .S_WREADY (S_AXI_HP1_WREADY), // Write Response channel signals. .S_BID (S_AXI_HP1_BID), .S_BRESP (S_AXI_HP1_BRESP), .S_BVALID (S_AXI_HP1_BVALID), .S_BREADY (S_AXI_HP1_BREADY), // Read Address channel signals. .S_ARID (S_AXI_HP1_ARID), .S_ARADDR (S_AXI_HP1_ARADDR), .S_ARLEN (S_AXI_HP1_ARLEN), .S_ARSIZE (S_AXI_HP1_ARSIZE), .S_ARBURST (S_AXI_HP1_ARBURST), .S_ARLOCK (S_AXI_HP1_ARLOCK), .S_ARCACHE (S_AXI_HP1_ARCACHE), .S_ARPROT (S_AXI_HP1_ARPROT), .S_ARVALID (S_AXI_HP1_ARVALID), .S_ARREADY (S_AXI_HP1_ARREADY), // Read Data channel signals. .S_RID (S_AXI_HP1_RID), .S_RDATA (S_AXI_HP1_RDATA), .S_RRESP (S_AXI_HP1_RRESP), .S_RLAST (S_AXI_HP1_RLAST), .S_RVALID (S_AXI_HP1_RVALID), .S_RREADY (S_AXI_HP1_RREADY), // Side band signals .S_AWQOS (S_AXI_HP1_AWQOS), .S_ARQOS (S_AXI_HP1_ARQOS), // these are needed only for HP ports .S_RDISSUECAP1_EN (S_AXI_HP1_RDISSUECAP1_EN), .S_WRISSUECAP1_EN (S_AXI_HP1_WRISSUECAP1_EN), .S_RCOUNT (S_AXI_HP1_RCOUNT), .S_WCOUNT (S_AXI_HP1_WCOUNT), .S_RACOUNT (S_AXI_HP1_RACOUNT), .S_WACOUNT (S_AXI_HP1_WACOUNT), .SW_CLK (net_sw_clk), .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp1), .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp1), .WR_DATA (net_wr_data_hp1), .WR_ADDR (net_wr_addr_hp1), .WR_BYTES (net_wr_bytes_hp1), .WR_DATA_VALID_DDR (net_wr_dv_ddr_hp1), .WR_DATA_VALID_OCM (net_wr_dv_ocm_hp1), .WR_QOS (net_wr_qos_hp1), .RD_REQ_DDR (net_rd_req_ddr_hp1), .RD_REQ_OCM (net_rd_req_ocm_hp1), .RD_ADDR (net_rd_addr_hp1), .RD_DATA_DDR (net_rd_data_ddr_hp1), .RD_DATA_OCM (net_rd_data_ocm_hp1), .RD_BYTES (net_rd_bytes_hp1), .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp1), .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp1), .RD_QOS (net_rd_qos_hp1) ); /* AXI Slave HP2 */ processing_system7_bfm_v2_0_afi_slave #( C_USE_S_AXI_HP2, // enable axi_hp2_name, // name C_S_AXI_HP2_DATA_WIDTH, // data width addr_width, /// address width axi_hp_id_width, // ID width C_S_AXI_HP2_BASEADDR, // slave base address C_S_AXI_HP2_HIGHADDR, // SLave size axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports axi_slv_excl_support) // Exclusive access support S_AXI_HP2(.S_RESETN (net_axi_hp2_rstn), .S_ACLK (S_AXI_HP2_ACLK), // Write Address channel .S_AWID (S_AXI_HP2_AWID), .S_AWADDR (S_AXI_HP2_AWADDR), .S_AWLEN (S_AXI_HP2_AWLEN), .S_AWSIZE (S_AXI_HP2_AWSIZE), .S_AWBURST (S_AXI_HP2_AWBURST), .S_AWLOCK (S_AXI_HP2_AWLOCK), .S_AWCACHE (S_AXI_HP2_AWCACHE), .S_AWPROT (S_AXI_HP2_AWPROT), .S_AWVALID (S_AXI_HP2_AWVALID), .S_AWREADY (S_AXI_HP2_AWREADY), // Write Data channel signals. .S_WID (S_AXI_HP2_WID), .S_WDATA (S_AXI_HP2_WDATA), .S_WSTRB (S_AXI_HP2_WSTRB), .S_WLAST (S_AXI_HP2_WLAST), .S_WVALID (S_AXI_HP2_WVALID), .S_WREADY (S_AXI_HP2_WREADY), // Write Response channel signals. .S_BID (S_AXI_HP2_BID), .S_BRESP (S_AXI_HP2_BRESP), .S_BVALID (S_AXI_HP2_BVALID), .S_BREADY (S_AXI_HP2_BREADY), // Read Address channel signals. .S_ARID (S_AXI_HP2_ARID), .S_ARADDR (S_AXI_HP2_ARADDR), .S_ARLEN (S_AXI_HP2_ARLEN), .S_ARSIZE (S_AXI_HP2_ARSIZE), .S_ARBURST (S_AXI_HP2_ARBURST), .S_ARLOCK (S_AXI_HP2_ARLOCK), .S_ARCACHE (S_AXI_HP2_ARCACHE), .S_ARPROT (S_AXI_HP2_ARPROT), .S_ARVALID (S_AXI_HP2_ARVALID), .S_ARREADY (S_AXI_HP2_ARREADY), // Read Data channel signals. .S_RID (S_AXI_HP2_RID), .S_RDATA (S_AXI_HP2_RDATA), .S_RRESP (S_AXI_HP2_RRESP), .S_RLAST (S_AXI_HP2_RLAST), .S_RVALID (S_AXI_HP2_RVALID), .S_RREADY (S_AXI_HP2_RREADY), // Side band signals .S_AWQOS (S_AXI_HP2_AWQOS), .S_ARQOS (S_AXI_HP2_ARQOS), // these are needed only for HP ports .S_RDISSUECAP1_EN (S_AXI_HP2_RDISSUECAP1_EN), .S_WRISSUECAP1_EN (S_AXI_HP2_WRISSUECAP1_EN), .S_RCOUNT (S_AXI_HP2_RCOUNT), .S_WCOUNT (S_AXI_HP2_WCOUNT), .S_RACOUNT (S_AXI_HP2_RACOUNT), .S_WACOUNT (S_AXI_HP2_WACOUNT), .SW_CLK (net_sw_clk), .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp2), .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp2), .WR_DATA (net_wr_data_hp2), .WR_ADDR (net_wr_addr_hp2), .WR_BYTES (net_wr_bytes_hp2), .WR_DATA_VALID_DDR (net_wr_dv_ddr_hp2), .WR_DATA_VALID_OCM (net_wr_dv_ocm_hp2), .WR_QOS (net_wr_qos_hp2), .RD_REQ_DDR (net_rd_req_ddr_hp2), .RD_REQ_OCM (net_rd_req_ocm_hp2), .RD_ADDR (net_rd_addr_hp2), .RD_DATA_DDR (net_rd_data_ddr_hp2), .RD_DATA_OCM (net_rd_data_ocm_hp2), .RD_BYTES (net_rd_bytes_hp2), .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp2), .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp2), .RD_QOS (net_rd_qos_hp2) ); /* AXI Slave HP3 */ processing_system7_bfm_v2_0_afi_slave #( C_USE_S_AXI_HP3, // enable axi_hp3_name, // name C_S_AXI_HP3_DATA_WIDTH, // data width addr_width, /// address width axi_hp_id_width, // ID width C_S_AXI_HP3_BASEADDR, // slave base address C_S_AXI_HP3_HIGHADDR, // SLave size axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports axi_slv_excl_support) // Exclusive access support S_AXI_HP3(.S_RESETN (net_axi_hp3_rstn), .S_ACLK (S_AXI_HP3_ACLK), // Write ADDRESS CHANNEL .S_AWID (S_AXI_HP3_AWID), .S_AWADDR (S_AXI_HP3_AWADDR), .S_AWLEN (S_AXI_HP3_AWLEN), .S_AWSIZE (S_AXI_HP3_AWSIZE), .S_AWBURST (S_AXI_HP3_AWBURST), .S_AWLOCK (S_AXI_HP3_AWLOCK), .S_AWCACHE (S_AXI_HP3_AWCACHE), .S_AWPROT (S_AXI_HP3_AWPROT), .S_AWVALID (S_AXI_HP3_AWVALID), .S_AWREADY (S_AXI_HP3_AWREADY), // Write Data channel signals. .S_WID (S_AXI_HP3_WID), .S_WDATA (S_AXI_HP3_WDATA), .S_WSTRB (S_AXI_HP3_WSTRB), .S_WLAST (S_AXI_HP3_WLAST), .S_WVALID (S_AXI_HP3_WVALID), .S_WREADY (S_AXI_HP3_WREADY), // Write Response channel signals. .S_BID (S_AXI_HP3_BID), .S_BRESP (S_AXI_HP3_BRESP), .S_BVALID (S_AXI_HP3_BVALID), .S_BREADY (S_AXI_HP3_BREADY), // Read Address channel signals. .S_ARID (S_AXI_HP3_ARID), .S_ARADDR (S_AXI_HP3_ARADDR), .S_ARLEN (S_AXI_HP3_ARLEN), .S_ARSIZE (S_AXI_HP3_ARSIZE), .S_ARBURST (S_AXI_HP3_ARBURST), .S_ARLOCK (S_AXI_HP3_ARLOCK), .S_ARCACHE (S_AXI_HP3_ARCACHE), .S_ARPROT (S_AXI_HP3_ARPROT), .S_ARVALID (S_AXI_HP3_ARVALID), .S_ARREADY (S_AXI_HP3_ARREADY), // Read Data channel signals. .S_RID (S_AXI_HP3_RID), .S_RDATA (S_AXI_HP3_RDATA), .S_RRESP (S_AXI_HP3_RRESP), .S_RLAST (S_AXI_HP3_RLAST), .S_RVALID (S_AXI_HP3_RVALID), .S_RREADY (S_AXI_HP3_RREADY), // Side band signals .S_AWQOS (S_AXI_HP3_AWQOS), .S_ARQOS (S_AXI_HP3_ARQOS), // these are needed only for HP ports .S_RDISSUECAP1_EN (S_AXI_HP3_RDISSUECAP1_EN), .S_WRISSUECAP1_EN (S_AXI_HP3_WRISSUECAP1_EN), .S_RCOUNT (S_AXI_HP3_RCOUNT), .S_WCOUNT (S_AXI_HP3_WCOUNT), .S_RACOUNT (S_AXI_HP3_RACOUNT), .S_WACOUNT (S_AXI_HP3_WACOUNT), .SW_CLK (net_sw_clk), .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp3), .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp3), .WR_DATA (net_wr_data_hp3), .WR_ADDR (net_wr_addr_hp3), .WR_BYTES (net_wr_bytes_hp3), .WR_DATA_VALID_DDR (net_wr_dv_ddr_hp3), .WR_DATA_VALID_OCM (net_wr_dv_ocm_hp3), .WR_QOS (net_wr_qos_hp3), .RD_REQ_DDR (net_rd_req_ddr_hp3), .RD_REQ_OCM (net_rd_req_ocm_hp3), .RD_ADDR (net_rd_addr_hp3), .RD_DATA_DDR (net_rd_data_ddr_hp3), .RD_DATA_OCM (net_rd_data_ocm_hp3), .RD_BYTES (net_rd_bytes_hp3), .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp3), .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp3), .RD_QOS (net_rd_qos_hp3) );
// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // Description: SRL based FIFO for AXIS/AXI Channels. //-------------------------------------------------------------------------- `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_infrastructure_v1_1_axic_srl_fifo #( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// parameter C_FAMILY = "virtex7", parameter integer C_PAYLOAD_WIDTH = 1, parameter integer C_FIFO_DEPTH = 16 // Range: 4-16. ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire aclk, // Clock input wire aresetn, // Reset input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data input wire s_valid, // Input data valid output reg s_ready, // Input data ready output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data output reg m_valid, // Output data valid input wire m_ready // Output data ready ); //////////////////////////////////////////////////////////////////////////////// // Functions //////////////////////////////////////////////////////////////////////////////// // ceiling logb2 function integer f_clogb2 (input integer size); integer s; begin s = size; s = s - 1; for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1) s = s >> 1; end endfunction // clogb2 //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH); //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index; wire [4-1:0] fifo_addr; wire push; wire pop ; reg areset_r1; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// always @(posedge aclk) begin areset_r1 <= ~aresetn; end always @(posedge aclk) begin if (~aresetn) begin fifo_index <= {LP_LOG_FIFO_DEPTH{1\'b1}}; end else begin fifo_index <= push & ~pop ? fifo_index + 1\'b1 : ~push & pop ? fifo_index - 1\'b1 : fifo_index; end end assign push = s_valid & s_ready; always @(posedge aclk) begin if (~aresetn) begin s_ready <= 1\'b0; end else begin s_ready <= areset_r1 ? 1\'b1 : push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2\'d2)) ? 1\'b0 : ~push & pop ? 1\'b1 : s_ready; end end assign pop = m_valid & m_ready; always @(posedge aclk) begin if (~aresetn) begin m_valid <= 1\'b0; end else begin m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1\'b0}}) ? 1\'b0 : push & ~pop ? 1\'b1 : m_valid; end end generate if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0]; assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1\'b0}}; end else begin : gen_fifo_addr assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0]; end endgenerate generate genvar i; for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit SRL16E u_srl_fifo( .Q ( m_payload[i] ) , .A0 ( fifo_addr[0] ) , .A1 ( fifo_addr[1] ) , .A2 ( fifo_addr[2] ) , .A3 ( fifo_addr[3] ) , .CE ( push ) , .CLK ( aclk ) , .D ( s_payload[i] ) ); end endgenerate endmodule `default_nettype wire
/***************************************************************************** * File : processing_system7_bfm_v2_0_reg_params.v * * Date : 2012-11 * * Description : Parameters for Register Address and Default values. * *****************************************************************************/ // Register default value info for chip pele_ps // This code was auto-generated by xregdb.py ver. 0.68, Thu Jul 12 10:32:25 2012 // 54 modules, 2532 registers. // ************************************************************ // Module afi0 AFI // doc version: 1.1 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter afi0__AFI_RDCHAN_CTRL = 32'hF8008000; parameter val_afi0__AFI_RDCHAN_CTRL = 32'h00000000; parameter mask_afi0__AFI_RDCHAN_CTRL = 32'hFFFFFFFF; parameter afi0__AFI_RDCHAN_ISSUINGCAP = 32'hF8008004; parameter val_afi0__AFI_RDCHAN_ISSUINGCAP = 32'h00000007; parameter mask_afi0__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF; parameter afi0__AFI_RDQOS = 32'hF8008008; parameter val_afi0__AFI_RDQOS = 32'h00000000; parameter mask_afi0__AFI_RDQOS = 32'hFFFFFFFF; parameter afi0__AFI_RDDATAFIFO_LEVEL = 32'hF800800C; parameter val_afi0__AFI_RDDATAFIFO_LEVEL = 32'h00000000; parameter mask_afi0__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF; parameter afi0__AFI_RDDEBUG = 32'hF8008010; parameter val_afi0__AFI_RDDEBUG = 32'h00000000; parameter mask_afi0__AFI_RDDEBUG = 32'hFFFFFFFF; parameter afi0__AFI_WRCHAN_CTRL = 32'hF8008014; parameter val_afi0__AFI_WRCHAN_CTRL = 32'h00000F00; parameter mask_afi0__AFI_WRCHAN_CTRL = 32'hFFFFFFFF; parameter afi0__AFI_WRCHAN_ISSUINGCAP = 32'hF8008018; parameter val_afi0__AFI_WRCHAN_ISSUINGCAP = 32'h00000007; parameter mask_afi0__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF; parameter afi0__AFI_WRQOS = 32'hF800801C; parameter val_afi0__AFI_WRQOS = 32'h00000000; parameter mask_afi0__AFI_WRQOS = 32'hFFFFFFFF; parameter afi0__AFI_WRDATAFIFO_LEVEL = 32'hF8008020; parameter val_afi0__AFI_WRDATAFIFO_LEVEL = 32'h00000000; parameter mask_afi0__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF; parameter afi0__AFI_WRDEBUG = 32'hF8008024; parameter val_afi0__AFI_WRDEBUG = 32'h00000000; parameter mask_afi0__AFI_WRDEBUG = 32'hFFFFFFFF; // ************************************************************ // Module afi1 AFI // doc version: 1.1 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter afi1__AFI_RDCHAN_CTRL = 32'hF8009000; parameter val_afi1__AFI_RDCHAN_CTRL = 32'h00000000; parameter mask_afi1__AFI_RDCHAN_CTRL = 32'hFFFFFFFF; parameter afi1__AFI_RDCHAN_ISSUINGCAP = 32'hF8009004; parameter val_afi1__AFI_RDCHAN_ISSUINGCAP = 32'h00000007; parameter mask_afi1__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF; parameter afi1__AFI_RDQOS = 32'hF8009008; parameter val_afi1__AFI_RDQOS = 32'h00000000; parameter mask_afi1__AFI_RDQOS = 32'hFFFFFFFF; parameter afi1__AFI_RDDATAFIFO_LEVEL = 32'hF800900C; parameter val_afi1__AFI_RDDATAFIFO_LEVEL = 32'h00000000; parameter mask_afi1__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF; parameter afi1__AFI_RDDEBUG = 32'hF8009010; parameter val_afi1__AFI_RDDEBUG = 32'h00000000; parameter mask_afi1__AFI_RDDEBUG = 32'hFFFFFFFF; parameter afi1__AFI_WRCHAN_CTRL = 32'hF8009014; parameter val_afi1__AFI_WRCHAN_CTRL = 32'h00000F00; parameter mask_afi1__AFI_WRCHAN_CTRL = 32'hFFFFFFFF; parameter afi1__AFI_WRCHAN_ISSUINGCAP = 32'hF8009018; parameter val_afi1__AFI_WRCHAN_ISSUINGCAP = 32'h00000007; parameter mask_afi1__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF; parameter afi1__AFI_WRQOS = 32'hF800901C; parameter val_afi1__AFI_WRQOS = 32'h00000000; parameter mask_afi1__AFI_WRQOS = 32'hFFFFFFFF; parameter afi1__AFI_WRDATAFIFO_LEVEL = 32'hF8009020; parameter val_afi1__AFI_WRDATAFIFO_LEVEL = 32'h00000000; parameter mask_afi1__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF; parameter afi1__AFI_WRDEBUG = 32'hF8009024; parameter val_afi1__AFI_WRDEBUG = 32'h00000000; parameter mask_afi1__AFI_WRDEBUG = 32'hFFFFFFFF; // ************************************************************ // Module afi2 AFI // doc version: 1.1 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter afi2__AFI_RDCHAN_CTRL = 32'hF800A000; parameter val_afi2__AFI_RDCHAN_CTRL = 32'h00000000; parameter mask_afi2__AFI_RDCHAN_CTRL = 32'hFFFFFFFF; parameter afi2__AFI_RDCHAN_ISSUINGCAP = 32'hF800A004; parameter val_afi2__AFI_RDCHAN_ISSUINGCAP = 32'h00000007; parameter mask_afi2__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF; parameter afi2__AFI_RDQOS = 32'hF800A008; parameter val_afi2__AFI_RDQOS = 32'h00000000; parameter mask_afi2__AFI_RDQOS = 32'hFFFFFFFF; parameter afi2__AFI_RDDATAFIFO_LEVEL = 32'hF800A00C; parameter val_afi2__AFI_RDDATAFIFO_LEVEL = 32'h00000000; parameter mask_afi2__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF; parameter afi2__AFI_RDDEBUG = 32'hF800A010; parameter val_afi2__AFI_RDDEBUG = 32'h00000000; parameter mask_afi2__AFI_RDDEBUG = 32'hFFFFFFFF; parameter afi2__AFI_WRCHAN_CTRL = 32'hF800A014; parameter val_afi2__AFI_WRCHAN_CTRL = 32'h00000F00; parameter mask_afi2__AFI_WRCHAN_CTRL = 32'hFFFFFFFF; parameter afi2__AFI_WRCHAN_ISSUINGCAP = 32'hF800A018; parameter val_afi2__AFI_WRCHAN_ISSUINGCAP = 32'h00000007; parameter mask_afi2__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF; parameter afi2__AFI_WRQOS = 32'hF800A01C; parameter val_afi2__AFI_WRQOS = 32'h00000000; parameter mask_afi2__AFI_WRQOS = 32'hFFFFFFFF; parameter afi2__AFI_WRDATAFIFO_LEVEL = 32'hF800A020; parameter val_afi2__AFI_WRDATAFIFO_LEVEL = 32'h00000000; parameter mask_afi2__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF; parameter afi2__AFI_WRDEBUG = 32'hF800A024; parameter val_afi2__AFI_WRDEBUG = 32'h00000000; parameter mask_afi2__AFI_WRDEBUG = 32'hFFFFFFFF; // ************************************************************ // Module afi3 AFI // doc version: 1.1 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter afi3__AFI_RDCHAN_CTRL = 32'hF800B000; parameter val_afi3__AFI_RDCHAN_CTRL = 32'h00000000; parameter mask_afi3__AFI_RDCHAN_CTRL = 32'hFFFFFFFF; parameter afi3__AFI_RDCHAN_ISSUINGCAP = 32'hF800B004; parameter val_afi3__AFI_RDCHAN_ISSUINGCAP = 32'h00000007; parameter mask_afi3__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF; parameter afi3__AFI_RDQOS = 32'hF800B008; parameter val_afi3__AFI_RDQOS = 32'h00000000; parameter mask_afi3__AFI_RDQOS = 32'hFFFFFFFF; parameter afi3__AFI_RDDATAFIFO_LEVEL = 32'hF800B00C; parameter val_afi3__AFI_RDDATAFIFO_LEVEL = 32'h00000000; parameter mask_afi3__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF; parameter afi3__AFI_RDDEBUG = 32'hF800B010; parameter val_afi3__AFI_RDDEBUG = 32'h00000000; parameter mask_afi3__AFI_RDDEBUG = 32'hFFFFFFFF; parameter afi3__AFI_WRCHAN_CTRL = 32'hF800B014; parameter val_afi3__AFI_WRCHAN_CTRL = 32'h00000F00; parameter mask_afi3__AFI_WRCHAN_CTRL = 32'hFFFFFFFF; parameter afi3__AFI_WRCHAN_ISSUINGCAP = 32'hF800B018; parameter val_afi3__AFI_WRCHAN_ISSUINGCAP = 32'h00000007; parameter mask_afi3__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF; parameter afi3__AFI_WRQOS = 32'hF800B01C; parameter val_afi3__AFI_WRQOS = 32'h00000000; parameter mask_afi3__AFI_WRQOS = 32'hFFFFFFFF; parameter afi3__AFI_WRDATAFIFO_LEVEL = 32'hF800B020; parameter val_afi3__AFI_WRDATAFIFO_LEVEL = 32'h00000000; parameter mask_afi3__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF; parameter afi3__AFI_WRDEBUG = 32'hF800B024; parameter val_afi3__AFI_WRDEBUG = 32'h00000000; parameter mask_afi3__AFI_WRDEBUG = 32'hFFFFFFFF; // ************************************************************ // Module can0 can // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter can0__SRR = 32'hE0008000; parameter val_can0__SRR = 32'h00000000; parameter mask_can0__SRR = 32'hFFFFFFFF; parameter can0__MSR = 32'hE0008004; parameter val_can0__MSR = 32'h00000000; parameter mask_can0__MSR = 32'hFFFFFFFF; parameter can0__BRPR = 32'hE0008008; parameter val_can0__BRPR = 32'h00000000; parameter mask_can0__BRPR = 32'hFFFFFFFF; parameter can0__BTR = 32'hE000800C; parameter val_can0__BTR = 32'h00000000; parameter mask_can0__BTR = 32'hFFFFFFFF; parameter can0__ECR = 32'hE0008010; parameter val_can0__ECR = 32'h00000000; parameter mask_can0__ECR = 32'hFFFFFFFF; parameter can0__ESR = 32'hE0008014; parameter val_can0__ESR = 32'h00000000; parameter mask_can0__ESR = 32'hFFFFFFFF; parameter can0__SR = 32'hE0008018; parameter val_can0__SR = 32'h00000001; parameter mask_can0__SR = 32'hFFFFFFFF; parameter can0__ISR = 32'hE000801C; parameter val_can0__ISR = 32'h00006000; parameter mask_can0__ISR = 32'hFFFFFFFF; parameter can0__IER = 32'hE0008020; parameter val_can0__IER = 32'h00000000; parameter mask_can0__IER = 32'hFFFFFFFF; parameter can0__ICR = 32'hE0008024; parameter val_can0__ICR = 32'h00000000; parameter mask_can0__ICR = 32'hFFFFFFFF; parameter can0__TCR = 32'hE0008028; parameter val_can0__TCR = 32'h00000000; parameter mask_can0__TCR = 32'hFFFFFFFF; parameter can0__WIR = 32'hE000802C; parameter val_can0__WIR = 32'h00003F3F; parameter mask_can0__WIR = 32'hFFFFFFFF; parameter can0__TXFIFO_ID = 32'hE0008030; parameter val_can0__TXFIFO_ID = 32'h00000000; parameter mask_can0__TXFIFO_ID = 32'hFFFFFFFF; parameter can0__TXFIFO_DLC = 32'hE0008034; parameter val_can0__TXFIFO_DLC = 32'h00000000; parameter mask_can0__TXFIFO_DLC = 32'hFFFFFFFF; parameter can0__TXFIFO_DATA1 = 32'hE0008038; parameter val_can0__TXFIFO_DATA1 = 32'h00000000; parameter mask_can0__TXFIFO_DATA1 = 32'hFFFFFFFF; parameter can0__TXFIFO_DATA2 = 32'hE000803C; parameter val_can0__TXFIFO_DATA2 = 32'h00000000; parameter mask_can0__TXFIFO_DATA2 = 32'hFFFFFFFF; parameter can0__TXHPB_ID = 32'hE0008040; parameter val_can0__TXHPB_ID = 32'h00000000; parameter mask_can0__TXHPB_ID = 32'hFFFFFFFF; parameter can0__TXHPB_DLC = 32'hE0008044; parameter val_can0__TXHPB_DLC = 32'h00000000; parameter mask_can0__TXHPB_DLC = 32'hFFFFFFFF; parameter can0__TXHPB_DATA1 = 32'hE0008048; parameter val_can0__TXHPB_DATA1 = 32'h00000000; parameter mask_can0__TXHPB_DATA1 = 32'hFFFFFFFF; parameter can0__TXHPB_DATA2 = 32'hE000804C; parameter val_can0__TXHPB_DATA2 = 32'h00000000; parameter mask_can0__TXHPB_DATA2 = 32'hFFFFFFFF; parameter can0__RXFIFO_ID = 32'hE0008050; parameter val_can0__RXFIFO_ID = 32'h00000000; parameter mask_can0__RXFIFO_ID = 32'h00000000; parameter can0__RXFIFO_DLC = 32'hE0008054; parameter val_can0__RXFIFO_DLC = 32'h00000000; parameter mask_can0__RXFIFO_DLC = 32'h00000000; parameter can0__RXFIFO_DATA1 = 32'hE0008058; parameter val_can0__RXFIFO_DATA1 = 32'h00000000; parameter mask_can0__RXFIFO_DATA1 = 32'h00000000; parameter can0__RXFIFO_DATA2 = 32'hE000805C; parameter val_can0__RXFIFO_DATA2 = 32'h00000000; parameter mask_can0__RXFIFO_DATA2 = 32'h00000000; parameter can0__AFR = 32'hE0008060; parameter val_can0__AFR = 32'h00000000; parameter mask_can0__AFR = 32'hFFFFFFFF; parameter can0__AFMR1 = 32'hE0008064; parameter val_can0__AFMR1 = 32'h00000000; parameter mask_can0__AFMR1 = 32'h00000000; parameter can0__AFIR1 = 32'hE0008068; parameter val_can0__AFIR1 = 32'h00000000; parameter mask_can0__AFIR1 = 32'h00000000; parameter can0__AFMR2 = 32'hE000806C; parameter val_can0__AFMR2 = 32'h00000000; parameter mask_can0__AFMR2 = 32'h00000000; parameter can0__AFIR2 = 32'hE0008070; parameter val_can0__AFIR2 = 32'h00000000; parameter mask_can0__AFIR2 = 32'h00000000; parameter can0__AFMR3 = 32'hE0008074; parameter val_can0__AFMR3 = 32'h00000000; parameter mask_can0__AFMR3 = 32'h00000000; parameter can0__AFIR3 = 32'hE0008078; parameter val_can0__AFIR3 = 32'h00000000; parameter mask_can0__AFIR3 = 32'h00000000; parameter can0__AFMR4 = 32'hE000807C; parameter val_can0__AFMR4 = 32'h00000000; parameter mask_can0__AFMR4 = 32'h00000000; parameter can0__AFIR4 = 32'hE0008080; parameter val_can0__AFIR4 = 32'h00000000; parameter mask_can0__AFIR4 = 32'h00000000; // ************************************************************ // Module can1 can // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter can1__SRR = 32'hE0009000; parameter val_can1__SRR = 32'h00000000; parameter mask_can1__SRR = 32'hFFFFFFFF; parameter can1__MSR = 32'hE0009004; parameter val_can1__MSR = 32'h00000000; parameter mask_can1__MSR = 32'hFFFFFFFF; parameter can1__BRPR = 32'hE0009008; parameter val_can1__BRPR = 32'h00000000; parameter mask_can1__BRPR = 32'hFFFFFFFF; parameter can1__BTR = 32'hE000900C; parameter val_can1__BTR = 32'h00000000; parameter mask_can1__BTR = 32'hFFFFFFFF; parameter can1__ECR = 32'hE0009010; parameter val_can1__ECR = 32'h00000000; parameter mask_can1__ECR = 32'hFFFFFFFF; parameter can1__ESR = 32'hE0009014; parameter val_can1__ESR = 32'h00000000; parameter mask_can1__ESR = 32'hFFFFFFFF; parameter can1__SR = 32'hE0009018; parameter val_can1__SR = 32'h00000001; parameter mask_can1__SR = 32'hFFFFFFFF; parameter can1__ISR = 32'hE000901C; parameter val_can1__ISR = 32'h00006000; parameter mask_can1__ISR = 32'hFFFFFFFF; parameter can1__IER = 32'hE0009020; parameter val_can1__IER = 32'h00000000; parameter mask_can1__IER = 32'hFFFFFFFF; parameter can1__ICR = 32'hE0009024; parameter val_can1__ICR = 32'h00000000; parameter mask_can1__ICR = 32'hFFFFFFFF; parameter can1__TCR = 32'hE0009028; parameter val_can1__TCR = 32'h00000000; parameter mask_can1__TCR = 32'hFFFFFFFF; parameter can1__WIR = 32'hE000902C; parameter val_can1__WIR = 32'h00003F3F; parameter mask_can1__WIR = 32'hFFFFFFFF; parameter can1__TXFIFO_ID = 32'hE0009030; parameter val_can1__TXFIFO_ID = 32'h00000000; parameter mask_can1__TXFIFO_ID = 32'hFFFFFFFF; parameter can1__TXFIFO_DLC = 32'hE0009034; parameter val_can1__TXFIFO_DLC = 32'h00000000; parameter mask_can1__TXFIFO_DLC = 32'hFFFFFFFF; parameter can1__TXFIFO_DATA1 = 32'hE0009038; parameter val_can1__TXFIFO_DATA1 = 32'h00000000; parameter mask_can1__TXFIFO_DATA1 = 32'hFFFFFFFF; parameter can1__TXFIFO_DATA2 = 32'hE000903C; parameter val_can1__TXFIFO_DATA2 = 32'h00000000; parameter mask_can1__TXFIFO_DATA2 = 32'hFFFFFFFF; parameter can1__TXHPB_ID = 32'hE0009040; parameter val_can1__TXHPB_ID = 32'h00000000; parameter mask_can1__TXHPB_ID = 32'hFFFFFFFF; parameter can1__TXHPB_DLC = 32'hE0009044; parameter val_can1__TXHPB_DLC = 32'h00000000; parameter mask_can1__TXHPB_DLC = 32'hFFFFFFFF; parameter can1__TXHPB_DATA1 = 32'hE0009048; parameter val_can1__TXHPB_DATA1 = 32'h00000000; parameter mask_can1__TXHPB_DATA1 = 32'hFFFFFFFF; parameter can1__TXHPB_DATA2 = 32'hE000904C; parameter val_can1__TXHPB_DATA2 = 32'h00000000; parameter mask_can1__TXHPB_DATA2 = 32'hFFFFFFFF; parameter can1__RXFIFO_ID = 32'hE0009050; parameter val_can1__RXFIFO_ID = 32'h00000000; parameter mask_can1__RXFIFO_ID = 32'h00000000; parameter can1__RXFIFO_DLC = 32'hE0009054; parameter val_can1__RXFIFO_DLC = 32'h00000000; parameter mask_can1__RXFIFO_DLC = 32'h00000000; parameter can1__RXFIFO_DATA1 = 32'hE0009058; parameter val_can1__RXFIFO_DATA1 = 32'h00000000; parameter mask_can1__RXFIFO_DATA1 = 32'h00000000; parameter can1__RXFIFO_DATA2 = 32'hE000905C; parameter val_can1__RXFIFO_DATA2 = 32'h00000000; parameter mask_can1__RXFIFO_DATA2 = 32'h00000000; parameter can1__AFR = 32'hE0009060; parameter val_can1__AFR = 32'h00000000; parameter mask_can1__AFR = 32'hFFFFFFFF; parameter can1__AFMR1 = 32'hE0009064; parameter val_can1__AFMR1 = 32'h00000000; parameter mask_can1__AFMR1 = 32'h00000000; parameter can1__AFIR1 = 32'hE0009068; parameter val_can1__AFIR1 = 32'h00000000; parameter mask_can1__AFIR1 = 32'h00000000; parameter can1__AFMR2 = 32'hE000906C; parameter val_can1__AFMR2 = 32'h00000000; parameter mask_can1__AFMR2 = 32'h00000000; parameter can1__AFIR2 = 32'hE0009070; parameter val_can1__AFIR2 = 32'h00000000; parameter mask_can1__AFIR2 = 32'h00000000; parameter can1__AFMR3 = 32'hE0009074; parameter val_can1__AFMR3 = 32'h00000000; parameter mask_can1__AFMR3 = 32'h00000000; parameter can1__AFIR3 = 32'hE0009078; parameter val_can1__AFIR3 = 32'h00000000; parameter mask_can1__AFIR3 = 32'h00000000; parameter can1__AFMR4 = 32'hE000907C; parameter val_can1__AFMR4 = 32'h00000000; parameter mask_can1__AFMR4 = 32'h00000000; parameter can1__AFIR4 = 32'hE0009080; parameter val_can1__AFIR4 = 32'h00000000; parameter mask_can1__AFIR4 = 32'h00000000; // ************************************************************ // Module ddrc ddrc // doc version: 1.25 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter ddrc__ddrc_ctrl = 32'hF8006000; parameter val_ddrc__ddrc_ctrl = 32'h00000200; parameter mask_ddrc__ddrc_ctrl = 32'hFFFFFFFF; parameter ddrc__Two_rank_cfg = 32'hF8006004; parameter val_ddrc__Two_rank_cfg = 32'h000C1076; parameter mask_ddrc__Two_rank_cfg = 32'h1FFFFFFF; parameter ddrc__HPR_reg = 32'hF8006008; parameter val_ddrc__HPR_reg = 32'h03C0780F; parameter mask_ddrc__HPR_reg = 32'h03FFFFFF; parameter ddrc__LPR_reg = 32'hF800600C; parameter val_ddrc__LPR_reg = 32'h03C0780F; parameter mask_ddrc__LPR_reg = 32'h03FFFFFF; parameter ddrc__WR_reg = 32'hF8006010; parameter val_ddrc__WR_reg = 32'h0007F80F; parameter mask_ddrc__WR_reg = 32'h03FFFFFF; parameter ddrc__DRAM_param_reg0 = 32'hF8006014; parameter val_ddrc__DRAM_param_reg0 = 32'h00041016; parameter mask_ddrc__DRAM_param_reg0 = 32'h001FFFFF; parameter ddrc__DRAM_param_reg1 = 32'hF8006018; parameter val_ddrc__DRAM_param_reg1 = 32'h351B48D9; parameter mask_ddrc__DRAM_param_reg1 = 32'hF7FFFFFF; parameter ddrc__DRAM_param_reg2 = 32'hF800601C; parameter val_ddrc__DRAM_param_reg2 = 32'h83015904; parameter mask_ddrc__DRAM_param_reg2 = 32'hFFFFFFFF; parameter ddrc__DRAM_param_reg3 = 32'hF8006020; parameter val_ddrc__DRAM_param_reg3 = 32'h250882D0; parameter mask_ddrc__DRAM_param_reg3 = 32'hFFFFFFFF; parameter ddrc__DRAM_param_reg4 = 32'hF8006024; parameter val_ddrc__DRAM_param_reg4 = 32'h0000003C; parameter mask_ddrc__DRAM_param_reg4 = 32'h0FFFFFFF; parameter ddrc__DRAM_init_param = 32'hF8006028; parameter val_ddrc__DRAM_init_param = 32'h00002007; parameter mask_ddrc__DRAM_init_param = 32'h00003FFF; parameter ddrc__DRAM_EMR_reg = 32'hF800602C; parameter val_ddrc__DRAM_EMR_reg = 32'h00000008; parameter mask_ddrc__DRAM_EMR_reg = 32'hFFFFFFFF; parameter ddrc__DRAM_EMR_MR_reg = 32'hF8006030; parameter val_ddrc__DRAM_EMR_MR_reg = 32'h00000940; parameter mask_ddrc__DRAM_EMR_MR_reg = 32'hFFFFFFFF; parameter ddrc__DRAM_burst8_rdwr = 32'hF8006034; parameter val_ddrc__DRAM_burst8_rdwr = 32'h00020034; parameter mask_ddrc__DRAM_burst8_rdwr = 32'h1FFFFFFF; parameter ddrc__DRAM_disable_DQ = 32'hF8006038; parameter val_ddrc__DRAM_disable_DQ = 32'h00000000; parameter mask_ddrc__DRAM_disable_DQ = 32'h00001FFF; parameter ddrc__DRAM_addr_map_bank = 32'hF800603C; parameter val_ddrc__DRAM_addr_map_bank = 32'h00000F77; parameter mask_ddrc__DRAM_addr_map_bank = 32'h000FFFFF; parameter ddrc__DRAM_addr_map_col = 32'hF8006040; parameter val_ddrc__DRAM_addr_map_col = 32'hFFF00000; parameter mask_ddrc__DRAM_addr_map_col = 32'hFFFFFFFF; parameter ddrc__DRAM_addr_map_row = 32'hF8006044; parameter val_ddrc__DRAM_addr_map_row = 32'h0FF55555; parameter mask_ddrc__DRAM_addr_map_row = 32'h0FFFFFFF; parameter ddrc__DRAM_ODT_reg = 32'hF8006048; parameter val_ddrc__DRAM_ODT_reg = 32'h00000249; parameter mask_ddrc__DRAM_ODT_reg = 32'h3FFFFFFF; parameter ddrc__phy_dbg_reg = 32'hF800604C; parameter val_ddrc__phy_dbg_reg = 32'h00000000; parameter mask_ddrc__phy_dbg_reg = 32'h000FFFFF; parameter ddrc__phy_cmd_timeout_rddata_cpt = 32'hF8006050; parameter val_ddrc__phy_cmd_timeout_rddata_cpt = 32'h00010200; parameter mask_ddrc__phy_cmd_timeout_rddata_cpt = 32'hFFFFFFFF; parameter ddrc__mode_sts_reg = 32'hF8006054; parameter val_ddrc__mode_sts_reg = 32'h00000000; parameter mask_ddrc__mode_sts_reg = 32'h001FFFFF; parameter ddrc__DLL_calib = 32'hF8006058; parameter val_ddrc__DLL_calib = 32'h00000101; parameter mask_ddrc__DLL_calib = 32'h0001FFFF; parameter ddrc__ODT_delay_hold = 32'hF800605C; parameter val_ddrc__ODT_delay_hold = 32'h00000023; parameter mask_ddrc__ODT_delay_hold = 32'h0000FFFF; parameter ddrc__ctrl_reg1 = 32'hF8006060; parameter val_ddrc__ctrl_reg1 = 32'h0000003E; parameter mask_ddrc__ctrl_reg1 = 32'h00001FFF; parameter ddrc__ctrl_reg2 = 32'hF8006064; parameter val_ddrc__ctrl_reg2 = 32'h00020000; parameter mask_ddrc__ctrl_reg2 = 32'h0003FFFF; parameter ddrc__ctrl_reg3 = 32'hF8006068; parameter val_ddrc__ctrl_reg3 = 32'h00284027; parameter mask_ddrc__ctrl_reg3 = 32'h03FFFFFF; parameter ddrc__ctrl_reg4 = 32'hF800606C; parameter val_ddrc__ctrl_reg4 = 32'h00001610; parameter mask_ddrc__ctrl_reg4 = 32'h0000FFFF; parameter ddrc__ctrl_reg5 = 32'hF8006078; parameter val_ddrc__ctrl_reg5 = 32'h00455111; parameter mask_ddrc__ctrl_reg5 = 32'hFFFFFFFF; parameter ddrc__ctrl_reg6 = 32'hF800607C; parameter val_ddrc__ctrl_reg6 = 32'h00032222; parameter mask_ddrc__ctrl_reg6 = 32'hFFFFFFFF; parameter ddrc__CHE_REFRESH_TIMER01 = 32'hF80060A0; parameter val_ddrc__CHE_REFRESH_TIMER01 = 32'h00008000; parameter mask_ddrc__CHE_REFRESH_TIMER01 = 32'h00FFFFFF; parameter ddrc__CHE_T_ZQ = 32'hF80060A4; parameter val_ddrc__CHE_T_ZQ = 32'h10300802; parameter mask_ddrc__CHE_T_ZQ = 32'hFFFFFFFF; parameter ddrc__CHE_T_ZQ_Short_Interval_Reg = 32'hF80060A8; parameter val_ddrc__CHE_T_ZQ_Short_Interval_Reg = 32'h0020003A; parameter mask_ddrc__CHE_T_ZQ_Short_Interval_Reg = 32'h0FFFFFFF; parameter ddrc__deep_pwrdwn_reg = 32'hF80060AC; parameter val_ddrc__deep_pwrdwn_reg = 32'h00000000; parameter mask_ddrc__deep_pwrdwn_reg = 32'h000001FF; parameter ddrc__reg_2c = 32'hF80060B0; parameter val_ddrc__reg_2c = 32'h00000000; parameter mask_ddrc__reg_2c = 32'h1FFFFFFF; parameter ddrc__reg_2d = 32'hF80060B4; parameter val_ddrc__reg_2d = 32'h00000200; parameter mask_ddrc__reg_2d = 32'h000007FF; parameter ddrc__dfi_timing = 32'hF80060B8; parameter val_ddrc__dfi_timing = 32'h00200067; parameter mask_ddrc__dfi_timing = 32'h01FFFFFF; parameter ddrc__refresh_timer_2 = 32'hF80060BC; parameter val_ddrc__refresh_timer_2 = 32'h00000000; parameter mask_ddrc__refresh_timer_2 = 32'h00FFFFFF; parameter ddrc__nc_timing = 32'hF80060C0; parameter val_ddrc__nc_timing = 32'h00000000; parameter mask_ddrc__nc_timing = 32'h003FFFFF; parameter ddrc__CHE_ECC_CONTROL_REG_OFFSET = 32'hF80060C4; parameter val_ddrc__CHE_ECC_CONTROL_REG_OFFSET = 32'h00000000; parameter mask_ddrc__CHE_ECC_CONTROL_REG_OFFSET = 32'h00000003; parameter ddrc__CHE_CORR_ECC_LOG_REG_OFFSET = 32'hF80060C8; parameter val_ddrc__CHE_CORR_ECC_LOG_REG_OFFSET = 32'h00000000; parameter mask_ddrc__CHE_CORR_ECC_LOG_REG_OFFSET = 32'h000000FF; parameter ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET = 32'hF80060CC; parameter val_ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET = 32'h00000000; parameter mask_ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET = 32'h7FFFFFFF; parameter ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET = 32'hF80060D0; parameter val_ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET = 32'h00000000; parameter mask_ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET = 32'hFFFFFFFF; parameter ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET = 32'hF80060D4; parameter val_ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET = 32'h00000000; parameter mask_ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET = 32'hFFFFFFFF; parameter ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET = 32'hF80060D8; parameter val_ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET = 32'h00000000; parameter mask_ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET = 32'h000000FF; parameter ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET = 32'hF80060DC; parameter val_ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET = 32'h00000000; parameter mask_ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET = 32'h00000001; parameter ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET = 32'hF80060E0; parameter val_ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET = 32'h00000000; parameter mask_ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET = 32'h7FFFFFFF; parameter ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET = 32'hF80060E4; parameter val_ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET = 32'h00000000; parameter mask_ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET = 32'hFFFFFFFF; parameter ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET = 32'hF80060E8; parameter val_ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET = 32'h00000000; parameter mask_ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET = 32'hFFFFFFFF; parameter ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET = 32'hF80060EC; parameter val_ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET = 32'h00000000; parameter mask_ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET = 32'h000000FF; parameter ddrc__CHE_ECC_STATS_REG_OFFSET = 32'hF80060F0; parameter val_ddrc__CHE_ECC_STATS_REG_OFFSET = 32'h00000000; parameter mask_ddrc__CHE_ECC_STATS_REG_OFFSET = 32'h0000FFFF; parameter ddrc__ECC_scrub = 32'hF80060F4; parameter val_ddrc__ECC_scrub = 32'h00000008; parameter mask_ddrc__ECC_scrub = 32'h0000000F; parameter ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET = 32'hF80060F8; parameter val_ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET = 32'h00000000; parameter mask_ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET = 32'hFFFFFFFF; parameter ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET = 32'hF80060FC; parameter val_ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET = 32'h00000000; parameter mask_ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET = 32'hFFFFFFFF; parameter ddrc__phy_rcvr_enable = 32'hF8006114; parameter val_ddrc__phy_rcvr_enable = 32'h00000000; parameter mask_ddrc__phy_rcvr_enable = 32'h000000FF; parameter ddrc__PHY_Config0 = 32'hF8006118; parameter val_ddrc__PHY_Config0 = 32'h40000001; parameter mask_ddrc__PHY_Config0 = 32'h7FFFFFFF; parameter ddrc__PHY_Config1 = 32'hF800611C; parameter val_ddrc__PHY_Config1 = 32'h40000001; parameter mask_ddrc__PHY_Config1 = 32'h7FFFFFFF; parameter ddrc__PHY_Config2 = 32'hF8006120; parameter val_ddrc__PHY_Config2 = 32'h40000001; parameter mask_ddrc__PHY_Config2 = 32'h7FFFFFFF; parameter ddrc__PHY_Config3 = 32'hF8006124; parameter val_ddrc__PHY_Config3 = 32'h40000001; parameter mask_ddrc__PHY_Config3 = 32'h7FFFFFFF; parameter ddrc__phy_init_ratio0 = 32'hF800612C; parameter val_ddrc__phy_init_ratio0 = 32'h00000000; parameter mask_ddrc__phy_init_ratio0 = 32'h000FFFFF; parameter ddrc__phy_init_ratio1 = 32'hF8006130; parameter val_ddrc__phy_init_ratio1 = 32'h00000000; parameter mask_ddrc__phy_init_ratio1 = 32'h000FFFFF; parameter ddrc__phy_init_ratio2 = 32'hF8006134; parameter val_ddrc__phy_init_ratio2 = 32'h00000000; parameter mask_ddrc__phy_init_ratio2 = 32'h000FFFFF; parameter ddrc__phy_init_ratio3 = 32'hF8006138; parameter val_ddrc__phy_init_ratio3 = 32'h00000000; parameter mask_ddrc__phy_init_ratio3 = 32'h000FFFFF; parameter ddrc__phy_rd_dqs_cfg0 = 32'hF8006140; parameter val_ddrc__phy_rd_dqs_cfg0 = 32'h00000040; parameter mask_ddrc__phy_rd_dqs_cfg0 = 32'h000FFFFF; parameter ddrc__phy_rd_dqs_cfg1 = 32'hF8006144; parameter val_ddrc__phy_rd_dqs_cfg1 = 32'h00000040; parameter mask_ddrc__phy_rd_dqs_cfg1 = 32'h000FFFFF; parameter ddrc__phy_rd_dqs_cfg2 = 32'hF8006148; parameter val_ddrc__phy_rd_dqs_cfg2 = 32'h00000040; parameter mask_ddrc__phy_rd_dqs_cfg2 = 32'h000FFFFF; parameter ddrc__phy_rd_dqs_cfg3 = 32'hF800614C; parameter val_ddrc__phy_rd_dqs_cfg3 = 32'h00000040; parameter mask_ddrc__phy_rd_dqs_cfg3 = 32'h000FFFFF; parameter ddrc__phy_wr_dqs_cfg0 = 32'hF8006154; parameter val_ddrc__phy_wr_dqs_cfg0 = 32'h00000000; parameter mask_ddrc__phy_wr_dqs_cfg0 = 32'h000FFFFF; parameter ddrc__phy_wr_dqs_cfg1 = 32'hF8006158; parameter val_ddrc__phy_wr_dqs_cfg1 = 32'h00000000; parameter mask_ddrc__phy_wr_dqs_cfg1 = 32'h000FFFFF; parameter ddrc__phy_wr_dqs_cfg2 = 32'hF800615C; parameter val_ddrc__phy_wr_dqs_cfg2 = 32'h00000000; parameter mask_ddrc__phy_wr_dqs_cfg2 = 32'h000FFFFF; parameter ddrc__phy_wr_dqs_cfg3 = 32'hF8006160; parameter val_ddrc__phy_wr_dqs_cfg3 = 32'h00000000; parameter mask_ddrc__phy_wr_dqs_cfg3 = 32'h000FFFFF; parameter ddrc__phy_we_cfg0 = 32'hF8006168; parameter val_ddrc__phy_we_cfg0 = 32'h00000040; parameter mask_ddrc__phy_we_cfg0 = 32'h001FFFFF; parameter ddrc__phy_we_cfg1 = 32'hF800616C; parameter val_ddrc__phy_we_cfg1 = 32'h00000040; parameter mask_ddrc__phy_we_cfg1 = 32'h001FFFFF; parameter ddrc__phy_we_cfg2 = 32'hF8006170; parameter val_ddrc__phy_we_cfg2 = 32'h00000040; parameter mask_ddrc__phy_we_cfg2 = 32'h001FFFFF; parameter ddrc__phy_we_cfg3 = 32'hF8006174; parameter val_ddrc__phy_we_cfg3 = 32'h00000040; parameter mask_ddrc__phy_we_cfg3 = 32'h001FFFFF; parameter ddrc__wr_data_slv0 = 32'hF800617C; parameter val_ddrc__wr_data_slv0 = 32'h00000080; parameter mask_ddrc__wr_data_slv0 = 32'h000FFFFF; parameter ddrc__wr_data_slv1 = 32'hF8006180; parameter val_ddrc__wr_data_slv1 = 32'h00000080; parameter mask_ddrc__wr_data_slv1 = 32'h000FFFFF; parameter ddrc__wr_data_slv2 = 32'hF8006184; parameter val_ddrc__wr_data_slv2 = 32'h00000080; parameter mask_ddrc__wr_data_slv2 = 32'h000FFFFF; parameter ddrc__wr_data_slv3 = 32'hF8006188; parameter val_ddrc__wr_data_slv3 = 32'h00000080; parameter mask_ddrc__wr_data_slv3 = 32'h000FFFFF; parameter ddrc__reg_64 = 32'hF8006190; parameter val_ddrc__reg_64 = 32'h10020000; parameter mask_ddrc__reg_64 = 32'hFFFFFFFF; parameter ddrc__reg_65 = 32'hF8006194; parameter val_ddrc__reg_65 = 32'h00000000; parameter mask_ddrc__reg_65 = 32'h000FFFFF; parameter ddrc__reg69_6a0 = 32'hF80061A4; parameter val_ddrc__reg69_6a0 = 32'h000F0000; parameter mask_ddrc__reg69_6a0 = 32'h1FFFFFFF; parameter ddrc__reg69_6a1 = 32'hF80061A8; parameter val_ddrc__reg69_6a1 = 32'h000F0000; parameter mask_ddrc__reg69_6a1 = 32'h1FFFFFFF; parameter ddrc__reg6c_6d2 = 32'hF80061B0; parameter val_ddrc__reg6c_6d2 = 32'h000F0000; parameter mask_ddrc__reg6c_6d2 = 32'h1FFFFFFF; parameter ddrc__reg6c_6d3 = 32'hF80061B4; parameter val_ddrc__reg6c_6d3 = 32'h000F0000; parameter mask_ddrc__reg6c_6d3 = 32'h1FFFFFFF; parameter ddrc__reg6e_710 = 32'hF80061B8; parameter val_ddrc__reg6e_710 = 32'h00000000; parameter mask_ddrc__reg6e_710 = 32'h00000000; parameter ddrc__reg6e_711 = 32'hF80061BC; parameter val_ddrc__reg6e_711 = 32'h00000000; parameter mask_ddrc__reg6e_711 = 32'h00000000; parameter ddrc__reg6e_712 = 32'hF80061C0; parameter val_ddrc__reg6e_712 = 32'h00000000; parameter mask_ddrc__reg6e_712 = 32'h00000000; parameter ddrc__reg6e_713 = 32'hF80061C4; parameter val_ddrc__reg6e_713 = 32'h00000000; parameter mask_ddrc__reg6e_713 = 32'h00000000; parameter ddrc__phy_dll_sts0 = 32'hF80061CC; parameter val_ddrc__phy_dll_sts0 = 32'h00000000; parameter mask_ddrc__phy_dll_sts0 = 32'h07FFFFFF; parameter ddrc__phy_dll_sts1 = 32'hF80061D0; parameter val_ddrc__phy_dll_sts1 = 32'h00000000; parameter mask_ddrc__phy_dll_sts1 = 32'h07FFFFFF; parameter ddrc__phy_dll_sts2 = 32'hF80061D4; parameter val_ddrc__phy_dll_sts2 = 32'h00000000; parameter mask_ddrc__phy_dll_sts2 = 32'h07FFFFFF; parameter ddrc__phy_dll_sts3 = 32'hF80061D8; parameter val_ddrc__phy_dll_sts3 = 32'h00000000; parameter mask_ddrc__phy_dll_sts3 = 32'h07FFFFFF; parameter ddrc__dll_lock_sts = 32'hF80061E0; parameter val_ddrc__dll_lock_sts = 32'h00000000; parameter mask_ddrc__dll_lock_sts = 32'h00FFFFFF; parameter ddrc__phy_ctrl_sts = 32'hF80061E4; parameter val_ddrc__phy_ctrl_sts = 32'h00000000; parameter mask_ddrc__phy_ctrl_sts = 32'h3FF80000; parameter ddrc__phy_ctrl_sts_reg2 = 32'hF80061E8; parameter val_ddrc__phy_ctrl_sts_reg2 = 32'h00000000; parameter mask_ddrc__phy_ctrl_sts_reg2 = 32'h07FFFFFF; parameter ddrc__axi_id = 32'hF8006200; parameter val_ddrc__axi_id = 32'h00153042; parameter mask_ddrc__axi_id = 32'h03FFFFFF; parameter ddrc__page_mask = 32'hF8006204; parameter val_ddrc__page_mask = 32'h00000000; parameter mask_ddrc__page_mask = 32'hFFFFFFFF; parameter ddrc__axi_priority_wr_port0 = 32'hF8006208; parameter val_ddrc__axi_priority_wr_port0 = 32'h000803FF; parameter mask_ddrc__axi_priority_wr_port0 = 32'h000FFFFF; parameter ddrc__axi_priority_wr_port1 = 32'hF800620C; parameter val_ddrc__axi_priority_wr_port1 = 32'h000803FF; parameter mask_ddrc__axi_priority_wr_port1 = 32'h000FFFFF; parameter ddrc__axi_priority_wr_port2 = 32'hF8006210; parameter val_ddrc__axi_priority_wr_port2 = 32'h000803FF; parameter mask_ddrc__axi_priority_wr_port2 = 32'h000FFFFF; parameter ddrc__axi_priority_wr_port3 = 32'hF8006214; parameter val_ddrc__axi_priority_wr_port3 = 32'h000803FF; parameter mask_ddrc__axi_priority_wr_port3 = 32'h000FFFFF; parameter ddrc__axi_priority_rd_port0 = 32'hF8006218; parameter val_ddrc__axi_priority_rd_port0 = 32'h000003FF; parameter mask_ddrc__axi_priority_rd_port0 = 32'h000FFFFF; parameter ddrc__axi_priority_rd_port1 = 32'hF800621C; parameter val_ddrc__axi_priority_rd_port1 = 32'h000003FF; parameter mask_ddrc__axi_priority_rd_port1 = 32'h000FFFFF; parameter ddrc__axi_priority_rd_port2 = 32'hF8006220; parameter val_ddrc__axi_priority_rd_port2 = 32'h000003FF; parameter mask_ddrc__axi_priority_rd_port2 = 32'h000FFFFF; parameter ddrc__axi_priority_rd_port3 = 32'hF8006224; parameter val_ddrc__axi_priority_rd_port3 = 32'h000003FF; parameter mask_ddrc__axi_priority_rd_port3 = 32'h000FFFFF; parameter ddrc__AHB_priority_cfg0 = 32'hF8006248; parameter val_ddrc__AHB_priority_cfg0 = 32'h000003FF; parameter mask_ddrc__AHB_priority_cfg0 = 32'h000FFFFF; parameter ddrc__AHB_priority_cfg1 = 32'hF800624C; parameter val_ddrc__AHB_priority_cfg1 = 32'h000003FF; parameter mask_ddrc__AHB_priority_cfg1 = 32'h000FFFFF; parameter ddrc__AHB_priority_cfg2 = 32'hF8006250; parameter val_ddrc__AHB_priority_cfg2 = 32'h000003FF; parameter mask_ddrc__AHB_priority_cfg2 = 32'h000FFFFF; parameter ddrc__AHB_priority_cfg3 = 32'hF8006254; parameter val_ddrc__AHB_priority_cfg3 = 32'h000003FF; parameter mask_ddrc__AHB_priority_cfg3 = 32'h000FFFFF; parameter ddrc__perf_mon0 = 32'hF8006260; parameter val_ddrc__perf_mon0 = 32'h00000000; parameter mask_ddrc__perf_mon0 = 32'h7FFFFFFF; parameter ddrc__perf_mon1 = 32'hF8006264; parameter val_ddrc__perf_mon1 = 32'h00000000; parameter mask_ddrc__perf_mon1 = 32'h7FFFFFFF; parameter ddrc__perf_mon2 = 32'hF8006268; parameter val_ddrc__perf_mon2 = 32'h00000000; parameter mask_ddrc__perf_mon2 = 32'h7FFFFFFF; parameter ddrc__perf_mon3 = 32'hF800626C; parameter val_ddrc__perf_mon3 = 32'h00000000; parameter mask_ddrc__perf_mon3 = 32'h7FFFFFFF; parameter ddrc__perf_mon20 = 32'hF8006270; parameter val_ddrc__perf_mon20 = 32'h00000000; parameter mask_ddrc__perf_mon20 = 32'hFFFFFFFF; parameter ddrc__perf_mon21 = 32'hF8006274; parameter val_ddrc__perf_mon21 = 32'h00000000; parameter mask_ddrc__perf_mon21 = 32'hFFFFFFFF; parameter ddrc__perf_mon22 = 32'hF8006278; parameter val_ddrc__perf_mon22 = 32'h00000000; parameter mask_ddrc__perf_mon22 = 32'hFFFFFFFF; parameter ddrc__perf_mon23 = 32'hF800627C; parameter val_ddrc__perf_mon23 = 32'h00000000; parameter mask_ddrc__perf_mon23 = 32'hFFFFFFFF; parameter ddrc__perf_mon30 = 32'hF8006280; parameter val_ddrc__perf_mon30 = 32'h00000000; parameter mask_ddrc__perf_mon30 = 32'h0000FFFF; parameter ddrc__perf_mon31 = 32'hF8006284; parameter val_ddrc__perf_mon31 = 32'h00000000; parameter mask_ddrc__perf_mon31 = 32'h0000FFFF; parameter ddrc__perf_mon32 = 32'hF8006288; parameter val_ddrc__perf_mon32 = 32'h00000000; parameter mask_ddrc__perf_mon32 = 32'h0000FFFF; parameter ddrc__perf_mon33 = 32'hF800628C; parameter val_ddrc__perf_mon33 = 32'h00000000; parameter mask_ddrc__perf_mon33 = 32'h0000FFFF; parameter ddrc__trusted_mem_cfg = 32'hF8006290; parameter val_ddrc__trusted_mem_cfg = 32'h00000000; parameter mask_ddrc__trusted_mem_cfg = 32'h0000FFFF; parameter ddrc__excl_access_cfg0 = 32'hF8006294; parameter val_ddrc__excl_access_cfg0 = 32'h00000000; parameter mask_ddrc__excl_access_cfg0 = 32'h0003FFFF; parameter ddrc__excl_access_cfg1 = 32'hF8006298; parameter val_ddrc__excl_access_cfg1 = 32'h00000000; parameter mask_ddrc__excl_access_cfg1 = 32'h0003FFFF; parameter ddrc__excl_access_cfg2 = 32'hF800629C; parameter val_ddrc__excl_access_cfg2 = 32'h00000000; parameter mask_ddrc__excl_access_cfg2 = 32'h0003FFFF; parameter ddrc__excl_access_cfg3 = 32'hF80062A0; parameter val_ddrc__excl_access_cfg3 = 32'h00000000; parameter mask_ddrc__excl_access_cfg3 = 32'h0003FFFF; parameter ddrc__mode_reg_read = 32'hF80062A4; parameter val_ddrc__mode_reg_read = 32'h00000000; parameter mask_ddrc__mode_reg_read = 32'hFFFFFFFF; parameter ddrc__lpddr_ctrl0 = 32'hF80062A8; parameter val_ddrc__lpddr_ctrl0 = 32'h00000000; parameter mask_ddrc__lpddr_ctrl0 = 32'h00000FFF; parameter ddrc__lpddr_ctrl1 = 32'hF80062AC; parameter val_ddrc__lpddr_ctrl1 = 32'h00000000; parameter mask_ddrc__lpddr_ctrl1 = 32'hFFFFFFFF; parameter ddrc__lpddr_ctrl2 = 32'hF80062B0; parameter val_ddrc__lpddr_ctrl2 = 32'h003C0015; parameter mask_ddrc__lpddr_ctrl2 = 32'h003FFFFF; parameter ddrc__lpddr_ctrl3 = 32'hF80062B4; parameter val_ddrc__lpddr_ctrl3 = 32'h00000601; parameter mask_ddrc__lpddr_ctrl3 = 32'h0003FFFF; parameter ddrc__phy_wr_lvl_fsm = 32'hF80062B8; parameter val_ddrc__phy_wr_lvl_fsm = 32'h00004444; parameter mask_ddrc__phy_wr_lvl_fsm = 32'h00007FFF; parameter ddrc__phy_rd_lvl_fsm = 32'hF80062BC; parameter val_ddrc__phy_rd_lvl_fsm = 32'h00008888; parameter mask_ddrc__phy_rd_lvl_fsm = 32'h0000FFFF; parameter ddrc__phy_gate_lvl_fsm = 32'hF80062C0; parameter val_ddrc__phy_gate_lvl_fsm = 32'h00004444; parameter mask_ddrc__phy_gate_lvl_fsm = 32'h00007FFF; // ************************************************************ // Module debug_axim axim // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter debug_axim__GLOBAL_CTRL = 32'hF880C000; parameter val_debug_axim__GLOBAL_CTRL = 32'h00000002; parameter mask_debug_axim__GLOBAL_CTRL = 32'h00000003; parameter debug_axim__GLOBAL_STATUS = 32'hF880C004; parameter val_debug_axim__GLOBAL_STATUS = 32'h00001000; parameter mask_debug_axim__GLOBAL_STATUS = 32'h00001FC3; parameter debug_axim__FILTER_CTRL = 32'hF880C010; parameter val_debug_axim__FILTER_CTRL = 32'h00000000; parameter mask_debug_axim__FILTER_CTRL = 32'h0000007F; parameter debug_axim__TRIGGER_CTRL = 32'hF880C020; parameter val_debug_axim__TRIGGER_CTRL = 32'h00000000; parameter mask_debug_axim__TRIGGER_CTRL = 32'h0000FFFF; parameter debug_axim__TRIGGER_STATUS = 32'hF880C024; parameter val_debug_axim__TRIGGER_STATUS = 32'h00000000; parameter mask_debug_axim__TRIGGER_STATUS = 32'h00000003; parameter debug_axim__PACKET_CTRL = 32'hF880C030; parameter val_debug_axim__PACKET_CTRL = 32'h00070000; parameter mask_debug_axim__PACKET_CTRL = 32'h0007FFFF; parameter debug_axim__TOUT_CTRL = 32'hF880C040; parameter val_debug_axim__TOUT_CTRL = 32'h00000000; parameter mask_debug_axim__TOUT_CTRL = 32'h0000007F; parameter debug_axim__TOUT_THRESH = 32'hF880C044; parameter val_debug_axim__TOUT_THRESH = 32'h00008000; parameter mask_debug_axim__TOUT_THRESH = 32'hFFFFFFFF; parameter debug_axim__FIFO_CURRENT = 32'hF880C050; parameter val_debug_axim__FIFO_CURRENT = 32'h80000000; parameter mask_debug_axim__FIFO_CURRENT = 32'hFFFFFFFF; parameter debug_axim__FIFO_HYSTER = 32'hF880C054; parameter val_debug_axim__FIFO_HYSTER = 32'h00000100; parameter mask_debug_axim__FIFO_HYSTER = 32'h000003FF; parameter debug_axim__SYNC_CURRENT = 32'hF880C060; parameter val_debug_axim__SYNC_CURRENT = 32'h00000000; parameter mask_debug_axim__SYNC_CURRENT = 32'h00000FFF; parameter debug_axim__SYNC_RELOAD = 32'hF880C064; parameter val_debug_axim__SYNC_RELOAD = 32'h00000800; parameter mask_debug_axim__SYNC_RELOAD = 32'h00000FFF; parameter debug_axim__TSTMP_CURRENT = 32'hF880C070; parameter val_debug_axim__TSTMP_CURRENT = 32'h00000000; parameter mask_debug_axim__TSTMP_CURRENT = 32'h00000000; parameter debug_axim__ADDR0_MASK = 32'hF880C200; parameter val_debug_axim__ADDR0_MASK = 32'h7FFFFFFC; parameter mask_debug_axim__ADDR0_MASK = 32'h7FFFFFFF; parameter debug_axim__ADDR0_LOWER = 32'hF880C204; parameter val_debug_axim__ADDR0_LOWER = 32'h00000000; parameter mask_debug_axim__ADDR0_LOWER = 32'h7FFFFFFF; parameter debug_axim__ADDR0_UPPER = 32'hF880C208; parameter val_debug_axim__ADDR0_UPPER = 32'h7FFFFFFC; parameter mask_debug_axim__ADDR0_UPPER = 32'h7FFFFFFF; parameter debug_axim__ADDR0_MISC = 32'hF880C20C; parameter val_debug_axim__ADDR0_MISC = 32'h00000000; parameter mask_debug_axim__ADDR0_MISC = 32'h00007FFF; parameter debug_axim__ADDR1_MASK = 32'hF880C210; parameter val_debug_axim__ADDR1_MASK = 32'h7FFFFFFC; parameter mask_debug_axim__ADDR1_MASK = 32'h7FFFFFFF; parameter debug_axim__ADDR1_LOWER = 32'hF880C214; parameter val_debug_axim__ADDR1_LOWER = 32'h00000000; parameter mask_debug_axim__ADDR1_LOWER = 32'h7FFFFFFF; parameter debug_axim__ADDR1_UPPER = 32'hF880C218; parameter val_debug_axim__ADDR1_UPPER = 32'h7FFFFFFC; parameter mask_debug_axim__ADDR1_UPPER = 32'h7FFFFFFF; parameter debug_axim__ADDR1_MISC = 32'hF880C21C; parameter val_debug_axim__ADDR1_MISC = 32'h00000000; parameter mask_debug_axim__ADDR1_MISC = 32'h00007FFF; parameter debug_axim__ADDR2_MASK = 32'hF880C220; parameter val_debug_axim__ADDR2_MASK = 32'h7FFFFFFC; parameter mask_debug_axim__ADDR2_MASK = 32'h7FFFFFFF; parameter debug_axim__ADDR2_LOWER = 32'hF880C224; parameter val_debug_axim__ADDR2_LOWER = 32'h00000000; parameter mask_debug_axim__ADDR2_LOWER = 32'h7FFFFFFF; parameter debug_axim__ADDR2_UPPER = 32'hF880C228; parameter val_debug_axim__ADDR2_UPPER = 32'h7FFFFFFC; parameter mask_debug_axim__ADDR2_UPPER = 32'h7FFFFFFF; parameter debug_axim__ADDR2_MISC = 32'hF880C22C; parameter val_debug_axim__ADDR2_MISC = 32'h00000000; parameter mask_debug_axim__ADDR2_MISC = 32'h00007FFF; parameter debug_axim__ADDR3_MASK = 32'hF880C230; parameter val_debug_axim__ADDR3_MASK = 32'h7FFFFFFC; parameter mask_debug_axim__ADDR3_MASK = 32'h7FFFFFFF; parameter debug_axim__ADDR3_LOWER = 32'hF880C234; parameter val_debug_axim__ADDR3_LOWER = 32'h00000000; parameter mask_debug_axim__ADDR3_LOWER = 32'h7FFFFFFF; parameter debug_axim__ADDR3_UPPER = 32'hF880C238; parameter val_debug_axim__ADDR3_UPPER = 32'h7FFFFFFC; parameter mask_debug_axim__ADDR3_UPPER = 32'h7FFFFFFF; parameter debug_axim__ADDR3_MISC = 32'hF880C23C; parameter val_debug_axim__ADDR3_MISC = 32'h00000000; parameter mask_debug_axim__ADDR3_MISC = 32'h00007FFF; parameter debug_axim__ID0_MASK = 32'hF880C300; parameter val_debug_axim__ID0_MASK = 32'h000003FF; parameter mask_debug_axim__ID0_MASK = 32'h000003FF; parameter debug_axim__ID0_LOWER = 32'hF880C304; parameter val_debug_axim__ID0_LOWER = 32'h00000000; parameter mask_debug_axim__ID0_LOWER = 32'h000003FF; parameter debug_axim__ID0_UPPER = 32'hF880C308; parameter val_debug_axim__ID0_UPPER = 32'h000003FF; parameter mask_debug_axim__ID0_UPPER = 32'h000003FF; parameter debug_axim__ID0_MISC = 32'hF880C30C; parameter val_debug_axim__ID0_MISC = 32'h00000000; parameter mask_debug_axim__ID0_MISC = 32'h00003FFF; parameter debug_axim__ID1_MASK = 32'hF880C310; parameter val_debug_axim__ID1_MASK = 32'h000003FF; parameter mask_debug_axim__ID1_MASK = 32'h000003FF; parameter debug_axim__ID1_LOWER = 32'hF880C314; parameter val_debug_axim__ID1_LOWER = 32'h00000000; parameter mask_debug_axim__ID1_LOWER = 32'h000003FF; parameter debug_axim__ID1_UPPER = 32'hF880C318; parameter val_debug_axim__ID1_UPPER = 32'h000003FF; parameter mask_debug_axim__ID1_UPPER = 32'h000003FF; parameter debug_axim__ID1_MISC = 32'hF880C31C; parameter val_debug_axim__ID1_MISC = 32'h00000000; parameter mask_debug_axim__ID1_MISC = 32'h00003FFF; parameter debug_axim__ID2_MASK = 32'hF880C320; parameter val_debug_axim__ID2_MASK = 32'h000003FF; parameter mask_debug_axim__ID2_MASK = 32'h000003FF; parameter debug_axim__ID2_LOWER = 32'hF880C324; parameter val_debug_axim__ID2_LOWER = 32'h00000000; parameter mask_debug_axim__ID2_LOWER = 32'h000003FF; parameter debug_axim__ID2_UPPER = 32'hF880C328; parameter val_debug_axim__ID2_UPPER = 32'h000003FF; parameter mask_debug_axim__ID2_UPPER = 32'h000003FF; parameter debug_axim__ID2_MISC = 32'hF880C32C; parameter val_debug_axim__ID2_MISC = 32'h00000000; parameter mask_debug_axim__ID2_MISC = 32'h00003FFF; parameter debug_axim__ID3_MASK = 32'hF880C330; parameter val_debug_axim__ID3_MASK = 32'h000003FF; parameter mask_debug_axim__ID3_MASK = 32'h000003FF; parameter debug_axim__ID3_LOWER = 32'hF880C334; parameter val_debug_axim__ID3_LOWER = 32'h00000000; parameter mask_debug_axim__ID3_LOWER = 32'h000003FF; parameter debug_axim__ID3_UPPER = 32'hF880C338; parameter val_debug_axim__ID3_UPPER = 32'h000003FF; parameter mask_debug_axim__ID3_UPPER = 32'h000003FF; parameter debug_axim__ID3_MISC = 32'hF880C33C; parameter val_debug_axim__ID3_MISC = 32'h00000000; parameter mask_debug_axim__ID3_MISC = 32'h00003FFF; parameter debug_axim__AXI_SEL = 32'hF880C800; parameter val_debug_axim__AXI_SEL = 32'h00000000; parameter mask_debug_axim__AXI_SEL = 32'h00000007; parameter debug_axim__IT_TRIGOUT = 32'hF880CED0; parameter val_debug_axim__IT_TRIGOUT = 32'h00000000; parameter mask_debug_axim__IT_TRIGOUT = 32'h00000001; parameter debug_axim__IT_TRIGOUTACK = 32'hF880CED4; parameter val_debug_axim__IT_TRIGOUTACK = 32'h00000000; parameter mask_debug_axim__IT_TRIGOUTACK = 32'h00000000; parameter debug_axim__IT_TRIGIN = 32'hF880CED8; parameter val_debug_axim__IT_TRIGIN = 32'h00000000; parameter mask_debug_axim__IT_TRIGIN = 32'h00000000; parameter debug_axim__IT_TRIGINACK = 32'hF880CEDC; parameter val_debug_axim__IT_TRIGINACK = 32'h00000000; parameter mask_debug_axim__IT_TRIGINACK = 32'h00000001; parameter debug_axim__IT_ATBDATA = 32'hF880CEEC; parameter val_debug_axim__IT_ATBDATA = 32'h00000000; parameter mask_debug_axim__IT_ATBDATA = 32'h0000001F; parameter debug_axim__IT_ATBSTATUS = 32'hF880CEF0; parameter val_debug_axim__IT_ATBSTATUS = 32'h00000000; parameter mask_debug_axim__IT_ATBSTATUS = 32'h00000000; parameter debug_axim__IT_ATBCTRL1 = 32'hF880CEF4; parameter val_debug_axim__IT_ATBCTRL1 = 32'h00000000; parameter mask_debug_axim__IT_ATBCTRL1 = 32'h0000007F; parameter debug_axim__IT_ATBCTRL0 = 32'hF880CEF8; parameter val_debug_axim__IT_ATBCTRL0 = 32'h00000000; parameter mask_debug_axim__IT_ATBCTRL0 = 32'h000003FF; parameter debug_axim__IT_CTRL = 32'hF880CF00; parameter val_debug_axim__IT_CTRL = 32'h00000000; parameter mask_debug_axim__IT_CTRL = 32'h00000001; parameter debug_axim__CLAIM_SET = 32'hF880CFA0; parameter val_debug_axim__CLAIM_SET = 32'h00000001; parameter mask_debug_axim__CLAIM_SET = 32'h0000000F; parameter debug_axim__CLAIM_CLEAR = 32'hF880CFA4; parameter val_debug_axim__CLAIM_CLEAR = 32'h00000000; parameter mask_debug_axim__CLAIM_CLEAR = 32'h0000000F; parameter debug_axim__LOCK_ACCESS = 32'hF880CFB0; parameter val_debug_axim__LOCK_ACCESS = 32'h00000000; parameter mask_debug_axim__LOCK_ACCESS = 32'hFFFFFFFF; parameter debug_axim__LOCK_STATUS = 32'hF880CFB4; parameter val_debug_axim__LOCK_STATUS = 32'h00000003; parameter mask_debug_axim__LOCK_STATUS = 32'h00000007; parameter debug_axim__AUTH_STATUS = 32'hF880CFB8; parameter val_debug_axim__AUTH_STATUS = 32'h00000000; parameter mask_debug_axim__AUTH_STATUS = 32'h00000033; parameter debug_axim__DEV_ID = 32'hF880CFC8; parameter val_debug_axim__DEV_ID = 32'h00000000; parameter mask_debug_axim__DEV_ID = 32'hFFFFFFFF; parameter debug_axim__DEV_TYPE = 32'hF880CFCC; parameter val_debug_axim__DEV_TYPE = 32'h00000043; parameter mask_debug_axim__DEV_TYPE = 32'hFFFFFFFF; parameter debug_axim__PERIPHID4 = 32'hF880CFD0; parameter val_debug_axim__PERIPHID4 = 32'h00000003; parameter mask_debug_axim__PERIPHID4 = 32'hFFFFFFFF; parameter debug_axim__PERIPHID5 = 32'hF880CFD4; parameter val_debug_axim__PERIPHID5 = 32'h00000000; parameter mask_debug_axim__PERIPHID5 = 32'hFFFFFFFF; parameter debug_axim__PERIPHID6 = 32'hF880CFD8; parameter val_debug_axim__PERIPHID6 = 32'h00000000; parameter mask_debug_axim__PERIPHID6 = 32'hFFFFFFFF; parameter debug_axim__PERIPHID7 = 32'hF880CFDC; parameter val_debug_axim__PERIPHID7 = 32'h00000000; parameter mask_debug_axim__PERIPHID7 = 32'hFFFFFFFF; parameter debug_axim__PERIPHID0 = 32'hF880CFE0; parameter val_debug_axim__PERIPHID0 = 32'h000000B2; parameter mask_debug_axim__PERIPHID0 = 32'hFFFFFFFF; parameter debug_axim__PERIPHID1 = 32'hF880CFE4; parameter val_debug_axim__PERIPHID1 = 32'h00000093; parameter mask_debug_axim__PERIPHID1 = 32'hFFFFFFFF; parameter debug_axim__PERIPHID2 = 32'hF880CFE8; parameter val_debug_axim__PERIPHID2 = 32'h00000008; parameter mask_debug_axim__PERIPHID2 = 32'hFFFFFFFF; parameter debug_axim__PERIPHID3 = 32'hF880CFEC; parameter val_debug_axim__PERIPHID3 = 32'h00000002; parameter mask_debug_axim__PERIPHID3 = 32'hFFFFFFFF; parameter debug_axim__COMPID0 = 32'hF880CFF0; parameter val_debug_axim__COMPID0 = 32'h0000000D; parameter mask_debug_axim__COMPID0 = 32'hFFFFFFFF; parameter debug_axim__COMPID1 = 32'hF880CFF4; parameter val_debug_axim__COMPID1 = 32'h00000090; parameter mask_debug_axim__COMPID1 = 32'hFFFFFFFF; parameter debug_axim__COMPID2 = 32'hF880CFF8; parameter val_debug_axim__COMPID2 = 32'h00000005; parameter mask_debug_axim__COMPID2 = 32'hFFFFFFFF; parameter debug_axim__COMPID3 = 32'hF880CFFC; parameter val_debug_axim__COMPID3 = 32'h000000B1; parameter mask_debug_axim__COMPID3 = 32'hFFFFFFFF; // ************************************************************ // Module debug_cpu_cti0 cti // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter debug_cpu_cti0__CTICONTROL = 32'hF8898000; parameter val_debug_cpu_cti0__CTICONTROL = 32'h00000000; parameter mask_debug_cpu_cti0__CTICONTROL = 32'h00000001; parameter debug_cpu_cti0__CTIINTACK = 32'hF8898010; parameter val_debug_cpu_cti0__CTIINTACK = 32'h00000000; parameter mask_debug_cpu_cti0__CTIINTACK = 32'h000000FF; parameter debug_cpu_cti0__CTIAPPSET = 32'hF8898014; parameter val_debug_cpu_cti0__CTIAPPSET = 32'h00000000; parameter mask_debug_cpu_cti0__CTIAPPSET = 32'h0000000F; parameter debug_cpu_cti0__CTIAPPCLEAR = 32'hF8898018; parameter val_debug_cpu_cti0__CTIAPPCLEAR = 32'h00000000; parameter mask_debug_cpu_cti0__CTIAPPCLEAR = 32'h0000000F; parameter debug_cpu_cti0__CTIAPPPULSE = 32'hF889801C; parameter val_debug_cpu_cti0__CTIAPPPULSE = 32'h00000000; parameter mask_debug_cpu_cti0__CTIAPPPULSE = 32'h0000000F; parameter debug_cpu_cti0__CTIINEN0 = 32'hF8898020; parameter val_debug_cpu_cti0__CTIINEN0 = 32'h00000000; parameter mask_debug_cpu_cti0__CTIINEN0 = 32'h0000000F; parameter debug_cpu_cti0__CTIINEN1 = 32'hF8898024; parameter val_debug_cpu_cti0__CTIINEN1 = 32'h00000000; parameter mask_debug_cpu_cti0__CTIINEN1 = 32'h0000000F; parameter debug_cpu_cti0__CTIINEN2 = 32'hF8898028; parameter val_debug_cpu_cti0__CTIINEN2 = 32'h00000000; parameter mask_debug_cpu_cti0__CTIINEN2 = 32'h0000000F; parameter debug_cpu_cti0__CTIINEN3 = 32'hF889802C; parameter val_debug_cpu_cti0__CTIINEN3 = 32'h00000000; parameter mask_debug_cpu_cti0__CTIINEN3 = 32'h0000000F; parameter debug_cpu_cti0__CTIINEN4 = 32'hF8898030; parameter val_debug_cpu_cti0__CTIINEN4 = 32'h00000000; parameter mask_debug_cpu_cti0__CTIINEN4 = 32'h0000000F; parameter debug_cpu_cti0__CTIINEN5 = 32'hF8898034; parameter val_debug_cpu_cti0__CTIINEN5 = 32'h00000000; parameter mask_debug_cpu_cti0__CTIINEN5 = 32'h0000000F; parameter debug_cpu_cti0__CTIINEN6 = 32'hF8898038; parameter val_debug_cpu_cti0__CTIINEN6 = 32'h00000000; parameter mask_debug_cpu_cti0__CTIINEN6 = 32'h0000000F; parameter debug_cpu_cti0__CTIINEN7 = 32'hF889803C; parameter val_debug_cpu_cti0__CTIINEN7 = 32'h00000000; parameter mask_debug_cpu_cti0__CTIINEN7 = 32'h0000000F; parameter debug_cpu_cti0__CTIOUTEN0 = 32'hF88980A0; parameter val_debug_cpu_cti0__CTIOUTEN0 = 32'h00000000; parameter mask_debug_cpu_cti0__CTIOUTEN0 = 32'h0000000F; parameter debug_cpu_cti0__CTIOUTEN1 = 32'hF88980A4; parameter val_debug_cpu_cti0__CTIOUTEN1 = 32'h00000000; parameter mask_debug_cpu_cti0__CTIOUTEN1 = 32'h0000000F; parameter debug_cpu_cti0__CTIOUTEN2 = 32'hF88980A8; parameter val_debug_cpu_cti0__CTIOUTEN2 = 32'h00000000; parameter mask_debug_cpu_cti0__CTIOUTEN2 = 32'h0000000F; parameter debug_cpu_cti0__CTIOUTEN3 = 32'hF88980AC; parameter val_debug_cpu_cti0__CTIOUTEN3 = 32'h00000000; parameter mask_debug_cpu_cti0__CTIOUTEN3 = 32'h0000000F; parameter debug_cpu_cti0__CTIOUTEN4 = 32'hF88980B0; parameter val_debug_cpu_cti0__CTIOUTEN4 = 32'h00000000; parameter mask_debug_cpu_cti0__CTIOUTEN4 = 32'h0000000F; parameter debug_cpu_cti0__CTIOUTEN5 = 32'hF88980B4; parameter val_debug_cpu_cti0__CTIOUTEN5 = 32'h00000000; parameter mask_debug_cpu_cti0__CTIOUTEN5 = 32'h0000000F; parameter debug_cpu_cti0__CTIOUTEN6 = 32'hF88980B8; parameter val_debug_cpu_cti0__CTIOUTEN6 = 32'h00000000; parameter mask_debug_cpu_cti0__CTIOUTEN6 = 32'h0000000F; parameter debug_cpu_cti0__CTIOUTEN7 = 32'hF88980BC; parameter val_debug_cpu_cti0__CTIOUTEN7 = 32'h00000000; parameter mask_debug_cpu_cti0__CTIOUTEN7 = 32'h0000000F; parameter debug_cpu_cti0__CTITRIGINSTATUS = 32'hF8898130; parameter val_debug_cpu_cti0__CTITRIGINSTATUS = 32'h00000000; parameter mask_debug_cpu_cti0__CTITRIGINSTATUS = 32'h00000000; parameter debug_cpu_cti0__CTITRIGOUTSTATUS = 32'hF8898134; parameter val_debug_cpu_cti0__CTITRIGOUTSTATUS = 32'h00000000; parameter mask_debug_cpu_cti0__CTITRIGOUTSTATUS = 32'h000000FF; parameter debug_cpu_cti0__CTICHINSTATUS = 32'hF8898138; parameter val_debug_cpu_cti0__CTICHINSTATUS = 32'h00000000; parameter mask_debug_cpu_cti0__CTICHINSTATUS = 32'h00000000; parameter debug_cpu_cti0__CTICHOUTSTATUS = 32'hF889813C; parameter val_debug_cpu_cti0__CTICHOUTSTATUS = 32'h00000000; parameter mask_debug_cpu_cti0__CTICHOUTSTATUS = 32'h0000000F; parameter debug_cpu_cti0__CTIGATE = 32'hF8898140; parameter val_debug_cpu_cti0__CTIGATE = 32'h0000000F; parameter mask_debug_cpu_cti0__CTIGATE = 32'h0000000F; parameter debug_cpu_cti0__ASICCTL = 32'hF8898144; parameter val_debug_cpu_cti0__ASICCTL = 32'h00000000; parameter mask_debug_cpu_cti0__ASICCTL = 32'h000000FF; parameter debug_cpu_cti0__ITCHINACK = 32'hF8898EDC; parameter val_debug_cpu_cti0__ITCHINACK = 32'h00000000; parameter mask_debug_cpu_cti0__ITCHINACK = 32'h0000000F; parameter debug_cpu_cti0__ITTRIGINACK = 32'hF8898EE0; parameter val_debug_cpu_cti0__ITTRIGINACK = 32'h00000000; parameter mask_debug_cpu_cti0__ITTRIGINACK = 32'h000000FF; parameter debug_cpu_cti0__ITCHOUT = 32'hF8898EE4; parameter val_debug_cpu_cti0__ITCHOUT = 32'h00000000; parameter mask_debug_cpu_cti0__ITCHOUT = 32'h0000000F; parameter debug_cpu_cti0__ITTRIGOUT = 32'hF8898EE8; parameter val_debug_cpu_cti0__ITTRIGOUT = 32'h00000000; parameter mask_debug_cpu_cti0__ITTRIGOUT = 32'h000000FF; parameter debug_cpu_cti0__ITCHOUTACK = 32'hF8898EEC; parameter val_debug_cpu_cti0__ITCHOUTACK = 32'h00000000; parameter mask_debug_cpu_cti0__ITCHOUTACK = 32'h0000000F; parameter debug_cpu_cti0__ITTRIGOUTACK = 32'hF8898EF0; parameter val_debug_cpu_cti0__ITTRIGOUTACK = 32'h00000000; parameter mask_debug_cpu_cti0__ITTRIGOUTACK = 32'h000000FF; parameter debug_cpu_cti0__ITCHIN = 32'hF8898EF4; parameter val_debug_cpu_cti0__ITCHIN = 32'h00000000; parameter mask_debug_cpu_cti0__ITCHIN = 32'h0000000F; parameter debug_cpu_cti0__ITTRIGIN = 32'hF8898EF8; parameter val_debug_cpu_cti0__ITTRIGIN = 32'h00000000; parameter mask_debug_cpu_cti0__ITTRIGIN = 32'h000000FF; parameter debug_cpu_cti0__ITCTRL = 32'hF8898F00; parameter val_debug_cpu_cti0__ITCTRL = 32'h00000000; parameter mask_debug_cpu_cti0__ITCTRL = 32'h00000001; parameter debug_cpu_cti0__CTSR = 32'hF8898FA0; parameter val_debug_cpu_cti0__CTSR = 32'h0000000F; parameter mask_debug_cpu_cti0__CTSR = 32'h0000000F; parameter debug_cpu_cti0__CTCR = 32'hF8898FA4; parameter val_debug_cpu_cti0__CTCR = 32'h00000000; parameter mask_debug_cpu_cti0__CTCR = 32'h0000000F; parameter debug_cpu_cti0__LAR = 32'hF8898FB0; parameter val_debug_cpu_cti0__LAR = 32'h00000000; parameter mask_debug_cpu_cti0__LAR = 32'hFFFFFFFF; parameter debug_cpu_cti0__LSR = 32'hF8898FB4; parameter val_debug_cpu_cti0__LSR = 32'h00000003; parameter mask_debug_cpu_cti0__LSR = 32'h00000007; parameter debug_cpu_cti0__ASR = 32'hF8898FB8; parameter val_debug_cpu_cti0__ASR = 32'h00000005; parameter mask_debug_cpu_cti0__ASR = 32'h00000005; parameter debug_cpu_cti0__DEVID = 32'hF8898FC8; parameter val_debug_cpu_cti0__DEVID = 32'h00040800; parameter mask_debug_cpu_cti0__DEVID = 32'h000FFFFF; parameter debug_cpu_cti0__DTIR = 32'hF8898FCC; parameter val_debug_cpu_cti0__DTIR = 32'h00000014; parameter mask_debug_cpu_cti0__DTIR = 32'h000000FF; parameter debug_cpu_cti0__PERIPHID4 = 32'hF8898FD0; parameter val_debug_cpu_cti0__PERIPHID4 = 32'h00000004; parameter mask_debug_cpu_cti0__PERIPHID4 = 32'h000000FF; parameter debug_cpu_cti0__PERIPHID5 = 32'hF8898FD4; parameter val_debug_cpu_cti0__PERIPHID5 = 32'h00000000; parameter mask_debug_cpu_cti0__PERIPHID5 = 32'h000000FF; parameter debug_cpu_cti0__PERIPHID6 = 32'hF8898FD8; parameter val_debug_cpu_cti0__PERIPHID6 = 32'h00000000; parameter mask_debug_cpu_cti0__PERIPHID6 = 32'h000000FF; parameter debug_cpu_cti0__PERIPHID7 = 32'hF8898FDC; parameter val_debug_cpu_cti0__PERIPHID7 = 32'h00000000; parameter mask_debug_cpu_cti0__PERIPHID7 = 32'h000000FF; parameter debug_cpu_cti0__PERIPHID0 = 32'hF8898FE0; parameter val_debug_cpu_cti0__PERIPHID0 = 32'h00000006; parameter mask_debug_cpu_cti0__PERIPHID0 = 32'h000000FF; parameter debug_cpu_cti0__PERIPHID1 = 32'hF8898FE4; parameter val_debug_cpu_cti0__PERIPHID1 = 32'h000000B9; parameter mask_debug_cpu_cti0__PERIPHID1 = 32'h000000FF; parameter debug_cpu_cti0__PERIPHID2 = 32'hF8898FE8; parameter val_debug_cpu_cti0__PERIPHID2 = 32'h0000002B; parameter mask_debug_cpu_cti0__PERIPHID2 = 32'h000000FF; parameter debug_cpu_cti0__PERIPHID3 = 32'hF8898FEC; parameter val_debug_cpu_cti0__PERIPHID3 = 32'h00000000; parameter mask_debug_cpu_cti0__PERIPHID3 = 32'h000000FF; parameter debug_cpu_cti0__COMPID0 = 32'hF8898FF0; parameter val_debug_cpu_cti0__COMPID0 = 32'h0000000D; parameter mask_debug_cpu_cti0__COMPID0 = 32'h000000FF; parameter debug_cpu_cti0__COMPID1 = 32'hF8898FF4; parameter val_debug_cpu_cti0__COMPID1 = 32'h00000090; parameter mask_debug_cpu_cti0__COMPID1 = 32'h000000FF; parameter debug_cpu_cti0__COMPID2 = 32'hF8898FF8; parameter val_debug_cpu_cti0__COMPID2 = 32'h00000005; parameter mask_debug_cpu_cti0__COMPID2 = 32'h000000FF; parameter debug_cpu_cti0__COMPID3 = 32'hF8898FFC; parameter val_debug_cpu_cti0__COMPID3 = 32'h000000B1; parameter mask_debug_cpu_cti0__COMPID3 = 32'h000000FF; // ************************************************************ // Module debug_cpu_cti1 cti // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter debug_cpu_cti1__CTICONTROL = 32'hF8899000; parameter val_debug_cpu_cti1__CTICONTROL = 32'h00000000; parameter mask_debug_cpu_cti1__CTICONTROL = 32'h00000001; parameter debug_cpu_cti1__CTIINTACK = 32'hF8899010; parameter val_debug_cpu_cti1__CTIINTACK = 32'h00000000; parameter mask_debug_cpu_cti1__CTIINTACK = 32'h000000FF; parameter debug_cpu_cti1__CTIAPPSET = 32'hF8899014; parameter val_debug_cpu_cti1__CTIAPPSET = 32'h00000000; parameter mask_debug_cpu_cti1__CTIAPPSET = 32'h0000000F; parameter debug_cpu_cti1__CTIAPPCLEAR = 32'hF8899018; parameter val_debug_cpu_cti1__CTIAPPCLEAR = 32'h00000000; parameter mask_debug_cpu_cti1__CTIAPPCLEAR = 32'h0000000F; parameter debug_cpu_cti1__CTIAPPPULSE = 32'hF889901C; parameter val_debug_cpu_cti1__CTIAPPPULSE = 32'h00000000; parameter mask_debug_cpu_cti1__CTIAPPPULSE = 32'h0000000F; parameter debug_cpu_cti1__CTIINEN0 = 32'hF8899020; parameter val_debug_cpu_cti1__CTIINEN0 = 32'h00000000; parameter mask_debug_cpu_cti1__CTIINEN0 = 32'h0000000F; parameter debug_cpu_cti1__CTIINEN1 = 32'hF8899024; parameter val_debug_cpu_cti1__CTIINEN1 = 32'h00000000; parameter mask_debug_cpu_cti1__CTIINEN1 = 32'h0000000F; parameter debug_cpu_cti1__CTIINEN2 = 32'hF8899028; parameter val_debug_cpu_cti1__CTIINEN2 = 32'h00000000; parameter mask_debug_cpu_cti1__CTIINEN2 = 32'h0000000F; parameter debug_cpu_cti1__CTIINEN3 = 32'hF889902C; parameter val_debug_cpu_cti1__CTIINEN3 = 32'h00000000; parameter mask_debug_cpu_cti1__CTIINEN3 = 32'h0000000F; parameter debug_cpu_cti1__CTIINEN4 = 32'hF8899030; parameter val_debug_cpu_cti1__CTIINEN4 = 32'h00000000; parameter mask_debug_cpu_cti1__CTIINEN4 = 32'h0000000F; parameter debug_cpu_cti1__CTIINEN5 = 32'hF8899034; parameter val_debug_cpu_cti1__CTIINEN5 = 32'h00000000; parameter mask_debug_cpu_cti1__CTIINEN5 = 32'h0000000F; parameter debug_cpu_cti1__CTIINEN6 = 32'hF8899038; parameter val_debug_cpu_cti1__CTIINEN6 = 32'h00000000; parameter mask_debug_cpu_cti1__CTIINEN6 = 32'h0000000F; parameter debug_cpu_cti1__CTIINEN7 = 32'hF889903C; parameter val_debug_cpu_cti1__CTIINEN7 = 32'h00000000; parameter mask_debug_cpu_cti1__CTIINEN7 = 32'h0000000F; parameter debug_cpu_cti1__CTIOUTEN0 = 32'hF88990A0; parameter val_debug_cpu_cti1__CTIOUTEN0 = 32'h00000000; parameter mask_debug_cpu_cti1__CTIOUTEN0 = 32'h0000000F; parameter debug_cpu_cti1__CTIOUTEN1 = 32'hF88990A4; parameter val_debug_cpu_cti1__CTIOUTEN1 = 32'h00000000; parameter mask_debug_cpu_cti1__CTIOUTEN1 = 32'h0000000F; parameter debug_cpu_cti1__CTIOUTEN2 = 32'hF88990A8; parameter val_debug_cpu_cti1__CTIOUTEN2 = 32'h00000000; parameter mask_debug_cpu_cti1__CTIOUTEN2 = 32'h0000000F; parameter debug_cpu_cti1__CTIOUTEN3 = 32'hF88990AC; parameter val_debug_cpu_cti1__CTIOUTEN3 = 32'h00000000; parameter mask_debug_cpu_cti1__CTIOUTEN3 = 32'h0000000F; parameter debug_cpu_cti1__CTIOUTEN4 = 32'hF88990B0; parameter val_debug_cpu_cti1__CTIOUTEN4 = 32'h00000000; parameter mask_debug_cpu_cti1__CTIOUTEN4 = 32'h0000000F; parameter debug_cpu_cti1__CTIOUTEN5 = 32'hF88990B4; parameter val_debug_cpu_cti1__CTIOUTEN5 = 32'h00000000; parameter mask_debug_cpu_cti1__CTIOUTEN5 = 32'h0000000F; parameter debug_cpu_cti1__CTIOUTEN6 = 32'hF88990B8; parameter val_debug_cpu_cti1__CTIOUTEN6 = 32'h00000000; parameter mask_debug_cpu_cti1__CTIOUTEN6 = 32'h0000000F; parameter debug_cpu_cti1__CTIOUTEN7 = 32'hF88990BC; parameter val_debug_cpu_cti1__CTIOUTEN7 = 32'h00000000; parameter mask_debug_cpu_cti1__CTIOUTEN7 = 32'h0000000F; parameter debug_cpu_cti1__CTITRIGINSTATUS = 32'hF8899130; parameter val_debug_cpu_cti1__CTITRIGINSTATUS = 32'h00000000; parameter mask_debug_cpu_cti1__CTITRIGINSTATUS = 32'h00000000; parameter debug_cpu_cti1__CTITRIGOUTSTATUS = 32'hF8899134; parameter val_debug_cpu_cti1__CTITRIGOUTSTATUS = 32'h00000000; parameter mask_debug_cpu_cti1__CTITRIGOUTSTATUS = 32'h000000FF; parameter debug_cpu_cti1__CTICHINSTATUS = 32'hF8899138; parameter val_debug_cpu_cti1__CTICHINSTATUS = 32'h00000000; parameter mask_debug_cpu_cti1__CTICHINSTATUS = 32'h00000000; parameter debug_cpu_cti1__CTICHOUTSTATUS = 32'hF889913C; parameter val_debug_cpu_cti1__CTICHOUTSTATUS = 32'h00000000; parameter mask_debug_cpu_cti1__CTICHOUTSTATUS = 32'h0000000F; parameter debug_cpu_cti1__CTIGATE = 32'hF8899140; parameter val_debug_cpu_cti1__CTIGATE = 32'h0000000F; parameter mask_debug_cpu_cti1__CTIGATE = 32'h0000000F; parameter debug_cpu_cti1__ASICCTL = 32'hF8899144; parameter val_debug_cpu_cti1__ASICCTL = 32'h00000000; parameter mask_debug_cpu_cti1__ASICCTL = 32'h000000FF; parameter debug_cpu_cti1__ITCHINACK = 32'hF8899EDC; parameter val_debug_cpu_cti1__ITCHINACK = 32'h00000000; parameter mask_debug_cpu_cti1__ITCHINACK = 32'h0000000F; parameter debug_cpu_cti1__ITTRIGINACK = 32'hF8899EE0; parameter val_debug_cpu_cti1__ITTRIGINACK = 32'h00000000; parameter mask_debug_cpu_cti1__ITTRIGINACK = 32'h000000FF; parameter debug_cpu_cti1__ITCHOUT = 32'hF8899EE4; parameter val_debug_cpu_cti1__ITCHOUT = 32'h00000000; parameter mask_debug_cpu_cti1__ITCHOUT = 32'h0000000F; parameter debug_cpu_cti1__ITTRIGOUT = 32'hF8899EE8; parameter val_debug_cpu_cti1__ITTRIGOUT = 32'h00000000; parameter mask_debug_cpu_cti1__ITTRIGOUT = 32'h000000FF; parameter debug_cpu_cti1__ITCHOUTACK = 32'hF8899EEC; parameter val_debug_cpu_cti1__ITCHOUTACK = 32'h00000000; parameter mask_debug_cpu_cti1__ITCHOUTACK = 32'h0000000F; parameter debug_cpu_cti1__ITTRIGOUTACK = 32'hF8899EF0; parameter val_debug_cpu_cti1__ITTRIGOUTACK = 32'h00000000; parameter mask_debug_cpu_cti1__ITTRIGOUTACK = 32'h000000FF; parameter debug_cpu_cti1__ITCHIN = 32'hF8899EF4; parameter val_debug_cpu_cti1__ITCHIN = 32'h00000000; parameter mask_debug_cpu_cti1__ITCHIN = 32'h0000000F; parameter debug_cpu_cti1__ITTRIGIN = 32'hF8899EF8; parameter val_debug_cpu_cti1__ITTRIGIN = 32'h00000000; parameter mask_debug_cpu_cti1__ITTRIGIN = 32'h000000FF; parameter debug_cpu_cti1__ITCTRL = 32'hF8899F00; parameter val_debug_cpu_cti1__ITCTRL = 32'h00000000; parameter mask_debug_cpu_cti1__ITCTRL = 32'h00000001; parameter debug_cpu_cti1__CTSR = 32'hF8899FA0; parameter val_debug_cpu_cti1__CTSR = 32'h0000000F; parameter mask_debug_cpu_cti1__CTSR = 32'h0000000F; parameter debug_cpu_cti1__CTCR = 32'hF8899FA4; parameter val_debug_cpu_cti1__CTCR = 32'h00000000; parameter mask_debug_cpu_cti1__CTCR = 32'h0000000F; parameter debug_cpu_cti1__LAR = 32'hF8899FB0; parameter val_debug_cpu_cti1__LAR = 32'h00000000; parameter mask_debug_cpu_cti1__LAR = 32'hFFFFFFFF; parameter debug_cpu_cti1__LSR = 32'hF8899FB4; parameter val_debug_cpu_cti1__LSR = 32'h00000003; parameter mask_debug_cpu_cti1__LSR = 32'h00000007; parameter debug_cpu_cti1__ASR = 32'hF8899FB8; parameter val_debug_cpu_cti1__ASR = 32'h00000005; parameter mask_debug_cpu_cti1__ASR = 32'h00000005; parameter debug_cpu_cti1__DEVID = 32'hF8899FC8; parameter val_debug_cpu_cti1__DEVID = 32'h00040800; parameter mask_debug_cpu_cti1__DEVID = 32'h000FFFFF; parameter debug_cpu_cti1__DTIR = 32'hF8899FCC; parameter val_debug_cpu_cti1__DTIR = 32'h00000014; parameter mask_debug_cpu_cti1__DTIR = 32'h000000FF; parameter debug_cpu_cti1__PERIPHID4 = 32'hF8899FD0; parameter val_debug_cpu_cti1__PERIPHID4 = 32'h00000004; parameter mask_debug_cpu_cti1__PERIPHID4 = 32'h000000FF; parameter debug_cpu_cti1__PERIPHID5 = 32'hF8899FD4; parameter val_debug_cpu_cti1__PERIPHID5 = 32'h00000000; parameter mask_debug_cpu_cti1__PERIPHID5 = 32'h000000FF; parameter debug_cpu_cti1__PERIPHID6 = 32'hF8899FD8; parameter val_debug_cpu_cti1__PERIPHID6 = 32'h00000000; parameter mask_debug_cpu_cti1__PERIPHID6 = 32'h000000FF; parameter debug_cpu_cti1__PERIPHID7 = 32'hF8899FDC; parameter val_debug_cpu_cti1__PERIPHID7 = 32'h00000000; parameter mask_debug_cpu_cti1__PERIPHID7 = 32'h000000FF; parameter debug_cpu_cti1__PERIPHID0 = 32'hF8899FE0; parameter val_debug_cpu_cti1__PERIPHID0 = 32'h00000006; parameter mask_debug_cpu_cti1__PERIPHID0 = 32'h000000FF; parameter debug_cpu_cti1__PERIPHID1 = 32'hF8899FE4; parameter val_debug_cpu_cti1__PERIPHID1 = 32'h000000B9; parameter mask_debug_cpu_cti1__PERIPHID1 = 32'h000000FF; parameter debug_cpu_cti1__PERIPHID2 = 32'hF8899FE8; parameter val_debug_cpu_cti1__PERIPHID2 = 32'h0000002B; parameter mask_debug_cpu_cti1__PERIPHID2 = 32'h000000FF; parameter debug_cpu_cti1__PERIPHID3 = 32'hF8899FEC; parameter val_debug_cpu_cti1__PERIPHID3 = 32'h00000000; parameter mask_debug_cpu_cti1__PERIPHID3 = 32'h000000FF; parameter debug_cpu_cti1__COMPID0 = 32'hF8899FF0; parameter val_debug_cpu_cti1__COMPID0 = 32'h0000000D; parameter mask_debug_cpu_cti1__COMPID0 = 32'h000000FF; parameter debug_cpu_cti1__COMPID1 = 32'hF8899FF4; parameter val_debug_cpu_cti1__COMPID1 = 32'h00000090; parameter mask_debug_cpu_cti1__COMPID1 = 32'h000000FF; parameter debug_cpu_cti1__COMPID2 = 32'hF8899FF8; parameter val_debug_cpu_cti1__COMPID2 = 32'h00000005; parameter mask_debug_cpu_cti1__COMPID2 = 32'h000000FF; parameter debug_cpu_cti1__COMPID3 = 32'hF8899FFC; parameter val_debug_cpu_cti1__COMPID3 = 32'h000000B1; parameter mask_debug_cpu_cti1__COMPID3 = 32'h000000FF; // ************************************************************ // Module debug_cpu_pmu0 cortexa9_pmu // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter debug_cpu_pmu0__PMXEVCNTR0 = 32'hF8891000; parameter val_debug_cpu_pmu0__PMXEVCNTR0 = 32'h00000000; parameter mask_debug_cpu_pmu0__PMXEVCNTR0 = 32'h00000000; parameter debug_cpu_pmu0__PMXEVCNTR1 = 32'hF8891004; parameter val_debug_cpu_pmu0__PMXEVCNTR1 = 32'h00000000; parameter mask_debug_cpu_pmu0__PMXEVCNTR1 = 32'h00000000; parameter debug_cpu_pmu0__PMXEVCNTR2 = 32'hF8891008; parameter val_debug_cpu_pmu0__PMXEVCNTR2 = 32'h00000000; parameter mask_debug_cpu_pmu0__PMXEVCNTR2 = 32'h00000000; parameter debug_cpu_pmu0__PMXEVCNTR3 = 32'hF889100C; parameter val_debug_cpu_pmu0__PMXEVCNTR3 = 32'h00000000; parameter mask_debug_cpu_pmu0__PMXEVCNTR3 = 32'h00000000; parameter debug_cpu_pmu0__PMXEVCNTR4 = 32'hF8891010; parameter val_debug_cpu_pmu0__PMXEVCNTR4 = 32'h00000000; parameter mask_debug_cpu_pmu0__PMXEVCNTR4 = 32'h00000000; parameter debug_cpu_pmu0__PMXEVCNTR5 = 32'hF8891014; parameter val_debug_cpu_pmu0__PMXEVCNTR5 = 32'h00000000; parameter mask_debug_cpu_pmu0__PMXEVCNTR5 = 32'h00000000; parameter debug_cpu_pmu0__PMCCNTR = 32'hF889107C; parameter val_debug_cpu_pmu0__PMCCNTR = 32'h00000000; parameter mask_debug_cpu_pmu0__PMCCNTR = 32'h00000000; parameter debug_cpu_pmu0__PMXEVTYPER0 = 32'hF8891400; parameter val_debug_cpu_pmu0__PMXEVTYPER0 = 32'h00000000; parameter mask_debug_cpu_pmu0__PMXEVTYPER0 = 32'h00000000; parameter debug_cpu_pmu0__PMXEVTYPER1 = 32'hF8891404; parameter val_debug_cpu_pmu0__PMXEVTYPER1 = 32'h00000000; parameter mask_debug_cpu_pmu0__PMXEVTYPER1 = 32'h00000000; parameter debug_cpu_pmu0__PMXEVTYPER2 = 32'hF8891408; parameter val_debug_cpu_pmu0__PMXEVTYPER2 = 32'h00000000; parameter mask_debug_cpu_pmu0__PMXEVTYPER2 = 32'h00000000; parameter debug_cpu_pmu0__PMXEVTYPER3 = 32'hF889140C; parameter val_debug_cpu_pmu0__PMXEVTYPER3 = 32'h00000000; parameter mask_debug_cpu_pmu0__PMXEVTYPER3 = 32'h00000000; parameter debug_cpu_pmu0__PMXEVTYPER4 = 32'hF8891410; parameter val_debug_cpu_pmu0__PMXEVTYPER4 = 32'h00000000; parameter mask_debug_cpu_pmu0__PMXEVTYPER4 = 32'h00000000; parameter debug_cpu_pmu0__PMXEVTYPER5 = 32'hF8891414; parameter val_debug_cpu_pmu0__PMXEVTYPER5 = 32'h00000000; parameter mask_debug_cpu_pmu0__PMXEVTYPER5 = 32'h00000000; parameter debug_cpu_pmu0__PMCNTENSET = 32'hF8891C00; parameter val_debug_cpu_pmu0__PMCNTENSET = 32'h00000000; parameter mask_debug_cpu_pmu0__PMCNTENSET = 32'hFFFFFFFF; parameter debug_cpu_pmu0__PMCNTENCLR = 32'hF8891C20; parameter val_debug_cpu_pmu0__PMCNTENCLR = 32'h00000000; parameter mask_debug_cpu_pmu0__PMCNTENCLR = 32'hFFFFFFFF; parameter debug_cpu_pmu0__PMINTENSET = 32'hF8891C40; parameter val_debug_cpu_pmu0__PMINTENSET = 32'h00000000; parameter mask_debug_cpu_pmu0__PMINTENSET = 32'hFFFFFFFF; parameter debug_cpu_pmu0__PMINTENCLR = 32'hF8891C60; parameter val_debug_cpu_pmu0__PMINTENCLR = 32'h00000000; parameter mask_debug_cpu_pmu0__PMINTENCLR = 32'hFFFFFFFF; parameter debug_cpu_pmu0__PMOVSR = 32'hF8891C80; parameter val_debug_cpu_pmu0__PMOVSR = 32'h00000000; parameter mask_debug_cpu_pmu0__PMOVSR = 32'h00000000; parameter debug_cpu_pmu0__PMSWINC = 32'hF8891CA0; parameter val_debug_cpu_pmu0__PMSWINC = 32'h00000000; parameter mask_debug_cpu_pmu0__PMSWINC = 32'h00000000; parameter debug_cpu_pmu0__PMCR = 32'hF8891E04; parameter val_debug_cpu_pmu0__PMCR = 32'h41093000; parameter mask_debug_cpu_pmu0__PMCR = 32'hFFFFFFFF; parameter debug_cpu_pmu0__PMUSERENR = 32'hF8891E08; parameter val_debug_cpu_pmu0__PMUSERENR = 32'h00000000; parameter mask_debug_cpu_pmu0__PMUSERENR = 32'hFFFFFFFF; // ************************************************************ // Module debug_cpu_pmu1 cortexa9_pmu // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter debug_cpu_pmu1__PMXEVCNTR0 = 32'hF8893000; parameter val_debug_cpu_pmu1__PMXEVCNTR0 = 32'h00000000; parameter mask_debug_cpu_pmu1__PMXEVCNTR0 = 32'h00000000; parameter debug_cpu_pmu1__PMXEVCNTR1 = 32'hF8893004; parameter val_debug_cpu_pmu1__PMXEVCNTR1 = 32'h00000000; parameter mask_debug_cpu_pmu1__PMXEVCNTR1 = 32'h00000000; parameter debug_cpu_pmu1__PMXEVCNTR2 = 32'hF8893008; parameter val_debug_cpu_pmu1__PMXEVCNTR2 = 32'h00000000; parameter mask_debug_cpu_pmu1__PMXEVCNTR2 = 32'h00000000; parameter debug_cpu_pmu1__PMXEVCNTR3 = 32'hF889300C; parameter val_debug_cpu_pmu1__PMXEVCNTR3 = 32'h00000000; parameter mask_debug_cpu_pmu1__PMXEVCNTR3 = 32'h00000000; parameter debug_cpu_pmu1__PMXEVCNTR4 = 32'hF8893010; parameter val_debug_cpu_pmu1__PMXEVCNTR4 = 32'h00000000; parameter mask_debug_cpu_pmu1__PMXEVCNTR4 = 32'h00000000; parameter debug_cpu_pmu1__PMXEVCNTR5 = 32'hF8893014; parameter val_debug_cpu_pmu1__PMXEVCNTR5 = 32'h00000000; parameter mask_debug_cpu_pmu1__PMXEVCNTR5 = 32'h00000000; parameter debug_cpu_pmu1__PMCCNTR = 32'hF889307C; parameter val_debug_cpu_pmu1__PMCCNTR = 32'h00000000; parameter mask_debug_cpu_pmu1__PMCCNTR = 32'h00000000; parameter debug_cpu_pmu1__PMXEVTYPER0 = 32'hF8893400; parameter val_debug_cpu_pmu1__PMXEVTYPER0 = 32'h00000000; parameter mask_debug_cpu_pmu1__PMXEVTYPER0 = 32'h00000000; parameter debug_cpu_pmu1__PMXEVTYPER1 = 32'hF8893404; parameter val_debug_cpu_pmu1__PMXEVTYPER1 = 32'h00000000; parameter mask_debug_cpu_pmu1__PMXEVTYPER1 = 32'h00000000; parameter debug_cpu_pmu1__PMXEVTYPER2 = 32'hF8893408; parameter val_debug_cpu_pmu1__PMXEVTYPER2 = 32'h00000000; parameter mask_debug_cpu_pmu1__PMXEVTYPER2 = 32'h00000000; parameter debug_cpu_pmu1__PMXEVTYPER3 = 32'hF889340C; parameter val_debug_cpu_pmu1__PMXEVTYPER3 = 32'h00000000; parameter mask_debug_cpu_pmu1__PMXEVTYPER3 = 32'h00000000; parameter debug_cpu_pmu1__PMXEVTYPER4 = 32'hF8893410; parameter val_debug_cpu_pmu1__PMXEVTYPER4 = 32'h00000000; parameter mask_debug_cpu_pmu1__PMXEVTYPER4 = 32'h00000000; parameter debug_cpu_pmu1__PMXEVTYPER5 = 32'hF8893414; parameter val_debug_cpu_pmu1__PMXEVTYPER5 = 32'h00000000; parameter mask_debug_cpu_pmu1__PMXEVTYPER5 = 32'h00000000; parameter debug_cpu_pmu1__PMCNTENSET = 32'hF8893C00; parameter val_debug_cpu_pmu1__PMCNTENSET = 32'h00000000; parameter mask_debug_cpu_pmu1__PMCNTENSET = 32'hFFFFFFFF; parameter debug_cpu_pmu1__PMCNTENCLR = 32'hF8893C20; parameter val_debug_cpu_pmu1__PMCNTENCLR = 32'h00000000; parameter mask_debug_cpu_pmu1__PMCNTENCLR = 32'hFFFFFFFF; parameter debug_cpu_pmu1__PMINTENSET = 32'hF8893C40; parameter val_debug_cpu_pmu1__PMINTENSET = 32'h00000000; parameter mask_debug_cpu_pmu1__PMINTENSET = 32'hFFFFFFFF; parameter debug_cpu_pmu1__PMINTENCLR = 32'hF8893C60; parameter val_debug_cpu_pmu1__PMINTENCLR = 32'h00000000; parameter mask_debug_cpu_pmu1__PMINTENCLR = 32'hFFFFFFFF; parameter debug_cpu_pmu1__PMOVSR = 32'hF8893C80; parameter val_debug_cpu_pmu1__PMOVSR = 32'h00000000; parameter mask_debug_cpu_pmu1__PMOVSR = 32'h00000000; parameter debug_cpu_pmu1__PMSWINC = 32'hF8893CA0; parameter val_debug_cpu_pmu1__PMSWINC = 32'h00000000; parameter mask_debug_cpu_pmu1__PMSWINC = 32'h00000000; parameter debug_cpu_pmu1__PMCR = 32'hF8893E04; parameter val_debug_cpu_pmu1__PMCR = 32'h41093000; parameter mask_debug_cpu_pmu1__PMCR = 32'hFFFFFFFF; parameter debug_cpu_pmu1__PMUSERENR = 32'hF8893E08; parameter val_debug_cpu_pmu1__PMUSERENR = 32'h00000000; parameter mask_debug_cpu_pmu1__PMUSERENR = 32'hFFFFFFFF; // ************************************************************ // Module debug_cpu_ptm0 ptm // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter debug_cpu_ptm0__ETMCR = 32'hF889C000; parameter val_debug_cpu_ptm0__ETMCR = 32'h00000400; parameter mask_debug_cpu_ptm0__ETMCR = 32'h3FFFFFFF; parameter debug_cpu_ptm0__ETMCCR = 32'hF889C004; parameter val_debug_cpu_ptm0__ETMCCR = 32'h8D294004; parameter mask_debug_cpu_ptm0__ETMCCR = 32'hFFFFFFFF; parameter debug_cpu_ptm0__ETMTRIGGER = 32'hF889C008; parameter val_debug_cpu_ptm0__ETMTRIGGER = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMTRIGGER = 32'h0001FFFF; parameter debug_cpu_ptm0__ETMSR = 32'hF889C010; parameter val_debug_cpu_ptm0__ETMSR = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMSR = 32'h0000000F; parameter debug_cpu_ptm0__ETMSCR = 32'hF889C014; parameter val_debug_cpu_ptm0__ETMSCR = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMSCR = 32'h00007FFF; parameter debug_cpu_ptm0__ETMTSSCR = 32'hF889C018; parameter val_debug_cpu_ptm0__ETMTSSCR = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMTSSCR = 32'h00FFFFFF; parameter debug_cpu_ptm0__ETMTECR1 = 32'hF889C024; parameter val_debug_cpu_ptm0__ETMTECR1 = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMTECR1 = 32'h03FFFFFF; parameter debug_cpu_ptm0__ETMACVR1 = 32'hF889C040; parameter val_debug_cpu_ptm0__ETMACVR1 = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMACVR1 = 32'hFFFFFFFF; parameter debug_cpu_ptm0__ETMACVR2 = 32'hF889C044; parameter val_debug_cpu_ptm0__ETMACVR2 = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMACVR2 = 32'hFFFFFFFF; parameter debug_cpu_ptm0__ETMACVR3 = 32'hF889C048; parameter val_debug_cpu_ptm0__ETMACVR3 = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMACVR3 = 32'hFFFFFFFF; parameter debug_cpu_ptm0__ETMACVR4 = 32'hF889C04C; parameter val_debug_cpu_ptm0__ETMACVR4 = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMACVR4 = 32'hFFFFFFFF; parameter debug_cpu_ptm0__ETMACVR5 = 32'hF889C050; parameter val_debug_cpu_ptm0__ETMACVR5 = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMACVR5 = 32'hFFFFFFFF; parameter debug_cpu_ptm0__ETMACVR6 = 32'hF889C054; parameter val_debug_cpu_ptm0__ETMACVR6 = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMACVR6 = 32'hFFFFFFFF; parameter debug_cpu_ptm0__ETMACVR7 = 32'hF889C058; parameter val_debug_cpu_ptm0__ETMACVR7 = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMACVR7 = 32'hFFFFFFFF; parameter debug_cpu_ptm0__ETMACVR8 = 32'hF889C05C; parameter val_debug_cpu_ptm0__ETMACVR8 = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMACVR8 = 32'hFFFFFFFF; parameter debug_cpu_ptm0__ETMACTR1 = 32'hF889C080; parameter val_debug_cpu_ptm0__ETMACTR1 = 32'h00000001; parameter mask_debug_cpu_ptm0__ETMACTR1 = 32'h00000FFF; parameter debug_cpu_ptm0__ETMACTR2 = 32'hF889C084; parameter val_debug_cpu_ptm0__ETMACTR2 = 32'h00000001; parameter mask_debug_cpu_ptm0__ETMACTR2 = 32'h00000FFF; parameter debug_cpu_ptm0__ETMACTR3 = 32'hF889C088; parameter val_debug_cpu_ptm0__ETMACTR3 = 32'h00000001; parameter mask_debug_cpu_ptm0__ETMACTR3 = 32'h00000FFF; parameter debug_cpu_ptm0__ETMACTR4 = 32'hF889C08C; parameter val_debug_cpu_ptm0__ETMACTR4 = 32'h00000001; parameter mask_debug_cpu_ptm0__ETMACTR4 = 32'h00000FFF; parameter debug_cpu_ptm0__ETMACTR5 = 32'hF889C090; parameter val_debug_cpu_ptm0__ETMACTR5 = 32'h00000001; parameter mask_debug_cpu_ptm0__ETMACTR5 = 32'h00000FFF; parameter debug_cpu_ptm0__ETMACTR6 = 32'hF889C094; parameter val_debug_cpu_ptm0__ETMACTR6 = 32'h00000001; parameter mask_debug_cpu_ptm0__ETMACTR6 = 32'h00000FFF; parameter debug_cpu_ptm0__ETMACTR7 = 32'hF889C098; parameter val_debug_cpu_ptm0__ETMACTR7 = 32'h00000001; parameter mask_debug_cpu_ptm0__ETMACTR7 = 32'h00000FFF; parameter debug_cpu_ptm0__ETMACTR8 = 32'hF889C09C; parameter val_debug_cpu_ptm0__ETMACTR8 = 32'h00000001; parameter mask_debug_cpu_ptm0__ETMACTR8 = 32'h00000FFF; parameter debug_cpu_ptm0__ETMCNTRLDVR1 = 32'hF889C140; parameter val_debug_cpu_ptm0__ETMCNTRLDVR1 = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMCNTRLDVR1 = 32'h0000FFFF; parameter debug_cpu_ptm0__ETMCNTRLDVR2 = 32'hF889C144; parameter val_debug_cpu_ptm0__ETMCNTRLDVR2 = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMCNTRLDVR2 = 32'h0000FFFF; parameter debug_cpu_ptm0__ETMCNTENR1 = 32'hF889C150; parameter val_debug_cpu_ptm0__ETMCNTENR1 = 32'h00020000; parameter mask_debug_cpu_ptm0__ETMCNTENR1 = 32'h0003FFFF; parameter debug_cpu_ptm0__ETMCNTENR2 = 32'hF889C154; parameter val_debug_cpu_ptm0__ETMCNTENR2 = 32'h00020000; parameter mask_debug_cpu_ptm0__ETMCNTENR2 = 32'h0003FFFF; parameter debug_cpu_ptm0__ETMCNTRLDEVR1 = 32'hF889C160; parameter val_debug_cpu_ptm0__ETMCNTRLDEVR1 = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMCNTRLDEVR1 = 32'h0001FFFF; parameter debug_cpu_ptm0__ETMCNTRLDEVR2 = 32'hF889C164; parameter val_debug_cpu_ptm0__ETMCNTRLDEVR2 = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMCNTRLDEVR2 = 32'h0001FFFF; parameter debug_cpu_ptm0__ETMCNTVR1 = 32'hF889C170; parameter val_debug_cpu_ptm0__ETMCNTVR1 = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMCNTVR1 = 32'h0000FFFF; parameter debug_cpu_ptm0__ETMCNTVR2 = 32'hF889C174; parameter val_debug_cpu_ptm0__ETMCNTVR2 = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMCNTVR2 = 32'h0000FFFF; parameter debug_cpu_ptm0__ETMSQ12EVR = 32'hF889C180; parameter val_debug_cpu_ptm0__ETMSQ12EVR = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMSQ12EVR = 32'h0001FFFF; parameter debug_cpu_ptm0__ETMSQ21EVR = 32'hF889C184; parameter val_debug_cpu_ptm0__ETMSQ21EVR = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMSQ21EVR = 32'h0001FFFF; parameter debug_cpu_ptm0__ETMSQ23EVR = 32'hF889C188; parameter val_debug_cpu_ptm0__ETMSQ23EVR = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMSQ23EVR = 32'h0001FFFF; parameter debug_cpu_ptm0__ETMSQ31EVR = 32'hF889C18C; parameter val_debug_cpu_ptm0__ETMSQ31EVR = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMSQ31EVR = 32'h0001FFFF; parameter debug_cpu_ptm0__ETMSQ32EVR = 32'hF889C190; parameter val_debug_cpu_ptm0__ETMSQ32EVR = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMSQ32EVR = 32'h0001FFFF; parameter debug_cpu_ptm0__ETMSQ13EVR = 32'hF889C194; parameter val_debug_cpu_ptm0__ETMSQ13EVR = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMSQ13EVR = 32'h0001FFFF; parameter debug_cpu_ptm0__ETMSQR = 32'hF889C19C; parameter val_debug_cpu_ptm0__ETMSQR = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMSQR = 32'h00000003; parameter debug_cpu_ptm0__ETMEXTOUTEVR1 = 32'hF889C1A0; parameter val_debug_cpu_ptm0__ETMEXTOUTEVR1 = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMEXTOUTEVR1 = 32'h0001FFFF; parameter debug_cpu_ptm0__ETMEXTOUTEVR2 = 32'hF889C1A4; parameter val_debug_cpu_ptm0__ETMEXTOUTEVR2 = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMEXTOUTEVR2 = 32'h0001FFFF; parameter debug_cpu_ptm0__ETMCIDCVR1 = 32'hF889C1B0; parameter val_debug_cpu_ptm0__ETMCIDCVR1 = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMCIDCVR1 = 32'hF"b"FFFFFFF; parameter debug_cpu_ptm0__ETMCIDCMR = 32'hF889C1BC; parameter val_debug_cpu_ptm0__ETMCIDCMR = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMCIDCMR = 32'hFFFFFFFF; parameter debug_cpu_ptm0__ETMSYNCFR = 32'hF889C1E0; parameter val_debug_cpu_ptm0__ETMSYNCFR = 32'h00000400; parameter mask_debug_cpu_ptm0__ETMSYNCFR = 32'h00000FFF; parameter debug_cpu_ptm0__ETMIDR = 32'hF889C1E4; parameter val_debug_cpu_ptm0__ETMIDR = 32'h411CF300; parameter mask_debug_cpu_ptm0__ETMIDR = 32'hFFFFFFFF; parameter debug_cpu_ptm0__ETMCCER = 32'hF889C1E8; parameter val_debug_cpu_ptm0__ETMCCER = 32'h00C019A2; parameter mask_debug_cpu_ptm0__ETMCCER = 32'h03FFFFFF; parameter debug_cpu_ptm0__ETMEXTINSELR = 32'hF889C1EC; parameter val_debug_cpu_ptm0__ETMEXTINSELR = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMEXTINSELR = 32'h00003FFF; parameter debug_cpu_ptm0__ETMAUXCR = 32'hF889C1FC; parameter val_debug_cpu_ptm0__ETMAUXCR = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMAUXCR = 32'h0000000F; parameter debug_cpu_ptm0__ETMTRACEIDR = 32'hF889C200; parameter val_debug_cpu_ptm0__ETMTRACEIDR = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMTRACEIDR = 32'h0000007F; parameter debug_cpu_ptm0__OSLSR = 32'hF889C304; parameter val_debug_cpu_ptm0__OSLSR = 32'h00000000; parameter mask_debug_cpu_ptm0__OSLSR = 32'hFFFFFFFF; parameter debug_cpu_ptm0__ETMPDSR = 32'hF889C314; parameter val_debug_cpu_ptm0__ETMPDSR = 32'h00000001; parameter mask_debug_cpu_ptm0__ETMPDSR = 32'hFFFFFFFF; parameter debug_cpu_ptm0__ITMISCOUT = 32'hF889CEDC; parameter val_debug_cpu_ptm0__ITMISCOUT = 32'h00000000; parameter mask_debug_cpu_ptm0__ITMISCOUT = 32'h000003FF; parameter debug_cpu_ptm0__ITMISCIN = 32'hF889CEE0; parameter val_debug_cpu_ptm0__ITMISCIN = 32'h00000000; parameter mask_debug_cpu_ptm0__ITMISCIN = 32'h00000020; parameter debug_cpu_ptm0__ITTRIGGER = 32'hF889CEE8; parameter val_debug_cpu_ptm0__ITTRIGGER = 32'h00000000; parameter mask_debug_cpu_ptm0__ITTRIGGER = 32'h00000001; parameter debug_cpu_ptm0__ITATBDATA0 = 32'hF889CEEC; parameter val_debug_cpu_ptm0__ITATBDATA0 = 32'h00000000; parameter mask_debug_cpu_ptm0__ITATBDATA0 = 32'h0000001F; parameter debug_cpu_ptm0__ITATBCTR2 = 32'hF889CEF0; parameter val_debug_cpu_ptm0__ITATBCTR2 = 32'h00000000; parameter mask_debug_cpu_ptm0__ITATBCTR2 = 32'h00000000; parameter debug_cpu_ptm0__ITATBID = 32'hF889CEF4; parameter val_debug_cpu_ptm0__ITATBID = 32'h00000000; parameter mask_debug_cpu_ptm0__ITATBID = 32'h0000007F; parameter debug_cpu_ptm0__ITATBCTR0 = 32'hF889CEF8; parameter val_debug_cpu_ptm0__ITATBCTR0 = 32'h00000000; parameter mask_debug_cpu_ptm0__ITATBCTR0 = 32'h000003FF; parameter debug_cpu_ptm0__ETMITCTRL = 32'hF889CF00; parameter val_debug_cpu_ptm0__ETMITCTRL = 32'h00000000; parameter mask_debug_cpu_ptm0__ETMITCTRL = 32'h00000001; parameter debug_cpu_ptm0__CTSR = 32'hF889CFA0; parameter val_debug_cpu_ptm0__CTSR = 32'h000000FF; parameter mask_debug_cpu_ptm0__CTSR = 32'h000000FF; parameter debug_cpu_ptm0__CTCR = 32'hF889CFA4; parameter val_debug_cpu_ptm0__CTCR = 32'h00000000; parameter mask_debug_cpu_ptm0__CTCR = 32'h000000FF; parameter debug_cpu_ptm0__LAR = 32'hF889CFB0; parameter val_debug_cpu_ptm0__LAR = 32'h00000000; parameter mask_debug_cpu_ptm0__LAR = 32'hFFFFFFFF; parameter debug_cpu_ptm0__LSR = 32'hF889CFB4; parameter val_debug_cpu_ptm0__LSR = 32'h00000003; parameter mask_debug_cpu_ptm0__LSR = 32'h00000007; parameter debug_cpu_ptm0__ASR = 32'hF889CFB8; parameter val_debug_cpu_ptm0__ASR = 32'h00000000; parameter mask_debug_cpu_ptm0__ASR = 32'h000000F3; parameter debug_cpu_ptm0__DEVID = 32'hF889CFC8; parameter val_debug_cpu_ptm0__DEVID = 32'h00000000; parameter mask_debug_cpu_ptm0__DEVID = 32'hFFFFFFFF; parameter debug_cpu_ptm0__DTIR = 32'hF889CFCC; parameter val_debug_cpu_ptm0__DTIR = 32'h00000013; parameter mask_debug_cpu_ptm0__DTIR = 32'h000000FF; parameter debug_cpu_ptm0__PERIPHID4 = 32'hF889CFD0; parameter val_debug_cpu_ptm0__PERIPHID4 = 32'h00000004; parameter mask_debug_cpu_ptm0__PERIPHID4 = 32'h000000FF; parameter debug_cpu_ptm0__PERIPHID5 = 32'hF889CFD4; parameter val_debug_cpu_ptm0__PERIPHID5 = 32'h00000000; parameter mask_debug_cpu_ptm0__PERIPHID5 = 32'h000000FF; parameter debug_cpu_ptm0__PERIPHID6 = 32'hF889CFD8; parameter val_debug_cpu_ptm0__PERIPHID6 = 32'h00000000; parameter mask_debug_cpu_ptm0__PERIPHID6 = 32'h000000FF; parameter debug_cpu_ptm0__PERIPHID7 = 32'hF889CFDC; parameter val_debug_cpu_ptm0__PERIPHID7 = 32'h00000000; parameter mask_debug_cpu_ptm0__PERIPHID7 = 32'h000000FF; parameter debug_cpu_ptm0__PERIPHID0 = 32'hF889CFE0; parameter val_debug_cpu_ptm0__PERIPHID0 = 32'h00000050; parameter mask_debug_cpu_ptm0__PERIPHID0 = 32'h000000FF; parameter debug_cpu_ptm0__PERIPHID1 = 32'hF889CFE4; parameter val_debug_cpu_ptm0__PERIPHID1 = 32'h000000B9; parameter mask_debug_cpu_ptm0__PERIPHID1 = 32'h000000FF; parameter debug_cpu_ptm0__PERIPHID2 = 32'hF889CFE8; parameter val_debug_cpu_ptm0__PERIPHID2 = 32'h0000001B; parameter mask_debug_cpu_ptm0__PERIPHID2 = 32'h000000FF; parameter debug_cpu_ptm0__PERIPHID3 = 32'hF889CFEC; parameter val_debug_cpu_ptm0__PERIPHID3 = 32'h00000000; parameter mask_debug_cpu_ptm0__PERIPHID3 = 32'h000000FF; parameter debug_cpu_ptm0__COMPID0 = 32'hF889CFF0; parameter val_debug_cpu_ptm0__COMPID0 = 32'h0000000D; parameter mask_debug_cpu_ptm0__COMPID0 = 32'h000000FF; parameter debug_cpu_ptm0__COMPID1 = 32'hF889CFF4; parameter val_debug_cpu_ptm0__COMPID1 = 32'h00000090; parameter mask_debug_cpu_ptm0__COMPID1 = 32'h000000FF; parameter debug_cpu_ptm0__COMPID2 = 32'hF889CFF8; parameter val_debug_cpu_ptm0__COMPID2 = 32'h00000005; parameter mask_debug_cpu_ptm0__COMPID2 = 32'h000000FF; parameter debug_cpu_ptm0__COMPID3 = 32'hF889CFFC; parameter val_debug_cpu_ptm0__COMPID3 = 32'h000000B1; parameter mask_debug_cpu_ptm0__COMPID3 = 32'h000000FF; // ************************************************************ // Module debug_cpu_ptm1 ptm // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter debug_cpu_ptm1__ETMCR = 32'hF889D000; parameter val_debug_cpu_ptm1__ETMCR = 32'h00000400; parameter mask_debug_cpu_ptm1__ETMCR = 32'h3FFFFFFF; parameter debug_cpu_ptm1__ETMCCR = 32'hF889D004; parameter val_debug_cpu_ptm1__ETMCCR = 32'h8D294004; parameter mask_debug_cpu_ptm1__ETMCCR = 32'hFFFFFFFF; parameter debug_cpu_ptm1__ETMTRIGGER = 32'hF889D008; parameter val_debug_cpu_ptm1__ETMTRIGGER = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMTRIGGER = 32'h0001FFFF; parameter debug_cpu_ptm1__ETMSR = 32'hF889D010; parameter val_debug_cpu_ptm1__ETMSR = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMSR = 32'h0000000F; parameter debug_cpu_ptm1__ETMSCR = 32'hF889D014; parameter val_debug_cpu_ptm1__ETMSCR = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMSCR = 32'h00007FFF; parameter debug_cpu_ptm1__ETMTSSCR = 32'hF889D018; parameter val_debug_cpu_ptm1__ETMTSSCR = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMTSSCR = 32'h00FFFFFF; parameter debug_cpu_ptm1__ETMTECR1 = 32'hF889D024; parameter val_debug_cpu_ptm1__ETMTECR1 = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMTECR1 = 32'h03FFFFFF; parameter debug_cpu_ptm1__ETMACVR1 = 32'hF889D040; parameter val_debug_cpu_ptm1__ETMACVR1 = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMACVR1 = 32'hFFFFFFFF; parameter debug_cpu_ptm1__ETMACVR2 = 32'hF889D044; parameter val_debug_cpu_ptm1__ETMACVR2 = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMACVR2 = 32'hFFFFFFFF; parameter debug_cpu_ptm1__ETMACVR3 = 32'hF889D048; parameter val_debug_cpu_ptm1__ETMACVR3 = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMACVR3 = 32'hFFFFFFFF; parameter debug_cpu_ptm1__ETMACVR4 = 32'hF889D04C; parameter val_debug_cpu_ptm1__ETMACVR4 = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMACVR4 = 32'hFFFFFFFF; parameter debug_cpu_ptm1__ETMACVR5 = 32'hF889D050; parameter val_debug_cpu_ptm1__ETMACVR5 = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMACVR5 = 32'hFFFFFFFF; parameter debug_cpu_ptm1__ETMACVR6 = 32'hF889D054; parameter val_debug_cpu_ptm1__ETMACVR6 = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMACVR6 = 32'hFFFFFFFF; parameter debug_cpu_ptm1__ETMACVR7 = 32'hF889D058; parameter val_debug_cpu_ptm1__ETMACVR7 = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMACVR7 = 32'hFFFFFFFF; parameter debug_cpu_ptm1__ETMACVR8 = 32'hF889D05C; parameter val_debug_cpu_ptm1__ETMACVR8 = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMACVR8 = 32'hFFFFFFFF; parameter debug_cpu_ptm1__ETMACTR1 = 32'hF889D080; parameter val_debug_cpu_ptm1__ETMACTR1 = 32'h00000001; parameter mask_debug_cpu_ptm1__ETMACTR1 = 32'h00000FFF; parameter debug_cpu_ptm1__ETMACTR2 = 32'hF889D084; parameter val_debug_cpu_ptm1__ETMACTR2 = 32'h00000001; parameter mask_debug_cpu_ptm1__ETMACTR2 = 32'h00000FFF; parameter debug_cpu_ptm1__ETMACTR3 = 32'hF889D088; parameter val_debug_cpu_ptm1__ETMACTR3 = 32'h00000001; parameter mask_debug_cpu_ptm1__ETMACTR3 = 32'h00000FFF; parameter debug_cpu_ptm1__ETMACTR4 = 32'hF889D08C; parameter val_debug_cpu_ptm1__ETMACTR4 = 32'h00000001; parameter mask_debug_cpu_ptm1__ETMACTR4 = 32'h00000FFF; parameter debug_cpu_ptm1__ETMACTR5 = 32'hF889D090; parameter val_debug_cpu_ptm1__ETMACTR5 = 32'h00000001; parameter mask_debug_cpu_ptm1__ETMACTR5 = 32'h00000FFF; parameter debug_cpu_ptm1__ETMACTR6 = 32'hF889D094; parameter val_debug_cpu_ptm1__ETMACTR6 = 32'h00000001; parameter mask_debug_cpu_ptm1__ETMACTR6 = 32'h00000FFF; parameter debug_cpu_ptm1__ETMACTR7 = 32'hF889D098; parameter val_debug_cpu_ptm1__ETMACTR7 = 32'h00000001; parameter mask_debug_cpu_ptm1__ETMACTR7 = 32'h00000FFF; parameter debug_cpu_ptm1__ETMACTR8 = 32'hF889D09C; parameter val_debug_cpu_ptm1__ETMACTR8 = 32'h00000001; parameter mask_debug_cpu_ptm1__ETMACTR8 = 32'h00000FFF; parameter debug_cpu_ptm1__ETMCNTRLDVR1 = 32'hF889D140; parameter val_debug_cpu_ptm1__ETMCNTRLDVR1 = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMCNTRLDVR1 = 32'h0000FFFF; parameter debug_cpu_ptm1__ETMCNTRLDVR2 = 32'hF889D144; parameter val_debug_cpu_ptm1__ETMCNTRLDVR2 = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMCNTRLDVR2 = 32'h0000FFFF; parameter debug_cpu_ptm1__ETMCNTENR1 = 32'hF889D150; parameter val_debug_cpu_ptm1__ETMCNTENR1 = 32'h00020000; parameter mask_debug_cpu_ptm1__ETMCNTENR1 = 32'h0003FFFF; parameter debug_cpu_ptm1__ETMCNTENR2 = 32'hF889D154; parameter val_debug_cpu_ptm1__ETMCNTENR2 = 32'h00020000; parameter mask_debug_cpu_ptm1__ETMCNTENR2 = 32'h0003FFFF; parameter debug_cpu_ptm1__ETMCNTRLDEVR1 = 32'hF889D160; parameter val_debug_cpu_ptm1__ETMCNTRLDEVR1 = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMCNTRLDEVR1 = 32'h0001FFFF; parameter debug_cpu_ptm1__ETMCNTRLDEVR2 = 32'hF889D164; parameter val_debug_cpu_ptm1__ETMCNTRLDEVR2 = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMCNTRLDEVR2 = 32'h0001FFFF; parameter debug_cpu_ptm1__ETMCNTVR1 = 32'hF889D170; parameter val_debug_cpu_ptm1__ETMCNTVR1 = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMCNTVR1 = 32'h0000FFFF; parameter debug_cpu_ptm1__ETMCNTVR2 = 32'hF889D174; parameter val_debug_cpu_ptm1__ETMCNTVR2 = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMCNTVR2 = 32'h0000FFFF; parameter debug_cpu_ptm1__ETMSQ12EVR = 32'hF889D180; parameter val_debug_cpu_ptm1__ETMSQ12EVR = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMSQ12EVR = 32'h0001FFFF; parameter debug_cpu_ptm1__ETMSQ21EVR = 32'hF889D184; parameter val_debug_cpu_ptm1__ETMSQ21EVR = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMSQ21EVR = 32'h0001FFFF; parameter debug_cpu_ptm1__ETMSQ23EVR = 32'hF889D188; parameter val_debug_cpu_ptm1__ETMSQ23EVR = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMSQ23EVR = 32'h0001FFFF; parameter debug_cpu_ptm1__ETMSQ31EVR = 32'hF889D18C; parameter val_debug_cpu_ptm1__ETMSQ31EVR = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMSQ31EVR = 32'h0001FFFF; parameter debug_cpu_ptm1__ETMSQ32EVR = 32'hF889D190; parameter val_debug_cpu_ptm1__ETMSQ32EVR = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMSQ32EVR = 32'h0001FFFF; parameter debug_cpu_ptm1__ETMSQ13EVR = 32'hF889D194; parameter val_debug_cpu_ptm1__ETMSQ13EVR = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMSQ13EVR = 32'h0001FFFF; parameter debug_cpu_ptm1__ETMSQR = 32'hF889D19C; parameter val_debug_cpu_ptm1__ETMSQR = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMSQR = 32'h00000003; parameter debug_cpu_ptm1__ETMEXTOUTEVR1 = 32'hF889D1A0; parameter val_debug_cpu_ptm1__ETMEXTOUTEVR1 = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMEXTOUTEVR1 = 32'h0001FFFF; parameter debug_cpu_ptm1__ETMEXTOUTEVR2 = 32'hF889D1A4; parameter val_debug_cpu_ptm1__ETMEXTOUTEVR2 = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMEXTOUTEVR2 = 32'h0001FFFF; parameter debug_cpu_ptm1__ETMCIDCVR1 = 32'hF889D1B0; parameter val_debug_cpu_ptm1__ETMCIDCVR1 = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMCIDCVR1 = 32'hFFFFFFFF; parameter debug_cpu_ptm1__ETMCIDCMR = 32'hF889D1BC; parameter val_debug_cpu_ptm1__ETMCIDCMR = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMCIDCMR = 32'hFFFFFFFF; parameter debug_cpu_ptm1__ETMSYNCFR = 32'hF889D1E0; parameter val_debug_cpu_ptm1__ETMSYNCFR = 32'h00000400; parameter mask_debug_cpu_ptm1__ETMSYNCFR = 32'h00000FFF; parameter debug_cpu_ptm1__ETMIDR = 32'hF889D1E4; parameter val_debug_cpu_ptm1__ETMIDR = 32'h411CF300; parameter mask_debug_cpu_ptm1__ETMIDR = 32'hFFFFFFFF; parameter debug_cpu_ptm1__ETMCCER = 32'hF889D1E8; parameter val_debug_cpu_ptm1__ETMCCER = 32'h00C019A2; parameter mask_debug_cpu_ptm1__ETMCCER = 32'h03FFFFFF; parameter debug_cpu_ptm1__ETMEXTINSELR = 32'hF889D1EC; parameter val_debug_cpu_ptm1__ETMEXTINSELR = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMEXTINSELR = 32'h00003FFF; parameter debug_cpu_ptm1__ETMAUXCR = 32'hF889D1FC; parameter val_debug_cpu_ptm1__ETMAUXCR = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMAUXCR = 32'h0000000F; parameter debug_cpu_ptm1__ETMTRACEIDR = 32'hF889D200; parameter val_debug_cpu_ptm1__ETMTRACEIDR = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMTRACEIDR = 32'h0000007F; parameter debug_cpu_ptm1__OSLSR = 32'hF889D304; parameter val_debug_cpu_ptm1__OSLSR = 32'h00000000; parameter mask_debug_cpu_ptm1__OSLSR = 32'hFFFFFFFF; parameter debug_cpu_ptm1__ETMPDSR = 32'hF889D314; parameter val_debug_cpu_ptm1__ETMPDSR = 32'h00000001; parameter mask_debug_cpu_ptm1__ETMPDSR = 32'hFFFFFFFF; parameter debug_cpu_ptm1__ITMISCOUT = 32'hF889DEDC; parameter val_debug_cpu_ptm1__ITMISCOUT = 32'h00000000; parameter mask_debug_cpu_ptm1__ITMISCOUT = 32'h000003FF; parameter debug_cpu_ptm1__ITMISCIN = 32'hF889DEE0; parameter val_debug_cpu_ptm1__ITMISCIN = 32'h00000000; parameter mask_debug_cpu_ptm1__ITMISCIN = 32'h00000020; parameter debug_cpu_ptm1__ITTRIGGER = 32'hF889DEE8; parameter val_debug_cpu_ptm1__ITTRIGGER = 32'h00000000; parameter mask_debug_cpu_ptm1__ITTRIGGER = 32'h00000001; parameter debug_cpu_ptm1__ITATBDATA0 = 32'hF889DEEC; parameter val_debug_cpu_ptm1__ITATBDATA0 = 32'h00000000; parameter mask_debug_cpu_ptm1__ITATBDATA0 = 32'h0000001F; parameter debug_cpu_ptm1__ITATBCTR2 = 32'hF889DEF0; parameter val_debug_cpu_ptm1__ITATBCTR2 = 32'h00000000; parameter mask_debug_cpu_ptm1__ITATBCTR2 = 32'h00000000; parameter debug_cpu_ptm1__ITATBID = 32'hF889DEF4; parameter val_debug_cpu_ptm1__ITATBID = 32'h00000000; parameter mask_debug_cpu_ptm1__ITATBID = 32'h0000007F; parameter debug_cpu_ptm1__ITATBCTR0 = 32'hF889DEF8; parameter val_debug_cpu_ptm1__ITATBCTR0 = 32'h00000000; parameter mask_debug_cpu_ptm1__ITATBCTR0 = 32'h000003FF; parameter debug_cpu_ptm1__ETMITCTRL = 32'hF889DF00; parameter val_debug_cpu_ptm1__ETMITCTRL = 32'h00000000; parameter mask_debug_cpu_ptm1__ETMITCTRL = 32'h00000001; parameter debug_cpu_ptm1__CTSR = 32'hF889DFA0; parameter val_debug_cpu_ptm1__CTSR = 32'h000000FF; parameter mask_debug_cpu_ptm1__CTSR = 32'h000000FF; parameter debug_cpu_ptm1__CTCR = 32'hF889DFA4; parameter val_debug_cpu_ptm1__CTCR = 32'h00000000; parameter mask_debug_cpu_ptm1__CTCR = 32'h000000FF; parameter debug_cpu_ptm1__LAR = 32'hF889DFB0; parameter val_debug_cpu_ptm1__LAR = 32'h00000000; parameter mask_debug_cpu_ptm1__LAR = 32'hFFFFFFFF; parameter debug_cpu_ptm1__LSR = 32'hF889DFB4; parameter val_debug_cpu_ptm1__LSR = 32'h00000003; parameter mask_debug_cpu_ptm1__LSR = 32'h00000007; parameter debug_cpu_ptm1__ASR = 32'hF889DFB8; parameter val_debug_cpu_ptm1__ASR = 32'h00000000; parameter mask_debug_cpu_ptm1__ASR = 32'h000000F3; parameter debug_cpu_ptm1__DEVID = 32'hF889DFC8; parameter val_debug_cpu_ptm1__DEVID = 32'h00000000; parameter mask_debug_cpu_ptm1__DEVID = 32'hFFFFFFFF; parameter debug_cpu_ptm1__DTIR = 32'hF889DFCC; parameter val_debug_cpu_ptm1__DTIR = 32'h00000013; parameter mask_debug_cpu_ptm1__DTIR = 32'h000000FF; parameter debug_cpu_ptm1__PERIPHID4 = 32'hF889DFD0; parameter val_debug_cpu_ptm1__PERIPHID4 = 32'h00000004; parameter mask_debug_cpu_ptm1__PERIPHID4 = 32'h000000FF; parameter debug_cpu_ptm1__PERIPHID5 = 32'hF889DFD4; parameter val_debug_cpu_ptm1__PERIPHID5 = 32'h00000000; parameter mask_debug_cpu_ptm1__PERIPHID5 = 32'h000000FF; parameter debug_cpu_ptm1__PERIPHID6 = 32'hF889DFD8; parameter val_debug_cpu_ptm1__PERIPHID6 = 32'h00000000; parameter mask_debug_cpu_ptm1__PERIPHID6 = 32'h000000FF; parameter debug_cpu_ptm1__PERIPHID7 = 32'hF889DFDC; parameter val_debug_cpu_ptm1__PERIPHID7 = 32'h00000000; parameter mask_debug_cpu_ptm1__PERIPHID7 = 32'h000000FF; parameter debug_cpu_ptm1__PERIPHID0 = 32'hF889DFE0; parameter val_debug_cpu_ptm1__PERIPHID0 = 32'h00000050; parameter mask_debug_cpu_ptm1__PERIPHID0 = 32'h000000FF; parameter debug_cpu_ptm1__PERIPHID1 = 32'hF889DFE4; parameter val_debug_cpu_ptm1__PERIPHID1 = 32'h000000B9; parameter mask_debug_cpu_ptm1__PERIPHID1 = 32'h000000FF; parameter debug_cpu_ptm1__PERIPHID2 = 32'hF889DFE8; parameter val_debug_cpu_ptm1__PERIPHID2 = 32'h0000001B; parameter mask_debug_cpu_ptm1__PERIPHID2 = 32'h000000FF; parameter debug_cpu_ptm1__PERIPHID3 = 32'hF889DFEC; parameter val_debug_cpu_ptm1__PERIPHID3 = 32'h00000000; parameter mask_debug_cpu_ptm1__PERIPHID3 = 32'h000000FF; parameter debug_cpu_ptm1__COMPID0 = 32'hF889DFF0; parameter val_debug_cpu_ptm1__COMPID0 = 32'h0000000D; parameter mask_debug_cpu_ptm1__COMPID0 = 32'h000000FF; parameter debug_cpu_ptm1__COMPID1 = 32'hF889DFF4; parameter val_debug_cpu_ptm1__COMPID1 = 32'h00000090; parameter mask_debug_cpu_ptm1__COMPID1 = 32'h000000FF; parameter debug_cpu_ptm1__COMPID2 = 32'hF889DFF8; parameter val_debug_cpu_ptm1__COMPID2 = 32'h00000005; parameter mask_debug_cpu_ptm1__COMPID2 = 32'h000000FF; parameter debug_cpu_ptm1__COMPID3 = 32'hF889DFFC; parameter val_debug_cpu_ptm1__COMPID3 = 32'h000000B1; parameter mask_debug_cpu_ptm1__COMPID3 = 32'h000000FF; // ************************************************************ // Module debug_cti_axim cti // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter debug_cti_axim__CTICONTROL = 32'hF880A000; parameter val_debug_cti_axim__CTICONTROL = 32'h00000000; parameter mask_debug_cti_axim__CTICONTROL = 32'h00000001; parameter debug_cti_axim__CTIINTACK = 32'hF880A010; parameter val_debug_cti_axim__CTIINTACK = 32'h00000000; parameter mask_debug_cti_axim__CTIINTACK = 32'h000000FF; parameter debug_cti_axim__CTIAPPSET = 32'hF880A014; parameter val_debug_cti_axim__CTIAPPSET = 32'h00000000; parameter mask_debug_cti_axim__CTIAPPSET = 32'h0000000F; parameter debug_cti_axim__CTIAPPCLEAR = 32'hF880A018; parameter val_debug_cti_axim__CTIAPPCLEAR = 32'h00000000; parameter mask_debug_cti_axim__CTIAPPCLEAR = 32'h0000000F; parameter debug_cti_axim__CTIAPPPULSE = 32'hF880A01C; parameter val_debug_cti_axim__CTIAPPPULSE = 32'h00000000; parameter mask_debug_cti_axim__CTIAPPPULSE = 32'h0000000F; parameter debug_cti_axim__CTIINEN0 = 32'hF880A020; parameter val_debug_cti_axim__CTIINEN0 = 32'h00000000; parameter mask_debug_cti_axim__CTIINEN0 = 32'h0000000F; parameter debug_cti_axim__CTIINEN1 = 32'hF880A024; parameter val_debug_cti_axim__CTIINEN1 = 32'h00000000; parameter mask_debug_cti_axim__CTIINEN1 = 32'h0000000F; parameter debug_cti_axim__CTIINEN2 = 32'hF880A028; parameter val_debug_cti_axim__CTIINEN2 = 32'h00000000; parameter mask_debug_cti_axim__CTIINEN2 = 32'h0000000F; parameter debug_cti_axim__CTIINEN3 = 32'hF880A02C; parameter val_debug_cti_axim__CTIINEN3 = 32'h00000000; parameter mask_debug_cti_axim__CTIINEN3 = 32'h0000000F; parameter debug_cti_axim__CTIINEN4 = 32'hF880A030; parameter val_debug_cti_axim__CTIINEN4 = 32'h00000000; parameter mask_debug_cti_axim__CTIINEN4 = 32'h0000000F; parameter debug_cti_axim__CTIINEN5 = 32'hF880A034; parameter val_debug_cti_axim__CTIINEN5 = 32'h00000000; parameter mask_debug_cti_axim__CTIINEN5 = 32'h0000000F; parameter debug_cti_axim__CTIINEN6 = 32'hF880A038; parameter val_debug_cti_axim__CTIINEN6 = 32'h00000000; parameter mask_debug_cti_axim__CTIINEN6 = 32'h0000000F; parameter debug_cti_axim__CTIINEN7 = 32'hF880A03C; parameter val_debug_cti_axim__CTIINEN7 = 32'h00000000; parameter mask_debug_cti_axim__CTIINEN7 = 32'h0000000F; parameter debug_cti_axim__CTIOUTEN0 = 32'hF880A0A0; parameter val_debug_cti_axim__CTIOUTEN0 = 32'h00000000; parameter mask_debug_cti_axim__CTIOUTEN0 = 32'h0000000F; parameter debug_cti_axim__CTIOUTEN1 = 32'hF880A0A4; parameter val_debug_cti_axim__CTIOUTEN1 = 32'h00000000; parameter mask_debug_cti_axim__CTIOUTEN1 = 32'h0000000F; parameter debug_cti_axim__CTIOUTEN2 = 32'hF880A0A8; parameter val_debug_cti_axim__CTIOUTEN2 = 32'h00000000; parameter mask_debug_cti_axim__CTIOUTEN2 = 32'h0000000F; parameter debug_cti_axim__CTIOUTEN3 = 32'hF880A0AC; parameter val_debug_cti_axim__CTIOUTEN3 = 32'h00000000; parameter mask_debug_cti_axim__CTIOUTEN3 = 32'h0000000F; parameter debug_cti_axim__CTIOUTEN4 = 32'hF880A0B0; parameter val_debug_cti_axim__CTIOUTEN4 = 32'h00000000; parameter mask_debug_cti_axim__CTIOUTEN4 = 32'h0000000F; parameter debug_cti_axim__CTIOUTEN5 = 32'hF880A0B4; parameter val_debug_cti_axim__CTIOUTEN5 = 32'h00000000; parameter mask_debug_cti_axim__CTIOUTEN5 = 32'h0000000F; parameter debug_cti_axim__CTIOUTEN6 = 32'hF880A0B8; parameter val_debug_cti_axim__CTIOUTEN6 = 32'h00000000; parameter mask_debug_cti_axim__CTIOUTEN6 = 32'h0000000F; parameter debug_cti_axim__CTIOUTEN7 = 32'hF880A0BC; parameter val_debug_cti_axim__CTIOUTEN7 = 32'h00000000; parameter mask_debug_cti_axim__CTIOUTEN7 = 32'h0000000F; parameter debug_cti_axim__CTITRIGINSTATUS = 32'hF880A130; parameter val_debug_cti_axim__CTITRIGINSTATUS = 32'h00000000; parameter mask_debug_cti_axim__CTITRIGINSTATUS = 32'h00000000; parameter debug_cti_axim__CTITRIGOUTSTATUS = 32'hF880A134; parameter val_debug_cti_axim__CTITRIGOUTSTATUS = 32'h00000000; parameter mask_debug_cti_axim__CTITRIGOUTSTATUS = 32'h000000FF; parameter debug_cti_axim__CTICHINSTATUS = 32'hF880A138; parameter val_debug_cti_axim__CTICHINSTATUS = 32'h00000000; parameter mask_debug_cti_axim__CTICHINSTATUS = 32'h00000000; parameter debug_cti_axim__CTICHOUTSTATUS = 32'hF880A13C; parameter val_debug_cti_axim__CTICHOUTSTATUS = 32'h00000000; parameter mask_debug_cti_axim__CTICHOUTSTATUS = 32'h0000000F; parameter debug_cti_axim__CTIGATE = 32'hF880A140; parameter val_debug_cti_axim__CTIGATE = 32'h0000000F; parameter mask_debug_cti_axim__CTIGATE = 32'h0000000F; parameter debug_cti_axim__ASICCTL = 32'hF880A144; parameter val_debug_cti_axim__ASICCTL = 32'h00000000; parameter mask_debug_cti_axim__ASICCTL = 32'h000000FF; parameter debug_cti_axim__ITCHINACK = 32'hF880AEDC; parameter val_debug_cti_axim__ITCHINACK = 32'h00000000; parameter mask_debug_cti_axim__ITCHINACK = 32'h0000000F; parameter debug_cti_axim__ITTRIGINACK = 32'hF880AEE0; parameter val_debug_cti_axim__ITTRIGINACK = 32'h00000000; parameter mask_debug_cti_axim__ITTRIGINACK = 32'h000000FF; parameter debug_cti_axim__ITCHOUT = 32'hF880AEE4; parameter val_debug_cti_axim__ITCHOUT = 32'h00000000; parameter mask_debug_cti_axim__ITCHOUT = 32'h0000000F; parameter debug_cti_axim__ITTRIGOUT = 32'hF880AEE8; parameter val_debug_cti_axim__ITTRIGOUT = 32'h00000000; parameter mask_debug_cti_axim__ITTRIGOUT = 32'h000000FF; parameter debug_cti_axim__ITCHOUTACK = 32'hF880AEEC; parameter val_debug_cti_axim__ITCHOUTACK = 32'h00000000; parameter mask_debug_cti_axim__ITCHOUTACK = 32'h0000000F; parameter debug_cti_axim__ITTRIGOUTACK = 32'hF880AEF0; parameter val_debug_cti_axim__ITTRIGOUTACK = 32'h00000000; parameter mask_debug_cti_axim__ITTRIGOUTACK = 32'h000000FF; parameter debug_cti_axim__ITCHIN = 32'hF880AEF4; parameter val_debug_cti_axim__ITCHIN = 32'h00000000; parameter mask_debug_cti_axim__ITCHIN = 32'h0000000F; parameter debug_cti_axim__ITTRIGIN = 32'hF880AEF8; parameter val_debug_cti_axim__ITTRIGIN = 32'h00000000; parameter mask_debug_cti_axim__ITTRIGIN = 32'h000000FF; parameter debug_cti_axim__ITCTRL = 32'hF880AF00; parameter val_debug_cti_axim__ITCTRL = 32'h00000000; parameter mask_debug_cti_axim__ITCTRL = 32'h00000001; parameter debug_cti_axim__CTSR = 32'hF880AFA0; parameter val_debug_cti_axim__CTSR = 32'h0000000F; parameter mask_debug_cti_axim__CTSR = 32'h0000000F; parameter debug_cti_axim__CTCR = 32'hF880AFA4; parameter val_debug_cti_axim__CTCR = 32'h00000000; parameter mask_debug_cti_axim__CTCR = 32'h0000000F; parameter debug_cti_axim__LAR = 32'hF880AFB0; parameter val_debug_cti_axim__LAR = 32'h00000000; parameter mask_debug_cti_axim__LAR = 32'hFFFFFFFF; parameter debug_cti_axim__LSR = 32'hF880AFB4; parameter val_debug_cti_axim__LSR = 32'h00000003; parameter mask_debug_cti_axim__LSR = 32'h00000007; parameter debug_cti_axim__ASR = 32'hF880AFB8; parameter val_debug_cti_axim__ASR = 32'h00000005; parameter mask_debug_cti_axim__ASR = 32'h00000005; parameter debug_cti_axim__DEVID = 32'hF880AFC8; parameter val_debug_cti_axim__DEVID = 32'h00040800; parameter mask_debug_cti_axim__DEVID = 32'h000FFFFF; parameter debug_cti_axim__DTIR = 32'hF880AFCC; parameter val_debug_cti_axim__DTIR = 32'h00000014; parameter mask_debug_cti_axim__DTIR = 32'h000000FF; parameter debug_cti_axim__PERIPHID4 = 32'hF880AFD0; parameter val_debug_cti_axim__PERIPHID4 = 32'h00000004; parameter mask_debug_cti_axim__PERIPHID4 = 32'h000000FF; parameter debug_cti_axim__PERIPHID5 = 32'hF880AFD4; parameter val_debug_cti_axim__PERIPHID5 = 32'h00000000; parameter mask_debug_cti_axim__PERIPHID5 = 32'h000000FF; parameter debug_cti_axim__PERIPHID6 = 32'hF880AFD8; parameter val_debug_cti_axim__PERIPHID6 = 32'h00000000; parameter mask_debug_cti_axim__PERIPHID6 = 32'h000000FF; parameter debug_cti_axim__PERIPHID7 = 32'hF880AFDC; parameter val_debug_cti_axim__PERIPHID7 = 32'h00000000; parameter mask_debug_cti_axim__PERIPHID7 = 32'h000000FF; parameter debug_cti_axim__PERIPHID0 = 32'hF880AFE0; parameter val_debug_cti_axim__PERIPHID0 = 32'h00000006; parameter mask_debug_cti_axim__PERIPHID0 = 32'h000000FF; parameter debug_cti_axim__PERIPHID1 = 32'hF880AFE4; parameter val_debug_cti_axim__PERIPHID1 = 32'h000000B9; parameter mask_debug_cti_axim__PERIPHID1 = 32'h000000FF; parameter debug_cti_axim__PERIPHID2 = 32'hF880AFE8; parameter val_debug_cti_axim__PERIPHID2 = 32'h0000002B; parameter mask_debug_cti_axim__PERIPHID2 = 32'h000000FF; parameter debug_cti_axim__PERIPHID3 = 32'hF880AFEC; parameter val_debug_cti_axim__PERIPHID3 = 32'h00000000; parameter mask_debug_cti_axim__PERIPHID3 = 32'h000000FF; parameter debug_cti_axim__COMPID0 = 32'hF880AFF0; parameter val_debug_cti_axim__COMPID0 = 32'h0000000D; parameter mask_debug_cti_axim__COMPID0 = 32'h000000FF; parameter debug_cti_axim__COMPID1 = 32'hF880AFF4; parameter val_debug_cti_axim__COMPID1 = 32'h00000090; parameter mask_debug_cti_axim__COMPID1 = 32'h000000FF; parameter debug_cti_axim__COMPID2 = 32'hF880AFF8; parameter val_debug_cti_axim__COMPID2 = 32'h00000005; parameter mask_debug_cti_axim__COMPID2 = 32'h000000FF; parameter debug_cti_axim__COMPID3 = 32'hF880AFFC; parameter val_debug_cti_axim__COMPID3 = 32'h000000B1; parameter mask_debug_cti_axim__COMPID3 = 32'h000000FF; // ************************************************************ // Module debug_cti_etb_tpiu cti // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter debug_cti_etb_tpiu__CTICONTROL = 32'hF8802000; parameter val_debug_cti_etb_tpiu__CTICONTROL = 32'h00000000; parameter mask_debug_cti_etb_tpiu__CTICONTROL = 32'h00000001; parameter debug_cti_etb_tpiu__CTIINTACK = 32'hF8802010; parameter val_debug_cti_etb_tpiu__CTIINTACK = 32'h00000000; parameter mask_debug_cti_etb_tpiu__CTIINTACK = 32'h000000FF; parameter debug_cti_etb_tpiu__CTIAPPSET = 32'hF8802014; parameter val_debug_cti_etb_tpiu__CTIAPPSET = 32'h00000000; parameter mask_debug_cti_etb_tpiu__CTIAPPSET = 32'h0000000F; parameter debug_cti_etb_tpiu__CTIAPPCLEAR = 32'hF8802018; parameter val_debug_cti_etb_tpiu__CTIAPPCLEAR = 32'h00000000; parameter mask_debug_cti_etb_tpiu__CTIAPPCLEAR = 32'h0000000F; parameter debug_cti_etb_tpiu__CTIAPPPULSE = 32'hF880201C; parameter val_debug_cti_etb_tpiu__CTIAPPPULSE = 32'h00000000; parameter mask_debug_cti_etb_tpiu__CTIAPPPULSE = 32'h0000000F; parameter debug_cti_etb_tpiu__CTIINEN0 = 32'hF8802020; parameter val_debug_cti_etb_tpiu__CTIINEN0 = 32'h00000000; parameter mask_debug_cti_etb_tpiu__CTIINEN0 = 32'h0000000F; parameter debug_cti_etb_tpiu__CTIINEN1 = 32'hF8802024; parameter val_debug_cti_etb_tpiu__CTIINEN1 = 32'h00000000; parameter mask_debug_cti_etb_tpiu__CTIINEN1 = 32'h0000000F; parameter debug_cti_etb_tpiu__CTIINEN2 = 32'hF8802028; parameter val_debug_cti_etb_tpiu__CTIINEN2 = 32'h00000000; parameter mask_debug_cti_etb_tpiu__CTIINEN2 = 32'h0000000F; parameter debug_cti_etb_tpiu__CTIINEN3 = 32'hF880202C; parameter val_debug_cti_etb_tpiu__CTIINEN3 = 32'h00000000; parameter mask_debug_cti_etb_tpiu__CTIINEN3 = 32'h0000000F; parameter debug_cti_etb_tpiu__CTIINEN4 = 32'hF8802030; parameter val_debug_cti_etb_tpiu__CTIINEN4 = 32'h00000000; parameter mask_debug_cti_etb_tpiu__CTIINEN4 = 32'h0000000F; parameter debug_cti_etb_tpiu__CTIINEN5 = 32'hF8802034; parameter val_debug_cti_etb_tpiu__CTIINEN5 = 32'h00000000; parameter mask_debug_cti_etb_tpiu__CTIINEN5 = 32'h0000000F; parameter debug_cti_etb_tpiu__CTIINEN6 = 32'hF8802038; parameter val_debug_cti_etb_tpiu__CTIINEN6 = 32'h00000000; parameter mask_debug_cti_etb_tpiu__CTIINEN6 = 32'h0000000F; parameter debug_cti_etb_tpiu__CTIINEN7 = 32'hF880203C; parameter val_debug_cti_etb_tpiu__CTIINEN7 = 32'h00000000; parameter mask_debug_cti_etb_tpiu__CTIINEN7 = 32'h0000000F; parameter debug_cti_etb_tpiu__CTIOUTEN0 = 32'hF88020A0; parameter val_debug_cti_etb_tpiu__CTIOUTEN0 = 32'h00000000; parameter mask_debug_cti_etb_tpiu__CTIOUTEN0 = 32'h0000000F; parameter debug_cti_etb_tpiu__CTIOUTEN1 = 32'hF88020A4; parameter val_debug_cti_etb_tpiu__CTIOUTEN1 = 32'h00000000; parameter mask_debug_cti_etb_tpiu__CTIOUTEN1 = 32'h0000000F; parameter debug_cti_etb_tpiu__CTIOUTEN2 = 32'hF88020A8; parameter val_debug_cti_etb_tpiu__CTIOUTEN2 = 32'h00000000; parameter mask_debug_cti_etb_tpiu__CTIOUTEN2 = 32'h0000000F; parameter debug_cti_etb_tpiu__CTIOUTEN3 = 32'hF88020AC; parameter val_debug_cti_etb_tpiu__CTIOUTEN3 = 32'h00000000; parameter mask_debug_cti_etb_tpiu__CTIOUTEN3 = 32'h0000000F; parameter debug_cti_etb_tpiu__CTIOUTEN4 = 32'hF88020B0; parameter val_debug_cti_etb_tpiu__CTIOUTEN4 = 32'h00000000; parameter mask_debug_cti_etb_tpiu__CTIOUTEN4 = 32'h0000000F; parameter debug_cti_etb_tpiu__CTIOUTEN5 = 32'hF88020B4; parameter val_debug_cti_etb_tpiu__CTIOUTEN5 = 32'h00000000; parameter mask_debug_cti_etb_tpiu__CTIOUTEN5 = 32'h0000000F; parameter debug_cti_etb_tpiu__CTIOUTEN6 = 32'hF88020B8; parameter val_debug_cti_etb_tpiu__CTIOUTEN6 = 32'h00000000; parameter mask_debug_cti_etb_tpiu__CTIOUTEN6 = 32'h0000000F; parameter debug_cti_etb_tpiu__CTIOUTEN7 = 32'hF88020BC; parameter val_debug_cti_etb_tpiu__CTIOUTEN7 = 32'h00000000; parameter mask_debug_cti_etb_tpiu__CTIOUTEN7 = 32'h0000000F; parameter debug_cti_etb_tpiu__CTITRIGINSTATUS = 32'hF8802130; parameter val_debug_cti_etb_tpiu__CTITRIGINSTATUS = 32'h00000000; parameter mask_debug_cti_etb_tpiu__CTITRIGINSTATUS = 32'h00000000; parameter debug_cti_etb_tpiu__CTITRIGOUTSTATUS = 32'hF8802134; parameter val_debug_cti_etb_tpiu__CTITRIGOUTSTATUS = 32'h00000000; parameter mask_debug_cti_etb_tpiu__CTITRIGOUTSTATUS = 32'h000000FF; parameter debug_cti_etb_tpiu__CTICHINSTATUS = 32'hF8802138; parameter val_debug_cti_etb_tpiu__CTICHINSTATUS = 32'h00000000; parameter mask_debug_cti_etb_tpiu__CTICHINSTATUS = 32'h00000000; parameter debug_cti_etb_tpiu__CTICHOUTSTATUS = 32'hF880213C; parameter val_debug_cti_etb_tpiu__CTICHOUTSTATUS = 32'h00000000; parameter mask_debug_cti_etb_tpiu__CTICHOUTSTATUS = 32'h0000000F; parameter debug_cti_etb_tpiu__CTIGATE = 32'hF8802140; parameter val_debug_cti_etb_tpiu__CTIGATE = 32'h0000000F; parameter mask_debug_cti_etb_tpiu__CTIGATE = 32'h0000000F; parameter debug_cti_etb_tpiu__ASICCTL = 32'hF8802144; parameter val_debug_cti_etb_tpiu__ASICCTL = 32'h00000000; parameter mask_debug_cti_etb_tpiu__ASICCTL = 32'h000000FF; parameter debug_cti_etb_tpiu__ITCHINACK = 32'hF8802EDC; parameter val_debug_cti_etb_tpiu__ITCHINACK = 32'h00000000; parameter mask_debug_cti_etb_tpiu__ITCHINACK = 32'h0000000F; parameter debug_cti_etb_tpiu__ITTRIGINACK = 32'hF8802EE0; parameter val_debug_cti_etb_tpiu__ITTRIGINACK = 32'h00000000; parameter mask_debug_cti_etb_tpiu__ITTRIGINACK = 32'h000000FF; parameter debug_cti_etb_tpiu__ITCHOUT = 32'hF8802EE4; parameter val_debug_cti_etb_tpiu__ITCHOUT = 32'h00000000; parameter mask_debug_cti_etb_tpiu__ITCHOUT = 32'h0000000F; parameter debug_cti_etb_tpiu__ITTRIGOUT = 32'hF8802EE8; parameter val_debug_cti_etb_tpiu__ITTRIGOUT = 32'h00000000; parameter mask_debug_cti_etb_tpiu__ITTRIGOUT = 32'h000000FF; parameter debug_cti_etb_tpiu__ITCHOUTACK = 32'hF8802EEC; parameter val_debug_cti_etb_tpiu__ITCHOUTACK = 32'h00000000; parameter mask_debug_cti_etb_tpiu__ITCHOUTACK = 32'h0000000F; parameter debug_cti_etb_tpiu__ITTRIGOUTACK = 32'hF8802EF0; parameter val_debug_cti_etb_tpiu__ITTRIGOUTACK = 32'h00000000; parameter mask_debug_cti_etb_tpiu__ITTRIGOUTACK = 32'h000000FF; parameter debug_cti_etb_tpiu__ITCHIN = 32'hF8802EF4; parameter val_debug_cti_etb_tpiu__ITCHIN = 32'h00000000; parameter mask_debug_cti_etb_tpiu__ITCHIN = 32'h0000000F; parameter debug_cti_etb_tpiu__ITTRIGIN = 32'hF8802EF8; parameter val_debug_cti_etb_tpiu__ITTRIGIN = 32'h00000000; parameter mask_debug_cti_etb_tpiu__ITTRIGIN = 32'h000000FF; parameter debug_cti_etb_tpiu__ITCTRL = 32'hF8802F00; parameter val_debug_cti_etb_tpiu__ITCTRL = 32'h00000000; parameter mask_debug_cti_etb_tpiu__ITCTRL = 32'h00000001; parameter debug_cti_etb_tpiu__CTSR = 32'hF8802FA0; parameter val_debug_cti_etb_tpiu__CTSR = 32'h0000000F; parameter mask_debug_cti_etb_tpiu__CTSR = 32'h0000000F; parameter debug_cti_etb_tpiu__CTCR = 32'hF8802FA4; parameter val_debug_cti_etb_tpiu__CTCR = 32'h00000000; parameter mask_debug_cti_etb_tpiu__CTCR = 32'h0000000F; parameter debug_cti_etb_tpiu__LAR = 32'hF8802FB0; parameter val_debug_cti_etb_tpiu__LAR = 32'h00000000; parameter mask_debug_cti_etb_tpiu__LAR = 32'hFFFFFFFF; parameter debug_cti_etb_tpiu__LSR = 32'hF8802FB4; parameter val_debug_cti_etb_tpiu__LSR = 32'h00000003; parameter mask_debug_cti_etb_tpiu__LSR = 32'h00000007; parameter debug_cti_etb_tpiu__ASR = 32'hF8802FB8; parameter val_debug_cti_etb_tpiu__ASR = 32'h00000005; parameter mask_debug_cti_etb_tpiu__ASR = 32'h00000005; parameter debug_cti_etb_tpiu__DEVID = 32'hF8802FC8; parameter val_debug_cti_etb_tpiu__DEVID = 32'h00040800; parameter mask_debug_cti_etb_tpiu__DEVID = 32'h000FFFFF; parameter debug_cti_etb_tpiu__DTIR = 32'hF8802FCC; parameter val_debug_cti_etb_tpiu__DTIR = 32'h00000014; parameter mask_debug_cti_etb_tpiu__DTIR = 32'h000000FF; parameter debug_cti_etb_tpiu__PERIPHID4 = 32'hF8802FD0; parameter val_debug_cti_etb_tpiu__PERIPHID4 = 32'h00000004; parameter mask_debug_cti_etb_tpiu__PERIPHID4 = 32'h000000FF; parameter debug_cti_etb_tpiu__PERIPHID5 = 32'hF8802FD4; parameter val_debug_cti_etb_tpiu__PERIPHID5 = 32'h00000000; parameter mask_debug_cti_etb_tpiu__PERIPHID5 = 32'h000000FF; parameter debug_cti_etb_tpiu__PERIPHID6 = 32'hF8802FD8; parameter val_debug_cti_etb_tpiu__PERIPHID6 = 32'h00000000; parameter mask_debug_cti_etb_tpiu__PERIPHID6 = 32'h000000FF; parameter debug_cti_etb_tpiu__PERIPHID7 = 32'hF8802FDC; parameter val_debug_cti_etb_tpiu__PERIPHID7 = 32'h00000000; parameter mask_debug_cti_etb_tpiu__PERIPHID7 = 32'h000000FF; parameter debug_cti_etb_tpiu__PERIPHID0 = 32'hF8802FE0; parameter val_debug_cti_etb_tpiu__PERIPHID0 = 32'h00000006; parameter mask_debug_cti_etb_tpiu__PERIPHID0 = 32'h000000FF; parameter debug_cti_etb_tpiu__PERIPHID1 = 32'hF8802FE4; parameter val_debug_cti_etb_tpiu__PERIPHID1 = 32'h000000B9; parameter mask_debug_cti_etb_tpiu__PERIPHID1 = 32'h000000FF; parameter debug_cti_etb_tpiu__PERIPHID2 = 32'hF8802FE8; parameter val_debug_cti_etb_tpiu__PERIPHID2 = 32'h0000002B; parameter mask_debug_cti_etb_tpiu__PERIPHID2 = 32'h000000FF; parameter debug_cti_etb_tpiu__PERIPHID3 = 32'hF8802FEC; parameter val_debug_cti_etb_tpiu__PERIPHID3 = 32'h00000000; parameter mask_debug_cti_etb_tpiu__PERIPHID3 = 32'h000000FF; parameter debug_cti_etb_tpiu__COMPID0 = 32'hF8802FF0; parameter val_debug_cti_etb_tpiu__COMPID0 = 32'h0000000D; parameter mask_debug_cti_etb_tpiu__COMPID0 = 32'h000000FF; parameter debug_cti_etb_tpiu__COMPID1 = 32'hF8802FF4; parameter val_debug_cti_etb_tpiu__COMPID1 = 32'h00000090; parameter mask_debug_cti_etb_tpiu__COMPID1 = 32'h000000FF; parameter debug_cti_etb_tpiu__COMPID2 = 32'hF8802FF8; parameter val_debug_cti_etb_tpiu__COMPID2 = 32'h00000005; parameter mask_debug_cti_etb_tpiu__COMPID2 = 32'h000000FF; parameter debug_cti_etb_tpiu__COMPID3 = 32'hF8802FFC; parameter val_debug_cti_etb_tpiu__COMPID3 = 32'h000000B1; parameter mask_debug_cti_etb_tpiu__COMPID3 = 32'h000000FF; // ************************************************************ // Module debug_cti_ftm cti // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter debug_cti_ftm__CTICONTROL = 32'hF8809000; parameter val_debug_cti_ftm__CTICONTROL = 32'h00000000; parameter mask_debug_cti_ftm__CTICONTROL = 32'h00000001; parameter debug_cti_ftm__CTIINTACK = 32'hF8809010; parameter val_debug_cti_ftm__CTIINTACK = 32'h00000000; parameter mask_debug_cti_ftm__CTIINTACK = 32'h000000FF; parameter debug_cti_ftm__CTIAPPSET = 32'hF8809014; parameter val_debug_cti_ftm__CTIAPPSET = 32'h00000000; parameter mask_debug_cti_ftm__CTIAPPSET = 32'h0000000F; parameter debug_cti_ftm__CTIAPPCLEAR = 32'hF8809018; parameter val_debug_cti_ftm__CTIAPPCLEAR = 32'h00000000; parameter mask_debug_cti_ftm__CTIAPPCLEAR = 32'h0000000F; parameter debug_cti_ftm__CTIAPPPULSE = 32'hF880901C; parameter val_debug_cti_ftm__CTIAPPPULSE = 32'h00000000; parameter mask_debug_cti_ftm__CTIAPPPULSE = 32'h0000000F; parameter debug_cti_ftm__CTIINEN0 = 32'hF8809020; parameter val_debug_cti_ftm__CTIINEN0 = 32'h00000000; parameter mask_debug_cti_ftm__CTIINEN0 = 32'h0000000F; parameter debug_cti_ftm__CTIINEN1 = 32'hF8809024; parameter val_debug_cti_ftm__CTIINEN1 = 32'h00000000; parameter mask_debug_cti_ftm__CTIINEN1 = 32'h0000000F; parameter debug_cti_ftm__CTIINEN2 = 32'hF8809028; parameter val_debug_cti_ftm__CTIINEN2 = 32'h00000000; parameter mask_debug_cti_ftm__CTIINEN2 = 32'h0000000F; parameter debug_cti_ftm__CTIINEN3 = 32'hF880902C; parameter val_debug_cti_ftm__CTIINEN3 = 32'h00000000; parameter mask_debug_cti_ftm__CTIINEN3 = 32'h0000000F; parameter debug_cti_ftm__CTIINEN4 = 32'hF8809030; parameter val_debug_cti_ftm__CTIINEN4 = 32'h00000000; parameter mask_debug_cti_ftm__CTIINEN4 = 32'h0000000F; parameter debug_cti_ftm__CTIINEN5 = 32'hF8809034; parameter val_debug_cti_ftm__CTIINEN5 = 32'h00000000; parameter mask_debug_cti_ftm__CTIINEN5 = 32'h0000000F; parameter debug_cti_ftm__CTIINEN6 = 32'hF8809038; parameter val_debug_cti_ftm__CTIINEN6 = 32'h00000000; parameter mask_debug_cti_ftm__CTIINEN6 = 32'h0000000F; parameter debug_cti_ftm__CTIINEN7 = 32'hF880903C; parameter val_debug_cti_ftm__CTIINEN7 = 32'h00000000; parameter mask_debug_cti_ftm__CTIINEN7 = 32'h0000000F; parameter debug_cti_ftm__CTIOUTEN0 = 32'hF88090A0; parameter val_debug_cti_ftm__CTIOUTEN0 = 32'h00000000; parameter mask_debug_cti_ftm__CTIOUTEN0 = 32'h0000000F; parameter debug_cti_ftm__CTIOUTEN1 = 32'hF88090A4; parameter val_debug_cti_ftm__CTIOUTEN1 = 32'h00000000; parameter mask_debug_cti_ftm__CTIOUTEN1 = 32'h0000000F; parameter debug_cti_ftm__CTIOUTEN2 = 32'hF88090A8; parameter val_debug_cti_ftm__CTIOUTEN2 = 32'h00000000; parameter mask_debug_cti_ftm__CTIOUTEN2 = 32'h0000000F; parameter debug_cti_ftm__CTIOUTEN3 = 32'hF88090AC; parameter val_debug_cti_ftm__CTIOUTEN3 = 32'h00000000; parameter mask_debug_cti_ftm__CTIOUTEN3 = 32'h0000000F; parameter debug_cti_ftm__CTIOUTEN4 = 32'hF88090B0; parameter val_debug_cti_ftm__CTIOUTEN4 = 32'h00000000; parameter mask_debug_cti_ftm__CTIOUTEN4 = 32'h0000000F; parameter debug_cti_ftm__CTIOUTEN5 = 32'hF88090B4; parameter val_debug_cti_ftm__CTIOUTEN5 = 32'h00000000; parameter mask_debug_cti_ftm__CTIOUTEN5 = 32'h0000000F; parameter debug_cti_ftm__CTIOUTEN6 = 32'hF88090B8; parameter val_debug_cti_ftm__CTIOUTEN6 = 32'h00000000; parameter mask_debug_cti_ftm__CTIOUTEN6 = 32'h0000000F; parameter debug_cti_ftm__CTIOUTEN7 = 32'hF88090BC; parameter val_debug_cti_ftm__CTIOUTEN7 = 32'h00000000; parameter mask_debug_cti_ftm__CTIOUTEN7 = 32'h0000000F; parameter debug_cti_ftm__CTITRIGINSTATUS = 32'hF8809130; parameter val_debug_cti_ftm__CTITRIGINSTATUS = 32'h00000000; parameter mask_debug_cti_ftm__CTITRIGINSTATUS = 32'h00000000; parameter debug_cti_ftm__CTITRIGOUTSTATUS = 32'hF8809134; parameter val_debug_cti_ftm__CTITRIGOUTSTATUS = 32'h00000000; parameter mask_debug_cti_ftm__CTITRIGOUTSTATUS = 32'h000000FF; parameter debug_cti_ftm__CTICHINSTATUS = 32'hF8809138; parameter val_debug_cti_ftm__CTICHINSTATUS = 32'h00000000; parameter mask_debug_cti_ftm__CTICHINSTATUS = 32'h00000000; parameter debug_cti_ftm__CTICHOUTSTATUS = 32'hF880913C; parameter val_debug_cti_ftm__CTICHOUTSTATUS = 32'h00000000; parameter mask_debug_cti_ftm__CTICHOUTSTATUS = 32'h0000000F; parameter debug_cti_ftm__CTIGATE = 32'hF8809140; parameter val_debug_cti_ftm__CTIGATE = 32'h0000000F; parameter mask_debug_cti_ftm__CTIGATE = 32'h0000000F; parameter debug_cti_ftm__ASICCTL = 32'hF8809144; parameter val_debug_cti_ftm__ASICCTL = 32'h00000000; parameter mask_debug_cti_ftm__ASICCTL = 32'h000000FF; parameter debug_cti_ftm__ITCHINACK = 32'hF8809EDC; parameter val_debug_cti_ftm__ITCHINACK = 32'h00000000; parameter mask_debug_cti_ftm__ITCHINACK = 32'h0000000F; parameter debug_cti_ftm__ITTRIGINACK = 32'hF8809EE0; parameter val_debug_cti_ftm__ITTRIGINACK = 32'h00000000; parameter mask_debug_cti_ftm__ITTRIGINACK = 32'h000000FF; parameter debug_cti_ftm__ITCHOUT = 32'hF8809EE4; parameter val_debug_cti_ftm__ITCHOUT = 32'h00000000; parameter mask_debug_cti_ftm__ITCHOUT = 32'h0000000F; parameter debug_cti_ftm__ITTRIGOUT = 32'hF8809EE8; parameter val_debug_cti_ftm__ITTRIGOUT = 32'h00000000; parameter mask_debug_cti_ftm__ITTRIGOUT = 32'h000000FF; parameter debug_cti_ftm__ITCHOUTACK = 32'hF8809EEC; parameter val_debug_cti_ftm__ITCHOUTACK = 32'h00000000; parameter mask_debug_cti_ftm__ITCHOUTACK = 32'h0000000F; parameter debug_cti_ftm__ITTRIGOUTACK = 32'hF8809EF0; parameter val_debug_cti_ftm__ITTRIGOUTACK = 32'h00000000; parameter mask_debug_cti_ftm__ITTRIGOUTACK = 32'h000000FF; parameter debug_cti_ftm__ITCHIN = 32'hF8809EF4; parameter val_debug_cti_ftm__ITCHIN = 32'h00000000; parameter mask_debug_cti_ftm__ITCHIN = 32'h0000000F; parameter debug_cti_ftm__ITTRIGIN = 32'hF8809EF8; parameter val_debug_cti_ftm__ITTRIGIN = 32'h00000000; parameter mask_debug_cti_ftm__ITTRIGIN = 32'h000000FF; parameter debug_cti_ftm__ITCTRL = 32'hF8809F00; parameter val_debug_cti_ftm__ITCTRL = 32'h00000000; parameter mask_debug_cti_ftm__ITCTRL = 32'h00000001; parameter debug_cti_ftm__CTSR = 32'hF8809FA0; parameter val_debug_cti_ftm__CTSR = 32'h0000000F; parameter mask_debug_cti_ftm__CTSR = 32'h0000000F; parameter debug_cti_ftm__CTCR = 32'hF8809FA4; parameter val_debug_cti_ftm__CTCR = 32'h00000000; parameter mask_debug_cti_ftm__CTCR = 32'h0000000F; parameter debug_cti_ftm__LAR = 32'hF8809FB0; parameter val_debug_cti_ftm__LAR = 32'h00000000; parameter mask_debug_cti_ftm__LAR = 32'hFFFFFFFF; parameter debug_cti_ftm__LSR = 32'hF8809FB4; parameter val_debug_cti_ftm__LSR = 32'h00000003; parameter mask_debug_cti_ftm__LSR = 32'h00000007; parameter debug_cti_ftm__ASR = 32'hF8809FB8; parameter val_debug_cti_ftm__ASR = 32'h00000005; parameter mask_debug_cti_ftm__ASR = 32'h00000005; parameter debug_cti_ftm__DEVID = 32'hF8809FC8; parameter val_debug_cti_ftm__DEVID = 32'h00040800; parameter mask_debug_cti_ftm__DEVID = 32'h000FFFFF; parameter debug_cti_ftm__DTIR = 32'hF8809FCC; parameter val_debug_cti_ftm__DTIR = 32'h00000014; parameter mask_debug_cti_ftm__DTIR = 32'h000000FF; parameter debug_cti_ftm__PERIPHID4 = 32'hF8809FD0; parameter val_debug_cti_ftm__PERIPHID4 = 32'h00000004; parameter mask_debug_cti_ftm__PERIPHID4 = 32'h000000FF; parameter debug_cti_ftm__PERIPHID5 = 32'hF8809FD4; parameter val_debug_cti_ftm__PERIPHID5 = 32'h00000000; parameter mask_debug_cti_ftm__PERIPHID5 = 32'h000000FF; parameter debug_cti_ftm__PERIPHID6 = 32'hF8809FD8; parameter val_debug_cti_ftm__PERIPHID6 = 32'h00000000; parameter mask_debug_cti_ftm__PERIPHID6 = 32'h000000FF; parameter debug_cti_ftm__PERIPHID7 = 32'hF8809FDC; parameter val_debug_cti_ftm__PERIPHID7 = 32'h00000000; parameter mask_debug_cti_ftm__PERIPHID7 = 32'h000000FF; parameter debug_cti_ftm__PERIPHID0 = 32'hF8809FE0; parameter val_debug_cti_ftm__PERIPHID0 = 32'h00000006; parameter mask_debug_cti_ftm__PERIPHID0 = 32'h000000FF; parameter debug_cti_ftm__PERIPHID1 = 32'hF8809FE4; parameter val_debug_cti_ftm__PERIPHID1 = 32'h000000B9; parameter mask_debug_cti_ftm__PERIPHID1 = 32'h000000FF; parameter debug_cti_ftm__PERIPHID2 = 32'hF8809FE8; parameter val_debug_cti_ftm__PERIPHID2 = 32'h0000002B; parameter mask_debug_cti_ftm__PERIPHID2 = 32'h000000FF; parameter debug_cti_ftm__PERIPHID3 = 32'hF8809FEC; parameter val_debug_cti_ftm__PERIPHID3 = 32'h00000000; parameter mask_debug_cti_ftm__PERIPHID3 = 32'h000000FF; parameter debug_cti_ftm__COMPID0 = 32'hF8809FF0; parameter val_debug_cti_ftm__COMPID0 = 32'h0000000D; parameter mask_debug_cti_ftm__COMPID0 = 32'h000000FF; parameter debug_cti_ftm__COMPID1 = 32'hF8809FF4; parameter val_debug_cti_ftm__COMPID1 = 32'h00000090; parameter mask_debug_cti_ftm__COMPID1 = 32'h000000FF; parameter debug_cti_ftm__COMPID2 = 32'hF8809FF8; parameter val_debug_cti_ftm__COMPID2 = 32'h00000005; parameter mask_debug_cti_ftm__COMPID2 = 32'h000000FF; parameter debug_cti_ftm__COMPID3 = 32'hF8809FFC; parameter val_debug_cti_ftm__COMPID3 = 32'h000000B1; parameter mask_debug_cti_ftm__COMPID3 = 32'h000000FF; // ************************************************************ // Module debug_dap_rom dap // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter debug_dap_rom__ROMENTRY00 = 32'hF8800000; parameter val_debug_dap_rom__ROMENTRY00 = 32'h00001003; parameter mask_debug_dap_rom__ROMENTRY00 = 32'hFFFFFFFF; parameter debug_dap_rom__ROMENTRY01 = 32'hF8800004; parameter val_debug_dap_rom__ROMENTRY01 = 32'h00002003; parameter mask_debug_dap_rom__ROMENTRY01 = 32'hFFFFFFFF; parameter debug_dap_rom__ROMENTRY02 = 32'hF8800008; parameter val_debug_dap_rom__ROMENTRY02 = 32'h00003003; parameter mask_debug_dap_rom__ROMENTRY02 = 32'hFFFFFFFF; parameter debug_dap_rom__ROMENTRY03 = 32'hF880000C; parameter val_debug_dap_rom__ROMENTRY03 = 32'h00004003; parameter mask_debug_dap_rom__ROMENTRY03 = 32'hFFFFFFFF; parameter debug_dap_rom__ROMENTRY04 = 32'hF8800010; parameter val_debug_dap_rom__ROMENTRY04 = 32'h00005003; parameter mask_debug_dap_rom__ROMENTRY04 = 32'hFFFFFFFF; parameter debug_dap_rom__ROMENTRY05 = 32'hF8800014; parameter val_debug_dap_rom__ROMENTRY05 = 32'h00009003; parameter mask_debug_dap_rom__ROMENTRY05 = 32'hFFFFFFFF; parameter debug_dap_rom__ROMENTRY06 = 32'hF8800018; parameter val_debug_dap_rom__ROMENTRY06 = 32'h0000A003; parameter mask_debug_dap_rom__ROMENTRY06 = 32'hFFFFFFFF; parameter debug_dap_rom__ROMENTRY07 = 32'hF880001C; parameter val_debug_dap_rom__ROMENTRY07 = 32'h0000B003; parameter mask_debug_dap_rom__ROMENTRY07 = 32'hFFFFFFFF; parameter debug_dap_rom__ROMENTRY08 = 32'hF8800020; parameter val_debug_dap_rom__ROMENTRY08 = 32'h0000C003; parameter mask_debug_dap_rom__ROMENTRY08 = 32'hFFFFFFFF; parameter debug_dap_rom__ROMENTRY09 = 32'hF8800024; parameter val_debug_dap_rom__ROMENTRY09 = 32'h00080003; parameter mask_debug_dap_rom__ROMENTRY09 = 32'hFFFFFFFF; parameter debug_dap_rom__ROMENTRY10 = 32'hF8800028; parameter val_debug_dap_rom__ROMENTRY10 = 32'h00000000; parameter mask_debug_dap_rom__ROMENTRY10 = 32'hFFFFFFFF; parameter debug_dap_rom__ROMENTRY11 = 32'hF880002C; parameter val_debug_dap_rom__ROMENTRY11 = 32'h00000000; parameter mask_debug_dap_rom__ROMENTRY11 = 32'hFFFFFFFF; parameter debug_dap_rom__ROMENTRY12 = 32'hF8800030; parameter val_debug_dap_rom__ROMENTRY12 = 32'h00000000; parameter mask_debug_dap_rom__ROMENTRY12 = 32'hFFFFFFFF; parameter debug_dap_rom__ROMENTRY13 = 32'hF8800034; parameter val_debug_dap_rom__ROMENTRY13 = 32'h00000000; parameter mask_debug_dap_rom__ROMENTRY13 = 32'hFFFFFFFF; parameter debug_dap_rom__ROMENTRY14 = 32'hF8800038; parameter val_debug_dap_rom__ROMENTRY14 = 32'h00000000; parameter mask_debug_dap_rom__ROMENTRY14 = 32'hFFFFFFFF; parameter debug_dap_rom__ROMENTRY15 = 32'hF880003C; parameter val_debug_dap_rom__ROMENTRY15 = 32'h00000000; parameter mask_debug_dap_rom__ROMENTRY15 = 32'hFFFFFFFF; parameter debug_dap_rom__PERIPHID4 = 32'hF8800FD0; parameter val_debug_dap_rom__PERIPHID4 = 32'h00000003; parameter mask_debug_dap_rom__PERIPHID4 = 32'h000000FF; parameter debug_dap_rom__PERIPHID5 = 32'hF8800FD4; parameter val_debug_dap_rom__PERIPHID5 = 32'h00000000; parameter mask_debug_dap_rom__PERIPHID5 = 32'h000000FF; parameter debug_dap_rom__PERIPHID6 = 32'hF8800FD8; parameter val_debug_dap_rom__PERIPHID6 = 32'h00000000; parameter mask_debug_dap_rom__PERIPHID6 = 32'h000000FF; parameter debug_dap_rom__PERIPHID7 = 32'hF8800FDC; parameter val_debug_dap_rom__PERIPHID7 = 32'h00000000; parameter mask_debug_dap_rom__PERIPHID7 = 32'h000000FF; parameter debug_dap_rom__PERIPHID0 = 32'hF8800FE0; parameter val_debug_dap_rom__PERIPHID0 = 32'h000000B2; parameter mask_debug_dap_rom__PERIPHID0 = 32'h000000FF; parameter debug_dap_rom__PERIPHID1 = 32'hF8800FE4; parameter val_debug_dap_rom__PERIPHID1 = 32'h00000093; parameter mask_debug_dap_rom__PERIPHID1 = 32'h000000FF; parameter debug_dap_rom__PERIPHID2 = 32'hF8800FE8; parameter val_debug_dap_rom__PERIPHID2 = 32'h00000008; parameter mask_debug_dap_rom__PERIPHID2 = 32'h000000FF; parameter debug_dap_rom__PERIPHID3 = 32'hF8800FEC; parameter val_debug_dap_rom__PERIPHID3 = 32'h00000000; parameter mask_debug_dap_rom__PERIPHID3 = 32'h000000FF; parameter debug_dap_rom__COMPID0 = 32'hF8800FF0; parameter val_debug_dap_rom__COMPID0 = 32'h0000000D; parameter mask_debug_dap_rom__COMPID0 = 32'h000000FF; parameter debug_dap_rom__COMPID1 = 32'hF8800FF4; parameter val_debug_dap_rom__COMPID1 = 32'h00000010; parameter mask_debug_dap_rom__COMPID1 = 32'h000000FF; parameter debug_dap_rom__COMPID2 = 32'hF8800FF8; parameter val_debug_dap_rom__COMPID2 = 32'h00000005; parameter mask_debug_dap_rom__COMPID2 = 32'h000000FF; parameter debug_dap_rom__COMPID3 = 32'hF8800FFC; parameter val_debug_dap_rom__COMPID3 = 32'h000000B1; parameter mask_debug_dap_rom__COMPID3 = 32'h000000FF; // ************************************************************ // Module debug_etb etb // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter debug_etb__RDP = 32'hF8801004; parameter val_debug_etb__RDP = 32'h00000400; parameter mask_debug_etb__RDP = 32'hFFFFFFFF; parameter debug_etb__STS = 32'hF880100C; parameter val_debug_etb__STS = 32'h00000000; parameter mask_debug_etb__STS = 32'h0000000F; parameter debug_etb__RRD = 32'hF8801010; parameter val_debug_etb__RRD = 32'h00000000; parameter mask_debug_etb__RRD = 32'hFFFFFFFF; parameter debug_etb__RRP = 32'hF8801014; parameter val_debug_etb__RRP = 32'h00000000; parameter mask_debug_etb__RRP = 32'h000003FF; parameter debug_etb__RWP = 32'hF8801018; parameter val_debug_etb__RWP = 32'h00000000; parameter mask_debug_etb__RWP = 32'h000003FF; parameter debug_etb__TRG = 32'hF880101C; parameter val_debug_etb__TRG = 32'h00000000; parameter mask_debug_etb__TRG = 32'h000003FF; parameter debug_etb__CTL = 32'hF8801020; parameter val_debug_etb__CTL = 32'h00000000; parameter mask_debug_etb__CTL = 32'h00000001; parameter debug_etb__RWD = 32'hF8801024; parameter val_debug_etb__RWD = 32'h00000000; parameter mask_debug_etb__RWD = 32'hFFFFFFFF; parameter debug_etb__FFSR = 32'hF8801300; parameter val_debug_etb__FFSR = 32'h00000000; parameter mask_debug_etb__FFSR = 32'h00000003; parameter debug_etb__FFCR = 32'hF8801304; parameter val_debug_etb__FFCR = 32'h00000200; parameter mask_debug_etb__FFCR = 32'h00003FFF; parameter debug_etb__ITMISCOP0 = 32'hF8801EE0; parameter val_debug_etb__ITMISCOP0 = 32'h00000000; parameter mask_debug_etb__ITMISCOP0 = 32'h00000003; parameter debug_etb__ITTRFLINACK = 32'hF8801EE4; parameter val_debug_etb__ITTRFLINACK = 32'h00000000; parameter mask_debug_etb__ITTRFLINACK = 32'h00000003; parameter debug_etb__ITTRFLIN = 32'hF8801EE8; parameter val_debug_etb__ITTRFLIN = 32'h00000000; parameter mask_debug_etb__ITTRFLIN = 32'h00000003; parameter debug_etb__ITATBDATA0 = 32'hF8801EEC; parameter val_debug_etb__ITATBDATA0 = 32'h00000000; parameter mask_debug_etb__ITATBDATA0 = 32'h0000001F; parameter debug_etb__ITATBCTR2 = 32'hF8801EF0; parameter val_debug_etb__ITATBCTR2 = 32'h00000000; parameter mask_debug_etb__ITATBCTR2 = 32'h00000003; parameter debug_etb__ITATBCTR1 = 32'hF8801EF4; parameter val_debug_etb__ITATBCTR1 = 32'h00000000; parameter mask_debug_etb__ITATBCTR1 = 32'h0000007F; parameter debug_etb__ITATBCTR0 = 32'hF8801EF8; parameter val_debug_etb__ITATBCTR0 = 32'h00000000; parameter mask_debug_etb__ITATBCTR0 = 32'h000003FF; parameter debug_etb__IMCR = 32'hF8801F00; parameter val_debug_etb__IMCR = 32'h00000000; parameter mask_debug_etb__IMCR = 32'h00000001; parameter debug_etb__CTSR = 32'hF8801FA0; parameter val_debug_etb__CTSR = 32'h0000000F; parameter mask_debug_etb__CTSR = 32'h0000000F; parameter debug_etb__CTCR = 32'hF8801FA4; parameter val_debug_etb__CTCR = 32'h00000000; parameter mask_debug_etb__CTCR = 32'h0000000F; parameter debug_etb__LAR = 32'hF8801FB0; parameter val_debug_etb__LAR = 32'h00000000; parameter mask_debug_etb__LAR = 32'hFFFFFFFF; parameter debug_etb__LSR = 32'hF8801FB4; parameter val_debug_etb__LSR = 32'h00000003; parameter mask_debug_etb__LSR = 32'h00000007; parameter debug_etb__ASR = 32'hF8801FB8; parameter val_debug_etb__ASR = 32'h00000000; parameter mask_debug_etb__ASR = 32'h000000FF; parameter debug_etb__DEVID = 32'hF8801FC8; parameter val_debug_etb__DEVID = 32'h00000000; parameter mask_debug_etb__DEVID = 32'h0000003F; parameter debug_etb__DTIR = 32'hF8801FCC; parameter val_debug_etb__DTIR = 32'h00000021; parameter mask_debug_etb__DTIR = 32'h000000FF; parameter debug_etb__PERIPHID4 = 32'hF8801FD0; parameter val_debug_etb__PERIPHID4 = 32'h00000004; parameter mask_debug_etb__PERIPHID4 = 32'h000000FF; parameter debug_etb__PERIPHID5 = 32'hF8801FD4; parameter val_debug_etb__PERIPHID5 = 32'h00000000; parameter mask_debug_etb__PERIPHID5 = 32'h000000FF; parameter debug_etb__PERIPHID6 = 32'hF8801FD8; parameter val_debug_etb__PERIPHID6 = 32'h00000000; parameter mask_debug_etb__PERIPHID6 = 32'h000000FF; parameter debug_etb__PERIPHID7 = 32'hF8801FDC; parameter val_debug_etb__PERIPHID7 = 32'h00000000; parameter mask_debug_etb__PERIPHID7 = 32'h000000FF; parameter debug_etb__PERIPHID0 = 32'hF8801FE0; parameter val_debug_etb__PERIPHID0 = 32'h00000007; parameter mask_debug_etb__PERIPHID0 = 32'h000000FF; parameter debug_etb__PERIPHID1 = 32'hF8801FE4; parameter val_debug_etb__PERIPHID1 = 32'h000000B9; parameter mask_debug_etb__PERIPHID1 = 32'h000000FF; parameter debug_etb__PERIPHID2 = 32'hF8801FE8; parameter val_debug_etb__PERIPHID2 = 32'h0000002B; parameter mask_debug_etb__PERIPHID2 = 32'h000000FF; parameter debug_etb__PERIPHID3 = 32'hF8801FEC; parameter val_debug_etb__PERIPHID3 = 32'h00000000; parameter mask_debug_etb__PERIPHID3 = 32'h000000FF; parameter debug_etb__COMPID0 = 32'hF8801FF0; parameter val_debug_etb__COMPID0 = 32'h0000000D; parameter mask_debug_etb__COMPID0 = 32'h000000FF; parameter debug_etb__COMPID1 = 32'hF8801FF4; parameter val_debug_etb__COMPID1 = 32'h00000090; parameter mask_debug_etb__COMPID1 = 32'h000000FF; parameter debug_etb__COMPID2 = 32'hF8801FF8; parameter val_debug_etb__COMPID2 = 32'h00000005; parameter mask_debug_etb__COMPID2 = 32'h000000FF; parameter debug_etb__COMPID3 = 32'hF8801FFC; parameter val_debug_etb__COMPID3 = 32'h000000B1; parameter mask_debug_etb__COMPID3 = 32'h000000FF; // ************************************************************ // Module debug_ftm ftm // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter debug_ftm__FTMGLBCTRL = 32'hF880B000; parameter val_debug_ftm__FTMGLBCTRL = 32'h00000000; parameter mask_debug_ftm__FTMGLBCTRL = 32'h00000001; parameter debug_ftm__FTMSTATUS = 32'hF880B004; parameter val_debug_ftm__FTMSTATUS = 32'h00000082; parameter mask_debug_ftm__FTMSTATUS = 32'h000000FF; parameter debug_ftm__FTMCONTROL = 32'hF880B008; parameter val_debug_ftm__FTMCONTROL = 32'h00000000; parameter mask_debug_ftm__FTMCONTROL = 32'h00000007; parameter debug_ftm__FTMP2FDBG0 = 32'hF880B00C; parameter val_debug_ftm__FTMP2FDBG0 = 32'h00000000; parameter mask_debug_ftm__FTMP2FDBG0 = 32'h000000FF; parameter debug_ftm__FTMP2FDBG1 = 32'hF880B010; parameter val_debug_ftm__FTMP2FDBG1 = 32'h00000000; parameter mask_debug_ftm__FTMP2FDBG1 = 32'h000000FF; parameter debug_ftm__FTMP2FDBG2 = 32'hF880B014; parameter val_debug_ftm__FTMP2FDBG2 = 32'h00000000; parameter mask_debug_ftm__FTMP2FDBG2 = 32'h000000FF; parameter debug_ftm__FTMP2FDBG3 = 32'hF880B018; parameter val_debug_ftm__FTMP2FDBG3 = 32'h00000000; parameter mask_debug_ftm__FTMP2FDBG3 = 32'h000000FF; parameter debug_ftm__FTMF2PDBG0 = 32'hF880B01C; parameter val_debug_ftm__FTMF2PDBG0 = 32'h00000000; parameter mask_debug_ftm__FTMF2PDBG0 = 32'h000000FF; parameter debug_ftm__FTMF2PDBG1 = 32'hF880B020; parameter val_debug_ftm__FTMF2PDBG1 = 32'h00000000; parameter mask_debug_ftm__FTMF2PDBG1 = 32'h000000FF; parameter debug_ftm__FTMF2PDBG2 = 32'hF880B024; parameter val_debug_ftm__FTMF2PDBG2 = 32'h00000000; parameter mask_debug_ftm__FTMF2PDBG2 = 32'h000000FF; parameter debug_ftm__FTMF2PDBG3 = 32'hF880B028; parameter val_debug_ftm__FTMF2PDBG3 = 32'h00000000; parameter mask_debug_ftm__FTMF2PDBG3 = 32'h000000FF; parameter debug_ftm__CYCOUNTPRE = 32'hF880B02C; parameter val_debug_ftm__CYCOUNTPRE = 32'h00000000; parameter mask_debug_ftm__CYCOUNTPRE = 32'h0000000F; parameter debug_ftm__FTMSYNCRELOAD = 32'hF880B030; parameter val_debug_ftm__FTMSYNCRELOAD = 32'h00000000; parameter mask_debug_ftm__FTMSYNCRELOAD = 32'h00000FFF; parameter debug_ftm__FTMSYNCCOUT = 32'hF880B034; parameter val_debug_ftm__FTMSYNCCOUT = 32'h00000000; parameter mask_debug_ftm__FTMSYNCCOUT = 32'h00000FFF; parameter debug_ftm__FTMATID = 32'hF880B400; parameter val_debug_ftm__FTMATID = 32'h00000000; parameter mask_debug_ftm__FTMATID = 32'h0000007F; parameter debug_ftm__FTMITTRIGOUTACK = 32'hF880BED0; parameter val_debug_ftm__FTMITTRIGOUTACK = 32'h00000000; parameter mask_debug_ftm__FTMITTRIGOUTACK = 32'h0000000F; parameter debug_ftm__FTMITTRIGGER = 32'hF880BED4; parameter val_debug_ftm__FTMITTRIGGER = 32'h00000000; parameter mask_debug_ftm__FTMITTRIGGER = 32'h0000000F; parameter debug_ftm__FTMITTRACEDIS = 32'hF880BED8; parameter val_debug_ftm__FTMITTRACEDIS = 32'h00000000; parameter mask_debug_ftm__FTMITTRACEDIS = 32'h00000001; parameter debug_ftm__FTMITCYCCOUNT = 32'hF880BEDC; parameter val_debug_ftm__FTMITCYCCOUNT = 32'h00000001; parameter mask_debug_ftm__FTMITCYCCOUNT = 32'hFFFFFFFF; parameter debug_ftm__FTMITATBDATA0 = 32'hF880BEEC; parameter val_debug_ftm__FTMITATBDATA0 = 32'h00000000; parameter mask_debug_ftm__FTMITATBDATA0 = 32'h0000001F; parameter debug_ftm__FTMITATBCTR2 = 32'hF880BEF0; parameter val_debug_ftm__FTMITATBCTR2 = 32'h00000001; parameter mask_debug_ftm__FTMITATBCTR2 = 32'h00000003; parameter debug_ftm__FTMITATBCTR1 = 32'hF880BEF4; parameter val_debug_ftm__FTMITATBCTR1 = 32'h00000000; parameter mask_debug_ftm__FTMITATBCTR1 = 32'h0000007F; parameter debug_ftm__FTMITATBCTR0 = 32'hF880BEF8; parameter val_debug_ftm__FTMITATBCTR0 = 32'h00000000; parameter mask_debug_ftm__FTMITATBCTR0 = 32'h000003FF; parameter debug_ftm__FTMITCR = 32'hF880BF00; parameter val_debug_ftm__FTMITCR = 32'h00000000; parameter mask_debug_ftm__FTMITCR = 32'h00000001; parameter debug_ftm__CLAIMTAGSET = 32'hF880BFA0; parameter val_debug_ftm__CLAIMTAGSET = 32'h000000FF; parameter mask_debug_ftm__CLAIMTAGSET = 32'h000000FF; parameter debug_ftm__CLAIMTAGCLR = 32'hF880BFA4; parameter val_debug_ftm__CLAIMTAGCLR = 32'h000000FF; parameter mask_debug_ftm__CLAIMTAGCLR = 32'h000000FF; parameter debug_ftm__LOCK_ACCESS = 32'hF880BFB0; parameter val_debug_ftm__LOCK_ACCESS = 32'h00000000; parameter mask_debug_ftm__LOCK_ACCESS = 32'hFFFFFFFF; parameter debug_ftm__LOCK_STATUS = 32'hF880BFB4; parameter val_debug_ftm__LOCK_STATUS = 32'h00000003; parameter mask_debug_ftm__LOCK_STATUS = 32'h00000007; parameter debug_ftm__FTMAUTHSTATUS = 32'hF880BFB8; parameter val_debug_ftm__FTMAUTHSTATUS = 32'h00000088; parameter mask_debug_ftm__FTMAUTHSTATUS = 32'h000000FF; parameter debug_ftm__FTMDEVID = 32'hF880BFC8; parameter val_debug_ftm__FTMDEVID = 32'h00000000; parameter mask_debug_ftm__FTMDEVID = 32'h00000001; parameter debug_ftm__FTMDEV_TYPE = 32'hF880BFCC; parameter val_debug_ftm__FTMDEV_TYPE = 32'h00000033; parameter mask_debug_ftm__FTMDEV_TYPE = 32'h000000FF; parameter debug_ftm__FTMPERIPHID4 = 32'hF880BFD0; parameter val_debug_ftm__FTMPERIPHID4 = 32'h00000000; parameter mask_debug_ftm__FTMPERIPHID4 = 32'h000000FF; parameter debug_ftm__FTMPERIPHID5 = 32'hF880BFD4; parameter val_debug_ftm__FTMPERIPHID5 = 32'h00000000; parameter mask_debug_ftm__FTMPERIPHID5 = 32'h000000FF; parameter debug_ftm__FTMPERIPHID6 = 32'hF880BFD8; parameter val_debug_ftm__FTMPERIPHID6 = 32'h00000000; parameter mask_debug_ftm__FTMPERIPHID6 = 32'h000000FF; parameter debug_ftm__FTMPERIPHID7 = 32'hF880BFDC; parameter val_debug_ftm__FTMPERIPHID7 = 32'h00000000; parameter mask_debug_ftm__FTMPERIPHID7 = 32'h000000FF; parameter debug_ftm__FTMPERIPHID0 = 32'hF880BFE0; parameter val_debug_ftm__FTMPERIPHID0 = 32'h00000001; parameter mask_debug_ftm__FTMPERIPHID0 = 32'h000000FF; parameter debug_ftm__FTMPERIPHID1 = 32'hF880BFE4; parameter val_debug_ftm__FTMPERIPHID1 = 32'h00000090; parameter mask_debug_ftm__FTMPERIPHID1 = 32'h000000FF; parameter debug_ftm__FTMPERIPHID2 = 32'hF880BFE8; parameter val_debug_ftm__FTMPERIPHID2 = 32'h0000000C; parameter mask_debug_ftm__FTMPERIPHID2 = 32'h000000FF; parameter debug_ftm__FTMPERIPHID3 = 32'hF880BFEC; parameter val_debug_ftm__FTMPERIPHID3 = 32'h00000000; parameter mask_debug_ftm__FTMPERIPHID3 = 32'h000000FF; parameter debug_ftm__FTMCOMPONID0 = 32'hF880BFF0; parameter val_debug_ftm__FTMCOMPONID0 = 32'h0000000D; parameter mask_debug_ftm__FTMCOMPONID0 = 32'h000000FF; parameter debug_ftm__FTMCOMPONID1 = 32'hF880BFF4; parameter val_debug_ftm__FTMCOMPONID1 = 32'h00000090; parameter mask_debug_ftm__FTMCOMPONID1 = 32'h000000FF; parameter debug_ftm__FTMCOMPONID2 = 32'hF880BFF8; parameter val_debug_ftm__FTMCOMPONID2 = 32'h00000005; parameter mask_debug_ftm__FTMCOMPONID2 = 32'h000000FF; parameter debug_ftm__FTMCOMPONID3 = 32'hF880BFFC; parameter val_debug_ftm__FTMCOMPONID3 = 32'h000000B1; parameter mask_debug_ftm__FTMCOMPONID3 = 32'h000000FF; // ************************************************************ // Module debug_funnel funnel // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter debug_funnel__Control = 32'hF8804000; parameter val_debug_funnel__Control = 32'h00000300; parameter mask_debug_funnel__Control = 32'h00000FFF; parameter debug_funnel__PriControl = 32'hF8804004; parameter val_debug_funnel__PriControl = 32'h00FAC688; parameter mask_debug_funnel__PriControl = 32'h00FFFFFF; parameter debug_funnel__ITATBDATA0 = 32'hF8804EEC; parameter val_debug_funnel__ITATBDATA0 = 32'h00000000; parameter mask_debug_funnel__ITATBDATA0 = 32'h0000001F; parameter debug_funnel__ITATBCTR2 = 32'hF8804EF0; parameter val_debug_funnel__ITATBCTR2 = 32'h00000000; parameter mask_debug_funnel__ITATBCTR2 = 32'h00000003; parameter debug_funnel__ITATBCTR1 = 32'hF8804EF4; parameter val_debug_funnel__ITATBCTR1 = 32'h00000000; parameter mask_debug_funnel__ITATBCTR1 = 32'h0000007F; parameter debug_funnel__ITATBCTR0 = 32'hF8804EF8; parameter val_debug_funnel__ITATBCTR0 = 32'h00000000; parameter mask_debug_funnel__ITATBCTR0 = 32'h000003FF; parameter debug_funnel__IMCR = 32'hF8804F00; parameter val_debug_funnel__IMCR = 32'h00000000; parameter mask_debug_funnel__IMCR = 32'h00000001; parameter debug_funnel__CTSR = 32'hF8804FA0; parameter val_debug_funnel__CTSR = 32'h0000000F; parameter mask_debug_funnel__CTSR = 32'h0000000F; parameter debug_funnel__CTCR = 32'hF8804FA4; parameter val_debug_funnel__CTCR = 32'h00000000; parameter mask_debug_funnel__CTCR = 32'h0000000F; parameter debug_funnel__LAR = 32'hF8804FB0; parameter val_debug_funnel__LAR = 32'h00000000; parameter mask_debug_funnel__LAR = 32'hFFFFFFFF; parameter debug_funnel__LSR = 32'hF8804FB4; parameter val_debug_funnel__LSR = 32'h00000003; parameter mask_debug_funnel__LSR = 32'h00000007; parameter debug_funnel__ASR = 32'hF8804FB8; parameter val_debug_funnel__ASR = 32'h00000000; parameter mask_debug_funnel__ASR = 32'h000000FF; parameter debug_funnel__DEVID = 32'hF8804FC8; parameter val_debug_funnel__DEVID = 32'h00000028; parameter mask_debug_funnel__DEVID = 32'h000000FF; parameter debug_funnel__DTIR = 32'hF8804FCC; parameter val_debug_funnel__DTIR = 32'h00000012; parameter mask_debug_funnel__DTIR = 32'h000000FF; parameter debug_funnel__PERIPHID4 = 32'hF8804FD0; parameter val_debug_funnel__PERIPHID4 = 32'h00000004; parameter mask_debug_funnel__PERIPHID4 = 32'h000000FF; parameter debug_funnel__PERIPHID5 = 32'hF8804FD4; parameter val_debug_funnel__PERIPHID5 = 32'h00000000; parameter mask_debug_funnel__PERIPHID5 = 32'h000000FF; parameter debug_funnel__PERIPHID6 = 32'hF8804FD8; parameter val_debug_funnel__PERIPHID6 = 32'h00000000; parameter mask_debug_funnel__PERIPHID6 = 32'h000000FF; parameter debug_funnel__PERIPHID7 = 32'hF8804FDC; parameter val_debug_funnel__PERIPHID7 = 32'h00000000; parameter mask_debug_funnel__PERIPHID7 = 32'h000000FF; parameter debug_funnel__PERIPHID0 = 32'hF8804FE0; parameter val_debug_funnel__PERIPHID0 = 32'h00000008; parameter mask_debug_funnel__PERIPHID0 = 32'h000000FF; parameter debug_funnel__PERIPHID1 = 32'hF8804FE4; parameter val_debug_funnel__PERIPHID1 = 32'h000000B9; parameter mask_debug_funnel__PERIPHID1 = 32'h000000FF; parameter debug_funnel__PERIPHID2 = 32'hF8804FE8; parameter val_debug_funnel__PERIPHID2 = 32'h0000001B; parameter mask_debug_funnel__PERIPHID2 = 32'h000000FF; parameter debug_funnel__PERIPHID3 = 32'hF8804FEC; parameter val_debug_funnel__PERIPHID3 = 32'h00000000; parameter mask_debug_funnel__PERIPHID3 = 32'h000000FF; parameter debug_funnel__COMPID0 = 32'hF8804FF0; parameter val_debug_funnel__COMPID0 = 32'h0000000D; parameter mask_debug_funnel__COMPID0 = 32'h000000FF; parameter debug_funnel__COMPID1 = 32'hF8804FF4; parameter val_debug_funnel__COMPID1 = 32'h00000090; parameter mask_debug_funnel__COMPID1 = 32'h000000FF; parameter debug_funnel__COMPID2 = 32'hF8804FF8; parameter val_debug_funnel__COMPID2 = 32'h00000005; parameter mask_debug_funnel__COMPID2 = 32'h000000FF; parameter debug_funnel__COMPID3 = 32'hF8804FFC; parameter val_debug_funnel__COMPID3 = 32'h000000B1; parameter mask_debug_funnel__COMPID3 = 32'h000000FF; // ************************************************************ // Module debug_itm itm // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter debug_itm__StimPort00 = 32'hF8805000; parameter val_debug_itm__StimPort00 = 32'h00000000; parameter mask_debug_itm__StimPort00 = 32'hFFFFFFFF; parameter debug_itm__StimPort01 = 32'hF8805004; parameter val_debug_itm__StimPort01 = 32'h00000000; parameter mask_debug_itm__StimPort01 = 32'hFFFFFFFF; parameter debug_itm__StimPort02 = 32'hF8805008; parameter val_debug_itm__StimPort02 = 32'h00000000; parameter mask_debug_itm__StimPort02 = 32'hFFFFFFFF; parameter debug_itm__StimPort03 = 32'hF880500C; parameter val_debug_itm__StimPort03 = 32'h00000000; parameter mask_debug_itm__StimPort03 = 32'hFFFFFFFF; parameter debug_itm__StimPort04 = 32'hF8805010; parameter val_debug_itm__StimPort04 = 32'h00000000; parameter mask_debug_itm__StimPort04 = 32'hFFFFFFFF; parameter debug_itm__StimPort05 = 32'hF8805014; parameter val_debug_itm__StimPort05 = 32'h00000000; parameter mask_debug_itm__StimPort05 = 32'hFFFFFFFF; parameter debug_itm__StimPort06 = 32'hF8805018; parameter val_debug_itm__StimPort06 = 32'h00000000; parameter mask_debug_itm__StimPort06 = 32'hFFFFFFFF; parameter debug_itm__StimPort07 = 32'hF880501C; parameter val_debug_itm__StimPort07 = 32'h00000000; parameter mask_debug_itm__StimPort07 = 32'hFFFFFFFF; parameter debug_itm__StimPort08 = 32'hF8805020; parameter val_debug_itm__StimPort08 = 32'h00000000; parameter mask_debug_itm__StimPort08 = 32'hFFFFFFFF; parameter debug_itm__StimPort09 = 32'hF8805024; parameter val_debug_itm__StimPort09 = 32'h00000000; parameter mask_debug_itm__StimPort09 = 32'hFFFFFFFF; parameter debug_itm__StimPort10 = 32'hF8805028; parameter val_debug_itm__StimPort10 = 32'h00000000; parameter mask_debug_itm__StimPort10 = 32'hFFFFFFFF; parameter debug_itm__StimPort11 = 32'hF880502C; parameter val_debug_itm__StimPort11 = 32'h00000000; parameter mask_debug_itm__StimPort11 = 32'hFFFFFFFF; parameter debug_itm__StimPort12 = 32'hF8805030; parameter val_debug_itm__StimPort12 = 32'h00000000; parameter mask_debug_itm__StimPort12 = 32'hFFFFFFFF; parameter debug_itm__StimPort13 = 32'hF8805034; parameter val_debug_itm__StimPort13 = 32'h00000000; parameter mask_debug_itm__StimPort13 = 32'hFFFFFFFF; parameter debug_itm__StimPort14 = 32'hF8805038; parameter val_debug_itm__StimPort14 = 32'h00000000; parameter mask_debug_itm__StimPort14 = 32'hFFFFFFFF; parameter debug_itm__StimPort15 = 32'hF880503C; parameter val_debug_itm__StimPort15 = 32'h00000000; parameter mask_debug_itm__StimPort15 = 32'hFFFFFFFF; parameter debug_itm__StimPort16 = 32'hF8805040; parameter val_debug_itm__StimPort16 = 32'h00000000; parameter mask_debug_itm__StimPort16 = 32'hFFFFFFFF; parameter debug_itm__StimPort17 = 32'hF8805044; parameter val_debug_itm__StimPort17 = 32'h00000000; parameter mask_debug_itm__StimPort17 = 32'hFFFFFFFF; parameter debug_itm__StimPort18 = 32'hF8805048; parameter val_debug_itm__StimPort18 = 32'h00000000; parameter mask_debug_itm__StimPort18 = 32'hFFFFFFFF; parameter debug_itm__StimPort19 = 32'hF880504C; parameter val_debug_itm__StimPort19 = 32'h00000000; parameter mask_debug_itm__StimPort19 = 32'hFFFFFFFF; parameter debug_itm__StimPort20 = 32'hF8805050; parameter val_debug_itm__StimPort20 = 32'h00000000; parameter mask_debug_itm__StimPort20 = 32'hFFFFFFFF; parameter debug_itm__StimPort21 = 32'hF8805054; parameter val_debug_itm__StimPort21 = 32'h00000000; parameter mask_debug_itm__StimPort21 = 32'hFFFFFFFF; parameter debug_itm__StimPort22 = 32'hF8805058; parameter val_debug_itm__StimPort22 = 32'h00000000; parameter mask_debug_itm__StimPort22 = 32'hFFFFFFFF; parameter debug_itm__StimPort23 = 32'hF880505C; parameter val_debug_itm__StimPort23 = 32'h00000000; parameter mask_debug_itm__StimPort23 = 32'hFFFFFFFF; parameter debug_itm__StimPort24 = 32'hF8805060; parameter val_debug_itm__StimPort24 = 32'h00000000; parameter mask_debug_itm__StimPort24 = 32'hFFFFFFFF; parameter debug_itm__StimPort25 = 32'hF8805064; parameter val_debug_itm__StimPort25 = 32'h00000000; parameter mask_debug_itm__StimPort25 = 32'hFFFFFFFF; parameter debug_itm__StimPort26 = 32'hF8805068; parameter val_debug_itm__StimPort26 = 32'h00000000; parameter mask_debug_itm__StimPort26 = 32'hFFFFFFFF; parameter debug_itm__StimPort27 = 32'hF880506C; parameter val_debug_itm__StimPort27 = 32'h00000000; parameter mask_debug_itm__StimPort27 = 32'hFFFFFFFF; parameter debug_itm__StimPort28 = 32'hF8805070; parameter val_debug_itm__StimPort28 = 32'h00000000; parameter mask_debug_itm__StimPort28 = 32'hFFFFFFFF; parameter debug_itm__StimPort29 = 32'hF8805074; parameter val_debug_itm__StimPort29 = 32'h00000000; parameter mask_debug_itm__StimPort29 = 32'hFFFFFFFF; parameter debug_itm__StimPort30 = 32'hF8805078; parameter val_debug_itm__StimPort30 = 32'h00000000; parameter mask_debug_itm__StimPort30 = 32'hFFFFFFFF; parameter debug_itm__StimPort31 = 32'hF880507C; parameter val_debug_itm__StimPort31 = 32'h00000000; parameter mask_debug_itm__StimPort31 = 32'hFFFFFFFF; parameter debug_itm__TER = 32'hF8805E00; parameter val_debug_itm__TER = 32'h00000000; parameter mask_debug_itm__TER = 32'hFFFFFFFF; parameter debug_itm__TTR = 32'hF8805E20; parameter val_debug_itm__TTR = 32'h00000000; parameter mask_debug_itm__TTR = 32'hFFFFFFFF; parameter debug_itm__CR = 32'hF8805E80; parameter val_debug_itm__CR = 32'h00000004; parameter mask_debug_itm__CR = 32'h00FFFFFF; parameter debug_itm__SCR = 32'hF8805E90; parameter val_debug_itm__SCR = 32'h00000400; parameter mask_debug_itm__SCR = 32'h00000FFF; parameter debug_itm__ITTRIGOUTACK = 32'hF8805EE4; parameter val_debug_itm__ITTRIGOUTACK = 32'h00000000; parameter mask_debug_itm__ITTRIGOUTACK = 32'h00000001; parameter debug_itm__ITTRIGOUT = 32'hF8805EE8; parameter val_debug_itm__ITTRIGOUT = 32'h00000000; parameter mask_debug_itm__ITTRIGOUT = 32'h00000001; parameter debug_itm__ITATBDATA0 = 32'hF8805EEC; parameter val_debug_itm__ITATBDATA0 = 32'h00000000; parameter mask_debug_itm__ITATBDATA0 = 32'h00000003; parameter debug_itm__ITATBCTR2 = 32'hF8805EF0; parameter val_debug_itm__ITATBCTR2 = 32'h00000001; parameter mask_debug_itm__ITATBCTR2 = 32'h00000001; parameter debug_itm__ITATABCTR1 = 32'hF8805EF4; parameter val_debug_itm__ITATABCTR1 = 32'h00000000; parameter mask_debug_itm__ITATABCTR1 = 32'h0000007F; parameter debug_itm__ITATBCTR0 = 32'hF8805EF8; parameter val_debug_itm__ITATBCTR0 = 32'h00000000; parameter mask_debug_itm__ITATBCTR0 = 32'h00000003; parameter debug_itm__IMCR = 32'hF8805F00; parameter val_debug_itm__IMCR = 32'h00000000; parameter mask_debug_itm__IMCR = 32'h00000001; parameter debug_itm__CTSR = 32'hF8805FA0; parameter val_debug_itm__CTSR = 32'h000000FF; parameter mask_debug_itm__CTSR = 32'h000000FF; parameter debug_itm__CTCR = 32'hF8805FA4; parameter val_debug_itm__CTCR = 32'h00000000; parameter mask_debug_itm__CTCR = 32'h000000FF; parameter debug_itm__LAR = 32'hF8805FB0; parameter val_debug_itm__LAR = 32'h00000000; parameter mask_debug_itm__LAR = 32'hFFFFFFFF; parameter debug_itm__LSR = 32'hF8805FB4; parameter val_debug_itm__LSR = 32'h00000003; parameter mask_debug_itm__LSR = 32'h00000007; parameter debug_itm__ASR = 32'hF8805FB8; parameter val_debug_itm__ASR = 32'h00000088; parameter mask_debug_itm__ASR = 32'h000000FF; parameter debug_itm__DEVID = 32'hF8805FC8; parameter val_debug_itm__DEVID = 32'h00000020; parameter mask_debug_itm__DEVID = 32'h00001FFF; parameter debug_itm__DTIR = 32'hF8805FCC; parameter val_debug_itm__DTIR = 32'h00000043; parameter mask_debug_itm__DTIR = 32'h000000FF; parameter debug_itm__PERIPHID4 = 32'hF8805FD0; parameter val_debug_itm__PERIPHID4 = 32'h00000004; parameter mask_debug_itm__PERIPHID4 = 32'h000000FF; parameter debug_itm__PERIPHID5 = 32'hF8805FD4; parameter val_debug_itm__PERIPHID5 = 32'h00000000; parameter mask_debug_itm__PERIPHID5 = 32'h000000FF; parameter debug_itm__PERIPHID6 = 32'hF8805FD8; parameter val_debug_itm__PERIPHID6 = 32'h00000000; parameter mask_debug_itm__PERIPHID6 = 32'h000000FF; parameter debug_itm__PERIPHID7 = 32'hF8805FDC; parameter val_debug_itm__PERIPHID7 = 32'h00000000; parameter mask_debug_itm__PERIPHID7 = 32'h000000FF; parameter debug_itm__PERIPHID0 = 32'hF8805FE0; parameter val_debug_itm__PERIPHID0 = 32'h00000013; parameter mask_debug_itm__PERIPHID0 = 32'h000000FF; parameter debug_itm__PERIPHID1 = 32'hF8805FE4; parameter val_debug_itm__PERIPHID1 = 32'h000000B9; parameter mask_debug_itm__PERIPHID1 = 32'h000000FF; parameter debug_itm__PERIPHID2 = 32'hF8805FE8; parameter val_debug_itm__PERIPHID2 = 32'h0000002B; parameter mask_debug_itm__PERIPHID2 = 32'h000000FF; parameter debug_itm__PERIPHID3 = 32'hF8805FEC; parameter val_debug_itm__PERIPHID3 = 32'h00000000; parameter mask_debug_itm__PERIPHID3 = 32'h000000FF; parameter debug_itm__COMPID0 = 32'hF8805FF0; parameter val_debug_itm__COMPID0 = 32'h0000000D; parameter mask_debug_itm__COMPID0 = 32'h000000FF; parameter debug_itm__COMPID1 = 32'hF8805FF4; parameter val_debug_itm__COMPID1 = 32'h00000090; parameter mask_debug_itm__COMPID1 = 32'h000000FF; parameter debug_itm__COMPID2 = 32'hF8805FF8; parameter val_debug_itm__COMPID2 = 32'h00000005; parameter mask_debug_itm__COMPID2 = 32'h000000FF; parameter debug_itm__COMPID3 = 32'hF8805FFC; parameter val_debug_itm__COMPID3 = 32'h000000B1; parameter mask_debug_itm__COMPID3 = 32'h000000FF; // ************************************************************ // Module debug_tpiu tpiu // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter debug_tpiu__SuppSize = 32'hF8803000; parameter val_debug_tpiu__SuppSize = 32'hFFFFFFFF; parameter mask_debug_tpiu__SuppSize = 32'hFFFFFFFF; parameter debug_tpiu__CurrentSize = 32'hF8803004; parameter val_debug_tpiu__CurrentSize = 32'h00000001; parameter mask_debug_tpiu__CurrentSize = 32'hFFFFFFFF; parameter debug_tpiu__SuppTrigMode = 32'hF8803100; parameter val_debug_tpiu__SuppTrigMode = 32'h0000011F; parameter mask_debug_tpiu__SuppTrigMode = 32'h0003FFFF; parameter debug_tpiu__TrigCount = 32'hF8803104; parameter val_debug_tpiu__TrigCount = 32'h00000000; parameter mask_debug_tpiu__TrigCount = 32'h000000FF; parameter debug_tpiu__TrigMult = 32'hF8803108; parameter val_debug_tpiu__TrigMult = 32'h00000000; parameter mask_debug_tpiu__TrigMult = 32'h0000001F; parameter debug_tpiu__SuppTest = 32'hF8803200; parameter val_debug_tpiu__SuppTest = 32'h0003000F; parameter mask_debug_tpiu__SuppTest = 32'h0003FFFF; parameter debug_tpiu__CurrentTest = 32'hF8803204; parameter val_debug_tpiu__CurrentTest = 32'h00000000; parameter mask_debug_tpiu__CurrentTest = 32'h0003FFFF; parameter debug_tpiu__TestRepeatCount = 32'hF8803208; parameter val_debug_tpiu__TestRepeatCount = 32'h00000000; parameter mask_debug_tpiu__TestRepeatCount = 32'h000000FF; parameter debug_tpiu__FFSR = 32'hF8803300; parameter val_debug_tpiu__FFSR = 32'h00000006; parameter mask_debug_tpiu__FFSR = 32'h00000007; parameter debug_tpiu__FFCR = 32'hF8803304; parameter val_debug_tpiu__FFCR = 32'h00000000; parameter mask_debug_tpiu__FFCR = 32'h00003FFF; parameter debug_tpiu__FormatSyncCount = 32'hF8803308; parameter val_debug_tpiu__FormatSyncCount = 32'h00000040; parameter mask_debug_tpiu__FormatSyncCount = 32'h00000FFF; parameter debug_tpiu__EXTCTLIn = 32'hF8803400; parameter val_debug_tpiu__EXTCTLIn = 32'h00000000; parameter mask_debug_tpiu__EXTCTLIn = 32'h000000FF; parameter debug_tpiu__EXTCTLOut = 32'hF8803404; parameter val_debug_tpiu__EXTCTLOut = 32'h00000000; parameter mask_debug_tpiu__EXTCTLOut = 32'h000000FF; parameter debug_tpiu__ITTRFLINACK = 32'hF8803EE4; parameter val_debug_tpiu__ITTRFLINACK = 32'h00000000; parameter mask_debug_tpiu__ITTRFLINACK = 32'h00000003; parameter debug_tpiu__ITTRFLIN = 32'hF8803EE8; parameter val_debug_tpiu__ITTRFLIN = 32'h00000000; parameter mask_debug_tpiu__ITTRFLIN = 32'h00000000; parameter debug_tpiu__ITATBDATA0 = 32'hF8803EEC; parameter val_debug_tpiu__ITATBDATA0 = 32'h00000000; parameter mask_debug_tpiu__ITATBDATA0 = 32'h00000000; parameter debug_tpiu__ITATBCTR2 = 32'hF8803EF0; parameter val_debug_tpiu__ITATBCTR2 = 32'h00000000; parameter mask_debug_tpiu__ITATBCTR2 = 32'h00000003; parameter debug_tpiu__ITATBCTR1 = 32'hF8803EF4; parameter val_debug_tpiu__ITATBCTR1 = 32'h00000000; parameter mask_debug_tpiu__ITATBCTR1 = 32'h00000000; parameter debug_tpiu__ITATBCTR0 = 32'hF8803EF8; parameter val_debug_tpiu__ITATBCTR0 = 32'h00000000; parameter mask_debug_tpiu__ITATBCTR0 = 32'h00000000; parameter debug_tpiu__IMCR = 32'hF8803F00; parameter val_debug_tpiu__IMCR = 32'h00000000; parameter mask_debug_tpiu__IMCR = 32'h00000001; parameter debug_tpiu__CTSR = 32'hF8803FA0; parameter val_debug_tpiu__CTSR = 32'h0000000F; parameter mask_debug_tpiu__CTSR = 32'h0000000F; parameter debug_tpiu__CTCR = 32'hF8803FA4; parameter val_debug_tpiu__CTCR = 32'h00000000; parameter mask_debug_tpiu__CTCR = 32'h0000000F; parameter debug_tpiu__LAR = 32'hF8803FB0; parameter val_debug_tpiu__LAR = 32'h00000000; parameter mask_debug_tpiu__LAR = 32'hFFFFFFFF; parameter debug_tpiu__LSR = 32'hF8803FB4; parameter val_debug_tpiu__LSR = 32'h00000003; parameter mask_debug_tpiu__LSR = 32'h00000007; parameter debug_tpiu__ASR = 32'hF8803FB8; parameter val_debug_tpiu__ASR = 32'h00000000; parameter mask_debug_tpiu__ASR = 32'h000000FF; parameter debug_tpiu__DEVID = 32'hF8803FC8; parameter val_debug_tpiu__DEVID = 32'h000000A0; parameter mask_debug_tpiu__DEVID = 32'h00000FFF; parameter debug_tpiu__DTIR = 32'hF8803FCC; parameter val_debug_tpiu__DTIR = 32'h00000011; parameter mask_debug_tpiu__DTIR = 32'h000000FF; parameter debug_tpiu__PERIPHID4 = 32'hF8803FD0; parameter val_debug_tpiu__PERIPHID4 = 32'h00000004; parameter mask_debug_tpiu__PERIPHID4 = 32'h000000FF; parameter debug_tpiu__PERIPHID5 = 32'hF8803FD4; parameter val_debug_tpiu__PERIPHID5 = 32'h00000000; parameter mask_debug_tpiu__PERIPHID5 = 32'h000000FF; parameter debug_tpiu__PERIPHID6 = 32'hF8803FD8; parameter val_debug_tpiu__PERIPHID6 = 32'h00000000; parameter mask_debug_tpiu__PERIPHID6 = 32'h000000FF; parameter debug_tpiu__PERIPHID7 = 32'hF8803FDC; parameter val_debug_tpiu__PERIPHID7 = 32'h00000000; parameter mask_debug_tpiu__PERIPHID7 = 32'h000000FF; parameter debug_tpiu__PERIPHID0 = 32'hF8803FE0; parameter val_debug_tpiu__PERIPHID0 = 32'h00000012; parameter mask_debug_tpiu__PERIPHID0 = 32'h000000FF; parameter debug_tpiu__PERIPHID1 = 32'hF8803FE4; parameter val_debug_tpiu__PERIPHID1 = 32'h000000B9; parameter mask_debug_tpiu__PERIPHID1 = 32'h000000FF; parameter debug_tpiu__PERIPHID2 = 32'hF8803FE8; parameter val_debug_tpiu__PERIPHID2 = 32'h0000004B; parameter mask_debug_tpiu__PERIPHID2 = 32'h000000FF; parameter debug_tpiu__PERIPHID3 = 32'hF8803FEC; parameter val_debug_tpiu__PERIPHID3 = 32'h00000000; parameter mask_debug_tpiu__PERIPHID3 = 32'h000000FF; parameter debug_tpiu__COMPID0 = 32'hF8803FF0; parameter val_debug_tpiu__COMPID0 = 32'h0000000D; parameter mask_debug_tpiu__COMPID0 = 32'h000000FF; parameter debug_tpiu__COMPID1 = 32'hF8803FF4; parameter val_debug_tpiu__COMPID1 = 32'h00000090; parameter mask_debug_tpiu__COMPID1 = 32'h000000FF; parameter debug_tpiu__COMPID2 = 32'hF8803FF8; parameter val_debug_tpiu__COMPID2 = 32'h00000005; parameter mask_debug_tpiu__COMPID2 = 32'h000000FF; parameter debug_tpiu__COMPID3 = 32'hF8803FFC; parameter val_debug_tpiu__COMPID3 = 32'h000000B1; parameter mask_debug_tpiu__COMPID3 = 32'h000000FF; // ************************************************************ // Module devcfg devcfg // doc version: 1.1 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter devcfg__CTRL = 32'hF8007000; parameter val_devcfg__CTRL = 32'h0C000000; parameter mask_devcfg__CTRL = 32'hFFFFFFFF; parameter devcfg__LOCK = 32'hF8007004; parameter val_devcfg__LOCK = 32'h00000000; parameter mask_devcfg__LOCK = 32'hFFFFFFFF; parameter devcfg__CFG = 32'hF8007008; parameter val_devcfg__CFG = 32'h0000050B; parameter mask_devcfg__CFG = 32'hFFFFFFFF; parameter devcfg__INT_STS = 32'hF800700C; parameter val_devcfg__INT_STS = 32'h00000000; parameter mask_devcfg__INT_STS = 32'hFFFFFFFF; parameter devcfg__INT_MASK = 32'hF8007010; parameter val_devcfg__INT_MASK = 32'hFFFFFFFF; parameter mask_devcfg__INT_MASK = 32'hFFFFFFFF; parameter devcfg__STATUS = 32'hF8007014; parameter val_devcfg__STATUS = 32'h40000820; parameter mask_devcfg__STATUS = 32'hFFFFFFFF; parameter devcfg__DMA_SRC_ADDR = 32'hF8007018; parameter val_devcfg__DMA_SRC_ADDR = 32'h00000000; parameter mask_devcfg__DMA_SRC_ADDR = 32'hFFFFFFFF; parameter devcfg__DMA_DST_ADDR = 32'hF800701C; parameter val_devcfg__DMA_DST_ADDR = 32'h00000000; parameter mask_devcfg__DMA_DST_ADDR = 32'hFFFFFFFF; parameter devcfg__DMA_SRC_LEN = 32'hF8007020; parameter val_devcfg__DMA_SRC_LEN = 32'h00000000; parameter mask_devcfg__DMA_SRC_LEN = 32'hFFFFFFFF; parameter devcfg__DMA_DEST_LEN = 32'hF8007024; parameter val_devcfg__DMA_DEST_LEN = 32'h00000000; parameter mask_devcfg__DMA_DEST_LEN = 32'hFFFFFFFF; parameter devcfg__ROM_SHADOW = 32'hF8007028; parameter val_devcfg__ROM_SHADOW = 32'h00000000; parameter mask_devcfg__ROM_SHADOW = 32'hFFFFFFFF; parameter devcfg__MULTIBOOT_ADDR = 32'hF800702C; parameter val_devcfg__MULTIBOOT_ADDR = 32'h00000000; parameter mask_devcfg__MULTIBOOT_ADDR = 32'hFFFFFFFF; parameter devcfg__SW_ID = 32'hF8007030; parameter val_devcfg__SW_ID = 32'h00000000; parameter mask_devcfg__SW_ID = 32'hFFFFFFFF; parameter devcfg__UNLOCK = 32'hF8007034; parameter val_devcfg__UNLOCK = 32'h00000000; parameter mask_devcfg__UNLOCK = 32'hFFFFFFFF; parameter devcfg__MCTRL = 32'hF8007080; parameter val_devcfg__MCTRL = 32'h00800000; parameter mask_devcfg__MCTRL = 32'h0FFFFFFF; parameter devcfg__XADCIF_CFG = 32'hF8007100; parameter val_devcfg__XADCIF_CFG = 32'h00001114; parameter mask_devcfg__XADCIF_CFG = 32'hFFFFFFFF; parameter devcfg__XADCIF_INT_STS = 32'hF8007104; parameter val_devcfg__XADCIF_INT_STS = 32'h00000200; parameter mask_devcfg__XADCIF_INT_STS = 32'hFFFFFFFF; parameter devcfg__XADCIF_INT_MASK = 32'hF8007108; parameter val_devcfg__XADCIF_INT_MASK = 32'hFFFFFFFF; parameter mask_devcfg__XADCIF_INT_MASK = 32'hFFFFFFFF; parameter devcfg__XADCIF_MSTS = 32'hF800710C; parameter val_devcfg__XADCIF_MSTS = 32'h00000500; parameter mask_devcfg__XADCIF_MSTS = 32'hFFFFFFFF; parameter devcfg__XADCIF_CMDFIFO = 32'hF8007110; parameter val_devcfg__XADCIF_CMDFIFO = 32'h00000000; parameter mask_devcfg__XADCIF_CMDFIFO = 32'hFFFFFFFF; parameter devcfg__XADCIF_RDFIFO = 32'hF8007114; parameter val_devcfg__XADCIF_RDFIFO = 32'h00000000; parameter mask_devcfg__XADCIF_RDFIFO = 32'hFFFFFFFF; parameter devcfg__XADCIF_MCTL = 32'hF8007118; parameter val_devcfg__XADCIF_MCTL = 32'h00000010; parameter mask_devcfg__XADCIF_MCTL = 32'hFFFFFFFF; // ************************************************************ // Module dmac0_ns dmac // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter dmac0_ns__DSR = 32'hF8004000; parameter val_dmac0_ns__DSR = 32'h00000000; parameter mask_dmac0_ns__DSR = 32'hFFFFFFFF; parameter dmac0_ns__DPC = 32'hF8004004; parameter val_dmac0_ns__DPC = 32'h00000000; parameter mask_dmac0_ns__DPC = 32'hFFFFFFFF; parameter dmac0_ns__INTEN = 32'hF8004020; parameter val_dmac0_ns__INTEN = 32'h00000000; parameter mask_dmac0_ns__INTEN = 32'hFFFFFFFF; parameter dmac0_ns__INT_EVENT_RIS = 32'hF8004024; parameter val_dmac0_ns__INT_EVENT_RIS = 32'h00000000; parameter mask_dmac0_ns__INT_EVENT_RIS = 32'hFFFFFFFF; parameter dmac0_ns__INTMIS = 32'hF8004028; parameter val_dmac0_ns__INTMIS = 32'h00000000; parameter mask_dmac0_ns__INTMIS = 32'hFFFFFFFF; parameter dmac0_ns__INTCLR = 32'hF800402C; parameter val_dmac0_ns__INTCLR = 32'h00000000; parameter mask_dmac0_ns__INTCLR = 32'hFFFFFFFF; parameter dmac0_ns__FSRD = 32'hF8004030; parameter val_dmac0_ns__FSRD = 32'h00000000; parameter mask_dmac0_ns__FSRD = 32'hFFFFFFFF; parameter dmac0_ns__FSRC = 32'hF8004034; parameter val_dmac0_ns__FSRC = 32'h00000000; parameter mask_dmac0_ns__FSRC = 32'hFFFFFFFF; parameter dmac0_ns__FTRD = 32'hF8004038; parameter val_dmac0_ns__FTRD = 32'h00000000; parameter mask_dmac0_ns__FTRD = 32'hFFFFFFFF; parameter dmac0_ns__FTR0 = 32'hF8004040; parameter val_dmac0_ns__FTR0 = 32'h00000000; parameter mask_dmac0_ns__FTR0 = 32'hFFFFFFFF; parameter dmac0_ns__FTR1 = 32'hF8004044; parameter val_dmac0_ns__FTR1 = 32'h00000000; parameter mask_dmac0_ns__FTR1 = 32'hFFFFFFFF; parameter dmac0_ns__FTR2 = 32'hF8004048; parameter val_dmac0_ns__FTR2 = 32'h00000000; parameter mask_dmac0_ns__FTR2 = 32'hFFFFFFFF; parameter dmac0_ns__FTR3 = 32'hF800404C; parameter val_dmac0_ns__FTR3 = 32'h00000000; parameter mask_dmac0_ns__FTR3 = 32'hFFFFFFFF; parameter dmac0_ns__FTR4 = 32'hF8004050; parameter val_dmac0_ns__FTR4 = 32'h00000000; parameter mask_dmac0_ns__FTR4 = 32'hFFFFFFFF; parameter dmac0_ns__FTR5 = 32'hF8004054; parameter val_dmac0_ns__FTR5 = 32'h00000000; parameter mask_dmac0_ns__FTR5 = 32'hFFFFFFFF; parameter dmac0_ns__FTR6 = 32'hF8004058; parameter val_dmac0_ns__FTR6 = 32'h00000000; parameter mask_dmac0_ns__FTR6 = 32'hFFFFFFFF; parameter dmac0_ns__FTR7 = 32'hF800405C; parameter val_dmac0_ns__FTR7 = 32'h00000000; parameter mask_dmac0_ns__FTR7 = 32'hFFFFFFFF; parameter dmac0_ns__CSR0 = 32'hF8004100; parameter val_dmac0_ns__CSR0 = 32'h00000000; parameter mask_dmac0_ns__CSR0 = 32'hFFFFFFFF; parameter dmac0_ns__CPC0 = 32'hF8004104; parameter val_dmac0_ns__CPC0 = 32'h00000000; parameter mask_dmac0_ns__CPC0 = 32'hFFFFFFFF; parameter dmac0_ns__CSR1 = 32'hF8004108; parameter val_dmac0_ns__CSR1 = 32'h00000000; parameter mask_dmac0_ns__CSR1 = 32'hFFFFFFFF; parameter dmac0_ns__CPC1 = 32'hF800410C; parameter val_dmac0_ns__CPC1 = 32'h00000000; parameter mask_dmac0_ns__CPC1 = 32'hFFFFFFFF; parameter dmac0_ns__CSR2 = 32'hF8004110; parameter val_dmac0_ns__CSR2 = 32'h00000000; parameter mask_dmac0_ns__CSR2 = 32'hFFFFFFFF; parameter dmac0_ns__CPC2 = 32'hF8004114; parameter val_dmac0_ns__CPC2 = 32'h00000000; parameter mask_dmac0_ns__CPC2 = 32'hFFFFFFFF; parameter dmac0_ns__CSR3 = 32'hF8004118; parameter val_dmac0_ns__CSR3 = 32'h00000000; parameter mask_dmac0_ns__CSR3 = 32'hFFFFFFFF; parameter dmac0_ns__CPC3 = 32'hF800411C; parameter val_dmac0_ns__CPC3 = 32'h00000000; parameter mask_dmac0_ns__CPC3 = 32'hFFFFFFFF; parameter dmac0_ns__CSR4 = 32'hF8004120; parameter val_dmac0_ns__CSR4 = 32'h00000000; parameter mask_dmac0_ns__CSR4 = 32'hFFFFFFFF; parameter dmac0_ns__CPC4 = 32'hF8004124; parameter val_dmac0_ns__CPC4 = 32'h00000000; parameter mask_dmac0_ns__CPC4 = 32'hFFFFFFFF; parameter dmac0_ns__CSR5 = 32'hF8004128; parameter val_dmac0_ns__CSR5 = 32'h00000000; parameter mask_dmac0_ns__CSR5 = 32'hF"b"FFFFFFF; parameter dmac0_ns__CPC5 = 32'hF800412C; parameter val_dmac0_ns__CPC5 = 32'h00000000; parameter mask_dmac0_ns__CPC5 = 32'hFFFFFFFF; parameter dmac0_ns__CSR6 = 32'hF8004130; parameter val_dmac0_ns__CSR6 = 32'h00000000; parameter mask_dmac0_ns__CSR6 = 32'hFFFFFFFF; parameter dmac0_ns__CPC6 = 32'hF8004134; parameter val_dmac0_ns__CPC6 = 32'h00000000; parameter mask_dmac0_ns__CPC6 = 32'hFFFFFFFF; parameter dmac0_ns__CSR7 = 32'hF8004138; parameter val_dmac0_ns__CSR7 = 32'h00000000; parameter mask_dmac0_ns__CSR7 = 32'hFFFFFFFF; parameter dmac0_ns__CPC7 = 32'hF800413C; parameter val_dmac0_ns__CPC7 = 32'h00000000; parameter mask_dmac0_ns__CPC7 = 32'hFFFFFFFF; parameter dmac0_ns__SAR0 = 32'hF8004400; parameter val_dmac0_ns__SAR0 = 32'h00000000; parameter mask_dmac0_ns__SAR0 = 32'hFFFFFFFF; parameter dmac0_ns__DAR0 = 32'hF8004404; parameter val_dmac0_ns__DAR0 = 32'h00000000; parameter mask_dmac0_ns__DAR0 = 32'hFFFFFFFF; parameter dmac0_ns__CCR0 = 32'hF8004408; parameter val_dmac0_ns__CCR0 = 32'h00000000; parameter mask_dmac0_ns__CCR0 = 32'hFFFFFFFF; parameter dmac0_ns__LC0_0 = 32'hF800440C; parameter val_dmac0_ns__LC0_0 = 32'h00000000; parameter mask_dmac0_ns__LC0_0 = 32'hFFFFFFFF; parameter dmac0_ns__LC1_0 = 32'hF8004410; parameter val_dmac0_ns__LC1_0 = 32'h00000000; parameter mask_dmac0_ns__LC1_0 = 32'hFFFFFFFF; parameter dmac0_ns__SAR1 = 32'hF8004420; parameter val_dmac0_ns__SAR1 = 32'h00000000; parameter mask_dmac0_ns__SAR1 = 32'hFFFFFFFF; parameter dmac0_ns__DAR1 = 32'hF8004424; parameter val_dmac0_ns__DAR1 = 32'h00000000; parameter mask_dmac0_ns__DAR1 = 32'hFFFFFFFF; parameter dmac0_ns__CCR1 = 32'hF8004428; parameter val_dmac0_ns__CCR1 = 32'h00000000; parameter mask_dmac0_ns__CCR1 = 32'hFFFFFFFF; parameter dmac0_ns__LC0_1 = 32'hF800442C; parameter val_dmac0_ns__LC0_1 = 32'h00000000; parameter mask_dmac0_ns__LC0_1 = 32'hFFFFFFFF; parameter dmac0_ns__LC1_1 = 32'hF8004430; parameter val_dmac0_ns__LC1_1 = 32'h00000000; parameter mask_dmac0_ns__LC1_1 = 32'hFFFFFFFF; parameter dmac0_ns__SAR2 = 32'hF8004440; parameter val_dmac0_ns__SAR2 = 32'h00000000; parameter mask_dmac0_ns__SAR2 = 32'hFFFFFFFF; parameter dmac0_ns__DAR2 = 32'hF8004444; parameter val_dmac0_ns__DAR2 = 32'h00000000; parameter mask_dmac0_ns__DAR2 = 32'hFFFFFFFF; parameter dmac0_ns__CCR2 = 32'hF8004448; parameter val_dmac0_ns__CCR2 = 32'h00000000; parameter mask_dmac0_ns__CCR2 = 32'hFFFFFFFF; parameter dmac0_ns__LC0_2 = 32'hF800444C; parameter val_dmac0_ns__LC0_2 = 32'h00000000; parameter mask_dmac0_ns__LC0_2 = 32'hFFFFFFFF; parameter dmac0_ns__LC1_2 = 32'hF8004450; parameter val_dmac0_ns__LC1_2 = 32'h00000000; parameter mask_dmac0_ns__LC1_2 = 32'hFFFFFFFF; parameter dmac0_ns__SAR3 = 32'hF8004460; parameter val_dmac0_ns__SAR3 = 32'h00000000; parameter mask_dmac0_ns__SAR3 = 32'hFFFFFFFF; parameter dmac0_ns__DAR3 = 32'hF8004464; parameter val_dmac0_ns__DAR3 = 32'h00000000; parameter mask_dmac0_ns__DAR3 = 32'hFFFFFFFF; parameter dmac0_ns__CCR3 = 32'hF8004468; parameter val_dmac0_ns__CCR3 = 32'h00000000; parameter mask_dmac0_ns__CCR3 = 32'hFFFFFFFF; parameter dmac0_ns__LC0_3 = 32'hF800446C; parameter val_dmac0_ns__LC0_3 = 32'h00000000; parameter mask_dmac0_ns__LC0_3 = 32'hFFFFFFFF; parameter dmac0_ns__LC1_3 = 32'hF8004470; parameter val_dmac0_ns__LC1_3 = 32'h00000000; parameter mask_dmac0_ns__LC1_3 = 32'hFFFFFFFF; parameter dmac0_ns__SAR4 = 32'hF8004480; parameter val_dmac0_ns__SAR4 = 32'h00000000; parameter mask_dmac0_ns__SAR4 = 32'hFFFFFFFF; parameter dmac0_ns__DAR4 = 32'hF8004484; parameter val_dmac0_ns__DAR4 = 32'h00000000; parameter mask_dmac0_ns__DAR4 = 32'hFFFFFFFF; parameter dmac0_ns__CCR4 = 32'hF8004488; parameter val_dmac0_ns__CCR4 = 32'h00000000; parameter mask_dmac0_ns__CCR4 = 32'hFFFFFFFF; parameter dmac0_ns__LC0_4 = 32'hF800448C; parameter val_dmac0_ns__LC0_4 = 32'h00000000; parameter mask_dmac0_ns__LC0_4 = 32'hFFFFFFFF; parameter dmac0_ns__LC1_4 = 32'hF8004490; parameter val_dmac0_ns__LC1_4 = 32'h00000000; parameter mask_dmac0_ns__LC1_4 = 32'hFFFFFFFF; parameter dmac0_ns__SAR5 = 32'hF80044A0; parameter val_dmac0_ns__SAR5 = 32'h00000000; parameter mask_dmac0_ns__SAR5 = 32'hFFFFFFFF; parameter dmac0_ns__DAR5 = 32'hF80044A4; parameter val_dmac0_ns__DAR5 = 32'h00000000; parameter mask_dmac0_ns__DAR5 = 32'hFFFFFFFF; parameter dmac0_ns__CCR5 = 32'hF80044A8; parameter val_dmac0_ns__CCR5 = 32'h00000000; parameter mask_dmac0_ns__CCR5 = 32'hFFFFFFFF; parameter dmac0_ns__LC0_5 = 32'hF80044AC; parameter val_dmac0_ns__LC0_5 = 32'h00000000; parameter mask_dmac0_ns__LC0_5 = 32'hFFFFFFFF; parameter dmac0_ns__LC1_5 = 32'hF80044B0; parameter val_dmac0_ns__LC1_5 = 32'h00000000; parameter mask_dmac0_ns__LC1_5 = 32'hFFFFFFFF; parameter dmac0_ns__SAR6 = 32'hF80044C0; parameter val_dmac0_ns__SAR6 = 32'h00000000; parameter mask_dmac0_ns__SAR6 = 32'hFFFFFFFF; parameter dmac0_ns__DAR6 = 32'hF80044C4; parameter val_dmac0_ns__DAR6 = 32'h00000000; parameter mask_dmac0_ns__DAR6 = 32'hFFFFFFFF; parameter dmac0_ns__CCR6 = 32'hF80044C8; parameter val_dmac0_ns__CCR6 = 32'h00000000; parameter mask_dmac0_ns__CCR6 = 32'hFFFFFFFF; parameter dmac0_ns__LC0_6 = 32'hF80044CC; parameter val_dmac0_ns__LC0_6 = 32'h00000000; parameter mask_dmac0_ns__LC0_6 = 32'hFFFFFFFF; parameter dmac0_ns__LC1_6 = 32'hF80044D0; parameter val_dmac0_ns__LC1_6 = 32'h00000000; parameter mask_dmac0_ns__LC1_6 = 32'hFFFFFFFF; parameter dmac0_ns__SAR7 = 32'hF80044E0; parameter val_dmac0_ns__SAR7 = 32'h00000000; parameter mask_dmac0_ns__SAR7 = 32'hFFFFFFFF; parameter dmac0_ns__DAR7 = 32'hF80044E4; parameter val_dmac0_ns__DAR7 = 32'h00000000; parameter mask_dmac0_ns__DAR7 = 32'hFFFFFFFF; parameter dmac0_ns__CCR7 = 32'hF80044E8; parameter val_dmac0_ns__CCR7 = 32'h00000000; parameter mask_dmac0_ns__CCR7 = 32'hFFFFFFFF; parameter dmac0_ns__LC0_7 = 32'hF80044EC; parameter val_dmac0_ns__LC0_7 = 32'h00000000; parameter mask_dmac0_ns__LC0_7 = 32'hFFFFFFFF; parameter dmac0_ns__LC1_7 = 32'hF80044F0; parameter val_dmac0_ns__LC1_7 = 32'h00000000; parameter mask_dmac0_ns__LC1_7 = 32'hFFFFFFFF; parameter dmac0_ns__DBGSTATUS = 32'hF8004D00; parameter val_dmac0_ns__DBGSTATUS = 32'h00000000; parameter mask_dmac0_ns__DBGSTATUS = 32'hFFFFFFFF; parameter dmac0_ns__DBGCMD = 32'hF8004D04; parameter val_dmac0_ns__DBGCMD = 32'h00000000; parameter mask_dmac0_ns__DBGCMD = 32'hFFFFFFFF; parameter dmac0_ns__DBGINST0 = 32'hF8004D08; parameter val_dmac0_ns__DBGINST0 = 32'h00000000; parameter mask_dmac0_ns__DBGINST0 = 32'hFFFFFFFF; parameter dmac0_ns__DBGINST1 = 32'hF8004D0C; parameter val_dmac0_ns__DBGINST1 = 32'h00000000; parameter mask_dmac0_ns__DBGINST1 = 32'hFFFFFFFF; parameter dmac0_ns__CR0 = 32'hF8004E00; parameter val_dmac0_ns__CR0 = 32'h00000000; parameter mask_dmac0_ns__CR0 = 32'hFFFFFFFF; parameter dmac0_ns__CR1 = 32'hF8004E04; parameter val_dmac0_ns__CR1 = 32'h00000000; parameter mask_dmac0_ns__CR1 = 32'hFFFFFFFF; parameter dmac0_ns__CR2 = 32'hF8004E08; parameter val_dmac0_ns__CR2 = 32'h00000000; parameter mask_dmac0_ns__CR2 = 32'hFFFFFFFF; parameter dmac0_ns__CR3 = 32'hF8004E0C; parameter val_dmac0_ns__CR3 = 32'h00000000; parameter mask_dmac0_ns__CR3 = 32'hFFFFFFFF; parameter dmac0_ns__CR4 = 32'hF8004E10; parameter val_dmac0_ns__CR4 = 32'h00000000; parameter mask_dmac0_ns__CR4 = 32'hFFFFFFFF; parameter dmac0_ns__CRD = 32'hF8004E14; parameter val_dmac0_ns__CRD = 32'h00000000; parameter mask_dmac0_ns__CRD = 32'hFFFFFFFF; parameter dmac0_ns__WD = 32'hF8004E80; parameter val_dmac0_ns__WD = 32'h00000000; parameter mask_dmac0_ns__WD = 32'hFFFFFFFF; parameter dmac0_ns__periph_id_0 = 32'hF8004FE0; parameter val_dmac0_ns__periph_id_0 = 32'h00000000; parameter mask_dmac0_ns__periph_id_0 = 32'hFFFFFFFF; parameter dmac0_ns__periph_id_1 = 32'hF8004FE4; parameter val_dmac0_ns__periph_id_1 = 32'h00000000; parameter mask_dmac0_ns__periph_id_1 = 32'hFFFFFFFF; parameter dmac0_ns__periph_id_2 = 32'hF8004FE8; parameter val_dmac0_ns__periph_id_2 = 32'h00000000; parameter mask_dmac0_ns__periph_id_2 = 32'hFFFFFFFF; parameter dmac0_ns__periph_id_3 = 32'hF8004FEC; parameter val_dmac0_ns__periph_id_3 = 32'h00000000; parameter mask_dmac0_ns__periph_id_3 = 32'hFFFFFFFF; parameter dmac0_ns__pcell_id_0 = 32'hF8004FF0; parameter val_dmac0_ns__pcell_id_0 = 32'h00000000; parameter mask_dmac0_ns__pcell_id_0 = 32'hFFFFFFFF; parameter dmac0_ns__pcell_id_1 = 32'hF8004FF4; parameter val_dmac0_ns__pcell_id_1 = 32'h00000000; parameter mask_dmac0_ns__pcell_id_1 = 32'hFFFFFFFF; parameter dmac0_ns__pcell_id_2 = 32'hF8004FF8; parameter val_dmac0_ns__pcell_id_2 = 32'h00000000; parameter mask_dmac0_ns__pcell_id_2 = 32'hFFFFFFFF; parameter dmac0_ns__pcell_id_3 = 32'hF8004FFC; parameter val_dmac0_ns__pcell_id_3 = 32'h00000000; parameter mask_dmac0_ns__pcell_id_3 = 32'hFFFFFFFF; // ************************************************************ // Module dmac0_s dmac // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter dmac0_s__DSR = 32'hF8003000; parameter val_dmac0_s__DSR = 32'h00000000; parameter mask_dmac0_s__DSR = 32'hFFFFFFFF; parameter dmac0_s__DPC = 32'hF8003004; parameter val_dmac0_s__DPC = 32'h00000000; parameter mask_dmac0_s__DPC = 32'hFFFFFFFF; parameter dmac0_s__INTEN = 32'hF8003020; parameter val_dmac0_s__INTEN = 32'h00000000; parameter mask_dmac0_s__INTEN = 32'hFFFFFFFF; parameter dmac0_s__INT_EVENT_RIS = 32'hF8003024; parameter val_dmac0_s__INT_EVENT_RIS = 32'h00000000; parameter mask_dmac0_s__INT_EVENT_RIS = 32'hFFFFFFFF; parameter dmac0_s__INTMIS = 32'hF8003028; parameter val_dmac0_s__INTMIS = 32'h00000000; parameter mask_dmac0_s__INTMIS = 32'hFFFFFFFF; parameter dmac0_s__INTCLR = 32'hF800302C; parameter val_dmac0_s__INTCLR = 32'h00000000; parameter mask_dmac0_s__INTCLR = 32'hFFFFFFFF; parameter dmac0_s__FSRD = 32'hF8003030; parameter val_dmac0_s__FSRD = 32'h00000000; parameter mask_dmac0_s__FSRD = 32'hFFFFFFFF; parameter dmac0_s__FSRC = 32'hF8003034; parameter val_dmac0_s__FSRC = 32'h00000000; parameter mask_dmac0_s__FSRC = 32'hFFFFFFFF; parameter dmac0_s__FTRD = 32'hF8003038; parameter val_dmac0_s__FTRD = 32'h00000000; parameter mask_dmac0_s__FTRD = 32'hFFFFFFFF; parameter dmac0_s__FTR0 = 32'hF8003040; parameter val_dmac0_s__FTR0 = 32'h00000000; parameter mask_dmac0_s__FTR0 = 32'hFFFFFFFF; parameter dmac0_s__FTR1 = 32'hF8003044; parameter val_dmac0_s__FTR1 = 32'h00000000; parameter mask_dmac0_s__FTR1 = 32'hFFFFFFFF; parameter dmac0_s__FTR2 = 32'hF8003048; parameter val_dmac0_s__FTR2 = 32'h00000000; parameter mask_dmac0_s__FTR2 = 32'hFFFFFFFF; parameter dmac0_s__FTR3 = 32'hF800304C; parameter val_dmac0_s__FTR3 = 32'h00000000; parameter mask_dmac0_s__FTR3 = 32'hFFFFFFFF; parameter dmac0_s__FTR4 = 32'hF8003050; parameter val_dmac0_s__FTR4 = 32'h00000000; parameter mask_dmac0_s__FTR4 = 32'hFFFFFFFF; parameter dmac0_s__FTR5 = 32'hF8003054; parameter val_dmac0_s__FTR5 = 32'h00000000; parameter mask_dmac0_s__FTR5 = 32'hFFFFFFFF; parameter dmac0_s__FTR6 = 32'hF8003058; parameter val_dmac0_s__FTR6 = 32'h00000000; parameter mask_dmac0_s__FTR6 = 32'hFFFFFFFF; parameter dmac0_s__FTR7 = 32'hF800305C; parameter val_dmac0_s__FTR7 = 32'h00000000; parameter mask_dmac0_s__FTR7 = 32'hFFFFFFFF; parameter dmac0_s__CSR0 = 32'hF8003100; parameter val_dmac0_s__CSR0 = 32'h00000000; parameter mask_dmac0_s__CSR0 = 32'hFFFFFFFF; parameter dmac0_s__CPC0 = 32'hF8003104; parameter val_dmac0_s__CPC0 = 32'h00000000; parameter mask_dmac0_s__CPC0 = 32'hFFFFFFFF; parameter dmac0_s__CSR1 = 32'hF8003108; parameter val_dmac0_s__CSR1 = 32'h00000000; parameter mask_dmac0_s__CSR1 = 32'hFFFFFFFF; parameter dmac0_s__CPC1 = 32'hF800310C; parameter val_dmac0_s__CPC1 = 32'h00000000; parameter mask_dmac0_s__CPC1 = 32'hFFFFFFFF; parameter dmac0_s__CSR2 = 32'hF8003110; parameter val_dmac0_s__CSR2 = 32'h00000000; parameter mask_dmac0_s__CSR2 = 32'hFFFFFFFF; parameter dmac0_s__CPC2 = 32'hF8003114; parameter val_dmac0_s__CPC2 = 32'h00000000; parameter mask_dmac0_s__CPC2 = 32'hFFFFFFFF; parameter dmac0_s__CSR3 = 32'hF8003118; parameter val_dmac0_s__CSR3 = 32'h00000000; parameter mask_dmac0_s__CSR3 = 32'hFFFFFFFF; parameter dmac0_s__CPC3 = 32'hF800311C; parameter val_dmac0_s__CPC3 = 32'h00000000; parameter mask_dmac0_s__CPC3 = 32'hFFFFFFFF; parameter dmac0_s__CSR4 = 32'hF8003120; parameter val_dmac0_s__CSR4 = 32'h00000000; parameter mask_dmac0_s__CSR4 = 32'hFFFFFFFF; parameter dmac0_s__CPC4 = 32'hF8003124; parameter val_dmac0_s__CPC4 = 32'h00000000; parameter mask_dmac0_s__CPC4 = 32'hFFFFFFFF; parameter dmac0_s__CSR5 = 32'hF8003128; parameter val_dmac0_s__CSR5 = 32'h00000000; parameter mask_dmac0_s__CSR5 = 32'hFFFFFFFF; parameter dmac0_s__CPC5 = 32'hF800312C; parameter val_dmac0_s__CPC5 = 32'h00000000; parameter mask_dmac0_s__CPC5 = 32'hFFFFFFFF; parameter dmac0_s__CSR6 = 32'hF8003130; parameter val_dmac0_s__CSR6 = 32'h00000000; parameter mask_dmac0_s__CSR6 = 32'hFFFFFFFF; parameter dmac0_s__CPC6 = 32'hF8003134; parameter val_dmac0_s__CPC6 = 32'h00000000; parameter mask_dmac0_s__CPC6 = 32'hFFFFFFFF; parameter dmac0_s__CSR7 = 32'hF8003138; parameter val_dmac0_s__CSR7 = 32'h00000000; parameter mask_dmac0_s__CSR7 = 32'hFFFFFFFF; parameter dmac0_s__CPC7 = 32'hF800313C; parameter val_dmac0_s__CPC7 = 32'h00000000; parameter mask_dmac0_s__CPC7 = 32'hFFFFFFFF; parameter dmac0_s__SAR0 = 32'hF8003400; parameter val_dmac0_s__SAR0 = 32'h00000000; parameter mask_dmac0_s__SAR0 = 32'hFFFFFFFF; parameter dmac0_s__DAR0 = 32'hF8003404; parameter val_dmac0_s__DAR0 = 32'h00000000; parameter mask_dmac0_s__DAR0 = 32'hFFFFFFFF; parameter dmac0_s__CCR0 = 32'hF8003408; parameter val_dmac0_s__CCR0 = 32'h00800200; parameter mask_dmac0_s__CCR0 = 32'hFFFFFFFF; parameter dmac0_s__LC0_0 = 32'hF800340C; parameter val_dmac0_s__LC0_0 = 32'h00000000; parameter mask_dmac0_s__LC0_0 = 32'hFFFFFFFF; parameter dmac0_s__LC1_0 = 32'hF8003410; parameter val_dmac0_s__LC1_0 = 32'h00000000; parameter mask_dmac0_s__LC1_0 = 32'hFFFFFFFF; parameter dmac0_s__SAR1 = 32'hF8003420; parameter val_dmac0_s__SAR1 = 32'h00000000; parameter mask_dmac0_s__SAR1 = 32'hFFFFFFFF; parameter dmac0_s__DAR1 = 32'hF8003424; parameter val_dmac0_s__DAR1 = 32'h00000000; parameter mask_dmac0_s__DAR1 = 32'hFFFFFFFF; parameter dmac0_s__CCR1 = 32'hF8003428; parameter val_dmac0_s__CCR1 = 32'h00800200; parameter mask_dmac0_s__CCR1 = 32'hFFFFFFFF; parameter dmac0_s__LC0_1 = 32'hF800342C; parameter val_dmac0_s__LC0_1 = 32'h00000000; parameter mask_dmac0_s__LC0_1 = 32'hFFFFFFFF; parameter dmac0_s__LC1_1 = 32'hF8003430; parameter val_dmac0_s__LC1_1 = 32'h00000000; parameter mask_dmac0_s__LC1_1 = 32'hFFFFFFFF; parameter dmac0_s__SAR2 = 32'hF8003440; parameter val_dmac0_s__SAR2 = 32'h00000000; parameter mask_dmac0_s__SAR2 = 32'hFFFFFFFF; parameter dmac0_s__DAR2 = 32'hF8003444; parameter val_dmac0_s__DAR2 = 32'h00000000; parameter mask_dmac0_s__DAR2 = 32'hFFFFFFFF; parameter dmac0_s__CCR2 = 32'hF8003448; parameter val_dmac0_s__CCR2 = 32'h00800200; parameter mask_dmac0_s__CCR2 = 32'hFFFFFFFF; parameter dmac0_s__LC0_2 = 32'hF800344C; parameter val_dmac0_s__LC0_2 = 32'h00000000; parameter mask_dmac0_s__LC0_2 = 32'hFFFFFFFF; parameter dmac0_s__LC1_2 = 32'hF8003450; parameter val_dmac0_s__LC1_2 = 32'h00000000; parameter mask_dmac0_s__LC1_2 = 32'hFFFFFFFF; parameter dmac0_s__SAR3 = 32'hF8003460; parameter val_dmac0_s__SAR3 = 32'h00000000; parameter mask_dmac0_s__SAR3 = 32'hFFFFFFFF; parameter dmac0_s__DAR3 = 32'hF8003464; parameter val_dmac0_s__DAR3 = 32'h00000000; parameter mask_dmac0_s__DAR3 = 32'hFFFFFFFF; parameter dmac0_s__CCR3 = 32'hF8003468; parameter val_dmac0_s__CCR3 = 32'h00800200; parameter mask_dmac0_s__CCR3 = 32'hFFFFFFFF; parameter dmac0_s__LC0_3 = 32'hF800346C; parameter val_dmac0_s__LC0_3 = 32'h00000000; parameter mask_dmac0_s__LC0_3 = 32'hFFFFFFFF; parameter dmac0_s__LC1_3 = 32'hF8003470; parameter val_dmac0_s__LC1_3 = 32'h00000000; parameter mask_dmac0_s__LC1_3 = 32'hFFFFFFFF; parameter dmac0_s__SAR4 = 32'hF8003480; parameter val_dmac0_s__SAR4 = 32'h00000000; parameter mask_dmac0_s__SAR4 = 32'hFFFFFFFF; parameter dmac0_s__DAR4 = 32'hF8003484; parameter val_dmac0_s__DAR4 = 32'h00000000; parameter mask_dmac0_s__DAR4 = 32'hFFFFFFFF; parameter dmac0_s__CCR4 = 32'hF8003488; parameter val_dmac0_s__CCR4 = 32'h00800200; parameter mask_dmac0_s__CCR4 = 32'hFFFFFFFF; parameter dmac0_s__LC0_4 = 32'hF800348C; parameter val_dmac0_s__LC0_4 = 32'h00000000; parameter mask_dmac0_s__LC0_4 = 32'hFFFFFFFF; parameter dmac0_s__LC1_4 = 32'hF8003490; parameter val_dmac0_s__LC1_4 = 32'h00000000; parameter mask_dmac0_s__LC1_4 = 32'hFFFFFFFF; parameter dmac0_s__SAR5 = 32'hF80034A0; parameter val_dmac0_s__SAR5 = 32'h00000000; parameter mask_dmac0_s__SAR5 = 32'hFFFFFFFF; parameter dmac0_s__DAR5 = 32'hF80034A4; parameter val_dmac0_s__DAR5 = 32'h00000000; parameter mask_dmac0_s__DAR5 = 32'hFFFFFFFF; parameter dmac0_s__CCR5 = 32'hF80034A8; parameter val_dmac0_s__CCR5 = 32'h00800200; parameter mask_dmac0_s__CCR5 = 32'hFFFFFFFF; parameter dmac0_s__LC0_5 = 32'hF80034AC; parameter val_dmac0_s__LC0_5 = 32'h00000000; parameter mask_dmac0_s__LC0_5 = 32'hFFFFFFFF; parameter dmac0_s__LC1_5 = 32'hF80034B0; parameter val_dmac0_s__LC1_5 = 32'h00000000; parameter mask_dmac0_s__LC1_5 = 32'hFFFFFFFF; parameter dmac0_s__SAR6 = 32'hF80034C0; parameter val_dmac0_s__SAR6 = 32'h00000000; parameter mask_dmac0_s__SAR6 = 32'hFFFFFFFF; parameter dmac0_s__DAR6 = 32'hF80034C4; parameter val_dmac0_s__DAR6 = 32'h00000000; parameter mask_dmac0_s__DAR6 = 32'hFFFFFFFF; parameter dmac0_s__CCR6 = 32'hF80034C8; parameter val_dmac0_s__CCR6 = 32'h00800200; parameter mask_dmac0_s__CCR6 = 32'hFFFFFFFF; parameter dmac0_s__LC0_6 = 32'hF80034CC; parameter val_dmac0_s__LC0_6 = 32'h00000000; parameter mask_dmac0_s__LC0_6 = 32'hFFFFFFFF; parameter dmac0_s__LC1_6 = 32'hF80034D0; parameter val_dmac0_s__LC1_6 = 32'h00000000; parameter mask_dmac0_s__LC1_6 = 32'hFFFFFFFF; parameter dmac0_s__SAR7 = 32'hF80034E0; parameter val_dmac0_s__SAR7 = 32'h00000000; parameter mask_dmac0_s__SAR7 = 32'hFFFFFFFF; parameter dmac0_s__DAR7 = 32'hF80034E4; parameter val_dmac0_s__DAR7 = 32'h00000000; parameter mask_dmac0_s__DAR7 = 32'hFFFFFFFF; parameter dmac0_s__CCR7 = 32'hF80034E8; parameter val_dmac0_s__CCR7 = 32'h00800200; parameter mask_dmac0_s__CCR7 = 32'hFFFFFFFF; parameter dmac0_s__LC0_7 = 32'hF80034EC; parameter val_dmac0_s__LC0_7 = 32'h00000000; parameter mask_dmac0_s__LC0_7 = 32'hFFFFFFFF; parameter dmac0_s__LC1_7 = 32'hF80034F0; parameter val_dmac0_s__LC1_7 = 32'h00000000; parameter mask_dmac0_s__LC1_7 = 32'hFFFFFFFF; parameter dmac0_s__DBGSTATUS = 32'hF8003D00; parameter val_dmac0_s__DBGSTATUS = 32'h00000000; parameter mask_dmac0_s__DBGSTATUS = 32'hFFFFFFFF; parameter dmac0_s__DBGCMD = 32'hF8003D04; parameter val_dmac0_s__DBGCMD = 32'h00000000; parameter mask_dmac0_s__DBGCMD = 32'hFFFFFFFF; parameter dmac0_s__DBGINST0 = 32'hF8003D08; parameter val_dmac0_s__DBGINST0 = 32'h00000000; parameter mask_dmac0_s__DBGINST0 = 32'hFFFFFFFF; parameter dmac0_s__DBGINST1 = 32'hF8003D0C; parameter val_dmac0_s__DBGINST1 = 32'h00000000; parameter mask_dmac0_s__DBGINST1 = 32'hFFFFFFFF; parameter dmac0_s__CR0 = 32'hF8003E00; parameter val_dmac0_s__CR0 = 32'h001E3071; parameter mask_dmac0_s__CR0 = 32'hFFFFFFFF; parameter dmac0_s__CR1 = 32'hF8003E04; parameter val_dmac0_s__CR1 = 32'h00000074; parameter mask_dmac0_s__CR1 = 32'hFFFFFFFF; parameter dmac0_s__CR2 = 32'hF8003E08; parameter val_dmac0_s__CR2 = 32'h00000000; parameter mask_dmac0_s__CR2 = 32'hFFFFFFFF; parameter dmac0_s__CR3 = 32'hF8003E0C; parameter val_dmac0_s__CR3 = 32'h00000000; parameter mask_dmac0_s__CR3 = 32'hFFFFFFFF; parameter dmac0_s__CR4 = 32'hF8003E10; parameter val_dmac0_s__CR4 = 32'h00000000; parameter mask_dmac0_s__CR4 = 32'hFFFFFFFF; parameter dmac0_s__CRD = 32'hF8003E14; parameter val_dmac0_s__CRD = 32'h07FF7F73; parameter mask_dmac0_s__CRD = 32'hFFFFFFFF; parameter dmac0_s__WD = 32'hF8003E80; parameter val_dmac0_s__WD = 32'h00000000; parameter mask_dmac0_s__WD = 32'hFFFFFFFF; parameter dmac0_s__periph_id_0 = 32'hF8003FE0; parameter val_dmac0_s__periph_id_0 = 32'h00000030; parameter mask_dmac0_s__periph_id_0 = 32'hFFFFFFFF; parameter dmac0_s__periph_id_1 = 32'hF8003FE4; parameter val_dmac0_s__periph_id_1 = 32'h00000013; parameter mask_dmac0_s__periph_id_1 = 32'hFFFFFFFF; parameter dmac0_s__periph_id_2 = 32'hF8003FE8; parameter val_dmac0_s__periph_id_2 = 32'h00000024; parameter mask_dmac0_s__periph_id_2 = 32'hFFFFFFFF; parameter dmac0_s__periph_id_3 = 32'hF8003FEC; parameter val_dmac0_s__periph_id_3 = 32'h00000000; parameter mask_dmac0_s__periph_id_3 = 32'hFFFFFFFF; parameter dmac0_s__pcell_id_0 = 32'hF8003FF0; parameter val_dmac0_s__pcell_id_0 = 32'h0000000D; parameter mask_dmac0_s__pcell_id_0 = 32'hFFFFFFFF; parameter dmac0_s__pcell_id_1 = 32'hF8003FF4; parameter val_dmac0_s__pcell_id_1 = 32'h000000F0; parameter mask_dmac0_s__pcell_id_1 = 32'hFFFFFFFF; parameter dmac0_s__pcell_id_2 = 32'hF8003FF8; parameter val_dmac0_s__pcell_id_2 = 32'h00000005; parameter mask_dmac0_s__pcell_id_2 = 32'hFFFFFFFF; parameter dmac0_s__pcell_id_3 = 32'hF8003FFC; parameter val_dmac0_s__pcell_id_3 = 32'h000000B1; parameter mask_dmac0_s__pcell_id_3 = 32'hFFFFFFFF; // ************************************************************ // Module efuse_ctrl efuse_ctrl // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter efuse_ctrl__WR_LOCK = 32'hF800D000; parameter val_efuse_ctrl__WR_LOCK = 32'h00000000; parameter mask_efuse_ctrl__WR_LOCK = 32'hFFFFFFFF; parameter efuse_ctrl__WR_UNLOCK = 32'hF800D004; parameter val_efuse_ctrl__WR_UNLOCK = 32'h00000000; parameter mask_efuse_ctrl__WR_UNLOCK = 32'hFFFFFFFF; parameter efuse_ctrl__WR_LOCKSTA = 32'hF800D008; parameter val_efuse_ctrl__WR_LOCKSTA = 32'h00000001; parameter mask_efuse_ctrl__WR_LOCKSTA = 32'hFFFFFFFF; parameter efuse_ctrl__CFG = 32'hF800D00C; parameter val_efuse_ctrl__CFG = 32'h00010F00; parameter mask_efuse_ctrl__CFG = 32'hFFFFFFFF; parameter efuse_ctrl__STATUS = 32'hF800D010; parameter val_efuse_ctrl__STATUS = 32'h00100000; parameter mask_efuse_ctrl__STATUS = 32'hFFFFFFFF; parameter efuse_ctrl__CONTROL = 32'hF800D014; parameter val_efuse_ctrl__CONTROL = 32'h00000003; parameter mask_efuse_ctrl__CONTROL = 32'hFFFFFFFF; parameter efuse_ctrl__PGM_STBW = 32'hF800D018; parameter val_efuse_ctrl__PGM_STBW = 32'h000002D0; parameter mask_efuse_ctrl__PGM_STBW = 32'hFFFFFFFF; parameter efuse_ctrl__RD_STBW = 32'hF800D01C; parameter val_efuse_ctrl__RD_STBW = 32'h0000000B; parameter mask_efuse_ctrl__RD_STBW = 32'hFFFFFFFF; // ************************************************************ // Module gem0 GEM // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter gem0__net_ctrl = 32'hE000B000; parameter val_gem0__net_ctrl = 32'h00000000; parameter mask_gem0__net_ctrl = 32'hFFFFFFFF; parameter gem0__net_cfg = 32'hE000B004; parameter val_gem0__net_cfg = 32'h00080000; parameter mask_gem0__net_cfg = 32'hFFFFFFFF; parameter gem0__net_status = 32'hE000B008; parameter val_gem0__net_status = 32'h00000004; parameter mask_gem0__net_status = 32'hFFFFFFFD; parameter gem0__user_io = 32'hE000B00C; parameter val_gem0__user_io = 32'h00000000; parameter mask_gem0__user_io = 32'h0000FFFF; parameter gem0__dma_cfg = 32'hE000B010; parameter val_gem0__dma_cfg = 32'h00020784; parameter mask_gem0__dma_cfg = 32'hFFFFFFFF; parameter gem0__tx_status = 32'hE000B014; parameter val_gem0__tx_status = 32'h00000000; parameter mask_gem0__tx_status = 32'hFFFFFFFF; parameter gem0__rx_qbar = 32'hE000B018; parameter val_gem0__rx_qbar = 32'h00000000; parameter mask_gem0__rx_qbar = 32'hFFFFFFFF; parameter gem0__tx_qbar = 32'hE000B01C; parameter val_gem0__tx_qbar = 32'h00000000; parameter mask_gem0__tx_qbar = 32'hFFFFFFFF; parameter gem0__rx_status = 32'hE000B020; parameter val_gem0__rx_status = 32'h00000000; parameter mask_gem0__rx_status = 32'hFFFFFFFF; parameter gem0__intr_status = 32'hE000B024; parameter val_gem0__intr_status = 32'h00000000; parameter mask_gem0__intr_status = 32'hFFFFFFFF; parameter gem0__intr_en = 32'hE000B028; parameter val_gem0__intr_en = 32'h00000000; parameter mask_gem0__intr_en = 32'h00000000; parameter gem0__intr_dis = 32'hE000B02C; parameter val_gem0__intr_dis = 32'h00000000; parameter mask_gem0__intr_dis = 32'h00000000; parameter gem0__intr_mask = 32'hE000B030; parameter val_gem0__intr_mask = 32'h0001FFFF; parameter mask_gem0__intr_mask = 32'hFC01FFFF; parameter gem0__phy_maint = 32'hE000B034; parameter val_gem0__phy_maint = 32'h00000000; parameter mask_gem0__phy_maint = 32'hFFFFFFFF; parameter gem0__rx_pauseq = 32'hE000B038; parameter val_gem0__rx_pauseq = 32'h00000000; parameter mask_gem0__rx_pauseq = 32'hFFFFFFFF; parameter gem0__tx_pauseq = 32'hE000B03C; parameter val_gem0__tx_pauseq = 32'h0000FFFF; parameter mask_gem0__tx_pauseq = 32'hFFFFFFFF; parameter gem0__tx_partial_st_fwd = 32'hE000B040; parameter val_gem0__tx_partial_st_fwd = 32'h000003FF; parameter mask_gem0__tx_partial_st_fwd = 32'hFFFFFFFF; parameter gem0__rx_partial_st_fwd = 32'hE000B044; parameter val_gem0__rx_partial_st_fwd = 32'h000003FF; parameter mask_gem0__rx_partial_st_fwd = 32'hFFFFFFFF; parameter gem0__hash_bot = 32'hE000B080; parameter val_gem0__hash_bot = 32'h00000000; parameter mask_gem0__hash_bot = 32'hFFFFFFFF; parameter gem0__hash_top = 32'hE000B084; parameter val_gem0__hash_top = 32'h00000000; parameter mask_gem0__hash_top = 32'hFFFFFFFF; parameter gem0__spec_addr1_bot = 32'hE000B088; parameter val_gem0__spec_addr1_bot = 32'h00000000; parameter mask_gem0__spec_addr1_bot = 32'hFFFFFFFF; parameter gem0__spec_addr1_top = 32'hE000B08C; parameter val_gem0__spec_addr1_top = 32'h00000000; parameter mask_gem0__spec_addr1_top = 32'hFFFFFFFF; parameter gem0__spec_addr2_bot = 32'hE000B090; parameter val_gem0__spec_addr2_bot = 32'h00000000; parameter mask_gem0__spec_addr2_bot = 32'hFFFFFFFF; parameter gem0__spec_addr2_top = 32'hE000B094; parameter val_gem0__spec_addr2_top = 32'h00000000; parameter mask_gem0__spec_addr2_top = 32'hFFFFFFFF; parameter gem0__spec_addr3_bot = 32'hE000B098; parameter val_gem0__spec_addr3_bot = 32'h00000000; parameter mask_gem0__spec_addr3_bot = 32'hFFFFFFFF; parameter gem0__spec_addr3_top = 32'hE000B09C; parameter val_gem0__spec_addr3_top = 32'h00000000; parameter mask_gem0__spec_addr3_top = 32'hFFFFFFFF; parameter gem0__spec_addr4_bot = 32'hE000B0A0; parameter val_gem0__spec_addr4_bot = 32'h00000000; parameter mask_gem0__spec_addr4_bot = 32'hFFFFFFFF; parameter gem0__spec_addr4_top = 32'hE000B0A4; parameter val_gem0__spec_addr4_top = 32'h00000000; parameter mask_gem0__spec_addr4_top = 32'hFFFFFFFF; parameter gem0__type_id_match1 = 32'hE000B0A8; parameter val_gem0__type_id_match1 = 32'h00000000; parameter mask_gem0__type_id_match1 = 32'hFFFFFFFF; parameter gem0__type_id_match2 = 32'hE000B0AC; parameter val_gem0__type_id_match2 = 32'h00000000; parameter mask_gem0__type_id_match2 = 32'hFFFFFFFF; parameter gem0__type_id_match3 = 32'hE000B0B0; parameter val_gem0__type_id_match3 = 32'h00000000; parameter mask_gem0__type_id_match3 = 32'hFFFFFFFF; parameter gem0__type_id_match4 = 32'hE000B0B4; parameter val_gem0__type_id_match4 = 32'h00000000; parameter mask_gem0__type_id_match4 = 32'hFFFFFFFF; parameter gem0__wake_on_lan = 32'hE000B0B8; parameter val_gem0__wake_on_lan = 32'h00000000; parameter mask_gem0__wake_on_lan = 32'hFFFFFFFF; parameter gem0__ipg_stretch = 32'hE000B0BC; parameter val_gem0__ipg_stretch = 32'h00000000; parameter mask_gem0__ipg_stretch = 32'hFFFFFFFF; parameter gem0__stacked_vlan = 32'hE000B0C0; parameter val_gem0__stacked_vlan = 32'h00000000; parameter mask_gem0__stacked_vlan = 32'hFFFFFFFF; parameter gem0__tx_pfc_pause = 32'hE000B0C4; parameter val_gem0__tx_pfc_pause = 32'h00000000; parameter mask_gem0__tx_pfc_pause = 32'hFFFFFFFF; parameter gem0__spec_addr1_mask_bot = 32'hE000B0C8; parameter val_gem0__spec_addr1_mask_bot = 32'h00000000; parameter mask_gem0__spec_addr1_mask_bot = 32'hFFFFFFFF; parameter gem0__spec_addr1_mask_top = 32'hE000B0CC; parameter val_gem0__spec_addr1_mask_top = 32'h00000000; parameter mask_gem0__spec_addr1_mask_top = 32'hFFFFFFFF; parameter gem0__module_id = 32'hE000B0FC; parameter val_gem0__module_id = 32'h00020118; parameter mask_gem0__module_id = 32'hFFFFFFFF; parameter gem0__octets_tx_bot = 32'hE000B100; parameter val_gem0__octets_tx_bot = 32'h00000000; parameter mask_gem0__octets_tx_bot = 32'hFFFFFFFF; parameter gem0__octets_tx_top = 32'hE000B104; parameter val_gem0__octets_tx_top = 32'h00000000; parameter mask_gem0__octets_tx_top = 32'hFFFFFFFF; parameter gem0__frames_tx = 32'hE000B108; parameter val_gem0__frames_tx = 32'h00000000; parameter mask_gem0__frames_tx = 32'hFFFFFFFF; parameter gem0__broadcast_frames_tx = 32'hE000B10C; parameter val_gem0__broadcast_frames_tx = 32'h00000000; parameter mask_gem0__broadcast_frames_tx = 32'hFFFFFFFF; parameter gem0__multi_frames_tx = 32'hE000B110; parameter val_gem0__multi_frames_tx = 32'h00000000; parameter mask_gem0__multi_frames_tx = 32'hFFFFFFFF; parameter gem0__pause_frames_tx = 32'hE000B114; parameter val_gem0__pause_frames_tx = 32'h00000000; parameter mask_gem0__pause_frames_tx = 32'hFFFFFFFF; parameter gem0__frames_64b_tx = 32'hE000B118; parameter val_gem0__frames_64b_tx = 32'h00000000; parameter mask_gem0__frames_64b_tx = 32'hFFFFFFFF; parameter gem0__frames_65to127b_tx = 32'hE000B11C; parameter val_gem0__frames_65to127b_tx = 32'h00000000; parameter mask_gem0__frames_65to127b_tx = 32'hFFFFFFFF; parameter gem0__frames_128to255b_tx = 32'hE000B120; parameter val_gem0__frames_128to255b_tx = 32'h00000000; parameter mask_gem0__frames_128to255b_tx = 32'hFFFFFFFF; parameter gem0__frames_256to511b_tx = 32'hE000B124; parameter val_gem0__frames_256to511b_tx = 32'h00000000; parameter mask_gem0__frames_256to511b_tx = 32'hFFFFFFFF; parameter gem0__frames_512to1023b_tx = 32'hE000B128; parameter val_gem0__frames_512to1023b_tx = 32'h00000000; parameter mask_gem0__frames_512to1023b_tx = 32'hFFFFFFFF; parameter gem0__frames_1024to1518b_tx = 32'hE000B12C; parameter val_gem0__frames_1024to1518b_tx = 32'h00000000; parameter mask_gem0__frames_1024to1518b_tx = 32'hFFFFFFFF; parameter gem0__frames_gt1518b_tx = 32'hE000B130; parameter val_gem0__frames_gt1518b_tx = 32'h00000000; parameter mask_gem0__frames_gt1518b_tx = 32'hFFFFFFFF; parameter gem0__tx_under_runs = 32'hE000B134; parameter val_gem0__tx_under_runs = 32'h00000000; parameter mask_gem0__tx_under_runs = 32'hFFFFFFFF; parameter gem0__single_collisn_frames = 32'hE000B138; parameter val_gem0__single_collisn_frames = 32'h00000000; parameter mask_gem0__single_collisn_frames = 32'hFFFFFFFF; parameter gem0__multi_collisn_frames = 32'hE000B13C; parameter val_gem0__multi_collisn_frames = 32'h00000000; parameter mask_gem0__multi_collisn_frames = 32'hFFFFFFFF; parameter gem0__excessive_collisns = 32'hE000B140; parameter val_gem0__excessive_collisns = 32'h00000000; parameter mask_gem0__excessive_collisns = 32'hFFFFFFFF; parameter gem0__late_collisns = 32'hE000B144; parameter val_gem0__late_collisns = 32'h00000000; parameter mask_gem0__late_collisns = 32'hFFFFFFFF; parameter gem0__deferred_tx_frames = 32'hE000B148; parameter val_gem0__deferred_tx_frames = 32'h00000000; parameter mask_gem0__deferred_tx_frames = 32'hFFFFFFFF; parameter gem0__carrier_sense_errs = 32'hE000B14C; parameter val_gem0__carrier_sense_errs = 32'h00000000; parameter mask_gem0__carrier_sense_errs = 32'hFFFFFFFF; parameter gem0__octets_rx_bot = 32'hE000B150; parameter val_gem0__octets_rx_bot = 32'h00000000; parameter mask_gem0__octets_rx_bot = 32'hFFFFFFFF; parameter gem0__octets_rx_top = 32'hE000B154; parameter val_gem0__octets_rx_top = 32'h00000000; parameter mask_gem0__octets_rx_top = 32'hFFFFFFFF; parameter gem0__frames_rx = 32'hE000B158; parameter val_gem0__frames_rx = 32'h00000000; parameter mask_gem0__frames_rx = 32'hFFFFFFFF; parameter gem0__bdcast_fames_rx = 32'hE000B15C; parameter val_gem0__bdcast_fames_rx = 32'h00000000; parameter mask_gem0__bdcast_fames_rx = 32'hFFFFFFFF; parameter gem0__multi_frames_rx = 32'hE000B160; parameter val_gem0__multi_frames_rx = 32'h00000000; parameter mask_gem0__multi_frames_rx = 32'hFFFFFFFF; parameter gem0__pause_rx = 32'hE000B164; parameter val_gem0__pause_rx = 32'h00000000; parameter mask_gem0__pause_rx = 32'hFFFFFFFF; parameter gem0__frames_64b_rx = 32'hE000B168; parameter val_gem0__frames_64b_rx = 32'h00000000; parameter mask_gem0__frames_64b_rx = 32'hFFFFFFFF; parameter gem0__frames_65to127b_rx = 32'hE000B16C; parameter val_gem0__frames_65to127b_rx = 32'h00000000; parameter mask_gem0__frames_65to127b_rx = 32'hFFFFFFFF; parameter gem0__frames_128to255b_rx = 32'hE000B170; parameter val_gem0__frames_128to255b_rx = 32'h00000000; parameter mask_gem0__frames_128to255b_rx = 32'hFFFFFFFF; parameter gem0__frames_256to511b_rx = 32'hE000B174; parameter val_gem0__frames_256to511b_rx = 32'h00000000; parameter mask_gem0__frames_256to511b_rx = 32'hFFFFFFFF; parameter gem0__frames_512to1023b_rx = 32'hE000B178; parameter val_gem0__frames_512to1023b_rx = 32'h00000000; parameter mask_gem0__frames_512to1023b_rx = 32'hFFFFFFFF; parameter gem0__frames_1024to1518b_rx = 32'hE000B17C; parameter val_gem0__frames_1024to1518b_rx = 32'h00000000; parameter mask_gem0__frames_1024to1518b_rx = 32'hFFFFFFFF; parameter gem0__frames_gt1518b_rx = 32'hE000B180; parameter val_gem0__frames_gt1518b_rx = 32'h00000000; parameter mask_gem0__frames_gt1518b_rx = 32'hFFFFFFFF; parameter gem0__undersz_rx = 32'hE000B184; parameter val_gem0__undersz_rx = 32'h00000000; parameter mask_gem0__undersz_rx = 32'hFFFFFFFF; parameter gem0__oversz_rx = 32'hE000B188; parameter val_gem0__oversz_rx = 32'h00000000; parameter mask_gem0__oversz_rx = 32'hFFFFFFFF; parameter gem0__jab_rx = 32'hE000B18C; parameter val_gem0__jab_rx = 32'h00000000; parameter mask_gem0__jab_rx = 32'hFFFFFFFF; parameter gem0__fcs_errors = 32'hE000B190; parameter val_gem0__fcs_errors = 32'h00000000; parameter mask_gem0__fcs_errors = 32'hFFFFFFFF; parameter gem0__length_field_errors = 32'hE000B194; parameter val_gem0__length_field_errors = 32'h00000000; parameter mask_gem0__length_field_errors = 32'hFFFFFFFF; parameter gem0__rx_symbol_errors = 32'hE000B198; parameter val_gem0__rx_symbol_errors = 32'h00000000; parameter mask_gem0__rx_symbol_errors = 32'hFFFFFFFF; parameter gem0__align_errors = 32'hE000B19C; parameter val_gem0__align_errors = 32'h00000000; parameter mask_gem0__align_errors = 32'hFFFFFFFF; parameter gem0__rx_resource_errors = 32'hE000B1A0; parameter val_gem0__rx_resource_errors = 32'h00000000; parameter mask_gem0__rx_resource_errors = 32'hFFFFFFFF; parameter gem0__rx_overrun_errors = 32'hE000B1A4; parameter val_gem0__rx_overrun_errors = 32'h00000000; parameter mask_gem0__rx_overrun_errors = 32'hFFFFFFFF; parameter gem0__ip_hdr_csum_errors = 32'hE000B1A8; parameter val_gem0__ip_hdr_csum_errors = 32'h00000000; parameter mask_gem0__ip_hdr_csum_errors = 32'hFFFFFFFF; parameter gem0__tcp_csum_errors = 32'hE000B1AC; parameter val_gem0__tcp_csum_errors = 32'h00000000; parameter mask_gem0__tcp_csum_errors = 32'hFFFFFFFF; parameter gem0__udp_csum_errors = 32'hE000B1B0; parameter val_gem0__udp_csum_errors = 32'h00000000; parameter mask_gem0__udp_csum_errors = 32'hFFFFFFFF; parameter gem0__timer_strobe_s = 32'hE000B1C8; parameter val_gem0__timer_strobe_s = 32'h00000000; parameter mask_gem0__timer_strobe_s = 32'hFFFFFFFF; parameter gem0__timer_strobe_ns = 32'hE000B1CC; parameter val_gem0__timer_strobe_ns = 32'h00000000; parameter mask_gem0__timer_strobe_ns = 32'hFFFFFFFF; parameter gem0__timer_s = 32'hE000B1D0; parameter val_gem0__timer_s = 32'h00000000; parameter mask_gem0__timer_s = 32'hFFFFFFFF; parameter gem0__timer_ns = 32'hE000B1D4; parameter val_gem0__timer_ns = 32'h00000000; parameter mask_gem0__timer_ns = 32'hFFFFFFFF; parameter gem0__timer_adjust = 32'hE000B1D8; parameter val_gem0__timer_adjust = 32'h00000000; parameter mask_gem0__timer_adjust = 32'hFFFFFFFF; parameter gem0__timer_incr = 32'hE000B1DC; parameter val_gem0__timer_incr = 32'h00000000; parameter mask_gem0__timer_incr = 32'hFFFFFFFF; parameter gem0__ptp_tx_s = 32'hE000B1E0; parameter val_gem0__ptp_tx_s = 32'h00000000; parameter mask_gem0__ptp_tx_s = 32'hFFFFFFFF; parameter gem0__ptp_tx_ns = 32'hE000B1E4; parameter val_gem0__ptp_tx_ns = 32'h00000000; parameter mask_gem0__ptp_tx_ns = 32'hFFFFFFFF; parameter gem0__ptp_rx_s = 32'hE000B1E8; parameter val_gem0__ptp_rx_s = 32'h00000000; parameter mask_gem0__ptp_rx_s = 32'hFFFFFFFF; parameter gem0__ptp_rx_ns = 32'hE000B1EC; parameter val_gem0__ptp_rx_ns = 32'h00000000; parameter mask_gem0__ptp_rx_ns = 32'hFFFFFFFF; parameter gem0__ptp_peer_tx_s = 32'hE000B1F0; parameter val_gem0__ptp_peer_tx_s = 32'h00000000; parameter mask_gem0__ptp_peer_tx_s = 32'hFFFFFFFF; parameter gem0__ptp_peer_tx_ns = 32'hE000B1F4; parameter val_gem0__ptp_peer_tx_ns = 32'h00000000; parameter mask_gem0__ptp_peer_tx_ns = 32'hFFFFFFFF; parameter gem0__ptp_peer_rx_s = 32'hE000B1F8; parameter val_gem0__ptp_peer_rx_s = 32'h00000000; parameter mask_gem0__ptp_peer_rx_s = 32'hFFFFFFFF; parameter gem0__ptp_peer_rx_ns = 32'hE000B1FC; parameter val_gem0__ptp_peer_rx_ns = 32'h00000000; parameter mask_gem0__ptp_peer_rx_ns = 32'hFFFFFFFF; parameter gem0__pcs_ctrl = 32'hE000B200; parameter val_gem0__pcs_ctrl = 32'h00000000; parameter mask_gem0__pcs_ctrl = 32'h00000000; parameter gem0__pcs_status = 32'hE000B204; parameter val_gem0__pcs_status = 32'h00000000; parameter mask_gem0__pcs_status = 32'h00000000; parameter gem0__pcs_upper_phy_id = 32'hE000B208; parameter val_gem0__pcs_upper_phy_id = 32'h00000000; parameter mask_gem0__pcs_upper_phy_id = 32'h00000000; parameter gem0__pcs_lower_phy_id = 32'hE000B20C; parameter val_gem0__pcs_lower_phy_id = 32'h00000000; parameter mask_gem0__pcs_lower_phy_id = 32'h00000000; parameter gem0__pcs_autoneg_ad = 32'hE000B210; parameter val_gem0__pcs_autoneg_ad = 32'h00000000; parameter mask_gem0__pcs_autoneg_ad = 32'h00000000; parameter gem0__pcs_autoneg_ability = 32'hE000B214; parameter val_gem0__pcs_autoneg_ability = 32'h00000000; parameter mask_gem0__pcs_autoneg_ability = 32'h00000000; parameter gem0__pcs_autonec_exp = 32'hE000B218; parameter val_gem0__pcs_autonec_exp = 32'h00000000; parameter mask_gem0__pcs_autonec_exp = 32'h00000000; parameter gem0__pcs_autoneg_next_pg = 32'hE000B21C; parameter val_gem0__pcs_autoneg_next_pg = 32'h00000000; parameter mask_gem0__pcs_autoneg_next_pg = 32'h00000000; parameter gem0__pcs_autoneg_pnext_pg = 32'hE000B220; parameter val_gem0__pcs_autoneg_pnext_pg = 32'h00000000; parameter mask_gem0__pcs_autoneg_pnext_pg = 32'h00000000; parameter gem0__pcs_extended_status = 32'hE000B23C; parameter val_gem0__pcs_extended_status = 32'h00000000; parameter mask_gem0__pcs_extended_status = 32'h00000000; parameter gem0__design_cfg1 = 32'hE000B280; parameter val_gem0__design_cfg1 = 32'h02000000; parameter mask_gem0__design_cfg1 = 32'h0E000000; parameter gem0__design_cfg2 = 32'hE000B284; parameter val_gem0__design_cfg2 = 32'h2A813FFF; parameter mask_gem0__design_cfg2 = 32'h3FCFFFFF; parameter gem0__design_cfg3 = 32'hE000B288; parameter val_gem0__design_cfg3 = 32'h00000000; parameter mask_gem0__design_cfg3 = 32'hFFFFFFFF; parameter gem0__design_cfg4 = 32'hE000B28C; parameter val_gem0__design_cfg4 = 32'h00000000; parameter mask_gem0__design_cfg4 = 32'hFFFFFFFF; parameter gem0__design_cfg5 = 32'hE000B290; parameter val_gem0__design_cfg5 = 32'h002F2045; parameter mask_gem0__design_cfg5 = 32'h0FFFFCFF; parameter gem0__design_cfg6 = 32'hE000B294; parameter val_gem0__design_cfg6 = 32'h00000000; parameter mask_gem0__design_cfg6 = 32'h00000000; parameter gem0__design_cfg7 = 32'hE000B298; parameter val_gem0__design_cfg7 = 32'h00000000; parameter mask_gem0__design_cfg7 = 32'h00000000; parameter gem0__isr_pq1 = 32'hE000B400; parameter val_gem0__isr_pq1 = 32'h00000000; parameter mask_gem0__isr_pq1 = 32'h00000000; parameter gem0__isr_pq2 = 32'hE000B404; parameter val_gem0__isr_pq2 = 32'h00000000; parameter mask_gem0__isr_pq2 = 32'h00000000; parameter gem0__isr_pq3 = 32'hE000B408; parameter val_gem0__isr_pq3 = 32'h00000000; parameter mask_gem0__isr_pq3 = 32'h00000000; parameter gem0__isr_pq4 = 32'hE000B40C; parameter val_gem0__isr_pq4 = 32'h00000000; parameter mask_gem0__isr_pq4 = 32'h00000000; parameter gem0__isr_pq5 = 32'hE000B410; parameter val_gem0__isr_pq5 = 32'h00000000; parameter mask_gem0__isr_pq5 = 32'h00000000; parameter gem0__isr_pq6 = 32'hE000B414; parameter val_gem0__isr_pq6 = 32'h00000000; parameter mask_gem0__isr_pq6 = 32'h00000000; parameter gem0__isr_pq7 = 32'hE000B418; parameter val_gem0__isr_pq7 = 32'h00000000; parameter mask_gem0__isr_pq7 = 32'h00000000; parameter gem0__tx_qbar_q1 = 32'hE000B440; parameter val_gem0__tx_qbar_q1 = 32'h00000000; parameter mask_gem0__tx_qbar_q1 = 32'h00000000; parameter gem0__tx_qbar_q2 = 32'hE000B444; parameter val_gem0__tx_qbar_q2 = 32'h00000000; parameter mask_gem0__tx_qbar_q2 = 32'h00000000; parameter gem0__tx_qbar_q3 = 32'hE000B448; parameter val_gem0__tx_qbar_q3 = 32'h00000000; parameter mask_gem0__tx_qbar_q3 = 32'h00000000; parameter gem0__tx_qbar_q4 = 32'hE000B44C; parameter val_gem0__tx_qbar_q4 = 32'h00000000; parameter mask_gem0__tx_qbar_q4 = 32'h00000000; parameter gem0__tx_qbar_q5 = 32'hE000B450; parameter val_gem0__tx_qbar_q5 = 32'h00000000; parameter mask_gem0__tx_qbar_q5 = 32'h00000000; parameter gem0__tx_qbar_q6 = 32'hE000B454; parameter val_gem0__tx_qbar_q6 = 32'h00000000; parameter mask_gem0__tx_qbar_q6 = 32'h00000000; parameter gem0__tx_qbar_q7 = 32'hE000B458; parameter val_gem0__tx_qbar_q7 = 32'h00000000; parameter mask_gem0__tx_qbar_q7 = 32'h00000000; parameter gem0__rx_qbar_q1 = 32'hE000B480; parameter val_gem0__rx_qbar_q1 = 32'h00000000; parameter mask_gem0__rx_qbar_q1 = 32'h00000000; parameter gem0__rx_qbar_q2 = 32'hE000B484; parameter val_gem0__rx_qbar_q2 = 32'h00000000; parameter mask_gem0__rx_qbar_q2 = 32'h00000000; parameter gem0__rx_qbar_q3 = 32'hE000B488; parameter val_gem0__rx_qbar_q3 = 32'h00000000; parameter mask_gem0__rx_qbar_q3 = 32'h00000000; parameter gem0__rx_qbar_q4 = 32'hE000B48C; parameter val_gem0__rx_qbar_q4 = 32'h00000000; parameter mask_gem0__rx_qbar_q4 = 32'h00000000; parameter gem0__rx_qbar_q5 = 32'hE000B490; parameter val_gem0__rx_qbar_q5 = 32'h00000000; parameter mask_gem0__rx_qbar_q5 = 32'h00000000; parameter gem0__rx_qbar_q6 = 32'hE000B494; parameter val_gem0__rx_qbar_q6 = 32'h00000000; parameter mask_gem0__rx_qbar_q6 = 32'h00000000; parameter gem0__rx_qbar_q7 = 32'hE000B498; parameter val_gem0__rx_qbar_q7 = 32'h00000000; parameter mask_gem0__rx_qbar_q7 = 32'h00000000; parameter gem0__rx_bufsz_q1 = 32'hE000B4A0; parameter val_gem0__rx_bufsz_q1 = 32'h00000000; parameter mask_gem0__rx_bufsz_q1 = 32'h00000000; parameter gem0__rx_bufsz_q2 = 32'hE000B4A4; parameter val_gem0__rx_bufsz_q2 = 32'h00000000; parameter mask_gem0__rx_bufsz_q2 = 32'h00000000; parameter gem0__rx_bufsz_q3 = 32'hE000B4A8; parameter val_gem0__rx_bufsz_q3 = 32'h00000000; parameter mask_gem0__rx_bufsz_q3 = 32'h00000000; parameter gem0__rx_bufsz_q4 = 32'hE000B4AC; parameter val_gem0__rx_bufsz_q4 = 32'h00000000; parameter mask_gem0__rx_bufsz_q4 = 32'h00000000; parameter gem0__rx_bufsz_q5 = 32'hE000B4B0; parameter val_gem0__rx_bufsz_q5 = 32'h00000000; parameter mask_gem0__rx_bufsz_q5 = 32'h00000000; parameter gem0__rx_bufsz_q6 = 32'hE000B4B4; parameter val_gem0__rx_bufsz_q6 = 32'h00000000; parameter mask_gem0__rx_bufsz_q6 = 32'h00000000; parameter gem0__rx_bufsz_q7 = 32'hE000B4B8; parameter val_gem0__rx_bufsz_q7 = 32'h00000000; parameter mask_gem0__rx_bufsz_q7 = 32'h00000000; parameter gem0__screen_t1_r0 = 32'hE000B500; parameter val_gem0__screen_t1_r0 = 32'h00000000; parameter mask_gem0__screen_t1_r0 = 32'h00000000; parameter gem0__screen_t1_r1 = 32'hE000B504; parameter val_gem0__screen_t1_r1 = 32'h00000000; parameter mask_gem0__screen_t1_r1 = 32'h00000000; parameter gem0__screen_t1_r2 = 32'hE000B508; parameter val_gem0__screen_t1_r2 = 32'h00000000; parameter mask_gem0__screen_t1_r2 = 32'h00000000; parameter gem0__screen_t1_r3 = 32'hE000B50C; parameter val_gem0__screen_t1_r3 = 32'h00000000; parameter mask_gem0__screen_t1_r3 = 32'h00000000; parameter gem0__screen_t1_r4 = 32'hE000B510; parameter val_gem0__screen_t1_r4 = 32'h00000000; parameter mask_gem0__screen_t1_r4 = 32'h00000000; parameter gem0__screen_t1_r5 = 32'hE000B514; parameter val_gem0__screen_t1_r5 = 32'h00000000; parameter mask_gem0__screen_t1_r5 = 32'h00000000; parameter gem0__screen_t1_r6 = 32'hE000B518; parameter val_gem0__screen_t1_r6 = 32'h00000000; parameter mask_gem0__screen_t1_r6 = 32'h00000000; parameter gem0__screen_t1_r7 = 32'hE000B51C; parameter val_gem0__screen_t1_r7 = 32'h00000000; parameter mask_gem0__screen_t1_r7 = 32'h00000000; parameter gem0__screen_t1_r8 = 32'hE000B520; parameter val_gem0__screen_t1_r8 = 32'h00000000; parameter mask_gem0__screen_t1_r8 = 32'h00000000; parameter gem0__screen_t1_r9 = 32'hE000B524; parameter val_gem0__screen_t1_r9 = 32'h00000000; parameter mask_gem0__screen_t1_r9 = 32'h00000000; parameter gem0__screen_t1_r10 = 32'hE000B528; parameter val_gem0__screen_t1_r10 = 32'h00000000; parameter mask_gem0__screen_t1_r10 = 32'h00000000; parameter gem0__screen_t1_r11 = 32'hE000B52C; parameter val_gem0__screen_t1_r11 = 32'h00000000; parameter mask_gem0__screen_t1_r11 = 32'h00000000; parameter gem0__screen_t1_r12 = 32'hE000B530; parameter val_gem0__screen_t1_r12 = 32'h00000000; parameter mask_gem0__screen_t1_r12 = 32'h00000000; parameter gem0__screen_t1_r13 = 32'hE000B534; parameter val_gem0__screen_t1_r13 = 32'h00000000; parameter mask_gem0__screen_t1_r13 = 32'h00000000; parameter gem0__screen_t1_r14 = 32'hE000B538; parameter val_gem0__screen_t1_r14 = 32'h00000000; parameter mask_gem0__screen_t1_r14 = 32'h00000000; parameter gem0__screen_t1_r15 = 32'hE000B53C; parameter val_gem0__screen_t1_r15 = 32'h00000000; parameter mask_gem0__screen_t1_r15 = 32'h00000000; parameter gem0__screen_t2_r0 = 32'hE000B540; parameter val_gem0__screen_t2_r0 = 32'h00000000; parameter mask_gem0__screen_t2_r0 = 32'h00000000; parameter gem0__screen_t2_r1 = 32'hE000B544; parameter val_gem0__screen_t2_r1 = 32'h00000000; parameter mask_gem0__screen_t2_r1 = 32'h00000000; parameter gem0__screen_t2_r2 = 32'hE000B548; parameter val_gem0__screen_t2_r2 = 32'h00000000; parameter mask_gem0__screen_t2_r2 = 32'h00000000; parameter gem0__screen_t2_r3 = 32'hE000B54C; parameter val_gem0__screen_t2_r3 = 32'h00000000; parameter mask_gem0__screen_t2_r3 = 32'h00000000; parameter gem0__screen_t2_r4 = 32'hE000B550; parameter val_gem0__screen_t2_r4 = 32'h00000000; parameter mask_gem0__screen_t2_r4 = 32'h00000000; parameter gem0__screen_t2_r5 = 32'hE000B554; parameter val_gem0__screen_t2_r5 = 32'h00000000; parameter mask_gem0__screen_t2_r5 = 32'h00000000; parameter gem0__screen_t2_r6 = 32'hE000B558; parameter val_gem0__screen_t2_r6 = 32'h00000000; parameter mask_gem0__screen_t2_r6 = 32'h00000000; parameter gem0__screen_t2_r7 = 32'hE000B55C; parameter val_gem0__screen_t2_r7 = 32'h00000000; parameter mask_gem0__screen_t2_r7 = 32'h00000000; parameter gem0__screen_t2_r8 = 32'hE000B560; parameter val_gem0__screen_t2_r8 = 32'h00000000; parameter mask_gem0__screen_t2_r8 = 32'h00000000; parameter gem0__screen_t2_r9 = 32'hE000B564; parameter val_gem0__screen_t2_r9 = 32'h00000000; parameter mask_gem0__screen_t2_r9 = 32'h00000000; parameter gem0__screen_t2_r10 = 32'hE000B568; parameter val_gem0__screen_t2_r10 = 32'h00000000; parameter mask_gem0__screen_t2_r10 = 32'h00000000; parameter gem0__screen_t2_r11 = 32'hE000B56C; parameter val_gem0__screen_t2_r11 = 32'h00000000; parameter mask_gem0__screen_t2_r11 = 32'h00000000; parameter gem0__screen_t2_r12 = 32'hE000B570; parameter val_gem0__screen_t2_r12 = 32'h00000000; parameter mask_gem0__screen_t2_r12 = 32'h00000000; parameter gem0__screen_t2_r13 = 32'hE000B574; parameter val_gem0__screen_t2_r13 = 32'h00000000; parameter mask_gem0__screen_t2_r13 = 32'h00000000; parameter gem0__screen_t2_r14 = 32'hE000B578; parameter val_gem0__screen_t2_r14 = 32'h00000000; parameter mask_gem0__screen_t2_r14 = 32'h00000000; parameter gem0__screen_t2_r15 = 32'hE000B57C; parameter val_gem0__screen_t2_r15 = 32'h00000000; parameter mask_gem0__screen_t2_r15 = 32'h00000000; parameter gem0__intr_en_pq1 = 32'hE000B600; parameter val_gem0__intr_en_pq1 = 32'h00000000; parameter mask_gem0__intr_en_pq1 = 32'h00000000; parameter gem0__intr_en_pq2 = 32'hE000B604; parameter val_gem0__intr_en_pq2 = 32'h00000000; parameter mask_gem0__intr_en_pq2 = 32'h00000000; parameter gem0__intr_en_pq3 = 32'hE000B608; parameter val_gem0__intr_en_pq3 = 32'h00000000; parameter mask_gem0__intr_en_pq3 = 32'h00000000; parameter gem0__intr_en_pq4 = 32'hE000B60C; parameter val_gem0__intr_en_pq4 = 32'h00000000; parameter mask_gem0__intr_en_pq4 = 32'h00000000; parameter gem0__intr_en_pq5 = 32'hE000B610; parameter val_gem0__intr_en_pq5 = 32'h00000000; parameter mask_gem0__intr_en_pq5 = 32'h00000000; parameter gem0__intr_en_pq6 = 32'hE000B614; parameter val_gem0__intr_en_pq6 = 32'h00000000; parameter mask_gem0__intr_en_pq6 = 32'h00000000; parameter gem0__intr_en_pq7 = 32'hE000B618; parameter val_gem0__intr_en_pq7 = 32'h00000000; parameter mask_gem0__intr_en_pq7 = 32'h00000000; parameter gem0__intr_dis_pq1 = 32'hE000B620; parameter val_gem0__intr_dis_pq1 = 32'h00000000; parameter mask_gem0__intr_dis_pq1 = 32'h00000000; parameter gem0__intr_dis_pq2 = 32'hE000B624; parameter val_gem0__intr_dis_pq2 = 32'h00000000; parameter mask_gem0__intr_dis_pq2 = 32'h00000000; parameter gem0__intr_dis_pq3 = 32'hE000B628; parameter val_gem0__intr_dis_pq3 = 32'h00000000; parameter mask_gem0__intr_dis_pq3 = 32'h00000000; parameter gem0__intr_dis_pq4 = 32'hE000B62C; parameter val_gem0__intr_dis_pq4 = 32'h00000000; parameter mask_gem0__intr_dis_pq4 = 32'h00000000; parameter gem0__intr_dis_pq5 = 32'hE000B630; parameter val_gem0__intr_dis_pq5 = 32'h00000000; parameter mask_gem0__intr_dis_pq5 = 32'h00000000; parameter gem0__intr_dis_pq6 = 32'hE000B634; parameter val_gem0__intr_dis_pq6 = 32'h00000000; parameter mask_gem0__intr_dis_pq6 = 32'h00000000; parameter gem0__intr_dis_pq7 = 32'hE000B638; parameter val_gem0__intr_dis_pq7 = 32'h00000000; parameter mask_gem0__intr_dis_pq7 = 32'h00000000; parameter gem0__intr_mask_pq1 = 32'hE000B640; parameter val_gem0__intr_mask_pq1 = 32'h00000000; parameter mask_gem0__intr_mask_pq1 = 32'h00000000; parameter gem0__intr_mask_pq2 = 32'hE000B644; parameter val_gem0__intr_mask_pq2 = 32'h00000000; parameter mask_gem0__intr_mask_pq2 = 32'h00000000; parameter gem0__intr_mask_pq3 = 32'hE000B648; parameter val_gem0__intr_mask_pq3 = 32'h00000000; parameter mask_gem0__intr_mask_pq3 = 32'h00000000; parameter gem0__intr_mask_pq4 = 32'hE000B64C; parameter val_gem0__intr_mask_pq4 = 32'h00000000; parameter mask_gem0__intr_mask_pq4 = 32'h00000000; parameter gem0__intr_mask_pq5 = 32'hE000B650; parameter val_gem0__intr_mask_pq5 = 32'h00000000; parameter mask_gem0__intr_mask_pq5 = 32'h00000000; parameter gem0__intr_mask_pq6 = 32'hE000B654; parameter val_gem0__intr_mask_pq6 = 32'h00000000; parameter mask_gem0__intr_mask_pq6 = 32'h00000000; parameter gem0__intr_mask_pq7 = 32'hE000B658; parameter val_gem0__intr_mask_pq7 = 32'h00000000; parameter mask_gem0__intr_mask_pq7 = 32'h00000000; // ************************************************************ // Module gem1 GEM // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter gem1__net_ctrl = 32'hE000C000; parameter val_gem1__net_ctrl = 32'h00000000; parameter mask_gem1__net_ctrl = 32'hFFFFFFFF; parameter gem1__net_cfg = 32'hE000C004; parameter val_gem1__net_cfg = 32'h00080000; parameter mask_gem1__net_cfg = 32'hFFFFFFFF; parameter gem1__net_status = 32'hE000C008; parameter val_gem1__net_status = 32'h00000004; parameter mask_gem1__net_status = 32'hFFFFFFFD; parameter gem1__user_io = 32'hE000C00C; parameter val_gem1__user_io = 32'h00000000; parameter mask_gem1__user_io = 32'h0000FFFF; parameter gem1__dma_cfg = 32'hE000C010; parameter val_gem1__dma_cfg = 32'h00020784; parameter mask_gem1__dma_cfg = 32'hFFFFFFFF; parameter gem1__tx_status = 32'hE000C014; parameter val_gem1__tx_status = 32'h00000000; parameter mask_gem1__tx_status = 32'hFFFFFFFF; parameter gem1__rx_qbar = 32'hE000C018; parameter val_gem1__rx_qbar = 32'h00000000; parameter mask_gem1__rx_qbar = 32'hFFFFFFFF; parameter gem1__tx_qbar = 32'hE000C01C; parameter val_gem1__tx_qbar = 32'h00000000; parameter mask_gem1__tx_qbar = 32'hFFFFFFFF; parameter gem1__rx_status = 32'hE000C020; parameter val_gem1__rx_status = 32'h00000000; parameter mask_gem1__rx_status = 32'hFFFFFFFF; parameter gem1__intr_status = 32'hE000C024; parameter val_gem1__intr_status = 32'h00000000; parameter mask_gem1__intr_status = 32'hFFFFFFFF; parameter gem1__intr_en = 32'hE000C028; parameter val_gem1__intr_en = 32'h00000000; parameter mask_gem1__intr_en = 32'h00000000; parameter gem1__intr_dis = 32'hE000C02C; parameter val_gem1__intr_dis = 32'h00000000; parameter mask_gem1__intr_dis = 32'h00000000; parameter gem1__intr_mask = 32'hE000C030; parameter val_gem1__intr_mask = 32'h0001FFFF; parameter mask_gem1__intr_mask = 32'hFC01FFFF; parameter gem1__phy_maint = 32'hE000C034; parameter val_gem1__phy_maint = 32'h00000000; parameter mask_gem1__phy_maint = 32'hFFFFFFFF; parameter gem1__rx_pauseq = 32'hE000C038; parameter val_gem1__rx_pauseq = 32'h00000000; parameter mask_gem1__rx_pauseq = 32'hFFFFFFFF; parameter gem1__tx_pauseq = 32'hE000C03C; parameter val_gem1__tx_pauseq = 32'h0000FFFF; parameter mask_gem1__tx_pauseq = 32'hFFFFFFFF; parameter gem1__tx_partial_st_fwd = 32'hE000C040; parameter val_gem1__tx_partial_st_fwd = 32'h000003FF; parameter mask_gem1__tx_partial_st_fwd = 32'hFFFFFFFF; parameter gem1__rx_partial_st_fwd = 32'hE000C044; parameter val_gem1__rx_partial_st_fwd = 32'h000003FF; parameter mask_gem1__rx_partial_st_fwd = 32'hFFFFFFFF; parameter gem1__hash_bot = 32'hE000C080; parameter val_gem1__hash_bot = 32'h00000000; parameter mask_gem1__hash_bot = 32'hFFFFFFFF; parameter gem1__hash_top = 32'hE000C084; parameter val_gem1__hash_top = 32'h00000000; parameter mask_gem1__hash_top = 32'hFFFFFFFF; parameter gem1__spec_addr1_bot = 32'hE000C088; parameter val_gem1__spec_addr1_bot = 32'h00000000; parameter mask_gem1__spec_addr1_bot = 32'hFFFFFFFF; parameter gem1__spec_addr1_top = 32'hE000C08C; parameter val_gem1__spec_addr1_top = 32'h00000000; parameter mask_gem1__spec_addr1_top = 32'hFFFFFFFF; parameter gem1__spec_addr2_bot = 32'hE000C090; parameter val_gem1__spec_addr2_bot = 32'h00000000; parameter mask_gem1__spec_addr2_bot = 32'hFFFFFFFF; parameter gem1__spec_addr2_top = 32'hE000C094; parameter val_gem1__spec_addr2_top = 32'h00000000; parameter mask_gem1__spec_addr2_top = 32'hFFFFFFFF; parameter gem1__spec_addr3_bot = 32'hE000C098; parameter val_gem1__spec_addr3_bot = 32'h00000000; parameter mask_gem1__spec_addr3_bot = 32'hFFFFFFFF; parameter gem1__spec_addr3_top = 32'hE000C09C; parameter val_gem1__spec_addr3_top = 32'h00000000; parameter mask_gem1__spec_addr3_top = 32'hFFFFFFFF; parameter gem1__spec_addr4_bot = 32'hE000C0A0; parameter val_gem1__spec_addr4_bot = 32'h00000000; parameter mask_gem1__spec_addr4_bot = 32'hFFFFFFFF; parameter gem1__spec_addr4_top = 32'hE000C0A4; parameter val_gem1__spec_addr4_top = 32'h00000000; parameter mask_gem1__spec_addr4_top = 32'hFFFFFFFF; parameter gem1__type_id_match1 = 32'hE000C0A8; parameter val_gem1__type_id_match1 = 32'h00000000; parameter mask_gem1__type_id_match1 = 32'hFFFFFFFF; parameter gem1__type_id_match2 = 32'hE000C0AC; parameter val_gem1__type_id_match2 = 32'h00000000; parameter mask_gem1__type_id_match2 = 32'hFFFFFFFF; parameter gem1__type_id_match3 = 32'hE000C0B0; parameter val_gem1__type_id_match3 = 32'h00000000; parameter mask_gem1__type_id_match3 = 32'hFFFFFFFF; parameter gem1__type_id_match4 = 32'hE000C0B4; parameter val_gem1__type_id_match4 = 32'h00000000; parameter mask_gem1__type_id_match4 = 32'hFFFFFFFF; parameter gem1__wake_on_lan = 32'hE000C0B8; parameter val_gem1__wake_on_lan = 32'h00000000; parameter mask_gem1__wake_on_lan = 32'hFFFFFFFF; parameter gem1__ipg_stretch = 32'hE000C0BC; parameter val_gem1__ipg_stretch = 32'h00000000; parameter mask_gem1__ipg_stretch = 32'hFFFFFFFF; parameter gem1__stacked_vlan = 32'hE000C0C0; parameter val_gem1__stacked_vlan = 32'h00000000; parameter mask_gem1__stacked_vlan = 32'hFFFFFFFF; parameter gem1__tx_pfc_pause = 32'hE000C0C4; parameter val_gem1__tx_pfc_pause = 32'h00000000; parameter mask_gem1__tx_pfc_pause = 32'hFFFFFFFF; parameter gem1__spec_addr1_mask_bot = 32'hE000C0C8; parameter val_gem1__spec_addr1_mask_bot = 32'h00000000; parameter mask_gem1__spec_addr1_mask_bot = 32'hFFFFFFFF; parameter gem1__spec_addr1_mask_top = 32'hE000C0CC; parameter val_gem1__spec_addr1_mask_top = 32'h00000000; parameter mask_gem1__spec_addr1_mask_top = 32'hFFFFFFFF; parameter gem1__module_id = 32'hE000C0FC; parameter val_gem1__module_id = 32'h00020118; parameter mask_gem1__module_id = 32'hFFFFFFFF; parameter gem1__octets_tx_bot = 32'hE000C100; parameter val_gem1__octets_tx_bot = 32'h00000000; parameter mask_gem1__octets_tx_bot = 32'hFFFFFFFF; parameter gem1__octets_tx_top = 32'hE000C104; parameter val_gem1__octets_tx_top = 32'h00000000; parameter mask_gem1__octets_tx_top = 32'hFFFFFFFF; parameter gem1__frames_tx = 32'hE000C108; parameter val_gem1__frames_tx = 32'h00000000; parameter mask_gem1__frames_tx = 32'hFFFFFFFF; parameter gem1__broadcast_frames_tx = 32'hE000C10C; parameter val_gem1__broadcast_frames_tx = 32'h00000000; parameter mask_gem1__broadcast_frames_tx = 32'hFFFFFFFF; parameter gem1__multi_frames_tx = 32'hE000C110; parameter val_gem1__multi_frames_tx = 32'h00000000; parameter mask_gem1__multi_frames_tx = 32'hFFFFFFFF; parameter gem1__pause_frames_tx = 32'hE000C114; parameter val_gem1__pause_frames_tx = 32'h00000000; parameter mask_gem1__pause_frames_tx = 32'hFFFFFFFF; parameter gem1__frames_64b_tx = 32'hE000C118; parameter val_gem1__frames_64b_tx = 32'h00000000; parameter mask_gem1__frames_64b_tx = 32'hFFFFFFFF; parameter gem1__frames_65to127b_tx = 32'hE000C11C; parameter val_gem1__frames_65to127b_tx = 32'h00000000; parameter mask_gem1__frames_65to127b_tx = 32'hFFFFFFFF; parameter gem1__frames_128to255b_tx = 32'hE000C120; parameter val_gem1__frames_128to255b_tx = 32'h00000000; parameter mask_gem1__frames_128to255b_tx = 32'hFFFFFFFF; parameter gem1__frames_256to511b_tx = 32'hE000C124; parameter val_gem1__frames_256to511b_tx = 32'h00000000; parameter mask_gem1__frames_256to511b_tx = 32'hFFFFFFFF; parameter gem1__frames_512to1023b_tx = 32'hE000C128; parameter val_gem1__frames_512to1023b_tx = 32'h00000000; parameter mask_gem1__frames_512to1023b_tx = 32'hFFFFFFFF; parameter gem1__frames_1024to1518b_tx = 32'hE000C12C; parameter val_gem1__frames_1024to1518b_tx = 32'h00000000; parameter mask_gem1__frames_1024to1518b_tx = 32'hFFFFFFFF; parameter gem1__frames_gt1518b_tx = 32'hE000C130; parameter val_gem1__frames_gt1518b_tx = 32'h00000000; parameter mask_gem1__frames_gt1518b_tx = 32'hFFFFFFFF; parameter gem1__tx_under_runs = 32'hE000C134; parameter val_gem1__tx_under_runs = 32'h00000000; parameter mask_gem1__tx_under_runs = 32'hFFFFFFFF; parameter gem1__single_collisn_frames = 32'hE000C138; parameter val_gem1__single_collisn_frames = 32'h00000000; parameter mask_gem1__single_collisn_frames = 32'hFFFFFFFF; parameter gem1__multi_collisn_frames = 32'hE000C13C; parameter val_gem1__multi_collisn_frames = 32'h00000000; parameter mask_gem1__multi_collisn_frames = 32'hFFFFFFFF; parameter gem1__excessive_collisns = 32'hE000C140; parameter val_gem1__excessive_collisns = 32'h00000000; parameter mask_gem1__excessive_collisns = 32'hFFFFFFFF; parameter gem1__late_collisns = 32'hE000C144; parameter val_gem1__late_collisns = 32'h00000000; parameter mask_gem1__late_collisns = 32'hFFFFFFFF; parameter gem1__deferred_tx_frames = 32'hE000C148; parameter val_gem1__deferred_tx_frames = 32'h00000000; parameter mask_gem1__deferred_tx_frames = 32'hFFFFFFFF; parameter gem1__carrier_sense_errs = 32'hE000C14C; parameter val_gem1__carrier_sense_errs = 32'h00000000; parameter mask_gem1__carrier_sense_errs = 32'hFFFFFFFF; parameter gem1__octets_rx_bot = 32'hE000C150; parameter val_gem1__octets_rx_bot = 32'h00000000; parameter mask_gem1__octets_rx_bot = 32'hFFFFFFFF; parameter gem1__octets_rx_top = 32'hE000C154; parameter val_gem1__octets_rx_top = 32'h00000000; parameter mask_gem1__octets_rx_top = 32'hFFFFFFFF; parameter gem1__frames_rx = 32'hE000C158; parameter val_gem1__frames_rx = 32'h00000000; parameter mask_gem1__frames_rx = 32'hFFFFFFFF; parameter gem1__bdcast_fames_rx = 32'hE000C15C; parameter val_gem1__bdcast_fames_rx = 32'h00000000; parameter mask_gem1__bdcast_fames_rx = 32'hFFFFFFFF; parameter gem1__multi_frames_rx = 32'hE000C160; parameter val_gem1__multi_frames_rx = 32'h00000000; parameter mask_gem1__multi_frames_rx = 32'hFFFFFFFF; parameter gem1__pause_rx = 32'hE000C164; parameter val_gem1__pause_rx = 32'h00000000; parameter mask_gem1__pause_rx = 32'hFFFFFFFF; parameter gem1__frames_64b_rx = 32'hE000C168; parameter val_gem1__frames_64b_rx = 32'h00000000; parameter mask_gem1__frames_64b_rx = 32'hFFFFFFFF; parameter gem1__frames_65to127b_rx = 32'hE000C16C; parameter val_gem1__frames_65to127b_rx = 32'h00000000; parameter mask_gem1__frames_65to127b_rx = 32'hFFFFFFFF; parameter gem1__frames_128to255b_rx = 32'hE000C170; parameter val_gem1__frames_128to255b_rx = 32'h00000000; parameter mask_gem1__frames_128to255b_rx = 32'hFFFFFFFF; parameter gem1__frames_256to511b_rx = 32'hE000C174; parameter val_gem1__frames_256to511b_rx = 32'h00000000; parameter mask_gem1__frames_256to511b_rx = 32'hFFFFFFFF; parameter gem1__frames_512to1023b_rx = 32'hE000C178; parameter val_gem1__frames_512to1023b_rx = 32'h00000000; parameter mask_gem1__frames_512to1023b_rx = 32'hFFFFFFFF; parameter gem1__frames_1024to1518b_rx = 32'hE000C17C; parameter val_gem1__frames_1024to1518b_rx = 32'h00000000; parameter mask_gem1__frames_1024to1518b_rx = 32'hFFFFFFFF; parameter gem1__frames_gt1518b_rx = 32'hE000C180; parameter val_gem1__frames_gt1518b_rx = 32'h00000000; parameter mask_gem1__frames_gt1518b_rx = 32'hFFFFFFFF; parameter gem1__undersz_rx = 32'hE000C184; parameter val_gem1__undersz_rx = 32'h00000000; parameter mask_gem1__undersz_rx = 32'hFFFFFFFF; parameter gem1__oversz_rx = 32'hE000C188; parameter val_gem1__oversz_rx = 32'h00000000; parameter mask_gem1__oversz_rx = 32'hFFFFFFFF; parameter gem1__jab_rx = 32'hE000C18C; parameter val_gem1__jab_rx = 32'h00000000; parameter mask_gem1__jab_rx = 32'hFFFFFFFF; parameter gem1__fcs_errors = 32'hE000C190; parameter val_gem1__fcs_errors = 32'h00000000; parameter mask_gem1__fcs_errors = 32'hFFFFFFFF; parameter gem1__length_field_errors = 32'hE000C194; parameter val_gem1__length_field_errors = 32'h00000000; parameter mask_gem1__length_field_errors = 32'hFFFFFFFF; parameter gem1__rx_symbol_errors = 32'hE000C198; parameter val_gem1__rx_symbol_errors = 32'h00000000; parameter mask_gem1__rx_symbol_errors = 32'hFFFFFFFF; parameter gem1__align_errors = 32'hE000C19C; parameter val_gem1__align_errors = 32'h00000000; parameter mask_gem1__align_errors = 32'hFFFFFFFF; parameter gem1__rx_resource_errors = 32'hE000C1A0; parameter val_gem1__rx_resource_errors = 32'h00000000; parameter mask_gem1__rx_resource_errors = 32'hFFFFFFFF; parameter gem1__rx_overrun_errors = 32'hE000C1A4; parameter val_gem1__rx_overrun_errors = 32'h00000000; parameter mask_gem1__rx_overrun_errors = 32'hFFFFFFFF; parameter gem1__ip_hdr_csum_errors = 32'hE000C1A8; parameter val_gem1__ip_hdr_csum_errors = 32'h00000000; parameter mask_gem1__ip_hdr_csum_errors = 32'hFFFFFFFF; parameter gem1__tcp_csum_errors = 32'hE000C1AC; parameter val_gem1__tcp_csum_errors = 32'h00000000; parameter mask_gem1__tcp_csum_errors = 32'hFFFFFFFF; parameter gem1__udp_csum_errors = 32'hE000C1B0; parameter val_gem1__udp_csum_errors = 32'h00000000; parameter mask_gem1__udp_csum_errors = 32'hFFFFFFFF; parameter gem1__timer_strobe_s = 32'hE000C1C8; parameter val_gem1__timer_strobe_s = 32'h00000000; parameter mask_gem1__timer_strobe_s = 32'hFFFFFFFF; parameter gem1__timer_strobe_ns = 32'hE000C1CC; parameter val_gem1__timer_strobe_ns = 32'h00000000; parameter mask_gem1__timer_strobe_ns = 32'hFFFFFFFF; parameter gem1__timer_s = 32'hE000C1D0; parameter val_gem1__timer_s = 32'h00000000; parameter mask_gem1__timer_s = 32'hFFFFFFFF; parameter gem1__timer_ns = 32'hE000C1D4; parameter val_gem1__timer_ns = 32'h00000000; parameter mask_gem1__timer_ns = 32'hFFFFFFFF; parameter gem1__timer_adjust = 32'hE000C1D8; parameter val_gem1__timer_adjust = 32'h00000000; parameter mask_gem1__timer_adjust = 32'hFFFFFFFF; parameter gem1__timer_incr = 32'hE000C1DC; parameter val_gem1__timer_incr = 32'h00000000; parameter mask_gem1__timer_incr = 32'hFFFFFFFF; parameter gem1__ptp_tx_s = 32'hE000C1E0; parameter val_gem1__ptp_tx_s = 32'h00000000; parameter mask_gem1__ptp_tx_s = 32'hFFFFFFFF; parameter gem1__ptp_tx_ns = 32'hE000C1E4; parameter val_gem1__ptp_tx_ns = 32'h00000000; parameter mask_gem1__ptp_tx_ns = 32'hFFFFFFFF; parameter gem1__ptp_rx_s = 32'hE000C1E8; parameter val_gem1__ptp_rx_s = 32'h00000000; parameter mask_gem1__ptp_rx_s = 32'hFFFFFFFF; parameter gem1__ptp_rx_ns = 32'hE000C1EC; parameter val_gem1__ptp_rx_ns = 32'h00000000; parameter mask_gem1__ptp_rx_ns = 32'hFFFFFFFF; parameter gem1__ptp_peer_tx_s = 32'hE000C1F0; parameter val_gem1__ptp_peer_tx_s = 32'h00000000; parameter mask_gem1__ptp_peer_tx_s = 32'hFFFFFFFF; parameter gem1__ptp_peer_tx_ns = 32'hE000C1F4; parameter val_gem1__ptp_peer_tx_ns = 32'h00000000; parameter mask_gem1__ptp_peer_tx_ns = 32'hFFFFFFFF; parameter gem1__ptp_peer_rx_s = 32'hE000C1F8; parameter val_gem1__ptp_peer_rx_s = 32'h00000000; parameter mask_gem1__ptp_peer_rx_s = 32'hFFFFFFFF; parameter gem1__ptp_peer_rx_ns = 32'hE000C1FC; parameter val_gem1__ptp_peer_rx_ns = 32'h00000000; parameter mask_gem1__ptp_peer_rx_ns = 32'hFFFFFFFF; parameter gem1__pcs_ctrl = 32'hE000C200; parameter val_gem1__pcs_ctrl = 32'h00000000; parameter mask_gem1__pcs_ctrl = 32'h00000000; parameter gem1__pcs_status = 32'hE000C204; parameter val_gem1__pcs_status = 32'h00000000; parameter mask_gem1__pcs_status = 32'h00000000; parameter gem1__pcs_upper_phy_id = 32'hE000C208; parameter val_gem1__pcs_upper_phy_id = 32'h00000000; parameter mask_gem1__pcs_upper_phy_id = 32'h00000000; parameter gem1__pcs_lower_phy_id = 32'hE000C20C; parameter val_gem1__pcs_lower_phy_id = 32'h00000000; parameter mask_gem1__pcs_lower_phy_id = 32'h00000000; parameter gem1__pcs_autoneg_ad = 32'hE000C210; parameter val_gem1__pcs_autoneg_ad = 32'h00000000; parameter mask_gem1__pcs_autoneg_ad = 32'h00000000; parameter gem1__pcs_autoneg_ability = 32'hE000C214; parameter val_gem1__pcs_autoneg_ability = 32'h00000000; parameter mask_gem1__pcs_autoneg_ability = 32'h00000000; parameter gem1__pcs_autonec_exp = 32'hE000C218; parameter val_gem1__pcs_autonec_exp = 32'h00000000; parameter mask_gem1__pcs_autonec_exp = 32'h00000000; parameter gem1__pcs_autoneg_next_pg = 32'hE000C21C; parameter val_gem1__pcs_autoneg_next_pg = 32'h00000000; parameter mask_gem1__pcs_autoneg_next_pg = 32'h00000000; parameter gem1__pcs_autoneg_pnext_pg = 32'hE000C220; parameter val_gem1__pcs_autoneg_pnext_pg = 32'h00000000; parameter mask_gem1__pcs_autoneg_pnext_pg = 32'h00000000; parameter gem1__pcs_extended_status = 32'hE000C23C; parameter val_gem1__pcs_extended_status = 32'h00000000; parameter mask_gem1__pcs_extended_status = 32'h00000000; parameter gem1__design_cfg1 = 32'hE000C280; parameter val_gem1__design_cfg1 = 32'h02000000; parameter mask_gem1__design_cfg1 = 32'h0E000000; parameter gem1__design_cfg2 = 32'hE000C284; parameter val_gem1__design_cfg2 = 32'h2A813FFF; parameter mask_gem1__design_cfg2 = 32'h3FCFFFFF; parameter gem1__design_cfg3 = 32'hE000C288; parameter val_gem1__design_cfg3 = 32'h00000000; parameter mask_gem1__design_cfg3 = 32'hFFFFFFFF; parameter gem1__design_cfg4 = 32'hE000C28C; parameter val_gem1__design_cfg4 = 32'h00000000; parameter mask_gem1__design_cfg4 = 32'hFFFFFFFF; parameter gem1__design_cfg5 = 32'hE000C290; parameter val_gem1__design_cfg5 = 32'h002F2045; parameter mask_gem1__design_cfg5 = 32'h0FFFFCFF; parameter gem1__design_cfg6 = 32'hE000C294; parameter val_gem1__design_cfg6 = 32'h00000000; parameter mask_gem1__design_cfg6 = 32'h00000000; parameter gem1__design_cfg7 = 32'hE000C298; parameter val_gem1__design_cfg7 = 32'h00000000; parameter mask_gem1__design_cfg7 = 32'h00000000; parameter gem1__isr_pq1 = 32'hE000C400; parameter val_gem1__isr_pq1 = 32'h00000000; parameter mask_gem1__isr_pq1 = 32'h00000000; parameter gem1__isr_pq2 = 32'hE000C404; parameter val_gem1__isr_pq2 = 32'h00000000; parameter mask_gem1__isr_pq2 = 32'h00000000; parameter gem1__isr_pq3 = 32'hE000C408; parameter val_gem1__isr_pq3 = 32'h00000000; parameter mask_gem1__isr_pq3 = 32'h00000000; parameter gem1__isr_pq4 = 32'hE000C40C; parameter val_gem1__isr_pq4 = 32'h00000000; parameter mask_gem1__isr_pq4 = 32'h00000000; parameter gem1__isr_pq5 = 32'hE000C410; parameter val_gem1__isr_pq5 = 32'h00000000; parameter mask_gem1__isr_pq5 = 32'h00000000; parameter gem1__isr_pq6 = 32'hE000C414; parameter val_gem1__isr_pq6 = 32'h00000000; parameter mask_gem1__isr_pq6 = 32'h00000000; parameter gem1__isr_pq7 = 32'hE000C418; parameter val_gem1__isr_pq7 = 32'h00000000; parameter mask_gem1__isr_pq7 = 32'h00000000; parameter gem1__tx_qbar_q1 = 32'hE000C440; parameter val_gem1__tx_qbar_q1 = 32'h00000000; parameter mask_gem1__tx_qbar_q1 = 32'h00000000; parameter gem1__tx_qbar_q2 = 32'hE000C444; parameter val_gem1__tx_qbar_q2 = 32'h00000000; parameter mask_gem1__tx_qbar_q2 = 32'h00000000; parameter gem1__tx_qbar_q3 = 32'hE000C448; parameter val_gem1__tx_qbar_q3 = 32'h00000000; parameter mask_gem1__tx_qbar_q3 = 32'h00000000; parameter gem1__tx_qbar_q4 = 32'hE000C44C; parameter val_gem1__tx_qbar_q4 = 32'h00000000; parameter mask_gem1__tx_qbar_q4 = 32'h00000000; parameter gem1__tx_qbar_q5 = 32'hE000C450; parameter val_gem1__tx_qbar_q5 = 32'h00000000; parameter mask_gem1__tx_qbar_q5 = 32'h00000000; parameter gem1__tx_qbar_q6 = 32'hE000C454; parameter val_gem1__tx_qbar_q6 = 32'h00000000; parameter mask_gem1__tx_qbar_q6 = 32'h00000000; parameter gem1__tx_qbar_q7 = 32'hE000C458; parameter val_gem1__tx_qbar_q7 = 32'h00000000; parameter mask_gem1__tx_qbar_q7 = 32'h00000000; parameter gem1__rx_qbar_q1 = 32'hE000C480; parameter val_gem1__rx_qbar_q1 = 32'h00000000; parameter mask_gem1__rx_qbar_q1 = 32'h00000000; parameter gem1__rx_qbar_q2 = 32'hE000C484; parameter val_gem1__rx_qbar_q2 = 32'h00000000; parameter mask_gem1__rx_qbar_q2 = 32'h00000000; parameter gem1__rx_qbar_q3 = 32'hE000C488; parameter val_gem1__rx_qbar_q3 = 32'h00000000; parameter mask_gem1__rx_qbar_q3 = 32'h00000000; parameter gem1__rx_qbar_q4 = 32'hE000C48C; parameter val_gem1__rx_qbar_q4 = 32'h00000000; parameter mask_gem1__rx_qbar_q4 = 32'h00000000; parameter gem1__rx_qbar_q5 = 32'hE000C490; parameter val_gem1__rx_qbar_q5 = 32'h00000000; parameter mask_gem1__rx_qbar_q5 = 32'h00000000; parameter gem1__rx_qbar_q6 = 32'hE000C494; parameter val_gem1__rx_qbar_q6 = 32'h00000000; parameter mask_gem1__rx_qbar_q6 = 32'h00000000; parameter gem1__rx_qbar_q7 = 32'hE000C498; parameter val_gem1__rx_qbar_q7 = 32'h00000000; parameter mask_gem1__rx_qbar_q7 = 32'h00000000; parameter gem1__rx_bufsz_q1 = 32'hE000C4A0; parameter val_gem1__rx_bufsz_q1 = 32'h00000000; parameter mask_gem1__rx_bufsz_q1 = 32'h00000000; parameter gem1__rx_bufsz_q2 = 32'hE000C4A4; parameter val_gem1__rx_bufsz_q2 = 32'h00000000; parameter mask_gem1__rx_bufsz_q2 = 32'h00000000; parameter gem1__rx_bufsz_q3 = 32'hE000C4A8; parameter val_gem1__rx_bufsz_q3 = 32'h00000000; parameter mask_gem1__rx_bufsz_q3 = 32'h00000000; parameter gem1__rx_bufsz_q4 = 32'hE000C4AC; parameter val_gem1__rx_bufsz_q4 = 32'h00000000; parameter mask_gem1__rx_bufsz_q4 = 32'h00000000; parameter gem1__rx_bufsz_q5 = 32'hE000C4B0; parameter val_gem1__rx_bufsz_q5 = 32'h00000000; parameter mask_gem1__rx_bufsz_q5 = 32'h00000000; parameter gem1__rx_bufsz_q6 = 32'hE000C4B4; parameter val_gem1__rx_bufsz_q6 = 32'h00000000; parameter mask_gem1__rx_bufsz_q6 = 32'h00000000; parameter gem1__rx_bufsz_q7 = 32'hE000C4B8; parameter val_gem1__rx_bufsz_q7 = 32'h00000000; parameter mask_gem1__rx_bufsz_q7 = 32'h00000000; parameter gem1__screen_t1_r0 = 32'hE000C500; parameter val_gem1__screen_t1_r0 = 32'h00000000; parameter mask_gem1__screen_t1_r0 = 32'h00000000; parameter gem1__screen_t1_r1 = 32'hE000C504; parameter val_gem1__screen_t1_r1 = 32'h00000000; parameter mask_gem1__screen_t1_r1 = 32'h00000000; parameter gem1__screen_t1_r2 = 32'hE000C508; parameter val_gem1__screen_t1_r2 = 32'h00000000; parameter mask_gem1__screen_t1_r2 = 32'h00000000; parameter gem1__screen_t1_r3 = 32'hE000C50C; parameter val_gem1__screen_t1_r3 = 32'h00000000; parameter mask_gem1__screen_t1_r3 = 32'h00000000; parameter gem1__screen_t1_r4 = 32'hE000C510; parameter val_gem1__screen_t1_r4 = 32'h00000000; parameter mask_gem1__screen_t1_r4 = 32'h00000000; parameter gem1__screen_t1_r5 = 32'hE000C514; parameter val_gem1__screen_t1_r5 = 32'h00000000; parameter mask_gem1__screen_t1_r5 = 32'h00000000; parameter gem1__screen_t1_r6 = 32'hE000C518; parameter val_gem1__screen_t1_r6 = 32'h00000000; parameter mask_gem1__screen_t1_r6 = 32'h00000000; parameter gem1__screen_t1_r7 = 32'hE000C51C; parameter val_gem1__screen_t1_r7 = 32'h00000000; parameter mask_gem1__screen_t1_r7 = 32'h00000000; parameter gem1__screen_t1_r8 = 32'hE000C520; parameter val_gem1__screen_t1_r8 = 32'h00000000; parameter mask_gem1__screen_t1_r8 = 32'h00000000; parameter gem1__screen_t1_r9 = 32'hE000C524; parameter val_gem1__screen_t1_r9 = 32'h00000000; parameter mask_gem1__screen_t1_r9 = 32'h00000000; parameter gem1__screen_t1_r10 = 32'hE000C528; parameter val_gem1__screen_t1_r10 = 32'h00000000; parameter mask_gem1__screen_t1_r10 = 32'h00000000; parameter gem1__screen_t1_r11 = 32'hE000C52C; parameter val_gem1__screen_t1_r11 = 32'h00000000; parameter mask_gem1__screen_t1_r11 = 32'h00000000; parameter gem1__screen_t1_r12 = 32'hE000C530; parameter val_gem1__screen_t1_r12 = 32'h00000000; parameter mask_gem1__screen_t1_r12 = 32'h00000000; parameter gem1__screen_t1_r13 = 32'hE000C534; parameter val_gem1__screen_t1_r13 = 32'h00000000; parameter mask_gem1__screen_t1_r13 = 32'h00000000; parameter gem1__screen_t1_r14 = 32'hE000C538; parameter val_gem1__screen_t1_r14 = 32'h00000000; parameter mask_gem1__screen_t1_r14 = 32'h00000000; parameter gem1__screen_t1_r15 = 32'hE000C53C; parameter val_gem1__screen_t1_r15 = 32'h00000000; parameter mask_gem1__screen_t1_r15 = 32'h00000000; parameter gem1__screen_t2_r0 = 32'hE000C540; parameter val_gem1__screen_t2_r0 = 32'h00000000; parameter mask_gem1__screen_t2_r0 = 32'h00000000; parameter gem1__screen_t2_r1 = 32'hE000C544; parameter val_gem1__screen_t2_r1 = 32'h00000000; parameter mask_gem1__screen_t2_r1 = 32'h00000000; parameter gem1__screen_t2_r2 = 32'hE000C548; parameter val_gem1__screen_t2_r2 = 32'h00000000; parameter mask_gem1__screen_t2_r2 = 32'h00000000; parameter gem1__screen_t2_r3 = 32'hE000C54C; parameter val_gem1__screen_t2_r3 = 32'h00000000; parameter mask_gem1__screen_t2_r3 = 32'h00000000; parameter gem1__screen_t2_r4 = 32'hE000C550; parameter val_gem1__screen_t2_r4 = 32'h00000000; parameter mask_gem1__screen_t2_r4 = 32'h00000000; parameter gem1__screen_t2_r5 = 32'hE000C554; parameter val_gem1__screen_t2_r5 = 32'h00000000; parameter mask_gem1__screen_t2_r5 = 32'h00000000; parameter gem1__screen_t2_r6 = 32'hE000C558; parameter val_gem1__screen_t2_r6 = 32'h00000000; parameter mask_gem1__screen_t2_r6 = 32'h00000000; parameter gem1__screen_t2_r7 = 32'hE000C55C; parameter val_gem1__screen_t2_r7 = 32'h00000000; parameter mask_gem1__screen_t2_r7 = 32'h00000000; parameter gem1__screen_t2_r8 = 32'hE000C560; parameter val_gem1__screen_t2_r8 = 32'h00000000; parameter mask_gem1__screen_t2_r8 = 32'h00000000; parameter gem1__screen_t2_r9 = 32'hE000C564; parameter val_gem1__screen_t2_r9 = 32'h00000000; parameter mask_gem1__screen_t2_r9 = 32'h00000000; parameter gem1__screen_t2_r10 = 32'hE000C568; parameter val_gem1__screen_t2_r10 = 32'h00000000; parameter mask_gem1__screen_t2_r10 = 32'h00000000; parameter gem1__screen_t2_r11 = 32'hE000C56C; parameter val_gem1__screen_t2_r11 = 32'h00000000; parameter mask_gem1__screen_t2_r11 = 32'h00000000; parameter gem1__screen_t2_r12 = 32'hE000C570; parameter val_gem1__screen_t2_r12 = 32'h00000000; parameter mask_gem1__screen_t2_r12 = 32'h00000000; parameter gem1__screen_t2_r13 = 32'hE000C574; parameter val_gem1__screen_t2_r13 = 32'h00000000; parameter mask_gem1__screen_t2_r13 = 32'h00000000; parameter gem1__screen_t2_r14 = 32'hE000C578; parameter val_gem1__screen_t2_r14 = 32'h00000000; parameter mask_gem1__screen_t2_r14 = 32'h00000000; parameter gem1__screen_t2_r15 = 32'hE000C57C; parameter val_gem1__screen_t2_r15 = 32'h00000000; parameter mask_gem1__screen_t2_r15 = 32'h00000000; parameter gem1__intr_en_pq1 = 32'hE000C600; parameter val_gem1__intr_en_pq1 = 32'h00000000; parameter mask_gem1__intr_en_pq1 = 32'h00000000; parameter gem1__intr_en_pq2 = 32'hE000C604; parameter val_gem1__intr_en_pq2 = 32'h00000000; parameter mask_gem1__intr_en_pq2 = 32'h00000000; parameter gem1__intr_en_pq3 = 32'hE000C608; parameter val_gem1__intr_en_pq3 = 32'h00000000; parameter mask_gem1__intr_en_pq3 = 32'h00000000; parameter gem1__intr_en_pq4 = 32'hE000C60C; parameter val_gem1__intr_en_pq4 = 32'h00000000; parameter mask_gem1__intr_en_pq4 = 32'h00000000; parameter gem1__intr_en_pq5 = 32'hE000C610; parameter val_gem1__intr_en_pq5 = 32'h00000000; parameter mask_gem1__intr_en_pq5 = 32'h00000000; parameter gem1__intr_en_pq6 = 32'hE000C614; parameter val_gem1__intr_en_pq6 = 32'h00000000; parameter mask_gem1__intr_en_pq6 = 32'h00000000; parameter gem1__intr_en_pq7 = 32'hE000C618; parameter val_gem1__intr_en_pq7 = 32'h00000000; parameter mask_gem1__intr_en_pq7 = 32'h00000000; parameter gem1__intr_dis_pq1 = 32'hE000C620; parameter val_gem1__intr_dis_pq1 = 32'h00000000; parameter mask_gem1__intr_dis_pq1 = 32'h00000000; parameter gem1__intr_dis_pq2 = 32'hE000C624; parameter val_gem1__intr_dis_pq2 = 32'h00000000; parameter mask_gem1__intr_dis_pq2 = 32'h00000000; parameter gem1__intr_dis_pq3 = 32'hE000C628; parameter val_gem1__intr_dis_pq3 = 32'h00000000; parameter mask_gem1__intr_dis_pq3 = 32'h00000000; parameter gem1__intr_dis_pq4 = 32'hE000C62C; parameter val_gem1__intr_dis_pq4 = 32'h00000000; parameter mask_gem1__intr_dis_pq4 = 32'h00000000; parameter gem1__intr_dis_pq5 = 32'hE000C630; parameter val_gem1__intr_dis_pq5 = 32'h00000000; parameter mask_gem1__intr_dis_pq5 = 32'h00000000; parameter gem1__intr_dis_pq6 = 32'hE000C634; parameter val_gem1__intr_dis_pq6 = 32'h00000000; parameter mask_gem1__intr_dis_pq6 = 32'h00000000; parameter gem1__intr_dis_pq7 = 32'hE000C638; parameter val_gem1__intr_dis_pq7 = 32'h00000000; parameter mask_gem1__intr_dis_pq7 = 32'h00000000; parameter gem1__intr_mask_pq1 = 32'hE000C640; parameter val_gem1__intr_mask_pq1 = 32'h00000000; parameter mask_gem1__intr_mask_pq1 = 32'h00000000; parameter gem1__intr_mask_pq2 = 32'hE000C644; parameter val_gem1__intr_mask_pq2 = 32'h00000000; parameter mask_gem1__intr_mask_pq2 = 32'h00000000; parameter gem1__intr_mask_pq3 = 32'hE000C648; parameter val_gem1__intr_mask_pq3 = 32'h00000000; parameter mask_gem1__intr_mask_pq3 = 32'h00000000; parameter gem1__intr_mask_pq4 = 32'hE000C64C; parameter val_gem1__intr_mask_pq4 = 32'h00000000; parameter mask_gem1__intr_mask_pq4 = 32'h00000000; parameter gem1__intr_mask_pq5 = 32'hE000C650; parameter val_gem1__intr_mask_pq5 = 32'h00000000; parameter mask_gem1__intr_mask_pq5 = 32'h00000000; parameter gem1__intr_mask_pq6 = 32'hE000C654; parameter val_gem1__intr_mask_pq6 = 32'h00000000; parameter mask_gem1__intr_mask_pq6 = 32'h00000000; parameter gem1__intr_mask_pq7 = 32'hE000C658; parameter val_gem1__intr_mask_pq7 = 32'h00000000; parameter mask_gem1__intr_mask_pq7 = 32'h00000000; // ************************************************************ // Module gpio gpio // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter gpio__MASK_DATA_0_LSW = 32'hE000A000; parameter val_gpio__MASK_DATA_0_LSW = 32'h00000000; parameter mask_gpio__MASK_DATA_0_LSW = 32'hFFFF0000; parameter gpio__MASK_DATA_0_MSW = 32'hE000A004; parameter val_gpio__MASK_DATA_0_MSW = 32'h00000000; parameter mask_gpio__MASK_DATA_0_MSW = 32'hFFFF0000; parameter gpio__MASK_DATA_1_LSW = 32'hE000A008; parameter val_gpio__MASK_DATA_1_LSW = 32'h00000000; parameter mask_gpio__MASK_DATA_1_LSW = 32'hFFFF0000; parameter gpio__MASK_DATA_1_MSW = 32'hE000A00C; parameter val_gpio__MASK_DATA_1_MSW = 32'h00000000; parameter mask_gpio__MASK_DATA_1_MSW = 32'h003FFFC0; parameter gpio__MASK_DATA_2_LSW = 32'hE000A010; parameter val_gpio__MASK_DATA_2_LSW = 32'h00000000; parameter mask_gpio__MASK_DATA_2_LSW = 32'hFFFFFFFF; parameter gpio__MASK_DATA_2_MSW = 32'hE000A014; parameter val_gpio__MASK_DATA_2_MSW = 32'h00000000; parameter mask_gpio__MASK_DATA_2_MSW = 32'hFFFFFFFF; parameter gpio__MASK_DATA_3_LSW = 32'hE000A018; parameter val_gpio__MASK_DATA_3_LSW = 32'h00000000; parameter mask_gpio__MASK_DATA_3_LSW = 32'hFFFFFFFF; parameter gpio__MASK_DATA_3_MSW = 32'hE000A01C; parameter val_gpio__MASK_DATA_3_MSW = 32'h00000000; parameter mask_gpio__MASK_DATA_3_MSW = 32'hFFFFFFFF; parameter gpio__DATA_0 = 32'hE000A040; parameter val_gpio__DATA_0 = 32'h00000000; parameter mask_gpio__DATA_0 = 32'h00000000; parameter gpio__DATA_1 = 32'hE000A044; parameter val_gpio__DATA_1 = 32'h00000000; parameter mask_gpio__DATA_1 = 32'h00000000; parameter gpio__DATA_2 = 32'hE000A048; parameter val_gpio__DATA_2 = 32'h00000000; parameter mask_gpio__DATA_2 = 32'hFFFFFFFF; parameter gpio__DATA_3 = 32'hE000A04C; parameter val_gpio__DATA_3 = 32'h00000000; parameter mask_gpio__DATA_3 = 32'hFFFFFFFF; parameter gpio__DATA_0_RO = 32'hE000A060; parameter val_gpio__DATA_0_RO = 32'h00000000; parameter mask_gpio__DATA_0_RO = 32'h00000000; parameter gpio__DATA_1_RO = 32'hE000A064; parameter val_gpio__DATA_1_RO = 32'h00000000; parameter mask_gpio__DATA_1_RO = 32'h00000000; parameter gpio__DATA_2_RO = 32'hE000A068; parameter val_gpio__DATA_2_RO = 32'h00000000; parameter mask_gpio__DATA_2_RO = 32'hFFFFFFFF; parameter gpio__DATA_3_RO = 32'hE000A06C; parameter val_gpio__DATA_3_RO = 32'h00000000; parameter mask_gpio__DATA_3_RO = 32'hFFFFFFFF; parameter gpio__BYPM_0 = 32'hE000A200; parameter val_gpio__BYPM_0 = 32'h00000000; parameter mask_gpio__BYPM_0 = 32'hFFFFFFFF; parameter gpio__DIRM_0 = 32'hE000A204; parameter val_gpio__DIRM_0 = 32'h00000000; parameter mask_gpio__DIRM_0 = 32'hFFFFFFFF; parameter gpio__OEN_0 = 32'hE000A208; parameter val_gpio__OEN_0 = 32'h00000000; parameter mask_gpio__OEN_0 = 32'hFFFFFFFF; parameter gpio__INT_MASK_0 = 32'hE000A20C; parameter val_gpio__INT_MASK_0 = 32'h00000000; parameter mask_gpio__INT_MASK_0 = 32'hFFFFFFFF; parameter gpio__INT_EN_0 = 32'hE000A210; parameter val_gpio__INT_EN_0 = 32'h00000000; parameter mask_gpio__INT_EN_0 = 32'hFFFFFFFF; parameter gpio__INT_DIS_0 = 32'hE000A214; parameter val_gpio__INT_DIS_0 = 32'h00000000; parameter mask_gpio__INT_DIS_0 = 32'hFFFFFFFF; parameter gpio__INT_STAT_0 = 32'hE000A218; parameter val_gpio__INT_STAT_0 = 32'h00000000; parameter mask_gpio__INT_STAT_0 = 32'hFFFFFFFF; parameter gpio__INT_TYPE_0 = 32'hE000A21C; parameter val_gpio__INT_TYPE_0 = 32'hFFFFFFFF; parameter mask_gpio__INT_TYPE_0 = 32'hFFFFFFFF; parameter gpio__INT_POLARITY_0 = 32'hE000A220; parameter val_gpio__INT_POLARITY_0 = 32'h00000000; parameter mask_gpio__INT_POLARITY_0 = 32'hFFFFFFFF; parameter gpio__INT_ANY_0 = 32'hE000A224; parameter val_gpio__INT_ANY_0 = 32'h00000000; parameter mask_gpio__INT_ANY_0 = 32'hFFFFFFFF; parameter gpio__BYPM_1 = 32'hE000A240; parameter val_gpio__BYPM_1 = 32'h00000000; parameter mask_gpio__BYPM_1 = 32'h003FFFFF; parameter gpio__DIRM_1 = 32'hE000A244; parameter val_gpio__DIRM_1 = 32'h00000000; parameter mask_gpio__DIRM_1 = 32'h003FFFFF; parameter gpio__OEN_1 = 32'hE000A248; parameter val_gpio__OEN_1 = 32'h00000000; parameter mask_gpio__OEN_1 = 32'h003FFFFF; parameter gpio__INT_MASK_1 = 32'hE000A24C; parameter val_gpio__INT_MASK_1 = 32'h00000000; parameter mask_gpio__INT_MASK_1 = 32'h003FFFFF; parameter gpio__INT_EN_1 = 32'hE000A250; parameter val_gpio__INT_EN_1 = 32'h00000000; parameter mask_gpio__INT_EN_1 = 32'h003FFFFF; parameter gpio__INT_DIS_1 = 32'hE000A254; parameter val_gpio__INT_DIS_1 = 32'h00000000; parameter mask_gpio__INT_DIS_1 = 32'h003FFFFF; parameter gpio__INT_STAT_1 = 32'hE000A258; parameter val_gpio__INT_STAT_1 = 32'h00000000; parameter mask_gpio__INT_STAT_1 = 32'h003FFFFF; parameter gpio__INT_TYPE_1 = 32'hE000A25C; parameter val_gpio__INT_TYPE_1 = 32'h003FFFFF; parameter mask_gpio__INT_TYPE_1 = 32'h003FFFFF; parameter gpio__INT_POLARITY_1 = 32'hE000A260; parameter val_gpio__INT_POLARITY_1 = 32'h00000000; parameter mask_gpio__INT_POLARITY_1 = 32'h003FFFFF; parameter gpio__INT_ANY_1 = 32'hE000A264; parameter val_gpio__INT_ANY_1 = 32'h00000000; parameter mask_gpio__INT_ANY_1 = 32'h003FFFFF; parameter gpio__BYPM_2 = 32'hE000A280; parameter val_gpio__BYPM_2 = 32'h00000000; parameter mask_gpio__BYPM_2 = 32'hFFFFFFFF; parameter gpio__DIRM_2 = 32'hE000A284; parameter val_gpio__DIRM_2 = 32'h00000000; parameter mask_gpio__DIRM_2 = 32'hFFFFFFFF; parameter gpio__OEN_2 = 32'hE000A288; parameter val_gpio__OEN_2 = 32'h00000000; parameter mask_gpio__OEN_2 = 32'hFFFFFFFF; parameter gpio__INT_MASK_2 = 32'hE000A28C; parameter val_gpio__INT_MASK_2 = 32'h00000000; parameter mask_gpio__INT_MASK_2 = 32'hFFFFFFFF; parameter gpio__INT_EN_2 = 32'hE000A290; parameter val_gpio__INT_EN_2 = 32'h00000000; parameter mask_gpio__INT_EN_2 = 32'hFFFFFFFF; parameter gpio__INT_DIS_2 = 32'hE000A294; parameter val_gpio__INT_DIS_2 = 32'h00000000; parameter mask_gpio__INT_DIS_2 = 32'hFFFFFFFF; parameter gpio__INT_STAT_2 = 32'hE000A298; parameter val_gpio__INT_STAT_2 = 32'h00000000; parameter mask_gpio__INT_STAT_2 = 32'hFFFFFFFF; parameter gpio__INT_TYPE_2 = 32'hE000A29C; parameter val_gpio__INT_TYPE_"b"2 = 32'hFFFFFFFF; parameter mask_gpio__INT_TYPE_2 = 32'hFFFFFFFF; parameter gpio__INT_POLARITY_2 = 32'hE000A2A0; parameter val_gpio__INT_POLARITY_2 = 32'h00000000; parameter mask_gpio__INT_POLARITY_2 = 32'hFFFFFFFF; parameter gpio__INT_ANY_2 = 32'hE000A2A4; parameter val_gpio__INT_ANY_2 = 32'h00000000; parameter mask_gpio__INT_ANY_2 = 32'hFFFFFFFF; parameter gpio__BYPM_3 = 32'hE000A2C0; parameter val_gpio__BYPM_3 = 32'h00000000; parameter mask_gpio__BYPM_3 = 32'hFFFFFFFF; parameter gpio__DIRM_3 = 32'hE000A2C4; parameter val_gpio__DIRM_3 = 32'h00000000; parameter mask_gpio__DIRM_3 = 32'hFFFFFFFF; parameter gpio__OEN_3 = 32'hE000A2C8; parameter val_gpio__OEN_3 = 32'h00000000; parameter mask_gpio__OEN_3 = 32'hFFFFFFFF; parameter gpio__INT_MASK_3 = 32'hE000A2CC; parameter val_gpio__INT_MASK_3 = 32'h00000000; parameter mask_gpio__INT_MASK_3 = 32'hFFFFFFFF; parameter gpio__INT_EN_3 = 32'hE000A2D0; parameter val_gpio__INT_EN_3 = 32'h00000000; parameter mask_gpio__INT_EN_3 = 32'hFFFFFFFF; parameter gpio__INT_DIS_3 = 32'hE000A2D4; parameter val_gpio__INT_DIS_3 = 32'h00000000; parameter mask_gpio__INT_DIS_3 = 32'hFFFFFFFF; parameter gpio__INT_STAT_3 = 32'hE000A2D8; parameter val_gpio__INT_STAT_3 = 32'h00000000; parameter mask_gpio__INT_STAT_3 = 32'hFFFFFFFF; parameter gpio__INT_TYPE_3 = 32'hE000A2DC; parameter val_gpio__INT_TYPE_3 = 32'hFFFFFFFF; parameter mask_gpio__INT_TYPE_3 = 32'hFFFFFFFF; parameter gpio__INT_POLARITY_3 = 32'hE000A2E0; parameter val_gpio__INT_POLARITY_3 = 32'h00000000; parameter mask_gpio__INT_POLARITY_3 = 32'hFFFFFFFF; parameter gpio__INT_ANY_3 = 32'hE000A2E4; parameter val_gpio__INT_ANY_3 = 32'h00000000; parameter mask_gpio__INT_ANY_3 = 32'hFFFFFFFF; // ************************************************************ // Module gpv_iou_switch gpv_iou_switch // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter gpv_iou_switch__Remap = 32'hE0200000; parameter val_gpv_iou_switch__Remap = 32'h00000000; parameter mask_gpv_iou_switch__Remap = 32'h000000FF; parameter gpv_iou_switch__security2_sdio0 = 32'hE0200008; parameter val_gpv_iou_switch__security2_sdio0 = 32'h00000000; parameter mask_gpv_iou_switch__security2_sdio0 = 32'h00000001; parameter gpv_iou_switch__security3_sdio1 = 32'hE020000C; parameter val_gpv_iou_switch__security3_sdio1 = 32'h00000000; parameter mask_gpv_iou_switch__security3_sdio1 = 32'h00000001; parameter gpv_iou_switch__security4_qspi = 32'hE0200010; parameter val_gpv_iou_switch__security4_qspi = 32'h00000000; parameter mask_gpv_iou_switch__security4_qspi = 32'h00000001; parameter gpv_iou_switch__security5_miou = 32'hE0200014; parameter val_gpv_iou_switch__security5_miou = 32'h00000000; parameter mask_gpv_iou_switch__security5_miou = 32'h00000001; parameter gpv_iou_switch__security6_apb_slaves = 32'hE0200018; parameter val_gpv_iou_switch__security6_apb_slaves = 32'h00000000; parameter mask_gpv_iou_switch__security6_apb_slaves = 32'h00007FFF; parameter gpv_iou_switch__security7_smc = 32'hE020001C; parameter val_gpv_iou_switch__security7_smc = 32'h00000000; parameter mask_gpv_iou_switch__security7_smc = 32'h00000001; parameter gpv_iou_switch__peripheral_id4 = 32'hE0201FD0; parameter val_gpv_iou_switch__peripheral_id4 = 32'h00000004; parameter mask_gpv_iou_switch__peripheral_id4 = 32'h000000FF; parameter gpv_iou_switch__peripheral_id5 = 32'hE0201FD4; parameter val_gpv_iou_switch__peripheral_id5 = 32'h00000000; parameter mask_gpv_iou_switch__peripheral_id5 = 32'h000000FF; parameter gpv_iou_switch__peripheral_id6 = 32'hE0201FD8; parameter val_gpv_iou_switch__peripheral_id6 = 32'h00000000; parameter mask_gpv_iou_switch__peripheral_id6 = 32'h000000FF; parameter gpv_iou_switch__peripheral_id7 = 32'hE0201FDC; parameter val_gpv_iou_switch__peripheral_id7 = 32'h00000000; parameter mask_gpv_iou_switch__peripheral_id7 = 32'h000000FF; parameter gpv_iou_switch__peripheral_id0 = 32'hE0201FE0; parameter val_gpv_iou_switch__peripheral_id0 = 32'h00000001; parameter mask_gpv_iou_switch__peripheral_id0 = 32'h000000FF; parameter gpv_iou_switch__peripheral_id1 = 32'hE0201FE4; parameter val_gpv_iou_switch__peripheral_id1 = 32'h000000B3; parameter mask_gpv_iou_switch__peripheral_id1 = 32'h000000FF; parameter gpv_iou_switch__peripheral_id2 = 32'hE0201FE8; parameter val_gpv_iou_switch__peripheral_id2 = 32'h0000005B; parameter mask_gpv_iou_switch__peripheral_id2 = 32'h000000FF; parameter gpv_iou_switch__peripheral_id3 = 32'hE0201FEC; parameter val_gpv_iou_switch__peripheral_id3 = 32'h00000000; parameter mask_gpv_iou_switch__peripheral_id3 = 32'h000000FF; parameter gpv_iou_switch__component_id0 = 32'hE0201FF0; parameter val_gpv_iou_switch__component_id0 = 32'h0000000D; parameter mask_gpv_iou_switch__component_id0 = 32'h000000FF; parameter gpv_iou_switch__component_id1 = 32'hE0201FF4; parameter val_gpv_iou_switch__component_id1 = 32'h000000F0; parameter mask_gpv_iou_switch__component_id1 = 32'h000000FF; parameter gpv_iou_switch__component_id2 = 32'hE0201FF8; parameter val_gpv_iou_switch__component_id2 = 32'h00000005; parameter mask_gpv_iou_switch__component_id2 = 32'h000000FF; parameter gpv_iou_switch__component_id3 = 32'hE0201FFC; parameter val_gpv_iou_switch__component_id3 = 32'h000000B1; parameter mask_gpv_iou_switch__component_id3 = 32'h000000FF; parameter gpv_iou_switch__fn_mod_bm_iss_sdio0 = 32'hE0202008; parameter val_gpv_iou_switch__fn_mod_bm_iss_sdio0 = 32'h00000000; parameter mask_gpv_iou_switch__fn_mod_bm_iss_sdio0 = 32'h00000003; parameter gpv_iou_switch__ahb_cntl_sdio0 = 32'hE0202044; parameter val_gpv_iou_switch__ahb_cntl_sdio0 = 32'h00000000; parameter mask_gpv_iou_switch__ahb_cntl_sdio0 = 32'h00000000; parameter gpv_iou_switch__fn_mod_bm_iss_sdio1 = 32'hE0203008; parameter val_gpv_iou_switch__fn_mod_bm_iss_sdio1 = 32'h00000000; parameter mask_gpv_iou_switch__fn_mod_bm_iss_sdio1 = 32'h00000003; parameter gpv_iou_switch__ahb_cntl_sdio1 = 32'hE0203044; parameter val_gpv_iou_switch__ahb_cntl_sdio1 = 32'h00000000; parameter mask_gpv_iou_switch__ahb_cntl_sdio1 = 32'h00000000; parameter gpv_iou_switch__fn_mod_bm_iss_qspi = 32'hE0204008; parameter val_gpv_iou_switch__fn_mod_bm_iss_qspi = 32'h00000000; parameter mask_gpv_iou_switch__fn_mod_bm_iss_qspi = 32'h00000003; parameter gpv_iou_switch__fn_mod_bm_iss_miou = 32'hE0205008; parameter val_gpv_iou_switch__fn_mod_bm_iss_miou = 32'h00000000; parameter mask_gpv_iou_switch__fn_mod_bm_iss_miou = 32'h00000003; parameter gpv_iou_switch__fn_mod_bm_iss_smc = 32'hE0207008; parameter val_gpv_iou_switch__fn_mod_bm_iss_smc = 32'h00000000; parameter mask_gpv_iou_switch__fn_mod_bm_iss_smc = 32'h00000003; parameter gpv_iou_switch__fn_mod_ahb_gem0 = 32'hE0242028; parameter val_gpv_iou_switch__fn_mod_ahb_gem0 = 32'h00000000; parameter mask_gpv_iou_switch__fn_mod_ahb_gem0 = 32'h00000007; parameter gpv_iou_switch__read_qos_gem0 = 32'hE0242100; parameter val_gpv_iou_switch__read_qos_gem0 = 32'h00000000; parameter mask_gpv_iou_switch__read_qos_gem0 = 32'h0000000F; parameter gpv_iou_switch__write_qos_gem0 = 32'hE0242104; parameter val_gpv_iou_switch__write_qos_gem0 = 32'h00000000; parameter mask_gpv_iou_switch__write_qos_gem0 = 32'h0000000F; parameter gpv_iou_switch__fn_mod_iss_gem0 = 32'hE0242108; parameter val_gpv_iou_switch__fn_mod_iss_gem0 = 32'h00000000; parameter mask_gpv_iou_switch__fn_mod_iss_gem0 = 32'h00000003; parameter gpv_iou_switch__fn_mod_ahb_gem1 = 32'hE0243028; parameter val_gpv_iou_switch__fn_mod_ahb_gem1 = 32'h00000000; parameter mask_gpv_iou_switch__fn_mod_ahb_gem1 = 32'h00000007; parameter gpv_iou_switch__read_qos_gem1 = 32'hE0243100; parameter val_gpv_iou_switch__read_qos_gem1 = 32'h00000000; parameter mask_gpv_iou_switch__read_qos_gem1 = 32'h0000000F; parameter gpv_iou_switch__write_qos_gem1 = 32'hE0243104; parameter val_gpv_iou_switch__write_qos_gem1 = 32'h00000000; parameter mask_gpv_iou_switch__write_qos_gem1 = 32'h0000000F; parameter gpv_iou_switch__fn_mod_iss_gem1 = 32'hE0243108; parameter val_gpv_iou_switch__fn_mod_iss_gem1 = 32'h00000000; parameter mask_gpv_iou_switch__fn_mod_iss_gem1 = 32'h00000003; parameter gpv_iou_switch__fn_mod_ahb_usb0 = 32'hE0244028; parameter val_gpv_iou_switch__fn_mod_ahb_usb0 = 32'h00000000; parameter mask_gpv_iou_switch__fn_mod_ahb_usb0 = 32'h00000007; parameter gpv_iou_switch__read_qos_usb0 = 32'hE0244100; parameter val_gpv_iou_switch__read_qos_usb0 = 32'h00000000; parameter mask_gpv_iou_switch__read_qos_usb0 = 32'h0000000F; parameter gpv_iou_switch__write_qos_usb0 = 32'hE0244104; parameter val_gpv_iou_switch__write_qos_usb0 = 32'h00000000; parameter mask_gpv_iou_switch__write_qos_usb0 = 32'h0000000F; parameter gpv_iou_switch__fn_mod_iss_usb0 = 32'hE0244108; parameter val_gpv_iou_switch__fn_mod_iss_usb0 = 32'h00000000; parameter mask_gpv_iou_switch__fn_mod_iss_usb0 = 32'h00000003; parameter gpv_iou_switch__fn_mod_ahb_usb1 = 32'hE0245028; parameter val_gpv_iou_switch__fn_mod_ahb_usb1 = 32'h00000000; parameter mask_gpv_iou_switch__fn_mod_ahb_usb1 = 32'h00000007; parameter gpv_iou_switch__read_qos_usb1 = 32'hE0245100; parameter val_gpv_iou_switch__read_qos_usb1 = 32'h00000000; parameter mask_gpv_iou_switch__read_qos_usb1 = 32'h0000000F; parameter gpv_iou_switch__write_qos_usb1 = 32'hE0245104; parameter val_gpv_iou_switch__write_qos_usb1 = 32'h00000000; parameter mask_gpv_iou_switch__write_qos_usb1 = 32'h0000000F; parameter gpv_iou_switch__fn_mod_iss_usb1 = 32'hE0245108; parameter val_gpv_iou_switch__fn_mod_iss_usb1 = 32'h00000000; parameter mask_gpv_iou_switch__fn_mod_iss_usb1 = 32'h00000003; parameter gpv_iou_switch__fn_mod_ahb_sdio0 = 32'hE0246028; parameter val_gpv_iou_switch__fn_mod_ahb_sdio0 = 32'h00000000; parameter mask_gpv_iou_switch__fn_mod_ahb_sdio0 = 32'h00000007; parameter gpv_iou_switch__read_qos_sdio0 = 32'hE0246100; parameter val_gpv_iou_switch__read_qos_sdio0 = 32'h00000000; parameter mask_gpv_iou_switch__read_qos_sdio0 = 32'h0000000F; parameter gpv_iou_switch__write_qos_sdio0 = 32'hE0246104; parameter val_gpv_iou_switch__write_qos_sdio0 = 32'h00000000; parameter mask_gpv_iou_switch__write_qos_sdio0 = 32'h0000000F; parameter gpv_iou_switch__fn_mod_iss_sdio0 = 32'hE0246108; parameter val_gpv_iou_switch__fn_mod_iss_sdio0 = 32'h00000000; parameter mask_gpv_iou_switch__fn_mod_iss_sdio0 = 32'h00000003; parameter gpv_iou_switch__fn_mod_ahb_sdio1 = 32'hE0247028; parameter val_gpv_iou_switch__fn_mod_ahb_sdio1 = 32'h00000000; parameter mask_gpv_iou_switch__fn_mod_ahb_sdio1 = 32'h00000007; parameter gpv_iou_switch__read_qos_sdio1 = 32'hE0247100; parameter val_gpv_iou_switch__read_qos_sdio1 = 32'h00000000; parameter mask_gpv_iou_switch__read_qos_sdio1 = 32'h0000000F; parameter gpv_iou_switch__write_qos_sdio1 = 32'hE0247104; parameter val_gpv_iou_switch__write_qos_sdio1 = 32'h00000000; parameter mask_gpv_iou_switch__write_qos_sdio1 = 32'h0000000F; parameter gpv_iou_switch__fn_mod_iss_sdio1 = 32'hE0247108; parameter val_gpv_iou_switch__fn_mod_iss_sdio1 = 32'h00000000; parameter mask_gpv_iou_switch__fn_mod_iss_sdio1 = 32'h00000003; parameter gpv_iou_switch__fn_mod_iss_siou = 32'hE0249108; parameter val_gpv_iou_switch__fn_mod_iss_siou = 32'h00000000; parameter mask_gpv_iou_switch__fn_mod_iss_siou = 32'h00000003; // ************************************************************ // Module gpv_qos301_cpu qos301 // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter gpv_qos301_cpu__qos_cntl = 32'hF894610C; parameter val_gpv_qos301_cpu__qos_cntl = 32'h00000000; parameter mask_gpv_qos301_cpu__qos_cntl = 32'h000000FF; parameter gpv_qos301_cpu__max_ot = 32'hF8946110; parameter val_gpv_qos301_cpu__max_ot = 32'h00000000; parameter mask_gpv_qos301_cpu__max_ot = 32'h3FFF3FFF; parameter gpv_qos301_cpu__max_comb_ot = 32'hF8946114; parameter val_gpv_qos301_cpu__max_comb_ot = 32'h00000000; parameter mask_gpv_qos301_cpu__max_comb_ot = 32'h00007FFF; parameter gpv_qos301_cpu__aw_p = 32'hF8946118; parameter val_gpv_qos301_cpu__aw_p = 32'h00000000; parameter mask_gpv_qos301_cpu__aw_p = 32'hFF000000; parameter gpv_qos301_cpu__aw_b = 32'hF894611C; parameter val_gpv_qos301_cpu__aw_b = 32'h00000000; parameter mask_gpv_qos301_cpu__aw_b = 32'h0000FFFF; parameter gpv_qos301_cpu__aw_r = 32'hF8946120; parameter val_gpv_qos301_cpu__aw_r = 32'h00000000; parameter mask_gpv_qos301_cpu__aw_r = 32'hFFF00000; parameter gpv_qos301_cpu__ar_p = 32'hF8946124; parameter val_gpv_qos301_cpu__ar_p = 32'h00000000; parameter mask_gpv_qos301_cpu__ar_p = 32'hFF000000; parameter gpv_qos301_cpu__ar_b = 32'hF8946128; parameter val_gpv_qos301_cpu__ar_b = 32'h00000000; parameter mask_gpv_qos301_cpu__ar_b = 32'h0000FFFF; parameter gpv_qos301_cpu__ar_r = 32'hF894612C; parameter val_gpv_qos301_cpu__ar_r = 32'h00000000; parameter mask_gpv_qos301_cpu__ar_r = 32'hFFF00000; // ************************************************************ // Module gpv_qos301_dmac qos301 // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter gpv_qos301_dmac__qos_cntl = 32'hF894710C; parameter val_gpv_qos301_dmac__qos_cntl = 32'h00000000; parameter mask_gpv_qos301_dmac__qos_cntl = 32'h000000FF; parameter gpv_qos301_dmac__max_ot = 32'hF8947110; parameter val_gpv_qos301_dmac__max_ot = 32'h00000000; parameter mask_gpv_qos301_dmac__max_ot = 32'h3FFF3FFF; parameter gpv_qos301_dmac__max_comb_ot = 32'hF8947114; parameter val_gpv_qos301_dmac__max_comb_ot = 32'h00000000; parameter mask_gpv_qos301_dmac__max_comb_ot = 32'h00007FFF; parameter gpv_qos301_dmac__aw_p = 32'hF8947118; parameter val_gpv_qos301_dmac__aw_p = 32'h00000000; parameter mask_gpv_qos301_dmac__aw_p = 32'hFF000000; parameter gpv_qos301_dmac__aw_b = 32'hF894711C; parameter val_gpv_qos301_dmac__aw_b = 32'h00000000; parameter mask_gpv_qos301_dmac__aw_b = 32'h0000FFFF; parameter gpv_qos301_dmac__aw_r = 32'hF8947120; parameter val_gpv_qos301_dmac__aw_r = 32'h00000000; parameter mask_gpv_qos301_dmac__aw_r = 32'hFFF00000; parameter gpv_qos301_dmac__ar_p = 32'hF8947124; parameter val_gpv_qos301_dmac__ar_p = 32'h00000000; parameter mask_gpv_qos301_dmac__ar_p = 32'hFF000000; parameter gpv_qos301_dmac__ar_b = 32'hF8947128; parameter val_gpv_qos301_dmac__ar_b = 32'h00000000; parameter mask_gpv_qos301_dmac__ar_b = 32'h0000FFFF; parameter gpv_qos301_dmac__ar_r = 32'hF894712C; parameter val_gpv_qos301_dmac__ar_r = 32'h00000000; parameter mask_gpv_qos301_dmac__ar_r = 32'hFFF00000; // ************************************************************ // Module gpv_qos301_iou qos301 // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter gpv_qos301_iou__qos_cntl = 32'hF894810C; parameter val_gpv_qos301_iou__qos_cntl = 32'h00000000; parameter mask_gpv_qos301_iou__qos_cntl = 32'h000000FF; parameter gpv_qos301_iou__max_ot = 32'hF8948110; parameter val_gpv_qos301_iou__max_ot = 32'h00000000; parameter mask_gpv_qos301_iou__max_ot = 32'h3FFF3FFF; parameter gpv_qos301_iou__max_comb_ot = 32'hF8948114; parameter val_gpv_qos301_iou__max_comb_ot = 32'h00000000; parameter mask_gpv_qos301_iou__max_comb_ot = 32'h00007FFF; parameter gpv_qos301_iou__aw_p = 32'hF8948118; parameter val_gpv_qos301_iou__aw_p = 32'h00000000; parameter mask_gpv_qos301_iou__aw_p = 32'hFF000000; parameter gpv_qos301_iou__aw_b = 32'hF894811C; parameter val_gpv_qos301_iou__aw_b = 32'h00000000; parameter mask_gpv_qos301_iou__aw_b = 32'h0000FFFF; parameter gpv_qos301_iou__aw_r = 32'hF8948120; parameter val_gpv_qos301_iou__aw_r = 32'h00000000; parameter mask_gpv_qos301_iou__aw_r = 32'hFFF00000; parameter gpv_qos301_iou__ar_p = 32'hF8948124; parameter val_gpv_qos301_iou__ar_p = 32'h00000000; parameter mask_gpv_qos301_iou__ar_p = 32'hFF000000; parameter gpv_qos301_iou__ar_b = 32'hF8948128; parameter val_gpv_qos301_iou__ar_b = 32'h00000000; parameter mask_gpv_qos301_iou__ar_b = 32'h0000FFFF; parameter gpv_qos301_iou__ar_r = 32'hF894812C; parameter val_gpv_qos301_iou__ar_r = 32'h00000000; parameter mask_gpv_qos301_iou__ar_r = 32'hFFF00000; // ************************************************************ // Module gpv_trustzone nic301_addr_region_ctrl_registers // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter gpv_trustzone__Remap = 32'hF8900000; parameter val_gpv_trustzone__Remap = 32'h00000000; parameter mask_gpv_trustzone__Remap = 32'h000000C0; parameter gpv_trustzone__security_fssw_s0 = 32'hF890001C; parameter val_gpv_trustzone__security_fssw_s0 = 32'h00000000; parameter mask_gpv_trustzone__security_fssw_s0 = 32'h00000001; parameter gpv_trustzone__security_fssw_s1 = 32'hF8900020; parameter val_gpv_trustzone__security_fssw_s1 = 32'h00000000; parameter mask_gpv_trustzone__security_fssw_s1 = 32'h00000001; parameter gpv_trustzone__security_apb = 32'hF8900028; parameter val_gpv_trustzone__security_apb = 32'h00000000; parameter mask_gpv_trustzone__security_apb = 32'h0000003F; // ************************************************************ // Module i2c0 IIC // doc version: 1.2 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter i2c0__Control_reg0 = 32'hE0004000; parameter val_i2c0__Control_reg0 = 32'h00000000; parameter mask_i2c0__Control_reg0 = 32'h0000FFFF; parameter i2c0__Status_reg0 = 32'hE0004004; parameter val_i2c0__Status_reg0 = 32'h00000000; parameter mask_i2c0__Status_reg0 = 32'h0000FFFF; parameter i2c0__I2C_address_reg0 = 32'hE0004008; parameter val_i2c0__I2C_address_reg0 = 32'h00000000; parameter mask_i2c0__I2C_address_reg0 = 32'h0000FFFF; parameter i2c0__I2C_data_reg0 = 32'hE000400C; parameter val_i2c0__I2C_data_reg0 = 32'h00000000; parameter mask_i2c0__I2C_data_reg0 = 32'h0000FFFF; parameter i2c0__Interrupt_status_reg0 = 32'hE0004010; parameter val_i2c0__Interrupt_status_reg0 = 32'h00000000; parameter mask_i2c0__Interrupt_status_reg0 = 32'h0000FFFF; parameter i2c0__Transfer_size_reg0 = 32'hE0004014; parameter val_i2c0__Transfer_size_reg0 = 32'h00000000; parameter mask_i2c0__Transfer_size_reg0 = 32'h000000FF; parameter i2c0__Slave_mon_pause_reg0 = 32'hE0004018; parameter val_i2c0__Slave_mon_pause_reg0 = 32'h00000000; parameter mask_i2c0__Slave_mon_pause_reg0 = 32'h000000FF; parameter i2c0__Time_out_reg0 = 32'hE000401C; parameter val_i2c0__Time_out_reg0 = 32'h0000001F; parameter mask_i2c0__Time_out_reg0 = 32'h000000FF; parameter i2c0__Intrpt_mask_reg0 = 32'hE0004020; parameter val_i2c0__Intrpt_mask_reg0 = 32'h000002FF; parameter mask_i2c0__Intrpt_mask_reg0 = 32'h0000FFFF; parameter i2c0__Intrpt_enable_reg0 = 32'hE0004024; parameter val_i2c0__Intrpt_enable_reg0 = 32'h00000000; parameter mask_i2c0__Intrpt_enable_reg0 = 32'h0000FFFF; parameter i2c0__Intrpt_disable_reg0 = 32'hE0004028; parameter val_i2c0__Intrpt_disable_reg0 = 32'h00000000; parameter mask_i2c0__Intrpt_disable_reg0 = 32'h0000FFFF; // ************************************************************ // Module i2c1 IIC // doc version: 1.2 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter i2c1__Control_reg0 = 32'hE0005000; parameter val_i2c1__Control_reg0 = 32'h00000000; parameter mask_i2c1__Control_reg0 = 32'h0000FFFF; parameter i2c1__Status_reg0 = 32'hE0005004; parameter val_i2c1__Status_reg0 = 32'h00000000; parameter mask_i2c1__Status_reg0 = 32'h0000FFFF; parameter i2c1__I2C_address_reg0 = 32'hE0005008; parameter val_i2c1__I2C_address_reg0 = 32'h00000000; parameter mask_i2c1__I2C_address_reg0 = 32'h0000FFFF; parameter i2c1__I2C_data_reg0 = 32'hE000500C; parameter val_i2c1__I2C_data_reg0 = 32'h00000000; parameter mask_i2c1__I2C_data_reg0 = 32'h0000FFFF; parameter i2c1__Interrupt_status_reg0 = 32'hE0005010; parameter val_i2c1__Interrupt_status_reg0 = 32'h00000000; parameter mask_i2c1__Interrupt_status_reg0 = 32'h0000FFFF; parameter i2c1__Transfer_size_reg0 = 32'hE0005014; parameter val_i2c1__Transfer_size_reg0 = 32'h00000000; parameter mask_i2c1__Transfer_size_reg0 = 32'h000000FF; parameter i2c1__Slave_mon_pause_reg0 = 32'hE0005018; parameter val_i2c1__Slave_mon_pause_reg0 = 32'h00000000; parameter mask_i2c1__Slave_mon_pause_reg0 = 32'h000000FF; parameter i2c1__Time_out_reg0 = 32'hE000501C; parameter val_i2c1__Time_out_reg0 = 32'h0000001F; parameter mask_i2c1__Time_out_reg0 = 32'h000000FF; parameter i2c1__Intrpt_mask_reg0 = 32'hE0005020; parameter val_i2c1__Intrpt_mask_reg0 = 32'h000002FF; parameter mask_i2c1__Intrpt_mask_reg0 = 32'h0000FFFF; parameter i2c1__Intrpt_enable_reg0 = 32'hE0005024; parameter val_i2c1__Intrpt_enable_reg0 = 32'h00000000; parameter mask_i2c1__Intrpt_enable_reg0 = 32'h0000FFFF; parameter i2c1__Intrpt_disable_reg0 = 32'hE0005028; parameter val_i2c1__Intrpt_disable_reg0 = 32'h00000000; parameter mask_i2c1__Intrpt_disable_reg0 = 32'h0000FFFF; // ************************************************************ // Module l2cache L2Cpl310 // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter l2cache__reg0_cache_id = 32'hF8F02000; parameter val_l2cache__reg0_cache_id = 32'h410000C8; parameter mask_l2cache__reg0_cache_id = 32'hFFFFFFFF; parameter l2cache__reg0_cache_type = 32'hF8F02004; parameter val_l2cache__reg0_cache_type = 32'h9E300300; parameter mask_l2cache__reg0_cache_type = 32'hFFFFFFFF; parameter l2cache__reg1_control = 32'hF8F02100; parameter val_l2cache__reg1_control = 32'h00000000; parameter mask_l2cache__reg1_control = 32'h7FFFFFFF; parameter l2cache__reg1_aux_control = 32'hF8F02104; parameter val_l2cache__reg1_aux_control = 32'h02050000; parameter mask_l2cache__reg1_aux_control = 32'hFFFFFFFF; parameter l2cache__reg1_tag_ram_control = 32'hF8F02108; parameter val_l2cache__reg1_tag_ram_control = 32'h00000777; parameter mask_l2cache__reg1_tag_ram_control = 32'hFFFFFFFF; parameter l2cache__reg1_data_ram_control = 32'hF8F0210C; parameter val_l2cache__reg1_data_ram_control = 32'h00000777; parameter mask_l2cache__reg1_data_ram_control = 32'hFFFFFFFF; parameter l2cache__reg2_ev_counter_ctrl = 32'hF8F02200; parameter val_l2cache__reg2_ev_counter_ctrl = 32'h00000000; parameter mask_l2cache__reg2_ev_counter_ctrl = 32'hFFFFFFFF; parameter l2cache__reg2_ev_counter1_cfg = 32'hF8F02204; parameter val_l2cache__reg2_ev_counter1_cfg = 32'h00000000; parameter mask_l2cache__reg2_ev_counter1_cfg = 32'hFFFFFFFF; parameter l2cache__reg2_ev_counter0_cfg = 32'hF8F02208; parameter val_l2cache__reg2_ev_counter0_cfg = 32'h00000000; parameter mask_l2cache__reg2_ev_counter0_cfg = 32'hFFFFFFFF; parameter l2cache__reg2_ev_counter1 = 32'hF8F0220C; parameter val_l2cache__reg2_ev_counter1 = 32'h00000000; parameter mask_l2cache__reg2_ev_counter1 = 32'hFFFFFFFF; parameter l2cache__reg2_ev_counter0 = 32'hF8F02210; parameter val_l2cache__reg2_ev_counter0 = 32'h00000000; parameter mask_l2cache__reg2_ev_counter0 = 32'hFFFFFFFF; parameter l2cache__reg2_int_mask = 32'hF8F02214; parameter val_l2cache__reg2_int_mask = 32'h00000000; parameter mask_l2cache__reg2_int_mask = 32'hFFFFFFFF; parameter l2cache__reg2_int_mask_status = 32'hF8F02218; parameter val_l2cache__reg2_int_mask_status = 32'h00000000; parameter mask_l2cache__reg2_int_mask_status = 32'hFFFFFFFF; parameter l2cache__reg2_int_raw_status = 32'hF8F0221C; parameter val_l2cache__reg2_int_raw_status = 32'h00000000; parameter mask_l2cache__reg2_int_raw_status = 32'hFFFFFFFF; parameter l2cache__reg2_int_clear = 32'hF8F02220; parameter val_l2cache__reg2_int_clear = 32'h00000000; parameter mask_l2cache__reg2_int_clear = 32'hFFFFFFFF; parameter l2cache__reg7_cache_sync = 32'hF8F02730; parameter val_l2cache__reg7_cache_sync = 32'h00000000; parameter mask_l2cache__reg7_cache_sync = 32'hFFFFFFFF; parameter l2cache__reg7_inv_pa = 32'hF8F02770; parameter val_l2cache__reg7_inv_pa = 32'h00000000; parameter mask_l2cache__reg7_inv_pa = 32'hFFFFFFFF; parameter l2cache__reg7_inv_way = 32'hF8F0277C; parameter val_l2cache__reg7_inv_way = 32'h00000000; parameter mask_l2cache__reg7_inv_way = 32'hFFFFFFFF; parameter l2cache__reg7_clean_pa = 32'hF8F027B0; parameter val_l2cache__reg7_clean_pa = 32'h00000000; parameter mask_l2cache__reg7_clean_pa = 32'hFFFFFFFF; parameter l2cache__reg7_clean_index = 32'hF8F027B8; parameter val_l2cache__reg7_clean_index = 32'h00000000; parameter mask_l2cache__reg7_clean_index = 32'hFFFFFFFF; parameter l2cache__reg7_clean_way = 32'hF8F027BC; parameter val_l2cache__reg7_clean_way = 32'h00000000; parameter mask_l2cache__reg7_clean_way = 32'hFFFFFFFF; parameter l2cache__reg7_clean_inv_pa = 32'hF8F027F0; parameter val_l2cache__reg7_clean_inv_pa = 32'h00000000; parameter mask_l2cache__reg7_clean_inv_pa = 32'hFFFFFFFF; parameter l2cache__reg7_clean_inv_index = 32'hF8F027F8; parameter val_l2cache__reg7_clean_inv_index = 32'h00000000; parameter mask_l2cache__reg7_clean_inv_index = 32'hFFFFFFFF; parameter l2cache__reg7_clean_inv_way = 32'hF8F027FC; parameter val_l2cache__reg7_clean_inv_way = 32'h00000000; parameter mask_l2cache__reg7_clean_inv_way = 32'hFFFFFFFF; parameter l2cache__reg9_d_lockdown0 = 32'hF8F02900; parameter val_l2cache__reg9_d_lockdown0 = 32'h00000000; parameter mask_l2cache__reg9_d_lockdown0 = 32'hFFFFFFFF; parameter l2cache__reg9_i_lockdown0 = 32'hF8F02904; parameter val_l2cache__reg9_i_lockdown0 = 32'h00000000; parameter mask_l2cache__reg9_i_lockdown0 = 32'hFFFFFFFF; parameter l2cache__reg9_d_lockdown1 = 32'hF8F02908; parameter val_l2cache__reg9_d_lockdown1 = 32'h00000000; parameter mask_l2cache__reg9_d_lockdown1 = 32'hFFFFFFFF; parameter l2cache__reg9_i_lockdown1 = 32'hF8F0290C; parameter val_l2cache__reg9_i_lockdown1 = 32'h00000000; parameter mask_l2cache__reg9_i_lockdown1 = 32'hFFFFFFFF; parameter l2cache__reg9_d_lockdown2 = 32'hF8F02910; parameter val_l2cache__reg9_d_lockdown2 = 32'h00000000; parameter mask_l2cache__reg9_d_lockdown2 = 32'hFFFFFFFF; parameter l2cache__reg9_i_lockdown2 = 32'hF8F02914; parameter val_l2cache__reg9_i_lockdown2 = 32'h00000000; parameter mask_l2cache__reg9_i_lockdown2 = 32'hFFFFFFFF; parameter l2cache__reg9_d_lockdown3 = 32'hF8F02918; parameter val_l2cache__reg9_d_lockdown3 = 32'h00000000; parameter mask_l2cache__reg9_d_lockdown3 = 32'hFFFFFFFF; parameter l2cache__reg9_i_lockdown3 = 32'hF8F0291C; parameter val_l2cache__reg9_i_lockdown3 = 32'h00000000; parameter mask_l2cache__reg9_i_lockdown3 = 32'hFFFFFFFF; parameter l2cache__reg9_d_lockdown4 = 32'hF8F02920; parameter val_l2cache__reg9_d_lockdown4 = 32'h00000000; parameter mask_l2cache__reg9_d_lockdown4 = 32'hFFFFFFFF; parameter l2cache__reg9_i_lockdown4 = 32'hF8F02924; parameter val_l2cache__reg9_i_lockdown4 = 32'h00000000; parameter mask_l2cache__reg9_i_lockdown4 = 32'hFFFFFFFF; parameter l2cache__reg9_d_lockdown5 = 32'hF8F02928; parameter val_l2cache__reg9_d_lockdown5 = 32'h00000000; parameter mask_l2cache__reg9_d_lockdown5 = 32'hFFFFFFFF; parameter l2cache__reg9_i_lockdown5 = 32'hF8F0292C; parameter val_l2cache__reg9_i_lockdown5 = 32'h00000000; parameter mask_l2cache__reg9_i_lockdown5 = 32'hFFFFFFFF; parameter l2cache__reg9_d_lockdown6 = 32'hF8F02930; parameter val_l2cache__reg9_d_lockdown6 = 32'h00000000; parameter mask_l2cache__reg9_d_lockdown6 = 32'hFFFFFFFF; parameter l2cache__reg9_i_lockdown6 = 32'hF8F02934; parameter val_l2cache__reg9_i_lockdown6 = 32'h00000000; parameter mask_l2cache__reg9_i_lockdown6 = 32'hFFFFFFFF; parameter l2cache__reg9_d_lockdown7 = 32'hF8F02938; parameter val_l2cache__reg9_d_lockdown7 = 32'h00000000; parameter mask_l2cache__reg9_d_lockdown7 = 32'hFFFFFFFF; parameter l2cache__reg9_i_lockdown7 = 32'hF8F0293C; parameter val_l2cache__reg9_i_lockdown7 = 32'h00000000; parameter mask_l2cache__reg9_i_lockdown7 = 32'hFFFFFFFF; parameter l2cache__reg9_lock_line_en = 32'hF8F02950; parameter val_l2cache__reg9_lock_line_en = 32'h00000000; parameter mask_l2cache__reg9_lock_line_en = 32'hFFFFFFFF; parameter l2cache__reg9_unlock_way = 32'hF8F02954; parameter val_l2cache__reg9_unlock_way = 32'h00000000; parameter mask_l2cache__reg9_unlock_way = 32'hFFFFFFFF; parameter l2cache__reg12_addr_filtering_start = 32'hF8F02C00; parameter val_l2cache__reg12_addr_filtering_start = 32'h40000001; parameter mask_l2cache__reg12_addr_filtering_start = 32'hFFFFFFFF; parameter l2cache__reg12_addr_filtering_end = 32'hF8F02C04; parameter val_l2cache__reg12_addr_filtering_end = 32'hFFF00000; parameter mask_l2cache__reg12_addr_filtering_end = 32'hFFFFFFFF; parameter l2cache__reg15_debug_ctrl = 32'hF8F02F40; parameter val_l2cache__reg15_debug_ctrl = 32'h00000000; parameter mask_l2cache__reg15_debug_ctrl = 32'hFFFFFFFF; parameter l2cache__reg15_prefetch_ctrl = 32'hF8F02F60; parameter val_l2cache__reg15_prefetch_ctrl = 32'h00000000; parameter mask_l2cache__reg15_prefetch_ctrl = 32'hFFFFFFFF; parameter l2cache__reg15_power_ctrl = 32'hF8F02F80; parameter val_l2cache__reg15_power_ctrl = 32'h00000000; parameter mask_l2cache__reg15_power_ctrl = 32'hFFFFFFFF; // ************************************************************ // Module mpcore mpcore // doc version: 1.3 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter mpcore__SCU_CONTROL_REGISTER = 32'hF8F00000; parameter val_mpcore__SCU_CONTROL_REGISTER = 32'h00000002; parameter mask_mpcore__SCU_CONTROL_REGISTER = 32'hFFFFFFFF; parameter mpcore__SCU_CONFIGURATION_REGISTER = 32'hF8F00004; parameter val_mpcore__SCU_CONFIGURATION_REGISTER = 32'h00000501; parameter mask_mpcore__SCU_CONFIGURATION_REGISTER = 32'hFFFFFFFF; parameter mpcore__SCU_CPU_Power_Status_Register = 32'hF8F00008; parameter val_mpcore__SCU_CPU_Power_Status_Register = 32'h00000000; parameter mask_mpcore__SCU_CPU_Power_Status_Register = 32'hFFFFFFFF; parameter mpcore__SCU_Invalidate_All_Registers_in_Secure_State = 32'hF8F0000C; parameter val_mpcore__SCU_Invalidate_All_Registers_in_Secure_State = 32'h00000000; parameter mask_mpcore__SCU_Invalidate_All_Registers_in_Secure_State = 32'hFFFFFFFF; parameter mpcore__Filtering_Start_Address_Register = 32'hF8F00040; parameter val_mpcore__Filtering_Start_Address_Register = 32'h00100000; parameter mask_mpcore__Filtering_Start_Address_Register = 32'hFFFFFFFF; parameter mpcore__Filtering_End_Address_Register = 32'hF8F00044; parameter val_mpcore__Filtering_End_Address_Register = 32'h00000000; parameter mask_mpcore__Filtering_End_Address_Register = 32'hFFFFFFFF; parameter mpcore__SCU_Access_Control_Register_SAC = 32'hF8F00050; parameter val_mpcore__SCU_Access_Control_Register_SAC = 32'h0000000F; parameter mask_mpcore__SCU_Access_Control_Register_SAC = 32'hFFFFFFFF; parameter mpcore__SCU_Non_secure_Access_Control_Register = 32'hF8F00054; parameter val_mpcore__SCU_Non_secure_Access_Control_Register = 32'h00000000; parameter mask_mpcore__SCU_Non_secure_Access_Control_Register = 32'hFFFFFFFF; parameter mpcore__ICCICR = 32'hF8F00100; parameter val_mpcore__ICCICR = 32'h00000000; parameter mask_mpcore__ICCICR = 32'hFFFFFFFF; parameter mpcore__ICCPMR = 32'hF8F00104; parameter val_mpcore__ICCPMR = 32'h00000000; parameter mask_mpcore__ICCPMR = 32'hFFFFFFFF; parameter mpcore__ICCBPR = 32'hF8F00108; parameter val_mpcore__ICCBPR = 32'h00000002; parameter mask_mpcore__ICCBPR = 32'hFFFFFFFF; parameter mpcore__ICCIAR = 32'hF8F0010C; parameter val_mpcore__ICCIAR = 32'h000003FF; parameter mask_mpcore__ICCIAR = 32'hFFFFFFFF; parameter mpcore__ICCEOIR = 32'hF8F00110; parameter val_mpcore__ICCEOIR = 32'h00000000; parameter mask_mpcore__ICCEOIR = 32'hFFFFFFFF; parameter mpcore__ICCRPR = 32'hF8F00114; parameter val_mpcore__ICCRPR = 32'h000000FF; parameter mask_mpcore__ICCRPR = 32'hFFFFFFFF; parameter mpcore__ICCHPIR = 32'hF8F00118; parameter val_mpcore__ICCHPIR = 32'h000003FF; parameter mask_mpcore__ICCHPIR = 32'hFFFFFFFF; parameter mpcore__ICCABPR = 32'hF8F0011C; parameter val_mpcore__ICCABPR = 32'h00000003; parameter mask_mpcore__ICCABPR = 32'hFFFFFFFF; parameter mpcore__ICCIDR = 32'hF8F001FC; parameter val_mpcore__ICCIDR = 32'h3901243B; parameter mask_mpcore__ICCIDR = 32'hFFFFFFFF; parameter mpcore__Global_Timer_Counter_Register0 = 32'hF8F00200; parameter val_mpcore__Global_Timer_Counter_Register0 = 32'h00000000; parameter mask_mpcore__Global_Timer_Counter_Register0 = 32'hFFFFFFFF; parameter mpcore__Global_Timer_Counter_Register1 = 32'hF8F00204; parameter val_mpcore__Global_Timer_Counter_Register1 = 32'h00000000; parameter mask_mpcore__Global_Timer_Counter_Register1 = 32'hFFFFFFFF; parameter mpcore__Global_Timer_Control_Register = 32'hF8F00208; parameter val_mpcore__Global_Timer_Control_Register = 32'h00000000; parameter mask_mpcore__Global_Timer_Control_Register = 32'hFFFFFFFF; parameter mpcore__Global_Timer_Interrupt_Status_Register = 32'hF8F0020C; parameter val_mpcore__Global_Timer_Interrupt_Status_Register = 32'h00000000; parameter mask_mpcore__Global_Timer_Interrupt_Status_Register = 32'hFFFFFFFF; parameter mpcore__Comparator_Value_Register0 = 32'hF8F00210; parameter val_mpcore__Comparator_Value_Register0 = 32'h00000000; parameter mask_mpcore__Comparator_Value_Register0 = 32'hFFFFFFFF; parameter mpcore__Comparator_Value_Register1 = 32'hF8F00214; parameter val_mpcore__Comparator_Value_Register1 = 32'h00000000; parameter mask_mpcore__Comparator_Value_Register1 = 32'hFFFFFFFF; parameter mpcore__Auto_increment_Register = 32'hF8F00218; parameter val_mpcore__Auto_increment_Register = 32'h00000000; parameter mask_mpcore__Auto_increment_Register = 32'hFFFFFFFF; parameter mpcore__Private_Timer_Load_Register = 32'hF8F00600; parameter val_mpcore__Private_Timer_Load_Register = 32'h00000000; parameter mask_mpcore__Private_Timer_Load_Register = 32'hFFFFFFFF; parameter mpcore__Private_Timer_Counter_Register = 32'hF8F00604; parameter val_mpcore__Private_Timer_Counter_Register = 32'h00000000; parameter mask_mpcore__Private_Timer_Counter_Register = 32'hFFFFFFFF; parameter mpcore__Private_Timer_Control_Register = 32'hF8F00608; parameter val_mpcore__Private_Timer_Control_Register = 32'h00000000; parameter mask_mpcore__Private_Timer_Control_Register = 32'hFFFFFFFF; parameter mpcore__Private_Timer_Interrupt_Status_Register = 32'hF8F0060C; parameter val_mpcore__Private_Timer_Interrupt_Status_Register = 32'h00000000; parameter mask_mpcore__Private_Timer_Interrupt_Status_Register = 32'hFFFFFFFF; parameter mpcore__Watchdog_Load_Register = 32'hF8F00620; parameter val_mpcore__Watchdog_Load_Register = 32'h00000000; parameter mask_mpcore__Watchdog_Load_Register = 32'hFFFFFFFF; parameter mpcore__Watchdog_Counter_Register = 32'hF8F00624; parameter val_mpcore__Watchdog_Counter_Register = 32'h00000000; parameter mask_mpcore__Watchdog_Counter_Register = 32'hFFFFFFFF; parameter mpcore__Watchdog_Control_Register = 32'hF8F00628; parameter val_mpcore__Watchdog_Control_Register = 32'h00000000; parameter mask_mpcore__Watchdog_Control_Register = 32'hFFFFFFFF; parameter mpcore__Watchdog_Interrupt_Status_Register = 32'hF8F0062C; parameter val_mpcore__Watchdog_Interrupt_Status_Register = 32'h00000000; parameter mask_mpcore__Watchdog_Interrupt_Status_Register = 32'hFFFFFFFF; parameter mpcore__Watchdog_Reset_Status_Register = 32'hF8F00630; parameter val_mpcore__Watchdog_Reset_Status_Register = 32'h00000000; parameter mask_mpcore__Watchdog_Reset_Status_Register = 32'hFFFFFFFF; parameter mpcore__Watchdog_Disable_Register = 32'hF8F00634; parameter val_mpcore__Watchdog_Disable_Register = 32'h00000000; parameter mask_mpcore__Watchdog_Disable_Register = 32'hFFFFFFFF; parameter mpcore__ICDDCR = 32'hF8F01000; parameter val_mpcore__ICDDCR = 32'h00000000; parameter mask_mpcore__ICDDCR = 32'hFFFFFFFF; parameter mpcore__ICDICTR = 32'hF8F01004; parameter val_mpcore__ICDICTR = 32'h00000C22; parameter mask_mpcore__ICDICTR = 32'hE000FFFF; parameter mpcore__ICDIIDR = 32'hF8F01008; parameter val_mpcore__ICDIIDR = 32'h0102043B; parameter mask_mpcore__ICDIIDR = 32'hFFFFFFFF; parameter mpcore__ICDISR0 = 32'hF8F01080; parameter val_mpcore__ICDISR0 = 32'h00000000; parameter mask_mpcore__ICDISR0 = 32'hFFFFFFFF; parameter mpcore__ICDISR1 = 32'hF8F01084; parameter val_mpcore__ICDISR1 = 32'h00000000; parameter mask_mpcore__ICDISR1 = 32'hFFFFFFFF; parameter mpcore__ICDISR2 = 32'hF8F01088; parameter val_mpcore__ICDISR2 = 32'h00000000; parameter mask_mpcore__ICDISR2 = 32'hFFFFFFFF; parameter mpcore__ICDISER0 = 32'hF8F01100; parameter val_mpcore__ICDISER0 = 32'h0000FFFF; parameter mask_mpcore__ICDISER0 = 32'hFFFFFFFF; parameter mpcore__ICDISER1 = 32'hF8F01104; parameter val_mpcore__ICDISER1 = 32'h00000000; parameter mask_mpcore__ICDISER1 = 32'hFFFFFFFF; parameter mpcore__ICDISER2 = 32'hF8F01108; parameter val_mpcore__ICDISER2 = 32'h00000000; parameter mask_mpcore__ICDISER2 = 32'hFFFFFFFF; parameter mpcore__ICDICER0 = 32'hF8F01180; parameter val_mpcore__ICDICER0 = 32'h0000FFFF; parameter mask_mpcore__ICDICER0 = 32'hFFFFFFFF; parameter mpcore__ICDICER1 = 32'hF8F01184; parameter val_mpcore__ICDICER1 = 32'h00000000; parameter mask_mpcore__ICDICER1 = 32'hFFFFFFFF; parameter mpcore__ICDICER2 = 32'hF8F01188; parameter val_mpcore__ICDICER2 = 32'h00000000; parameter mask_mpcore__ICDICER2 = 32'hFFFFFFFF; parameter mpcore__ICDISPR0 = 32'hF8F01200; parameter val_mpcore__ICDISPR0 = 32'h00000000; parameter mask_mpcore__ICDISPR0 = 32'hFFFFFFFF; parameter mpcore__ICDISPR1 = 32'hF8F01204; parameter val_mpcore__ICDISPR1 = 32'h00000000; parameter mask_mpcore__ICDISPR1 = 32'hFFFFFFFF; parameter mpcore__ICDISPR2 = 32'hF8F01208; parameter val_mpcore__ICDISPR2 = 32'h00000000; parameter mask_mpcore__ICDISPR2 = 32'hFFFFFFFF; parameter mpcore__ICDICPR0 = 32'hF8F01280; parameter val_mpcore__ICDICPR0 = 32'h00000000; parameter mask_mpcore__ICDICPR0 = 32'hFFFFFFFF; parameter mpcore__ICDICPR1 = 32'hF8F01284; parameter val_mpcore__ICDICPR1 = 32'h00000000; parameter mask_mpcore__ICDICPR1 = 32'hFFFFFFFF; parameter mpcore__ICDICPR2 = 32'hF8F01288; parameter val_mpcore__ICDICPR2 = 32'h00000000; parameter mask_mpcore__ICDICPR2 = 32'hFFFFFFFF; parameter mpcore__ICDABR0 = 32'hF8F01300; parameter val_mpcore__ICDABR0 = 32'h00000000; parameter mask_mpcore__ICDABR0 = 32'hFFFFFFFF; parameter mpcore__ICDABR1 = 32'hF8F01304; parameter val_mpcore__ICDABR1 = 32'h00000000; parameter mask_mpcore__ICDABR1 = 32'hFFFFFFFF; parameter mpcore__ICDABR2 = 32'hF8F01308; parameter val_mpcore__ICDABR2 = 32'h00000000; parameter mask_mpcore__ICDABR2 = 32'hFFFFFFFF; parameter mpcore__ICDIPR0 = 32'hF8F01400; parameter val_mpcore__ICDIPR0 = 32'h00000000; parameter mask_mpcore__ICDIPR0 = 32'hFFFFFFFF; parameter mpcore__ICDIPR1 = 32'hF8F01404; parameter val_mpcore__ICDIPR1 = 32'h00000000; parameter mask_mpcore__ICDIPR1 = 32'hFFFFFFFF; parameter mpcore__ICDIPR2 = 32'hF8F01408; parameter val_mpcore__ICDIPR2 = 32'h00000000; parameter mask_mpcore__ICDIPR2 = 32'hFFFFFFFF; parameter mpcore__ICDIPR3 = 32'hF8F0140C; parameter val_mpcore__ICDIPR3 = 32'h00000000; parameter mask_mpcore__ICDIPR3 = 32'hFFFFFFFF; parameter mpcore__ICDIPR4 = 32'hF8F01410; parameter val_mpcore__ICDIPR4 = 32'h00000000; parameter mask_mpcore__ICDIPR4 = 32'hFFFFFFFF; parameter mpcore__ICDIPR5 = 32'hF8F01414; parameter val_mpcore__ICDIPR5 = 32'h00000000; parameter mask_mpcore__ICDIPR5 = 32'hFFFFFFFF; parameter mpcore__ICDIPR6 = 32'hF8F01418; parameter val_mpcore__ICDIPR6 = 32'h00000000; parameter mask_mpcore__ICDIPR6 = 32'hFFFFFFFF; parameter mpcore__ICDIPR7 = 32'hF8F0141C; parameter val_mpcore__ICDIPR7 = 32'h00000000; parameter mask_mpcore__ICDIPR7 = 32'hFFFFFFFF; parameter mpcore__ICDIPR8 = 32'hF8F01420; parameter val_mpcore__ICDIPR8 = 32'h00000000; parameter mask_mpcore__ICDIPR8 = 32'hFFFFFFFF; parameter mpcore__ICDIPR9 = 32'hF8F01424; parameter val_mpcore__ICDIPR9 = 32'h00000000; parameter mask_mpcore__ICDIPR9 = 32'hFFFFFFFF; parameter mpcore__ICDIPR10 = 32'hF8F01428; parameter val_mpcore__ICDIPR10 = 32'h00000000; parameter mask_mpcore__ICDIPR10 = 32'hFFFFFFFF; parameter mpcore__ICDIPR11 = 32'hF8F0142C; parameter val_mpcore__ICDIPR11 = 32'h00000000; parameter mask_mpcore__ICDIPR11 = 32'hFFFFFFFF; parameter mpcore__ICDIPR12 = 32'hF8F01430; parameter val_mpcore__ICDIPR12 = 32'h00000000; parameter mask_mpcore__ICDIPR12 = 32'hFFFFFFFF; parameter mpcore__ICDIPR13 = 32'hF8F01434; parameter val_mpcore__ICDIPR13 = 32'h00000000; parameter mask_mpcore__ICDIPR13 = 32'hFFFFFFFF; parameter mpcore__ICDIPR14 = 32'hF8F01438; parameter val_mpcore__ICDIPR14 = 32'h00000000; parameter mask_mpcore__ICDIPR14 = 32'hFFFFFFFF; parameter mpcore__ICDIPR15 = 32'hF8F0143C; parameter val_mpcore__ICDIPR15 = 32'h00000000; parameter mask_mpcore__ICDIPR15 = 32'hFFFFFFFF; parameter mpcore__ICDIPR16 = 32'hF8F01440; parameter val_mpcore__ICDIPR16 = 32'h00000000; parameter mask_mpcore__ICDIPR16 = 32'hFFFFFFFF; parameter mpcore__ICDIPR17 = 32'hF8F01444; parameter val_mpcore__ICDIPR17 = 32'h00000000; parameter mask_mpcore__ICDIPR17 = 32'hFFFFFFFF; parameter mpcore__ICDIPR18 = 32'hF8F01448; parameter val_mpcore__ICDIPR18 = 32'h00000000; parameter mask_mpcore__ICDIPR18 = 32'hFFFFFFFF; parameter mpcore__ICDIPR19 = 32'hF8F0144C; parameter val_mpcore__ICDIPR19 = 32'h00000000; parameter mask_mpcore__ICDIPR19 = 32'hFFFFFFFF; parameter mpcore__ICDIPR20 = 32'hF8F01450; parameter val_mpcore__ICDIPR20 = 32'h00000000; parameter mask_mpcore__ICDIPR20 = 32'hFFFFFFFF; parameter mpcore__ICDIPR21 = 32'hF8F01454; parameter val_mpcore__ICDIPR21 = 32'h00000000; parameter mask_mpcore__ICDIPR21 = 32'hFFFFFFFF; parameter mpcore__ICDIPR22 = 32'hF8F01458; parameter val_mpcore__ICDIPR22 = 32'h00000000; parameter mask_mpcore__ICDIPR22 = 32'hFFFFFFFF; parameter mpcore__ICDIPR23 = 32'hF8F0145C; parameter val_mpcore__ICDIPR23 = 32'h00000000; parameter mask_mpcore__ICDIPR23 = 32'hFFFFFFFF; parameter mpcore__ICDIPTR0 = 32'hF8F01800; parameter val_mpcore__ICDIPTR0 = 32'h01010101; parameter mask_mpcore__ICDIPTR0 = 32'hFFFFFFFF; parameter mpcore__ICDIPTR1 = 32'hF8F01804; parameter val_mpcore__ICDIPTR1 = 32'h01010101; parameter mask_mpcore__ICDIPTR1 = 32'hFFFFFFFF; parameter mpcore__ICDIPTR2 = 32'hF8F01808; parameter val_mpcore__ICDIPTR2 = 32'h01010101; parameter mask_mpcore__ICDIPTR2 = 32'hFFFFFFFF; parameter mpcore__ICDIPTR3 = 32'hF8F0180C; parameter val_mpcore__ICDIPTR3 = 32'h01010101; parameter mask_mpcore__ICDIPTR3 = 32'hFFFFFFFF; parameter mpcore__ICDIPTR4 = 32'hF8F01810; parameter val_mpcore__ICDIPTR4 = 32'h01010101; parameter mask_mpcore__ICDIPTR4 = 32'hFFFFFFFF; parameter mpcore__ICDIPTR5 = 32'hF8F01814; parameter val_mpcore__ICDIPTR5 = 32'h01010101; parameter mask_mpcore__ICDIPTR5 = 32'hFFFFFFFF; parameter mpcore__ICDIPTR6 = 32'hF8F01818; parameter val_mpcore__ICDIPTR6 = 32'h01010101; parameter mask_mpcore__ICDIPTR6 = 32'hFFFFFFFF; parameter mpcore__ICDIPTR7 = 32'hF8F0181C; parameter val_mpcore__ICDIPTR7 = 32'h01010101; parameter mask_mpcore__ICDIPTR7 = 32'hFFFFFFFF; parameter mpcore__ICDIPTR8 = 32'hF8F01820; parameter val_mpcore__ICDIPTR8 = 32'h01010101; parameter mask_mpcore__ICDIPTR8 = 32'hFFFFFFFF; parameter mpcore__ICDIPTR9 = 32'hF8F01824; parameter val_mpcore__ICDIPTR9 = 32'h01010101; parameter mask_mpcore__ICDIPTR9 = 32'hFFFFFFFF; parameter mpcore__ICDIPTR10 = 32'hF8F01828; parameter val_mpcore__ICDIPTR10 = 32'h01010101; parameter mask_mpcore__ICDIPTR10 = 32'hFFFFFFFF; parameter mpcore__ICDIPTR11 = 32'hF8F0182C; parameter val_mpcore__ICDIPTR11 = 32'h01010101; parameter mask_mpcore__ICDIPTR11 = 32'hFFFFFFFF; parameter mpcore__ICDIPTR12 = 32'hF8F01830; parameter val_mpcore__ICDIPTR12 = 32'h01010101; parameter mask_mpcore__ICDIPTR12 = 32'hFFFFFFFF; parameter mpcore__ICDIPTR13 = 32'hF8F01834; parameter val_mpcore__ICDIPTR13 = 32'h01010101; parameter mask_mpcore__ICDIPTR13 = 32'hFFFFFFFF; parameter mpcore__ICDIPTR14 = 32'hF8F01838; parameter val_mpcore__ICDIPTR14 = 32'h01010101; parameter mask_mpcore__ICDIPTR14 = 32'hFFFFFFFF; parameter mpcore__ICDIPTR15 = 32'hF8F0183C; parameter val_mpcore__ICDIPTR15 = 32'h01010101; parameter mask_mpcore__ICDIPTR15 = 32'hFFFFFFFF; parameter mpcore__ICDIPTR16 = 32'hF8F01840; parameter val_mpcore__ICDIPTR16 = 32'h01010101; parameter mask_mpcore__ICDIPTR16 = 32'hFFFFFFFF; parameter mpcore__ICDIPTR17 = 32'hF8F01844; parameter val_mpcore__ICDIPTR17 = 32'h01010101; parameter mask_mpcore__ICDIPTR17 = 32'hFFFFFFFF; parameter mpcore__ICDIPTR18 = 32'hF8F01848; parameter val_mpcore__ICDIPTR18 = 32'h01010101; parameter mask_mpcore__ICDIPTR18 = 32'hFFFFFFFF; parameter mpcore__ICDIPTR19 = 32'hF8F0184C; parameter val_mpcore__ICDIPTR19 = 32'h01010101; parameter mask_mpcore__ICDIPTR19 = 32'hFFFFFFFF; parameter mpcore__ICDIPTR20 = 32'hF8F01850; parameter val_mpcore__ICDIPTR20 = 32'h01010101; parameter mask_mpcore__ICDIPTR20 = 32'hFFFFFFFF; parameter mpcore__ICDIPTR21 = 32'hF8F01854; parameter val_mpcore__ICDIPTR21 = 32'h01010101; parameter mask_mpcore__ICDIPTR21 = 32'hFFFFFFFF; parameter mpcore__ICDIPTR22 = 32'hF8F01858; parameter val_mpcore__ICDIPTR22 = 32'h01010101; parameter mask_mpcore__ICDIPTR22 = 32'hFFFFFFFF; parameter mpcore__ICDIPTR23 = 32'hF8F0185C; parameter val_mpcore__ICDIPTR23 = 32'h01010101; parameter mask_mpcore__ICDIPTR23 = 32'hFFFFFFFF; parameter mpcore__ICDICFR0 = 32'hF8F01C00; parameter val_mpcore__ICDICFR0 = 32'hAAAAAAAA; parameter mask_mpcore__ICDICFR0 = 32'hFFFFFFFF; parameter mpcore__ICDICFR1 = 32'hF8F01C04; parameter val_mpcore__ICDICFR1 = 32'h7DC00000; parameter mask_mpcore__ICDICFR1 = 32'hFFFFFFFF; parameter mpcore__ICDICFR2 = 32'hF8F01C08; parameter val_mpcore__ICDICFR2 = 32'h55555555; parameter mask_mpcore__ICDICFR2 = 32'hFFFFFFFF; parameter mpcore__ICDICFR3 = 32'hF8F01C0C; parameter val_mpcore__ICDICFR3 = 32'h55555555; parameter mask_mpcore__ICDICFR3 = 32'hFFFFFFFF; parameter mpcore__ICDICFR4 = 32'hF8F01C10; parameter val_mpcore__ICDICFR4 = 32'h55555555; parameter mask_mpcore__ICDICFR4 = 32'hFFFFFFFF; parameter mpcore__ICDICFR5 = 32'hF8F01C14; parameter val_mpcore__ICDICFR5 = 32'h55555555; parameter mask_mpcore__ICDICFR5 = 32'hFFFFFFFF; parameter mpcore__ppi_status = 32'hF8F01D00; parameter val_mpcore__ppi_status = 32'h00000000; parameter mask_mpcore__ppi_status = 32'hFFFFFFFF; parameter mpcore__spi_status_0 = 32'hF8F01D04; parameter val_mpcore__spi_status_0 = 32'h00000000; parameter mask_mpcore__spi_status_0 = 32'hFFFFFFFF; parameter mpcore__spi_status_1 = 32'hF8F01D08; parameter val_mpcore__spi_status_1 = 32'h00000000; parameter mask_mpcore__spi_status_1 = 32'hFFFFFFFF; parameter mpcore__ICDSGIR = 32'hF8F01F00; parameter val_mpcore__ICDSGIR = 32'h00000000; parameter mask_mpcore__ICDSGIR = 32'hFFFFFFFF; parameter mpcore__ICPIDR4 = 32'hF8F01FD0; parameter val_mpcore__ICPIDR4 = 32'h00000004; parameter mask_mpcore__ICPIDR4 = 32'hFFFFFFFF; parameter mpcore__ICPIDR5 = 32'hF8F01FD4; parameter val_mpcore__ICPIDR5 = 32'h00000000; parameter mask_mpcore__ICPIDR5 = 32'hFFFFFFFF; parameter mpcore__ICPIDR6 = 32'hF8F01FD8; parameter val_mpcore__ICPIDR6 = 32'h00000000; parameter mask_mpcore__ICPIDR6 = 32'hFFFFFFFF; parameter mpcore__ICPIDR7 = 32'hF8F01FDC; parameter val_mpcore__ICPIDR7 = 32'h00000000; parameter mask_mpcore__ICPIDR7 = 32'hFFFFFFFF; parameter mpcore__ICPIDR0 = 32'hF8F01FE0; parameter val_mpcore__ICPIDR0 = 32'h00000090; parameter mask_mpcore__ICPIDR0 = 32'hFFFFFFFF; parameter mpcore__ICPIDR1 = 32'hF8F01FE4; parameter val_mpcore__ICPIDR1 = 32'h000000B3; parameter mask_mpcore__ICPIDR1 = 32'hFFFFFFFF; parameter mpcore__ICPIDR2 = 32'hF8F01FE8; parameter val_mpcore__ICPIDR2 = 32'h0000001B; parameter mask_mpcore__ICPIDR2 = 32'hFFFFFFFF; parameter mpcore__ICPIDR3 = 32'hF8F01FEC; parameter val_mpcore__ICPIDR3 = 32'h00000000; parameter mask_mpcore__ICPIDR3 = 32'hFFFFFFFF; parameter mpcore__ICCIDR0 = 32'hF8F01FF0; parameter val_mpcore__ICCIDR0 = 32'h0000000D; parameter mask_mpcore__ICCIDR0 = 32'hFFFFFFFF; parameter mpcore__ICCIDR1 = 32'hF8F01FF4; parameter val_mpcore__ICCIDR1 = 32'h000000F0; parameter mask_mpcore__ICCIDR1 = 32'hFFFFFFFF; parameter mpcore__ICCIDR2 = 32'hF8F01FF8; parameter val_mpcore__ICCIDR2 = 32'h00000005; parameter mask_mpcore__ICCIDR2 = 32'hFFFFFFFF; parameter mpcore__ICCIDR3 = 32'hF8F01FFC; parameter val_mpcore__ICCIDR3 = 32'h000000B1; parameter mask_mpcore__ICCIDR3 = 32'hFFFFFFFF; // ************************************************************ // Module ocm ocm // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter ocm__OCM_PARITY_CTRL = 32'hF800C000; parameter val_ocm__OCM_PARITY_CTRL = 32'h00000000; parameter mask_ocm__OCM_PARITY_CTRL = 32'hFFFFFFFF; parameter ocm__OCM_PARITY_ERRADDRESS = 32'hF800C004; parameter val_ocm__OCM_PARITY_ERRADDRESS = 32'h00000000; parameter mask_ocm__OCM_PARITY_ERRADDRESS = 32'hFFFFFFFF; parameter ocm__OCM_IRQ_STS = 32'hF800C008; parameter val_ocm__OCM_IRQ_STS = 32'h00000000; parameter mask_ocm__OCM_IRQ_STS = 32'hFFFFFFFF; parameter ocm__OCM_CONTROL = 32'hF800C00C; parameter val_ocm__OCM_CONTROL = 32'h00000000; parameter mask_ocm__OCM_CONTROL = 32'hFFFFFFFF; // ************************************************************ // Module qspi qspi // doc version: 0.8, based on 11/01/10 Linear Quad-SPI Controller // Design Specification document // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter qspi__Config_reg = 32'hE000D000; parameter val_qspi__Config_reg = 32'h80000000; parameter mask_qspi__Config_reg = 32'hFFFDFFFF; parameter qspi__Intr_status_REG = 32'hE000D004; parameter val_qspi__Intr_status_REG = 32'h00000004; parameter mask_qspi__Intr_status_REG = 32'hFFFFFFFF; parameter qspi__Intrpt_en_REG = 32'hE000D008; parameter val_qspi__Intrpt_en_REG = 32'h00000000; parameter mask_qspi__Intrpt_en_REG = 32'hFFFFFFFF; parameter qspi__Intrpt_dis_REG = 32'hE000D00C; parameter val_qspi__Intrpt_dis_REG = 32'h00000000; parameter mask_qspi__Intrpt_dis_REG = 32'hFFFFFFFF; parameter qspi__Intrpt_mask_REG = 32'hE000D010; parameter val_qspi__Intrpt_mask_REG = 32'h00000000; parameter mask_qspi__Intrpt_mask_REG = 32'hFFFFFFFF; parameter qspi__En_REG = 32'hE000D014; parameter val_qspi__En_REG = 32'h00000000; parameter mask_qspi__En_REG = 32'hFFFFFFFF; parameter qspi__Delay_REG = 32'hE000D018; parameter val_qspi__Delay_REG = 32'h00000000; parameter mask_qspi__Delay_REG = 32'hFFFFFFFF; parameter qspi__TXD0 = 32'hE000D01C; parameter val_qspi__TXD0 = 32'h00000000; parameter mask_qspi__TXD0 = 32'hFFFFFFFF; parameter qspi__Rx_data_REG = 32'hE000D020; parameter val_qspi__Rx_data_REG = 32'h00000000; parameter mask_qspi__Rx_data_REG = 32'hFFFFFFFF; parameter qspi__Slave_Idle_count_REG = 32'hE000D024; parameter val_qspi__Slave_Idle_count_REG = 32'h000000FF; parameter mask_qspi__Slave_Idle_count_REG = 32'hFFFFFFFF; parameter qspi__TX_thres_REG = 32'hE000D028; parameter val_qspi__TX_thres_REG = 32'h00000001; parameter mask_qspi__TX_thres_REG = 32'hFFFFFFFF; parameter qspi__RX_thres_REG = 32'hE000D02C; parameter val_qspi__RX_thres_REG = 32'h00000001; parameter mask_qspi__RX_thres_REG = 32'hFFFFFFFF; parameter qspi__GPIO = 32'hE000D030; parameter val_qspi__GPIO = 32'h00000001; parameter mask_qspi__GPIO = 32'hFFFFFFFF; parameter qspi__LPBK_DLY_ADJ = 32'hE000D038; parameter val_qspi__LPBK_DLY_ADJ = 32'h00000033; parameter mask_qspi__LPBK_DLY_ADJ = 32'hFFFFFFFF; parameter qspi__TXD1 = 32'hE000D080; parameter val_qspi__TXD1 = 32'h00000000; parameter mask_qspi__TXD1 = 32'hFFFFFFFF; parameter qspi__TXD2 = 32'hE000D084; parameter val_qspi__TXD2 = 32'h00000000; parameter mask_qspi__TXD2 = 32'hFFFFFFFF; parameter qspi__TXD3 = 32'hE000D088; parameter val_qspi__TXD3 = 32'h00000000; parameter mask_qspi__TXD3 = 32'hFFFFFFFF; parameter qspi__LQSPI_CFG = 32'hE000D0A0; parameter val_qspi__LQSPI_CFG = 32'h03A002EB; parameter mask_qspi__LQSPI_CFG = 32'hFBFF07FF; parameter qspi__LQSPI_STS = 32'hE000D0A4; parameter val_qspi__LQSPI_STS = 32'h00000000; parameter mask_qspi__LQSPI_STS = 32'h000001FF; parameter qspi__MOD_ID = 32'hE000D0FC; parameter val_qspi__MOD_ID = 32'h01090101; parameter mask_qspi__MOD_ID = 32'hFFFFFFFF; // ************************************************************ // Module sd0 sdio // doc version: 4.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter sd0__SDMA_system_address_register = 32'hE0100000; parameter val_sd0__SDMA_system_address_register = 32'h00000000; parameter mask_sd0__SDMA_system_address_register = 32'hFFFFFFFF; parameter sd0__Block_Size_Block_Count = 32'hE0100004; parameter val_sd0__Block_Size_Block_Count = 32'h00000000; parameter mask_sd0__Block_Size_Block_Count = 32'hFFFFFFFF; parameter sd0__Argument = 32'hE0100008; parameter val_sd0__Argument = 32'h00000000; parameter mask_sd0__Argument = 32'hFFFFFFFF; parameter sd0__Transfer_Mode_Command = 32'hE010000C; parameter val_sd0__Transfer_Mode_Command = 32'h00000000; parameter mask_sd0__Transfer_Mode_Command = 32'h1FFFFFFF; parameter sd0__Response0 = 32'hE0100010; parameter val_sd0__Response0 = 32'h00000000; parameter mask_sd0__Response0 = 32'hFFFFFFFF; parameter sd0__Response1 = 32'hE0100014; parameter val_sd0__Response1 = 32'h00000000; parameter mask_sd0__Response1 = 32'hFFFFFFFF; parameter sd0__Response2 = 32'hE0100018; parameter val_sd0__Response2 = 32'h00000000; parameter mask_sd0__Response2 = 32'hFFFFFFFF; parameter sd0__Response3 = 32'hE010001C; parameter val_sd0__Response3 = 32'h00000000; parameter mask_sd0__Response3 = 32'hFFFFFFFF; parameter sd0__Buffer_Data_Port = 32'hE0100020; parameter val_sd0__Buffer_Data_Port = 32'h00000000; parameter mask_sd0__Buffer_Data_Port = 32'hFFFFFFFF; parameter sd0__Present_State = 32'hE0100024; parameter val_sd0__Present_State = 32'h01F20000; parameter mask_sd0__Present_State = 32'h01FFFFFF; parameter sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hE0100028; parameter val_sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'h00000000; parameter mask_sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hFFFFFFFF; parameter sd0__Clock_Control_Timeout_control_Software_reset = 32'hE010002C; parameter val_sd0__Clock_Control_Timeout_control_Software_reset = 32'h00000000; parameter mask_sd0__Clock_Control_Timeout_control_Software_reset = 32'h07FFFFFF; parameter sd0__Normal_interrupt_status_Error_interrupt_status = 32'hE0100030; parameter val_sd0__Normal_interrupt_status_Error_interrupt_status = 32'h00000000; parameter mask_sd0__Normal_interrupt_status_Error_interrupt_status = 32'h3FFFFFFF; parameter sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'hE0100034; parameter val_sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h00000000; parameter mask_sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h3FFFFFFF; parameter sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'hE0100038; parameter val_sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h00000000; parameter mask_sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h3FFFFFFF; parameter sd0__Auto_CMD12_error_status = 32'hE010003C; parameter val_sd0__Auto_CMD12_error_status = 32'h00000000; parameter mask_sd0__Auto_CMD12_error_status = 32'h000000FF; parameter sd0__Capabilities = 32'hE0100040; parameter val_sd0__Capabilities = 32'h69EC0080; parameter mask_sd0__Capabilities = 32'h7FFFFFFF; parameter sd0__Maximum_current_capabilities = 32'hE0100048; parameter val_sd0__Maximum_current_capabilities = 32'h00000001; parameter mask_sd0__Maximum_current_capabilities = 32'h00FFFFFF; parameter sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hE0100050; parameter val_sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'h00000000; parameter mask_sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hFFFFFFFF; parameter sd0__ADMA_error_status = 32'hE0100054; parameter val_sd0__ADMA_error_status = 32'h00000000; parameter mask_sd0__ADMA_error_status = 32'h00000007; parameter sd0__ADMA_system_address = 32'hE0100058; parameter val_sd0__ADMA_system_address = 32'h00000000; parameter mask_sd0__ADMA_system_address = 32'hFFFFFFFF; parameter sd0__Boot_Timeout_control = 32'hE0100060; parameter val_sd0__Boot_Timeout_control = 32'h00000000; parameter mask_sd0__Boot_Timeout_control = 32'hFFFFFFFF; parameter sd0__Debug_Selection = 32'hE0100064; parameter val_sd0__Debug_Selection = 32'h00000000; parameter mask_sd0__Debug_Selection = 32'h00000001; parameter sd0__SPI_interrupt_support = 32'hE01000F0; parameter val_sd0__SPI_interrupt_support = 32'h00000000; parameter mask_sd0__SPI_interrupt_support = 32'h000000FF; parameter sd0__Slot_interrupt_status_Host_controller_version = 32'hE01000FC; parameter val_sd0__Slot_interrupt_status_Host_controller_version = 32'h89010000; parameter mask_sd0__Slot_interrupt_status_Host_controller_version = 32'hFFFFFFFF; // ************************************************************ // Module sd1 sdio // doc version: 4.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter sd1__SDMA_system_address_register = 32'hE0101000; parameter val_sd1__SDMA_system_address_register = 32'h00000000; parameter mask_sd1__SDMA_system_address_register = 32'hFFFFFFFF; parameter sd1__Block_Size_Block_Count = 32'hE0101004; parameter val_sd1__Block_Size_Block_Count = 32'h00000000; parameter mask_sd1__Block_Size_Block_Count = 32'hFFFFFFFF; parameter sd1__Argument = 32'hE0101008; parameter val_sd1__Argument = 32'h00000000; parameter mask_sd1__Argument = 32'hFFFFFFFF; parameter sd1__Transfer_Mode_Command = 32'hE010100C; parameter val_sd1__Transfer_Mode_Command = 32'h00000000; parameter mask_sd1__Transfer_Mode_Command = 32'h1FFFFFFF; parameter sd1__Response0 = 32'hE0101010; parameter val_sd1__Response0 = 32'h00000000; parameter mask_sd1__Response0 = 32'hFFFFFFFF; parameter sd1__Response1 = 32'hE0101014; parameter val_sd1__Response1 = 32'h00000000; parameter mask_sd1__Response1 = 32'hFFFFFFFF; parameter sd1__Response2 = 32'hE0101018; parameter val_sd1__Response2 = 32'h00000000; parameter mask_sd1__Response2 = 32'hFFFFFFFF; parameter sd1__Response3 = 32'hE010101C; parameter val_sd1__Response3 = 32'h00000000; parameter mask_sd1__Response3 = 32'hFFFFFFFF; parameter sd1__Buffer_Data_Port = 32'hE0101020; parameter val_sd1__Buffer_Data_Port = 32'h00000000; parameter mask_sd1__Buffer_Data_Port = 32'hFFFFFFFF; parameter sd1__Present_State = 32'hE0101024; parameter val_sd1__Present_State = 32'h01F20000; parameter mask_sd1__Present_State = 32'h01FFFFFF; parameter sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hE0101028; parameter val_sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'h00000000; parameter mask_sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hFFFFFFFF; parameter sd1__Clock_Control_Timeout_control_Software_reset = 32'hE010102C; parameter val_sd1__Clock_Control_Timeout_control_Software_reset = 32'h00000000; parameter mask_sd1__Clock_Control_Timeout_control_Software_reset = 32'h07FFFFFF; parameter sd1__Normal_interrupt_status_Error_interrupt_status = 32'hE0101030; parameter val_sd1__Normal_interrupt_status_Error_interrupt_status = 32'h00000000; parameter mask_sd1__Normal_interrupt_status_Error_interrupt_status = 32'h3FFFFFFF; parameter sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'hE0101034; parameter val_sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h00000000; parameter mask_sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h3FFFFFFF; parameter sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'hE0101038; parameter val_sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h00000000; parameter mask_sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h3FFFFFFF; parameter sd1__Auto_CMD12_error_status = 32'hE010103C; parameter val_sd1__Auto_CMD12_error_status = 32'h00000000; parameter mask_sd1__Auto_CMD12_error_status = 32'h000000FF; parameter sd1__Capabilities = 32'hE0101040; parameter val_sd1__Capabilities = 32'h69EC0080; parameter mask_sd1__Capabilities = 32'h7FFFFFFF; parameter sd1__Maximum_current_capabilities = 32'hE0101048; parameter val_sd1__Maximum_current_capabilities = 32'h00000001; parameter mask_sd1__Maximum_current_capabilities = 32'h00FFFFFF; parameter sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hE0101050; parameter val_sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'h00000000; parameter mask_sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hFFFFFFFF; parameter sd1__ADMA_error_status = 32'hE0101054; parameter val_sd1__ADMA_error_status = 32'h00000000; parameter mask_sd1__ADMA_error_status = 32'h00000007; parameter sd1__ADMA_system_address = 32'hE0101058; parameter val_sd1__ADMA_system_address = 32'h00000000; parameter mask_sd1__ADMA_system_address = 32'hFFFFFFFF; parameter sd1__Boot_Timeout_control = 32'hE0101060; parameter val_sd1__Boot_Timeout_control = 32'h00000000; parameter mask_sd1__Boot_Timeout_control = 32'hFFFFFFFF; parameter sd1__Debug_Selection = 32'hE0101064; parameter val_sd1__Debug_Selection = 32'h00000000; parameter mask_sd1__Debug_Selection = 32'h00000001; parameter sd1__SPI_interrupt_support = 32'hE01010F0; parameter val_sd1__SPI_interrupt_support = 32'h00000000; parameter mask_sd1__SPI_interrupt_support = 32'h000000FF; parameter sd1__Slot_interrupt_status_Host_controller_version = 32'hE01010FC; parameter val_sd1__Slot_interrupt_status_Host_controller_version = 32'h89010000; parameter mask_sd1__Slot_interrupt_status_Host_controller_version = 32'hFFFFFFFF; // ************************************************************ // Module slcr slcr // doc version: 1.3, based on 11/18/2010 SLCR_spec.doc // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter slcr__SCL = 32'hF8000000; parameter val_slcr__SCL = 32'h00000000; parameter mask_slcr__SCL = 32'hFFFFFFFF; parameter slcr__SLCR_LOCK = 32'hF8000004; parameter val_slcr__SLCR_LOCK = 32'h00000000; parameter mask_slcr__SLCR_LOCK = 32'hFFFFFFFF; parameter slcr__SLCR_UNLOCK = 32'hF8000008; parameter val_slcr__SLCR_UNLOCK = 32'h00000000; parameter mask_slcr__SLCR_UNLOCK = 32'hFFFFFFFF; parameter slcr__SLCR_LOCKSTA = 32'hF800000C; parameter val_slcr__SLCR_LOCKSTA = 32'h00000001; parameter mask_slcr__SLCR_LOCKSTA = 32'hFFFFFFFF; parameter slcr__ARM_PLL_CTRL = 32'hF8000100; parameter val_slcr__ARM_PLL_CTRL = 32'h0001A008; parameter mask_slcr__ARM_PLL_CTRL = 32'hFFFFFFFF; parameter slcr__DDR_PLL_CTRL = 32'hF8000104; parameter val_slcr__DDR_PLL_CTRL = 32'h0001A008; parameter mask_slcr__DDR_PLL_CTRL = 32'hFFFFFFFF; parameter slcr__IO_PLL_CTRL = 32'hF8000108; parameter val_slcr__IO_PLL_CTRL = 32'h0001A008; parameter mask_slcr__IO_PLL_CTRL = 32'hFFFFFFFF; parameter slcr__PLL_STATUS = 32'hF800010C; parameter val_slcr__PLL_STATUS = 32'h0000003F; parameter mask_slcr__PLL_STATUS = 32'hFFFFFFFF; parameter slcr__ARM_PLL_CFG = 32'hF8000110; parameter val_slcr__ARM_PLL_CFG = 32'h00177EA0; parameter mask_slcr__ARM_PLL_CFG = 32'hFFFFFFFF; parameter slcr__DDR_PLL_CFG = 32'hF8000114; parameter val_slcr__DDR_PLL_CFG = 32'h00177EA0; parameter mask_slcr__DDR_PLL_CFG = 32'hFFFFFFFF; parameter slcr__IO_PLL_CFG = 32'hF8000118; parameter val_slcr__IO_PLL_CFG = 32'h00177EA0; parameter mask_slcr__IO_PLL_CFG = 32'hFFFFFFFF; parameter slcr__PLL_BG_CTRL = 32'hF800011C; parameter val_slcr__PLL_BG_CTRL = 32'h00000000; parameter mask_slcr__PLL_BG_CTRL = 32'hFFFFFFFF; parameter slcr__ARM_CLK_CTRL = 32'hF8000120; parameter val_slcr__ARM_CLK_CTRL = 32'h1F000400; parameter mask_slcr__ARM_CLK_CTRL = 32'hFFFFFFFF; parameter slcr__DDR_CLK_CTRL = 32'hF8000124; parameter val_slcr__DDR_CLK_CTRL = 32'h18400003; parameter mask_slcr__DDR_CLK_CTRL = 32'hFFFFFFFF; parameter slcr__DCI_CLK_CTRL = 32'hF8000128; parameter val_slcr__DCI_CLK_CTRL = 32'h01E03201; parameter mask_slcr__DCI_CLK_CTRL = 32'hFFFFFFFF; parameter slcr__APER_CLK_CTRL = 32'hF800012C; parameter val_slcr__APER_CLK_CTRL = 32'h01FFCCCD; parameter mask_slcr__APER_CLK_CTRL = 32'hFFFFFFFF; parameter slcr__USB0_CLK_CTRL = 32'hF8000130; parameter val_slcr__USB0_CLK_CTRL = 32'h00101941; parameter mask_slcr__USB0_CLK_CTRL = 32'hFFFFFFFF; parameter slcr__USB1_CLK_CTRL = 32'hF8000134; parameter val_slcr__USB1_CLK_CTRL = 32'h00101941; parameter mask_slcr__USB1_CLK_CTRL = 32'hFFFFFFFF; parameter slcr__GEM0_RCLK_CTRL = 32'hF8000138; parameter val_slcr__GEM0_RCLK_CTRL = 32'h00000001; parameter mask_slcr__GEM0_RCLK_CTRL = 32'hFFFFFFFF; parameter slcr__GEM1_RCLK_CTRL = 32'hF800013C; parameter val_slcr__GEM1_RCLK_CTRL = 32'h00000001; parameter mask_slcr__GEM1_RCLK_CTRL = 32'hFFFFFFFF; parameter slcr__GEM0_CLK_CTRL = 32'hF8000140; parameter val_slcr__GEM0_CLK_CTRL = 32'h00003C01; parameter mask_slcr__GEM0_CLK_CTRL = 32'hFFFFFFFF; parameter slcr__GEM1_CLK_CTRL = 32'hF8000144; parameter val_slcr__GEM1_CLK_CTRL = 32'h00003C01; parameter mask_slcr__GEM1_CLK_CTRL = 32'hFFFFFFFF; parameter slcr__SMC_CLK_CTRL = 32'hF8000148; parameter val_slcr__SMC_CLK_CTRL = 32'h00003C21; parameter mask_slcr__SMC_CLK_CTRL = 32'hFFFFFFFF; parameter slcr__LQSPI_CLK_CTRL = 32'hF800014C; parameter val_slcr__LQSPI_CLK_CTRL = 32'h00002821; parameter mask_slcr__LQSPI_CLK_CTRL = 32'hFFFFFFFF; parameter slcr__SDIO_CLK_CTRL = 32'hF8000150; parameter val_slcr__SDIO_CLK_CTRL = 32'h00001E03; parameter mask_slcr__SDIO_CLK_CTRL = 32'hFFFFFFFF; parameter slcr__UART_CLK_CTRL = 32'hF8000154; parameter val_slcr__UART_CLK_CTRL = 32'h00003F03; parameter mask_slcr__UART_CLK_CTRL = 32'hFFFFFFFF; parameter slcr__SPI_CLK_CTRL = 32'hF8000158; parameter val_slcr__SPI_CLK_CTRL = 32'h00003F03; parameter mask_slcr__SPI_CLK_CTRL = 32'hFFFFFFFF; parameter slcr__CAN_CLK_CTRL = 32'hF800015C; parameter val_slcr__CAN_CLK_CTRL = 32'h00501903; parameter mask_slcr__CAN_CLK_CTRL = 32'hFFFFFFFF; parameter slcr__CAN_MIOCLK_CTRL = 32'hF8000160; parameter val_slcr__CAN_MIOCLK_CTRL = 32'h00000000; parameter mask_slcr__CAN_MIOCLK_CTRL = 32'hFFFFFFFF; parameter slcr__DBG_CLK_CTRL = 32'hF8000164; parameter val_slcr__DBG_CLK_CTRL = 32'h00000F03; parameter mask_slcr__DBG_CLK_CTRL = 32'hFFFFFFFF; parameter slcr__PCAP_CLK_CTRL = 32'hF8000168; parameter val_slcr__PCAP_CLK_CTRL = 32'h00000F01; parameter mask_slcr__PCAP_CLK_CTRL = 32'hFFFFFFFF; parameter slcr__TOPSW_CLK_CTRL = 32'hF800016C; parameter val_slcr__TOPSW_CLK_CTRL = 32'h00000000; parameter mask_slcr__TOPSW_CLK_CTRL = 32'hFFFFFFFF; parameter slcr__FPGA0_CLK_CTRL = 32'hF8000170; parameter val_slcr__FPGA0_CLK_CTRL = 32'h00101800; parameter mask_slcr__FPGA0_CLK_CTRL = 32'hFFFFFFFF; parameter slcr__FPGA0_THR_CTRL = 32'hF8000174; parameter val_slcr__FPGA0_THR_CTRL = 32'h00000000; parameter mask_slcr__FPGA0_THR_CTRL = 32'hFFFFFFFF; parameter slcr__FPGA0_THR_CNT = 32'hF8000178; parameter val_slcr__FPGA0_THR_CNT = 32'h00000000; parameter mask_slcr__FPGA0_THR_CNT = 32'hFFFFFFFF; parameter slcr__FPGA0_THR_STA = 32'hF800017C; parameter val_slcr__FPGA0_THR_STA = 32'h00010000; parameter mask_slcr__FPGA0_THR_STA = 32'hFFFFFFFF; parameter slcr__FPGA1_CLK_CTRL = 32'hF8000180; parameter val_slcr__FPGA1_CLK_CTRL = 32'h00101800; parameter mask_slcr__FPGA1_CLK_CTRL = 32'hFFFFFFFF; parameter slcr__FPGA1_THR_CTRL = 32'hF8000184; parameter val_slcr__FPGA1_THR_CTRL = 32'h00000000; parameter mask_slcr__FPGA1_THR_CTRL = 32'hFFFFFFFF; parameter slcr__FPGA1_THR_CNT = 32'hF8000188; parameter val_slcr__FPGA1_THR_CNT = 32'h00000000; parameter mask_slcr__FPGA1_THR_CNT = 32'hFFFFFFFF; parameter slcr__FPGA1_THR_STA = 32'hF800018C; parameter val_slcr__FPGA1_THR_STA = 32'h00010000; parameter mask_slcr__FPGA1_THR_STA = 32'hFFFFFFFF; parameter slcr__FPGA2_CLK_CTRL = 32'hF8000190; parameter val_slcr__FPGA2_CLK_CTRL = 32'h00101800; parameter mask_slcr__FPGA2_CLK_CTRL = 32'hFFFFFFFF; parameter slcr__FPGA2_THR_CTRL = 32'hF8000194; parameter val_slcr__FPGA2_THR_CTRL = 32'h00000000; parameter mask_slcr__FPGA2_THR_CTRL = 32'hFFFFFFFF; parameter slcr__FPGA2_THR_CNT = 32'hF8000198; parameter val_slcr__FPGA2_THR_CNT = 32'h00000000; parameter mask_slcr__FPGA2_THR_CNT = 32'hFFFFFFFF; parameter slcr__FPGA2_THR_STA = 32'hF800019C; parameter val_slcr__FPGA2_THR_STA = 32'h00010000; parameter mask_slcr__FPGA2_THR_STA = 32'hFFFFFFFF; parameter slcr__FPGA3_CLK_CTRL = 32'hF80001A0; parameter val_slcr__FPGA3_CLK_CTRL = 32'h00101800; parameter mask_slcr__FPGA3_CLK_CTRL = 32'hFFFFFFFF; parameter slcr__FPGA3_THR_CTRL = 32'hF80001A4; parameter val_slcr__FPGA3_THR_CTRL = 32'h00000000; parameter mask_slcr__FPGA3_THR_CTRL = 32'hFFFFFFFF; parameter slcr__FPGA3_THR_CNT = 32'hF80001A8; parameter val_slcr__FPGA3_THR_CNT = 32'h00000000; parameter mask_slcr__FPGA3_THR_CNT = 32'hFFFFFFFF; parameter slcr__FPGA3_THR_STA = 32'hF80001AC; parameter val_slcr__FPGA3_THR_STA = 32'h00010000; parameter mask_slcr__FPGA3_THR_STA = 32'hFFFFFFFF; parameter slcr__SRST_UART_CTRL = 32'hF80001B0; parameter val_slcr__SRST_UART_CTRL = 32'h00000000; parameter mask_slcr__SRST_UART_CTRL = 32'hFFFFFFFF; parameter slcr__BANDGAP_TRIM = 32'hF80001B8; parameter val_slcr__BANDGAP_TRIM = 32'h0000001F; parameter mask_slcr__BANDGAP_TRIM = 32'hFFFFFFFF; parameter slcr__CC_TEST = 32'hF80001BC; parameter val_slcr__CC_TEST = 32'h00000000; parameter mask_slcr__CC_TEST = 32'hFFFFFFFF; parameter slcr__PLL_PREDIVISOR = 32'hF80001C0; parameter val_slcr__PLL_PREDIVISOR = 32'h00000001; parameter mask_slcr__PLL_PREDIVISOR = 32'hFFFFFFFF; parameter slcr__CLK_621_TRUE = 32'hF80001C4; parameter val_slcr__CLK_621_TRUE = 32'h00000001; parameter mask_slcr__CLK_621_TRUE = 32'hFFFFFFC1; parameter slcr__PICTURE_DBG = 32'hF80001D0; parameter val_slcr__PICTURE_DBG = 32'h00000000; parameter mask_slcr__PICTURE_DBG = 32'hFFFFFFFF; parameter slcr__PICTURE_DBG_UCNT = 32'hF80001D4; parameter val_slcr__PICTURE_DBG_UCNT = 32'h00000000; parameter mask_slcr__PICTURE_DBG_UCNT = 32'hFFFFFFFF; parameter slcr__PICTURE_DBG_LCNT = 32'hF80001D8; parameter val_slcr__PICTURE_DBG_LCNT = 32'h00000000; parameter mask_slcr__PICTURE_DBG_LCNT = 32'hFFFFFFFF; parameter slcr__PSS_RST_CTRL = 32'hF8000200; parameter val_slcr__PSS_RST_CTRL = 32'h00000000; parameter mask_slcr__PSS_RST_CTRL = 32'hFFFFFFFF; parameter slcr__DDR_RST_CTRL = 32'hF8000204; parameter val_slcr__DDR_RST_CTRL = 32'h00000000; parameter mask_slcr__DDR_RST_CTRL = 32'hFFFFFFFF; parameter slcr__TOPSW_RST_CTRL = 32'hF8000208; parameter val_slcr__TOPSW_RST_CTRL = 32'h00000000; parameter mask_slcr__TOPSW_RST_CTRL = 32'hFFFFFFFF; parameter slcr__DMAC_RST_CTRL = 32'hF800020C; parameter val_slcr__DMAC_RST_CTRL = 32'h00000000; parameter mask_slcr__DMAC_RST_CTRL = 32'hFFFFFFFF; parameter slcr__USB_RST_CTRL = 32'hF8000210; parameter val_slcr__USB_RST_CTRL = 32'h00000000; parameter mask_slcr__USB_RST_CTRL = 32'hFFFFFFFF; parameter slcr__GEM_RST_CTRL = 32'hF8000214; parameter val_slcr__GEM_RST_CTRL = 32'h00000000; parameter mask_slcr__GEM_RST_CTRL = 32'hFFFFFFFF; parameter slcr__SDIO_RST_CTRL = 32'hF8000218; parameter val_slcr__SDIO_RST_CTRL = 32'h00000000; parameter mask_slcr__SDIO_RST_CTRL = 32'hFFFFFFFF; parameter slcr__SPI_RST_CTRL = 32'hF800021C; parameter val_slcr__SPI_RST_CTRL = 32'h00000000; parameter mask_slcr__SPI_RST_CTRL = 32'hFFFFFFFF; parameter slcr__CAN_RST_CTRL = 32'hF8000220; parameter val_slcr__CAN_RST_CTRL = 32'h00000000; parameter mask_slcr__CAN_RST_CTRL = 32'hFFFFFFFF; parameter slcr__I2C_RST_CTRL = 32'hF8000224; parameter val_slcr__I2C_RST_CTRL = 32'h00000000; parameter mask_slcr__I2C_RST_CTRL = 32'hFFFFFFFF; parameter slcr__UART_RST_CTRL = 32'hF8000228; parameter val_slcr__UART_RST_CTRL = 32'h00000000; parameter mask_slcr__UART_RST_CTRL = 32'hFFFFFFFF; parameter slcr__GPIO_RST_CTRL = 32'hF800022C; parameter val_slcr__GPIO_RST_CTRL = 32'h00000000; parameter mask_slcr__GPIO_RST_CTRL = 32'hFFFFFFFF; parameter slcr__LQSPI_RST_CTRL = 32'hF8000230; parameter val_slcr__LQSPI_RST_CTRL = 32'h00000000; parameter mask_slcr__LQSPI_RST_CTRL = 32'hFFFFFFFF; parameter slcr__SMC_RST_CTRL = 32'hF8000234; parameter val_slcr__SMC_RST_CTRL = 32'h00000000; parameter mask_slcr__SMC_RST_CTRL = 32'hFFFFFFFF; parameter slcr__OCM_RST_CTRL = 32'hF8000238; parameter val_slcr__OCM_RST_CTRL = 32'h00000000; parameter mask_slcr__OCM_RST_CTRL = 32'hFFFFFFFF; parameter slcr__DEVCI_RST_CTRL = 32'hF800023C; parameter val_slcr__DEVCI_RST_CTRL = 32'h00000000; parameter mask_slcr__DEVCI_RST_CTRL = 32'hFFFFFFFF; parameter slcr__FPGA_RST_CTRL = 32'hF8000240; parameter val_slcr__FPGA_RST_CTRL = 32'h01F33F0F; parameter mask_slcr__FPGA_RST_CTRL = 32'hFFFFFFFF; parameter slcr__A9_CPU_RST_CTRL = 32'hF8000244; parameter val_slcr__A9_CPU_RST_CTRL = 32'h00000000; parameter mask_slcr__A9_CPU_RST_CTRL = 32'hFFFFFFFF; parameter slcr__RS_AWDT_CTRL = 32'hF800024C; parameter val_slcr__RS_AWDT_CTRL = 32'h00000000; parameter mask_slcr__RS_AWDT_CTRL = 32'hFFFFFFFF; parameter slcr__RST_REASON = 32'hF8000250; parameter val_slcr__RST_REASON = 32'h00000040; parameter mask_slcr__RST_REASON = 32'hFFFFFFFF; parameter slcr__RST_REASON_CLR = 32'hF8000254; parameter val_slcr__RST_REASON_CLR = 32'h00000000; parameter mask_slcr__RST_REASON_CLR = 32'hFFFFFFFF; parameter slcr__REBOOT_STATUS = 32'hF8000258; parameter val_slcr__REBOOT_STATUS = 32'h00400000; parameter mask_slcr__REBOOT_STATUS = 32'hFFFFFFFF; parameter slcr__BOOT_MODE = 32'hF800025C; parameter val_slcr__BOOT_MODE = 32'h00000000; parameter mask_slcr__BOOT_MODE = 32'hFFFFFFF0; parameter slcr__APU_CTRL = 32'hF8000300; parameter val_slcr__APU_CTRL = 32'h00000000; parameter mask_slcr__APU_CTRL = 32'hFFFFFFFF; parameter slcr__WDT_CLK_SEL = 32'hF8000304; parameter val_slcr__WDT_CLK_SEL = 32'h00000000; parameter mask_slcr__WDT_CLK_SEL = 32'hFFFFFFFF; parameter slcr__TZ_OCM_RAM0 = 32'hF8000400; parameter val_slcr__TZ_OCM_RAM0 = 32'h00000000; parameter mask_slcr__TZ_OCM_RAM0 = 32'hFFFFFFFF; parameter slcr__TZ_OCM_RAM1 = 32'hF8000404; parameter val_slcr__TZ_OCM_RAM1 = 32'h00000000; parameter mask_slcr__TZ_OCM_RAM1 = 32'hFFFFFFFF; parameter slcr__TZ_OCM_ROM = 32'hF8000408; parameter val_slcr__TZ_OCM_ROM = 32'h00000000; parameter mask_slcr__TZ_OCM_ROM = 32'hFFFFFFFF; parameter slcr__TZ_DDR_RAM = 32'hF8000430; parameter val_slcr__TZ_DDR_RAM = 32'h00000000; parameter mask_slcr__TZ_DDR_RAM = 32'h00000001; parameter slcr__TZ_DMA_NS = 32'hF8000440; parameter val_slcr__TZ_DMA_NS = 32'h00000000; parameter mask_slcr__TZ_DMA_NS = 32'hFFFFFFFF; parameter slcr__TZ_DMA_IRQ_NS = 32'hF8000444; parameter val_slcr__TZ_DMA_IRQ_NS = 32'h00000000; parameter mask_slcr__TZ_DMA_IRQ_NS = 32'hFFFFFFFF; parameter slcr__TZ_DMA_PERIPH_NS = 32'hF8000448; parameter val_slcr__TZ_DMA_PERIPH_NS = 32'h00000000; parameter mask_slcr__TZ_DMA_PERIPH_NS = 32'hFFFFFFFF; parameter slcr__TZ_GEM = 32'hF8000450; parameter val_slcr__TZ_GEM = 32'h00000000; parameter mask_slcr__TZ_GEM = 32'hFFFFFFFF; parameter slcr__TZ_SDIO = 32'hF8000454; parameter val_slcr__TZ_SDIO = 32'h00000000; parameter mask_slcr__TZ_SDIO = 32'hFFFFFFFF; parameter slcr__TZ_USB = 32'hF8000458; parameter val_slcr__TZ_USB = 32'h00000000; parameter mask_slcr__TZ_USB = 32'hFFFFFFFF; parameter slcr__TZ_FPGA_M = 32'hF8000484; parameter val_slcr__TZ_FPGA_M = 32'h00000000; parameter mask_slcr__TZ_FPGA_M = 32'hFFFFFFFF; parameter slcr__TZ_FPGA_AFI = 32'hF8000488; parameter val_slcr__TZ_FPGA_AFI = 32'h00000000; parameter mask_slcr__TZ_FPGA_AFI = 32'hFFFFFFFF; parameter slcr__DBG_CTRL = 32'hF8000500; parameter val_slcr__DBG_CTRL = 32'h00000000; parameter mask_slcr__DBG_CTRL = 32'hFFFFFFFF; parameter slcr__PSS_IDCODE = 32'hF8000530; parameter val_slcr__PSS_IDCODE = 32'h03720093; parameter mask_slcr__PSS_IDCODE = 32'h0FFE0FFF; parameter slcr__DDR_URGENT = 32'hF8000600; parameter val_slcr__DDR_URGENT = 32'h00000000; parameter mask_slcr__DDR_URGENT = 32'hFFFFFFFF; parameter slcr__DDR_CAL_START = 32'hF800060C; parameter val_slcr__DDR_CAL_START = 32'h00000000; parameter mask_slcr__DDR_CAL_START = 32'hFFFFFFFF; parameter slcr__DDR_REF_START = 32'hF8000614; parameter val_slcr__DDR_REF_START = 32'h00000000; parameter mask_slcr__DDR_REF_START = 32'hFFFFFFFF; parameter slcr__DDR_CMD_STA = 32'hF8000618; parameter val_slcr__DDR_CMD_STA = 32'h00000000; parameter mask_slcr__DDR_CMD_STA = 32'hFFFFFFFF; parameter slcr__DDR_URGENT_SEL = 32'hF800061C; parameter val_slcr__DDR_URGENT_SEL = 32'h00000000; parameter mask_slcr__DDR_URGENT_SEL = 32'hFFFFFFFF; parameter slcr__DDR_DFI_STATUS = 32'hF8000620; parameter val_slcr__DDR_DFI_STATUS = 32'h00000000; parameter mask_slcr__DDR_DFI_STATUS = 32'hFFFFFFFF; parameter slcr__MIO_PIN_00 = 32'hF8000700; parameter val_slcr__MIO_PIN_00 = 32'h00001601; parameter mask_slcr__MIO_PIN_00 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_01 = 32'hF8000704; parameter val_slcr__MIO_PIN_01 = 32'h00001601; parameter mask_slcr__MIO_PIN_01 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_02 = 32'hF8000708; parameter val_slcr__MIO_PIN_02 = 32'h00000601; parameter mask_slcr__MIO_PIN_02 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_03 = 32'hF800070C; parameter val_slcr__MIO_PIN_03 = 32'h00000601; parameter mask_slcr__MIO_PIN_03 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_04 = 32'hF8000710; parameter val_slcr__MIO_PIN_04 = 32'h00000601; parameter mask_slcr__MIO_PIN_04 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_05 = 32'hF8000714; parameter val_slcr__MIO_PIN_05 = 32'h00000601; parameter mask_slcr__MIO_PIN_05 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_06 = 32'hF8000718; parameter val_slcr__MIO_PIN_06 = 32'h00000601; parameter mask_slcr__MIO_PIN_06 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_07 = 32'hF800071C; parameter val_slcr__MIO_PIN_07 = 32'h00000601; parameter mask_slcr__MIO_PIN_07 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_08 = 32'hF8000720; parameter val_slcr__MIO_PIN_08 = 32'h00000601; parameter mask_slcr__MIO_PIN_08 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_09 = 32'hF8000724; parameter val_slcr__MIO_PIN_09 = 32'h00001601; parameter mask_slcr__MIO_PIN_09 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_10 = 32'hF8000728; parameter val_slcr__MIO_PIN_10 = 32'h00001601; parameter mask_slcr__MIO_PIN_10 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_11 = 32'hF800072C; parameter val_slcr__MIO_PIN_11 = 32'h00001601; parameter mask_slcr__MIO_PIN_11 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_12 = 32'hF8000730; parameter val_slcr__MIO_PIN_12 = 32'h00001601; parameter mask_slcr__MIO_PIN_12 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_13 = 32'hF8000734; parameter val_slcr__MIO_PIN_13 = 32'h00001601; parameter mask_slcr__MIO_PIN_13 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_14 = 32'hF8000738; parameter val_slcr__MIO_PIN_14 = 32'h00001601; parameter mask_slcr__MIO_PIN_14 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_15 = 32'hF800073C; parameter val_slcr__MIO_PIN_15 = 32'h00001601; parameter mask_slcr__MIO_PIN_15 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_16 = 32'hF8000740; parameter val_slcr__MIO_PIN_16 = 32'h00001601; parameter mask_slcr__MIO_PIN_16 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_17 = 32'hF8000744; parameter val_slcr__MIO_PIN_17 = 32'h00001601; parameter mask_slcr__MIO_PIN_17 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_18 = 32'hF8000748; parameter val_slcr__MIO_PIN_18 = 32'h00001601; parameter mask_slcr__MIO_PIN_18 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_19 = 32'hF800074C; parameter val_slcr__MIO_PIN_19 = 32'h00001601; parameter mask_slcr__MIO_PIN_19 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_20 = 32'hF8000750; parameter val_slcr__MIO_PIN_20 = 32'h00001601; parameter mask_slcr__MIO_PIN_20 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_21 = 32'hF8000754; parameter val_slcr__MIO_PIN_21 = 32'h00001601; parameter mask_slcr__MIO_PIN_21 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_22 = 32'hF8000758; parameter val_slcr__MIO_PIN_22 = 32'h00001601; parameter mask_slcr__MIO_PIN_22 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_23 = 32'hF800075C; parameter val_slcr__MIO_PIN_23 = 32'h00001601; parameter mask_slcr__MIO_PIN_23 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_24 = 32'hF8000760; parameter val_slcr__MIO_PIN_24 = 32'h00001601; parameter mask_slcr__MIO_PIN_24 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_25 = 32'hF8000764; parameter val_slcr__MIO_PIN_25 = 32'h00001601; parameter mask_slcr__MIO_PIN_25 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_26 = 32'hF8000768; parameter val_slcr__MIO_PIN_26 = 32'h00001601; parameter mask_slcr__MIO_PIN_26 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_27 = 32'hF800076C; parameter val_slcr__MIO_PIN_27 = 32'h00001601; parameter mask_slcr__MIO_PIN_27 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_28 = 32'hF8000770; parameter val_slcr__MIO_PIN_28 = 32'h00001601; parameter mask_slcr__MIO_PIN_28 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_2"b"9 = 32'hF8000774; parameter val_slcr__MIO_PIN_29 = 32'h00001601; parameter mask_slcr__MIO_PIN_29 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_30 = 32'hF8000778; parameter val_slcr__MIO_PIN_30 = 32'h00001601; parameter mask_slcr__MIO_PIN_30 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_31 = 32'hF800077C; parameter val_slcr__MIO_PIN_31 = 32'h00001601; parameter mask_slcr__MIO_PIN_31 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_32 = 32'hF8000780; parameter val_slcr__MIO_PIN_32 = 32'h00001601; parameter mask_slcr__MIO_PIN_32 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_33 = 32'hF8000784; parameter val_slcr__MIO_PIN_33 = 32'h00001601; parameter mask_slcr__MIO_PIN_33 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_34 = 32'hF8000788; parameter val_slcr__MIO_PIN_34 = 32'h00001601; parameter mask_slcr__MIO_PIN_34 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_35 = 32'hF800078C; parameter val_slcr__MIO_PIN_35 = 32'h00001601; parameter mask_slcr__MIO_PIN_35 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_36 = 32'hF8000790; parameter val_slcr__MIO_PIN_36 = 32'h00001601; parameter mask_slcr__MIO_PIN_36 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_37 = 32'hF8000794; parameter val_slcr__MIO_PIN_37 = 32'h00001601; parameter mask_slcr__MIO_PIN_37 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_38 = 32'hF8000798; parameter val_slcr__MIO_PIN_38 = 32'h00001601; parameter mask_slcr__MIO_PIN_38 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_39 = 32'hF800079C; parameter val_slcr__MIO_PIN_39 = 32'h00001601; parameter mask_slcr__MIO_PIN_39 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_40 = 32'hF80007A0; parameter val_slcr__MIO_PIN_40 = 32'h00001601; parameter mask_slcr__MIO_PIN_40 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_41 = 32'hF80007A4; parameter val_slcr__MIO_PIN_41 = 32'h00001601; parameter mask_slcr__MIO_PIN_41 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_42 = 32'hF80007A8; parameter val_slcr__MIO_PIN_42 = 32'h00001601; parameter mask_slcr__MIO_PIN_42 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_43 = 32'hF80007AC; parameter val_slcr__MIO_PIN_43 = 32'h00001601; parameter mask_slcr__MIO_PIN_43 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_44 = 32'hF80007B0; parameter val_slcr__MIO_PIN_44 = 32'h00001601; parameter mask_slcr__MIO_PIN_44 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_45 = 32'hF80007B4; parameter val_slcr__MIO_PIN_45 = 32'h00001601; parameter mask_slcr__MIO_PIN_45 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_46 = 32'hF80007B8; parameter val_slcr__MIO_PIN_46 = 32'h00001601; parameter mask_slcr__MIO_PIN_46 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_47 = 32'hF80007BC; parameter val_slcr__MIO_PIN_47 = 32'h00001601; parameter mask_slcr__MIO_PIN_47 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_48 = 32'hF80007C0; parameter val_slcr__MIO_PIN_48 = 32'h00001601; parameter mask_slcr__MIO_PIN_48 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_49 = 32'hF80007C4; parameter val_slcr__MIO_PIN_49 = 32'h00001601; parameter mask_slcr__MIO_PIN_49 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_50 = 32'hF80007C8; parameter val_slcr__MIO_PIN_50 = 32'h00001601; parameter mask_slcr__MIO_PIN_50 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_51 = 32'hF80007CC; parameter val_slcr__MIO_PIN_51 = 32'h00001601; parameter mask_slcr__MIO_PIN_51 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_52 = 32'hF80007D0; parameter val_slcr__MIO_PIN_52 = 32'h00001601; parameter mask_slcr__MIO_PIN_52 = 32'hFFFFFFFF; parameter slcr__MIO_PIN_53 = 32'hF80007D4; parameter val_slcr__MIO_PIN_53 = 32'h00001601; parameter mask_slcr__MIO_PIN_53 = 32'hFFFFFFFF; parameter slcr__MIO_FMIO_GEM_SEL = 32'hF8000800; parameter val_slcr__MIO_FMIO_GEM_SEL = 32'h00000000; parameter mask_slcr__MIO_FMIO_GEM_SEL = 32'hFFFFFFFF; parameter slcr__MIO_LOOPBACK = 32'hF8000804; parameter val_slcr__MIO_LOOPBACK = 32'h00000000; parameter mask_slcr__MIO_LOOPBACK = 32'hFFFFFFFF; parameter slcr__MIO_MST_TRI0 = 32'hF800080C; parameter val_slcr__MIO_MST_TRI0 = 32'hFFFFFFFF; parameter mask_slcr__MIO_MST_TRI0 = 32'hFFFFFFFF; parameter slcr__MIO_MST_TRI1 = 32'hF8000810; parameter val_slcr__MIO_MST_TRI1 = 32'h003FFFFF; parameter mask_slcr__MIO_MST_TRI1 = 32'hFFFFFFFF; parameter slcr__SD0_WP_CD_SEL = 32'hF8000830; parameter val_slcr__SD0_WP_CD_SEL = 32'h00000000; parameter mask_slcr__SD0_WP_CD_SEL = 32'hFFFFFFFF; parameter slcr__SD1_WP_CD_SEL = 32'hF8000834; parameter val_slcr__SD1_WP_CD_SEL = 32'h00000000; parameter mask_slcr__SD1_WP_CD_SEL = 32'hFFFFFFFF; parameter slcr__LVL_SHFTR_EN = 32'hF8000900; parameter val_slcr__LVL_SHFTR_EN = 32'h00000000; parameter mask_slcr__LVL_SHFTR_EN = 32'hFFFFFFFF; parameter slcr__OCM_CFG = 32'hF8000910; parameter val_slcr__OCM_CFG = 32'h00000000; parameter mask_slcr__OCM_CFG = 32'hFFFFFFFF; parameter slcr__CPU0_RAM0 = 32'hF8000A00; parameter val_slcr__CPU0_RAM0 = 32'h00020202; parameter mask_slcr__CPU0_RAM0 = 32'h00FFFFFF; parameter slcr__CPU0_RAM1 = 32'hF8000A04; parameter val_slcr__CPU0_RAM1 = 32'h00020202; parameter mask_slcr__CPU0_RAM1 = 32'h00FFFFFF; parameter slcr__CPU0_RAM2 = 32'hF8000A08; parameter val_slcr__CPU0_RAM2 = 32'h02020202; parameter mask_slcr__CPU0_RAM2 = 32'hFFFFFFFF; parameter slcr__CPU1_RAM0 = 32'hF8000A0C; parameter val_slcr__CPU1_RAM0 = 32'h00020202; parameter mask_slcr__CPU1_RAM0 = 32'h00FFFFFF; parameter slcr__CPU1_RAM1 = 32'hF8000A10; parameter val_slcr__CPU1_RAM1 = 32'h00020202; parameter mask_slcr__CPU1_RAM1 = 32'h00FFFFFF; parameter slcr__CPU1_RAM2 = 32'hF8000A14; parameter val_slcr__CPU1_RAM2 = 32'h02020202; parameter mask_slcr__CPU1_RAM2 = 32'hFFFFFFFF; parameter slcr__SCU_RAM = 32'hF8000A18; parameter val_slcr__SCU_RAM = 32'h00000002; parameter mask_slcr__SCU_RAM = 32'h000000FF; parameter slcr__L2C_RAM = 32'hF8000A1C; parameter val_slcr__L2C_RAM = 32'h00020202; parameter mask_slcr__L2C_RAM = 32'h00FFFFFF; parameter slcr__IOU_RAM_GEM01 = 32'hF8000A30; parameter val_slcr__IOU_RAM_GEM01 = 32'h09090909; parameter mask_slcr__IOU_RAM_GEM01 = 32'hFFFFFFFF; parameter slcr__IOU_RAM_USB01 = 32'hF8000A34; parameter val_slcr__IOU_RAM_USB01 = 32'h09090909; parameter mask_slcr__IOU_RAM_USB01 = 32'hFFFFFFFF; parameter slcr__IOU_RAM_SDIO0 = 32'hF8000A38; parameter val_slcr__IOU_RAM_SDIO0 = 32'h09090909; parameter mask_slcr__IOU_RAM_SDIO0 = 32'hFFFFFFFF; parameter slcr__IOU_RAM_SDIO1 = 32'hF8000A3C; parameter val_slcr__IOU_RAM_SDIO1 = 32'h09090909; parameter mask_slcr__IOU_RAM_SDIO1 = 32'hFFFFFFFF; parameter slcr__IOU_RAM_CAN0 = 32'hF8000A40; parameter val_slcr__IOU_RAM_CAN0 = 32'h00090909; parameter mask_slcr__IOU_RAM_CAN0 = 32'h00FFFFFF; parameter slcr__IOU_RAM_CAN1 = 32'hF8000A44; parameter val_slcr__IOU_RAM_CAN1 = 32'h00090909; parameter mask_slcr__IOU_RAM_CAN1 = 32'h00FFFFFF; parameter slcr__IOU_RAM_LQSPI = 32'hF8000A48; parameter val_slcr__IOU_RAM_LQSPI = 32'h00000909; parameter mask_slcr__IOU_RAM_LQSPI = 32'h0000FFFF; parameter slcr__DMAC_RAM = 32'hF8000A50; parameter val_slcr__DMAC_RAM = 32'h00000009; parameter mask_slcr__DMAC_RAM = 32'h000000FF; parameter slcr__AFI0_RAM0 = 32'hF8000A60; parameter val_slcr__AFI0_RAM0 = 32'h09090909; parameter mask_slcr__AFI0_RAM0 = 32'hFFFFFFFF; parameter slcr__AFI0_RAM1 = 32'hF8000A64; parameter val_slcr__AFI0_RAM1 = 32'h09090909; parameter mask_slcr__AFI0_RAM1 = 32'hFFFFFFFF; parameter slcr__AFI0_RAM2 = 32'hF8000A68; parameter val_slcr__AFI0_RAM2 = 32'h00000909; parameter mask_slcr__AFI0_RAM2 = 32'h0000FFFF; parameter slcr__AFI1_RAM0 = 32'hF8000A6C; parameter val_slcr__AFI1_RAM0 = 32'h09090909; parameter mask_slcr__AFI1_RAM0 = 32'hFFFFFFFF; parameter slcr__AFI1_RAM1 = 32'hF8000A70; parameter val_slcr__AFI1_RAM1 = 32'h09090909; parameter mask_slcr__AFI1_RAM1 = 32'hFFFFFFFF; parameter slcr__AFI1_RAM2 = 32'hF8000A74; parameter val_slcr__AFI1_RAM2 = 32'h00000909; parameter mask_slcr__AFI1_RAM2 = 32'h0000FFFF; parameter slcr__AFI2_RAM0 = 32'hF8000A78; parameter val_slcr__AFI2_RAM0 = 32'h09090909; parameter mask_slcr__AFI2_RAM0 = 32'hFFFFFFFF; parameter slcr__AFI2_RAM1 = 32'hF8000A7C; parameter val_slcr__AFI2_RAM1 = 32'h09090909; parameter mask_slcr__AFI2_RAM1 = 32'hFFFFFFFF; parameter slcr__AFI2_RAM2 = 32'hF8000A80; parameter val_slcr__AFI2_RAM2 = 32'h00000909; parameter mask_slcr__AFI2_RAM2 = 32'h0000FFFF; parameter slcr__AFI3_RAM0 = 32'hF8000A84; parameter val_slcr__AFI3_RAM0 = 32'h09090909; parameter mask_slcr__AFI3_RAM0 = 32'hFFFFFFFF; parameter slcr__AFI3_RAM1 = 32'hF8000A88; parameter val_slcr__AFI3_RAM1 = 32'h09090909; parameter mask_slcr__AFI3_RAM1 = 32'hFFFFFFFF; parameter slcr__AFI3_RAM2 = 32'hF8000A8C; parameter val_slcr__AFI3_RAM2 = 32'h00000909; parameter mask_slcr__AFI3_RAM2 = 32'h0000FFFF; parameter slcr__OCM_RAM = 32'hF8000A90; parameter val_slcr__OCM_RAM = 32'h01010101; parameter mask_slcr__OCM_RAM = 32'hFFFFFFFF; parameter slcr__OCM_ROM0 = 32'hF8000A94; parameter val_slcr__OCM_ROM0 = 32'h09090909; parameter mask_slcr__OCM_ROM0 = 32'hFFFFFFFF; parameter slcr__OCM_ROM1 = 32'hF8000A98; parameter val_slcr__OCM_ROM1 = 32'h09090909; parameter mask_slcr__OCM_ROM1 = 32'hFFFFFFFF; parameter slcr__DEVCI_RAM = 32'hF8000AA0; parameter val_slcr__DEVCI_RAM = 32'h00000909; parameter mask_slcr__DEVCI_RAM = 32'h0000FFFF; parameter slcr__CSG_RAM = 32'hF8000AB0; parameter val_slcr__CSG_RAM = 32'h00000001; parameter mask_slcr__CSG_RAM = 32'h000000FF; parameter slcr__GPIOB_CTRL = 32'hF8000B00; parameter val_slcr__GPIOB_CTRL = 32'h00000000; parameter mask_slcr__GPIOB_CTRL = 32'hFFFFFFFF; parameter slcr__GPIOB_CFG_CMOS18 = 32'hF8000B04; parameter val_slcr__GPIOB_CFG_CMOS18 = 32'h00000000; parameter mask_slcr__GPIOB_CFG_CMOS18 = 32'hFFFFFFFF; parameter slcr__GPIOB_CFG_CMOS25 = 32'hF8000B08; parameter val_slcr__GPIOB_CFG_CMOS25 = 32'h00000000; parameter mask_slcr__GPIOB_CFG_CMOS25 = 32'hFFFFFFFF; parameter slcr__GPIOB_CFG_CMOS33 = 32'hF8000B0C; parameter val_slcr__GPIOB_CFG_CMOS33 = 32'h00000000; parameter mask_slcr__GPIOB_CFG_CMOS33 = 32'hFFFFFFFF; parameter slcr__GPIOB_CFG_LVTTL = 32'hF8000B10; parameter val_slcr__GPIOB_CFG_LVTTL = 32'h00000000; parameter mask_slcr__GPIOB_CFG_LVTTL = 32'hFFFFFFFF; parameter slcr__GPIOB_CFG_HSTL = 32'hF8000B14; parameter val_slcr__GPIOB_CFG_HSTL = 32'h00000000; parameter mask_slcr__GPIOB_CFG_HSTL = 32'hFFFFFFFF; parameter slcr__GPIOB_DRVR_BIAS_CTRL = 32'hF8000B18; parameter val_slcr__GPIOB_DRVR_BIAS_CTRL = 32'h00000000; parameter mask_slcr__GPIOB_DRVR_BIAS_CTRL = 32'hFFFFFFFF; parameter slcr__DDRIOB_ADDR0 = 32'hF8000B40; parameter val_slcr__DDRIOB_ADDR0 = 32'h00000800; parameter mask_slcr__DDRIOB_ADDR0 = 32'hFFFFFFFF; parameter slcr__DDRIOB_ADDR1 = 32'hF8000B44; parameter val_slcr__DDRIOB_ADDR1 = 32'h00000800; parameter mask_slcr__DDRIOB_ADDR1 = 32'hFFFFFFFF; parameter slcr__DDRIOB_DATA0 = 32'hF8000B48; parameter val_slcr__DDRIOB_DATA0 = 32'h00000800; parameter mask_slcr__DDRIOB_DATA0 = 32'hFFFFFFFF; parameter slcr__DDRIOB_DATA1 = 32'hF8000B4C; parameter val_slcr__DDRIOB_DATA1 = 32'h00000800; parameter mask_slcr__DDRIOB_DATA1 = 32'hFFFFFFFF; parameter slcr__DDRIOB_DIFF0 = 32'hF8000B50; parameter val_slcr__DDRIOB_DIFF0 = 32'h00000800; parameter mask_slcr__DDRIOB_DIFF0 = 32'hFFFFFFFF; parameter slcr__DDRIOB_DIFF1 = 32'hF8000B54; parameter val_slcr__DDRIOB_DIFF1 = 32'h00000800; parameter mask_slcr__DDRIOB_DIFF1 = 32'hFFFFFFFF; parameter slcr__DDRIOB_CLOCK = 32'hF8000B58; parameter val_slcr__DDRIOB_CLOCK = 32'h00000800; parameter mask_slcr__DDRIOB_CLOCK = 32'hFFFFFFFF; parameter slcr__DDRIOB_DRIVE_SLEW_ADDR = 32'hF8000B5C; parameter val_slcr__DDRIOB_DRIVE_SLEW_ADDR = 32'h00000000; parameter mask_slcr__DDRIOB_DRIVE_SLEW_ADDR = 32'hFFFFFFFF; parameter slcr__DDRIOB_DRIVE_SLEW_DATA = 32'hF8000B60; parameter val_slcr__DDRIOB_DRIVE_SLEW_DATA = 32'h00000000; parameter mask_slcr__DDRIOB_DRIVE_SLEW_DATA = 32'hFFFFFFFF; parameter slcr__DDRIOB_DRIVE_SLEW_DIFF = 32'hF8000B64; parameter val_slcr__DDRIOB_DRIVE_SLEW_DIFF = 32'h00000000; parameter mask_slcr__DDRIOB_DRIVE_SLEW_DIFF = 32'hFFFFFFFF; parameter slcr__DDRIOB_DRIVE_SLEW_CLOCK = 32'hF8000B68; parameter val_slcr__DDRIOB_DRIVE_SLEW_CLOCK = 32'h00000000; parameter mask_slcr__DDRIOB_DRIVE_SLEW_CLOCK = 32'hFFFFFFFF; parameter slcr__DDRIOB_DDR_CTRL = 32'hF8000B6C; parameter val_slcr__DDRIOB_DDR_CTRL = 32'h00000000; parameter mask_slcr__DDRIOB_DDR_CTRL = 32'hFFFFFFFF; parameter slcr__DDRIOB_DCI_CTRL = 32'hF8000B70; parameter val_slcr__DDRIOB_DCI_CTRL = 32'h00000020; parameter mask_slcr__DDRIOB_DCI_CTRL = 32'hFFFFFFFF; parameter slcr__DDRIOB_DCI_STATUS = 32'hF8000B74; parameter val_slcr__DDRIOB_DCI_STATUS = 32'h00000000; parameter mask_slcr__DDRIOB_DCI_STATUS = 32'hFFFFFFFF; // ************************************************************ // Module smcc pl353 // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter smcc__memc_status = 32'hE000E000; parameter val_smcc__memc_status = 32'h00000000; parameter mask_smcc__memc_status = 32'h00001FFF; parameter smcc__memif_cfg = 32'hE000E004; parameter val_smcc__memif_cfg = 32'h00011205; parameter mask_smcc__memif_cfg = 32'h0003FFFF; parameter smcc__memc_cfg_set = 32'hE000E008; parameter val_smcc__memc_cfg_set = 32'h00000000; parameter mask_smcc__memc_cfg_set = 32'h00000000; parameter smcc__memc_cfg_clr = 32'hE000E00C; parameter val_smcc__memc_cfg_clr = 32'h00000000; parameter mask_smcc__memc_cfg_clr = 32'h00000000; parameter smcc__direct_cmd = 32'hE000E010; parameter val_smcc__direct_cmd = 32'h00000000; parameter mask_smcc__direct_cmd = 32'h00000000; parameter smcc__set_cycles = 32'hE000E014; parameter val_smcc__set_cycles = 32'h00000000; parameter mask_smcc__set_cycles = 32'h00000000; parameter smcc__set_opmode = 32'hE000E018; parameter val_smcc__set_opmode = 32'h00000000; parameter mask_smcc__set_opmode = 32'h00000000; parameter smcc__refresh_period_0 = 32'hE000E020; parameter val_smcc__refresh_period_0 = 32'h00000000; parameter mask_smcc__refresh_period_0 = 32'h0000000F; parameter smcc__refresh_period_1 = 32'hE000E024; parameter val_smcc__refresh_period_1 = 32'h00000000; parameter mask_smcc__refresh_period_1 = 32'h0000000F; parameter smcc__sram_cycles0_0 = 32'hE000E100; parameter val_smcc__sram_cycles0_0 = 32'h0002B3CC; parameter mask_smcc__sram_cycles0_0 = 32'h001FFFFF; parameter smcc__opmode0_0 = 32'hE000E104; parameter val_smcc__opmode0_0 = 32'hE2FE0800; parameter mask_smcc__opmode0_0 = 32'hFFFFFFFF; parameter smcc__sram_cycles0_1 = 32'hE000E120; parameter val_smcc__sram_cycles0_1 = 32'h0002B3CC; parameter mask_smcc__sram_cycles0_1 = 32'h001FFFFF; parameter smcc__opmode0_1 = 32'hE000E124; parameter val_smcc__opmode0_1 = 32'hE4FE0800; parameter mask_smcc__opmode0_1 = 32'hFFFFFFFF; parameter smcc__nand_cycles1_0 = 32'hE000E180; parameter val_smcc__nand_cycles1_0 = 32'h0024ABCC; parameter mask_smcc__nand_cycles1_0 = 32'h00FFFFFF; parameter smcc__opmode1_0 = 32'hE000E184; parameter val_smcc__opmode1_0 = 32'hE1FF0001; parameter mask_smcc__opmode1_0 = 32'hFFFFFFFF; parameter smcc__user_status = 32'hE000E200; parameter val_smcc__user_status = 32'h00000000; parameter mask_smcc__user_status = 32'h000000FF; parameter smcc__user_config = 32'hE000E204; parameter val_smcc__user_config = 32'h00000000; parameter mask_smcc__user_config = 32'h00000000; parameter smcc__ecc_status_0 = 32'hE000E300; parameter val_smcc__ecc_status_0 = 32'h00000000; parameter mask_smcc__ecc_status_0 = 32'h3FFFFFFF; parameter smcc__ecc_memcfg_0 = 32'hE000E304; parameter val_smcc__ecc_memcfg_0 = 32'h00000000; parameter mask_smcc__ecc_memcfg_0 = 32'h00001FFF; parameter smcc__ecc_memcommand1_0 = 32'hE000E308; parameter val_smcc__ecc_memcommand1_0 = 32'h00000000; parameter mask_smcc__ecc_memcommand1_0 = 32'h01FFFFFF; parameter smcc__ecc_memcommand2_0 = 32'hE000E30C; parameter val_smcc__ecc_memcommand2_0 = 32'h00000000; parameter mask_smcc__ecc_memcommand2_0 = 32'h01FFFFFF; parameter smcc__ecc_addr0_0 = 32'hE000E310; parameter val_smcc__ecc_addr0_0 = 32'h00000000; parameter mask_smcc__ecc_addr0_0 = 32'hFFFFFFFF; parameter smcc__ecc_addr1_0 = 32'hE000E314; parameter val_smcc__ecc_addr1_0 = 32'h00000000; parameter mask_smcc__ecc_addr1_0 = 32'h00FFFFFF; parameter smcc__ecc_value0_0 = 32'hE000E318; parameter val_smcc__ecc_value0_0 = 32'h00000000; parameter mask_smcc__ecc_value0_0 = 32'hFFFFFFFF; parameter smcc__ecc_value1_0 = 32'hE000E31C; parameter val_smcc__ecc_value1_0 = 32'h00000000; parameter mask_smcc__ecc_value1_0 = 32'hFFFFFFFF; parameter smcc__ecc_value2_0 = 32'hE000E320; parameter val_smcc__ecc_value2_0 = 32'h00000000; parameter mask_smcc__ecc_value2_0 = 32'hFFFFFFFF; parameter smcc__ecc_value3_0 = 32'hE000E324; parameter val_smcc__ecc_value3_0 = 32'h00000000; parameter mask_smcc__ecc_value3_0 = 32'hFFFFFFFF; parameter smcc__ecc_status_1 = 32'hE000E400; parameter val_smcc__ecc_status_1 = 32'h00000000; parameter mask_smcc__ecc_status_1 = 32'h3FFFFFFF; parameter smcc__ecc_memcfg_1 = 32'hE000E404; parameter val_smcc__ecc_memcfg_1 = 32'h00000043; parameter mask_smcc__ecc_memcfg_1 = 32'h00001FFF; parameter smcc__ecc_memcommand1_1 = 32'hE000E408; parameter val_smcc__ecc_memcommand1_1 = 32'h01300080; parameter mask_smcc__ecc_memcommand1_1 = 32'h01FFFFFF; parameter smcc__ecc_memcommand2_1 = 32'hE000E40C; parameter val_smcc__ecc_memcommand2_1 = 32'h01E00585; parameter mask_smcc__ecc_memcommand2_1 = 32'h01FFFFFF; parameter smcc__ecc_addr0_1 = 32'hE000E410; parameter val_smcc__ecc_addr0_1 = 32'h00000000; parameter mask_smcc__ecc_addr0_1 = 32'hFFFFFFFF; parameter smcc__ecc_addr1_1 = 32'hE000E414; parameter val_smcc__ecc_addr1_1 = 32'h00000000; parameter mask_smcc__ecc_addr1_1 = 32'h00FFFFFF; parameter smcc__ecc_value0_1 = 32'hE000E418; parameter val_smcc__ecc_value0_1 = 32'h00000000; parameter mask_smcc__ecc_value0_1 = 32'hFFFFFFFF; parameter smcc__ecc_value1_1 = 32'hE000E41C; parameter val_smcc__ecc_value1_1 = 32'h00000000; parameter mask_smcc__ecc_value1_1 = 32'hFFFFFFFF; parameter smcc__ecc_value2_1 = 32'hE000E420; parameter val_smcc__ecc_value2_1 = 32'h00000000; parameter mask_smcc__ecc_value2_1 = 32'hFFFFFFFF; parameter smcc__ecc_value3_1 = 32'hE000E424; parameter val_smcc__ecc_value3_1 = 32'h00000000; parameter mask_smcc__ecc_value3_1 = 32'hFFFFFFFF; parameter smcc__integration_test = 32'hE000EE00; parameter val_smcc__integration_test = 32'h00000000; parameter mask_smcc__integration_test = 32'hFFFFFFFF; parameter smcc__periph_id_0 = 32'hE000EFE0; parameter val_smcc__periph_id_0 = 32'h00000053; parameter mask_smcc__periph_id_0 = 32'h000000FF; parameter smcc__periph_id_1 = 32'hE000EFE4; parameter val_smcc__periph_id_1 = 32'h00000013; parameter mask_smcc__periph_id_1 = 32'h000000FF; parameter smcc__periph_id_2 = 32'hE000EFE8; parameter val_smcc__periph_id_2 = 32'h00000054; parameter mask_smcc__periph_id_2 = 32'h000000FF; parameter smcc__periph_id_3 = 32'hE000EFEC; parameter val_smcc__periph_id_3 = 32'h00000000; parameter mask_smcc__periph_id_3 = 32'h00000001; parameter smcc__pcell_id_0 = 32'hE000EFF0; parameter val_smcc__pcell_id_0 = 32'h0000000D; parameter mask_smcc__pcell_id_0 = 32'h000000FF; parameter smcc__pcell_id_1 = 32'hE000EFF4; parameter val_smcc__pcell_id_1 = 32'h000000F0; parameter mask_smcc__pcell_id_1 = 32'h000000FF; parameter smcc__pcell_id_2 = 32'hE000EFF8; parameter val_smcc__pcell_id_2 = 32'h00000005; parameter mask_smcc__pcell_id_2 = 32'h000000FF; parameter smcc__pcell_id_3 = 32'hE000EFFC; parameter val_smcc__pcell_id_3 = 32'h000000B1; parameter mask_smcc__pcell_id_3 = 32'h000000FF; // ************************************************************ // Module spi0 SPI // doc version: 1.2 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter spi0__Config_reg0 = 32'hE0006000; parameter val_spi0__Config_reg0 = 32'h00020000; parameter mask_spi0__Config_reg0 = 32'hFFFFFFFF; parameter spi0__Intr_status_reg0 = 32'hE0006004; parameter val_spi0__Intr_status_reg0 = 32'h00000004; parameter mask_spi0__Intr_status_reg0 = 32'hFFFFFFFF; parameter spi0__Intrpt_en_reg0 = 32'hE0006008; parameter val_spi0__Intrpt_en_reg0 = 32'h00000000; parameter mask_spi0__Intrpt_en_reg0 = 32'hFFFFFFFF; parameter spi0__Intrpt_dis_reg0 = 32'hE000600C; parameter val_spi0__Intrpt_dis_reg0 = 32'h00000000; parameter mask_spi0__Intrpt_dis_reg0 = 32'hFFFFFFFF; parameter spi0__Intrpt_mask_reg0 = 32'hE0006010; parameter val_spi0__Intrpt_mask_reg0 = 32'h00000000; parameter mask_spi0__Intrpt_mask_reg0 = 32'hFFFFFFFF; parameter spi0__En_reg0 = 32'hE0006014; parameter val_spi0__En_reg0 = 32'h00000000; parameter mask_spi0__En_reg0 = 32'hFFFFFFFF; parameter spi0__Delay_reg0 = 32'hE0006018; parameter val_spi0__Delay_reg0 = 32'h00000000; parameter mask_spi0__Delay_reg0 = 32'hFFFFFFFF; parameter spi0__Tx_data_reg0 = 32'hE000601C; parameter val_spi0__Tx_data_reg0 = 32'h00000000; parameter mask_spi0__Tx_data_reg0 = 32'hFFFFFFFF; parameter spi0__Rx_data_reg0 = 32'hE0006020; parameter val_spi0__Rx_data_reg0 = 32'h00000000; parameter mask_spi0__Rx_data_reg0 = 32'hFFFFFFFF; parameter spi0__Slave_Idle_count_reg0 = 32'hE0006024; parameter val_spi0__Slave_Idle_count_reg0 = 32'h000000FF; parameter mask_spi0__Slave_Idle_count_reg0 = 32'hFFFFFFFF; parameter spi0__TX_thres_reg0 = 32'hE0006028; parameter val_spi0__TX_thres_reg0 = 32'h00000001; parameter mask_spi0__TX_thres_reg0 = 32'hFFFFFFFF; parameter spi0__RX_thres_reg0 = 32'hE000602C; parameter val_spi0__RX_thres_reg0 = 32'h00000001; parameter mask_spi0__RX_thres_reg0 = 32'hFFFFFFFF; parameter spi0__Mod_id_reg0 = 32'hE00060FC; parameter val_spi0__Mod_id_reg0 = 32'h00090106; parameter mask_spi0__Mod_id_reg0 = 32'hFFFFFFFF; // ************************************************************ // Module spi1 SPI // doc version: 1.2 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter spi1__Config_reg0 = 32'hE0007000; parameter val_spi1__Config_reg0 = 32'h00020000; parameter mask_spi1__Config_reg0 = 32'hFFFFFFFF; parameter spi1__Intr_status_reg0 = 32'hE0007004; parameter val_spi1__Intr_status_reg0 = 32'h00000004; parameter mask_spi1__Intr_status_reg0 = 32'hFFFFFFFF; parameter spi1__Intrpt_en_reg0 = 32'hE0007008; parameter val_spi1__Intrpt_en_reg0 = 32'h00000000; parameter mask_spi1__Intrpt_en_reg0 = 32'hFFFFFFFF; parameter spi1__Intrpt_dis_reg0 = 32'hE000700C; parameter val_spi1__Intrpt_dis_reg0 = 32'h00000000; parameter mask_spi1__Intrpt_dis_reg0 = 32'hFFFFFFFF; parameter spi1__Intrpt_mask_reg0 = 32'hE0007010; parameter val_spi1__Intrpt_mask_reg0 = 32'h00000000; parameter mask_spi1__Intrpt_mask_reg0 = 32'hFFFFFFFF; parameter spi1__En_reg0 = 32'hE0007014; parameter val_spi1__En_reg0 = 32'h00000000; parameter mask_spi1__En_reg0 = 32'hFFFFFFFF; parameter spi1__Delay_reg0 = 32'hE0007018; parameter val_spi1__Delay_reg0 = 32'h00000000; parameter mask_spi1__Delay_reg0 = 32'hFFFFFFFF; parameter spi1__Tx_data_reg0 = 32'hE000701C; parameter val_spi1__Tx_data_reg0 = 32'h00000000; parameter mask_spi1__Tx_data_reg0 = 32'hFFFFFFFF; parameter spi1__Rx_data_reg0 = 32'hE0007020; parameter val_spi1__Rx_data_reg0 = 32'h00000000; parameter mask_spi1__Rx_data_reg0 = 32'hFFFFFFFF; parameter spi1__Slave_Idle_count_reg0 = 32'hE0007024; parameter val_spi1__Slave_Idle_count_reg0 = 32'h000000FF; parameter mask_spi1__Slave_Idle_count_reg0 = 32'hFFFFFFFF; parameter spi1__TX_thres_reg0 = 32'hE0007028; parameter val_spi1__TX_thres_reg0 = 32'h00000001; parameter mask_spi1__TX_thres_reg0 = 32'hFFFFFFFF; parameter spi1__RX_thres_reg0 = 32'hE000702C; parameter val_spi1__RX_thres_reg0 = 32'h00000001; parameter mask_spi1__RX_thres_reg0 = 32'hFFFFFFFF; parameter spi1__Mod_id_reg0 = 32'hE00070FC; parameter val_spi1__Mod_id_reg0 = 32'h00090106; parameter mask_spi1__Mod_id_reg0 = 32'hFFFFFFFF; // ************************************************************ // Module swdt swdt // doc version: 2.1 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter swdt__MODE = 32'hF8005000; parameter val_swdt__MODE = 32'h000001C2; parameter mask_swdt__MODE = 32'h00FFFFFF; parameter swdt__CONTROL = 32'hF8005004; parameter val_swdt__CONTROL = 32'h03FFC3FC; parameter mask_swdt__CONTROL = 32'h03FFFFFF; parameter swdt__RESTART = 32'hF8005008; parameter val_swdt__RESTART = 32'h00000000; parameter mask_swdt__RESTART = 32'h0000FFFF; parameter swdt__STATUS = 32'hF800500C; parameter val_swdt__STATUS = 32'h00000000; parameter mask_swdt__STATUS = 32'h00000001; // ************************************************************ // Module ttc0 ttc // doc version: 2.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter ttc0__Clock_Control_1 = 32'hF8001000; parameter val_ttc0__Clock_Control_1 = 32'h00000000; parameter mask_ttc0__Clock_Control_1 = 32'h0000007F; parameter ttc0__Clock_Control_2 = 32'hF8001004; parameter val_ttc0__Clock_Control_2 = 32'h00000000; parameter mask_ttc0__Clock_Control_2 = 32'h0000007F; parameter ttc0__Clock_Control_3 = 32'hF8001008; parameter val_ttc0__Clock_Control_3 = 32'h00000000; parameter mask_ttc0__Clock_Control_3 = 32'h0000007F; parameter ttc0__Counter_Control_1 = 32'hF800100C; parameter val_ttc0__Counter_Control_1 = 32'h00000021; parameter mask_ttc0__Counter_Control_1 = 32'h0000007F; parameter ttc0__Counter_Control_2 = 32'hF8001010; parameter val_ttc0__Counter_Control_2 = 32'h00000021; parameter mask_ttc0__Counter_Control_2 = 32'h0000007F; parameter ttc0__Counter_Control_3 = 32'hF8001014; parameter val_ttc0__Counter_Control_3 = 32'h00000021; parameter mask_ttc0__Counter_Control_3 = 32'h0000007F; parameter ttc0__Counter_Value_1 = 32'hF8001018; parameter val_ttc0__Counter_Value_1 = 32'h00000000; parameter mask_ttc0__Counter_Value_1 = 32'h0000FFFF; parameter ttc0__Counter_Value_2 = 32'hF800101C; parameter val_ttc0__Counter_Value_2 = 32'h00000000; parameter mask_ttc0__Counter_Value_2 = 32'h0000FFFF; parameter ttc0__Counter_Value_3 = 32'hF8001020; parameter val_ttc0__Counter_Value_3 = 32'h00000000; parameter mask_ttc0__Counter_Value_3 = 32'h0000FFFF; parameter ttc0__Interval_Counter_1 = 32'hF8001024; parameter val_ttc0__Interval_Counter_1 = 32'h00000000; parameter mask_ttc0__Interval_Counter_1 = 32'h0000FFFF; parameter ttc0__Interval_Counter_2 = 32'hF8001028; parameter val_ttc0__Interval_Counter_2 = 32'h00000000; parameter mask_ttc0__Interval_Counter_2 = 32'h0000FFFF; parameter ttc0__Interval_Counter_3 = 32'hF800102C; parameter val_ttc0__Interval_Counter_3 = 32'h00000000; parameter mask_ttc0__Interval_Counter_3 = 32'h0000FFFF; parameter ttc0__Match_1_Counter_1 = 32'hF8001030; parameter val_ttc0__Match_1_Counter_1 = 32'h00000000; parameter mask_ttc0__Match_1_Counter_1 = 32'h0000FFFF; parameter ttc0__Match_1_Counter_2 = 32'hF8001034; parameter val_ttc0__Match_1_Counter_2 = 32'h00000000; parameter mask_ttc0__Match_1_Counter_2 = 32'h0000FFFF; parameter ttc0__Match_1_Counter_3 = 32'hF8001038; parameter val_ttc0__Match_1_Counter_3 = 32'h00000000; parameter mask_ttc0__Match_1_Counter_3 = 32'h0000FFFF; parameter ttc0__Match_2_Counter_1 = 32'hF800103C; parameter val_ttc0__Match_2_Counter_1 = 32'h00000000; parameter mask_ttc0__Match_2_Counter_1 = 32'h0000FFFF; parameter ttc0__Match_2_Counter_2 = 32'hF8001040; parameter val_ttc0__Match_2_Counter_2 = 32'h00000000; parameter mask_ttc0__Match_2_Counter_2 = 32'h0000FFFF; parameter ttc0__Match_2_Counter_3 = 32'hF8001044; parameter val_ttc0__Match_2_Counter_3 = 32'h00000000; parameter mask_ttc0__Match_2_Counter_3 = 32'h0000FFFF; parameter ttc0__Match_3_Counter_1 = 32'hF8001048; parameter val_ttc0__Match_3_Counter_1 = 32'h00000000; parameter mask_ttc0__Match_3_Counter_1 = 32'h0000FFFF; parameter ttc0__Match_3_Counter_2 = 32'hF800104C; parameter val_ttc0__Match_3_Counter_2 = 32'h00000000; parameter mask_ttc0__Match_3_Counter_2 = 32'h0000FFFF; parameter ttc0__Match_3_Counter_3 = 32'hF8001050; parameter val_ttc0__Match_3_Counter_3 = 32'h00000000; parameter mask_ttc0__Match_3_Counter_3 = 32'h0000FFFF; parameter ttc0__Interrupt_Register_1 = 32'hF8001054; parameter val_ttc0__Interrupt_Register_1 = 32'h00000000; parameter mask_ttc0__Interrupt_Register_1 = 32'h0000003F; parameter ttc0__Interrupt_Register_2 = 32'hF8001058; parameter val_ttc0__Interrupt_Register_2 = 32'h00000000; parameter mask_ttc0__Interrupt_Register_2 = 32'h0000003F; parameter ttc0__Interrupt_Register_3 = 32'hF800105C; parameter val_ttc0__Interrupt_Register_3 = 32'h00000000; parameter mask_ttc0__Interrupt_Register_3 = 32'h0000003F; parameter ttc0__Interrupt_Enable_1 = 32'hF8001060; parameter val_ttc0__Interrupt_Enable_1 = 32'h00000000; parameter mask_ttc0__Interrupt_Enable_1 = 32'h0000003F; parameter ttc0__Interrupt_Enable_2 = 32'hF8001064; parameter val_ttc0__Interrupt_Enable_2 = 32'h00000000; parameter mask_ttc0__Interrupt_Enable_2 = 32'h0000003F; parameter ttc0__Interrupt_Enable_3 = 32'hF8001068; parameter val_ttc0__Interrupt_Enable_3 = 32'h00000000; parameter mask_ttc0__Interrupt_Enable_3 = 32'h0000003F; parameter ttc0__Event_Control_Timer_1 = 32'hF800106C; parameter val_ttc0__Event_Control_Timer_1 = 32'h00000000; parameter mask_ttc0__Event_Control_Timer_1 = 32'h00000007; parameter ttc0__Event_Control_Timer_2 = 32'hF8001070; parameter val_ttc0__Event_Control_Timer_2 = 32'h00000000; parameter mask_ttc0__Event_Control_Timer_2 = 32'h00000007; parameter ttc0__Event_Control_Timer_3 = 32'hF8001074; parameter val_ttc0__Event_Control_Timer_3 = 32'h00000000; parameter mask_ttc0__Event_Control_Timer_3 = 32'h00000007; parameter ttc0__Event_Register_1 = 32'hF8001078; parameter val_ttc0__Event_Register_1 = 32'h00000000; parameter mask_ttc0__Event_Register_1 = 32'h0000FFFF; parameter ttc0__Event_Register_2 = 32'hF800107C; parameter val_ttc0__Event_Register_2 = 32'h00000000; parameter mask_ttc0__Event_Register_2 = 32'h0000FFFF; parameter ttc0__Event_Register_3 = 32'hF8001080; parameter val_ttc0__Event_Register_3 = 32'h00000000; parameter mask_ttc0__Event_Register_3 = 32'h0000FFFF; // ************************************************************ // Module ttc1 ttc // doc version: 2.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter ttc1__Clock_Control_1 = 32'hF8002000; parameter val_ttc1__Clock_Control_1 = 32'h00000000; parameter mask_ttc1__Clock_Control_1 = 32'h0000007F; parameter ttc1__Clock_Control_2 = 32'hF8002004; parameter val_ttc1__Clock_Control_2 = 32'h00000000; parameter mask_ttc1__Clock_Control_2 = 32'h0000007F; parameter ttc1__Clock_Control_3 = 32'hF8002008; parameter val_ttc1__Clock_Control_3 = 32'h00000000; parameter mask_ttc1__Clock_Control_3 = 32'h0000007F; parameter ttc1__Counter_Control_1 = 32'hF800200C; parameter val_ttc1__Counter_Control_1 = 32'h00000021; parameter mask_ttc1__Counter_Control_1 = 32'h0000007F; parameter ttc1__Counter_Control_2 = 32'hF8002010; parameter val_ttc1__Counter_Control_2 = 32'h00000021; parameter mask_ttc1__Counter_Control_2 = 32'h0000007F; parameter ttc1__Counter_Control_3 = 32'hF8002014; parameter val_ttc1__Counter_Control_3 = 32'h00000021; parameter mask_ttc1__Counter_Control_3 = 32'h0000007F; parameter ttc1__Counter_Value_1 = 32'hF8002018; parameter val_ttc1__Counter_Value_1 = 32'h00000000; parameter mask_ttc1__Counter_Value_1 = 32'h0000FFFF; parameter ttc1__Counter_Value_2 = 32'hF800201C; parameter val_ttc1__Counter_Value_2 = 32'h00000000; parameter mask_ttc1__Counter_Value_2 = 32'h0000FFFF; parameter ttc1__Counter_Value_3 = 32'hF8002020; parameter val_ttc1__Counter_Value_3 = 32'h00000000; parameter mask_ttc1__Counter_Value_3 = 32'h0000FFFF; parameter ttc1__Interval_Counter_1 = 32'hF8002024; parameter val_ttc1__Interval_Counter_1 = 32'h00000000; parameter mask_ttc1__Interval_Counter_1 = 32'h0000FFFF; parameter ttc1__Interval_Counter_2 = 32'hF8002028; parameter val_ttc1__Interval_Counter_2 = 32'h00000000; parameter mask_ttc1__Interval_Counter_2 = 32'h0000FFFF; parameter ttc1__Interval_Counter_3 = 32'hF800202C; parameter val_ttc1__Interval_Counter_3 = 32'h00000000; parameter mask_ttc1__Interval_Counter_3 = 32'h0000FFFF; parameter ttc1__Match_1_Counter_1 = 32'hF8002030; parameter val_ttc1__Match_1_Counter_1 = 32'h00000000; parameter mask_ttc1__Match_1_Counter_1 = 32'h0000FFFF; parameter ttc1__Match_1_Counter_2 = 32'hF8002034; parameter val_ttc1__Match_1_Counter_2 = 32'h00000000; parameter mask_ttc1__Match_1_Counter_2 = 32'h0000FFFF; parameter ttc1__Match_1_Counter_3 = 32'hF8002038; parameter val_ttc1__Match_1_Counter_3 = 32'h00000000; parameter mask_ttc1__Match_1_Counter_3 = 32'h0000FFFF; parameter ttc1__Match_2_Counter_1 = 32'hF800203C; parameter val_ttc1__Match_2_Counter_1 = 32'h00000000; parameter mask_ttc1__Match_2_Counter_1 = 32'h0000FFFF; parameter ttc1__Match_2_Counter_2 = 32'hF8002040; parameter val_ttc1__Match_2_Counter_2 = 32'h00000000; parameter mask_ttc1__Match_2_Counter_2 = 32'h0000FFFF; parameter ttc1__Match_2_Counter_3 = 32'hF8002044; parameter val_ttc1__Match_2_Counter_3 = 32'h00000000; parameter mask_ttc1__Match_2_Counter_3 = 32'h0000FFFF; parameter ttc1__Match_3_Counter_1 = 32'hF8002048; parameter val_ttc1__Match_3_Counter_1 = 32'h00000000; parameter mask_ttc1__Match_3_Counter_1 = 32'h0000FFFF; parameter ttc1__Match_3_Counter_2 = 32'hF800204C; parameter val_ttc1__Match_3_Counter_2 = 32'h00000000; parameter mask_ttc1__Match_3_Counter_2 = 32'h0000FFFF; parameter ttc1__Match_3_Counter_3 = 32'hF8002050; parameter val_ttc1__Match_3_Counter_3 = 32'h00000000; parameter mask_ttc1__Match_3_Counter_3 = 32'h0000FFFF; parameter ttc1__Interrupt_Register_1 = 32'hF8002054; parameter val_ttc1__Interrupt_Register_1 = 32'h00000000; parameter mask_ttc1__Interrupt_Register_1 = 32'h0000003F; parameter ttc1__Interrupt_Register_2 = 32'hF8002058; parameter val_ttc1__Interrupt_Register_2 = 32'h00000000; parameter mask_ttc1__Interrupt_Register_2 = 32'h0000003F; parameter ttc1__Interrupt_Register_3 = 32'hF800205C; parameter val_ttc1__Interrupt_Register_3 = 32'h00000000; parameter mask_ttc1__Interrupt_Register_3 = 32'h0000003F; parameter ttc1__Interrupt_Enable_1 = 32'hF8002060; parameter val_ttc1__Interrupt_Enable_1 = 32'h00000000; parameter mask_ttc1__Interrupt_Enable_1 = 32'h0000003F; parameter ttc1__Interrupt_Enable_2 = 32'hF8002064; parameter val_ttc1__Interrupt_Enable_2 = 32'h00000000; parameter mask_ttc1__Interrupt_Enable_2 = 32'h0000003F; parameter ttc1__Interrupt_Enable_3 = 32'hF8002068; parameter val_ttc1__Interrupt_Enable_3 = 32'h00000000; parameter mask_ttc1__Interrupt_Enable_3 = 32'h0000003F; parameter ttc1__Event_Control_Timer_1 = 32'hF800206C; parameter val_ttc1__Event_Control_Timer_1 = 32'h00000000; parameter mask_ttc1__Event_Control_Timer_1 = 32'h00000007; parameter ttc1__Event_Control_Timer_2 = 32'hF8002070; parameter val_ttc1__Event_Control_Timer_2 = 32'h00000000; parameter mask_ttc1__Event_Control_Timer_2 = 32'h00000007; parameter ttc1__Event_Control_Timer_3 = 32'hF8002074; parameter val_ttc1__Event_Control_Timer_3 = 32'h00000000; parameter mask_ttc1__Event_Control_Timer_3 = 32'h00000007; parameter ttc1__Event_Register_1 = 32'hF8002078; parameter val_ttc1__Event_Register_1 = 32'h00000000; parameter mask_ttc1__Event_Register_1 = 32'h0000FFFF; parameter ttc1__Event_Register_2 = 32'hF800207C; parameter val_ttc1__Event_Register_2 = 32'h00000000; parameter mask_ttc1__Event_Register_2 = 32'h0000FFFF; parameter ttc1__Event_Register_3 = 32'hF8002080; parameter val_ttc1__Event_Register_3 = 32'h00000000; parameter mask_ttc1__Event_Register_3 = 32'h0000FFFF; // ************************************************************ // Module uart0 UART // doc version: 1.2 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter uart0__Control_reg0 = 32'hE0000000; parameter val_uart0__Control_reg0 = 32'h00000128; parameter mask_uart0__Control_reg0 = 32'hFFFFFFFF; parameter uart0__mode_reg0 = 32'hE0000004; parameter val_uart0__mode_reg0 = 32'h00000000; parameter mask_uart0__mode_reg0 = 32'hFFFFFFFF; parameter uart0__Intrpt_en_reg0 = 32'hE0000008; parameter val_uart0__Intrpt_en_reg0 = 32'h00000000; parameter mask_uart0__Intrpt_en_reg0 = 32'hFFFFFFFF; parameter uart0__Intrpt_dis_reg0 = 32'hE000000C; parameter val_uart0__Intrpt_dis_reg0 = 32'h00000000; parameter mask_uart0__Intrpt_dis_reg0 = 32'hFFFFFFFF; parameter uart0__Intrpt_mask_reg0 = 32'hE0000010; parameter val_uart0__Intrpt_mask_reg0 = 32'h00000000; parameter mask_uart0__Intrpt_mask_reg0 = 32'hFFFFFFFF; parameter uart0__Chnl_int_sts_reg0 = 32'hE0000014; parameter val_uart0__Chnl_int_sts_reg0 = 32'h00000200; parameter mask_uart0__Chnl_int_sts_reg0 = 32'hFFFFFFFF; parameter uart0__Baud_rate_gen_reg0 = 32'hE0000018; parameter val_uart0__Baud_rate_gen_reg0 = 32'h0000028B; parameter mask_uart0__Baud_rate_gen_reg0 = 32'hFFFFFFFF; parameter uart0__Rcvr_timeout_reg0 = 32'hE000001C; parameter val_uart0__Rcvr_timeout_reg0 = 32'h00000000; parameter mask_uart0__Rcvr_timeout_reg0 = 32'hFFFFFFFF; parameter uart0__Rcvr_FIFO_trigger_level0 = 32'hE0000020; parameter val_uart0__Rcvr_FIFO_trigger_level0 = 32'h00000020; parameter mask_uart0__Rcvr_FIFO_trigger_level0 = 32'hFFFFFFFF; parameter uart0__Modem_ctrl_reg0 = 32'hE0000024; parameter val_uart0__Modem_ctrl_reg0 = 32'h00000000; parameter mask_uart0__Modem_ctrl_reg0 = 32'hFFFFFFFF; parameter uart0__Modem_sts_reg0 = 32'hE0000028; parameter val_uart0__Modem_sts_reg0 = 32'h00000000; parameter mask_uart0__Modem_sts_reg0 = 32'h00000000; parameter uart0__Channel_sts_reg0 = 32'hE000002C; parameter val_uart0__Channel_sts_reg0 = 32'h00000000; parameter mask_uart0__Channel_sts_reg0 = 32'hFFFFFFFF; parameter uart0__TX_RX_FIFO0 = 32'hE0000030; parameter val_uart0__TX_RX_FIFO0 = 32'h00000000; parameter mask_uart0__TX_RX_FIFO0 = 32'hFFFFFFFF; parameter uart0__Baud_rate_divider_reg0 = 32'hE0000034; parameter val_uart0__Baud_rate_divider_reg0 = 32'h0000000F; parameter mask_uart0__Baud_rate_divider_reg0 = 32'hFFFFFFFF; parameter uart0__Flow_delay_reg0 = 32'hE0000038; parameter val_uart0__Flow_delay_reg0 = 32'h00000000; parameter mask_uart0__Flow_delay_reg0 = 32'hFFFFFFFF; parameter uart0__IR_min_rcv_pulse_wdth0 = 32'hE000003C; parameter val_uart0__IR_min_rcv_pulse_wdth0 = 32'h00000000; parameter mask_uart0__IR_min_rcv_pulse_wdth0 = 32'hFFFFFFFF; parameter uart0__IR_transmitted_pulse_wdth0 = 32'hE0000040; parameter val_uart0__IR_transmitted_pulse_wdth0 = 32'h00000000; parameter mask_uart0__IR_transmitted_pulse_wdth0 = 32'hFFFF00FF; parameter uart0__Tx_FIFO_trigger_level0 = 32'hE0000044; parameter val_uart0__Tx_FIFO_trigger_level0 = 32'h00000020; parameter mask_uart0__Tx_FIFO_trigger_level0 = 32'hFFFFFFFF; // ************************************************************ // Module uart1 UART // doc version: 1.2 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter uart1__Control_reg0 = 32'hE0001000; parameter val_uart1__Control_reg0 = 32'h00000128; parameter mask_uart1__Control_reg0 = 32'hFFFFFFFF; parameter uart1__mode_reg0 = 32'hE0001004; parameter val_uart1__mode_reg0 = 32'h00000000; parameter mask_uart1__mode_reg0 = 32'hFFFFFFFF; parameter uart1__Intrpt_en_reg0 = 32'hE0001008; parameter val_uart1__Intrpt_en_reg0 = 32'h00000000; parameter mask_uart1__Intrpt_en_reg0 = 32'hFFFFFFFF; parameter uart1__Intrpt_dis_reg0 = 32'hE000100C; parameter val_uart1__Intrpt_dis_reg0 = 32'h00000000; parameter mask_uart1__Intrpt_dis_reg0 = 32'hFFFFFFFF; parameter uart1__Intrpt_mask_reg0 = 32'hE0001010; parameter val_uart1__Intrpt_mask_reg0 = 32'h00000000; parameter mask_uart1__Intrpt_mask_reg0 = 32'hFFFFFFFF; parameter uart1__Chnl_int_sts_reg0 = 32'hE0001014; parameter val_uart1__Chnl_int_sts_reg0 = 32'h00000200; parameter mask_uart1__Chnl_int_sts_reg0 = 32'hFFFFFFFF; parameter uart1__Baud_rate_gen_reg0 = 32'hE0001018; parameter val_uart1__Baud_rate_gen_reg0 = 32'h0000028B; parameter mask_uart1__Baud_rate_gen_reg0 = 32'hFFFFFFFF; parameter uart1__Rcvr_timeout_reg0 = 32'hE000101C; parameter val_uart1__Rcvr_timeout_reg0 = 32'h00000000; parameter mask_uart1__Rcvr_timeout_reg0 = 32'hFFFFFFFF; parameter uart1__Rcvr_FIFO_trigger_level0 = 32'hE0001020; parameter val_uart1__Rcvr_FIFO_trigger_level0 = 32'h00000020; parameter mask_uart1__Rcvr_FIFO_trigger_level0 = 32'hFFFFFFFF; parameter uart1__Modem_ctrl_reg0 = 32'hE0001024; parameter val_uart1__Modem_ctrl_reg0 = 32'h00000000; parameter mask_uart1__Modem_ctrl_reg0 = 32'hFFFFFFFF; parameter uart1__Modem_sts_reg0 = 32'hE0001028; parameter val_uart1__Modem_sts_reg0 = 32'h00000000; parameter mask_uart1__Modem_sts_reg0 = 32'h00000000; parameter uart1__Channel_sts_reg0 = 32'hE000102C; parameter val_uart1__Channel_sts_reg0 = 32'h00000000; parameter mask_uart1__Channel_sts_reg0 = 32'hFFFFFFFF; parameter uart1__TX_RX_FIFO0 = 32'hE0001030; parameter val_uart1__TX_RX_FIFO0 = 32'h00000000; parameter mask_uart1__TX_RX_FIFO0 = 32'hFFFFFFFF; parameter uart1__Baud_rate_divider_reg0 = 32'hE0001034; parameter val_uart1__Baud_rate_divider_reg0 = 32'h0000000F; parameter mask_uart1__Baud_rate_divider_reg0 = 32'hFFFFFFFF; parameter uart1__Flow_delay_reg0 = 32'hE0001038; parameter val_uart1__Flow_delay_reg0 = 32'h00000000; parameter mask_uart1__Flow_delay_reg0 = 32'hFFFFFFFF; parameter uart1__IR_min_rcv_pulse_wdth0 = 32'hE000103C; parameter val_uart1__IR_min_rcv_pulse_wdth0 = 32'h00000000; parameter mask_uart1__IR_min_rcv_pulse_wdth0 = 32'hFFFFFFFF; parameter uart1__IR_transmitted_pulse_wdth0 = 32'hE0001040; parameter val_uart1__IR_transmitted_pulse_wdth0 = 32'h00000000; parameter mask_uart1__IR_transmitted_pulse_wdth0 = 32'hFFFF00FF; parameter uart1__Tx_FIFO_trigger_level0 = 32'hE0001044; parameter val_uart1__Tx_FIFO_trigger_level0 = 32'h00000020; parameter mask_uart1__Tx_FIFO_trigger_level0 = 32'hFFFFFFFF; // ************************************************************ // Module usb0 usb // doc version: 1.3 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter usb0__ID = 32'hE0002000; parameter val_usb0__ID = 32'hE441FA05; parameter mask_usb0__ID = 32'hFFFFFFFF; parameter usb0__HWGENERAL = 32'hE0002004; parameter val_usb0__HWGENERAL = 32'h00000083; parameter mask_usb0__HWGENERAL = 32'h00000FFF; parameter usb0__HWHOST = 32'hE0002008; parameter val_usb0__HWHOST = 32'h10020001; parameter mask_usb0__HWHOST = 32'hFFFFFFFF; parameter usb0__HWDEVICE = 32'hE000200C; parameter val_usb0__HWDEVICE = 32'h00000019; parameter mask_usb0__HWDEVICE = 32'h0000003F; parameter usb0__HWTXBUF = 32'hE0002010; parameter val_usb0__HWTXBUF = 32'h80060A10; parameter mask_usb0__HWTXBUF = 32'hFFFFFFFF; parameter usb0__HWRXBUF = 32'hE0002014; parameter val_usb0__HWRXBUF = 32'h00000A10; parameter mask_usb0__HWRXBUF = 32'hFF00FFFF; parameter usb0__GPTIMER0LD = 32'hE0002080; parameter val_usb0__GPTIMER0LD = 32'h00000000; parameter mask_usb0__GPTIMER0LD = 32'h00FFFFFF; parameter usb0__GPTIMER0CTRL = 32'hE0002084; parameter val_usb0__GPTIMER0CTRL = 32'h00000000; parameter mask_usb0__GPTIMER0CTRL = 32'hFFFFFFFF; parameter usb0__GPTIMER1LD = 32'hE0002088; parameter val_usb0__GPTIMER1LD = 32'h00000000; parameter mask_usb0__GPTIMER1LD = 32'h00FFFFFF; parameter usb0__GPTIMER1CTRL = 32'hE000208C; parameter val_usb0__GPTIMER1CTRL = 32'h00000000; parameter mask_usb0__GPTIMER1CTRL = 32'hFFFFFFFF; parameter usb0__SBUSCFG = 32'hE0002090; parameter val_usb0__SBUSCFG = 32'h00000003; parameter mask_usb0__SBUSCFG = 32'h00000007; parameter usb0__CAPLENGTH_HCIVERSION = 32'hE0002100; parameter val_usb0__CAPLENGTH_HCIVERSION = 32'h01000040; parameter mask_usb0__CAPLENGTH_HCIVERSION = 32'hFFFFFFFF; parameter usb0__HCSPARAMS = 32'hE0002104; parameter val_usb0__HCSPARAMS = 32'h00010011; parameter mask_usb0__HCSPARAMS = 32'h0FFFFFFF; parameter usb0__HCCPARAMS = 32'hE0002108; parameter val_usb0__HCCPARAMS = 32'h00000006; parameter mask_usb0__HCCPARAMS = 32'h0000FFFF; parameter usb0__DCIVERSION = 32'hE0002120; parameter val_usb0__DCIVERSION = 32'h00000001; parameter mask_usb0__DCIVERSION = 32'h0000FFFF; parameter usb0__DCCPARAMS = 32'hE0002124; parameter val_usb0__DCCPARAMS = 32'h0000018C; parameter mask_usb0__DCCPARAMS = 32'h000001FF; parameter usb0__USBCMD = 32'hE0002140; parameter val_usb0__USBCMD = 32'h00000B00; parameter mask_usb0__USBCMD = 32'h00FFFFFF; parameter usb0__USBSTS = 32'hE0002144; parameter val_usb0__USBSTS = 32'h00000000; parameter mask_usb0__USBSTS = 32'h03FFFFFF; parameter usb0__USBINTR = 32'hE0002148; parameter val_usb0__USBINTR = 32'h00000000; parameter mask_usb0__USBINTR = 32'h03FF0FFF; parameter usb0__FRINDEX = 32'hE000214C; parameter val_usb0__FRINDEX = 32'h00000000; parameter mask_usb0__FRINDEX = 32'h00003FFF; parameter usb0__PERIODICLISTBASE_DEVICEADDR = 32'hE0002154; parameter val_usb0__PERIODICLISTBASE_DEVICEADDR = 32'h00000000; parameter mask_usb0__PERIODICLISTBASE_DEVICEADDR = 32'hFFFFFFFF; parameter usb0__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hE0002158; parameter val_usb0__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'h00000000; parameter mask_usb0__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hFFFFFFFF; parameter usb0__TTCTRL = 32'hE000215C; parameter val_usb0__TTCTRL = 32'h00000000; parameter mask_usb0__TTCTRL = 32'hFFFFFFFF; parameter usb0__BURSTSIZE = 32'hE0002160; parameter val_usb0__BURSTSIZE = 32'h00001010; parameter mask_usb0__BURSTSIZE = 32'h0001FFFF; parameter usb0__TXFILLTUNING = 32'hE0002164; parameter val_usb0__TXFILLTUNING = 32'h00020000; parameter mask_usb0__TXFILLTUNING = 32'h003FFFFF; parameter usb0__TXTTFILLTUNING = 32'hE0002168; parameter val_usb0__TXTTFILLTUNING = 32'h00000000; parameter mask_usb0__TXTTFILLTUNING = 32'h00001FFF; parameter usb0__IC_USB = 32'hE000216C; parameter val_usb0__IC_USB = 32'h00000000; parameter mask_usb0__IC_USB = 32'hFFFFFFFF; parameter usb0__ULPI_VIEWPORT = 32'hE0002170; parameter val_usb0__ULPI_VIEWPORT = 32'h00000000; parameter mask_usb0__ULPI_VIEWPORT = 32'hFFFFFFFF; parameter usb0__ENDPTNAK = 32'hE0002178; parameter val_usb0__ENDPTNAK = 32'h00000000; parameter mask_usb0__ENDPTNAK = 32'hFFFFFFFF; parameter usb0__ENDPTNAKEN = 32'hE000217C; parameter val_usb0__ENDPTNAKEN = 32'h00000000; parameter mask_usb0__ENDPTNAKEN = 32'hFFFFFFFF; parameter usb0__CONFIGFLAG = 32'hE0002180; parameter val_usb0__CONFIGFLAG = 32'h00000001; parameter mask_usb0__CONFIGFLAG = 32'hFFFFFFFF; parameter usb0__PORTSC1 = 32'hE0002184; parameter val_usb0__PORTSC1 = 32'h00000000; parameter mask_usb0__PORTSC1 = 32'hFFFFFFFF; parameter usb0__OTGSC = 32'hE00021A4; parameter val_usb0__OTGSC = 32'h00000020; parameter mask_usb0__OTGSC = 32'hFFFFFFFF; parameter usb0__USBMODE = 32'hE00021A8; parameter val_usb0__USBMODE = 32'h00000000; parameter mask_usb0__USBMODE = 32'h0000FFFF; parameter usb0__ENDPTSETUPSTAT = 32'hE00021AC; parameter val_usb0__ENDPTSETUPSTAT = 32'h00000000; parameter mask_usb0__ENDPTSETUPSTAT = 32'h0000FFFF; parameter usb0__ENDPTPRIME = 32'hE00021B0; parameter val_usb0__ENDPTPRIME = 32'h00000000; parameter mask_usb0__ENDPTPRIME = 32'hFFFFFFFF; parameter usb0__ENDPTFLUSH = 32'hE00021B4; parameter val_usb0__ENDPTFLUSH = 32'h00000000; parameter mask_usb0__ENDPTFLUSH = 32'hFFFFFFFF; parameter usb0__ENDPTSTAT = 32'hE00021B8; parameter val_usb0__ENDPTSTAT = 32'h00000000; parameter mask_usb0__ENDPTSTAT = 32'hFFFFFFFF; parameter usb0__ENDPTCOMPLETE = 32'hE00021BC; parameter val_usb0__ENDPTCOMPLETE = 32'h00000000; parameter mask_usb0__ENDPTCOMPLETE = 32'hFFFFFFFF; parameter usb0__ENDPTCTRL0 = 32'hE00021C0; parameter val_usb0__ENDPTCTRL0 = 32'h00800080; parameter mask_usb0__ENDPTCTRL0 = 32'h00FFFFFF; parameter usb0__ENDPTCTRL1 = 32'hE00021C4; parameter val_usb0__ENDPTCTRL1 = 32'h00000000; parameter mask_usb0__ENDPTCTRL1 = 32'h00FFFFFF; parameter usb0__ENDPTCTRL2 = 32'hE00021C8; parameter val_usb0__ENDPTCTRL2 = 32'h00000000; parameter mask_usb0__ENDPTCTRL2 = 32'h00FFFFFF; parameter usb0__ENDPTCTRL3 = 32'hE00021CC; parameter val_usb0__ENDPTCTRL3 = 32'h00000000; parameter mask_usb0__ENDPTCTRL3 = 32'h00FFFFFF; parameter usb0__ENDPTCTRL4 = 32'hE00021D0; parameter val_usb0__ENDPTCTRL4 = 32'h00000000; parameter mask_usb0__ENDPTCTRL4 = 32'h00FFFFFF; parameter usb0__ENDPTCTRL5 = 32'hE00021D4; parameter val_usb0__ENDPTCTRL5 = 32'h00000000; parameter mask_usb0__ENDPTCTRL5 = 32'h00FFFFFF; parameter usb0__ENDPTCTRL6 = 32'hE00021D8; parameter val_usb0__ENDPTCTRL6 = 32'h00000000; parameter mask_usb0__ENDPTCTRL6 = 32'h00FFFFFF; parameter usb0__ENDPTCTRL7 = 32'hE00021DC; parameter val_usb0__ENDPTCTRL7 = 32'h00000000; parameter mask_usb0__ENDPTCTRL7 = 32'h00FFFFFF; parameter usb0__ENDPTCTRL8 = 32'hE00021E0; parameter val_usb0__ENDPTCTRL8 = 32'h00000000; parameter mask_usb0__ENDPTCTRL8 = 32'h00FFFFFF; parameter usb0__ENDPTCTRL9 = 32'hE00021E4; parameter val_usb0__ENDPTCTRL9 = 32'h00000000; parameter mask_usb0__ENDPTCTRL9 = 32'h00FFFFFF; parameter usb0__ENDPTCTRL10 = 32'hE00021E8; parameter val_usb0__ENDPTCTRL10 = 32'h00000000; parameter mask_usb0__ENDPTCTRL10 = 32'h00FFFFFF; parameter usb0__ENDPTCTRL11 = 32'hE00021EC; parameter val_usb0__ENDPTCTRL11 = 32'h00000000; parameter mask_usb0__ENDPTCTRL11 = 32'h00FFFFFF; parameter usb0__ENDPTCTRL12 = 32'hE00021F0; parameter val_usb0__ENDPTCTRL12 = 32'h00000000; parameter mask_usb0__ENDPTCTRL12 = 32'h00FFFFFF; // ************************************************************ // Module usb1 usb // doc version: 1.3 // ************************************************************ // ADDRESS DEVFALUE MASK NAME parameter usb1__ID = 32'hE0003000; parameter val_usb1__ID = 32'hE441FA05; parameter mask_usb1__ID = 32'hFFFFFFFF; parameter usb1__HWGENERAL = 32'hE0003004; parameter val_usb1__HWGENERAL = 32'h00000083; parameter mask_usb1__HWGENERAL = 32'h00000FFF; parameter usb1__HWHOST = 32'hE0003008; parameter val_usb1__HWHOST = 32'h10020001; parameter mask_usb1__HWHOST = 32'hFFFFFFFF; parameter usb1__HWDEVICE = 32'hE000300C; parameter val_usb1__HWDEVICE = 32'h00000019; parameter mask_usb1__HWDEVICE = 32'h0000003F; parameter usb1__HWTXBUF = 32'hE0003010; parameter val_usb1__HWTXBUF = 32'h80060A10; parameter mask_usb1__HWTXBUF = 32'hFFFFFFFF; parameter usb1__HWRXBUF = 32'hE0003014; parameter val_usb1__HWRXBUF = 32'h00000A10; parameter mask_usb1__HWRXBUF = 32'hFF00FFFF; parameter usb1__GPTIMER0LD = 32'hE0003080; parameter val_usb1__GPTIMER0LD = 32'h00000000; parameter mask_usb1__GPTIMER0LD = 32'h00FFFFFF; parameter usb1__GPTIMER0CTRL = 32'hE0003084; parameter val_usb1__GPTIMER0CTRL = 32'h00000000; parameter mask_usb1__GPTIMER0CTRL = 32'hFFFFFFFF; parameter usb1__GPTIMER1LD = 32'hE0003088; parameter val_usb1__GPTIMER1LD = 32'h00000000; parameter mask_usb1__GPTIMER1LD = 32'h00FFFFFF; parameter usb1__GPTIMER1CTRL = 32'hE000308C; parameter val_usb1__GPTIMER1CTRL = 32'h00000000; parameter mask_usb1__GPTIMER1CTRL = 32'hFFFFFFFF; parameter usb1__SBUSCFG = 32'hE0003090; parameter val_usb1__SBUSCFG = 32'h00000003; parameter mask_usb1__SBUSCFG = 32'h00000007; parameter usb1__CAPLENGTH_HCIVERSION = 32'hE0003100; parameter val_usb1__CAPLENGTH_HCIVERSION = 32'h01000040; parameter mask_usb1__CAPLENGTH_HCIVERSION = 32'hFFFFFFFF; parameter usb1__HCSPARAMS = 32'hE0003104; parameter val_usb1__HCSPARAMS = 32'h00010011; parameter mask_usb1__HCSPARAMS = 32'h0FFFFFFF; parameter usb1__HCCPARAMS = 32'hE0003108; parameter val_usb1__HCCPARAMS = 32'h00000006; parameter mask_usb1__HCCPARAMS = 32'h0000FFFF; parameter usb1__DCIVERSION = 32'hE0003120; parameter val_usb1__DCIVERSION = 32'h00000001; parameter mask_usb1__DCIVERSION = 32'h0000FFFF; parameter usb1__DCCPARAMS = 32'hE0003124; parameter val_usb1__DCCPARAMS = 32'h0000018C; parameter mask_usb1__DCCPARAMS = 32'h000001FF; parameter usb1__USBCMD = 32'hE0003140; parameter val_usb1__USBCMD = 32'h00000B00; parameter mask_usb1__USBCMD = 32'h00FFFFFF; parameter usb1__USBSTS = 32'hE0003144; parameter val_usb1__USBSTS = 32'h00000000; parameter mask_usb1__USBSTS = 32'h03FFFFFF; parameter usb1__USBINTR = 32'hE0003148; parameter val_usb1__USBINTR = 32'h00000000; parameter mask_usb1__USBINTR = 32'h03FF0FFF; parameter usb1__FRINDEX = 32'hE000314C; parameter val_usb1__FRINDEX = 32'h00000000; parameter mask_usb1__FRINDEX = 32'h00003FFF; parameter usb1__PERIODICLISTBASE_DEVICEADDR = 32'hE0003154; parameter val_usb1__PERIODICLISTBASE_DEVICEADDR = 32'h00000000; parameter mask_usb1__PERIODICLISTBASE_DEVICEADDR = 32'hFFFFFFFF; parameter usb1__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hE0003158; parameter val_usb1__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'h00000000; parameter mask_usb1__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hFFFFFFFF; parameter usb1__TTCTRL = 32'hE000315C; parameter val_usb1__TTCTRL = 32'h00000000; parameter mask_usb1__TTCTRL = 32'hFFFFFFFF; parameter usb1__BURSTSIZE = 32'hE0003160; parameter val_usb1__BURSTSIZE = 32'h00001010; parameter mask_usb1__BURSTSIZE = 32'h0001FFFF; parameter usb1__TXFILLTUNING = 32'hE0003164; parameter val_usb1__TXFILLTUNING = 32'h00020000; parameter mask_usb1__TXFILLTUNING = 32'h003FFFFF; parameter usb1__TXTTFILLTUNING = 32'hE0003168; parameter val_usb1__TXTTFILLTUNING = 32'h00000000; parameter mask_usb1__TXTTFILLTUNING = 32'h00001FFF; parameter usb1__IC_USB = 32'hE000316C; parameter val_usb1__IC_USB = 32'h00000000; parameter mask_usb1__IC_USB = 32'hFFFFFFFF; parameter usb1__ULPI_VIEWPORT = 32'hE0003170; parameter val_usb1__ULPI_VIEWPORT = 32'h00000000; parameter mask_usb1__ULPI_VIEWPORT = 32'hFFFFFFFF; parameter usb1__ENDPTNAK = 32'hE0003178; parameter val_usb1__ENDPTNAK = 32'h00000000; parameter mask_usb1__ENDPTNAK = 32'hFFFFFFFF; parameter usb1__ENDPTNAKEN = 32'hE000317C; parameter val_usb1__ENDPTNAKEN = 32'h00000000; parameter mask_usb1__ENDPTNAKEN = 32'hFFFFFFFF; parameter usb1__CONFIGFLAG = 32'hE0003180; parameter val_usb1__CONFIGFLAG = 32'h00000001; parameter mask_usb1__CONFIGFLAG = 32'hFFFFFFFF; parameter usb1__PORTSC1 = 32'hE0003184; parameter val_usb1__PORTSC1 = 32'h00000000; parameter mask_usb1__PORTSC1 = 32'hFFFFFFFF; parameter usb1__OTGSC = 32'hE00031A4; parameter val_usb1__OTGSC = 32'h00000020; parameter mask_usb1__OTGSC = 32'hFFFFFFFF; parameter usb1__USBMODE = 32'hE00031A8; parameter val_usb1__USBMODE = 32'h00000000; parameter mask_usb1__USBMODE = 32'h0000FFFF; parameter usb1__ENDPTSETUPSTAT = 32'hE00031AC; parameter val_usb1__ENDPTSETUPSTAT = 32'h00000000; parameter mask_usb1__ENDPTSETUPSTAT = 32'h0000FFFF; parameter usb1__ENDPTPRIME = 32'hE00031B0; parameter val_usb1__ENDPTPRIME = 32'h00000000; parameter mask_usb1__ENDPTPRIME = 32'hFFFFFFFF; parameter usb1__ENDPTFLUSH = 32'hE00031B4; parameter val_usb1__ENDPTFLUSH = 32'h00000000; parameter mask_usb1__ENDPTFLUSH = 32'hFFFFFFFF; parameter usb1__ENDPTSTAT = 32'hE00031B8; parameter val_usb1__ENDPTSTAT = 32'h00000000; parameter mask_usb1__ENDPTSTAT = 32'hFFFFFFFF; parameter usb1__ENDPTCOMPLETE = 32'hE00031BC; parameter val_usb1__ENDPTCOMPLETE = 32'h00000000; parameter mask_usb1__ENDPTCOMPLETE = 32'hFFFFFFFF; parameter usb1__ENDPTCTRL0 = 32'hE00031C0; parameter val_usb1__ENDPTCTRL0 = 32'h00800080; parameter mask_usb1__ENDPTCTRL0 = 32'h00FFFFFF; parameter usb1__ENDPTCTRL1 = 32'hE00031C4; parameter val_usb1__ENDPTCTRL1 = 32'h00000000; parameter mask_usb1__ENDPTCTRL1 = 32'h00FFFFFF; parameter usb1__ENDPTCTRL2 = 32'hE00031C8; parameter val_usb1__ENDPTCTRL2 = 32'h00000000; parameter mask_usb1__ENDPTCTRL2 = 32'h00FFFFFF; parameter usb1__ENDPTCTRL3 = 32'hE00031CC; parameter val_usb1__ENDPTCTRL3 = 32'h00000000; parameter mask_usb1__ENDPTCTRL3 = 32'h00FFFFFF; parameter usb1__ENDPTCTRL4 = 32'hE00031D0; parameter val_usb1__ENDPTCTRL4 = 32'h00000000; parameter mask_usb1__ENDPTCTRL4 = 32'h00FFFFFF; parameter usb1__ENDPTCTRL5 = 32'hE00031D4; parameter val_usb1__ENDPTCTRL5 = 32'h00000000; parameter mask_usb1__ENDPTCTRL5 = 32'h00FFFFFF; parameter usb1__ENDPTCTRL6 = 32'hE00031D8; parameter val_usb1__ENDPTCTRL6 = 32'h00000000; parameter mask_usb1__ENDPTCTRL6 = 32'h00FFFFFF; parameter usb1__ENDPTCTRL7 = 32'hE00031DC; parameter val_usb1__ENDPTCTRL7 = 32'h00000000; parameter mask_usb1__ENDPTCTRL7 = 32'h00FFFFFF; parameter usb1__ENDPTCTRL8 = 32'hE00031E0; parameter val_usb1__ENDPTCTRL8 = 32'h00000000; parameter mask_usb1__ENDPTCTRL8 = 32'h00FFFFFF; parameter usb1__ENDPTCTRL9 = 32'hE00031E4; parameter val_usb1__ENDPTCTRL9 = 32'h00000000; parameter mask_usb1__ENDPTCTRL9 = 32'h00FFFFFF; parameter usb1__ENDPTCTRL10 = 32'hE00031E8; parameter val_usb1__ENDPTCTRL10 = 32'h00000000; parameter mask_usb1__ENDPTCTRL10 = 32'h00FFFFFF; parameter usb1__ENDPTCTRL11 = 32'hE00031EC; parameter val_usb1__ENDPTCTRL11 = 32'h00000000; parameter mask_usb1__ENDPTCTRL11 = 32'h00FFFFFF; parameter usb1__ENDPTCTRL12 = 32'hE00031F0; parameter val_usb1__ENDPTCTRL12 = 32'h00000000; parameter mask_usb1__ENDPTCTRL12 = 32'h00FFFFFF;
/////////////////////////////////////////////////////////////////////////////// // // File name: axi_protocol_converter_v2_1_b2s_rd_cmd_fsm.v // /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_protocol_converter_v2_1_b2s_rd_cmd_fsm ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire clk , input wire reset , output wire s_arready , input wire s_arvalid , input wire [7:0] s_arlen , output wire m_arvalid , input wire m_arready , // signal to increment to the next mc transaction output wire next , // signal to the fsm there is another transaction required input wire next_pending , // Write Data portion has completed or Read FIFO has a slot available (not // full) input wire data_ready , // status signal for w_channel when command is written. output wire a_push , output wire r_push ); //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// // States localparam SM_IDLE = 2\'b00; localparam SM_CMD_EN = 2\'b01; localparam SM_CMD_ACCEPTED = 2\'b10; localparam SM_DONE = 2\'b11; //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// reg [1:0] state; // synthesis attribute MAX_FANOUT of state is 20; reg [1:0] state_r1; reg [1:0] next_state; reg [7:0] s_arlen_r; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL /////////////////////////////////////////////////////////////////////////////// // register for timing always @(posedge clk) begin if (reset) begin state <= SM_IDLE; state_r1 <= SM_IDLE; s_arlen_r <= 0; end else begin state <= next_state; state_r1 <= state; s_arlen_r <= s_arlen; end end // Next state transitions. always @( * ) begin next_state = state; case (state) SM_IDLE: if (s_arvalid & data_ready) begin next_state = SM_CMD_EN; end else begin next_state = state; end SM_CMD_EN: /////////////////////////////////////////////////////////////////// // Drive m_arvalid downstream in this state /////////////////////////////////////////////////////////////////// //If there is no fifo space if (~data_ready & m_arready & next_pending) begin /////////////////////////////////////////////////////////////////// //There is more to do, wait until data space is available drop valid next_state = SM_CMD_ACCEPTED; end else if (m_arready & ~next_pending)begin next_state = SM_DONE; end else if (m_arready & next_pending) begin next_state = SM_CMD_EN; end else begin next_state = state; end SM_CMD_ACCEPTED: if (data_ready) begin next_state = SM_CMD_EN; end else begin next_state = state; end SM_DONE: next_state = SM_IDLE; default: next_state = SM_IDLE; endcase end // Assign outputs based on current state. assign m_arvalid = (state == SM_CMD_EN); assign next = m_arready && (state == SM_CMD_EN); assign r_push = next; assign a_push = (state == SM_IDLE); assign s_arready = ((state == SM_CMD_EN) || (state == SM_DONE)) && (next_state == SM_IDLE); endmodule `default_nettype wire
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: Write Channel for ATC // // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // w_atc // //-------------------------------------------------------------------------- `timescale 1ps/1ps module processing_system7_v5_5_w_atc # ( parameter C_FAMILY = "rtl", // FPGA Family. Current version: virtex6, spartan6 or later. parameter integer C_AXI_ID_WIDTH = 4, // Width of all ID signals on SI and MI side of checker. // Range: >= 1. parameter integer C_AXI_DATA_WIDTH = 64, // Width of all DATA signals on SI and MI side of checker. // Range: 64. parameter integer C_AXI_WUSER_WIDTH = 1 // Width of AWUSER signals. // Range: >= 1. ) ( // Global Signals input wire ARESET, input wire ACLK, // Command Interface (In) input wire cmd_w_valid, input wire cmd_w_check, input wire [C_AXI_ID_WIDTH-1:0] cmd_w_id, output wire cmd_w_ready, // Command Interface (Out) output wire cmd_b_push, output wire cmd_b_error, output reg [C_AXI_ID_WIDTH-1:0] cmd_b_id, input wire cmd_b_full, // Slave Interface Write Port input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID, input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA, input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB, input wire S_AXI_WLAST, input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER, input wire S_AXI_WVALID, output wire S_AXI_WREADY, // Master Interface Write Address Port output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID, output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA, output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB, output wire M_AXI_WLAST, output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER, output wire M_AXI_WVALID, input wire M_AXI_WREADY ); ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// // Detecttion. wire any_strb_deasserted; wire incoming_strb_issue; reg first_word; reg strb_issue; // Data flow. wire data_pop; wire cmd_b_push_blocked; reg cmd_b_push_i; ///////////////////////////////////////////////////////////////////////////// // Detect error: // // Detect and accumulate error when a transaction shall be scanned for // potential issues. // Accumulation of error is restarted for each ne transaction. // ///////////////////////////////////////////////////////////////////////////// // Check stobe information assign any_strb_deasserted = ( S_AXI_WSTRB != {C_AXI_DATA_WIDTH/8{1\'b1}} ); assign incoming_strb_issue = cmd_w_valid & S_AXI_WVALID & cmd_w_check & any_strb_deasserted; // Keep track of first word in a transaction. always @ (posedge ACLK) begin if (ARESET) begin first_word <= 1\'b1; end else if ( data_pop ) begin first_word <= S_AXI_WLAST; end end // Keep track of error status. always @ (posedge ACLK) begin if (ARESET) begin strb_issue <= 1\'b0; cmd_b_id <= {C_AXI_ID_WIDTH{1\'b0}}; end else if ( data_pop ) begin if ( first_word ) begin strb_issue <= incoming_strb_issue; end else begin strb_issue <= incoming_strb_issue | strb_issue; end cmd_b_id <= cmd_w_id; end end assign cmd_b_error = strb_issue; ///////////////////////////////////////////////////////////////////////////// // Control command queue to B: // // Push command to B queue when all data for the transaction has flowed // through. // Delay pipelined command until there is room in the Queue. // ///////////////////////////////////////////////////////////////////////////// // Detect when data is popped. assign data_pop = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked; // Push command when last word in transfered (pipelined). always @ (posedge ACLK) begin if (ARESET) begin cmd_b_push_i <= 1\'b0; end else begin cmd_b_push_i <= ( S_AXI_WLAST & data_pop ) | cmd_b_push_blocked; end end // Detect if pipelined push is blocked. assign cmd_b_push_blocked = cmd_b_push_i & cmd_b_full; // Assign output. assign cmd_b_push = cmd_b_push_i & ~cmd_b_full; ///////////////////////////////////////////////////////////////////////////// // Transaction Throttling: // // Stall commands if FIFO is full or there is no valid command information // from AW. // ///////////////////////////////////////////////////////////////////////////// // Propagate masked valid. assign M_AXI_WVALID = S_AXI_WVALID & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked; // Return ready with push back. assign S_AXI_WREADY = M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked; // End of burst. assign cmd_w_ready = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked & S_AXI_WLAST; ///////////////////////////////////////////////////////////////////////////// // Write propagation: // // All information is simply forwarded on from the SI- to MI-Side untouched. // ///////////////////////////////////////////////////////////////////////////// // 1:1 mapping. assign M_AXI_WID = S_AXI_WID; assign M_AXI_WDATA = S_AXI_WDATA; assign M_AXI_WSTRB = S_AXI_WSTRB; assign M_AXI_WLAST = S_AXI_WLAST; assign M_AXI_WUSER = S_AXI_WUSER; endmodule
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // File name: crossbar.v // // Description: // This module is a M-master to N-slave AXI axi_crossbar_v2_1_crossbar switch. // The interface of this module consists of a vectored slave and master interface // in which all slots are sized and synchronized to the native width and clock // of the interconnect. // The SAMD axi_crossbar_v2_1_crossbar supports only AXI4 and AXI3 protocols. // All width, clock and protocol conversions are done outside this block, as are // any pipeline registers or data FIFOs. // This module contains all arbitration, decoders and channel multiplexing logic. // It also contains the diagnostic registers and control interface. // //----------------------------------------------------------------------------- // // Structure: // crossbar // si_transactor // addr_decoder // comparator_static // mux_enc // axic_srl_fifo // arbiter_resp // splitter // wdata_router // axic_reg_srl_fifo // wdata_mux // axic_reg_srl_fifo // mux_enc // addr_decoder // comparator_static // axic_srl_fifo // axi_register_slice // addr_arbiter // mux_enc // decerr_slave // //----------------------------------------------------------------------------- `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_crossbar_v2_1_crossbar # ( parameter C_FAMILY = "none", parameter integer C_NUM_SLAVE_SLOTS = 1, parameter integer C_NUM_MASTER_SLOTS = 1, parameter integer C_NUM_ADDR_RANGES = 1, parameter integer C_AXI_ID_WIDTH = 1, parameter integer C_AXI_ADDR_WIDTH = 32, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_PROTOCOL = 0, parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1\'b1}}, parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_HIGH_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1\'b0}}, parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_BASE_ID = {C_NUM_SLAVE_SLOTS*64{1\'b0}}, parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_HIGH_ID = {C_NUM_SLAVE_SLOTS*64{1\'b0}}, parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_THREAD_ID_WIDTH = {C_NUM_SLAVE_SLOTS{32\'h00000000}}, parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, parameter integer C_AXI_AWUSER_WIDTH = 1, parameter integer C_AXI_ARUSER_WIDTH = 1, parameter integer C_AXI_WUSER_WIDTH = 1, parameter integer C_AXI_RUSER_WIDTH = 1, parameter integer C_AXI_BUSER_WIDTH = 1, parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_WRITE = {C_NUM_SLAVE_SLOTS{1\'b1}}, parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_READ = {C_NUM_SLAVE_SLOTS{1\'b1}}, parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_WRITE = {C_NUM_MASTER_SLOTS{1\'b1}}, parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_READ = {C_NUM_MASTER_SLOTS{1\'b1}}, parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_CONNECTIVITY = {C_NUM_MASTER_SLOTS*32{1\'b1}}, parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_CONNECTIVITY = {C_NUM_MASTER_SLOTS*32{1\'b1}}, parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_SINGLE_THREAD = {C_NUM_SLAVE_SLOTS{32\'h00000000}}, parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_WRITE_ACCEPTANCE = {C_NUM_SLAVE_SLOTS{32\'h00000001}}, parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_READ_ACCEPTANCE = {C_NUM_SLAVE_SLOTS{32\'h00000001}}, parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_ISSUING = {C_NUM_MASTER_SLOTS{32\'h00000001}}, parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_ISSUING = {C_NUM_MASTER_SLOTS{32\'h00000001}}, parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY = {C_NUM_SLAVE_SLOTS{32\'h00000000}}, parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE = {C_NUM_MASTER_SLOTS{32\'h00000000}}, parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_ERR_MODE = {C_NUM_MASTER_SLOTS{32\'h00000000}}, parameter integer C_RANGE_CHECK = 0, parameter integer C_ADDR_DECODE = 0, parameter [(C_NUM_MASTER_SLOTS+1)*32-1:0] C_W_ISSUE_WIDTH = {C_NUM_MASTER_SLOTS+1{32\'h00000000}}, parameter [(C_NUM_MASTER_SLOTS+1)*32-1:0] C_R_ISSUE_WIDTH = {C_NUM_MASTER_SLOTS+1{32\'h00000000}}, parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_W_ACCEPT_WIDTH = {C_NUM_SLAVE_SLOTS{32\'h00000000}}, parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_R_ACCEPT_WIDTH = {C_NUM_SLAVE_SLOTS{32\'h00000000}}, parameter integer C_DEBUG = 1 ) ( // Global Signals input wire ACLK, input wire ARESETN, // Slave Interface Write Address Ports input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_AWID, input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR, input wire [C_NUM_SLAVE_SLOTS*8-1:0] S_AXI_AWLEN, input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_AWSIZE, input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_AWBURST, input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_AWLOCK, input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWCACHE, input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_AWPROT, // input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWREGION, input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWQOS, input wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_AWVALID, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_AWREADY, // Slave Interface Write Data Ports input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_WID, input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA, input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WLAST, input wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WVALID, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WREADY, // Slave Interface Write Response Ports output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_BID, output wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_BRESP, output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_BVALID, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_BREADY, // Slave Interface Read Address Ports input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_ARID, input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR, input wire [C_NUM_SLAVE_SLOTS*8-1:0] S_AXI_ARLEN, input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_ARSIZE, input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_ARBURST, input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_ARLOCK, input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARCACHE, input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_ARPROT, // input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARREGION, input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARQOS, input wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_ARVALID, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_ARREADY, // Slave Interface Read Data Ports output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_RID, output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA, output wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_RRESP, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RLAST, output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RVALID, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RREADY, // Master Interface Write Address Port output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_AWID, output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR, output wire [C_NUM_MASTER_SLOTS*8-1:0] M_AXI_AWLEN, output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_AWSIZE, output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_AWBURST, output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_AWLOCK, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWCACHE, output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_AWPROT, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWREGION, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWQOS, output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_AWVALID, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_AWREADY, // Master Interface Write Data Ports output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_WID, output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA, output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WLAST, output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WVALID, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WREADY, // Master Interface Write Response Ports input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_BID, input wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_BRESP, input wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_BVALID, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_BREADY, // Master Interface Read Address Port output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_ARID, output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR, output wire [C_NUM_MASTER_SLOTS*8-1:0] M_AXI_ARLEN, output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_ARSIZE, output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_ARBURST, output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_ARLOCK, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARCACHE, output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_ARPROT, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARREGION, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARQOS, output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_ARVALID, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_ARREADY, // Master Interface Read Data Ports input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_RID, input wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA, input wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_RRESP, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RLAST, input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RVALID, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RREADY ); localparam integer P_AXI4 = 0; localparam integer P_AXI3 = 1; localparam integer P_AXILITE = 2; localparam integer P_WRITE = 0; localparam integer P_READ = 1; localparam integer P_NUM_MASTER_SLOTS_LOG = f_ceil_log2(C_NUM_MASTER_SLOTS); localparam integer P_NUM_SLAVE_SLOTS_LOG = f_ceil_log2((C_NUM_SLAVE_SLOTS>1) ? C_NUM_SLAVE_SLOTS : 2); localparam integer P_AXI_WID_WIDTH = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 1; localparam integer P_ST_AWMESG_WIDTH = 2+4+4 + C_AXI_AWUSER_WIDTH; localparam integer P_AA_AWMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+4 + P_ST_AWMESG_WIDTH; localparam integer P_ST_ARMESG_WIDTH = 2+4+4 + C_AXI_ARUSER_WIDTH; localparam integer P_AA_ARMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+4 + P_ST_ARMESG_WIDTH; localparam integer P_ST_BMESG_WIDTH = 2 + C_AXI_BUSER_WIDTH; localparam integer P_ST_RMESG_WIDTH = 2 + C_AXI_RUSER_WIDTH + C_AXI_DATA_WIDTH; localparam integer P_WR_WMESG_WIDTH = C_AXI_DATA_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_WUSER_WIDTH + P_AXI_WID_WIDTH; localparam [31:0] P_BYPASS = 32\'h00000000; localparam [31:0] P_FWD_REV = 32\'h00000001; localparam [31:0] P_SIMPLE = 32\'h00000007; localparam [(C_NUM_MASTER_SLOTS+1)-1:0] P_M_AXI_SUPPORTS_READ = {1\'b1, C_M_AXI_SUPPORTS_READ[0+:C_NUM_MASTER_SLOTS]}; localparam [(C_NUM_MASTER_SLOTS+1)-1:0] P_M_AXI_SUPPORTS_WRITE = {1\'b1, C_M_AXI_SUPPORTS_WRITE[0+:C_NUM_MASTER_SLOTS]}; localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_WRITE_CONNECTIVITY = {{32{1\'b1}}, C_M_AXI_WRITE_CONNECTIVITY[0+:C_NUM_MASTER_SLOTS*32]}; localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_READ_CONNECTIVITY = {{32{1\'b1}}, C_M_AXI_READ_CONNECTIVITY[0+:C_NUM_MASTER_SLOTS*32]}; localparam [C_NUM_SLAVE_SLOTS*32-1:0] P_S_AXI_WRITE_CONNECTIVITY = f_si_write_connectivity(0); localparam [C_NUM_SLAVE_SLOTS*32-1:0] P_S_AXI_READ_CONNECTIVITY = f_si_read_connectivity(0); localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_READ_ISSUING = {32\'h00000001, C_M_AXI_READ_ISSUING[0+:C_NUM_MASTER_SLOTS*32]}; localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_WRITE_ISSUING = {32\'h00000001, C_M_AXI_WRITE_ISSUING[0+:C_NUM_MASTER_SLOTS*32]}; localparam P_DECERR = 2\'b11; //--------------------------------------------------------------------------- // Functions //--------------------------------------------------------------------------- // Ceiling of log2(x) function integer f_ceil_log2 ( input integer x ); integer acc; begin acc=0; while ((2**acc) < x) acc = acc + 1; f_ceil_log2 = acc; end endfunction // Isolate thread bits of input S_ID and add to BASE_ID (RNG00) to form MI-side ID value // only for end-point SI-slots function [C_AXI_ID_WIDTH-1:0] f_extend_ID ( input [C_AXI_ID_WIDTH-1:0] s_id, input integer slot ); begin f_extend_ID = C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] | (s_id & (C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] ^ C_S_AXI_HIGH_ID[slot*64+:C_AXI_ID_WIDTH])); end endfunction // Write connectivity array transposed function [C_NUM_SLAVE_SLOTS*32-1:0] f_si_write_connectivity ( input integer null_arg ); integer si_slot; integer mi_slot; reg [C_NUM_SLAVE_SLOTS*32-1:0] result; begin result = {C_NUM_SLAVE_SLOTS*32{1\'b1}}; for (si_slot=0; si_slot<C_NUM_SLAVE_SLOTS; si_slot=si_slot+1) begin for (mi_slot=0; mi_slot<C_NUM_MASTER_SLOTS; mi_slot=mi_slot+1) begin result[si_slot*32+mi_slot] = C_M_AXI_WRITE_CONNECTIVITY[mi_slot*32+si_slot]; end end f_si_write_connectivity = result; end endfunction // Read connectivity array transposed function [C_NUM_SLAVE_SLOTS*32-1:0] f_si_read_connectivity ( input integer null_arg ); integer si_slot; integer mi_slot; reg [C_NUM_SLAVE_SLOTS*32-1:0] result; begin result = {C_NUM_SLAVE_SLOTS*32{1\'b1}}; for (si_slot=0; si_slot<C_NUM_SLAVE_SLOTS; si_slot=si_slot+1) begin for (mi_slot=0; mi_slot<C_NUM_MASTER_SLOTS; mi_slot=mi_slot+1) begin result[si_slot*32+mi_slot] = C_M_AXI_READ_CONNECTIVITY[mi_slot*32+si_slot]; end end f_si_read_connectivity = result; end endfunction genvar gen_si_slot; genvar gen_mi_slot; wire [C_NUM_SLAVE_SLOTS*P_ST_AWMESG_WIDTH-1:0] si_st_awmesg ; wire [C_NUM_SLAVE_SLOTS*P_ST_AWMESG_WIDTH-1:0] st_tmp_awmesg ; wire [C_NUM_SLAVE_SLOTS*P_AA_AWMESG_WIDTH-1:0] tmp_aa_awmesg ; wire [P_AA_AWMESG_WIDTH-1:0] aa_mi_awmesg ; wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] st_aa_awid ; wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] st_aa_awaddr ; wire [C_NUM_SLAVE_SLOTS*8-1:0] st_aa_awlen ; wire [C_NUM_SLAVE_SLOTS*3-1:0] st_aa_awsize ; wire [C_NUM_SLAVE_SLOTS*2-1:0] st_aa_awlock ; wire [C_NUM_SLAVE_SLOTS*3-1:0] st_aa_awprot ; wire [C_NUM_SLAVE_SLOTS*4-1:0] st_aa_awregion ; wire [C_NUM_SLAVE_SLOTS*8-1:0] st_aa_awerror ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_aa_awtarget_hot ; wire [C_NUM_SLAVE_SLOTS*(P_NUM_MASTER_SLOTS_LOG+1)-1:0] st_aa_awtarget_enc ; wire [P_NUM_SLAVE_SLOTS_LOG*1-1:0] aa_wm_awgrant_enc ; wire [(C_NUM_MASTER_SLOTS+1)-1:0] aa_mi_awtarget_hot ; wire [C_NUM_SLAVE_SLOTS*1-1:0] st_aa_awvalid_qual ; wire [C_NUM_SLAVE_SLOTS*1-1:0] st_ss_awvalid ; wire [C_NUM_SLAVE_SLOTS*1-1:0] st_ss_awready ; wire [C_NUM_SLAVE_SLOTS*1-1:0] ss_wr_awvalid ; wire [C_NUM_SLAVE_SLOTS*1-1:0] ss_wr_awready ; wire [C_NUM_SLAVE_SLOTS*1-1:0] ss_aa_awvalid ; wire [C_NUM_SLAVE_SLOTS*1-1:0] ss_aa_awready ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] sa_wm_awvalid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] sa_wm_awready ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_awvalid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_awready ; wire aa_sa_awvalid ; wire aa_sa_awready ; wire aa_mi_arready ; wire mi_awvalid_en ; wire sa_wm_awvalid_en ; wire sa_wm_awready_mux ; wire [C_NUM_SLAVE_SLOTS*P_ST_ARMESG_WIDTH-1:0] si_st_armesg ; wire [C_NUM_SLAVE_SLOTS*P_ST_ARMESG_WIDTH-1:0] st_tmp_armesg ; wire [C_NUM_SLAVE_SLOTS*P_AA_ARMESG_WIDTH-1:0] tmp_aa_armesg ; wire [P_AA_ARMESG_WIDTH-1:0] aa_mi_armesg ; wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] st_aa_arid ; wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] st_aa_araddr ; wire [C_NUM_SLAVE_SLOTS*8-1:0] st_aa_arlen ; wire [C_NUM_SLAVE_SLOTS*3-1:0] st_aa_arsize ; wire [C_NUM_SLAVE_SLOTS*2-1:0] st_aa_arlock ; wire [C_NUM_SLAVE_SLOTS*3-1:0] st_aa_arprot ; wire [C_NUM_SLAVE_SLOTS*4-1:0] st_aa_arregion ; wire [C_NUM_SLAVE_SLOTS*8-1:0] st_aa_arerror ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_aa_artarget_hot ; wire [C_NUM_SLAVE_SLOTS*(P_NUM_MASTER_SLOTS_LOG+1)-1:0] st_aa_artarget_enc ; wire [(C_NUM_MASTER_SLOTS+1)-1:0] aa_mi_artarget_hot ; wire [P_NUM_SLAVE_SLOTS_LOG*1-1:0] aa_mi_argrant_enc ; wire [C_NUM_SLAVE_SLOTS*1-1:0] st_aa_arvalid_qual ; wire [C_NUM_SLAVE_SLOTS*1-1:0] st_aa_arvalid ; wire [C_NUM_SLAVE_SLOTS*1-1:0] st_aa_arready ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_arvalid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_arready ; wire aa_mi_arvalid ; wire mi_awready_mux ; wire [C_NUM_SLAVE_SLOTS*P_ST_BMESG_WIDTH-1:0] st_si_bmesg ; wire [(C_NUM_MASTER_SLOTS+1)*P_ST_BMESG_WIDTH-1:0] st_mr_bmesg ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] st_mr_bid ; wire [(C_NUM_MASTER_SLOTS+1)*2-1:0] st_mr_bresp ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_BUSER_WIDTH-1:0] st_mr_buser ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_bvalid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_bready ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_tmp_bready ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_tmp_bid_target ; wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0] tmp_mr_bid_target ; wire [(C_NUM_MASTER_SLOTS+1)*P_NUM_SLAVE_SLOTS_LOG-1:0] debug_bid_target_i ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] bid_match ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] mi_bid ; wire [(C_NUM_MASTER_SLOTS+1)*2-1:0] mi_bresp ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_BUSER_WIDTH-1:0] mi_buser ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_bvalid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_bready ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] bready_carry ; wire [C_NUM_SLAVE_SLOTS*P_ST_RMESG_WIDTH-1:0] st_si_rmesg ; wire [(C_NUM_MASTER_SLOTS+1)*P_ST_RMESG_WIDTH-1:0] st_mr_rmesg ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] st_mr_rid ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0] st_mr_rdata ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_RUSER_WIDTH-1:0] st_mr_ruser ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_rlast ; wire [(C_NUM_MASTER_SLOTS+1)*2-1:0] st_mr_rresp ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_rvalid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_rready ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_tmp_rready ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_tmp_rid_target ; wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0] tmp_mr_rid_target ; wire [(C_NUM_MASTER_SLOTS+1)*P_NUM_SLAVE_SLOTS_LOG-1:0] debug_rid_target_i ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] rid_match ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] mi_rid ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0] mi_rdata ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_RUSER_WIDTH-1:0] mi_ruser ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_rlast ; wire [(C_NUM_MASTER_SLOTS+1)*2-1:0] mi_rresp ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_rvalid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_rready ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] rready_carry ; wire [C_NUM_SLAVE_SLOTS*P_WR_WMESG_WIDTH-1:0] si_wr_wmesg ; wire [C_NUM_SLAVE_SLOTS*P_WR_WMESG_WIDTH-1:0] wr_wm_wmesg ; wire [C_NUM_SLAVE_SLOTS*1-1:0] wr_wm_wlast ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] wr_tmp_wvalid ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] wr_tmp_wready ; wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0] tmp_wm_wvalid ; wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0] tmp_wm_wready ; wire [(C_NUM_MASTER_SLOTS+1)*P_WR_WMESG_WIDTH-1:0] wm_mr_wmesg ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0] wm_mr_wdata ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH/8-1:0] wm_mr_wstrb ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] wm_mr_wid ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_WUSER_WIDTH-1:0] wm_mr_wuser ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] wm_mr_wlast ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] wm_mr_wvalid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] wm_mr_wready ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0] mi_wdata ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH/8-1:0] mi_wstrb ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_WUSER_WIDTH-1:0] mi_wuser ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] mi_wid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_wlast ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_wvalid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_wready ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] w_cmd_push ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] w_cmd_pop ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] r_cmd_push ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] r_cmd_pop ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_awmaxissuing ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_armaxissuing ; reg [(C_NUM_MASTER_SLOTS+1)*8-1:0] w_issuing_cnt ; reg [(C_NUM_MASTER_SLOTS+1)*8-1:0] r_issuing_cnt ; reg [8-1:0] debug_aw_trans_seq_i ; reg [8-1:0] debug_ar_trans_seq_i ; wire [(C_NUM_MASTER_SLOTS+1)*8-1:0] debug_w_trans_seq_i ; reg [(C_NUM_MASTER_SLOTS+1)*8-1:0] debug_w_beat_cnt_i ; reg aresetn_d = 1\'b0; // Reset delay register always @(posedge ACLK) begin if (~ARESETN) begin aresetn_d <= 1\'b0; end else begin aresetn_d <= ARESETN; end end wire reset; assign reset = ~aresetn_d; generate for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_slave_slots if (C_S_AXI_SUPPORTS_READ[gen_si_slot]) begin : gen_si_read axi_crossbar_v2_1_si_transactor # // "ST": SI Transactor (read channel) ( .C_FAMILY (C_FAMILY), .C_SI (gen_si_slot), .C_DIR (P_READ), .C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES), .C_NUM_M (C_NUM_MASTER_SLOTS), .C_NUM_M_LOG (P_NUM_MASTER_SLOTS_LOG), .C_ACCEPTANCE (C_S_AXI_READ_ACCEPTANCE[gen_si_slot*32+:32]), .C_ACCEPTANCE_LOG (C_R_ACCEPT_WIDTH[gen_si_slot*32+:32]), .C_ID_WIDTH (C_AXI_ID_WIDTH), .C_THREAD_ID_WIDTH (C_S_AXI_THREAD_ID_WIDTH[gen_si_slot*32+:32]), .C_ADDR_WIDTH (C_AXI_ADDR_WIDTH), .C_AMESG_WIDTH (P_ST_ARMESG_WIDTH), .C_RMESG_WIDTH (P_ST_RMESG_WIDTH), .C_BASE_ID (C_S_AXI_BASE_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]), .C_HIGH_ID (C_S_AXI_HIGH_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]), .C_SINGLE_THREAD (C_S_AXI_SINGLE_THREAD[gen_si_slot*32+:32]), .C_BASE_ADDR (C_M_AXI_BASE_ADDR), .C_HIGH_ADDR (C_M_AXI_HIGH_ADDR), .C_TARGET_QUAL (P_S_AXI_READ_CONNECTIVITY[gen_si_slot*32+:C_NUM_MASTER_SLOTS]), .C_M_AXI_SECURE (C_M_AXI_SECURE), .C_RANGE_CHECK (C_RANGE_CHECK), .C_ADDR_DECODE (C_ADDR_DECODE), .C_ERR_MODE (C_M_AXI_ERR_MODE), .C_DEBUG (C_DEBUG) ) si_transactor_ar ( .ACLK (ACLK), .ARESET (reset), .S_AID (f_extend_ID(S_AXI_ARID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot)), .S_AADDR (S_AXI_ARADDR[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]), .S_ALEN (S_AXI_ARLEN[gen_si_slot*8+:8]), .S_ASIZE (S_AXI_ARSIZE[gen_si_slot*3+:3]), .S_ABURST (S_AXI_ARBURST[gen_si_slot*2+:2]), .S_ALOCK (S_AXI_ARLOCK[gen_si_slot*2+:2]), .S_APROT (S_AXI_ARPROT[gen_si_slot*3+:3]), // .S_AREGION (S_AXI_ARREGION[gen_si_slot*4+:4]), .S_AMESG (si_st_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH]), .S_AVALID (S_AXI_ARVALID[gen_si_slot]), .S_AREADY (S_AXI_ARREADY[gen_si_slot]), .M_AID (st_aa_arid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .M_AADDR (st_aa_araddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]), .M_ALEN (st_aa_arlen[gen_si_slot*8+:8]), .M_ASIZE (st_aa_arsize[gen_si_slot*3+:3]), .M_ALOCK (st_aa_arlock[gen_si_slot*2+:2]), .M_APROT (st_aa_arprot[gen_si_slot*3+:3]), .M_AREGION (st_aa_arregion[gen_si_slot*4+:4]), .M_AMESG (st_tmp_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH]), .M_ATARGET_HOT (st_aa_artarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]), .M_ATARGET_ENC (st_aa_artarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]), .M_AERROR (st_aa_arerror[gen_si_slot*8+:8]), .M_AVALID_QUAL (st_aa_arvalid_qual[gen_si_slot]), .M_AVALID (st_aa_arvalid[gen_si_slot]), .M_AREADY (st_aa_arready[gen_si_slot]), .S_RID (S_AXI_RID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .S_RMESG (st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH]), .S_RLAST (S_AXI_RLAST[gen_si_slot]), .S_RVALID (S_AXI_RVALID[gen_si_slot]), .S_RREADY (S_AXI_RREADY[gen_si_slot]), .M_RID (st_mr_rid), .M_RLAST (st_mr_rlast), .M_RMESG (st_mr_rmesg), .M_RVALID (st_mr_rvalid), .M_RREADY (st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]), .M_RTARGET (st_tmp_rid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]), .DEBUG_A_TRANS_SEQ (C_DEBUG ? debug_ar_trans_seq_i : 8\'h0) ); assign si_st_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH] = { S_AXI_ARUSER[gen_si_slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH], S_AXI_ARQOS[gen_si_slot*4+:4], S_AXI_ARCACHE[gen_si_slot*4+:4], S_AXI_ARBURST[gen_si_slot*2+:2] }; assign tmp_aa_armesg[gen_si_slot*P_AA_ARMESG_WIDTH+:P_AA_ARMESG_WIDTH] = { st_tmp_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH], st_aa_arregion[gen_si_slot*4+:4], st_aa_arprot[gen_si_slot*3+:3], st_aa_arlock[gen_si_slot*2+:2], st_aa_arsize[gen_si_slot*3+:3], st_aa_arlen[gen_si_slot*8+:8], st_aa_araddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH], st_aa_arid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] }; assign S_AXI_RRESP[gen_si_slot*2+:2] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+:2]; assign S_AXI_RUSER[gen_si_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+2 +: C_AXI_RUSER_WIDTH]; assign S_AXI_RDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+2+C_AXI_RUSER_WIDTH +: C_AXI_DATA_WIDTH]; end else begin : gen_no_si_read assign S_AXI_ARREADY[gen_si_slot] = 1\'b0; assign st_aa_arvalid[gen_si_slot] = 1\'b0; assign st_aa_arvalid_qual[gen_si_slot] = 1\'b1; assign tmp_aa_armesg[gen_si_slot*P_AA_ARMESG_WIDTH+:P_AA_ARMESG_WIDTH] = 0; assign S_AXI_RID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0; assign S_AXI_RRESP[gen_si_slot*2+:2] = 0; assign S_AXI_RUSER[gen_si_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = 0; assign S_AXI_RDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0; assign S_AXI_RVALID[gen_si_slot] = 1\'b0; assign S_AXI_RLAST[gen_si_slot] = 1\'b0; assign st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0; assign st_aa_artarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0; end // gen_si_read if (C_S_AXI_SUPPORTS_WRITE[gen_si_slot]) begin : gen_si_write axi_crossbar_v2_1_si_transactor # // "ST": SI Transactor (write channel) ( .C_FAMILY (C_FAMILY), .C_SI (gen_si_slot), .C_DIR (P_WRITE), .C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES), .C_NUM_M (C_NUM_MASTER_SLOTS), .C_NUM_M_LOG (P_NUM_MASTER_SLOTS_LOG), .C_ACCEPTANCE (C_S_AXI_WRITE_ACCEPTANCE[gen_si_slot*32+:32]), .C_ACCEPTANCE_LOG (C_W_ACCEPT_WIDTH[gen_si_slot*32+:32]), .C_ID_WIDTH (C_AXI_ID_WIDTH), .C_THREAD_ID_WIDTH (C_S_AXI_THREAD_ID_WIDTH[gen_si_slot*32+:32]), .C_ADDR_WIDTH (C_AXI_ADDR_WIDTH), .C_AMESG_WIDTH (P_ST_AWMESG_WIDTH), .C_RMESG_WIDTH (P_ST_BMESG_WIDTH), .C_BASE_ID (C_S_AXI_BASE_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]), .C_HIGH_ID (C_S_AXI_HIGH_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]), .C_SINGLE_THREAD (C_S_AXI_SINGLE_THREAD[gen_si_slot*32+:32]), .C_BASE_ADDR (C_M_AXI_BASE_ADDR), .C_HIGH_ADDR (C_M_AXI_HIGH_ADDR), .C_TARGET_QUAL (P_S_AXI_WRITE_CONNECTIVITY[gen_si_slot*32+:C_NUM_MASTER_SLOTS]), .C_M_AXI_SECURE (C_M_AXI_SECURE), .C_RANGE_CHECK (C_RANGE_CHECK), .C_ADDR_DECODE (C_ADDR_DECODE), .C_ERR_MODE (C_M_AXI_ERR_MODE), .C_DEBUG (C_DEBUG) ) si_transactor_aw ( .ACLK (ACLK), .ARESET (reset), .S_AID (f_extend_ID(S_AXI_AWID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot)), .S_AADDR (S_AXI_AWADDR[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]), .S_ALEN (S_AXI_AWLEN[gen_si_slot*8+:8]), .S_ASIZE (S_AXI_AWSIZE[gen_si_slot*3+:3]), .S_ABURST (S_AXI_AWBURST[gen_si_slot*2+:2]), .S_ALOCK (S_AXI_AWLOCK[gen_si_slot*2+:2]), .S_APROT (S_AXI_AWPROT[gen_si_slot*3+:3]), // .S_AREGION (S_AXI_AWREGION[gen_si_slot*4+:4]), .S_AMESG (si_st_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH]), .S_AVALID (S_AXI_AWVALID[gen_si_slot]), .S_AREADY (S_AXI_AWREADY[gen_si_slot]), .M_AID (st_aa_awid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .M_AADDR (st_aa_awaddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]), .M_ALEN (st_aa_awlen[gen_si_slot*8+:8]), .M_ASIZE (st_aa_awsize[gen_si_slot*3+:3]), .M_ALOCK (st_aa_awlock[gen_si_slot*2+:2]), .M_APROT (st_aa_awprot[gen_si_slot*3+:3]), .M_AREGION (st_aa_awregion[gen_si_slot*4+:4]), .M_AMESG (st_tmp_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH]), .M_ATARGET_HOT (st_aa_awtarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]), .M_ATARGET_ENC (st_aa_awtarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]), .M_AERROR (st_aa_awerror[gen_si_slot*8+:8]), .M_AVALID_QUAL (st_aa_awvalid_qual[gen_si_slot]), .M_AVALID (st_ss_awvalid[gen_si_slot]), .M_AREADY (st_ss_awready[gen_si_slot]), .S_RID (S_AXI_BID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .S_RMESG (st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH]), .S_RLAST (), .S_RVALID (S_AXI_BVALID[gen_si_slot]), .S_RREADY (S_AXI_BREADY[gen_si_slot]), .M_RID (st_mr_bid), .M_RLAST ({(C_NUM_MASTER_SLOTS+1){1\'b1}}), .M_RMESG (st_mr_bmesg), .M_RVALID (st_mr_bvalid), .M_RREADY (st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]), .M_RTARGET (st_tmp_bid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]), .DEBUG_A_TRANS_SEQ (C_DEBUG ? debug_aw_trans_seq_i : 8\'h0) ); // Note: Concatenation of mesg signals is from MSB to LSB; assignments that chop mesg signals appear in opposite order. assign si_st_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH] = { S_AXI_AWUSER[gen_si_slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH], S_AXI_AWQOS[gen_si_slot*4+:4], S_AXI_AWCACHE[gen_si_slot*4+:4], S_AXI_AWBURST[gen_si_slot*2+:2] }; assign tmp_aa_awmesg[gen_si_slot*P_AA_AWMESG_WIDTH+:P_AA_AWMESG_WIDTH] = { st_tmp_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH], st_aa_awregion[gen_si_slot*4+:4], st_aa_awprot[gen_si_slot*3+:3], st_aa_awlock[gen_si_slot*2+:2], st_aa_awsize[gen_si_slot*3+:3], st_aa_awlen[gen_si_slot*8+:8], st_aa_awaddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH], st_aa_awid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] }; assign S_AXI_BRESP[gen_si_slot*2+:2] = st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+:2]; assign S_AXI_BUSER[gen_si_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+2 +: C_AXI_BUSER_WIDTH]; // AW SI-transactor transfer completes upon completion of both W-router address acceptance (command push) and AW arbitration axi_crossbar_v2_1_splitter # // "SS": Splitter from SI-Transactor (write channel) ( .C_NUM_M (2) ) splitter_aw_si ( .ACLK (ACLK), .ARESET (reset), .S_VALID (st_ss_awvalid[gen_si_slot]), .S_READY (st_ss_awready[gen_si_slot]), .M_VALID ({ss_wr_awvalid[gen_si_slot], ss_aa_awvalid[gen_si_slot]}), .M_READY ({ss_wr_awready[gen_si_slot], ss_aa_awready[gen_si_slot]}) ); axi_crossbar_v2_1_wdata_router # // "WR": Write data Router ( .C_FAMILY (C_FAMILY), .C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS+1), .C_SELECT_WIDTH (P_NUM_MASTER_SLOTS_LOG+1), .C_WMESG_WIDTH (P_WR_WMESG_WIDTH), .C_FIFO_DEPTH_LOG (C_W_ACCEPT_WIDTH[gen_si_slot*32+:6]) ) wdata_router_w ( .ACLK (ACLK), .ARESET (reset), // Write transfer input from the current SI-slot .S_WMESG (si_wr_wmesg[gen_si_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH]), .S_WLAST (S_AXI_WLAST[gen_si_slot]), .S_WVALID (S_AXI_WVALID[gen_si_slot]), .S_WREADY (S_AXI_WREADY[gen_si_slot]), // Vector of write transfer outputs to each MI-slot\'s W-mux .M_WMESG (wr_wm_wmesg[gen_si_slot*(P_WR_WMESG_WIDTH)+:P_WR_WMESG_WIDTH]), .M_WLAST (wr_wm_wlast[gen_si_slot]), .M_WVALID (wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]), .M_WREADY (wr_tmp_wready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]), // AW command push from local SI-slot .S_ASELECT (st_aa_awtarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]), // Target MI-slot .S_AVALID (ss_wr_awvalid[gen_si_slot]), .S_AREADY (ss_wr_awready[gen_si_slot]) ); assign si_wr_wmesg[gen_si_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH] = { ((C_AXI_PROTOCOL == P_AXI3) ? f_extend_ID(S_AXI_WID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot) : 1\'b0), S_AXI_WUSER[gen_si_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH], S_AXI_WSTRB[gen_si_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8], S_AXI_WDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] }; end else begin : gen_no_si_write assign S_AXI_AWREADY[gen_si_slot] = 1\'b0; assign ss_aa_awvalid[gen_si_slot] = 1\'b0; assign st_aa_awvalid_qual[gen_si_slot] = 1\'b1; assign tmp_aa_awmesg[gen_si_slot*P_AA_AWMESG_WIDTH+:P_AA_AWMESG_WIDTH] = 0; assign S_AXI_BID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0; assign S_AXI_BRESP[gen_si_slot*2+:2] = 0; assign S_AXI_BUSER[gen_si_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = 0; assign S_AXI_BVALID[gen_si_slot] = 1\'b0; assign st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0; assign S_AXI_WREADY[gen_si_slot] = 1\'b0; assign wr_wm_wmesg[gen_si_slot*(P_WR_WMESG_WIDTH)+:P_WR_WMESG_WIDTH] = 0; assign wr_wm_wlast[gen_si_slot] = 1\'b0; assign wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0; assign st_aa_awtarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0; end // gen_si_write end // gen_slave_slots for (gen_mi_slot=0; gen_mi_slot<C_NUM_MASTER_SLOTS+1; gen_mi_slot=gen_mi_slot+1) begin : gen_master_slots if (P_M_AXI_SUPPORTS_READ[gen_mi_slot]) begin : gen_mi_read if (C_NUM_SLAVE_SLOTS>1) begin : gen_rid_decoder axi_crossbar_v2_1_addr_decoder # ( .C_FAMILY (C_FAMILY), .C_NUM_TARGETS (C_NUM_SLAVE_SLOTS), .C_NUM_TARGETS_LOG (P_NUM_SLAVE_SLOTS_LOG), .C_NUM_RANGES (1), .C_ADDR_WIDTH (C_AXI_ID_WIDTH), .C_TARGET_ENC (C_DEBUG), .C_TARGET_HOT (1), .C_REGION_ENC (0), .C_BASE_ADDR (C_S_AXI_BASE_ID), .C_HIGH_ADDR (C_S_AXI_HIGH_ID), .C_TARGET_QUAL (P_M_AXI_READ_CONNECTIVITY[gen_mi_slot*32+:C_NUM_SLAVE_SLOTS]), .C_RESOLUTION (0) ) rid_decoder_inst ( .ADDR (st_mr_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .TARGET_HOT (tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]), .TARGET_ENC (debug_rid_target_i[gen_mi_slot*P_NUM_SLAVE_SLOTS_LOG+:P_NUM_SLAVE_SLOTS_LOG]), .MATCH (rid_match[gen_mi_slot]), .REGION () ); end else begin : gen_no_rid_decoder assign tmp_mr_rid_target[gen_mi_slot] = 1\'b1; // All response transfers route to solo SI-slot. assign rid_match[gen_mi_slot] = 1\'b1; end assign st_mr_rmesg[gen_mi_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH] = { st_mr_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH], st_mr_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH], st_mr_rresp[gen_mi_slot*2+:2] }; end else begin : gen_no_mi_read assign tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0; assign rid_match[gen_mi_slot] = 1\'b0; assign st_mr_rmesg[gen_mi_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH] = 0; end // gen_mi_read if (P_M_AXI_SUPPORTS_WRITE[gen_mi_slot]) begin : gen_mi_write if (C_NUM_SLAVE_SLOTS>1) begin : gen_bid_decoder axi_crossbar_v2_1_addr_decoder # ( .C_FAMILY (C_FAMILY), .C_NUM_TARGETS (C_NUM_SLAVE_SLOTS), .C_NUM_TARGETS_LOG (P_NUM_SLAVE_SLOTS_LOG), .C_NUM_RANGES (1), .C_ADDR_WIDTH (C_AXI_ID_WIDTH), .C_TARGET_ENC (C_DEBUG), .C_TARGET_HOT (1), .C_REGION_ENC (0), .C_BASE_ADDR (C_S_AXI_BASE_ID), .C_HIGH_ADDR (C_S_AXI_HIGH_ID), .C_TARGET_QUAL (P_M_AXI_WRITE_CONNECTIVITY[gen_mi_slot*32+:C_NUM_SLAVE_SLOTS]), .C_RESOLUTION (0) ) bid_decoder_inst ( .ADDR (st_mr_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .TARGET_HOT (tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]), .TARGET_ENC (debug_bid_target_i[gen_mi_slot*P_NUM_SLAVE_SLOTS_LOG+:P_NUM_SLAVE_SLOTS_LOG]), .MATCH (bid_match[gen_mi_slot]), .REGION () ); end else begin : gen_no_bid_decoder assign tmp_mr_bid_target[gen_mi_slot] = 1\'b1; // All response transfers route to solo SI-slot. assign bid_match[gen_mi_slot] = 1\'b1; end axi_crossbar_v2_1_wdata_mux # // "WM": Write data Mux, per MI-slot (incl error-handler) ( .C_FAMILY (C_FAMILY), .C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS), .C_SELECT_WIDTH (P_NUM_SLAVE_SLOTS_LOG), .C_WMESG_WIDTH (P_WR_WMESG_WIDTH), .C_FIFO_DEPTH_LOG (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]) ) wdata_mux_w ( .ACLK (ACLK), .ARESET (reset), // Vector of write transfer inputs from each SI-slot\'s W-router .S_WMESG (wr_wm_wmesg), .S_WLAST (wr_wm_wlast), .S_WVALID (tmp_wm_wvalid[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]), .S_WREADY (tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]), // Write transfer output to the current MI-slot .M_WMESG (wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH]), .M_WLAST (wm_mr_wlast[gen_mi_slot]), .M_WVALID (wm_mr_wvalid[gen_mi_slot]), .M_WREADY (wm_mr_wready[gen_mi_slot]), // AW command push from AW arbiter output .S_ASELECT (aa_wm_awgrant_enc), // SI-slot selected by arbiter .S_AVALID (sa_wm_awvalid[gen_mi_slot]), .S_AREADY (sa_wm_awready[gen_mi_slot]) ); if (C_DEBUG) begin : gen_debug_w // DEBUG WRITE BEAT COUNTER always @(posedge ACLK) begin if (reset) begin debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= 0; end else begin if (mi_wvalid[gen_mi_slot] & mi_wready[gen_mi_slot]) begin if (mi_wlast[gen_mi_slot]) begin debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= 0; end else begin debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= debug_w_beat_cnt_i[gen_mi_slot*8+:8] + 1; end end end end // clocked process // DEBUG W-CHANNEL TRANSACTION SEQUENCE QUEUE axi_data_fifo_v2_1_axic_srl_fifo # ( .C_FAMILY (C_FAMILY), .C_FIFO_WIDTH (8), .C_FIFO_DEPTH_LOG (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]), .C_USE_FULL (0) ) debug_w_seq_fifo ( .ACLK (ACLK), .ARESET (reset), .S_MESG (debug_aw_trans_seq_i), .S_VALID (sa_wm_awvalid[gen_mi_slot]), .S_READY (), .M_MESG (debug_w_trans_seq_i[gen_mi_slot*8+:8]), .M_VALID (), .M_READY (mi_wvalid[gen_mi_slot] & mi_wready[gen_mi_slot] & mi_wlast[gen_mi_slot]) ); end // gen_debug_w assign wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH +: C_AXI_DATA_WIDTH]; assign wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH +: C_AXI_DATA_WIDTH/8]; assign wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8 +: C_AXI_WUSER_WIDTH]; assign wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH+(C_AXI_DATA_WIDTH/8)+C_AXI_WUSER_WIDTH +: P_AXI_WID_WIDTH]; assign st_mr_bmesg[gen_mi_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH] = { st_mr_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH], st_mr_bresp[gen_mi_slot*2+:2] }; end else begin : gen_no_mi_write assign tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0; assign bid_match[gen_mi_slot] = 1\'b0; assign wm_mr_wvalid[gen_mi_slot] = 0; assign wm_mr_wlast[gen_mi_slot] = 0; assign wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0; assign wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = 0; assign wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = 0; assign wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0; assign st_mr_bmesg[gen_mi_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH] = 0; assign tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0; assign sa_wm_awready[gen_mi_slot] = 0; end // gen_mi_write for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_trans_si // Transpose handshakes from W-router (SxM) to W-mux (MxS). assign tmp_wm_wvalid[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot] = 'b'wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot]; assign wr_tmp_wready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot]; // Transpose response enables from ID decoders (MxS) to si_transactors (SxM). assign st_tmp_bid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot]; assign st_tmp_rid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot]; end // gen_trans_si assign bready_carry[gen_mi_slot] = st_tmp_bready[gen_mi_slot]; assign rready_carry[gen_mi_slot] = st_tmp_rready[gen_mi_slot]; for (gen_si_slot=1; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_resp_carry_si assign bready_carry[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = // Generate M_BREADY if ... bready_carry[(gen_si_slot-1)*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] | // For any SI-slot (OR carry-chain across all SI-slots), ... st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot]; // The write SI transactor indicates BREADY for that MI-slot. assign rready_carry[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = // Generate M_RREADY if ... rready_carry[(gen_si_slot-1)*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] | // For any SI-slot (OR carry-chain across all SI-slots), ... st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot]; // The write SI transactor indicates RREADY for that MI-slot. end // gen_resp_carry_si assign w_cmd_push[gen_mi_slot] = mi_awvalid[gen_mi_slot] && mi_awready[gen_mi_slot] && P_M_AXI_SUPPORTS_WRITE[gen_mi_slot]; assign r_cmd_push[gen_mi_slot] = mi_arvalid[gen_mi_slot] && mi_arready[gen_mi_slot] && P_M_AXI_SUPPORTS_READ[gen_mi_slot]; assign w_cmd_pop[gen_mi_slot] = st_mr_bvalid[gen_mi_slot] && st_mr_bready[gen_mi_slot] && P_M_AXI_SUPPORTS_WRITE[gen_mi_slot]; assign r_cmd_pop[gen_mi_slot] = st_mr_rvalid[gen_mi_slot] && st_mr_rready[gen_mi_slot] && st_mr_rlast[gen_mi_slot] && P_M_AXI_SUPPORTS_READ[gen_mi_slot]; // Disqualify arbitration of SI-slot if targeted MI-slot has reached its issuing limit. assign mi_awmaxissuing[gen_mi_slot] = (w_issuing_cnt[gen_mi_slot*8 +: (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] == P_M_AXI_WRITE_ISSUING[gen_mi_slot*32 +: (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)]) & ~w_cmd_pop[gen_mi_slot]; assign mi_armaxissuing[gen_mi_slot] = (r_issuing_cnt[gen_mi_slot*8 +: (C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] == P_M_AXI_READ_ISSUING[gen_mi_slot*32 +: (C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)]) & ~r_cmd_pop[gen_mi_slot]; always @(posedge ACLK) begin if (reset) begin w_issuing_cnt[gen_mi_slot*8+:8] <= 0; // Some high-order bits remain constant 0 r_issuing_cnt[gen_mi_slot*8+:8] <= 0; // Some high-order bits remain constant 0 end else begin if (w_cmd_push[gen_mi_slot] && ~w_cmd_pop[gen_mi_slot]) begin w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] + 1; end else if (w_cmd_pop[gen_mi_slot] && ~w_cmd_push[gen_mi_slot] && (|w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)])) begin w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] - 1; end if (r_cmd_push[gen_mi_slot] && ~r_cmd_pop[gen_mi_slot]) begin r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] + 1; end else if (r_cmd_pop[gen_mi_slot] && ~r_cmd_push[gen_mi_slot] && (|r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)])) begin r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] - 1; end end end // Clocked process // Reg-slice must break combinatorial path from M_BID and M_RID inputs to M_BREADY and M_RREADY outputs. // (See m_rready_i and m_resp_en combinatorial assignments in si_transactor.) // Reg-slice incurs +1 latency, but no bubble-cycles. axi_register_slice_v2_1_axi_register_slice # // "MR": MI-side R/B-channel Reg-slice, per MI-slot (pass-through if only 1 SI-slot configured) ( .C_FAMILY (C_FAMILY), .C_AXI_PROTOCOL ((C_AXI_PROTOCOL == P_AXI3) ? P_AXI3 : P_AXI4), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_AXI_ADDR_WIDTH (1), .C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH), .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS), .C_AXI_AWUSER_WIDTH (1), .C_AXI_ARUSER_WIDTH (1), .C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH), .C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH), .C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH), .C_REG_CONFIG_AW (P_BYPASS), .C_REG_CONFIG_AR (P_BYPASS), .C_REG_CONFIG_W (P_BYPASS), .C_REG_CONFIG_R (P_M_AXI_SUPPORTS_READ[gen_mi_slot] ? P_FWD_REV : P_BYPASS), .C_REG_CONFIG_B (P_M_AXI_SUPPORTS_WRITE[gen_mi_slot] ? P_SIMPLE : P_BYPASS) ) reg_slice_mi ( .aresetn (ARESETN), .aclk (ACLK), .s_axi_awid ({C_AXI_ID_WIDTH{1\'b0}}), .s_axi_awaddr ({1{1\'b0}}), .s_axi_awlen ({((C_AXI_PROTOCOL == P_AXI3) ? 4 : 8){1\'b0}}), .s_axi_awsize ({3{1\'b0}}), .s_axi_awburst ({2{1\'b0}}), .s_axi_awlock ({((C_AXI_PROTOCOL == P_AXI3) ? 2 : 1){1\'b0}}), .s_axi_awcache ({4{1\'b0}}), .s_axi_awprot ({3{1\'b0}}), .s_axi_awregion ({4{1\'b0}}), .s_axi_awqos ({4{1\'b0}}), .s_axi_awuser ({1{1\'b0}}), .s_axi_awvalid ({1{1\'b0}}), .s_axi_awready (), .s_axi_wid (wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .s_axi_wdata (wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]), .s_axi_wstrb (wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8]), .s_axi_wlast (wm_mr_wlast[gen_mi_slot]), .s_axi_wuser (wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]), .s_axi_wvalid (wm_mr_wvalid[gen_mi_slot]), .s_axi_wready (wm_mr_wready[gen_mi_slot]), .s_axi_bid (st_mr_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] ), .s_axi_bresp (st_mr_bresp[gen_mi_slot*2+:2] ), .s_axi_buser (st_mr_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] ), .s_axi_bvalid (st_mr_bvalid[gen_mi_slot*1+:1] ), .s_axi_bready (st_mr_bready[gen_mi_slot*1+:1] ), .s_axi_arid ({C_AXI_ID_WIDTH{1\'b0}}), .s_axi_araddr ({1{1\'b0}}), .s_axi_arlen ({((C_AXI_PROTOCOL == P_AXI3) ? 4 : 8){1\'b0}}), .s_axi_arsize ({3{1\'b0}}), .s_axi_arburst ({2{1\'b0}}), .s_axi_arlock ({((C_AXI_PROTOCOL == P_AXI3) ? 2 : 1){1\'b0}}), .s_axi_arcache ({4{1\'b0}}), .s_axi_arprot ({3{1\'b0}}), .s_axi_arregion ({4{1\'b0}}), .s_axi_arqos ({4{1\'b0}}), .s_axi_aruser ({1{1\'b0}}), .s_axi_arvalid ({1{1\'b0}}), .s_axi_arready (), .s_axi_rid (st_mr_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] ), .s_axi_rdata (st_mr_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] ), .s_axi_rresp (st_mr_rresp[gen_mi_slot*2+:2] ), .s_axi_rlast (st_mr_rlast[gen_mi_slot*1+:1] ), .s_axi_ruser (st_mr_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] ), .s_axi_rvalid (st_mr_rvalid[gen_mi_slot*1+:1] ), .s_axi_rready (st_mr_rready[gen_mi_slot*1+:1] ), .m_axi_awid (), .m_axi_awaddr (), .m_axi_awlen (), .m_axi_awsize (), .m_axi_awburst (), .m_axi_awlock (), .m_axi_awcache (), .m_axi_awprot (), .m_axi_awregion (), .m_axi_awqos (), .m_axi_awuser (), .m_axi_awvalid (), .m_axi_awready ({1{1\'b0}}), .m_axi_wid (mi_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .m_axi_wdata (mi_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]), .m_axi_wstrb (mi_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8]), .m_axi_wlast (mi_wlast[gen_mi_slot]), .m_axi_wuser (mi_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]), .m_axi_wvalid (mi_wvalid[gen_mi_slot]), .m_axi_wready (mi_wready[gen_mi_slot]), .m_axi_bid (mi_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] ), .m_axi_bresp (mi_bresp[gen_mi_slot*2+:2] ), .m_axi_buser (mi_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] ), .m_axi_bvalid (mi_bvalid[gen_mi_slot*1+:1] ), .m_axi_bready (mi_bready[gen_mi_slot*1+:1] ), .m_axi_arid (), .m_axi_araddr (), .m_axi_arlen (), .m_axi_arsize (), .m_axi_arburst (), .m_axi_arlock (), .m_axi_arcache (), .m_axi_arprot (), .m_axi_arregion (), .m_axi_arqos (), .m_axi_aruser (), .m_axi_arvalid (), .m_axi_arready ({1{1\'b0}}), .m_axi_rid (mi_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] ), .m_axi_rdata (mi_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] ), .m_axi_rresp (mi_rresp[gen_mi_slot*2+:2] ), .m_axi_rlast (mi_rlast[gen_mi_slot*1+:1] ), .m_axi_ruser (mi_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] ), .m_axi_rvalid (mi_rvalid[gen_mi_slot*1+:1] ), .m_axi_rready (mi_rready[gen_mi_slot*1+:1] ) ); end // gen_master_slots (Next gen_mi_slot) // Highest row of *ready_carry contains accumulated OR across all SI-slots, for each MI-slot. assign st_mr_bready = bready_carry[(C_NUM_SLAVE_SLOTS-1)*(C_NUM_MASTER_SLOTS+1) +: C_NUM_MASTER_SLOTS+1]; assign st_mr_rready = rready_carry[(C_NUM_SLAVE_SLOTS-1)*(C_NUM_MASTER_SLOTS+1) +: C_NUM_MASTER_SLOTS+1]; // Assign MI-side B, R and W channel ports (exclude error handler signals). assign mi_bid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] = M_AXI_BID; assign mi_bvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_BVALID; assign mi_bresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_BRESP; assign mi_buser[0+:C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH] = M_AXI_BUSER; assign M_AXI_BREADY = mi_bready[0+:C_NUM_MASTER_SLOTS]; assign mi_rid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] = M_AXI_RID; assign mi_rlast[0+:C_NUM_MASTER_SLOTS] = M_AXI_RLAST; assign mi_rvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_RVALID; assign mi_rresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_RRESP; assign mi_ruser[0+:C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH] = M_AXI_RUSER; assign mi_rdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH] = M_AXI_RDATA; assign M_AXI_RREADY = mi_rready[0+:C_NUM_MASTER_SLOTS]; assign M_AXI_WLAST = mi_wlast[0+:C_NUM_MASTER_SLOTS]; assign M_AXI_WVALID = mi_wvalid[0+:C_NUM_MASTER_SLOTS]; assign M_AXI_WUSER = mi_wuser[0+:C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH]; assign M_AXI_WID = (C_AXI_PROTOCOL == P_AXI3) ? mi_wid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] : 0; assign M_AXI_WDATA = mi_wdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH]; assign M_AXI_WSTRB = mi_wstrb[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8]; assign mi_wready[0+:C_NUM_MASTER_SLOTS] = M_AXI_WREADY; axi_crossbar_v2_1_addr_arbiter # // "AA": Addr Arbiter (AW channel) ( .C_FAMILY (C_FAMILY), .C_NUM_M (C_NUM_MASTER_SLOTS+1), .C_NUM_S (C_NUM_SLAVE_SLOTS), .C_NUM_S_LOG (P_NUM_SLAVE_SLOTS_LOG), .C_MESG_WIDTH (P_AA_AWMESG_WIDTH), .C_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY) ) addr_arbiter_aw ( .ACLK (ACLK), .ARESET (reset), // Vector of SI-side AW command request inputs .S_MESG (tmp_aa_awmesg), .S_TARGET_HOT (st_aa_awtarget_hot), .S_VALID (ss_aa_awvalid), .S_VALID_QUAL (st_aa_awvalid_qual), .S_READY (ss_aa_awready), // Granted AW command output .M_MESG (aa_mi_awmesg), .M_TARGET_HOT (aa_mi_awtarget_hot), // MI-slot targeted by granted command .M_GRANT_ENC (aa_wm_awgrant_enc), // SI-slot index of granted command .M_VALID (aa_sa_awvalid), .M_READY (aa_sa_awready), .ISSUING_LIMIT (mi_awmaxissuing) ); // Broadcast AW transfer payload to all MI-slots assign M_AXI_AWID = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[0+:C_AXI_ID_WIDTH]}}; assign M_AXI_AWADDR = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+:C_AXI_ADDR_WIDTH]}}; assign M_AXI_AWLEN = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]}}; assign M_AXI_AWSIZE = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +:3]}}; assign M_AXI_AWLOCK = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +:2]}}; assign M_AXI_AWPROT = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +:3]}}; assign M_AXI_AWREGION = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +:4]}}; assign M_AXI_AWBURST = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4 +:2]}}; assign M_AXI_AWCACHE = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2 +:4]}}; assign M_AXI_AWQOS = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4 +:4]}}; assign M_AXI_AWUSER = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4+4 +:C_AXI_AWUSER_WIDTH]}}; axi_crossbar_v2_1_addr_arbiter # // "AA": Addr Arbiter (AR channel) ( .C_FAMILY (C_FAMILY), .C_NUM_M (C_NUM_MASTER_SLOTS+1), .C_NUM_S (C_NUM_SLAVE_SLOTS), .C_NUM_S_LOG (P_NUM_SLAVE_SLOTS_LOG), .C_MESG_WIDTH (P_AA_ARMESG_WIDTH), .C_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY) ) addr_arbiter_ar ( .ACLK (ACLK), .ARESET (reset), // Vector of SI-side AR command request inputs .S_MESG (tmp_aa_armesg), .S_TARGET_HOT (st_aa_artarget_hot), .S_VALID_QUAL (st_aa_arvalid_qual), .S_VALID (st_aa_arvalid), .S_READY (st_aa_arready), // Granted AR command output .M_MESG (aa_mi_armesg), .M_TARGET_HOT (aa_mi_artarget_hot), // MI-slot targeted by granted command .M_GRANT_ENC (aa_mi_argrant_enc), .M_VALID (aa_mi_arvalid), // SI-slot index of granted command .M_READY (aa_mi_arready), .ISSUING_LIMIT (mi_armaxissuing) ); if (C_DEBUG) begin : gen_debug_trans_seq // DEBUG WRITE TRANSACTION SEQUENCE COUNTER always @(posedge ACLK) begin if (reset) begin debug_aw_trans_seq_i <= 1; end else begin if (aa_sa_awvalid && aa_sa_awready) begin debug_aw_trans_seq_i <= debug_aw_trans_seq_i + 1; end end end // DEBUG READ TRANSACTION SEQUENCE COUNTER always @(posedge ACLK) begin if (reset) begin debug_ar_trans_seq_i <= 1; end else begin if (aa_mi_arvalid && aa_mi_arready) begin debug_ar_trans_seq_i <= debug_ar_trans_seq_i + 1; end end end end // gen_debug_trans_seq // Broadcast AR transfer payload to all MI-slots assign M_AXI_ARID = {C_NUM_MASTER_SLOTS{aa_mi_armesg[0+:C_AXI_ID_WIDTH]}}; assign M_AXI_ARADDR = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+:C_AXI_ADDR_WIDTH]}}; assign M_AXI_ARLEN = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]}}; assign M_AXI_ARSIZE = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +:3]}}; assign M_AXI_ARLOCK = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +:2]}}; assign M_AXI_ARPROT = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +:3]}}; assign M_AXI_ARREGION = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +:4]}}; assign M_AXI_ARBURST = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4 +:2]}}; assign M_AXI_ARCACHE = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2 +:4]}}; assign M_AXI_ARQOS = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4 +:4]}}; assign M_AXI_ARUSER = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4+4 +:C_AXI_ARUSER_WIDTH]}}; // AW arbiter command transfer completes upon completion of both M-side AW-channel transfer and W-mux address acceptance (command push). axi_crossbar_v2_1_splitter # // "SA": Splitter for Write Addr Arbiter ( .C_NUM_M (2) ) splitter_aw_mi ( .ACLK (ACLK), .ARESET (reset), .S_VALID (aa_sa_awvalid), .S_READY (aa_sa_awready), .M_VALID ({mi_awvalid_en, sa_wm_awvalid_en}), .M_READY ({mi_awready_mux, sa_wm_awready_mux}) ); assign mi_awvalid = aa_mi_awtarget_hot & {C_NUM_MASTER_SLOTS+1{mi_awvalid_en}}; assign mi_awready_mux = |(aa_mi_awtarget_hot & mi_awready); assign M_AXI_AWVALID = mi_awvalid[0+:C_NUM_MASTER_SLOTS]; // Slot C_NUM_MASTER_SLOTS+1 is the error handler assign mi_awready[0+:C_NUM_MASTER_SLOTS] = M_AXI_AWREADY; assign sa_wm_awvalid = aa_mi_awtarget_hot & {C_NUM_MASTER_SLOTS+1{sa_wm_awvalid_en}}; assign sa_wm_awready_mux = |(aa_mi_awtarget_hot & sa_wm_awready); assign mi_arvalid = aa_mi_artarget_hot & {C_NUM_MASTER_SLOTS+1{aa_mi_arvalid}}; assign aa_mi_arready = |(aa_mi_artarget_hot & mi_arready); assign M_AXI_ARVALID = mi_arvalid[0+:C_NUM_MASTER_SLOTS]; // Slot C_NUM_MASTER_SLOTS+1 is the error handler assign mi_arready[0+:C_NUM_MASTER_SLOTS] = M_AXI_ARREADY; // MI-slot # C_NUM_MASTER_SLOTS is the error handler if (C_RANGE_CHECK) begin : gen_decerr_slave axi_crossbar_v2_1_decerr_slave # ( .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH), .C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH), .C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH), .C_AXI_PROTOCOL (C_AXI_PROTOCOL), .C_RESP (P_DECERR) ) decerr_slave_inst ( .S_AXI_ACLK (ACLK), .S_AXI_ARESET (reset), .S_AXI_AWID (aa_mi_awmesg[0+:C_AXI_ID_WIDTH]), .S_AXI_AWVALID (mi_awvalid[C_NUM_MASTER_SLOTS]), .S_AXI_AWREADY (mi_awready[C_NUM_MASTER_SLOTS]), .S_AXI_WLAST (mi_wlast[C_NUM_MASTER_SLOTS]), .S_AXI_WVALID (mi_wvalid[C_NUM_MASTER_SLOTS]), .S_AXI_WREADY (mi_wready[C_NUM_MASTER_SLOTS]), .S_AXI_BID (mi_bid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .S_AXI_BRESP (mi_bresp[C_NUM_MASTER_SLOTS*2+:2]), .S_AXI_BUSER (mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]), .S_AXI_BVALID (mi_bvalid[C_NUM_MASTER_SLOTS]), .S_AXI_BREADY (mi_bready[C_NUM_MASTER_SLOTS]), .S_AXI_ARID (aa_mi_armesg[0+:C_AXI_ID_WIDTH]), .S_AXI_ARLEN (aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]), .S_AXI_ARVALID (mi_arvalid[C_NUM_MASTER_SLOTS]), .S_AXI_ARREADY (mi_arready[C_NUM_MASTER_SLOTS]), .S_AXI_RID (mi_rid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .S_AXI_RDATA (mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]), .S_AXI_RRESP (mi_rresp[C_NUM_MASTER_SLOTS*2+:2]), .S_AXI_RUSER (mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]), .S_AXI_RLAST (mi_rlast[C_NUM_MASTER_SLOTS]), .S_AXI_RVALID (mi_rvalid[C_NUM_MASTER_SLOTS]), .S_AXI_RREADY (mi_rready[C_NUM_MASTER_SLOTS]) ); end else begin : gen_no_decerr_slave assign mi_awready[C_NUM_MASTER_SLOTS] = 1\'b0; assign mi_wready[C_NUM_MASTER_SLOTS] = 1\'b0; assign mi_arready[C_NUM_MASTER_SLOTS] = 1\'b0; assign mi_awready[C_NUM_MASTER_SLOTS] = 1\'b0; assign mi_awready[C_NUM_MASTER_SLOTS] = 1\'b0; assign mi_bid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0; assign mi_bresp[C_NUM_MASTER_SLOTS*2+:2] = 0; assign mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = 0; assign mi_bvalid[C_NUM_MASTER_SLOTS] = 1\'b0; assign mi_rid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0; assign mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0; assign mi_rresp[C_NUM_MASTER_SLOTS*2+:2] = 0; assign mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = 0; assign mi_rlast[C_NUM_MASTER_SLOTS] = 1\'b0; assign mi_rvalid[C_NUM_MASTER_SLOTS] = 1\'b0; end // gen_decerr_slave endgenerate endmodule `default_nettype wire
// -- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // AXI data fifo module: // 5-channel memory-mapped AXI4 interfaces. // SRL or BRAM based FIFO on AXI W and/or R channels. // FIFO to accommodate various data flow rates through the AXI interconnect // // Verilog-standard: Verilog 2001 //----------------------------------------------------------------------------- // // Structure: // axi_data_fifo // fifo_generator // //----------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module axi_data_fifo_v2_1_axi_data_fifo # ( parameter C_FAMILY = "virtex7", parameter integer C_AXI_PROTOCOL = 0, parameter integer C_AXI_ID_WIDTH = 4, parameter integer C_AXI_ADDR_WIDTH = 32, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, parameter integer C_AXI_AWUSER_WIDTH = 1, parameter integer C_AXI_ARUSER_WIDTH = 1, parameter integer C_AXI_WUSER_WIDTH = 1, parameter integer C_AXI_RUSER_WIDTH = 1, parameter integer C_AXI_BUSER_WIDTH = 1, parameter integer C_AXI_WRITE_FIFO_DEPTH = 0, // Range: (0, 32, 512) parameter C_AXI_WRITE_FIFO_TYPE = "lut", // "lut" = LUT (SRL) based, // "bram" = BRAM based parameter integer C_AXI_WRITE_FIFO_DELAY = 0, // 0 = No, 1 = Yes // Indicates whether AWVALID and WVALID assertion is delayed until: // a. the corresponding WLAST is stored in the FIFO, or // b. no WLAST is stored and the FIFO is full. // 0 means AW channel is pass-through and // WVALID is asserted whenever FIFO is not empty. parameter integer C_AXI_READ_FIFO_DEPTH = 0, // Range: (0, 32, 512) parameter C_AXI_READ_FIFO_TYPE = "lut", // "lut" = LUT (SRL) based, // "bram" = BRAM based parameter integer C_AXI_READ_FIFO_DELAY = 0) // 0 = No, 1 = Yes // Indicates whether ARVALID assertion is delayed until the // the remaining vacancy of the FIFO is at least the burst length // as indicated by ARLEN. // 0 means AR channel is pass-through. // System Signals (input wire aclk, input wire aresetn, // Slave Interface Write Address Ports input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid, input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen, input wire [3-1:0] s_axi_awsize, input wire [2-1:0] s_axi_awburst, input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock, input wire [4-1:0] s_axi_awcache, input wire [3-1:0] s_axi_awprot, input wire [4-1:0] s_axi_awregion, input wire [4-1:0] s_axi_awqos, input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser, input wire s_axi_awvalid, output wire s_axi_awready, // Slave Interface Write Data Ports input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid, input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata, input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, input wire s_axi_wlast, input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser, input wire s_axi_wvalid, output wire s_axi_wready, // Slave Interface Write Response Ports output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid, output wire [2-1:0] s_axi_bresp, output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser, output wire s_axi_bvalid, input wire s_axi_bready, // Slave Interface Read Address Ports input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid, input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr, input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen, input wire [3-1:0] s_axi_arsize, input wire [2-1:0] s_axi_arburst, input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock, input wire [4-1:0] s_axi_arcache, input wire [3-1:0] s_axi_arprot, input wire [4-1:0] s_axi_arregion, input wire [4-1:0] s_axi_arqos, input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser, input wire s_axi_arvalid, output wire s_axi_arready, // Slave Interface Read Data Ports output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid, output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata, output wire [2-1:0] s_axi_rresp, output wire s_axi_rlast, output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser, output wire s_axi_rvalid, input wire s_axi_rready, // Master Interface Write Address Port output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid, output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen, output wire [3-1:0] m_axi_awsize, output wire [2-1:0] m_axi_awburst, output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock, output wire [4-1:0] m_axi_awcache, output wire [3-1:0] m_axi_awprot, output wire [4-1:0] m_axi_awregion, output wire [4-1:0] m_axi_awqos, output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser, output wire m_axi_awvalid, input wire m_axi_awready, // Master Interface Write Data Ports output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid, output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata, output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb, output wire m_axi_wlast, output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser, output wire m_axi_wvalid, input wire m_axi_wready, // Master Interface Write Response Ports input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid, input wire [2-1:0] m_axi_bresp, input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser, input wire m_axi_bvalid, output wire m_axi_bready, // Master Interface Read Address Port output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid, output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr, output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen, output wire [3-1:0] m_axi_arsize, output wire [2-1:0] m_axi_arburst, output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock, output wire [4-1:0] m_axi_arcache, output wire [3-1:0] m_axi_arprot, output wire [4-1:0] m_axi_arregion, output wire [4-1:0] m_axi_arqos, output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser, output wire m_axi_arvalid, input wire m_axi_arready, // Master Interface Read Data Ports input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid, input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata, input wire [2-1:0] m_axi_rresp, input wire m_axi_rlast, input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser, input wire m_axi_rvalid, output wire m_axi_rready); localparam integer P_WIDTH_RACH = 4+4+3+4+2+3+((C_AXI_PROTOCOL==1)?6:9)+C_AXI_ADDR_WIDTH+C_AXI_ID_WIDTH+C_AXI_ARUSER_WIDTH; localparam integer P_WIDTH_WACH = 4+4+3+4+2+3+((C_AXI_PROTOCOL==1)?6:9)+C_AXI_ADDR_WIDTH+C_AXI_ID_WIDTH+C_AXI_AWUSER_WIDTH; localparam integer P_WIDTH_RDCH = 1 + 2 + C_AXI_DATA_WIDTH + C_AXI_ID_WIDTH + C_AXI_RUSER_WIDTH; localparam integer P_WIDTH_WDCH = 1+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8+((C_AXI_PROTOCOL==1)?C_AXI_ID_WIDTH:0)+C_AXI_WUSER_WIDTH; localparam integer P_WIDTH_WRCH = 2 + C_AXI_ID_WIDTH + C_AXI_BUSER_WIDTH; localparam P_PRIM_FIFO_TYPE = "512x72" ; localparam integer P_AXI4 = 0; localparam integer P_AXI3 = 1; localparam integer P_AXILITE = 2; localparam integer P_WRITE_FIFO_DEPTH_LOG = (C_AXI_WRITE_FIFO_DEPTH > 1) ? f_ceil_log2(C_AXI_WRITE_FIFO_DEPTH) : 1; localparam integer P_READ_FIFO_DEPTH_LOG = (C_AXI_READ_FIFO_DEPTH > 1) ? f_ceil_log2(C_AXI_READ_FIFO_DEPTH) : 1; // Ceiling of log2(x) function integer f_ceil_log2 ( input integer x ); integer acc; begin acc=0; while ((2**acc) < x) acc = acc + 1; f_ceil_log2 = acc; end endfunction generate if (((C_AXI_WRITE_FIFO_DEPTH == 0) && (C_AXI_READ_FIFO_DEPTH == 0)) || (C_AXI_PROTOCOL == P_AXILITE)) begin : gen_bypass assign m_axi_awid = s_axi_awid; assign m_axi_awaddr = s_axi_awaddr; assign m_axi_awlen = s_axi_awlen; assign m_axi_awsize = s_axi_awsize; assign m_axi_awburst = s_axi_awburst; assign m_axi_awlock = s_axi_awlock; assign m_axi_awcache = s_axi_awcache; assign m_axi_awprot = s_axi_awprot; assign m_axi_awregion = s_axi_awregion; assign m_axi_awqos = s_axi_awqos; assign m_axi_awuser = s_axi_awuser; assign m_axi_awvalid = s_axi_awvalid; assign s_axi_awready = m_axi_awready; assign m_axi_wid = s_axi_wid; assign m_axi_wdata = s_axi_wdata; assign m_axi_wstrb = s_axi_wstrb; assign m_axi_wlast = s_axi_wlast; assign m_axi_wuser = s_axi_wuser; assign m_axi_wvalid = s_axi_wvalid; assign s_axi_wready = m_axi_wready; assign s_axi_bid = m_axi_bid; assign s_axi_bresp = m_axi_bresp; assign s_axi_buser = m_axi_buser; assign s_axi_bvalid = m_axi_bvalid; assign m_axi_bready = s_axi_bready; assign m_axi_arid = s_axi_arid; assign m_axi_araddr = s_axi_araddr; assign m_axi_arlen = s_axi_arlen; assign m_axi_arsize = s_axi_arsize; assign m_axi_arburst = s_axi_arburst; assign m_axi_arlock = s_axi_arlock; assign m_axi_arcache = s_axi_arcache; assign m_axi_arprot = s_axi_arprot; assign m_axi_arregion = s_axi_arregion; assign m_axi_arqos = s_axi_arqos; assign m_axi_aruser = s_axi_aruser; assign m_axi_arvalid = s_axi_arvalid; assign s_axi_arready = m_axi_arready; assign s_axi_rid = m_axi_rid; assign s_axi_rdata = m_axi_rdata; assign s_axi_rresp = m_axi_rresp; assign s_axi_rlast = m_axi_rlast; assign s_axi_ruser = m_axi_ruser; assign s_axi_rvalid = m_axi_rvalid; assign m_axi_rready = s_axi_rready; end else begin : gen_fifo wire [4-1:0] s_axi_awregion_i; wire [4-1:0] s_axi_arregion_i; wire [4-1:0] m_axi_awregion_i; wire [4-1:0] m_axi_arregion_i; wire [C_AXI_ID_WIDTH-1:0] s_axi_wid_i; wire [C_AXI_ID_WIDTH-1:0] m_axi_wid_i; assign s_axi_awregion_i = (C_AXI_PROTOCOL == P_AXI3) ? 4\'b0 : s_axi_awregion; assign s_axi_arregion_i = (C_AXI_PROTOCOL == P_AXI3) ? 4\'b0 : s_axi_arregion; assign m_axi_awregion = (C_AXI_PROTOCOL == P_AXI3) ? 4\'b0 : m_axi_awregion_i; assign m_axi_arregion = (C_AXI_PROTOCOL == P_AXI3) ? 4\'b0 : m_axi_arregion_i; assign s_axi_wid_i = (C_AXI_PROTOCOL == P_AXI3) ? s_axi_wid : {C_AXI_ID_WIDTH{1\'b0}}; assign m_axi_wid = (C_AXI_PROTOCOL == P_AXI3) ? m_axi_wid_i : {C_AXI_ID_WIDTH{1\'b0}}; fifo_generator_v12_0 #( .C_INTERFACE_TYPE(2), .C_AXI_TYPE((C_AXI_PROTOCOL == P_AXI4) ? 1 : 3), .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH), .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH), .C_HAS_AXI_ID(1), .C_AXI_LEN_WIDTH((C_AXI_PROTOCOL == P_AXI4) ? 8 : 4), .C_AXI_LOCK_WIDTH((C_AXI_PROTOCOL == P_AXI4) ? 1 : 2), .C_HAS_AXI_ARUSER(1), .C_HAS_AXI_AWUSER(1), .C_HAS_AXI_BUSER(1), .C_HAS_AXI_RUSER(1), .C_HAS_AXI_WUSER(1), .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH), .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH), .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH), .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH), .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH), .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH), .C_DIN_WIDTH_RACH(P_WIDTH_RACH), .C_DIN_WIDTH_RDCH(P_WIDTH_RDCH), .C_DIN_WIDTH_WACH(P_WIDTH_WACH), .C_DIN_WIDTH_WDCH(P_WIDTH_WDCH), .C_DIN_WIDTH_WRCH(P_WIDTH_WDCH), .C_RACH_TYPE(((C_AXI_READ_FIFO_DEPTH != 0) && C_AXI_READ_FIFO_DELAY) ? 0 : 2), .C_WACH_TYPE(((C_AXI_WRITE_FIFO_DEPTH != 0) && C_AXI_WRITE_FIFO_DELAY) ? 0 : 2), .C_WDCH_TYPE((C_AXI_WRITE_FIFO_DEPTH != 0) ? 0 : 2), .C_RDCH_TYPE((C_AXI_READ_FIFO_DEPTH != 0) ? 0 : 2), .C_WRCH_TYPE(2), .C_COMMON_CLOCK(1), .C_ADD_NGC_CONSTRAINT(0), .C_APPLICATION_TYPE_AXIS(0), .C_APPLICATION_TYPE_RACH(C_AXI_READ_FIFO_DELAY ? 1 : 0), .C_APPLICATION_TYPE_RDCH(0), .C_APPLICATION_TYPE_WACH(C_AXI_WRITE_FIFO_DELAY ? 1 : 0), .C_APPLICATION_TYPE_WDCH(0), .C_APPLICATION_TYPE_WRCH(0), .C_AXIS_TDATA_WIDTH(64), .C_AXIS_TDEST_WIDTH(4), .C_AXIS_TID_WIDTH(8), .C_AXIS_TKEEP_WIDTH(4), .C_AXIS_TSTRB_WIDTH(4), .C_AXIS_TUSER_WIDTH(4), .C_AXIS_TYPE(0), .C_COUNT_TYPE(0), .C_DATA_COUNT_WIDTH(10), .C_DEFAULT_VALUE("BlankString"), .C_DIN_WIDTH(18), .C_DIN_WIDTH_AXIS(1), .C_DOUT_RST_VAL("0"), .C_DOUT_WIDTH(18), .C_ENABLE_RLOCS(0), .C_ENABLE_RST_SYNC(1), .C_ERROR_INJECTION_TYPE(0), .C_ERROR_INJECTION_TYPE_AXIS(0), .C_ERROR_INJECTION_TYPE_RACH(0), .C_ERROR_INJECTION_TYPE_RDCH(0), .C_ERROR_INJECTION_TYPE_WACH(0), .C_ERROR_INJECTION_TYPE_WDCH(0), .C_ERROR_INJECTION_TYPE_WRCH(0), .C_FAMILY(C_FAMILY), .C_FULL_FLAGS_RST_VAL(1), .C_HAS_ALMOST_EMPTY(0), .C_HAS_ALMOST_FULL(0), .C_HAS_AXI_RD_CHANNEL(1), .C_HAS_AXI_WR_CHANNEL(1), .C_HAS_AXIS_TDATA(0), .C_HAS_AXIS_TDEST(0), .C_HAS_AXIS_TID(0), .C_HAS_AXIS_TKEEP(0), .C_HAS_AXIS_TLAST(0), .C_HAS_AXIS_TREADY(1), .C_HAS_AXIS_TSTRB(0), .C_HAS_AXIS_TUSER(0), .C_HAS_BACKUP(0), .C_HAS_DATA_COUNT(0), .C_HAS_DATA_COUNTS_AXIS(0), .C_HAS_DATA_COUNTS_RACH(0), .C_HAS_DATA_COUNTS_RDCH(0), .C_HAS_DATA_COUNTS_WACH(0), .C_HAS_DATA_COUNTS_WDCH(0), .C_HAS_DATA_COUNTS_WRCH(0), .C_HAS_INT_CLK(0), .C_HAS_MASTER_CE(0), .C_HAS_MEMINIT_FILE(0), .C_HAS_OVERFLOW(0), .C_HAS_PROG_FLAGS_AXIS(0), .C_HAS_PROG_FLAGS_RACH(0), .C_HAS_PROG_FLAGS_RDCH(0), .C_HAS_PROG_FLAGS_WACH(0), .C_HAS_PROG_FLAGS_WDCH(0), .C_HAS_PROG_FLAGS_WRCH(0), .C_HAS_RD_DATA_COUNT(0), .C_HAS_RD_RST(0), .C_HAS_RST(1), .C_HAS_SLAVE_CE(0), .C_HAS_SRST(0), .C_HAS_UNDERFLOW(0), .C_HAS_VALID(0), .C_HAS_WR_ACK(0), .C_HAS_WR_DATA_COUNT(0), .C_HAS_WR_RST(0), .C_IMPLEMENTATION_TYPE(0), .C_IMPLEMENTATION_TYPE_AXIS(1), .C_IMPLEMENTATION_TYPE_RACH(2), .C_IMPLEMENTATION_TYPE_RDCH((C_AXI_READ_FIFO_TYPE == "bram") ? 1 : 2), .C_IMPLEMENTATION_TYPE_WACH(2), .C_IMPLEMENTATION_TYPE_WDCH((C_AXI_WRITE_FIFO_TYPE == "bram") ? 1 : 2), .C_IMPLEMENTATION_TYPE_WRCH(2), .C_INIT_WR_PNTR_VAL(0), .C_MEMORY_TYPE(1), .C_MIF_FILE_NAME("BlankString"), .C_MSGON_VAL(1), .C_OPTIMIZATION_MODE(0), .C_OVERFLOW_LOW(0), .C_PRELOAD_LATENCY(1), .C_PRELOAD_REGS(0), .C_PRIM_FIFO_TYPE(P_PRIM_FIFO_TYPE), .C_PROG_EMPTY_THRESH_ASSERT_VAL(2), .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022), .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(30), .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(510), .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(30), .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(510), .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(14), .C_PROG_EMPTY_THRESH_NEGATE_VAL(3), .C_PROG_EMPTY_TYPE(0), .C_PROG_EMPTY_TYPE_AXIS(5), .C_PROG_EMPTY_TYPE_RACH(5), .C_PROG_EMPTY_TYPE_RDCH(5), .C_PROG_EMPTY_TYPE_WACH(5), .C_PROG_EMPTY_TYPE_WDCH(5), .C_PROG_EMPTY_TYPE_WRCH(5), .C_PROG_FULL_THRESH_ASSERT_VAL(1022), .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023), .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(31), .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(511), .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(31), .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(511), .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15), .C_PROG_FULL_THRESH_NEGATE_VAL(1021), .C_PROG_FULL_TYPE(0), .C_PROG_FULL_TYPE_AXIS(5), .C_PROG_FULL_TYPE_RACH(5), .C_PROG_FULL_TYPE_RDCH(5), .C_PROG_FULL_TYPE_WACH(5), .C_PROG_FULL_TYPE_WDCH(5), .C_PROG_FULL_TYPE_WRCH(5), .C_RD_DATA_COUNT_WIDTH(10), .C_RD_DEPTH(1024), .C_RD_FREQ(1), .C_RD_PNTR_WIDTH(10), .C_REG_SLICE_MODE_AXIS(0), .C_REG_SLICE_MODE_RACH(0), .C_REG_SLICE_MODE_RDCH(0), .C_REG_SLICE_MODE_WACH(0), .C_REG_SLICE_MODE_WDCH(0), .C_REG_SLICE_MODE_WRCH(0), .C_UNDERFLOW_LOW(0), .C_USE_COMMON_OVERFLOW(0), .C_USE_COMMON_UNDERFLOW(0), .C_USE_DEFAULT_SETTINGS(0), .C_USE_DOUT_RST(1), .C_USE_ECC(0), .C_USE_ECC_AXIS(0), .C_USE_ECC_RACH(0), .C_USE_ECC_RDCH(0), .C_USE_ECC_WACH(0), .C_USE_ECC_WDCH(0), .C_USE_ECC_WRCH(0), .C_USE_EMBEDDED_REG(0), .C_USE_FIFO16_FLAGS(0), .C_USE_FWFT_DATA_COUNT(0), .C_VALID_LOW(0), .C_WR_ACK_LOW(0), .C_WR_DATA_COUNT_WIDTH(10), .C_WR_DEPTH(1024), .C_WR_DEPTH_AXIS(1024), .C_WR_DEPTH_RACH(32), .C_WR_DEPTH_RDCH(C_AXI_READ_FIFO_DEPTH), .C_WR_DEPTH_WACH(32), .C_WR_DEPTH_WDCH(C_AXI_WRITE_FIFO_DEPTH), .C_WR_DEPTH_WRCH(16), .C_WR_FREQ(1), .C_WR_PNTR_WIDTH(10), .C_WR_PNTR_WIDTH_AXIS(10), .C_WR_PNTR_WIDTH_RACH(5), .C_WR_PNTR_WIDTH_RDCH((C_AXI_READ_FIFO_DEPTH> 1) ? f_ceil_log2(C_AXI_READ_FIFO_DEPTH) : 1), .C_WR_PNTR_WIDTH_WACH(5), .C_WR_PNTR_WIDTH_WDCH((C_AXI_WRITE_FIFO_DEPTH > 1) ? f_ceil_log2(C_AXI_WRITE_FIFO_DEPTH) : 1), .C_WR_PNTR_WIDTH_WRCH(4), .C_WR_RESPONSE_LATENCY(1) ) fifo_gen_inst ( .s_aclk(aclk), .s_aresetn(aresetn), .s_axi_awid(s_axi_awid), .s_axi_awaddr(s_axi_awaddr), .s_axi_awlen(s_axi_awlen), .s_axi_awsize(s_axi_awsize), .s_axi_awburst(s_axi_awburst), .s_axi_awlock(s_axi_awlock), .s_axi_awcache(s_axi_awcache), .s_axi_awprot(s_axi_awprot), .s_axi_awqos(s_axi_awqos), .s_axi_awregion(s_axi_awregion_i), .s_axi_awuser(s_axi_awuser), .s_axi_awvalid(s_axi_awvalid), .s_axi_awready(s_axi_awready), .s_axi_wid(s_axi_wid_i), .s_axi_wdata(s_axi_wdata), .s_axi_wstrb(s_axi_wstrb), .s_axi_wlast(s_axi_wlast), .s_axi_wvalid(s_axi_wvalid), .s_axi_wready(s_axi_wready), .s_axi_bid(s_axi_bid), .s_axi_bresp(s_axi_bresp), .s_axi_bvalid(s_axi_bvalid), .s_axi_bready(s_axi_bready), .m_axi_awid(m_axi_awid), .m_axi_awaddr(m_axi_awaddr), .m_axi_awlen(m_axi_awlen), .m_axi_awsize(m_axi_awsize), .m_axi_awburst(m_axi_awburst), .m_axi_awlock(m_axi_awlock), .m_axi_awcache(m_axi_awcache), .m_axi_awprot(m_axi_awprot), .m_axi_awqos(m_axi_awqos), .m_axi_awregion(m_axi_awregion_i), .m_axi_awuser(m_axi_awuser), .m_axi_awvalid(m_axi_awvalid), .m_axi_awready(m_axi_awready), .m_axi_wid(m_axi_wid_i), .m_axi_wdata(m_axi_wdata), .m_axi_wstrb(m_axi_wstrb), .m_axi_wlast(m_axi_wlast), .m_axi_wvalid(m_axi_wvalid), .m_axi_wready(m_axi_wready), .m_axi_bid(m_axi_bid), .m_axi_bresp(m_axi_bresp), .m_axi_bvalid(m_axi_bvalid), .m_axi_bready(m_axi_bready), .s_axi_arid(s_axi_arid), .s_axi_araddr(s_axi_araddr), .s_axi_arlen(s_axi_arlen), .s_axi_arsize(s_axi_arsize), .s_axi_arburst(s_axi_arburst), .s_axi_arlock(s_axi_arlock), .s_axi_arcache(s_axi_arcache), .s_axi_arprot(s_axi_arprot), .s_axi_arqos(s_axi_arqos), .s_axi_arregion(s_axi_arregion_i), .s_axi_arvalid(s_axi_arvalid), .s_axi_arready(s_axi_arready), .s_axi_rid(s_axi_rid), .s_axi_rdata(s_axi_rdata), .s_axi_rresp(s_axi_rresp), .s_axi_rlast(s_axi_rlast), .s_axi_rvalid(s_axi_rvalid), .s_axi_rready(s_axi_rready), .m_axi_arid(m_axi_arid), .m_axi_araddr(m_axi_araddr), .m_axi_arlen(m_axi_arlen), .m_axi_arsize(m_axi_arsize), .m_axi_arburst(m_axi_arburst), .m_axi_arlock(m_axi_arlock), .m_axi_arcache(m_axi_arcache), .m_axi_arprot(m_axi_arprot), .m_axi_arqos(m_axi_arqos), .m_axi_arregion(m_axi_arregion_i), .m_axi_arvalid(m_axi_arvalid), .m_axi_arready(m_axi_arready), .m_axi_rid(m_axi_rid), .m_axi_rdata(m_axi_rdata), .m_axi_rresp(m_axi_rresp), .m_axi_rlast(m_axi_rlast), .m_axi_rvalid(m_axi_rvalid), .m_axi_rready(m_axi_rready), .m_aclk(aclk), .m_aclk_en(1\'b1), .s_aclk_en(1\'b1), .s_axi_wuser(s_axi_wuser), .s_axi_buser(s_axi_buser), .m_axi_wuser(m_axi_wuser), .m_axi_buser(m_axi_buser), .s_axi_aruser(s_axi_aruser), .s_axi_ruser(s_axi_ruser), .m_axi_aruser(m_axi_aruser), .m_axi_ruser(m_axi_ruser), .almost_empty(), .almost_full(), .axis_data_count(), .axis_dbiterr(), .axis_injectdbiterr(1\'b0), .axis_injectsbiterr(1\'b0), .axis_overflow(), .axis_prog_empty(), .axis_prog_empty_thresh(10\'b0), .axis_prog_full(), .axis_prog_full_thresh(10\'b0), .axis_rd_data_count(), .axis_sbiterr(), .axis_underflow(), .axis_wr_data_count(), .axi_ar_data_count(), .axi_ar_dbiterr(), .axi_ar_injectdbiterr(1\'b0), .axi_ar_injectsbiterr(1\'b0), .axi_ar_overflow(), .axi_ar_prog_empty(), .axi_ar_prog_empty_thresh(5\'b0), .axi_ar_prog_full(), .axi_ar_prog_full_thresh(5\'b0), .axi_ar_rd_data_count(), .axi_ar_sbiterr(), .axi_ar_underflow(), .axi_ar_wr_data_count(), .axi_aw_data_count(), .axi_aw_dbiterr(), .axi_aw_injectdbiterr(1\'b0), .axi_aw_injectsbiterr(1\'b0), .axi_aw_overflow(), .axi_aw_prog_empty(), .axi_aw_prog_empty_thresh(5\'b0), .axi_aw_prog_full(), .axi_aw_prog_full_thresh(5\'b0), .axi_aw_rd_data_count(), .axi_aw_sbiterr(), .axi_aw_underflow(), .axi_aw_wr_data_count(), .axi_b_data_count(), .axi_b_dbiterr(), .axi_b_injectdbiterr(1\'b0), .axi_b_injectsbiterr(1\'b0), .axi_b_overflow(), .axi_b_prog_empty(), .axi_b_prog_empty_thresh(4\'b0), .axi_b_prog_full(), .axi_b_prog_full_thresh(4\'b0), .axi_b_rd_data_count(), .axi_b_sbiterr(), .axi_b_underflow(), .axi_b_wr_data_count(), .axi_r_data_count(), .axi_r_dbiterr(), .axi_r_injectdbiterr(1\'b0), .axi_r_injectsbiterr(1\'b0), .axi_r_overflow(), .axi_r_prog_empty(), .axi_r_prog_empty_thresh({P_READ_FIFO_DEPTH_LOG{1\'b0}}), .axi_r_prog_full(), .axi_r_prog_full_thresh({P_READ_FIFO_DEPTH_LOG{1\'b0}}), .axi_r_rd_data_count(), .axi_r_sbiterr(), .axi_r_underflow(), .axi_r_wr_data_count(), .axi_w_data_count(), .axi_w_dbiterr(), .axi_w_injectdbiterr(1\'b0), .axi_w_injectsbiterr(1\'b0), .axi_w_overflow(), .axi_w_prog_empty(), .axi_w_prog_empty_thresh({P_WRITE_FIFO_DEPTH_LOG{1\'b0}}), .axi_w_prog_full(), .axi_w_prog_full_thresh({P_WRITE_FIFO_DEPTH_LOG{1\'b0}}), .axi_w_rd_data_count(), .axi_w_sbiterr(), .axi_w_underflow(), .axi_w_wr_data_count(), .backup(1\'b0), .backup_marker(1\'b0), .clk(1\'b0), .data_count(), .dbiterr(), .din(18\'b0), .dout(), .empty(), .full(), .injectdbiterr(1\'b0), .injectsbiterr(1\'b0), .int_clk(1\'b0), .m_axis_tdata(), .m_axis_tdest(), .m_axis_tid(), .m_axis_tkeep(), .m_axis_tlast(), .m_axis_tready(1\'b0), .m_axis_tstrb(), .m_axis_tuser(), .m_axis_tvalid(), .overflow(), .prog_empty(), .prog_empty_thresh(10\'b0), .prog_empty_thresh_assert(10\'b0), .prog_empty_thresh_negate(10\'b0), .prog_full(), .prog_full_thresh(10\'b0), .prog_full_thresh_assert(10\'b0), .prog_full_thresh_negate(10\'b0), .rd_clk(1\'b0), .rd_data_count(), .rd_en(1\'b0), .rd_rst(1\'b0), .rst(1\'b0), .sbiterr(), .srst(1\'b0), .s_axis_tdata(64\'b0), .s_axis_tdest(4\'b0), .s_axis_tid(8\'b0), .s_axis_tkeep(4\'b0), .s_axis_tlast(1\'b0), .s_axis_tready(), .s_axis_tstrb(4\'b0), .s_axis_tuser(4\'b0), .s_axis_tvalid(1\'b0), .underflow(), .valid(), .wr_ack(), .wr_clk(1\'b0), .wr_data_count(), .wr_en(1\'b0), .wr_rst(1\'b0), .wr_rst_busy(), .rd_rst_busy(), .sleep(1\'b0) ); end endgenerate endmodule
/////////////////////////////////////////////////////////////////////////////// // // File name: axi_protocol_converter_v2_1_b2s_wrap_cmd.v // /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_protocol_converter_v2_1_b2s_wrap_cmd # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // Width of AxADDR // Range: 32. parameter integer C_AXI_ADDR_WIDTH = 32 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire clk , input wire reset , input wire [C_AXI_ADDR_WIDTH-1:0] axaddr , input wire [7:0] axlen , input wire [2:0] axsize , // axhandshake = axvalid & axready input wire axhandshake , output wire [C_AXI_ADDR_WIDTH-1:0] cmd_byte_addr , // Connections to/from fsm module // signal to increment to the next mc transaction input wire next , // signal to the fsm there is another transaction required output reg next_pending ); //////////////////////////////////////////////////////////////////////////////// // Wire and register declarations //////////////////////////////////////////////////////////////////////////////// reg sel_first; wire [11:0] axaddr_i; wire [3:0] axlen_i; reg [11:0] wrap_boundary_axaddr; reg [3:0] axaddr_offset; reg [3:0] wrap_second_len; reg [11:0] wrap_boundary_axaddr_r; reg [3:0] axaddr_offset_r; reg [3:0] wrap_second_len_r; reg [4:0] axlen_cnt; reg [4:0] wrap_cnt_r; wire [4:0] wrap_cnt; reg [11:0] axaddr_wrap; reg next_pending_r; localparam L_AXI_ADDR_LOW_BIT = (C_AXI_ADDR_WIDTH >= 12) ? 12 : 11; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// generate if (C_AXI_ADDR_WIDTH > 12) begin : ADDR_GT_4K assign cmd_byte_addr = (sel_first) ? axaddr : {axaddr[C_AXI_ADDR_WIDTH-1:L_AXI_ADDR_LOW_BIT],axaddr_wrap[11:0]}; end else begin : ADDR_4K assign cmd_byte_addr = (sel_first) ? axaddr : axaddr_wrap[11:0]; end endgenerate assign axaddr_i = axaddr[11:0]; assign axlen_i = axlen[3:0]; // Mask bits based on transaction length to get wrap boundary low address // Offset used to calculate the length of each transaction always @( * ) begin if(axhandshake) begin wrap_boundary_axaddr = axaddr_i & ~(axlen_i << axsize[1:0]); axaddr_offset = axaddr_i[axsize[1:0] +: 4] & axlen_i; end else begin wrap_boundary_axaddr = wrap_boundary_axaddr_r; axaddr_offset = axaddr_offset_r; end end // case (axsize[1:0]) // 2\'b00 : axaddr_offset = axaddr_i[4:0] & axlen_i; // 2\'b01 : axaddr_offset = axaddr_i[5:1] & axlen_i; // 2\'b10 : axaddr_offset = axaddr_i[6:2] & axlen_i; // 2\'b11 : axaddr_offset = axaddr_i[7:3] & axlen_i; // default : axaddr_offset = axaddr_i[7:3] & axlen_i; // endcase // The first and the second command from the wrap transaction could // be of odd length or even length with address offset. This will be // an issue with BL8, extra transactions have to be issued. // Rounding up the length to account for extra transactions. always @( * ) begin if(axhandshake) begin wrap_second_len = (axaddr_offset >0) ? axaddr_offset - 1 : 0; end else begin wrap_second_len = wrap_second_len_r; end end // registering to be used in the combo logic. always @(posedge clk) begin wrap_boundary_axaddr_r <= wrap_boundary_axaddr; axaddr_offset_r <= axaddr_offset; wrap_second_len_r <= wrap_second_len; end // determining if extra data is required for even offsets // wrap_cnt used to switch the address for first and second transaction. assign wrap_cnt = {1\'b0, wrap_second_len + {3\'b000, (|axaddr_offset)}}; always @(posedge clk) wrap_cnt_r <= wrap_cnt; always @(posedge clk) begin if (axhandshake) begin axaddr_wrap <= axaddr[11:0]; end if(next)begin if(axlen_cnt == wrap_cnt_r) begin axaddr_wrap <= wrap_boundary_axaddr_r; end else begin axaddr_wrap <= axaddr_wrap + (1 << axsize[1:0]); end end end // Even numbber of transactions with offset, inc len by 2 for BL8 always @(posedge clk) begin if (axhandshake)begin axlen_cnt <= axlen_i; next_pending_r <= axlen_i >= 1; end else if (next) begin if (axlen_cnt > 1) begin axlen_cnt <= axlen_cnt - 1; next_pending_r <= (axlen_cnt - 1) >= 1; end else begin axlen_cnt <= 5\'d0; next_pending_r <= 1\'b0; end end end always @( * ) begin if (axhandshake)begin next_pending = axlen_i >= 1; end else if (next) begin if (axlen_cnt > 1) begin next_pending = (axlen_cnt - 1) >= 1; end else begin next_pending = 1\'b0; end end else begin next_pending = next_pending_r; end end // last and ignore signals to data channel. These signals are used for // BL8 to ignore and insert data for even len transactions with offset // and odd len transactions // For odd len transactions with no offset the last read is ignored and // last write is masked // For odd len transactions with offset the first read is ignored and // first write is masked // For even len transactions with offset the last & first read is ignored and // last& first write is masked // For even len transactions no ingnores or masks. // Indicates if we are on the first transaction of a mc translation with more // than 1 transaction. always @(posedge clk) begin if (reset | axhandshake) begin sel_first <= 1\'b1; end else if (next) begin sel_first <= 1\'b0; end end endmodule `default_nettype wire
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: // Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_carry logic. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module generic_baseblocks_v2_1_comparator_mask_static # ( parameter C_FAMILY = "virtex6", // FPGA Family. Current version: virtex6 or spartan6. parameter C_VALUE = 4\'b0, // Static value to compare against. parameter integer C_DATA_WIDTH = 4 // Data width for comparator. ) ( input wire CIN, input wire [C_DATA_WIDTH-1:0] A, input wire [C_DATA_WIDTH-1:0] M, output wire COUT ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// // Generate variable for bit vector. genvar lut_cnt; ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Bits per LUT for this architecture. localparam integer C_BITS_PER_LUT = 3; // Constants for packing levels. localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT; // localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT : C_DATA_WIDTH; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// wire [C_FIX_DATA_WIDTH-1:0] a_local; wire [C_FIX_DATA_WIDTH-1:0] b_local; wire [C_FIX_DATA_WIDTH-1:0] m_local; wire [C_NUM_LUT-1:0] sel; wire [C_NUM_LUT:0] carry_local; ///////////////////////////////////////////////////////////////////////////// // ///////////////////////////////////////////////////////////////////////////// generate // Assign input to local vectors. assign carry_local[0] = CIN; // Extend input data to fit. if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}}; assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}}; assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}}; end else begin : NO_EXTENDED_DATA assign a_local = A; assign b_local = C_VALUE; assign m_local = M; end // Instantiate one generic_baseblocks_v2_1_carry and per level. for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL // Create the local select signal assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) == ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ); // Instantiate each LUT level. generic_baseblocks_v2_1_carry_and # ( .C_FAMILY(C_FAMILY) ) compare_inst ( .COUT (carry_local[lut_cnt+1]), .CIN (carry_local[lut_cnt]), .S (sel[lut_cnt]) ); end // end for lut_cnt // Assign output from local vector. assign COUT = carry_local[C_NUM_LUT]; endgenerate endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: // Optimized 16/32 word deep FIFO. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module generic_baseblocks_v2_1_command_fifo # ( parameter C_FAMILY = "virtex6", parameter integer C_ENABLE_S_VALID_CARRY = 0, parameter integer C_ENABLE_REGISTERED_OUTPUT = 0, parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG // Range = [4:5]. parameter integer C_FIFO_WIDTH = 64 // Width of payload [1:512] ) ( // Global inputs input wire ACLK, // Clock input wire ARESET, // Reset // Information output wire EMPTY, // FIFO empty (all stages) // Slave Port input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals) input wire S_VALID, // FIFO push output wire S_READY, // FIFO not full // Master Port output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload output wire M_VALID, // FIFO not empty input wire M_READY // FIFO pop ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// // Generate variable for data vector. genvar addr_cnt; genvar bit_cnt; integer index; ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// wire [C_FIFO_DEPTH_LOG-1:0] addr; wire buffer_Full; wire buffer_Empty; wire next_Data_Exists; reg data_Exists_I; wire valid_Write; wire new_write; wire [C_FIFO_DEPTH_LOG-1:0] hsum_A; wire [C_FIFO_DEPTH_LOG-1:0] sum_A; wire [C_FIFO_DEPTH_LOG-1:0] addr_cy; wire buffer_full_early; wire [C_FIFO_WIDTH-1:0] M_MESG_I; // Payload wire M_VALID_I; // FIFO not empty wire M_READY_I; // FIFO pop ///////////////////////////////////////////////////////////////////////////// // Create Flags ///////////////////////////////////////////////////////////////////////////// assign buffer_full_early = ( (addr == {{C_FIFO_DEPTH_LOG-1{1\'b1}}, 1\'b0}) & valid_Write & ~M_READY_I ) | ( buffer_Full & ~M_READY_I ); assign S_READY = ~buffer_Full; assign buffer_Empty = (addr == {C_FIFO_DEPTH_LOG{1\'b0}}); assign next_Data_Exists = (data_Exists_I & ~buffer_Empty) | (buffer_Empty & S_VALID) | (data_Exists_I & ~(M_READY_I & data_Exists_I)); always @ (posedge ACLK) begin if (ARESET) begin data_Exists_I <= 1\'b0; end else begin data_Exists_I <= next_Data_Exists; end end assign M_VALID_I = data_Exists_I; // Select RTL or FPGA optimized instatiations for critical parts. generate if ( C_FAMILY == "rtl" || C_ENABLE_S_VALID_CARRY == 0 ) begin : USE_RTL_VALID_WRITE reg buffer_Full_q; assign valid_Write = S_VALID & ~buffer_Full; assign new_write = (S_VALID | ~buffer_Empty); assign addr_cy[0] = valid_Write; always @ (posedge ACLK) begin if (ARESET) begin buffer_Full_q <= 1\'b0; end else if ( data_Exists_I ) begin buffer_Full_q <= buffer_full_early; end end assign buffer_Full = buffer_Full_q; end else begin : USE_FPGA_VALID_WRITE wire s_valid_dummy1; wire s_valid_dummy2; wire sel_s_valid; wire sel_new_write; wire valid_Write_dummy1; wire valid_Write_dummy2; assign sel_s_valid = ~buffer_Full; generic_baseblocks_v2_1_carry_and # ( .C_FAMILY(C_FAMILY) ) s_valid_dummy_inst1 ( .CIN(S_VALID), .S(1\'b1), .COUT(s_valid_dummy1) ); generic_baseblocks_v2_1_carry_and # ( .C_FAMILY(C_FAMILY) ) s_valid_dummy_inst2 ( .CIN(s_valid_dummy1), .S(1\'b1), .COUT(s_valid_dummy2) ); generic_baseblocks_v2_1_carry_and # ( .C_FAMILY(C_FAMILY) ) valid_write_inst ( .CIN(s_valid_dummy2), .S(sel_s_valid), .COUT(valid_Write) ); assign sel_new_write = ~buffer_Empty; generic_baseblocks_v2_1_carry_latch_or # ( .C_FAMILY(C_FAMILY) ) new_write_inst ( .CIN(valid_Write), .I(sel_new_write), .O(new_write) ); generic_baseblocks_v2_1_carry_and # ( .C_FAMILY(C_FAMILY) ) valid_write_dummy_inst1 ( .CIN(valid_Write), .S(1\'b1), .COUT(valid_Write_dummy1) ); generic_baseblocks_v2_1_carry_and # ( .C_FAMILY(C_FAMILY) ) valid_write_dummy_inst2 ( .CIN(valid_Write_dummy1), .S(1\'b1), .COUT(valid_Write_dummy2) ); generic_baseblocks_v2_1_carry_and # ( .C_FAMILY(C_FAMILY) ) valid_write_dummy_inst3 ( .CIN(valid_Write_dummy2), .S(1\'b1), .COUT(addr_cy[0]) ); FDRE #( .INIT(1\'b0) // Initial value of register (1\'b0 or 1\'b1) ) FDRE_I1 ( .Q(buffer_Full), // Data output .C(ACLK), // Clock input .CE(data_Exists_I), // Clock enable input .R(ARESET), // Synchronous reset input .D(buffer_full_early) // Data input ); end endgenerate ///////////////////////////////////////////////////////////////////////////// // Create address pointer ///////////////////////////////////////////////////////////////////////////// generate if ( C_FAMILY == "rtl" ) begin : USE_RTL_ADDR reg [C_FIFO_DEPTH_LOG-1:0] addr_q; always @ (posedge ACLK) begin if (ARESET) begin addr_q <= {C_FIFO_DEPTH_LOG{1\'b0}}; end else if ( data_Exists_I ) begin if ( valid_Write & ~(M_READY_I & data_Exists_I) ) begin addr_q <= addr_q + 1\'b1; end else if ( ~valid_Write & (M_READY_I & data_Exists_I) & ~buffer_Empty ) begin addr_q <= addr_q - 1\'b1; end else begin addr_q <= addr_q; end end else begin addr_q <= addr_q; end end assign addr = addr_q; end else begin : USE_FPGA_ADDR for (addr_cnt = 0; addr_cnt < C_FIFO_DEPTH_LOG ; addr_cnt = addr_cnt + 1) begin : ADDR_GEN assign hsum_A[addr_cnt] = ((M_READY_I & data_Exists_I) ^ addr[addr_cnt]) & new_write; // Don\'t need the last muxcy, addr_cy(last) is not used anywhere if ( addr_cnt < C_FIFO_DEPTH_LOG - 1 ) begin : USE_MUXCY MUXCY MUXCY_inst ( .DI(addr[addr_cnt]), .CI(addr_cy[addr_cnt]), .S(hsum_A[addr_cnt]), .O(addr_cy[addr_cnt+1]) ); end else begin : NO_MUXCY end XORCY XORCY_inst ( .LI(hsum_A[addr_cnt]), .CI(addr_cy[addr_cnt]), .O(sum_A[addr_cnt]) ); FDRE #( .INIT(1\'b0) // Initial value of register (1\'b0 or 1\'b1) ) FDRE_inst ( .Q(addr[addr_cnt]), // Data output .C(ACLK), // Clock input .CE(data_Exists_I), // Clock enable input .R(ARESET), // Synchronous reset input .D(sum_A[addr_cnt]) // Data input ); end // end for bit_cnt end // C_FAMILY endgenerate ///////////////////////////////////////////////////////////////////////////// // Data storage ///////////////////////////////////////////////////////////////////////////// generate if ( C_FAMILY == "rtl" ) begin : USE_RTL_FIFO reg [C_FIFO_WIDTH-1:0] data_srl[2 ** C_FIFO_DEPTH_LOG-1:0]; always @ (posedge ACLK) begin if ( valid_Write ) begin for (index = 0; index < 2 ** C_FIFO_DEPTH_LOG-1 ; index = index + 1) begin data_srl[index+1] <= data_srl[index]; end data_srl[0] <= S_MESG; end end assign M_MESG_I = data_srl[addr]; end else begin : USE_FPGA_FIFO for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN if ( C_FIFO_DEPTH_LOG == 5 ) begin : USE_32 SRLC32E # ( .INIT(32\'h00000000) // Initial Value of Shift Register ) SRLC32E_inst ( .Q(M_MESG_I[bit_cnt]), // SRL data output .Q31(), // SRL cascade output pin .A(addr), // 5-bit shift depth select input .CE(valid_Write), // Clock enable input .CLK(ACLK), // Clock input .D(S_MESG[bit_cnt]) // SRL data input ); end else begin : USE_16 SRLC16E # ( .INIT(32\'h00000000) // Initial Value of Shift Register ) SRLC16E_inst ( .Q(M_MESG_I[bit_cnt]), // SRL data output .Q15(), // SRL cascade output pin .A0(addr[0]), // 4-bit shift depth select input 0 .A1(addr[1]), // 4-bit shift depth select input 1 .A2(addr[2]), // 4-bit shift depth select input 2 .A3(addr[3]), // 4-bit shift depth select input 3 .CE(valid_Write), // Clock enable input .CLK(ACLK), // Clock input .D(S_MESG[bit_cnt]) // SRL data input ); end // C_FIFO_DEPTH_LOG end // end for bit_cnt end // C_FAMILY endgenerate ///////////////////////////////////////////////////////////////////////////// // Pipeline stage ///////////////////////////////////////////////////////////////////////////// generate if ( C_ENABLE_REGISTERED_OUTPUT != 0 ) begin : USE_FF_OUT wire [C_FIFO_WIDTH-1:0] M_MESG_FF; // Payload wire M_VALID_FF; // FIFO not empty // Select RTL or FPGA optimized instatiations for critical parts. if ( C_FAMILY == "rtl" ) begin : USE_RTL_OUTPUT_PIPELINE reg [C_FIFO_WIDTH-1:0] M_MESG_Q; // Payload reg M_VALID_Q; // FIFO not empty always @ (posedge ACLK) begin if (ARESET) begin M_MESG_Q <= {C_FIFO_WIDTH{1\'b0}}; M_VALID_Q <= 1\'b0; end else begin if ( M_READY_I ) begin M_MESG_Q <= M_MESG_I; M_VALID_Q <= M_VALID_I; end end end assign M_MESG_FF = M_MESG_Q; assign M_VALID_FF = M_VALID_Q; end else begin : USE_FPGA_OUTPUT_PIPELINE reg [C_FIFO_WIDTH-1:0] M_MESG_CMB; // Payload reg M_VALID_CMB; // FIFO not empty always @ * begin if ( M_READY_I ) begin M_MESG_CMB <= M_MESG_I; M_VALID_CMB <= M_VALID_I; end else begin M_MESG_CMB <= M_MESG_FF; M_VALID_CMB <= M_VALID_FF; end end for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN FDRE #( .INIT(1\'b0) // Initial value of register (1\'b0 or 1\'b1) ) FDRE_inst ( .Q(M_MESG_FF[bit_cnt]), // Data output .C(ACLK), // Clock input .CE(1\'b1), // Clock enable input .R(ARESET), // Synchronous reset input .D(M_MESG_CMB[bit_cnt]) // Data input ); end // end for bit_cnt FDRE #( .INIT(1\'b0) // Initial value of register (1\'b0 or 1\'b1) ) FDRE_inst ( .Q(M_VALID_FF), // Data output .C(ACLK), // Clock input .CE(1\'b1), // Clock enable input .R(ARESET), // Synchronous reset input .D(M_VALID_CMB) // Data input ); end assign EMPTY = ~M_VALID_I & ~M_VALID_FF; assign M_MESG = M_MESG_FF; assign M_VALID = M_VALID_FF; assign M_READY_I = ( M_READY & M_VALID_FF ) | ~M_VALID_FF; end else begin : NO_FF_OUT assign EMPTY = ~M_VALID_I; assign M_MESG = M_MESG_I; assign M_VALID = M_VALID_I; assign M_READY_I = M_READY; end endgenerate endmodule
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // Filename: trace_buffer.v // Description: Trace port buffer //----------------------------------------------------------------------------- // Structure: This section shows the hierarchical structure of // pss_wrapper. // // --processing_system7 //\t\t\t\t\t\t\t |\t //\t\t\t\t\t\t\t --trace_buffer //----------------------------------------------------------------------------- module processing_system7_v5_5_trace_buffer # ( parameter integer FIFO_SIZE = 128, \tparameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0, parameter integer C_DELAY_CLKS = 12 ) ( input wire TRACE_CLK, input wire RST, input wire TRACE_VALID_IN, input wire [3:0] TRACE_ATID_IN, input wire [31:0] TRACE_DATA_IN, output wire TRACE_VALID_OUT, output wire [3:0] TRACE_ATID_OUT, output wire [31:0] TRACE_DATA_OUT ); //------------------------------------------------------------ // Architecture section //------------------------------------------------------------ // function called clogb2 that returns an integer which has the // value of the ceiling of the log base 2. function integer clogb2 (input integer bit_depth); integer i; integer temp_log; begin temp_log = 0; for(i=bit_depth; i > 0; i = i>>1) clogb2 = temp_log; temp_log=temp_log+1;\t\t end endfunction localparam DEPTH = clogb2(FIFO_SIZE-1); wire [31:0] reset_zeros; reg [31:0] trace_pedge; // write enable for FIFO reg [31:0] ti; reg [31:0] tom; reg [3:0] atid; reg [31:0] trace_fifo [FIFO_SIZE-1:0];//Memory reg [4:0] dly_ctr; reg [DEPTH-1:0] fifo_wp; reg [DEPTH-1:0] fifo_rp; reg fifo_re; wire fifo_empty; wire fifo_full; reg fifo_full_reg; assign reset_zeros = 32\'h0; // Pipeline Stage for Traceport ATID ports always @(posedge TRACE_CLK) begin // process pedge_ti // rising clock edge if((RST == 1\'b1)) begin atid <= reset_zeros; end else begin\t atid <= TRACE_ATID_IN; \t end end assign TRACE_ATID_OUT = atid; ///////////////////////////////////////////// // Generate FIFO data based on TRACE_VALID_IN ///////////////////////////////////////////// generate if (USE_TRACE_DATA_EDGE_DETECTOR == 0) begin : gen_no_data_edge_detector ///////////////////////////////////////////// \t\t // memory update process \t\t // Update memory when positive edge detected and FIFO not full \t\t always @(posedge TRACE_CLK) begin \t\t\t\tif (TRACE_VALID_IN == 1\'b1 && fifo_full_reg != 1\'b1) begin \t\t\t\t\ttrace_fifo[fifo_wp] <= TRACE_DATA_IN; \t\t\t\tend \t\t end \t\t // fifo write pointer \t\t always @(posedge TRACE_CLK) begin \t\t\t\t// process \t\t\t if(RST == 1\'b1) begin \t\t\t\tfifo_wp <= {DEPTH{1\'b0}}; \t\t\t end \t\t\t else if(TRACE_VALID_IN ) begin \t\t\t\tif(fifo_wp == (FIFO_SIZE - 1)) begin \t\t\t\t if (fifo_empty) begin \t\t\t\t\t fifo_wp <= {DEPTH{1\'b0}}; \t\t\t\t end \t\t\t\tend \t\t\t\telse begin \t\t\t\t fifo_wp <= fifo_wp + 1; \t\t\t\tend \t\t\t end \t\t end ///////////////////////////////////////////// // Generate FIFO data based on data edge ///////////////////////////////////////////// end else begin : gen_data_edge_detector ///////////////////////////////////////////// \t\t // purpose: check for pos edge on any trace input \t\t always @(posedge TRACE_CLK) begin \t\t\t // process pedge_ti \t\t\t // rising clock edge \t\t\t if((RST == 1\'b1)) begin \t\t\t\tti <= reset_zeros; \t\t\t\ttrace_pedge <= reset_zeros; \t\t\t end \t\t\t else begin \t\t\t\tti <= TRACE_DATA_IN; \t\t\t\ttrace_pedge <= (~ti & TRACE_DATA_IN); \t\t\t\t//trace_pedge <= ((~ti ^ TRACE_DATA_IN)) & ~ti; \t\t\t\t// posedge only \t\t\t end \t\t end \t\t \t\t // memory update process \t\t // Update memory when positive edge detected and FIFO not full \t\t always @(posedge TRACE_CLK) begin \t\t\t if(|(trace_pedge) == 1\'b1 && fifo_full_reg != 1\'b1) begin \t\t\t\ttrace_fifo[fifo_wp] <= trace_pedge; \t\t\t end \t\t end \t\t // fifo write pointer \t\t always @(posedge TRACE_CLK) begin \t\t\t\t// process \t\t\t if(RST == 1\'b1) begin \t\t\t\tfifo_wp <= {DEPTH{1\'b0}}; \t\t\t end \t\t\t else if(|(trace_pedge) == 1\'b1) begin \t\t\t\tif(fifo_wp == (FIFO_SIZE - 1)) begin \t\t\t\t if (fifo_empty) begin \t\t\t\t\t fifo_wp <= {DEPTH{1\'b0}}; \t\t\t\t end \t\t\t\tend \t\t\t\telse begin \t\t\t\t fifo_wp <= fifo_wp + 1; \t\t\t\tend \t\t\t end \t\t end end endgenerate always @(posedge TRACE_CLK) begin tom <= trace_fifo[fifo_rp] ; end // // fifo write pointer // always @(posedge TRACE_CLK) begin // // process // if(RST == 1\'b1) begin // fifo_wp <= {DEPTH{1\'b0}}; // end // else if(|(trace_pedge) == 1\'b1) begin // if(fifo_wp == (FIFO_SIZE - 1)) begin // fifo_wp <= {DEPTH{1\'b0}}; // end // else begin // fifo_wp <= fifo_wp + 1; // end // end // end // fifo read pointer update always @(posedge TRACE_CLK) begin if(RST == 1\'b1) begin fifo_rp <= {DEPTH{1\'b0}}; fifo_re <= 1\'b0; end else if(fifo_empty != 1\'b1 && dly_ctr == 5\'b00000 && fifo_re == 1\'b0) begin fifo_re <= 1\'b1; if(fifo_rp == (FIFO_SIZE - 1)) begin fifo_rp <= {DEPTH{1\'b0}}; end else begin fifo_rp <= fifo_rp + 1; end end else begin fifo_re <= 1\'b0; end end // delay counter update always @(posedge TRACE_CLK) begin if(RST == 1\'b1) begin dly_ctr <= 5\'h0; end else if (fifo_re == 1\'b1) begin dly_ctr <= C_DELAY_CLKS-1; end else if(dly_ctr != 5\'h0) begin dly_ctr <= dly_ctr - 1; end end // fifo empty update assign fifo_empty = (fifo_wp == fifo_rp) ? 1\'b1 : 1\'b0; // fifo full update assign fifo_full = (fifo_wp == FIFO_SIZE-1)? 1\'b1 : 1\'b0; always @(posedge TRACE_CLK) begin if(RST == 1\'b1) begin fifo_full_reg <= 1\'b0; end else if (fifo_empty) begin fifo_full_reg <= 1\'b0; \t end else begin\t fifo_full_reg <= fifo_full; end end // always @(posedge TRACE_CLK) begin // if(RST == 1\'b1) begin // fifo_full_reg <= 1\'b0; // end // else if ((fifo_wp == FIFO_SIZE-1) && (|(trace_pedge) == 1\'b1)) begin // fifo_full_reg <= 1\'b1; // end //\t else begin // fifo_full_reg <= 1\'b0; // end // end // assign TRACE_DATA_OUT = tom; assign TRACE_VALID_OUT = fifo_re; endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_reg_map.v * * Date : 2012-11 * * Description : Controller for Register Map Memory * *****************************************************************************/ /*** WA for CR # 695818 ***/ `ifdef XILINX_SIMULATOR `define XSIM_ISIM `endif `ifdef XILINX_ISIM `define XSIM_ISIM `endif module processing_system7_bfm_v2_0_reg_map(); `include "processing_system7_bfm_v2_0_local_params.v" /* Register definitions */ `include "processing_system7_bfm_v2_0_reg_params.v" parameter mem_size = 32\'h2000_0000; ///as the memory is implemented 4 byte wide parameter xsim_mem_size = 32\'h1000_0000; ///as the memory is implemented 4 byte wide 256 MB `ifdef XSIM_ISIM reg [data_width-1:0] reg_mem0 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem reg [data_width-1:0] reg_mem1 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem parameter addr_offset_bits = 26; `else reg /*sparse*/ [data_width-1:0] reg_mem [0:(mem_size/mem_width)-1]; // 512 MB needed for reg space parameter addr_offset_bits = 27; `endif /* preload reset_values from file */ task automatic pre_load_rst_values; input dummy; begin `include "processing_system7_bfm_v2_0_reg_init.v" /* This file has list of set_reset_data() calls to set the reset value for each register*/ end endtask /* writes the reset data into the reg memory */ task automatic set_reset_data; input [addr_width-1:0] address; input [data_width-1:0] data; reg [addr_width-1:0] addr; begin addr = address >> 2; `ifdef XSIM_ISIM case(addr[addr_width-1:addr_offset_bits]) 14 : reg_mem0[addr[addr_offset_bits-1:0]] = data; 15 : reg_mem1[addr[addr_offset_bits-1:0]] = data; endcase `else reg_mem[addr[addr_offset_bits-1:0]] = data; `endif end endtask /* writes the data into the reg memory */ task automatic set_data; input [addr_width-1:0] addr; input [data_width-1:0] data; begin `ifdef XSIM_ISIM case(addr[addr_width-1:addr_offset_bits]) 6\'h0E : reg_mem0[addr[addr_offset_bits-1:0]] = data; 6\'h0F : reg_mem1[addr[addr_offset_bits-1:0]] = data; endcase `else reg_mem[addr[addr_offset_bits-1:0]] = data; `endif end endtask /* get the read data from reg mem */ task automatic get_data; input [addr_width-1:0] addr; output [data_width-1:0] data; begin `ifdef XSIM_ISIM case(addr[addr_width-1:addr_offset_bits]) 6\'h0E : data = reg_mem0[addr[addr_offset_bits-1:0]]; 6\'h0F : data = reg_mem1[addr[addr_offset_bits-1:0]]; endcase `else data = reg_mem[addr[addr_offset_bits-1:0]]; `endif end endtask /* read chunk of registers */ task read_reg_mem; output[max_burst_bits-1 :0] data; input [addr_width-1:0] start_addr; input [max_burst_bytes_width:0] no_of_bytes; integer i; reg [addr_width-1:0] addr; reg [data_width-1:0] temp_rd_data; reg [max_burst_bits-1:0] temp_data; integer bytes_left; begin addr = start_addr >> shft_addr_bits; bytes_left = no_of_bytes; `ifdef XLNX_INT_DBG $display("[%0d] : %0s : Reading Register Map starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes ); `endif /* Get first data ... if unaligned address */ get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits- data_width]); if(no_of_bytes < mem_width ) begin repeat(max_burst_bytes - mem_width) temp_data = temp_data >> 8; end else begin bytes_left = bytes_left - mem_width; addr = addr+1; /* Got first data */ while (bytes_left > (mem_width-1) ) begin temp_data = temp_data >> data_width; get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]); addr = addr+1; bytes_left = bytes_left - mem_width; end /* Get last valid data in the burst*/ get_data(addr,temp_rd_data); while(bytes_left > 0) begin temp_data = temp_data >> 8; temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0]; temp_rd_data = temp_rd_data >> 8; bytes_left = bytes_left - 1; end /* align to the brst_byte length */ repeat(max_burst_bytes - no_of_bytes) temp_data = temp_data >> 8; end data = temp_data; `ifdef XLNX_INT_DBG $display("[%0d] : %0s : DONE -> Reading Register Map starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data ); `endif end endtask initial begin pre_load_rst_values(1); end endmodule
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // File name: si_transactor.v // // Description: // This module manages multi-threaded transactions for one SI-slot. // The module interface consists of a 1-slave to 1-master address channel, plus a // (M+1)-master (from M MI-slots plus error handler) to 1-slave response channel. // The module maintains transaction thread control registers that count the // number of outstanding transations for each thread and the target MI-slot. // On the address channel, the module decodes addresses to select among MI-slots // accessible to the SI-slot where it is instantiated. // It then qualifies whether each received transaction // should be propagated as a request to the address channel arbiter. // Transactions are blocked while there is any outstanding transaction to a // different slave (MI-slot) for the requested ID thread (for deadlock avoidance). // On the response channel, the module mulitplexes transfers from each of the // MI-slots whenever a transfer targets the ID of an active thread, // arbitrating between MI-slots if multiple threads respond concurrently. // //-------------------------------------------------------------------------- // // Structure: // si_transactor // addr_decoder // comparator_static // mux_enc // axic_srl_fifo // arbiter_resp // //----------------------------------------------------------------------------- `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_crossbar_v2_1_si_transactor # ( parameter C_FAMILY = "none", parameter integer C_SI = 0, // SI-slot number of current instance. parameter integer C_DIR = 0, // Direction: 0 = Write; 1 = Read. parameter integer C_NUM_ADDR_RANGES = 1, parameter integer C_NUM_M = 2, parameter integer C_NUM_M_LOG = 1, parameter integer C_ACCEPTANCE = 1, // Acceptance limit of this SI-slot. parameter integer C_ACCEPTANCE_LOG = 0, // Width of acceptance counter for this SI-slot. parameter integer C_ID_WIDTH = 1, parameter integer C_THREAD_ID_WIDTH = 0, parameter integer C_ADDR_WIDTH = 32, parameter integer C_AMESG_WIDTH = 1, // Used for AW or AR channel payload, depending on instantiation. parameter integer C_RMESG_WIDTH = 1, // Used for B or R channel payload, depending on instantiation. parameter [C_ID_WIDTH-1:0] C_BASE_ID = {C_ID_WIDTH{1\'b0}}, parameter [C_ID_WIDTH-1:0] C_HIGH_ID = {C_ID_WIDTH{1\'b0}}, parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1\'b1}}, parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1\'b0}}, parameter integer C_SINGLE_THREAD = 0, parameter [C_NUM_M-1:0] C_TARGET_QUAL = {C_NUM_M{1\'b1}}, parameter [C_NUM_M*32-1:0] C_M_AXI_SECURE = {C_NUM_M{32\'h00000000}}, parameter integer C_RANGE_CHECK = 0, parameter integer C_ADDR_DECODE =0, parameter [C_NUM_M*32-1:0] C_ERR_MODE = {C_NUM_M{32\'h00000000}}, parameter integer C_DEBUG = 1 ) ( // Global Signals input wire ACLK, input wire ARESET, // Slave Address Channel Interface Ports input wire [C_ID_WIDTH-1:0] S_AID, input wire [C_ADDR_WIDTH-1:0] S_AADDR, input wire [8-1:0] S_ALEN, input wire [3-1:0] S_ASIZE, input wire [2-1:0] S_ABURST, input wire [2-1:0] S_ALOCK, input wire [3-1:0] S_APROT, // input wire [4-1:0] S_AREGION, input wire [C_AMESG_WIDTH-1:0] S_AMESG, input wire S_AVALID, output wire S_AREADY, // Master Address Channel Interface Ports output wire [C_ID_WIDTH-1:0] M_AID, output wire [C_ADDR_WIDTH-1:0] M_AADDR, output wire [8-1:0] M_ALEN, output wire [3-1:0] M_ASIZE, output wire [2-1:0] M_ALOCK, output wire [3-1:0] M_APROT, output wire [4-1:0] M_AREGION, output wire [C_AMESG_WIDTH-1:0] M_AMESG, output wire [(C_NUM_M+1)-1:0] M_ATARGET_HOT, output wire [(C_NUM_M_LOG+1)-1:0] M_ATARGET_ENC, output wire [7:0] M_AERROR, output wire M_AVALID_QUAL, output wire M_AVALID, input wire M_AREADY, // Slave Response Channel Interface Ports output wire [C_ID_WIDTH-1:0] S_RID, output wire [C_RMESG_WIDTH-1:0] S_RMESG, output wire S_RLAST, output wire S_RVALID, input wire S_RREADY, // Master Response Channel Interface Ports input wire [(C_NUM_M+1)*C_ID_WIDTH-1:0] M_RID, input wire [(C_NUM_M+1)*C_RMESG_WIDTH-1:0] M_RMESG, input wire [(C_NUM_M+1)-1:0] M_RLAST, input wire [(C_NUM_M+1)-1:0] M_RVALID, output wire [(C_NUM_M+1)-1:0] M_RREADY, input wire [(C_NUM_M+1)-1:0] M_RTARGET, // Does response ID from each MI-slot target this SI slot? input wire [8-1:0] DEBUG_A_TRANS_SEQ ); localparam integer P_WRITE = 0; localparam integer P_READ = 1; localparam integer P_RMUX_MESG_WIDTH = C_ID_WIDTH + C_RMESG_WIDTH + 1; localparam [31:0] P_AXILITE_ERRMODE = 32\'h00000001; localparam integer P_NONSECURE_BIT = 1; localparam integer P_NUM_M_LOG_M1 = C_NUM_M_LOG ? C_NUM_M_LOG : 1; localparam [C_NUM_M-1:0] P_M_AXILITE = f_m_axilite(0); // Mask of AxiLite MI-slots localparam [1:0] P_FIXED = 2\'b00; localparam integer P_NUM_M_DE_LOG = f_ceil_log2(C_NUM_M+1); localparam integer P_THREAD_ID_WIDTH_M1 = (C_THREAD_ID_WIDTH > 0) ? C_THREAD_ID_WIDTH : 1; localparam integer P_NUM_ID_VAL = 2**C_THREAD_ID_WIDTH; localparam integer P_NUM_THREADS = (P_NUM_ID_VAL < C_ACCEPTANCE) ? P_NUM_ID_VAL : C_ACCEPTANCE; localparam [C_NUM_M-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE); // Mask of secure MI-slots // Ceiling of log2(x) function integer f_ceil_log2 ( input integer x ); integer acc; begin acc=0; while ((2**acc) < x) acc = acc + 1; f_ceil_log2 = acc; end endfunction // AxiLite protocol flag vector function [C_NUM_M-1:0] f_m_axilite ( input integer null_arg ); integer mi; begin for (mi=0; mi<C_NUM_M; mi=mi+1) begin f_m_axilite[mi] = (C_ERR_MODE[mi*32+:32] == P_AXILITE_ERRMODE); end end endfunction // Convert Bit32 vector of range [0,1] to Bit1 vector on MI function [C_NUM_M-1:0] f_bit32to1_mi (input [C_NUM_M*32-1:0] vec32); integer mi; begin for (mi=0; mi<C_NUM_M; mi=mi+1) begin f_bit32to1_mi[mi] = vec32[mi*32]; end end endfunction wire [C_NUM_M-1:0] target_mi_hot; wire [P_NUM_M_LOG_M1-1:0] target_mi_enc; wire [(C_NUM_M+1)-1:0] m_atarget_hot_i; wire [(P_NUM_M_DE_LOG)-1:0] m_atarget_enc_i; wire match; wire [3:0] target_region; wire [3:0] m_aregion_i; wire m_avalid_i; wire s_aready_i; wire any_error; wire s_rvalid_i; wire [C_ID_WIDTH-1:0] s_rid_i; wire s_rlast_i; wire [P_RMUX_MESG_WIDTH-1:0] si_rmux_mesg; wire [(C_NUM_M+1)*P_RMUX_MESG_WIDTH-1:0] mi_rmux_mesg; wire [(C_NUM_M+1)-1:0] m_rvalid_qual; wire [(C_NUM_M+1)-1:0] m_rready_arb; wire [(C_NUM_M+1)-1:0] m_rready_i; wire target_secure; wire target_axilite; wire m_avalid_qual_i; wire [7:0] m_aerror_i; genvar gen_mi; genvar gen_thread; generate if (C_ADDR_DECODE) begin : gen_addr_decoder axi_crossbar_v2_1_addr_decoder # ( .C_FAMILY (C_FAMILY), .C_NUM_TARGETS (C_NUM_M), .C_NUM_TARGETS_LOG (P_NUM_M_LOG_M1), .C_NUM_RANGES (C_NUM_ADDR_RANGES), .C_ADDR_WIDTH (C_ADDR_WIDTH), .C_TARGET_ENC (1), .C_TARGET_HOT (1), .C_REGION_ENC (1), .C_BASE_ADDR (C_BASE_ADDR), .C_HIGH_ADDR (C_HIGH_ADDR), .C_TARGET_QUAL (C_TARGET_QUAL), .C_RESOLUTION (2) ) addr_decoder_inst ( .ADDR (S_AADDR), .TARGET_HOT (target_mi_hot), .TARGET_ENC (target_mi_enc), .MATCH (match), .REGION (target_region) ); end else begin : gen_no_addr_decoder assign target_mi_hot = 1; assign target_mi_enc = 0; assign match = 1\'b1; assign target_region = 4\'b0000; end endgenerate assign target_secure = |(target_mi_hot & P_M_SECURE_MASK); assign target_axilite = |(target_mi_hot & P_M_AXILITE); assign any_error = C_RANGE_CHECK && (m_aerror_i != 0); // DECERR if error-detection enabled and any error condition. assign m_aerror_i[0] = ~match; // Invalid target address assign m_aerror_i[1] = target_secure && S_APROT[P_NONSECURE_BIT]; // TrustZone violation assign m_aerror_i[2] = target_axilite && ((S_ALEN != 0) || (S_ASIZE[1:0] == 2\'b11) || (S_ASIZE[2] == 1\'b1)); // AxiLite access violation assign m_aerror_i[7:3] = 5\'b00000; // Reserved assign M_ATARGET_HOT = m_atarget_hot_i; assign m_atarget_hot_i = (any_error ? {1\'b1, {C_NUM_M{1\'b0}}} : {1\'b0, target_mi_hot}); assign m_atarget_enc_i = (any_error ? C_NUM_M : target_mi_enc); assign M_AVALID = m_avalid_i; assign m_avalid_i = S_AVALID; assign M_AVALID_QUAL = m_avalid_qual_i; assign S_AREADY = s_aready_i; assign s_aready_i = M_AREADY; assign M_AERROR = m_aerror_i; assign M_ATARGET_ENC = m_atarget_enc_i; assign m_aregion_i = any_error ? 4\'b0000 : (C_ADDR_DECODE != 0) ? target_region : 4\'b0000; // assign m_aregion_i = any_error ? 4\'b0000 : (C_ADDR_DECODE != 0) ? target_region : S_AREGION; assign M_AREGION = m_aregion_i; assign M_AID = S_AID; assign M_AADDR = S_AADDR; assign M_ALEN = S_ALEN; assign M_ASIZE = S_ASIZE; assign M_ALOCK = S_ALOCK; assign M_APROT = S_APROT; assign M_AMESG = S_AMESG; assign S_RVALID = s_rvalid_i; assign M_RREADY = m_rready_i; assign s_rid_i = si_rmux_mesg[0+:C_ID_WIDTH]; assign S_RMESG = si_rmux_mesg[C_ID_WIDTH+:C_RMESG_WIDTH]; assign s_rlast_i = si_rmux_mesg[C_ID_WIDTH+C_RMESG_WIDTH+:1]; assign S_RID = s_rid_i; assign S_RLAST = s_rlast_i; assign m_rvalid_qual = M_RVALID & M_RTARGET; assign m_rready_i = m_rready_arb & M_RTARGET; generate for (gen_mi=0; gen_mi<(C_NUM_M+1); gen_mi=gen_mi+1) begin : gen_rmesg_mi // Note: Concatenation of mesg signals is from MSB to LSB; assignments that chop mesg signals appear in opposite order. assign mi_rmux_mesg[gen_mi*P_RMUX_MESG_WIDTH+:P_RMUX_MESG_WIDTH] = { M_RLAST[gen_mi], M_RMESG[gen_mi*C_RMESG_WIDTH+:C_RMESG_WIDTH], M_RID[gen_mi*C_ID_WIDTH+:C_ID_WIDTH] }; end // gen_rmesg_mi if (C_ACCEPTANCE == 1) begin : gen_single_issue wire cmd_push; wire cmd_pop; reg [(C_NUM_M+1)-1:0] active_target_hot; reg [P_NUM_M_DE_LOG-1:0] active_target_enc; reg accept_cnt; reg [8-1:0] debug_r_beat_cnt_i; wire [8-1:0] debug_r_trans_seq_i; assign cmd_push = M_AREADY; assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i; // Pop command queue if end of read burst assign m_avalid_qual_i = ~accept_cnt | cmd_pop; // Ready for arbitration if no outstanding transaction or transaction being completed always @(posedge ACLK) begin if (ARESET) begin accept_cnt <= 1\'b0; active_target_enc <= 0; active_target_hot <= 0; end else begin if (cmd_push) begin active_target_enc <= m_atarget_enc_i; active_target_hot <= m_atarget_hot_i; accept_cnt <= 1\'b1; end else if (cmd_pop) begin accept_cnt <= 1\'b0; end end end // Clocked process assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}}; assign s_rvalid_i = |(active_target_hot & m_rvalid_qual); generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY (C_FAMILY), .C_RATIO (C_NUM_M+1), .C_SEL_WIDTH (P_NUM_M_DE_LOG), .C_DATA_WIDTH (P_RMUX_MESG_WIDTH) ) mux_resp_single_issue ( .S (active_target_enc), .A (mi_rmux_mesg), .O (si_rmux_mesg), .OE (1\'b1) ); if (C_DEBUG) begin : gen_debug_r_single_issue // DEBUG READ BEAT COUNTER (only meaningful for R-channel) always @(posedge ACLK) begin if (ARESET) begin debug_r_beat_cnt_i <= 0; end else if (C_DIR == P_READ) begin if (s_rvalid_i && S_RREADY) begin if (s_rlast_i) begin debug_r_beat_cnt_i <= 0; end else begin debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1; end end end else begin debug_r_beat_cnt_i <= 0; end end // Clocked process // DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO axi_data_fifo_v2_1_axic_srl_fifo # ( .C_FAMILY (C_FAMILY), .C_FIFO_WIDTH (8), .C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1), .C_USE_FULL (0) ) debug_r_seq_fifo_single_issue ( .ACLK (ACLK), .ARESET (ARESET), .S_MESG (DEBUG_A_TRANS_SEQ), .S_VALID (cmd_push), .S_READY (), .M_MESG (debug_r_trans_seq_i), .M_VALID (), .M_READY (cmd_pop) ); end // gen_debug_r end else if (C_SINGLE_THREAD || (P_NUM_ID_VAL==1)) begin : gen_single_thread wire s_avalid_en; wire cmd_push; wire cmd_pop; reg [C_ID_WIDTH-1:0] active_id; reg [(C_NUM_M+1)-1:0] active_target_hot; reg [P_NUM_M_DE_LOG-1:0] active_target_enc; reg [4-1:0] active_region; reg [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt; reg [8-1:0] debug_r_beat_cnt_i; wire [8-1:0] debug_r_trans_seq_i; wire accept_limit ; // Implement single-region-per-ID cyclic dependency avoidance method. assign s_avalid_en = // This transaction is qualified to request arbitration if ... (accept_cnt == 0) || // Either there are no outstanding transactions, or ... (((P_NUM_ID_VAL==1) || (S_AID[P_THREAD_ID_WIDTH_M1-1:0] == active_id[P_THREAD_ID_WIDTH_M1-1:0])) && // the current transaction ID matches the previous, and ... (active_target_enc == m_atarget_enc_i) && // all outstanding transactions are to the same target MI ... (active_region == m_aregion_i)); // and to the same REGION. assign cmd_push = M_AREADY; assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i; // Pop command queue if end of read burst assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~cmd_pop; // Allow next push if a transaction is currently being completed assign m_avalid_qual_i = s_avalid_en & ~accept_limit; always @(posedge ACLK) begin if (ARESET) begin accept_cnt <= 0; active_id <= 0; active_target_enc <= 0; active_target_hot <= 0; active_region <= 0; end else begin if (cmd_push) begin active_id <= S_AID[P_THREAD_ID_WIDTH_M1-1:0]; active_target_enc <= m_atarget_enc_i; active_target_hot <= m_atarget_hot_i; active_region <= m_aregion_i; if (~cmd_pop) begin accept_cnt <= accept_cnt + 1; end end else begin if (cmd_pop & (accept_cnt != 0)) begin accept_cnt <= accept_cnt - 1; end end end end // Clocked process assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}}; assign s_rvalid_i = |(active_target_hot & m_rvalid_qual); generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY (C_FAMILY), .C_RATIO (C_NUM_M+1), .C_SEL_WIDTH (P_NUM_M_DE_LOG), .C_DATA_WIDTH (P_RMUX_MESG_WIDTH) ) mux_resp_single_thread ( .S (active_target_enc), .A (mi_rmux_mesg), .O (si_rmux_mesg), .OE (1\'b1) ); if (C_DEBUG) begin : gen_debug_r_single_thread // DEBUG READ BEAT COUNTER (only meaningful for R-channel) always @(posedge ACLK) begin if (ARESET) begin debug_r_beat_cnt_i <= 0; end else if (C_DIR == P_READ) begin if (s_rvalid_i && S_RREADY) begin if (s_rlast_i) begin debug_r_beat_cnt_i <= 0; end else begin debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1; end end end else begin debug_r_beat_cnt_i <= 0; end end // Clocked process // DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO axi_data_fifo_v2_1_axic_srl_fifo # ( .C_FAMILY (C_FAMILY), .C_FIFO_WIDTH (8), .C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1), .C_USE_FULL (0) ) debug_r_seq_fifo_single_thread ( .ACLK (ACLK), .ARESET (ARESET), .S_MESG (DEBUG_A_TRANS_SEQ), .S_VALID (cmd_push), .S_READY (), .M_MESG (debug_r_trans_seq_i), .M_VALID (), .M_READY (cmd_pop) ); end // gen_debug_r end else begin : gen_multi_thread wire [(P_NUM_M_DE_LOG)-1:0] resp_select; reg [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt; wire [P_NUM_THREADS-1:0] s_avalid_en; wire [P_NUM_THREADS-1:0] thread_valid; wire [P_NUM_THREADS-1:0] aid_match; wire [P_NUM_THREADS-1:0] rid_match; wire [P_NUM_THREADS-1:0] cmd_push; wire [P_NUM_THREADS-1:0] cmd_pop; wire [P_NUM_THREADS:0] accum_push; reg [P_NUM_THREADS*C_ID_WIDTH-1:0] active_id; reg [P_NUM_THREADS*8-1:0] active_target; reg [P_NUM_THREADS*8-1:0] active_region; reg [P_NUM_THREADS*8-1:0] active_cnt; reg [P_NUM_THREADS*8-1:0] debug_r_beat_cnt_i; wire [P_NUM_THREADS*8-1:0] debug_r_trans_seq_i; wire any_aid_match; wire any_rid_match; wire accept_limit; wire any_push; wire any_pop; axi_crossbar_v2_1_arbiter_resp # // Multi-thread response arbiter ( .C_FAMILY (C_FAMILY), .C_NUM_S (C_NUM_M+1), .C_NUM_S_LOG (P_NUM_M_DE_LOG), .C_GRANT_ENC (1), .C_GRANT_HOT (0) ) arbiter_resp_inst ( .ACLK (ACLK), .ARESET (ARESET), .S_VALID (m_rvalid_qual), .S_READY (m_rready_arb), .M_GRANT_HOT (), .M_GRANT_ENC (resp_select), .M_VALID (s_rvalid_i), .M_READY (S_RREADY) ); generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY (C_FAMILY), .C_RATIO (C_NUM_M+1), .C_SEL_WIDTH (P_NUM_M_DE_LOG), .C_DATA_WIDTH (P_RMUX_MESG_WIDTH) ) mux_resp_multi_thread ( .S (resp_select), .A (mi_rmux_mesg), .O (si_rmux_mesg), .OE (1\'b1) ); assign any_push = M_AREADY; assign any_pop = s_rvalid_i & S_RREADY & s_rlast_i; assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~any_pop; // Allow next push if a transaction is currently being completed assign m_avalid_qual_i = (&s_avalid_en) & ~accept_limit; // The current request is qualified for arbitration when it is qualified against all outstanding transaction threads. assign any_aid_match = |aid_match; assign any_rid_match = |rid_match; assign accum_push[0] = 1\'b0; always @(posedge ACLK) begin if (ARESET) begin accept_cnt <= 0; end else begin if (any_push & ~any_pop) begin accept_cnt <= accept_cnt + 1; end else if (any_pop & ~any_push & (accept_cnt != 0)) begin accept_cnt <= accept_cnt - 1; end end end // Clocked process for (gen_thread=0; gen_thread<P_NUM_THREADS; gen_thread=gen_thread+1) begin : gen_thread_loop assign thread_valid[gen_thread] = (active_cnt[gen_thread*8 +: C_ACCEPTANCE_LOG+1] != 0); assign aid_match[gen_thread] = // The currect thread is active for the requested transaction if thread_valid[gen_thread] && // this thread slot is not vacant, and ((S_AID[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]); // the requested ID matches the active ID for this thread. assign s_avalid_en[gen_thread] = // The current request is qualified against this thread slot if (~aid_match[gen_thread]) || // This thread slot is not active for the requested ID, or ((m_atarget_enc_i == active_target[gen_thread*8+:P_NUM_M_DE_LOG]) && // this outstanding transaction was to the same target and (m_aregion_i == active_region[gen_thread*8+:4])); // to the same region. // cmd_push points to the position of either the active thread for the requested ID or the lowest vacant thread slot. assign accum_push[gen_thread+1] = accum_push[gen_thread] | ~thread_valid[gen_thread]; assign cmd_push[gen_thread] = any_push & (aid_match[gen_thread] | ((~any_aid_match) & ~thread_valid[gen_thread] & ~accum_push[gen_thread])); // cmd_pop points to the position of the active thread that matches the current RID. assign rid_match[gen_thread] = thread_valid[gen_thread] & ((s_rid_i[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]); assign cmd_pop[gen_thread] = any_pop & rid_match[gen_thread]; always @(posedge ACLK) begin if (ARESET) begin active_id[gen_thread*C_ID_WIDTH+:C_ID_WIDTH] <= 0; active_target[gen_thread*8+:8] <= 0; active_region[gen_thread*8+:8] <= 0; active_cnt[gen_thread*8+:8] <= 0; end else begin if (cmd_push[gen_thread]) begin active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1] <= S_AID[P_THREAD_ID_WIDTH_M1-1:0]; active_target[gen_thread*8+:P_NUM_M_DE_LOG] <= m_atarget_enc_i; active_region[gen_thread*8+:4] <= m_aregion_i; if (~cmd_pop[gen_thread]) begin active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] + 1; end end else if (cmd_pop[gen_thread]) begin active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] - 1; end end end // Clocked process if (C_DEBUG) begin : gen_debug_r_multi_thread // DEBUG READ BEAT COUNTER (only meaningful for R-channel) always @(posedge ACLK) begin if (ARESET) begin debug_r_beat_cnt_i[gen_thread*8+:8] <= 0; end else if (C_DIR == P_READ) begin if (s_rvalid_i & S_RREADY & rid_match[gen_thread]) begin if (s_rlast_i) begin debug_r_beat_cnt_i[gen_thread*8+:8] <= 0; end else begin debug_r_beat_cnt_i[gen_thread*8+:8] <= debug_r_beat_cnt_i[gen_thread*8+:8] + 1; end end end else begin debug_r_beat_cnt_i[gen_thread*8+:8] <= 0; end end // Clocked process // DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO axi_data_fifo_v2_1_axic_srl_fifo # ( .C_FAMILY (C_FAMILY), .C_FIFO_WIDTH (8), .C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1), .C_USE_FULL (0) ) debug_r_seq_fifo_multi_thread ( .ACLK (ACLK), .ARESET (ARESET), .S_MESG (DEBUG_A_TRANS_SEQ), .S_VALID (cmd_push[gen_thread]), .S_READY (), .M_MESG (debug_r_trans_seq_i[gen_thread*8+:8]), .M_VALID (), .M_READY (cmd_pop[gen_thread]) ); end // gen_debug_r_multi_thread end // Next gen_thread_loop end // thread control endgenerate endmodule `default_nettype wire
// -- (c) Copyright 1995 - 2012 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------- // The synthesis directives "translate_off/translate_on" specified below are // supported by Xilinx, Mentor Graphics and Synplicity synthesis // tools. Ensure they are correct for your synthesis tool(s). // You must compile the fifo_generator wrapper file when simulating // the core. When compiling the wrapper file, be sure to // reference the XilinxCoreLib Verilog simulation library. For detailed // instructions, please refer to the "CORE Generator Help". `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module axi_data_fifo_v2_1_fifo_gen #( parameter C_FAMILY = "virtex7", parameter integer C_COMMON_CLOCK = 1, parameter integer C_SYNCHRONIZER_STAGE = 3, parameter integer C_FIFO_DEPTH_LOG = 5, parameter integer C_FIFO_WIDTH = 64, parameter C_FIFO_TYPE = "lut" )( clk, rst, wr_clk, wr_en, wr_ready, wr_data, rd_clk, rd_en, rd_valid, rd_data); input clk; input wr_clk; input rd_clk; input rst; input [C_FIFO_WIDTH-1 : 0] wr_data; input wr_en; input rd_en; output [C_FIFO_WIDTH-1 : 0] rd_data; output wr_ready; output rd_valid; wire full; wire empty; wire rd_valid = ~empty; wire wr_ready = ~full; localparam C_MEMORY_TYPE = (C_FIFO_TYPE == "bram")? 1 : 2; localparam C_IMPLEMENTATION_TYPE = (C_COMMON_CLOCK == 1)? 0 : 2; fifo_generator_v12_0 #( .C_COMMON_CLOCK(C_COMMON_CLOCK), .C_DIN_WIDTH(C_FIFO_WIDTH), .C_DOUT_WIDTH(C_FIFO_WIDTH), .C_FAMILY(C_FAMILY), .C_IMPLEMENTATION_TYPE(C_IMPLEMENTATION_TYPE), .C_MEMORY_TYPE(C_MEMORY_TYPE), .C_RD_DEPTH(1<<C_FIFO_DEPTH_LOG), .C_RD_PNTR_WIDTH(C_FIFO_DEPTH_LOG), .C_WR_DEPTH(1<<C_FIFO_DEPTH_LOG), .C_WR_PNTR_WIDTH(C_FIFO_DEPTH_LOG), .C_ADD_NGC_CONSTRAINT(0), .C_APPLICATION_TYPE_AXIS(0), .C_APPLICATION_TYPE_RACH(0), .C_APPLICATION_TYPE_RDCH(0), .C_APPLICATION_TYPE_WACH(0), .C_APPLICATION_TYPE_WDCH(0), .C_APPLICATION_TYPE_WRCH(0), .C_AXIS_TDATA_WIDTH(64), .C_AXIS_TDEST_WIDTH(4), .C_AXIS_TID_WIDTH(8), .C_AXIS_TKEEP_WIDTH(4), .C_AXIS_TSTRB_WIDTH(4), .C_AXIS_TUSER_WIDTH(4), .C_AXIS_TYPE(0), .C_AXI_ADDR_WIDTH(32), .C_AXI_ARUSER_WIDTH(1), .C_AXI_AWUSER_WIDTH(1), .C_AXI_BUSER_WIDTH(1), .C_AXI_DATA_WIDTH(64), .C_AXI_ID_WIDTH(4), .C_AXI_LEN_WIDTH(8), .C_AXI_LOCK_WIDTH(2), .C_AXI_RUSER_WIDTH(1), .C_AXI_TYPE(0), .C_AXI_WUSER_WIDTH(1), .C_COUNT_TYPE(0), .C_DATA_COUNT_WIDTH(6), .C_DEFAULT_VALUE("BlankString"), .C_DIN_WIDTH_AXIS(1), .C_DIN_WIDTH_RACH(32), .C_DIN_WIDTH_RDCH(64), .C_DIN_WIDTH_WACH(32), .C_DIN_WIDTH_WDCH(64), .C_DIN_WIDTH_WRCH(2), .C_DOUT_RST_VAL("0"), .C_ENABLE_RLOCS(0), .C_ENABLE_RST_SYNC(1), .C_ERROR_INJECTION_TYPE(0), .C_ERROR_INJECTION_TYPE_AXIS(0), .C_ERROR_INJECTION_TYPE_RACH(0), .C_ERROR_INJECTION_TYPE_RDCH(0), .C_ERROR_INJECTION_TYPE_WACH(0), .C_ERROR_INJECTION_TYPE_WDCH(0), .C_ERROR_INJECTION_TYPE_WRCH(0), .C_FULL_FLAGS_RST_VAL(0), .C_HAS_ALMOST_EMPTY(0), .C_HAS_ALMOST_FULL(0), .C_HAS_AXIS_TDATA(0), .C_HAS_AXIS_TDEST(0), .C_HAS_AXIS_TID(0), .C_HAS_AXIS_TKEEP(0), .C_HAS_AXIS_TLAST(0), .C_HAS_AXIS_TREADY(1), .C_HAS_AXIS_TSTRB(0), .C_HAS_AXIS_TUSER(0), .C_HAS_AXI_ARUSER(0), .C_HAS_AXI_AWUSER(0), .C_HAS_AXI_BUSER(0), .C_HAS_AXI_RD_CHANNEL(0), .C_HAS_AXI_RUSER(0), .C_HAS_AXI_WR_CHANNEL(0), .C_HAS_AXI_WUSER(0), .C_HAS_BACKUP(0), .C_HAS_DATA_COUNT(0), .C_HAS_DATA_COUNTS_AXIS(0), .C_HAS_DATA_COUNTS_RACH(0), .C_HAS_DATA_COUNTS_RDCH(0), .C_HAS_DATA_COUNTS_WACH(0), .C_HAS_DATA_COUNTS_WDCH(0), .C_HAS_DATA_COUNTS_WRCH(0), .C_HAS_INT_CLK(0), .C_HAS_MASTER_CE(0), .C_HAS_MEMINIT_FILE(0), .C_HAS_OVERFLOW(0), .C_HAS_PROG_FLAGS_AXIS(0), .C_HAS_PROG_FLAGS_RACH(0), .C_HAS_PROG_FLAGS_RDCH(0), .C_HAS_PROG_FLAGS_WACH(0), .C_HAS_PROG_FLAGS_WDCH(0), .C_HAS_PROG_FLAGS_WRCH(0), .C_HAS_RD_DATA_COUNT(0), .C_HAS_RD_RST(0), .C_HAS_RST(1), .C_HAS_SLAVE_CE(0), .C_HAS_SRST(0), .C_HAS_UNDERFLOW(0), .C_HAS_VALID(0), .C_HAS_WR_ACK(0), .C_HAS_WR_DATA_COUNT(0), .C_HAS_WR_RST(0), .C_IMPLEMENTATION_TYPE_AXIS(1), .C_IMPLEMENTATION_TYPE_RACH(1), .C_IMPLEMENTATION_TYPE_RDCH(1), .C_IMPLEMENTATION_TYPE_WACH(1), .C_IMPLEMENTATION_TYPE_WDCH(1), .C_IMPLEMENTATION_TYPE_WRCH(1), .C_INIT_WR_PNTR_VAL(0), .C_INTERFACE_TYPE(0), .C_MIF_FILE_NAME("BlankString"), .C_MSGON_VAL(1), .C_OPTIMIZATION_MODE(0), .C_OVERFLOW_LOW(0), .C_PRELOAD_LATENCY(0), .C_PRELOAD_REGS(1), .C_PRIM_FIFO_TYPE("512x36"), .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022), .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022), .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022), .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022), .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022), .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022), .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), .C_PROG_EMPTY_TYPE(0), .C_PROG_EMPTY_TYPE_AXIS(0), .C_PROG_EMPTY_TYPE_RACH(0), .C_PROG_EMPTY_TYPE_RDCH(0), .C_PROG_EMPTY_TYPE_WACH(0), .C_PROG_EMPTY_TYPE_WDCH(0), .C_PROG_EMPTY_TYPE_WRCH(0), .C_PROG_FULL_THRESH_ASSERT_VAL(31), .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023), .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023), .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023), .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023), .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023), .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023), .C_PROG_FULL_THRESH_NEGATE_VAL(30), .C_PROG_FULL_TYPE(0), .C_PROG_FULL_TYPE_AXIS(0), .C_PROG_FULL_TYPE_RACH(0), .C_PROG_FULL_TYPE_RDCH(0), .C_PROG_FULL_TYPE_WACH(0), .C_PROG_FULL_TYPE_WDCH(0), .C_PROG_FULL_TYPE_WRCH(0), .C_RACH_TYPE(0), .C_RDCH_TYPE(0), .C_RD_DATA_COUNT_WIDTH(6), .C_RD_FREQ(1), .C_REG_SLICE_MODE_AXIS(0), .C_REG_SLICE_MODE_RACH(0), .C_REG_SLICE_MODE_RDCH(0), .C_REG_SLICE_MODE_WACH(0), .C_REG_SLICE_MODE_WDCH(0), .C_REG_SLICE_MODE_WRCH(0), .C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE), .C_UNDERFLOW_LOW(0), .C_USE_COMMON_OVERFLOW(0), .C_USE_COMMON_UNDERFLOW(0), .C_USE_DEFAULT_SETTINGS(0), .C_USE_DOUT_RST(0), .C_USE_ECC(0), .C_USE_ECC_AXIS(0), .C_USE_ECC_RACH(0), .C_USE_ECC_RDCH(0), .C_USE_ECC_WACH(0), .C_USE_ECC_WDCH(0), .C_USE_ECC_WRCH(0), .C_USE_EMBEDDED_REG(0), .C_USE_FIFO16_FLAGS(0), .C_USE_FWFT_DATA_COUNT(1), .C_VALID_LOW(0), .C_WACH_TYPE(0), .C_WDCH_TYPE(0), .C_WRCH_TYPE(0), .C_WR_ACK_LOW(0), .C_WR_DATA_COUNT_WIDTH(6), .C_WR_DEPTH_AXIS(1024), .C_WR_DEPTH_RACH(16), .C_WR_DEPTH_RDCH(1024), .C_WR_DEPTH_WACH(16), .C_WR_DEPTH_WDCH(1024), .C_WR_DEPTH_WRCH(16), .C_WR_FREQ(1), .C_WR_PNTR_WIDTH_AXIS(10), .C_WR_PNTR_WIDTH_RACH(4), .C_WR_PNTR_WIDTH_RDCH(10), .C_WR_PNTR_WIDTH_WACH(4), .C_WR_PNTR_WIDTH_WDCH(10), .C_WR_PNTR_WIDTH_WRCH(4), .C_WR_RESPONSE_LATENCY(1) ) fifo_gen_inst ( .clk(clk), .din(wr_data), .dout(rd_data), .empty(empty), .full(full), .rd_clk(rd_clk), .rd_en(rd_en), .rst(rst), .wr_clk(wr_clk), .wr_en(wr_en), .almost_empty(), .almost_full(), .axi_ar_data_count(), .axi_ar_dbiterr(), .axi_ar_injectdbiterr(1\'b0), .axi_ar_injectsbiterr(1\'b0), .axi_ar_overflow(), .axi_ar_prog_empty(), .axi_ar_prog_empty_thresh(4\'b0), .axi_ar_prog_full(), .axi_ar_prog_full_thresh(4\'b0), .axi_ar_rd_data_count(), .axi_ar_sbiterr(), .axi_ar_underflow(), .axi_ar_wr_data_count(), .axi_aw_data_count(), .axi_aw_dbiterr(), .axi_aw_injectdbiterr(1\'b0), .axi_aw_injectsbiterr(1\'b0), .axi_aw_overflow(), .axi_aw_prog_empty(), .axi_aw_prog_empty_thresh(4\'b0), .axi_aw_prog_full(), .axi_aw_prog_full_thresh(4\'b0), .axi_aw_rd_data_count(), .axi_aw_sbiterr(), .axi_aw_underflow(), .axi_aw_wr_data_count(), .axi_b_data_count(), .axi_b_dbiterr(), .axi_b_injectdbiterr(1\'b0), .axi_b_injectsbiterr(1\'b0), .axi_b_overflow(), .axi_b_prog_empty(), .axi_b_prog_empty_thresh(4\'b0), .axi_b_prog_full(), .axi_b_prog_full_thresh(4\'b0), .axi_b_rd_data_count(), .axi_b_sbiterr(), .axi_b_underflow(), .axi_b_wr_data_count(), .axi_r_data_count(), .axi_r_dbiterr(), .axi_r_injectdbiterr(1\'b0), .axi_r_injectsbiterr(1\'b0), .axi_r_overflow(), .axi_r_prog_empty(), .axi_r_prog_empty_thresh(10\'b0), .axi_r_prog_full(), .axi_r_prog_full_thresh(10\'b0), .axi_r_rd_data_count(), .axi_r_sbiterr(), .axi_r_underflow(), .axi_r_wr_data_count(), .axi_w_data_count(), .axi_w_dbiterr(), .axi_w_injectdbiterr(1\'b0), .axi_w_injectsbiterr(1\'b0), .axi_w_overflow(), .axi_w_prog_empty(), .axi_w_prog_empty_thresh(10\'b0), .axi_w_prog_full(), .axi_w_prog_full_thresh(10\'b0), .axi_w_rd_data_count(), .axi_w_sbiterr(), .axi_w_underflow(), .axi_w_wr_data_count(), .axis_data_count(), .axis_dbiterr(), .axis_injectdbiterr(1\'b0), .axis_injectsbiterr(1\'b0), .axis_overflow(), .axis_prog_empty(), .axis_prog_empty_thresh(10\'b0), .axis_prog_full(), .axis_prog_full_thresh(10\'b0), .axis_rd_data_count(), .axis_sbiterr(), .axis_underflow(), .axis_wr_data_count(), .backup(1\'b0), .backup_marker(1\'b0), .data_count(), .dbiterr(), .injectdbiterr(1\'b0), .injectsbiterr(1\'b0), .int_clk(1\'b0), .m_aclk(1\'b0), .m_aclk_en(1\'b0), .m_axi_araddr(), .m_axi_arburst(), .m_axi_arcache(), .m_axi_arid(), .m_axi_arlen(), .m_axi_arlock(), .m_axi_arprot(), .m_axi_arqos(), .m_axi_arready(1\'b0), .m_axi_arregion(), .m_axi_arsize(), .m_axi_aruser(), .m_axi_arvalid(), .m_axi_awaddr(), .m_axi_awburst(), .m_axi_awcache(), .m_axi_awid(), .m_axi_awlen(), .m_axi_awlock(), .m_axi_awprot(), .m_axi_awqos(), .m_axi_awready(1\'b0), .m_axi_awregion(), .m_axi_awsize(), .m_axi_awuser(), .m_axi_awvalid(), .m_axi_bid(4\'b0), .m_axi_bready(), .m_axi_bresp(2\'b0), .m_axi_buser(1\'b0), .m_axi_bvalid(1\'b0), .m_axi_rdata(64\'b0), .m_axi_rid(4\'b0), .m_axi_rlast(1\'b0), .m_axi_rready(), .m_axi_rresp(2\'b0), .m_axi_ruser(1\'b0), .m_axi_rvalid(1\'b0), .m_axi_wdata(), .m_axi_wid(), .m_axi_wlast(), .m_axi_wready(1\'b0), .m_axi_wstrb(), .m_axi_wuser(), .m_axi_wvalid(), .m_axis_tdata(), .m_axis_tdest(), .m_axis_tid(), .m_axis_tkeep(), .m_axis_tlast(), .m_axis_tready(1\'b0), .m_axis_tstrb(), .m_axis_tuser(), .m_axis_tvalid(), .overflow(), .prog_empty(), .prog_empty_thresh(5\'b0), .prog_empty_thresh_assert(5\'b0), .prog_empty_thresh_negate(5\'b0), .prog_full(), .prog_full_thresh(5\'b0), .prog_full_thresh_assert(5\'b0), .prog_full_thresh_negate(5\'b0), .rd_data_count(), .rd_rst(1\'b0), .s_aclk(1\'b0), .s_aclk_en(1\'b0), .s_aresetn(1\'b0), .s_axi_araddr(32\'b0), .s_axi_arburst(2\'b0), .s_axi_arcache(4\'b0), .s_axi_arid(4\'b0), .s_axi_arlen(8\'b0), .s_axi_arlock(2\'b0), .s_axi_arprot(3\'b0), .s_axi_arqos(4\'b0), .s_axi_arready(), .s_axi_arregion(4\'b0), .s_axi_arsize(3\'b0), .s_axi_aruser(1\'b0), .s_axi_arvalid(1\'b0), .s_axi_awaddr(32\'b0), .s_axi_awburst(2\'b0), .s_axi_awcache(4\'b0), .s_axi_awid(4\'b0), .s_axi_awlen(8\'b0), .s_axi_awlock(2\'b0), .s_axi_awprot(3\'b0), .s_axi_awqos(4\'b0), .s_axi_awready(), .s_axi_awregion(4\'b0), .s_axi_awsize(3\'b0), .s_axi_awuser(1\'b0), .s_axi_awvalid(1\'b0), .s_axi_bid(), .s_axi_bready(1\'b0), .s_axi_bresp(), .s_axi_buser(), .s_axi_bvalid(), .s_axi_rdata(), .s_axi_rid(), .s_axi_rlast(), .s_axi_rready(1\'b0), .s_axi_rresp(), .s_axi_ruser(), .s_axi_rvalid(), .s_axi_wdata(64\'b0), .s_axi_wid(4\'b0), .s_axi_wlast(1\'b0), .s_axi_wready(), .s_axi_wstrb(8\'b0), .s_axi_wuser(1\'b0), .s_axi_wvalid(1\'b0), .s_axis_tdata(64\'b0), .s_axis_tdest(4\'b0), .s_axis_tid(8\'b0), .s_axis_tkeep(4\'b0), .s_axis_tlast(1\'b0), .s_axis_tready(), .s_axis_tstrb(4\'b0), .s_axis_tuser(4\'b0), .s_axis_tvalid(1\'b0), .sbiterr(), .srst(1\'b0), .underflow(), .valid(), .wr_ack(), .wr_data_count(), .wr_rst(1\'b0), .wr_rst_busy(), .rd_rst_busy(), .sleep(1\'b0) ); endmodule
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // // DO NOT MODIFY THIS FILE. // IP VLNV: xilinx.com:ip:axi_crossbar:2.1 // IP Revision: 5 `timescale 1ns/1ps (* DowngradeIPIdentifiedWarnings = "yes" *) module base_zynq_design_xbar_0 ( aclk, aresetn, s_axi_awid, s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid, m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready ); (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) input wire aclk; (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) input wire aresetn; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWID" *) input wire [11 : 0] s_axi_awid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *) input wire [31 : 0] s_axi_awaddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN" *) input wire [7 : 0] s_axi_awlen; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE" *) input wire [2 : 0] s_axi_awsize; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST" *) input wire [1 : 0] s_axi_awburst; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK" *) input wire [0 : 0] s_axi_awlock; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE" *) input wire [3 : 0] s_axi_awcache; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *) input wire [2 : 0] s_axi_awprot; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS" *) input wire [3 : 0] s_axi_awqos; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *) input wire [0 : 0] s_axi_awvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *) output wire [0 : 0] s_axi_awready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *) input wire [31 : 0] s_axi_wdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *) input wire [3 : 0] s_axi_wstrb; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST" *) input wire [0 : 0] s_axi_wlast; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *) input wire [0 : 0] s_axi_wvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *) output wire [0 : 0] s_axi_wready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BID" *) output wire [11 : 0] s_axi_bid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *) output wire [1 : 0] s_axi_bresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *) output wire [0 : 0] s_axi_bvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *) input wire [0 : 0] s_axi_bready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARID" *) input wire [11 : 0] s_axi_arid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *) input wire [31 : 0] s_axi_araddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN" *) input wire [7 : 0] s_axi_arlen; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE" *) input wire [2 : 0] s_axi_arsize; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST" *) input wire [1 : 0] s_axi_arburst; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK" *) input wire [0 : 0] s_axi_arlock; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE" *) input wire [3 : 0] s_axi_arcache; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *) input wire [2 : 0] s_axi_arprot; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS" *) input wire [3 : 0] s_axi_arqos; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *) input wire [0 : 0] s_axi_arvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *) output wire [0 : 0] s_axi_arready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RID" *) output wire [11 : 0] s_axi_rid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *) output wire [31 : 0] s_axi_rdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *) output wire [1 : 0] s_axi_rresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST" *) output wire [0 : 0] s_axi_rlast; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *) output wire [0 : 0] s_axi_rvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) input wire [0 : 0] s_axi_rready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32]" *) output wire [63 : 0] m_axi_awaddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLEN [7:0] [15:8]" *) output wire [15 : 0] m_axi_awlen; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE [2:0] [5:3]" *) output wire [5 : 0] m_axi_awsize; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI AWBURST [1:0] [3:2]" *) output wire [3 : 0] m_axi_awburst; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK [0:0] [1:1]" *) output wire [1 : 0] m_axi_awlock; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE [3:0] [7:4]" *) output wire [7 : 0] m_axi_awcache; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3]" *) output wire [5 : 0] m_axi_awprot; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREGION [3:0] [7:4]" *) output wire [7 : 0] m_axi_awregion; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWQOS [3:0] [7:4]" *) output wire [7 : 0] m_axi_awqos; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1]" *) output wire [1 : 0] m_axi_awvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1]" *) input wire [1 : 0] m_axi_awready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32]" *) output wire [63 : 0] m_axi_wdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4]" *) output wire [7 : 0] m_axi_wstrb; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WLAST [0:0] [1:1]" *) output wire [1 : 0] m_axi_wlast; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1]" *) output wire [1 : 0] m_axi_wvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1]" *) input wire [1 : 0] m_axi_wready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2]" *) input wire [3 : 0] m_axi_bresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1]" *) input wire [1 : 0] m_axi_bvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1]" *) output wire [1 : 0] m_axi_bready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32]" *) output wire [63 : 0] m_axi_araddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLEN [7:0] [15:8]" *) output wire [15 : 0] m_axi_arlen; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE [2:0] [5:3]" *) output wire [5 : 0] m_axi_arsize; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI ARBURST [1:0] [3:2]" *) output wire [3 : 0] m_axi_arburst; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK [0:0] [1:1]" *) output wire [1 : 0] m_axi_arlock; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE [3:0] [7:4]" *) output wire [7 : 0] m_axi_arcache; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3]" *) output wire [5 : 0] m_axi_arprot; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREGION [3:0] [7:4]" *) output wire [7 : 0] m_axi_arregion; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARQOS [3:0] [7:4]" *) output wire [7 : 0] m_axi_arqos; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1]" *) output wire [1 : 0] m_axi_arvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1]" *) input wire [1 : 0] m_axi_arready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32]" *) input wire [63 : 0] m_axi_rdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2]" *) input wire [3 : 0] m_axi_rresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RLAST [0:0] [1:1]" *) input wire [1 : 0] m_axi_rlast; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1]" *) input wire [1 : 0] m_axi_rvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1]" *) output wire [1 : 0] m_axi_rready; axi_crossbar_v2_1_axi_crossbar #( .C_FAMILY("zynq"), .C_NUM_SLAVE_SLOTS(1), .C_NUM_MASTER_SLOTS(2), .C_AXI_ID_WIDTH(12), .C_AXI_ADDR_WIDTH(32), .C_AXI_DATA_WIDTH(32), .C_AXI_PROTOCOL(0), .C_NUM_ADDR_RANGES(1), .C_M_AXI_BASE_ADDR(128\'H00000000400000000000000041200000), .C_M_AXI_ADDR_WIDTH(64\'H0000000d00000010), .C_S_AXI_BASE_ID(32\'H00000000), .C_S_AXI_THREAD_ID_WIDTH(32\'H0000000c), .C_AXI_SUPPORTS_USER_SIGNALS(0), .C_AXI_AWUSER_WIDTH(1), .C_AXI_ARUSER_WIDTH(1), .C_AXI_WUSER_WIDTH(1), .C_AXI_RUSER_WIDTH(1), .C_AXI_BUSER_WIDTH(1), .C_M_AXI_WRITE_CONNECTIVITY(64\'HFFFFFFFFFFFFFFFF), .C_M_AXI_READ_CONNECTIVITY(64\'HFFFFFFFFFFFFFFFF), .C_R_REGISTER(0), .C_S_AXI_SINGLE_THREAD(32\'H00000000), .C_S_AXI_WRITE_ACCEPTANCE(32\'H00000001), .C_S_AXI_READ_ACCEPTANCE(32\'H00000001), .C_M_AXI_WRITE_ISSUING(64\'H0000000100000001), .C_M_AXI_READ_ISSUING(64\'H0000000100000001), .C_S_AXI_ARB_PRIORITY(32\'H00000000), .C_M_AXI_SECURE(32\'H00000000), .C_CONNECTIVITY_MODE(0) ) inst ( .aclk(aclk), .aresetn(aresetn), .s_axi_awid(s_axi_awid), .s_axi_awaddr(s_axi_awaddr), .s_axi_awlen(s_axi_awlen), .s_axi_awsize(s_axi_awsize), .s_axi_awburst(s_axi_awburst), .s_axi_awlock(s_axi_awlock), .s_axi_awcache(s_axi_awcache), .s_axi_awprot(s_axi_awprot), .s_axi_awqos(s_axi_awqos), .s_axi_awuser(1\'H0), .s_axi_awvalid(s_axi_awvalid), .s_axi_awready(s_axi_awready), .s_axi_wid(12\'H000), .s_axi_wdata(s_axi_wdata), .s_axi_wstrb(s_axi_wstrb), .s_axi_wlast(s_axi_wlast), .s_axi_wuser(1\'H0), .s_axi_wvalid(s_axi_wvalid), .s_axi_wready(s_axi_wready), .s_axi_bid(s_axi_bid), .s_axi_bresp(s_axi_bresp), .s_axi_buser(), .s_axi_bvalid(s_axi_bvalid), .s_axi_bready(s_axi_bready), .s_axi_arid(s_axi_arid), .s_axi_araddr(s_axi_araddr), .s_axi_arlen(s_axi_arlen), .s_axi_arsize(s_axi_arsize), .s_axi_arburst(s_axi_arburst), .s_axi_arlock(s_axi_arlock), .s_axi_arcache(s_axi_arcache), .s_axi_arprot(s_axi_arprot), .s_axi_arqos(s_axi_arqos), .s_axi_aruser(1\'H0), .s_axi_arvalid(s_axi_arvalid), .s_axi_arready(s_axi_arready), .s_axi_rid(s_axi_rid), .s_axi_rdata(s_axi_rdata), .s_axi_rresp(s_axi_rresp), .s_axi_rlast(s_axi_rlast), .s_axi_ruser(), .s_axi_rvalid(s_axi_rvalid), .s_axi_rready(s_axi_rready), .m_axi_awid(), .m_axi_awaddr(m_axi_awaddr), .m_axi_awlen(m_axi_awlen), .m_axi_awsize(m_axi_awsize), .m_axi_awburst(m_axi_awburst), .m_axi_awlock(m_axi_awlock), .m_axi_awcache(m_axi_awcache), .m_axi_awprot(m_axi_awprot), .m_axi_awregion(m_axi_awregion), .m_axi_awqos(m_axi_awqos), .m_axi_awuser(), .m_axi_awvalid(m_axi_awvalid), .m_axi_awready(m_axi_awready), .m_axi_wid(), .m_axi_wdata(m_axi_wdata), .m_axi_wstrb(m_axi_wstrb), .m_axi_wlast(m_axi_wlast), .m_axi_wuser(), .m_axi_wvalid(m_axi_wvalid), .m_axi_wready(m_axi_wready), .m_axi_bid(24\'H000000), .m_axi_bresp(m_axi_bresp), .m_axi_buser(2\'H0), .m_axi_bvalid(m_axi_bvalid), .m_axi_bready(m_axi_bready), .m_axi_arid(), .m_axi_araddr(m_axi_araddr), .m_axi_arlen(m_axi_arlen), .m_axi_arsize(m_axi_arsize), .m_axi_arburst(m_axi_arburst), .m_axi_arlock(m_axi_arlock), .m_axi_arcache(m_axi_arcache), .m_axi_arprot(m_axi_arprot), .m_axi_arregion(m_axi_arregion), .m_axi_arqos(m_axi_arqos), .m_axi_aruser(), .m_axi_arvalid(m_axi_arvalid), .m_axi_arready(m_axi_arready), .m_axi_rid(24\'H000000), .m_axi_rdata(m_axi_rdata), .m_axi_rresp(m_axi_rresp), .m_axi_rlast(m_axi_rlast), .m_axi_ruser(2\'H0), .m_axi_rvalid(m_axi_rvalid), .m_axi_rready(m_axi_rready) ); endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: // Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_carry logic. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module generic_baseblocks_v2_1_comparator_static # ( parameter C_FAMILY = "virtex6", // FPGA Family. Current version: virtex6 or spartan6. parameter C_VALUE = 4\'b0, // Static value to compare against. parameter integer C_DATA_WIDTH = 4 // Data width for comparator. ) ( input wire CIN, input wire [C_DATA_WIDTH-1:0] A, output wire COUT ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// // Generate variable for bit vector. genvar bit_cnt; ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Bits per LUT for this architecture. localparam integer C_BITS_PER_LUT = 6; // Constants for packing levels. localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT; // localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT : C_DATA_WIDTH; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// wire [C_FIX_DATA_WIDTH-1:0] a_local; wire [C_FIX_DATA_WIDTH-1:0] b_local; wire [C_NUM_LUT-1:0] sel; wire [C_NUM_LUT:0] carry_local; ///////////////////////////////////////////////////////////////////////////// // ///////////////////////////////////////////////////////////////////////////// generate // Assign input to local vectors. assign carry_local[0] = CIN; // Extend input data to fit. if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}}; assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}}; end else begin : NO_EXTENDED_DATA assign a_local = A; assign b_local = C_VALUE; end // Instantiate one generic_baseblocks_v2_1_carry and per level. for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL // Create the local select signal assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ); // Instantiate each LUT level. generic_baseblocks_v2_1_carry_and # ( .C_FAMILY(C_FAMILY) ) compare_inst ( .COUT (carry_local[bit_cnt+1]), .CIN (carry_local[bit_cnt]), .S (sel[bit_cnt]) ); end // end for bit_cnt // Assign output from local vector. assign COUT = carry_local[C_NUM_LUT]; endgenerate endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: // Optimized Mux using MUXF7/8. // Any generic_baseblocks_v2_1_mux ratio. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // mux_enc // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module generic_baseblocks_v2_1_mux_enc # ( parameter C_FAMILY = "rtl", // FPGA Family. Current version: virtex6 or spartan6. parameter integer C_RATIO = 4, // Mux select ratio. Can be any binary value (>= 1) parameter integer C_SEL_WIDTH = 2, // Log2-ceiling of C_RATIO (>= 1) parameter integer C_DATA_WIDTH = 1 // Data width for generic_baseblocks_v2_1_comparator (>= 1) ) ( input wire [C_SEL_WIDTH-1:0] S, input wire [C_RATIO*C_DATA_WIDTH-1:0] A, output wire [C_DATA_WIDTH-1:0] O, input wire OE ); wire [C_DATA_WIDTH-1:0] o_i; genvar bit_cnt; function [C_DATA_WIDTH-1:0] f_mux ( input [C_SEL_WIDTH-1:0] s, input [C_RATIO*C_DATA_WIDTH-1:0] a ); integer i; reg [C_RATIO*C_DATA_WIDTH-1:0] carry; begin carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1\'b1:1\'b0}} & a[C_DATA_WIDTH-1:0]; for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] = carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] | ({C_DATA_WIDTH{(s==i)?1\'b1:1\'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]); end f_mux = carry[C_DATA_WIDTH*C_RATIO-1:C_DATA_WIDTH*(C_RATIO-1)]; end endfunction function [C_DATA_WIDTH-1:0] f_mux4 ( input [1:0] s, input [4*C_DATA_WIDTH-1:0] a ); integer i; reg [4*C_DATA_WIDTH-1:0] carry; begin carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1\'b1:1\'b0}} & a[C_DATA_WIDTH-1:0]; for (i=1;i<4;i=i+1) begin : gen_carrychain_enc carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] = carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] | ({C_DATA_WIDTH{(s==i)?1\'b1:1\'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]); end f_mux4 = carry[C_DATA_WIDTH*4-1:C_DATA_WIDTH*3]; end endfunction assign O = o_i & {C_DATA_WIDTH{OE}}; // OE is gated AFTER any MUXF7/8 (can only optimize forward into downstream logic) generate if ( C_RATIO < 2 ) begin : gen_bypass assign o_i = A; end else if ( C_FAMILY == "rtl" || C_RATIO < 5 ) begin : gen_rtl assign o_i = f_mux(S, A); end else begin : gen_fpga wire [C_DATA_WIDTH-1:0] l; wire [C_DATA_WIDTH-1:0] h; wire [C_DATA_WIDTH-1:0] ll; wire [C_DATA_WIDTH-1:0] lh; wire [C_DATA_WIDTH-1:0] hl; wire [C_DATA_WIDTH-1:0] hh; case (C_RATIO) 1, 5, 9, 13: assign hh = A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH]; 2, 6, 10, 14: assign hh = S[0] ? A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] : A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ; 3, 7, 11, 15: assign hh = S[1] ? A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] : (S[0] ? A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] : A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] ); 4, 8, 12, 16: assign hh = S[1] ? (S[0] ? A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] : A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ) : (S[0] ? A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] : A[(C_RATIO-4)*C_DATA_WIDTH +: C_DATA_WIDTH] ); 17: assign hh = S[1] ? (S[0] ? A[15*C_DATA_WIDTH +: C_DATA_WIDTH] : A[14*C_DATA_WIDTH +: C_DATA_WIDTH] ) : (S[0] ? A[13*C_DATA_WIDTH +: C_DATA_WIDTH] : A[12*C_DATA_WIDTH +: C_DATA_WIDTH] ); default: assign hh = 0; endcase case (C_RATIO) 5, 6, 7, 8: begin assign l = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]); for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_5_8 MUXF7 mux_s2_inst ( .I0 (l[bit_cnt]), .I1 (hh[bit_cnt]), .S (S[2]), .O (o_i[bit_cnt]) ); end end 9, 10, 11, 12: begin assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]); assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]); for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_9_12 MUXF7 muxf_s2_low_inst ( .I0 (ll[bit_cnt]), .I1 (lh[bit_cnt]), .S (S[2]), .O (l[bit_cnt]) ); MUXF8 muxf_s3_inst ( .I0 (l[bit_cnt]), .I1 (hh[bit_cnt]), .S (S[3]), .O (o_i[bit_cnt]) ); end end 13,14,15,16: begin assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]); assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]); assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]); for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_13_16 MUXF7 muxf_s2_low_inst ( .I0 (ll[bit_cnt]), .I1 (lh[bit_cnt]), .S (S[2]), .O (l[bit_cnt]) ); MUXF7 muxf_s2_hi_inst ( .I0 (hl[bit_cnt]), .I1 (hh[bit_cnt]), .S (S[2]), .O (h[bit_cnt]) ); MUXF8 muxf_s3_inst ( .I0 (l[bit_cnt]), .I1 (h[bit_cnt]), .S (S[3]), .O (o_i[bit_cnt]) ); end end 17: begin assign ll = S[4] ? A[16*C_DATA_WIDTH +: C_DATA_WIDTH] : f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]); // 5-input mux assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]); assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]); for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_17 MUXF7 muxf_s2_low_inst ( .I0 (ll[bit_cnt]), .I1 (lh[bit_cnt]), .S (S[2]), .O (l[bit_cnt]) ); MUXF7 muxf_s2_hi_inst ( .I0 (hl[bit_cnt]), .I1 (hh[bit_cnt]), .S (S[2]), .O (h[bit_cnt]) ); MUXF8 muxf_s3_inst ( .I0 (l[bit_cnt]), .I1 (h[bit_cnt]), .S (S[3]), .O (o_i[bit_cnt]) ); end end default: // If RATIO > 17, use RTL assign o_i = f_mux(S, A); endcase end // gen_fpga endgenerate endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_intr_rd_mem.v * * Date : 2012-11 * * Description : Mimics interconnect for Reads between AFI and DDRC/OCM * *****************************************************************************/ module processing_system7_bfm_v2_0_intr_rd_mem( sw_clk, rstn, full, empty, req, invalid_rd_req, rd_info, RD_DATA_OCM, RD_DATA_DDR, RD_DATA_VALID_OCM, RD_DATA_VALID_DDR ); `include "processing_system7_bfm_v2_0_local_params.v" input sw_clk, rstn; output full, empty; input RD_DATA_VALID_DDR, RD_DATA_VALID_OCM; input [max_burst_bits-1:0] RD_DATA_DDR, RD_DATA_OCM; input req, invalid_rd_req; input [rd_info_bits-1:0] rd_info; reg [intr_cnt_width-1:0] wr_ptr = 0, rd_ptr = 0; reg [rd_afi_fifo_bits-1:0] rd_fifo [0:intr_max_outstanding-1]; // Data, addr, size, burst, len, RID, RRESP, valid bytes wire full, empty; assign empty = (wr_ptr === rd_ptr)?1\'b1: 1\'b0; assign full = ((wr_ptr[intr_cnt_width-1]!== rd_ptr[intr_cnt_width-1]) && (wr_ptr[intr_cnt_width-2:0] === rd_ptr[intr_cnt_width-2:0]))?1\'b1 :1\'b0; /* read from the fifo */ task read_mem; output [rd_afi_fifo_bits-1:0] data; begin data = rd_fifo[rd_ptr[intr_cnt_width-1:0]]; if(rd_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) rd_ptr[intr_cnt_width-2:0] = 0; else rd_ptr = rd_ptr + 1; end endtask reg state; reg invalid_rd; /* write in the fifo */ always@(negedge rstn or posedge sw_clk) begin if(!rstn) begin wr_ptr <= 0; rd_ptr <= 0; state <= 0; invalid_rd <= 0; end else begin case (state) 0 : begin state <= 0; invalid_rd <= 0; if(req)begin state <= 1; invalid_rd <= invalid_rd_req; end end 1 : begin state <= 1; if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd) begin if(RD_DATA_VALID_DDR) rd_fifo[wr_ptr[intr_cnt_width-2:0]] <= {RD_DATA_DDR,rd_info}; else if(RD_DATA_VALID_OCM) rd_fifo[wr_ptr[intr_cnt_width-2:0]] <= {RD_DATA_OCM,rd_info}; else rd_fifo[wr_ptr[intr_cnt_width-2:0]] <= rd_info; if(wr_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) wr_ptr[intr_cnt_width-2:0] <= 0; else wr_ptr <= wr_ptr + 1; state <= 0; invalid_rd <= 0; end end endcase end end endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_local_params.v * * Date : 2012-11 * * Description : Parameters used in Zynq BFM * *****************************************************************************/ /* local */ parameter m_axi_gp0_baseaddr = 32\'h4000_0000; parameter m_axi_gp1_baseaddr = 32\'h8000_0000; parameter m_axi_gp0_highaddr = 32\'h7FFF_FFFF; parameter m_axi_gp1_highaddr = 32\'hBFFF_FFFF; parameter addr_width = 32; // maximum address width parameter data_width = 32; // maximum data width. parameter max_chars = 128; // max characters for file name parameter mem_width = data_width/8; /// memory width in bytes parameter shft_addr_bits = clogb2(mem_width); /// Address to be right shifted parameter int_width = 32; //integre width /* for internal read/write APIs used for data transfers */ parameter max_burst_len = 16; /// maximum brst length on axi parameter max_data_width = 64; // maximum data width for internal AXI bursts parameter max_burst_bits = (max_data_width * max_burst_len); // maximum data width for internal AXI bursts parameter max_burst_bytes = (max_burst_bits)/8; // maximum data bytes in each transfer parameter max_burst_bytes_width = clogb2(max_burst_bytes); // maximum data width for internal AXI bursts parameter max_registers = 32; parameter max_regs_width = clogb2(max_registers); parameter REG_MEM = 2\'b00, DDR_MEM = 2\'b01, OCM_MEM = 2\'b10, INVALID_MEM_TYPE = 2\'b11; /* Interrupt bits supported */ parameter irq_width = 16; /* GP Master0 & Master1 address decode */ parameter GP_M0 = 2\'b01; parameter GP_M1 = 2\'b10; parameter ALL_RANDOM= 2\'b00; parameter ALL_ZEROS = 2\'b01; parameter ALL_ONES = 2\'b10; parameter ddr_start_addr = 32\'h0008_0000; parameter ddr_end_addr = 32\'h3FFF_FFFF; parameter ocm_start_addr = 32\'h0000_0000; parameter ocm_end_addr = 32\'h0003_FFFF; parameter high_ocm_start_addr = 32\'hFFFC_0000; parameter high_ocm_end_addr = 32\'hFFFF_FFFF; parameter ocm_low_addr = 32\'hFFFF_0000; parameter reg_start_addr = 32\'hE000_0000; parameter reg_end_addr = 32\'hF8F0_2F80; /* for Master port APIs and AXI protocol related signal widths*/ parameter axi_burst_len = 16; parameter axi_len_width = clogb2(axi_burst_len); parameter axi_size_width = 3; parameter axi_brst_type_width = 2; parameter axi_lock_width = 2; parameter axi_cache_width = 4; parameter axi_prot_width = 3; parameter axi_rsp_width = 2; parameter axi_mgp_data_width = 32; parameter axi_mgp_id_width = 12; parameter axi_mgp_outstanding = 16; parameter axi_mgp_wr_id = 12\'hC00; parameter axi_mgp_rd_id = 12\'hC0C; parameter axi_mgp0_name = "M_AXI_GP0"; parameter axi_mgp1_name = "M_AXI_GP1"; parameter axi_qos_width = 4; parameter max_transfer_bytes = 128; // For Master APIs. parameter max_transfer_bytes_width = clogb2(max_transfer_bytes); // For Master APIs. /* for GP slave ports*/ parameter axi_sgp_data_width = 32; parameter axi_sgp_id_width = 6; parameter axi_sgp_rd_outstanding = 8; parameter axi_sgp_wr_outstanding = 8; parameter axi_sgp_outstanding = axi_sgp_rd_outstanding + axi_sgp_wr_outstanding; parameter axi_sgp0_name = "S_AXI_GP0"; parameter axi_sgp1_name = "S_AXI_GP1"; /* for ACP slave ports*/ parameter axi_acp_data_width = 64; parameter axi_acp_id_width = 3; parameter axi_acp_rd_outstanding = 7; parameter axi_acp_wr_outstanding = 3; parameter axi_acp_outstanding = axi_acp_rd_outstanding + axi_acp_wr_outstanding; parameter axi_acp_name = "S_AXI_ACP"; /* for HP slave ports*/ parameter axi_hp_id_width = 6; parameter axi_hp_outstanding = 256; /// dynamic based on RCOUNT, WCOUNT .. parameter axi_hp0_name = "S_AXI_HP0"; parameter axi_hp1_name = "S_AXI_HP1"; parameter axi_hp2_name = "S_AXI_HP2"; parameter axi_hp3_name = "S_AXI_HP3"; parameter axi_slv_excl_support = 0; // For Slave ports EXCL access is not supported parameter axi_mst_excl_support = 1; // For Master ports EXCL access is supported /* AXI transfer types */ parameter AXI_FIXED = 2\'b00; parameter AXI_INCR = 2\'b01; parameter AXI_WRAP = 2\'b10; /* Exclusive Access */ parameter AXI_NRML = 2\'b00; parameter AXI_EXCL = 2\'b01; parameter AXI_LOCK = 2\'b10; /* AXI Response types */ parameter AXI_OK = 2\'b00; parameter AXI_EXCL_OK = 2\'b01; parameter AXI_SLV_ERR = 2\'b10; parameter AXI_DEC_ERR = 2\'b11; function automatic integer clogb2; input [31:0] value; begin value = value - 1; for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin value = value >> 1; end end endfunction /* needed only for AFI modules and axi_slave modules for internal WRITE FIFOs and RESP FIFOs and interconnect fifo models */ /* WR FIFO data */ parameter wr_fifo_data_bits = axi_qos_width + addr_width + max_burst_bits + (max_burst_bytes_width+1); parameter wr_bytes_lsb = 0; parameter wr_bytes_msb = max_burst_bytes_width; parameter wr_addr_lsb = wr_bytes_msb + 1; parameter wr_addr_msb = wr_addr_lsb + addr_width-1; parameter wr_data_lsb = wr_addr_msb + 1; parameter wr_data_msb = wr_data_lsb + max_burst_bits-1; parameter wr_qos_lsb = wr_data_msb + 1; parameter wr_qos_msb = wr_qos_lsb + axi_qos_width-1; /* WR AFI FIFO data */ /* ID - 1071:1066 Resp - 1065:1064 data - 1063:40 address - 39:8 valid_bytes - 7:0 */ parameter wr_afi_fifo_data_bits = axi_qos_width + axi_len_width + axi_hp_id_width + axi_rsp_width + max_burst_bits + addr_width + (max_burst_bytes_width+1); parameter wr_afi_bytes_lsb = 0; parameter wr_afi_bytes_msb = max_burst_bytes_width; parameter wr_afi_addr_lsb = wr_afi_bytes_msb + 1; parameter wr_afi_addr_msb = wr_afi_addr_lsb + addr_width-1; parameter wr_afi_data_lsb = wr_afi_addr_msb + 1; parameter wr_afi_data_msb = wr_afi_data_lsb + max_burst_bits-1; parameter wr_afi_rsp_lsb = wr_afi_data_msb + 1; parameter wr_afi_rsp_msb = wr_afi_rsp_lsb + axi_rsp_width-1; parameter wr_afi_id_lsb = wr_afi_rsp_msb + 1; parameter wr_afi_id_msb = wr_afi_id_lsb + axi_hp_id_width-1; parameter wr_afi_ln_lsb = wr_afi_id_msb + 1; parameter wr_afi_ln_msb = wr_afi_ln_lsb + axi_len_width-1; parameter wr_afi_qos_lsb = wr_afi_ln_msb + 1; parameter wr_afi_qos_msb = wr_afi_qos_lsb + axi_qos_width-1; parameter afi_fifo_size = 1024; /// AFI FIFO is stored as 1024-bytes parameter afi_fifo_databits = 64; /// AFI FIFO is stored as 64-bits i.e 8 bytes per location (8 bytes(64-bits) * 128 locations = 1024 bytes) parameter afi_fifo_locations= afi_fifo_size/(afi_fifo_databits/8); /// AFI FIFO is stored as 128-locations with 8 bytes per location /* for interconnect fifo models */ parameter intr_max_outstanding = 8; parameter intr_cnt_width = clogb2(intr_max_outstanding+1); parameter rd_info_bits = addr_width + axi_size_width + axi_brst_type_width + axi_len_width + axi_hp_id_width + axi_rsp_width + (max_burst_bytes_width+1); parameter rd_afi_fifo_bits = max_burst_bits + rd_info_bits ; //Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes parameter rd_afi_bytes_lsb = 0; parameter rd_afi_bytes_msb = max_burst_bytes_width; parameter rd_afi_rsp_lsb = rd_afi_bytes_msb + 1; parameter rd_afi_rsp_msb = rd_afi_rsp_lsb + axi_rsp_width-1; parameter rd_afi_id_lsb = rd_afi_rsp_msb + 1; parameter rd_afi_id_msb = rd_afi_id_lsb + axi_hp_id_width-1; parameter rd_afi_ln_lsb = rd_afi_id_msb + 1; parameter rd_afi_ln_msb = rd_afi_ln_lsb + axi_len_width-1; parameter rd_afi_brst_lsb = rd_afi_ln_msb + 1; parameter rd_afi_brst_msb = rd_afi_brst_lsb + axi_brst_type_width-1; parameter rd_afi_siz_lsb = rd_afi_brst_msb + 1; parameter rd_afi_siz_msb = rd_afi_siz_lsb + axi_size_width-1; parameter rd_afi_addr_lsb = rd_afi_siz_msb + 1; parameter rd_afi_addr_msb = rd_afi_addr_lsb + addr_width-1; parameter rd_afi_data_lsb = rd_afi_addr_msb + 1; parameter rd_afi_data_msb = rd_afi_data_lsb + max_burst_bits-1; /* Latency types */ parameter BEST_CASE = 0; parameter AVG_CASE = 1; parameter WORST_CASE = 2; parameter RANDOM_CASE = 3; /* Latency Parameters ACP */ parameter acp_wr_min = 27; parameter acp_wr_avg = 16; parameter acp_wr_max = 21; parameter acp_rd_min = 34; parameter acp_rd_avg = 125; parameter acp_rd_max = 130; /* Latency Parameters GP */ parameter gp_wr_min = 46; parameter gp_wr_avg = 16; parameter gp_wr_max = 21; parameter gp_rd_min = 38; parameter gp_rd_avg = 125; parameter gp_rd_max = 130; /* Latency Parameters HP */ parameter afi_wr_min = 37; parameter afi_wr_avg = 41; parameter afi_wr_max = 42; parameter afi_rd_min = 41; parameter afi_rd_avg = 221; parameter afi_rd_max = 229; /* ID VALID and INVALID */ parameter secure_access_enabled = 0; parameter id_invalid = 0; parameter id_valid = 1; /* Display */ parameter DISP_INFO = "*ZYNQ_BFM_INFO"; parameter DISP_WARN = "*ZYNQ_BFM_WARNING"; parameter DISP_ERR = "*ZYNQ_BFM_ERROR"; parameter DISP_INT_INFO = "ZYNQ_BFM_INT_INFO";
/////////////////////////////////////////////////////////////////////////////// // // File name: axi_protocol_converter_v2_1_b2s_r_channel.v // // Description: // Read data channel module to buffer read data from MC, ignore // extra data in case of BL8 and send the data to AXI. // The MC will send out the read data as it is ready and it has to be // accepted. The read data FIFO in the axi_protocol_converter_v2_1_b2s_r_channel module will buffer // the data before being sent to AXI. The address channel module will // send the transaction information for every command that is sent to the // MC. The transaction information will be buffered in a transaction FIFO. // Based on the transaction FIFO information data will be ignored in // BL8 mode and the last signal to the AXI will be asserted. /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_protocol_converter_v2_1_b2s_r_channel # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // Width of ID signals. // Range: >= 1. parameter integer C_ID_WIDTH = 4, // Width of AXI xDATA and MCB xx_data // Range: 32, 64, 128. parameter integer C_DATA_WIDTH = 32 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire clk , input wire reset , output wire [C_ID_WIDTH-1:0] s_rid , output wire [C_DATA_WIDTH-1:0] s_rdata , output wire [1:0] s_rresp , output wire s_rlast , output wire s_rvalid , input wire s_rready , input wire [C_DATA_WIDTH-1:0] m_rdata , input wire [1:0] m_rresp , input wire m_rvalid , output wire m_rready , // Connections to/from axi_protocol_converter_v2_1_b2s_ar_channel module input wire r_push , output wire r_full , // length not needed. Can be removed. input wire [C_ID_WIDTH-1:0] r_arid , input wire r_rlast ); //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// localparam P_WIDTH = 1+C_ID_WIDTH; localparam P_DEPTH = 32; localparam P_AWIDTH = 5; localparam P_D_WIDTH = C_DATA_WIDTH + 2; // rd data FIFO depth varies based on burst length. // For Bl8 it is two times the size of transaction FIFO. // Only in 2:1 mode BL8 transactions will happen which results in // two beats of read data per read transaction. localparam P_D_DEPTH = 32; localparam P_D_AWIDTH = 5; //////////////////////////////////////////////////////////////////////////////// // Wire and register declarations //////////////////////////////////////////////////////////////////////////////// wire [C_ID_WIDTH+1-1:0] trans_in; wire [C_ID_WIDTH+1-1:0] trans_out; wire tr_empty; wire rhandshake; wire r_valid_i; wire [P_D_WIDTH-1:0] rd_data_fifo_in; wire [P_D_WIDTH-1:0] rd_data_fifo_out; wire rd_en; wire rd_full; wire rd_empty; wire rd_a_full; wire fifo_a_full; reg [C_ID_WIDTH-1:0] r_arid_r; reg r_rlast_r; reg r_push_r; wire fifo_full; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// assign s_rresp = rd_data_fifo_out[P_D_WIDTH-1:C_DATA_WIDTH]; assign s_rid = trans_out[1+:C_ID_WIDTH]; assign s_rdata = rd_data_fifo_out[C_DATA_WIDTH-1:0]; assign s_rlast = trans_out[0]; assign s_rvalid = ~rd_empty & ~tr_empty; // assign MCB outputs assign rd_en = rhandshake & (~rd_empty); assign rhandshake =(s_rvalid & s_rready); // register for timing always @(posedge clk) begin r_arid_r <= r_arid; r_rlast_r <= r_rlast; r_push_r <= r_push; end assign trans_in[0] = r_rlast_r; assign trans_in[1+:C_ID_WIDTH] = r_arid_r; // rd data fifo axi_protocol_converter_v2_1_b2s_simple_fifo #( .C_WIDTH (P_D_WIDTH), .C_AWIDTH (P_D_AWIDTH), .C_DEPTH (P_D_DEPTH) ) rd_data_fifo_0 ( .clk ( clk ) , .rst ( reset ) , .wr_en ( m_rvalid & m_rready ) , .rd_en ( rd_en ) , .din ( rd_data_fifo_in ) , .dout ( rd_data_fifo_out ) , .a_full ( rd_a_full ) , .full ( rd_full ) , .a_empty ( ) , .empty ( rd_empty ) ); assign rd_data_fifo_in = {m_rresp, m_rdata}; axi_protocol_converter_v2_1_b2s_simple_fifo #( .C_WIDTH (P_WIDTH), .C_AWIDTH (P_AWIDTH), .C_DEPTH (P_DEPTH) ) transaction_fifo_0 ( .clk ( clk ) , .rst ( reset ) , .wr_en ( r_push_r ) , .rd_en ( rd_en ) , .din ( trans_in ) , .dout ( trans_out ) , .a_full ( fifo_a_full ) , .full ( ) , .a_empty ( ) , .empty ( tr_empty ) ); assign fifo_full = fifo_a_full | rd_a_full ; assign r_full = fifo_full ; assign m_rready = ~rd_a_full; endmodule `default_nettype wire
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // // DO NOT MODIFY THIS FILE. // IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1 // IP Revision: 4 (* X_CORE_INFO = "axi_protocol_converter_v2_1_axi_protocol_converter,Vivado 2014.4" *) (* CHECK_LICENSE_TYPE = "base_zynq_design_auto_pc_1,axi_protocol_converter_v2_1_axi_protocol_converter,{}" *) (* CORE_GENERATION_INFO = "base_zynq_design_auto_pc_1,axi_protocol_converter_v2_1_axi_protocol_converter,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=0,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) module base_zynq_design_auto_pc_1 ( aclk, aresetn, s_axi_awid, s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid, m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_arid, m_axi_araddr, m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready ); (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *) input wire aclk; (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *) input wire aresetn; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input wire [11 : 0] s_axi_awid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input wire [31 : 0] s_axi_awaddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input wire [3 : 0] s_axi_awlen; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input wire [2 : 0] s_axi_awsize; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input wire [1 : 0] s_axi_awburst; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input wire [1 : 0] s_axi_awlock; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input wire [3 : 0] s_axi_awcache; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input wire [2 : 0] s_axi_awprot; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *) input wire [3 : 0] s_axi_awqos; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input wire s_axi_awvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output wire s_axi_awready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *) input wire [11 : 0] s_axi_wid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input wire [31 : 0] s_axi_wdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input wire [3 : 0] s_axi_wstrb; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input wire s_axi_wlast; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input wire s_axi_wvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output wire s_axi_wready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) output wire [11 : 0] s_axi_bid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output wire [1 : 0] s_axi_bresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output wire s_axi_bvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input wire s_axi_bready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) input wire [11 : 0] s_axi_arid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input wire [31 : 0] s_axi_araddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input wire [3 : 0] s_axi_arlen; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input wire [2 : 0] s_axi_arsize; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input wire [1 : 0] s_axi_arburst; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input wire [1 : 0] s_axi_arlock; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input wire [3 : 0] s_axi_arcache; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input wire [2 : 0] s_axi_arprot; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) input wire [3 : 0] s_axi_arqos; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input wire s_axi_arvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output wire s_axi_arready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) output wire [11 : 0] s_axi_rid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output wire [31 : 0] s_axi_rdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output wire [1 : 0] s_axi_rresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output wire s_axi_rlast; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output wire s_axi_rvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input wire s_axi_rready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *) output wire [11 : 0] m_axi_awid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output wire [31 : 0] m_axi_awaddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *) output wire [7 : 0] m_axi_awlen; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *) output wire [2 : 0] m_axi_awsize; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *) output wire [1 : 0] m_axi_awburst; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *) output wire [0 : 0] m_axi_awlock; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *) output wire [3 : 0] m_axi_awcache; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output wire [2 : 0] m_axi_awprot; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *) output wire [3 : 0] m_axi_awregion; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *) output wire [3 : 0] m_axi_awqos; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output wire m_axi_awvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input wire m_axi_awready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output wire [31 : 0] m_axi_wdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output wire [3 : 0] m_axi_wstrb; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *) output wire m_axi_wlast; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output wire m_axi_wvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input wire m_axi_wready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *) input wire [11 : 0] m_axi_bid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input wire [1 : 0] m_axi_bresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input wire m_axi_bvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output wire m_axi_bready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *) output wire [11 : 0] m_axi_arid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output wire [31 : 0] m_axi_araddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) output wire [7 : 0] m_axi_arlen; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *) output wire [2 : 0] m_axi_arsize; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *) output wire [1 : 0] m_axi_arburst; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *) output wire [0 : 0] m_axi_arlock; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *) output wire [3 : 0] m_axi_arcache; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output wire [2 : 0] m_axi_arprot; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *) output wire [3 : 0] m_axi_arregion; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *) output wire [3 : 0] m_axi_arqos; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output wire m_axi_arvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input wire m_axi_arready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *) input wire [11 : 0] m_axi_rid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input wire [31 : 0] m_axi_rdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input wire [1 : 0] m_axi_rresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *) input wire m_axi_rlast; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input wire m_axi_rvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) output wire m_axi_rready; axi_protocol_converter_v2_1_axi_protocol_converter #( .C_FAMILY("zynq"), .C_M_AXI_PROTOCOL(0), .C_S_AXI_PROTOCOL(1), .C_IGNORE_ID(0), .C_AXI_ID_WIDTH(12), .C_AXI_ADDR_WIDTH(32), .C_AXI_DATA_WIDTH(32), .C_AXI_SUPPORTS_WRITE(1), .C_AXI_SUPPORTS_READ(1), .C_AXI_SUPPORTS_USER_SIGNALS(0), .C_AXI_AWUSER_WIDTH(1), .C_AXI_ARUSER_WIDTH(1), .C_AXI_WUSER_WIDTH(1), .C_AXI_RUSER_WIDTH(1), .C_AXI_BUSER_WIDTH(1), .C_TRANSLATION_MODE(2) ) inst ( .aclk(aclk), .aresetn(aresetn), .s_axi_awid(s_axi_awid), .s_axi_awaddr(s_axi_awaddr), .s_axi_awlen(s_axi_awlen), .s_axi_awsize(s_axi_awsize), .s_axi_awburst(s_axi_awburst), .s_axi_awlock(s_axi_awlock), .s_axi_awcache(s_axi_awcache), .s_axi_awprot(s_axi_awprot), .s_axi_awregion(4\'H0), .s_axi_awqos(s_axi_awqos), .s_axi_awuser(1\'H0), .s_axi_awvalid(s_axi_awvalid), .s_axi_awready(s_axi_awready), .s_axi_wid(s_axi_wid), .s_axi_wdata(s_axi_wdata), .s_axi_wstrb(s_axi_wstrb), .s_axi_wlast(s_axi_wlast), .s_axi_wuser(1\'H0), .s_axi_wvalid(s_axi_wvalid), .s_axi_wready(s_axi_wready), .s_axi_bid(s_axi_bid), .s_axi_bresp(s_axi_bresp), .s_axi_buser(), .s_axi_bvalid(s_axi_bvalid), .s_axi_bready(s_axi_bready), .s_axi_arid(s_axi_arid), .s_axi_araddr(s_axi_araddr), .s_axi_arlen(s_axi_arlen), .s_axi_arsize(s_axi_arsize), .s_axi_arburst(s_axi_arburst), .s_axi_arlock(s_axi_arlock), .s_axi_arcache(s_axi_arcache), .s_axi_arprot(s_axi_arprot), .s_axi_arregion(4\'H0), .s_axi_arqos(s_axi_arqos), .s_axi_aruser(1\'H0), .s_axi_arvalid(s_axi_arvalid), .s_axi_arready(s_axi_arready), .s_axi_rid(s_axi_rid), .s_axi_rdata(s_axi_rdata), .s_axi_rresp(s_axi_rresp), .s_axi_rlast(s_axi_rlast), .s_axi_ruser(), .s_axi_rvalid(s_axi_rvalid), .s_axi_rready(s_axi_rready), .m_axi_awid(m_axi_awid), .m_axi_awaddr(m_axi_awaddr), .m_axi_awlen(m_axi_awlen), .m_axi_awsize(m_axi_awsize), .m_axi_awburst(m_axi_awburst), .m_axi_awlock(m_axi_awlock), .m_axi_awcache(m_axi_awcache), .m_axi_awprot(m_axi_awprot), .m_axi_awregion(m_axi_awregion), .m_axi_awqos(m_axi_awqos), .m_axi_awuser(), .m_axi_awvalid(m_axi_awvalid), .m_axi_awready(m_axi_awready), .m_axi_wid(), .m_axi_wdata(m_axi_wdata), .m_axi_wstrb(m_axi_wstrb), .m_axi_wlast(m_axi_wlast), .m_axi_wuser(), .m_axi_wvalid(m_axi_wvalid), .m_axi_wready(m_axi_wready), .m_axi_bid(m_axi_bid), .m_axi_bresp(m_axi_bresp), .m_axi_buser(1\'H0), .m_axi_bvalid(m_axi_bvalid), .m_axi_bready(m_axi_bready), .m_axi_arid(m_axi_arid), .m_axi_araddr(m_axi_araddr), .m_axi_arlen(m_axi_arlen), .m_axi_arsize(m_axi_arsize), .m_axi_arburst(m_axi_arburst), .m_axi_arlock(m_axi_arlock), .m_axi_arcache(m_axi_arcache), .m_axi_arprot(m_axi_arprot), .m_axi_arregion(m_axi_arregion), .m_axi_arqos(m_axi_arqos), .m_axi_aruser(), .m_axi_arvalid(m_axi_arvalid), .m_axi_arready(m_axi_arready), .m_axi_rid(m_axi_rid), .m_axi_rdata(m_axi_rdata), .m_axi_rresp(m_axi_rresp), .m_axi_rlast(m_axi_rlast), .m_axi_ruser(1\'H0), .m_axi_rvalid(m_axi_rvalid), .m_axi_rready(m_axi_rready) ); endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_intr_wr_mem.v * * Date : 2012-11 * * Description : Mimics interconnect for Writes between AFI and DDRC/OCM * *****************************************************************************/ module processing_system7_bfm_v2_0_intr_wr_mem( sw_clk, rstn, full, WR_DATA_ACK_OCM, WR_DATA_ACK_DDR, WR_ADDR, WR_DATA, WR_BYTES, WR_QOS, WR_DATA_VALID_OCM, WR_DATA_VALID_DDR ); `include "processing_system7_bfm_v2_0_local_params.v" /* local parameters for interconnect wr fifo model */ input sw_clk, rstn; output full; input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM; output reg WR_DATA_VALID_DDR, WR_DATA_VALID_OCM; output reg [max_burst_bits-1:0] WR_DATA; output reg [addr_width-1:0] WR_ADDR; output reg [max_burst_bytes_width:0] WR_BYTES; output reg [axi_qos_width-1:0] WR_QOS; reg [intr_cnt_width-1:0] wr_ptr = 0, rd_ptr = 0; reg [wr_fifo_data_bits-1:0] wr_fifo [0:intr_max_outstanding-1]; wire empty; assign empty = (wr_ptr === rd_ptr)?1\'b1: 1\'b0; assign full = ((wr_ptr[intr_cnt_width-1]!== rd_ptr[intr_cnt_width-1]) && (wr_ptr[intr_cnt_width-2:0] === rd_ptr[intr_cnt_width-2:0]))?1\'b1 :1\'b0; parameter SEND_DATA = 0, WAIT_ACK = 1; reg state; task automatic write_mem; input [wr_fifo_data_bits-1:0] data; begin wr_fifo[wr_ptr[intr_cnt_width-2:0]] = data; if(wr_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) wr_ptr[intr_cnt_width-2:0] = 0; else wr_ptr = wr_ptr + 1; end endtask always@(negedge rstn or posedge sw_clk) begin if(!rstn) begin wr_ptr <= 0; rd_ptr <= 0; WR_DATA_VALID_DDR = 1\'b0; WR_DATA_VALID_OCM = 1\'b0; WR_QOS = 0; state = SEND_DATA; end else begin case(state) SEND_DATA :begin state = SEND_DATA; WR_DATA_VALID_OCM = 1\'b0; WR_DATA_VALID_DDR = 1\'b0; if(!empty) begin WR_DATA = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_data_msb : wr_data_lsb]; WR_ADDR = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_addr_msb : wr_addr_lsb]; WR_BYTES = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_bytes_msb : wr_bytes_lsb]; WR_QOS = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_qos_msb : wr_qos_lsb]; state = WAIT_ACK; case(decode_address(wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_addr_msb : wr_addr_lsb])) OCM_MEM : WR_DATA_VALID_OCM = 1; DDR_MEM : WR_DATA_VALID_DDR = 1; default : state = SEND_DATA; endcase rd_ptr <= rd_ptr+1; if(rd_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) rd_ptr[intr_cnt_width-2:0] = 0; end end WAIT_ACK :begin state = WAIT_ACK; if(WR_DATA_ACK_OCM | WR_DATA_ACK_DDR) begin WR_DATA_VALID_OCM = 1\'b0; WR_DATA_VALID_DDR = 1\'b0; state = SEND_DATA; end end endcase end end endmodule
`timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_protocol_converter_v2_1_b2s_ar_channel # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // Width of ID signals. // Range: >= 1. parameter integer C_ID_WIDTH = 4, // Width of AxADDR // Range: 32. parameter integer C_AXI_ADDR_WIDTH = 32 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// // AXI Slave Interface // Slave Interface System Signals input wire clk , input wire reset , // Slave Interface Read Address Ports input wire [C_ID_WIDTH-1:0] s_arid , input wire [C_AXI_ADDR_WIDTH-1:0] s_araddr , input wire [7:0] s_arlen , input wire [2:0] s_arsize , input wire [1:0] s_arburst , input wire s_arvalid , output wire s_arready , output wire m_arvalid , output wire [C_AXI_ADDR_WIDTH-1:0] m_araddr , input wire m_arready , // Connections to/from axi_protocol_converter_v2_1_b2s_r_channel module output wire [C_ID_WIDTH-1:0] r_arid , output wire r_push , output wire r_rlast , input wire r_full ); //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// wire next ; wire next_pending ; wire a_push; wire incr_burst; reg [C_ID_WIDTH-1:0] s_arid_r; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// // Translate the AXI transaction to the MC transaction(s) axi_protocol_converter_v2_1_b2s_cmd_translator # ( .C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ) cmd_translator_0 ( .clk ( clk ) , .reset ( reset ) , .s_axaddr ( s_araddr ) , .s_axlen ( s_arlen ) , .s_axsize ( s_arsize ) , .s_axburst ( s_arburst ) , .s_axhandshake ( s_arvalid & a_push ) , .incr_burst ( incr_burst ) , .m_axaddr ( m_araddr ) , .next ( next ) , .next_pending ( next_pending ) ); axi_protocol_converter_v2_1_b2s_rd_cmd_fsm ar_cmd_fsm_0 ( .clk ( clk ) , .reset ( reset ) , .s_arready ( s_arready ) , .s_arvalid ( s_arvalid ) , .s_arlen ( s_arlen ) , .m_arvalid ( m_arvalid ) , .m_arready ( m_arready ) , .next ( next ) , .next_pending ( next_pending ) , .data_ready ( ~r_full ) , .a_push ( a_push ) , .r_push ( r_push ) ); // these signals can be moved out of this block to the top level. assign r_arid = s_arid_r; assign r_rlast = ~next_pending; always @(posedge clk) begin s_arid_r <= s_arid ; end endmodule `default_nettype wire
/***************************************************************************** * File : processing_system7_bfm_v2_0_apis.v * * Date : 2012-11 * * Description : Set of Zynq BFM APIs that are used for writing tests. * *****************************************************************************/ /* API for setting the STOP_ON_ERROR*/ task automatic set_stop_on_error; input LEVEL; begin $display("[%0d] : %0s : Setting Stop On Error as %0b",$time, DISP_INFO, LEVEL); STOP_ON_ERROR = LEVEL; M_AXI_GP0.master.set_stop_on_error(LEVEL); M_AXI_GP1.master.set_stop_on_error(LEVEL); S_AXI_GP0.slave.set_stop_on_error(LEVEL); S_AXI_GP1.slave.set_stop_on_error(LEVEL); S_AXI_HP0.slave.set_stop_on_error(LEVEL); S_AXI_HP1.slave.set_stop_on_error(LEVEL); S_AXI_HP2.slave.set_stop_on_error(LEVEL); S_AXI_HP3.slave.set_stop_on_error(LEVEL); S_AXI_ACP.slave.set_stop_on_error(LEVEL); M_AXI_GP0.STOP_ON_ERROR = LEVEL; M_AXI_GP1.STOP_ON_ERROR = LEVEL; S_AXI_GP0.STOP_ON_ERROR = LEVEL; S_AXI_GP1.STOP_ON_ERROR = LEVEL; S_AXI_HP0.STOP_ON_ERROR = LEVEL; S_AXI_HP1.STOP_ON_ERROR = LEVEL; S_AXI_HP2.STOP_ON_ERROR = LEVEL; S_AXI_HP3.STOP_ON_ERROR = LEVEL; S_AXI_ACP.STOP_ON_ERROR = LEVEL; end endtask /* API for setting the verbosity for channel level info*/ task automatic set_channel_level_info; input [1023:0] name; input LEVEL; begin $display("[%0d] : [%0s] : %0s Port/s : Setting Channel Level Info as %0b",$time, DISP_INFO, name , LEVEL); case(name) "M_AXI_GP0" : M_AXI_GP0.master.set_channel_level_info(LEVEL); "M_AXI_GP1" : M_AXI_GP1.master.set_channel_level_info(LEVEL); "S_AXI_GP0" : S_AXI_GP0.slave.set_channel_level_info(LEVEL); "S_AXI_GP1" : S_AXI_GP1.slave.set_channel_level_info(LEVEL); "S_AXI_HP0" : S_AXI_HP0.slave.set_channel_level_info(LEVEL); "S_AXI_HP1" : S_AXI_HP1.slave.set_channel_level_info(LEVEL); "S_AXI_HP2" : S_AXI_HP2.slave.set_channel_level_info(LEVEL); "S_AXI_HP3" : S_AXI_HP3.slave.set_channel_level_info(LEVEL); "S_AXI_ACP" : S_AXI_ACP.slave.set_channel_level_info(LEVEL); "ALL" : begin M_AXI_GP0.master.set_channel_level_info(LEVEL); M_AXI_GP1.master.set_channel_level_info(LEVEL); S_AXI_GP0.slave.set_channel_level_info(LEVEL); S_AXI_GP1.slave.set_channel_level_info(LEVEL); S_AXI_HP0.slave.set_channel_level_info(LEVEL); S_AXI_HP1.slave.set_channel_level_info(LEVEL); S_AXI_HP2.slave.set_channel_level_info(LEVEL); S_AXI_HP3.slave.set_channel_level_info(LEVEL); S_AXI_ACP.slave.set_channel_level_info(LEVEL); end default : $display("[%0d] : %0s : Invalid Port name (%0s)",$time, DISP_ERR, name); endcase end endtask /* API for setting the verbosity for function level info*/ task automatic set_function_level_info; input [1023:0] name; input LEVEL; begin $display("[%0d] : [%0s] : %0s Port/s : Setting Function Level Info as %0b",$time, DISP_INFO, name , LEVEL); case(name) "M_AXI_GP0" : M_AXI_GP0.master.set_function_level_info(LEVEL); "M_AXI_GP1" : M_AXI_GP1.master.set_function_level_info(LEVEL); "S_AXI_GP0" : S_AXI_GP0.slave.set_function_level_info(LEVEL); "S_AXI_GP1" : S_AXI_GP1.slave.set_function_level_info(LEVEL); "S_AXI_HP0" : S_AXI_HP0.slave.set_function_level_info(LEVEL); "S_AXI_HP1" : S_AXI_HP1.slave.set_function_level_info(LEVEL); "S_AXI_HP2" : S_AXI_HP2.slave.set_function_level_info(LEVEL); "S_AXI_HP3" : S_AXI_HP3.slave.set_function_level_info(LEVEL); "S_AXI_ACP" : S_AXI_ACP.slave.set_function_level_info(LEVEL); "ALL" : begin M_AXI_GP0.master.set_function_level_info(LEVEL); M_AXI_GP1.master.set_function_level_info(LEVEL); S_AXI_GP0.slave.set_function_level_info(LEVEL); S_AXI_GP1.slave.set_function_level_info(LEVEL); S_AXI_HP0.slave.set_function_level_info(LEVEL); S_AXI_HP1.slave.set_function_level_info(LEVEL); S_AXI_HP2.slave.set_function_level_info(LEVEL); S_AXI_HP3.slave.set_function_level_info(LEVEL); S_AXI_ACP.slave.set_function_level_info(LEVEL); end default : $display("[%0d] : %0s : Invalid Port name (%0s)",$time, DISP_ERR, name); endcase end endtask /* API for setting the Message verbosity */ task automatic set_debug_level_info; input LEVEL; begin $display("[%0d] : %0s : Setting Debug Level Info as %0b",$time, DISP_INFO, LEVEL); DEBUG_INFO = LEVEL; M_AXI_GP0.DEBUG_INFO = LEVEL; M_AXI_GP1.DEBUG_INFO = LEVEL; S_AXI_GP0.DEBUG_INFO = LEVEL; S_AXI_GP1.DEBUG_INFO = LEVEL; S_AXI_HP0.DEBUG_INFO = LEVEL; S_AXI_HP1.DEBUG_INFO = LEVEL; S_AXI_HP2.DEBUG_INFO = LEVEL; S_AXI_HP3.DEBUG_INFO = LEVEL; S_AXI_ACP.DEBUG_INFO = LEVEL; end endtask /* API for setting ARQos Values */ task automatic set_arqos; input [1023:0] name; input [axi_qos_width-1:0] value; begin $display("[%0d] : [%0s] : %0s Port/s : Setting AWQOS as %0b",$time, DISP_INFO, name , value); case(name) "S_AXI_GP0" : S_AXI_GP0.set_arqos(value); "S_AXI_GP1" : S_AXI_GP1.set_arqos(value); "S_AXI_HP0" : S_AXI_HP0.set_arqos(value); "S_AXI_HP1" : S_AXI_HP1.set_arqos(value); "S_AXI_HP2" : S_AXI_HP2.set_arqos(value); "S_AXI_HP3" : S_AXI_HP3.set_arqos(value); "S_AXI_ACP" : S_AXI_ACP.set_arqos(value); default : $display("[%0d] : %0s : Invalid Slave Port name (%0s)",$time, DISP_ERR, name); endcase end endtask /* API for setting AWQos Values */ task automatic set_awqos; input [1023:0] name; input [axi_qos_width-1:0] value; begin $display("[%0d] : [%0s] : %0s Port/s : Setting ARQOS as %0b",$time, DISP_INFO, name , value); case(name) "S_AXI_GP0" : S_AXI_GP0.set_awqos(value); "S_AXI_GP1" : S_AXI_GP1.set_awqos(value); "S_AXI_HP0" : S_AXI_HP0.set_awqos(value); "S_AXI_HP1" : S_AXI_HP1.set_awqos(value); "S_AXI_HP2" : S_AXI_HP2.set_awqos(value); "S_AXI_HP3" : S_AXI_HP3.set_awqos(value); "S_AXI_ACP" : S_AXI_ACP.set_awqos(value); default : $display("[%0d] : %0s : Invalid Slave Port (%0s)",$time, DISP_ERR, name); endcase end endtask /* API for soft reset control */ task automatic fpga_soft_reset; input[data_width-1:0] reset_ctrl; begin if(DEBUG_INFO) $display("[%0d] : %0s : FPGA Soft Reset called for 0x%0h",$time, DISP_INFO, reset_ctrl); gen_rst.fpga_soft_reset(reset_ctrl); end endtask /* API for pre-loading memories from (DDR/OCM model) */ task automatic pre_load_mem_from_file; input [(max_chars*8)-1:0] file_name; input [addr_width-1:0] start_addr; input [int_width-1:0] no_of_bytes; reg [1:0] mem_type; integer succ; begin mem_type = decode_address(start_addr); succ = $fopen(file_name,"r"); if(succ == 0) begin $display("[%0d] : %0s : \'%0s\' doesn\'t exist. \'pre_load_mem_from_file\' call failed ...\ ",$time, DISP_ERR, file_name); if(STOP_ON_ERROR) $stop; end else if(check_addr_aligned(start_addr)) begin case(mem_type) OCM_MEM : begin ocmc.ocm.pre_load_mem_from_file(file_name,start_addr,no_of_bytes); if(DEBUG_INFO) $display("[%0d] : %0s : Starting Address(0x%0h) -> OCM Memory is pre-loaded with %0d bytes of data from file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name); end DDR_MEM : begin ddrc.ddr.pre_load_mem_from_file(file_name,start_addr,no_of_bytes); if(DEBUG_INFO) $display("[%0d] : %0s : Starting Address(0x%0h) -> DDR Memory is pre-loaded with %0d bytes of data from file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name); end default : begin $display("[%0d] : %0s : Address(0x%0h) is out-of-range. \'pre_load_mem_from_file\' call failed ...\ ",$time, DISP_ERR, start_addr); if(STOP_ON_ERROR) $stop; end endcase end else begin $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. \'pre_load_mem_from_file\' call failed ...",$time, DISP_ERR, start_addr); if(STOP_ON_ERROR) $stop; end end endtask /* API for pre-loading memories (DDR/OCM) */ task automatic pre_load_mem; input [1:0] data_type; input [addr_width-1:0] start_addr; input [int_width-1:0] no_of_bytes; reg [1:0] mem_type; begin mem_type = decode_address(start_addr); if(check_addr_aligned(start_addr)) begin case(mem_type) OCM_MEM : begin ocmc.ocm.pre_load_mem(data_type,start_addr,no_of_bytes); if(DEBUG_INFO) $display("[%0d] : %0s : Starting Address(0x%0h) -> OCM Memory is pre-loaded with %0d bytes of data",$time, DISP_INFO, start_addr, no_of_bytes); end DDR_MEM : begin ddrc.ddr.pre_load_mem(data_type,start_addr,no_of_bytes); if(DEBUG_INFO) $display("[%0d] : %0s : Starting Address(0x%0h) -> DDR Memory is pre-loaded with %0d bytes of data",$time, DISP_INFO, start_addr, no_of_bytes); end default : begin $display("[%0d] : %0s : Address(0x%0h) is out-of-range. \'pre_load_mem\' call failed ...\ ",$time, DISP_ERR, start_addr); if(STOP_ON_ERROR) $stop; end endcase end else begin $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. \'pre_load_mem\' call failed ...",$time, DISP_ERR, start_addr); if(STOP_ON_ERROR) $stop; end end endtask /* API for backdoor write to memories (DDR/OCM) */ task automatic write_mem; input [max_burst_bits-1 :0] data; input [addr_width-1:0] start_addr; input [max_burst_bytes_width:0] no_of_bytes; reg [1:0] mem_type; integer succ; begin mem_type = decode_address(start_addr); if(check_addr_aligned(start_addr)) begin case(mem_type) OCM_MEM : begin ocmc.ocm.write_mem(data,start_addr,no_of_bytes); if(DEBUG_INFO) $display("[%0d] : %0s : Starting Address(0x%0h) -> Write %0d bytes of data to OCM Memory",$time, DISP_INFO, start_addr, no_of_bytes); end DDR_MEM : begin ddrc.ddr.write_mem(data,start_addr,no_of_bytes); if(DEBUG_INFO) $display("[%0d] : %0s : Starting Address(0x%0h) -> Write %0d bytes of data to DDR Memory",$time, DISP_INFO, start_addr, no_of_bytes); end default : begin $display("[%0d] : %0s : Address(0x%0h) is out-of-range. \'write_mem\' call failed ...\ ",$time, DISP_ERR, start_addr); if(STOP_ON_ERROR) $stop; end endcase end else begin $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. \'write_mem\' call failed ...",$time, DISP_ERR, start_addr); if(STOP_ON_ERROR) $stop; end end endtask /* read_memory */ task automatic read_mem; input [addr_width-1:0] start_addr; input [max_burst_bytes_width :0] no_of_bytes; output[max_burst_bits-1 :0] data; reg [1:0] mem_type; integer succ; begin mem_type = decode_address(start_addr); if(check_addr_aligned(start_addr)) begin case(mem_type) OCM_MEM : begin ocmc.ocm.read_mem(data,start_addr,no_of_bytes); if(DEBUG_INFO) $display("[%0d] : %0s : Starting Address(0x%0h) -> Read %0d bytes of data from OCM Memory ",$time, DISP_INFO, start_addr, no_of_bytes); end DDR_MEM : begin ddrc.ddr.read_mem(data,start_addr,no_of_bytes); if(DEBUG_INFO) $display("[%0d] : %0s : Starting Address(0x%0h) -> Read %0d bytes of data from DDR Memory",$time, DISP_INFO, start_addr, no_of_bytes); end default : begin $display("[%0d] : %0s : Address(0x%0h) is out-of-range. \'read_mem\' call failed ...\ ",$time, DISP_ERR, start_addr); if(STOP_ON_ERROR) $stop; end endcase end else begin $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. \'read_mem\' call failed ...",$time, DISP_ERR, start_addr); if(STOP_ON_ERROR) $stop; end end endtask /* API for backdoor read to memories (DDR/OCM) */ task automatic peek_mem_to_file; input [(max_chars*8)-1:0] file_name; input [addr_width-1:0] start_addr; input [int_width-1:0] no_of_bytes; reg [1:0] mem_type; integer succ; begin mem_type = decode_address(start_addr); if(check_addr_aligned(start_addr)) begin case(mem_type) OCM_MEM : begin ocmc.ocm.peek_mem_to_file(file_name,start_addr,no_of_bytes); if(DEBUG_INFO) $display("[%0d] : %0s : Starting Address(0x%0h) -> Peeked %0d bytes of data from OCM Memory to file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name); end DDR_MEM : begin ddrc.ddr.peek_mem_to_file(file_name,start_addr,no_of_bytes); if(DEBUG_INFO) $display("[%0d] : %0s : Starting Address(0x%0h) -> Peeked %0d bytes of data from DDR Memory to file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name); end default : begin $display("[%0d] : %0s : Address(0x%0h) is out-of-range. \'peek_mem_to_file\' call failed ...\ ",$time, DISP_ERR, start_addr); if(STOP_ON_ERROR) $stop; end endcase end else begin $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. \'peek_mem_to_file\' call failed ...",$time, DISP_ERR, start_addr); if(STOP_ON_ERROR) $stop; end end endtask /* API to read interrupt status */ task automatic read_interrupt; output[irq_width-1:0] irq_status; begin irq_status = IRQ_F2P; if(DEBUG_INFO) $display("[%0d] : %0s : Reading Interrupt Status as 0x%0h",$time, DISP_INFO, irq_status); end endtask /* API to wait on interrup */ task automatic wait_interrupt; input [3:0] irq; output[irq_width-1:0] irq_status; begin if(DEBUG_INFO) $display("[%0d] : %0s : Waiting on Interrupt irq[%0d]",$time, DISP_INFO, irq); case(irq) 0 : wait(IRQ_F2P[0] === 1\'b1); 1 : wait(IRQ_F2P[1] === 1\'b1); 2 : wait(IRQ_F2P[2] === 1\'b1); 3 : wait(IRQ_F2P[3] === 1\'b1); 4 : wait(IRQ_F2P[4] === 1\'b1); 5 : wait(IRQ_F2P[5] === 1\'b1); 6 : wait(IRQ_F2P[6] === 1\'b1); 7 : wait(IRQ_F2P[7] === 1\'b1); 8 : wait(IRQ_F2P[8] === 1\'b1); 8 : wait(IRQ_F2P[9] === 1\'b1); 10: wait(IRQ_F2P[10] === 1\'b1); 11: wait(IRQ_F2P[11] === 1\'b1); 12: wait(IRQ_F2P[12] === 1\'b1); 13: wait(IRQ_F2P[13] === 1\'b1); 14: wait(IRQ_F2P[14] === 1\'b1); 15: wait(IRQ_F2P[15] === 1\'b1); default : $display("[%0d] : %0s : Only 16 Interrupt lines (irq_fp0:irq_fp15) are supported",$time, DISP_ERR); endcase if(DEBUG_INFO) $display("[%0d] : %0s : Received Interrupt irq[%0d]",$time, DISP_INFO, irq); irq_status = IRQ_F2P; end endtask /* API to wait for a certain match pattern*/ task automatic wait_mem_update; input[addr_width-1:0] address; input[data_width-1:0] data_in; output[data_width-1:0] data_out; reg[data_width-1:0] datao; begin if(mem_update_key) begin mem_update_key = 0; if(DEBUG_INFO) $display("[%0d] : %0s : \'wait_mem_update\' called for Address(0x%0h) , Match Pattern(0x%0h) \ ",$time, DISP_INFO, address, data_in); if(check_addr_aligned(address)) begin ddrc.ddr.wait_mem_update(address, datao); if(datao != data_in)begin $display("[%0d] : %0s : Address(0x%0h) -> DATA PATTERN MATCH FAILED, Expected data = 0x%0h, Received data = 0x%0h \ ",$time, DISP_ERR, address, data_in,datao); $stop; end else $display("[%0d] : %0s : Address(0x%0h) -> DATA PATTERN(0x%0h) MATCHED \ ",$time, DISP_INFO, address, data_in); data_out = datao; end else begin $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. \'wait_mem_update\' call failed ...\ ",$time, DISP_ERR, address); if(STOP_ON_ERROR) $stop; end mem_update_key = 1; end else $display("[%0d] : %0s : One instance of \'wait_mem_update\' thread is already running.Only one instance can be called at a time ...\ ",$time, DISP_WARN); end endtask /* API to initiate a WRITE transaction on one of the AXI-Master ports*/ task automatic write_from_file; input [(max_chars*8)-1:0] file_name; input [addr_width-1:0] start_addr; input [int_width-1:0] wr_size; output [axi_rsp_width-1:0] response; integer succ; begin succ = $fopen(file_name,"r"); if(succ == 0) begin $display("[%0d] : %0s : \'%0s\' doesn\'t exist. \'write_from_file\' call failed ...\ ",$time, DISP_ERR, file_name); if(STOP_ON_ERROR) $stop; end else if(!check_master_address(start_addr)) begin $display("[%0d] : %0s : Master Address(0x%0h) is out of range\ ",$time, DISP_ERR, start_addr); if(STOP_ON_ERROR) $stop; end else if(check_addr_aligned(start_addr)) begin $fclose(succ); case(start_addr[31:30]) GP_M0 : begin if(DEBUG_INFO) $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes from file %0s",$time, DISP_INFO, start_addr, wr_size, file_name); M_AXI_GP0.write_from_file(file_name,start_addr,wr_size,response); if(DEBUG_INFO) $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h)",$time, DISP_INFO, start_addr); end GP_M1 : begin if(DEBUG_INFO) $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes from file %0s",$time, DISP_INFO, start_addr, wr_size, file_name); M_AXI_GP1.write_from_file(file_name,start_addr,wr_size,response); if(DEBUG_INFO) $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h)",$time, DISP_INFO, start_addr); end default : begin $display("[%0d] : %0s : Invalid Address(0x%0h) \'write_from_file\' call failed ...\ ",$time, DISP_ERR, start_addr); end endcase end else begin $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. \'write_from_file\' call failed ...\ ",$time, DISP_ERR, start_addr); if(STOP_ON_ERROR) $stop; end end endtask /* API to initiate a READ transaction on one of the AXI-Master ports*/ task automatic read_to_file; input [(max_chars*8)-1:0] file_name; input [addr_width-1:0] start_addr; input [int_width-1:0] rd_size; output [axi_rsp_width-1:0] response; begin if(!check_master_address(start_addr)) begin $display("[%0d] : %0s : Master Address(0x%0h) is out of range\ ",$time, DISP_ERR , start_addr); if(STOP_ON_ERROR) $stop; end else if(check_addr_aligned(start_addr)) begin case(start_addr[31:30]) GP_M0 : begin if(DEBUG_INFO) $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes to file %0s",$time, DISP_INFO, start_addr, rd_size, file_name); M_AXI_GP0.read_to_file(file_name,start_addr,rd_size,response); if(DEBUG_INFO) $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h)",$time, DISP_INFO, start_addr); end GP_M1 : begin if(DEBUG_INFO) $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes to file %0s",$time, DISP_INFO, start_addr, rd_size, file_name); M_AXI_GP1.read_to_file(file_name,start_addr,rd_size,response); if(DEBUG_INFO) $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h)",$time, DISP_INFO, start_addr); end default : $display("[%0d] : %0s : Invalid Address(0x%0h) \'read_to_file\' call failed ...\ ",$time, DISP_ERR, start_addr); endcase end else begin $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. \'read_to_file\' call failed ...\ ",$time, DISP_ERR, start_addr); if(STOP_ON_ERROR) $stop; end end endtask /* API to initiate a WRITE transaction(<= 128 bytes) on one of the AXI-Master ports*/ task automatic write_data; input [addr_width-1:0] start_addr; input [max_transfer_bytes_width:0] wr_size; input [(max_transfer_bytes*8)-1:0] w_data; output [axi_rsp_width-1:0] response; reg[511:0] rsp; begin if(!check_master_address(start_addr)) begin $display("[%0d] : %0s : Master Address(0x%0h) is out of range. \'write_data\' call failed ...\ ",$time, DISP_ERR, start_addr); if(STOP_ON_ERROR) $stop; end else if(wr_size > max_transfer_bytes) begin $display("[%0d] : %0s : Byte Size supported is 128 bytes only. \'write_data\' call failed ...\ ",$time, DISP_ERR, start_addr); if(STOP_ON_ERROR) $stop; end else if(start_addr[31:30] === GP_M0) begin if(DEBUG_INFO) $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, wr_size); M_AXI_GP0.write_data(start_addr,wr_size,w_data,response); rsp = get_resp(response); if(DEBUG_INFO) $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response \'%0s\'",$time, DISP_INFO, start_addr, rsp); end else if(start_addr[31:30] === GP_M1) begin if(DEBUG_INFO) $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, wr_size); M_AXI_GP1.write_data(start_addr,wr_size,w_data,response); rsp = get_resp(response); if(DEBUG_INFO) $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response \'%0s\'",$time, DISP_INFO, start_addr, rsp); end else $display("[%0d] : %0s : Invalid Address(0x%0h) \'write_data\' call failed ...\ ",$time, DISP_ERR, start_addr); end endtask /* API to initiate a READ transaction(<= 128 bytes) on one of the AXI-Master ports*/ task automatic read_data; input [addr_width-1:0] start_addr; input [max_transfer_bytes_width:0] rd_size; output[(max_transfer_bytes*8)-1:0] rd_data; output [axi_rsp_width-1:0] response; reg[511:0] rsp; begin if(!check_master_address(start_addr)) begin $display("[%0d] : %0s : Master Address(0x%0h) is out of range \'read_data\' call failed ...\ ",$time, DISP_ERR, start_addr); if(STOP_ON_ERROR) $stop; end else if(rd_size > max_transfer_bytes) begin $display("[%0d] : %0s : Byte Size supported is 128 bytes only.\'read_data\' call failed ... \ ",$time, DISP_ERR, start_addr); if(STOP_ON_ERROR) $stop; end else if(start_addr[31:30] === GP_M0) begin if(DEBUG_INFO) $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes",$time, DISP_INFO, start_addr, rd_size); M_AXI_GP0.read_data(start_addr,rd_size,rd_data,response); rsp = get_resp(response); if(DEBUG_INFO) $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h) with Response \'%0s\'",$time, DISP_INFO, start_addr, rsp); end else if(start_addr[31:30] === GP_M1) begin if(DEBUG_INFO) $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes",$time, DISP_INFO, start_addr, rd_size); M_AXI_GP1.read_data(start_addr,rd_size,rd_data,response); rsp = get_resp(response); if(DEBUG_INFO) $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h) with Response \'%0s\'",$time, DISP_INFO, start_addr, rsp); end else $display("[%0d] : %0s : Invalid Address(0x%0h) \'read_data\' call failed ...\ ",$time, DISP_ERR, start_addr); end endtask /* Hooks to call to BFM APIs */ task automatic write_burst(input [addr_width-1:0] start_addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response); reg[511:0] rsp; begin if(!check_master_address(start_addr)) begin $display("[%0d] : %0s : Master Address(0x%0h) is out of range. \'write_burst\' call failed ...\ ",$time, DISP_ERR, start_addr); if(STOP_ON_ERROR) $stop; end else if(start_addr[31:30] === GP_M0) begin if(DEBUG_INFO) $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize); M_AXI_GP0.write_burst(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response); rsp = get_resp(response); if(DEBUG_INFO) $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response \'%0s\'",$time, DISP_INFO, start_addr, rsp); end else if(start_addr[31:30] === GP_M1) begin if(DEBUG_INFO) $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize); M_AXI_GP1.write_burst(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response); rsp = get_resp(response); if(DEBUG_INFO) $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response \'%0s\'",$time, DISP_INFO, start_addr, rsp); end else $display("[%0d] : %0s : Invalid Address(0x%0h) \'write_burst\' call failed ... \ ",$time, DISP_ERR, start_addr); end endtask task automatic write_burst_concurrent(input [addr_width-1:0] start_addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response); reg[511:0] rsp; /// string for response begin if(!check_master_address(start_addr)) begin $display("[%0d] : %0s : Master Address(0x%0h) is out of range. \'write_burst_concurrent\' call failed ...\ ",$time, DISP_ERR, start_addr); if(STOP_ON_ERROR) $stop; end else if(start_addr[31:30] === GP_M0) begin if(DEBUG_INFO) $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize); M_AXI_GP0.write_burst_concurrent(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response); rsp = get_resp(response); if(DEBUG_INFO) $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response \'%0s\'",$time, DISP_INFO, start_addr, rsp); end else if(start_addr[31:30] === GP_M1) begin if(DEBUG_INFO) $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize); M_AXI_GP1.write_burst_concurrent(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response); rsp = get_resp(response); if(DEBUG_INFO) $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response \'%0s\'",$time, DISP_INFO, start_addr, rsp); end else $display("[%0d] : %0s : Invalid Address(0x%0h) \'write_burst_concurrent\' call failed ... \ ",$time, DISP_ERR, start_addr); end endtask task automatic read_burst; input [addr_width-1:0] start_addr; input [axi_len_width-1:0] len; input [axi_size_width-1:0] siz; input [axi_brst_type_width-1:0] burst; input [axi_lock_width-1:0] lck; input [axi_cache_width-1:0] cache; input [axi_prot_width-1:0] prot; output [(axi_mgp_data_width*axi_burst_len)-1:0] data; output [(axi_rsp_width*axi_burst_len)-1:0] response; reg[511:0] rsp; begin if(!check_master_address(start_addr)) begin $display("[%0d] : %0s : Master Address(0x%0h) is out of range. \'read_burst\' call failed ...\ ",$time, DISP_ERR, start_addr); if(STOP_ON_ERROR) $stop; end else if(start_addr[31:30] === GP_M0) begin if(DEBUG_INFO) $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read",$time, DISP_INFO, start_addr); M_AXI_GP0.read_burst(start_addr,len,siz,burst,lck,cache,prot,data,response); rsp = get_resp(response); if(DEBUG_INFO) $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h) with Response \'%0s\'",$time, DISP_INFO, start_addr, rsp); end else if(start_addr[31:30] === GP_M1) begin if(DEBUG_INFO) $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read",$time, DISP_INFO, start_addr); M_AXI_GP1.read_burst(start_addr,len,siz,burst,lck,cache,prot,data,response); rsp = get_resp(response); if(DEBUG_INFO) $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h) with Response \'%0s\'",$time, DISP_INFO, start_addr, rsp); end else $display("[%0d] : %0s : Invalid Address(0x%0h) \'read_burst\' call failed ... \ ",$time, DISP_ERR, start_addr); end endtask task automatic wait_reg_update; input [addr_width-1:0] addr; input [data_width-1:0] data_i; input [data_width-1:0] mask_i; input [int_width-1:0] time_interval; input [int_width-1:0] time_out; output [data_width-1:0] data_o; reg upd_done0; reg upd_done1; begin if(!check_master_address(addr)) begin $display("[%0d] : %0s : Address(0x%0h) is out of range. \'wait_reg_update\' call failed ...\ ",$time, DISP_ERR, addr); if(STOP_ON_ERROR) $stop; end else if(addr[31:30] === GP_M0) begin if(reg_update_key_0) begin reg_update_key_0 = 0; if(DEBUG_INFO) $display("[%0d] : M_AXI_GP0 : %0s : \'wait_reg_update\' called for Address(0x%0h), Mask(0x%0h), Match Pattern(0x%0h) \ ",$time, DISP_INFO, addr, mask_i, data_i); M_AXI_GP0.wait_reg_update(addr, data_i, mask_i, time_interval, time_out, data_o, upd_done0); if(DEBUG_INFO && upd_done0) $display("[%0d] : M_AXI_GP0 : %0s : Register mapped at Address(0x%0h) is updated ",$time, DISP_INFO, addr); reg_update_key_0 = 1; end else $display("[%0d] : M_AXI_GP0 : One instance of \'wait_reg_update\' thread is already running.Only one instance can be called at a time ...\ ",$time, DISP_WARN); end else if(addr[31:30] === GP_M1) begin if(reg_update_key_1) begin reg_update_key_1 = 0; if(DEBUG_INFO) $display("[%0d] : M_AXI_GP1 : %0s : \'wait_reg_update\' called for Address(0x%0h), Mask(0x%0h), Match Pattern(0x%0h) \ ",$time, DISP_INFO, addr, mask_i, data_i); M_AXI_GP1.wait_reg_update(addr, data_i, mask_i, time_interval, time_out, data_o, upd_done1); if(DEBUG_INFO && upd_done1) $display("[%0d] : M_AXI_GP1 : %0s : Register mapped at Address(0x%0h) is updated ",$time, DISP_INFO, addr); reg_update_key_1 = 1; end else $display("[%0d] : M_AXI_GP1 : One instance of \'wait_reg_update\' thread is already running.Only one instance can be called at a time ...\ ",$time, DISP_WARN); end else $display("[%0d] : %0s : Invalid Address(0x%0h) \'wait_reg_update\' call failed ... \ ",$time, DISP_ERR, addr); end endtask /* API to read register map */ task read_register_map; input [addr_width-1:0] start_addr; input [max_regs_width:0] no_of_registers; output[max_burst_bits-1 :0] data; reg [max_regs_width:0] no_of_regs; begin no_of_regs = no_of_registers; if(no_of_registers > 32) begin $display("[%0d] : %0s : No_of_Registers(%0d) exceeds the supported number (32).\ Only 32 registers will be read.",$time, DISP_ERR, start_addr); no_of_regs = 32; end if(check_addr_aligned(start_addr)) begin if(decode_address(start_addr) == REG_MEM) begin if(DEBUG_INFO) $display("[%0d] : %0s : Reading Registers starting address (0x%0h) -> %0d registers",$time, DISP_INFO, start_addr,no_of_regs ); regc.regm.read_reg_mem(data,start_addr,no_of_regs*4); /// as each register is of 4 bytes if(DEBUG_INFO) $display("[%0d] : %0s : DONE -> Reading Registers starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INFO, start_addr, data ); end else begin $display("[%0d] : %0s : Invalid Address(0x%0h) for Register Read. \'read_register_map\' call failed ...",$time, DISP_ERR, start_addr); end end else begin data = 0; $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. \'read_register_map\' call failed ...",$time, DISP_ERR, start_addr); end end endtask /* API to read single register */ task read_register; input [addr_width-1:0] addr; output[data_width-1:0] data; begin if(check_addr_aligned(addr)) begin if(decode_address(addr) == REG_MEM) begin if(DEBUG_INFO) $display("[%0d] : %0s : Reading Register (0x%0h) ",$time, DISP_INFO, addr ); regc.regm.get_data(addr >> 2, data); if(DEBUG_INFO) $display("[%0d] : %0s : DONE -> Reading Register (0x%0h), Data returned(0x%0h)",$time, DISP_INFO, addr, data ); end else begin $display("[%0d] : %0s : Invalid Address(0x%0h) for Register Read. \'read_register\' call failed ...",$time, DISP_ERR, addr); end end else begin data = 0; $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. \'read_register\' call failed ...",$time, DISP_ERR, addr); end end endtask /* API to set the AXI-Slave profile*/ task automatic set_slave_profile; input[1023:0] name; input[1:0] latency ; begin if(DEBUG_INFO) $display("[%0d] : %0s : %0s Port/s : Setting Slave profile",$time, DISP_INFO, name); case(name) "S_AXI_GP0" : S_AXI_GP0.set_latency_type(latency); "S_AXI_GP1" : S_AXI_GP1.set_latency_type(latency); "S_AXI_HP0" : S_AXI_HP0.set_latency_type(latency); "S_AXI_HP1" : S_AXI_HP1.set_latency_type(latency); "S_AXI_HP2" : S_AXI_HP2.set_latency_type(latency); "S_AXI_HP3" : S_AXI_HP3.set_latency_type(latency); "S_AXI_ACP" : S_AXI_ACP.set_latency_type(latency); "ALL" : begin S_AXI_GP0.set_latency_type(latency); S_AXI_GP1.set_latency_type(latency); S_AXI_HP0.set_latency_type(latency); S_AXI_HP1.set_latency_type(latency); S_AXI_HP2.set_latency_type(latency); S_AXI_HP3.set_latency_type(latency); S_AXI_ACP.set_latency_type(latency); end endcase end endtask /*------------------------------ LOCAL APIs ------------------------------------------------ */ /* local API for address decoding*/ function automatic [1:0] decode_address; input [addr_width-1:0] address; begin if(!C_HIGH_OCM_EN && (address < ocm_end_addr || address >= ocm_low_addr )) decode_address = OCM_MEM; /// OCM else if(address >= ddr_start_addr && address <= ddr_end_addr) decode_address = DDR_MEM; /// DDR else if(C_HIGH_OCM_EN && address >= high_ocm_start_addr) decode_address = OCM_MEM; /// OCM else if(address >= reg_start_addr && reg_start_addr <= reg_end_addr) decode_address = REG_MEM; /// Register Map else decode_address = INVALID_MEM_TYPE; /// ERROR in Address end endfunction /* local API for checking address is 32-bit (4-byte) aligned */ function automatic check_addr_aligned; input [addr_width-1:0] address; begin if((address%4) !=0 ) begin // check_addr_aligned = 0; ///not_aligned end else check_addr_aligned = 1; end endfunction /* local API to check address for GP Masters */ function check_master_address; input [addr_width-1:0] address; begin if(address >= m_axi_gp0_baseaddr && address <= m_axi_gp0_highaddr) check_master_address = 1\'b1; else if(address >= m_axi_gp1_baseaddr && address <= m_axi_gp1_highaddr) check_master_address = 1\'b1; else check_master_address = 1\'b0; /// ERROR in Address end endfunction /* Response decode */ function automatic [511:0] get_resp; input[axi_rsp_width-1:0] response; begin case(response) 2\'b00 : get_resp = "OKAY"; 2\'b01 : get_resp = "EXOKAY"; 2\'b10 : get_resp = "SLVERR"; 2\'b11 : get_resp = "DECERR"; endcase end endfunction
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: Addr Decoder // Each received address is compared to base and high address pairs for each // of a set of decode targets. // The matching target\'s index (if any) is output combinatorially. // If the decode is successful (matches any target), the MATCH output is asserted. // For each target, a set of alternative address ranges may be specified. // The base and high address pairs are formatted as a pair of 2-dimensional arrays, // alternative address ranges iterate within each target. // The alternative range which matches the address is also output as REGION. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // addr_decoder // comparator_static // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module axi_crossbar_v2_1_addr_decoder # ( parameter C_FAMILY = "none", parameter integer C_NUM_TARGETS = 2, // Number of decode targets = [1:16] parameter integer C_NUM_TARGETS_LOG = 1, // Log2(C_NUM_TARGETS) parameter integer C_NUM_RANGES = 1, // Number of alternative ranges that // can match each target [1:16] parameter integer C_ADDR_WIDTH = 32, // Width of decoder operand and of // each base and high address [2:64] parameter integer C_TARGET_ENC = 0, // Enable encoded target output parameter integer C_TARGET_HOT = 1, // Enable 1-hot target output parameter integer C_REGION_ENC = 0, // Enable REGION output parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1\'b1}}, parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1\'b0}}, parameter [C_NUM_TARGETS:0] C_TARGET_QUAL = {C_NUM_TARGETS{1\'b1}}, // Indicates whether each target has connectivity. // Format: C_NUM_TARGETS{Bit1}. parameter integer C_RESOLUTION = 0, // Number of low-order ADDR bits that can be ignored when decoding. parameter integer C_COMPARATOR_THRESHOLD = 6 // Number of decoded ADDR bits above which will implement comparator_static. ) ( input wire [C_ADDR_WIDTH-1:0] ADDR, // Decoder input operand output wire [C_NUM_TARGETS-1:0] TARGET_HOT, // Target matching address (1-hot) output wire [C_NUM_TARGETS_LOG-1:0] TARGET_ENC, // Target matching address (encoded) output wire MATCH, // Decode successful output wire [3:0] REGION // Range within target matching address (encoded) ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. genvar target_cnt; genvar region_cnt; ///////////////////////////////////////////////////////////////////////////// // Function to detect addrs is in the addressable range. // Only compare 4KB page address (ignore low-order 12 bits) function decode_address; input [C_ADDR_WIDTH-1:0] base, high, addr; reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] mask; reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] addr_page; reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] base_page; reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] high_page; begin addr_page = addr[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION]; base_page = base[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION]; high_page = high[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION]; if (base[C_ADDR_WIDTH-1] & ~high[C_ADDR_WIDTH-1]) begin decode_address = 1\'b0; end else begin mask = base_page ^ high_page; if ( (base_page & ~mask) == (addr_page & ~mask) ) begin decode_address = 1\'b1; end else begin decode_address = 1\'b0; end end end endfunction // Generates a binary coded from onehotone encoded function [3:0] f_hot2enc ( input [15:0] one_hot ); begin f_hot2enc[0] = |(one_hot & 16\'b1010101010101010); f_hot2enc[1] = |(one_hot & 16\'b1100110011001100); f_hot2enc[2] = |(one_hot & 16\'b1111000011110000); f_hot2enc[3] = |(one_hot & 16\'b1111111100000000); end endfunction ///////////////////////////////////////////////////////////////////////////// // Internal signals wire [C_NUM_TARGETS-1:0] TARGET_HOT_I; // Target matching address (1-hot). wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT; // For address hit (1-hot). wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT_REG; // For address hit (1-hot). wire [C_NUM_RANGES-1:0] REGION_HOT; // Reginon matching address (1-hot). wire [3:0] TARGET_ENC_I; // Internal version of encoded hit. ///////////////////////////////////////////////////////////////////////////// // Generate detection per region per target. generate for (target_cnt = 0; target_cnt < C_NUM_TARGETS; target_cnt = target_cnt + 1) begin : gen_target for (region_cnt = 0; region_cnt < C_NUM_RANGES; region_cnt = region_cnt + 1) begin : gen_region // Detect if this is an address hit (including used region decoding). if ((C_ADDR_WIDTH - C_RESOLUTION) > C_COMPARATOR_THRESHOLD) begin : gen_comparator_static if (C_TARGET_QUAL[target_cnt] && ((C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] == 0) || (C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] != 0))) begin : gen_addr_range generic_baseblocks_v2_1_comparator_static # ( .C_FAMILY("rtl"), .C_VALUE(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION]), .C_DATA_WIDTH(C_ADDR_WIDTH-C_RESOLUTION) ) addr_decode_comparator ( .CIN(1\'b1), .A(ADDR[C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] & ~(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] ^ C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION])), .COUT(ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt]) ); end else begin : gen_null_range assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = 1\'b0; end end else begin : gen_no_comparator_static assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = C_TARGET_QUAL[target_cnt] ? decode_address( C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH], C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH], ADDR) : 1\'b0; end // gen_comparator_static assign ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS+target_cnt] = ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt]; assign REGION_HOT[region_cnt] = | ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS +: C_NUM_TARGETS]; end // gen_region // All regions are non-overlapping // => Or all the region detections for this target to determine if it is a hit. assign TARGET_HOT_I[target_cnt] = | ADDRESS_HIT[target_cnt*C_NUM_RANGES +: C_NUM_RANGES]; end // gen_target endgenerate ///////////////////////////////////////////////////////////////////////////// // All regions are non-overlapping // => Or all the target hit detections if it is a match. assign MATCH = | TARGET_HOT_I; ///////////////////////////////////////////////////////////////////////////// // Assign conditional onehot target output signal. generate if (C_TARGET_HOT == 1) begin : USE_TARGET_ONEHOT assign TARGET_HOT = MATCH ? TARGET_HOT_I : 1; end else begin : NO_TARGET_ONEHOT assign TARGET_HOT = {C_NUM_TARGETS{1\'b0}}; end endgenerate ///////////////////////////////////////////////////////////////////////////// // Assign conditional encoded target output signal. generate if (C_TARGET_ENC == 1) begin : USE_TARGET_ENCODED assign TARGET_ENC_I = f_hot2enc(TARGET_HOT_I); assign TARGET_ENC = TARGET_ENC_I[C_NUM_TARGETS_LOG-1:0]; end else begin : NO_TARGET_ENCODED assign TARGET_ENC = {C_NUM_TARGETS_LOG{1\'b0}}; end endgenerate ///////////////////////////////////////////////////////////////////////////// // Assign conditional encoded region output signal. generate if (C_TARGET_ENC == 1) begin : USE_REGION_ENCODED assign REGION = f_hot2enc(REGION_HOT); end else begin : NO_REGION_ENCODED assign REGION = 4\'b0; end endgenerate endmodule
//--------------------------------------------------------------------------- // Testbench //--------------------------------------------------------------------------- // //*************************************************************************** // DISCLAIMER OF LIABILITY // // This file contains proprietary and confidential information of // Xilinx, Inc. ("Xilinx"), that is distributed under a license // from Xilinx, and may be used, copied and/or disclosed only // pursuant to the terms of a valid license agreement with Xilinx. // // XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION // ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER // EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT // LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, // MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx // does not warrant that functions included in the Materials will // meet the requirements of Licensee, or that the operation of the // Materials will be uninterrupted or error-free, or that defects // in the Materials will be corrected. Furthermore, Xilinx does // not warrant or make any representations regarding use, or the // results of the use, of the Materials in terms of correctness, // accuracy, reliability or otherwise. // // Xilinx products are not designed or intended to be fail-safe, // or for use in any application requiring fail-safe performance, // such as life-support or safety devices or systems, Class III // medical devices, nuclear facilities, applications related to // the deployment of airbags, or any other applications that could // lead to death, personal injury or severe property or // environmental damage (individually and collectively, "critical // applications"). Customer assumes the sole risk and liability // of any use of Xilinx products in critical applications, // subject only to applicable laws and regulations governing // limitations on product liability. // // Copyright 2009 Xilinx, Inc. // All rights reserved. // // This disclaimer and copyright notice must be retained as part // of this file at all times. //*************************************************************************** // `timescale 1ns / 1ps module tb; reg tb_ACLK; reg tb_ARESETn; wire temp_clk; wire temp_rstn; reg [31:0] read_data; wire [7:0] leds; reg resp; initial begin tb_ACLK = 1\'b0; end //------------------------------------------------------------------------ // Simple Clock Generator //------------------------------------------------------------------------ always #10 tb_ACLK = !tb_ACLK; initial begin $display ("running the tb"); tb_ARESETn = 1\'b0; repeat(2)@(posedge tb_ACLK); tb_ARESETn = 1\'b1; @(posedge tb_ACLK); repeat(5) @(posedge tb_ACLK); //Reset the PL tb.zynq_sys.base_zynq_design_i.processing_system7_0.inst.fpga_soft_reset(32\'h1); tb.zynq_sys.base_zynq_design_i.processing_system7_0.inst.fpga_soft_reset(32\'h0); //This drives the LEDs on the GPIO output tb.zynq_sys.base_zynq_design_i.processing_system7_0.inst.write_data(32\'h41200000,4, 32\'hFFFFFFFF, resp); $display ("LEDs are toggled, observe the waveform"); //Write into the BRAM through GP0 and read back tb.zynq_sys.base_zynq_design_i.processing_system7_0.inst.write_data(32\'h40000000,4, 32\'hDEADBEEF, resp); tb.zynq_sys.base_zynq_design_i.processing_system7_0.inst.read_data(32\'h40000000,4,read_data,resp); $display ("%t, running the testbench, data read from BRAM was 32\'h%x",$time, read_data); if(read_data == 32\'hDEADBEEF) begin $display ("Zynq BFM Test PASSED"); end else begin $display ("Zynq BFM Test FAILED"); end $display ("Simulation completed"); $stop; end assign temp_clk = tb_ACLK; assign temp_rstn = tb_ARESETn; base_zynq_design_wrapper zynq_sys (.DDR_addr(), .DDR_ba(), .DDR_cas_n(), .DDR_ck_n(), .DDR_ck_p(), .DDR_cke(), .DDR_cs_n(), .DDR_dm(), .DDR_dq(), .DDR_dqs_n(), .DDR_dqs_p(), .DDR_odt(), .DDR_ras_n(), .DDR_reset_n(), .DDR_we_n(), .FIXED_IO_ddr_vrn(), .FIXED_IO_ddr_vrp(), .FIXED_IO_mio(), .FIXED_IO_ps_clk(temp_clk), .FIXED_IO_ps_porb(temp_rstn ), .FIXED_IO_ps_srstb(temp_rstn), .leds_8bits_tri_o(leds)); endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_arb_hp0_1.v * * Date : 2012-11 * * Description : Module that arbitrates between RD/WR requests from 2 ports. * Used for modelling the Top_Interconnect switch. *****************************************************************************/ module processing_system7_bfm_v2_0_arb_hp0_1( sw_clk, rstn, w_qos_hp0, r_qos_hp0, w_qos_hp1, r_qos_hp1, wr_ack_ddr_hp0, wr_data_hp0, wr_addr_hp0, wr_bytes_hp0, wr_dv_ddr_hp0, rd_req_ddr_hp0, rd_addr_hp0, rd_bytes_hp0, rd_data_ddr_hp0, rd_dv_ddr_hp0, wr_ack_ddr_hp1, wr_data_hp1, wr_addr_hp1, wr_bytes_hp1, wr_dv_ddr_hp1, rd_req_ddr_hp1, rd_addr_hp1, rd_bytes_hp1, rd_data_ddr_hp1, rd_dv_ddr_hp1, ddr_wr_ack, ddr_wr_dv, ddr_rd_req, ddr_rd_dv, ddr_rd_qos, ddr_wr_qos, ddr_wr_addr, ddr_wr_data, ddr_wr_bytes, ddr_rd_addr, ddr_rd_data, ddr_rd_bytes ); `include "processing_system7_bfm_v2_0_local_params.v" input sw_clk; input rstn; input [axi_qos_width-1:0] w_qos_hp0; input [axi_qos_width-1:0] r_qos_hp0; input [axi_qos_width-1:0] w_qos_hp1; input [axi_qos_width-1:0] r_qos_hp1; input [axi_qos_width-1:0] ddr_rd_qos; input [axi_qos_width-1:0] ddr_wr_qos; output wr_ack_ddr_hp0; input [max_burst_bits-1:0] wr_data_hp0; input [addr_width-1:0] wr_addr_hp0; input [max_burst_bytes_width:0] wr_bytes_hp0; output wr_dv_ddr_hp0; input rd_req_ddr_hp0; input [addr_width-1:0] rd_addr_hp0; input [max_burst_bytes_width:0] rd_bytes_hp0; output [max_burst_bits-1:0] rd_data_ddr_hp0; output rd_dv_ddr_hp0; output wr_ack_ddr_hp1; input [max_burst_bits-1:0] wr_data_hp1; input [addr_width-1:0] wr_addr_hp1; input [max_burst_bytes_width:0] wr_bytes_hp1; output wr_dv_ddr_hp1; input rd_req_ddr_hp1; input [addr_width-1:0] rd_addr_hp1; input [max_burst_bytes_width:0] rd_bytes_hp1; output [max_burst_bits-1:0] rd_data_ddr_hp1; output rd_dv_ddr_hp1; input ddr_wr_ack; output ddr_wr_dv; output [addr_width-1:0]ddr_wr_addr; output [max_burst_bits-1:0]ddr_wr_data; output [max_burst_bytes_width:0]ddr_wr_bytes; input ddr_rd_dv; input [max_burst_bits-1:0] ddr_rd_data; output ddr_rd_req; output [addr_width-1:0] ddr_rd_addr; output [max_burst_bytes_width:0] ddr_rd_bytes; processing_system7_bfm_v2_0_arb_wr ddr_hp_wr( .rstn(rstn), .sw_clk(sw_clk), .qos1(w_qos_hp0), .qos2(w_qos_hp1), .prt_dv1(wr_dv_ddr_hp0), .prt_dv2(wr_dv_ddr_hp1), .prt_data1(wr_data_hp0), .prt_data2(wr_data_hp1), .prt_addr1(wr_addr_hp0), .prt_addr2(wr_addr_hp1), .prt_bytes1(wr_bytes_hp0), .prt_bytes2(wr_bytes_hp1), .prt_ack1(wr_ack_ddr_hp0), .prt_ack2(wr_ack_ddr_hp1), .prt_req(ddr_wr_dv), .prt_qos(ddr_wr_qos), .prt_data(ddr_wr_data), .prt_addr(ddr_wr_addr), .prt_bytes(ddr_wr_bytes), .prt_ack(ddr_wr_ack) ); processing_system7_bfm_v2_0_arb_rd ddr_hp_rd( .rstn(rstn), .sw_clk(sw_clk), .qos1(r_qos_hp0), .qos2(r_qos_hp1), .prt_req1(rd_req_ddr_hp0), .prt_req2(rd_req_ddr_hp1), .prt_data1(rd_data_ddr_hp0), .prt_data2(rd_data_ddr_hp1), .prt_addr1(rd_addr_hp0), .prt_addr2(rd_addr_hp1), .prt_bytes1(rd_bytes_hp0), .prt_bytes2(rd_bytes_hp1), .prt_dv1(rd_dv_ddr_hp0), .prt_dv2(rd_dv_ddr_hp1), .prt_qos(ddr_rd_qos), .prt_req(ddr_rd_req), .prt_data(ddr_rd_data), .prt_addr(ddr_rd_addr), .prt_bytes(ddr_rd_bytes), .prt_dv(ddr_rd_dv) ); endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_afi_slave.v * * Date : 2012-11 * * Description : Model that acts as AFI port interface. It uses AXI3 Slave BFM * from Cadence. *****************************************************************************/ module processing_system7_bfm_v2_0_afi_slave ( S_RESETN, S_ARREADY, S_AWREADY, S_BVALID, S_RLAST, S_RVALID, S_WREADY, S_BRESP, S_RRESP, S_RDATA, S_BID, S_RID, S_ACLK, S_ARVALID, S_AWVALID, S_BREADY, S_RREADY, S_WLAST, S_WVALID, S_ARBURST, S_ARLOCK, S_ARSIZE, S_AWBURST, S_AWLOCK, S_AWSIZE, S_ARPROT, S_AWPROT, S_ARADDR, S_AWADDR, S_WDATA, S_ARCACHE, S_ARLEN, S_AWCACHE, S_AWLEN, S_WSTRB, S_ARID, S_AWID, S_WID, S_AWQOS, S_ARQOS, SW_CLK, WR_DATA_ACK_OCM, WR_DATA_ACK_DDR, WR_ADDR, WR_DATA, WR_BYTES, WR_DATA_VALID_OCM, WR_DATA_VALID_DDR, WR_QOS, RD_REQ_DDR, RD_REQ_OCM, RD_ADDR, RD_DATA_OCM, RD_DATA_DDR, RD_BYTES, RD_QOS, RD_DATA_VALID_OCM, RD_DATA_VALID_DDR, S_RDISSUECAP1_EN, S_WRISSUECAP1_EN, S_RCOUNT, S_WCOUNT, S_RACOUNT, S_WACOUNT ); parameter enable_this_port = 0; parameter slave_name = "Slave"; parameter data_bus_width = 32; parameter address_bus_width = 32; parameter id_bus_width = 6; parameter slave_base_address = 0; parameter slave_high_address = 4; parameter max_outstanding_transactions = 8; parameter exclusive_access_supported = 0; `include "processing_system7_bfm_v2_0_local_params.v" /* Local parameters only for this module */ /* Internal counters that are used as Read/Write pointers to the fifo\'s that store all the transaction info on all channles. This parameter is used to define the width of these pointers --> depending on Maximum outstanding transactions supported. 1-bit extra width than the no.of.bits needed to represent the outstanding transactions Extra bit helps in generating the empty and full flags */ parameter int_cntr_width = clogb2(max_outstanding_transactions)+1; /* RESP data */ parameter rsp_fifo_bits = axi_rsp_width+id_bus_width; parameter rsp_lsb = 0; parameter rsp_msb = axi_rsp_width-1; parameter rsp_id_lsb = rsp_msb + 1; parameter rsp_id_msb = rsp_id_lsb + id_bus_width-1; input S_RESETN; output S_ARREADY; output S_AWREADY; output S_BVALID; output S_RLAST; output S_RVALID; output S_WREADY; output [axi_rsp_width-1:0] S_BRESP; output [axi_rsp_width-1:0] S_RRESP; output [data_bus_width-1:0] S_RDATA; output [id_bus_width-1:0] S_BID; output [id_bus_width-1:0] S_RID; input S_ACLK; input S_ARVALID; input S_AWVALID; input S_BREADY; input S_RREADY; input S_WLAST; input S_WVALID; input [axi_brst_type_width-1:0] S_ARBURST; input [axi_lock_width-1:0] S_ARLOCK; input [axi_size_width-1:0] S_ARSIZE; input [axi_brst_type_width-1:0] S_AWBURST; input [axi_lock_width-1:0] S_AWLOCK; input [axi_size_width-1:0] S_AWSIZE; input [axi_prot_width-1:0] S_ARPROT; input [axi_prot_width-1:0] S_AWPROT; input [address_bus_width-1:0] S_ARADDR; input [address_bus_width-1:0] S_AWADDR; input [data_bus_width-1:0] S_WDATA; input [axi_cache_width-1:0] S_ARCACHE; input [axi_cache_width-1:0] S_ARLEN; input [axi_qos_width-1:0] S_ARQOS; input [axi_cache_width-1:0] S_AWCACHE; input [axi_len_width-1:0] S_AWLEN; input [axi_qos_width-1:0] S_AWQOS; input [(data_bus_width/8)-1:0] S_WSTRB; input [id_bus_width-1:0] S_ARID; input [id_bus_width-1:0] S_AWID; input [id_bus_width-1:0] S_WID; input SW_CLK; input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM; output WR_DATA_VALID_DDR, WR_DATA_VALID_OCM; output [max_burst_bits-1:0] WR_DATA; output [addr_width-1:0] WR_ADDR; output [max_transfer_bytes_width:0] WR_BYTES; output reg RD_REQ_OCM, RD_REQ_DDR; output reg [addr_width-1:0] RD_ADDR; input [max_burst_bits-1:0] RD_DATA_DDR,RD_DATA_OCM; output reg[max_transfer_bytes_width:0] RD_BYTES; input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR; output [axi_qos_width-1:0] WR_QOS; output reg [axi_qos_width-1:0] RD_QOS; input S_RDISSUECAP1_EN; input S_WRISSUECAP1_EN; output [7:0] S_RCOUNT; output [7:0] S_WCOUNT; output [2:0] S_RACOUNT; output [5:0] S_WACOUNT; wire net_ARVALID; wire net_AWVALID; wire net_WVALID; real s_aclk_period; cdn_axi3_slave_bfm #(slave_name, data_bus_width, address_bus_width, id_bus_width, slave_base_address, (slave_high_address- slave_base_address), max_outstanding_transactions, 0, ///MEMORY_MODEL_MODE, exclusive_access_supported) slave (.ACLK (S_ACLK), .ARESETn (S_RESETN), /// confirm this // Write Address Channel .AWID (S_AWID), .AWADDR (S_AWADDR), .AWLEN (S_AWLEN), .AWSIZE (S_AWSIZE), .AWBURST (S_AWBURST), .AWLOCK (S_AWLOCK), .AWCACHE (S_AWCACHE), .AWPROT (S_AWPROT), .AWVALID (net_AWVALID), .AWREADY (S_AWREADY), // Write Data Channel Signals. .WID (S_WID), .WDATA (S_WDATA), .WSTRB (S_WSTRB), .WLAST (S_WLAST), .WVALID (net_WVALID), .WREADY (S_WREADY), // Write Response Channel Signals. .BID (S_BID), .BRESP (S_BRESP), .BVALID (S_BVALID), .BREADY (S_BREADY), // Read Address Channel Signals. .ARID (S_ARID), .ARADDR (S_ARADDR), .ARLEN (S_ARLEN), .ARSIZE (S_ARSIZE), .ARBURST (S_ARBURST), .ARLOCK (S_ARLOCK), .ARCACHE (S_ARCACHE), .ARPROT (S_ARPROT), .ARVALID (net_ARVALID), .ARREADY (S_ARREADY), // Read Data Channel Signals. .RID (S_RID), .RDATA (S_RDATA), .RRESP (S_RRESP), .RLAST (S_RLAST), .RVALID (S_RVALID), .RREADY (S_RREADY)); wire wr_intr_fifo_full; reg temp_wr_intr_fifo_full; /* Interconnect WR_FIFO model instance */ processing_system7_bfm_v2_0_intr_wr_mem wr_intr_fifo(SW_CLK, S_RESETN, wr_intr_fifo_full, WR_DATA_ACK_OCM, WR_DATA_ACK_DDR, WR_ADDR, WR_DATA, WR_BYTES, WR_QOS, WR_DATA_VALID_OCM, WR_DATA_VALID_DDR); /* Register the async \'full\' signal to S_ACLK clock */ always@(posedge S_ACLK) temp_wr_intr_fifo_full = wr_intr_fifo_full; /* Latency type and Debug/Error Control */ reg[1:0] latency_type = RANDOM_CASE; reg DEBUG_INFO = 1; reg STOP_ON_ERROR = 1\'b1; /* Internal nets/regs for calling slave BFM API\'s*/ reg [wr_afi_fifo_data_bits-1:0] wr_fifo [0:max_outstanding_transactions-1]; reg [int_cntr_width-1:0] wr_fifo_wr_ptr = 0, wr_fifo_rd_ptr = 0; wire wr_fifo_empty; /* Store the awvalid receive time --- necessary for calculating the bresp latency */ reg [7:0] aw_time_cnt = 0,bresp_time_cnt = 0; real awvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new awvalid is received reg awvalid_flag[0:max_outstanding_transactions]; // store the time when a new awvalid is received /* Address Write Channel handshake*/ reg[int_cntr_width-1:0] aw_cnt = 0;// /* various FIFOs for storing the ADDR channel info */ reg [axi_size_width-1:0] awsize [0:max_outstanding_transactions-1]; reg [axi_prot_width-1:0] awprot [0:max_outstanding_transactions-1]; reg [axi_lock_width-1:0] awlock [0:max_outstanding_transactions-1]; reg [axi_cache_width-1:0] awcache [0:max_outstanding_transactions-1]; reg [axi_brst_type_width-1:0] awbrst [0:max_outstanding_transactions-1]; reg [axi_len_width-1:0] awlen [0:max_outstanding_transactions-1]; reg aw_flag [0:max_outstanding_transactions-1]; reg [addr_width-1:0] awaddr [0:max_outstanding_transactions-1]; reg [id_bus_width-1:0] awid [0:max_outstanding_transactions-1]; reg [axi_qos_width-1:0] awqos [0:max_outstanding_transactions-1]; wire aw_fifo_full; // indicates awvalid_fifo is full (max outstanding transactions reached) /* internal fifos to store burst write data, ID & strobes*/ reg [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_outstanding_transactions-1]; reg [max_burst_bytes_width:0] burst_valid_bytes [0:max_outstanding_transactions-1]; /// total valid bytes received in a complete burst transfer reg wlast_flag [0:max_outstanding_transactions-1]; // flag to indicate WLAST received wire wd_fifo_full; /* Write Data Channel and Write Response handshake signals*/ reg [int_cntr_width-1:0] wd_cnt = 0; reg [(data_bus_width*axi_burst_len)-1:0] aligned_wr_data; reg [addr_width-1:0] aligned_wr_addr; reg [max_burst_bytes_width:0] valid_data_bytes; reg [int_cntr_width-1:0] wr_bresp_cnt = 0; reg [axi_rsp_width-1:0] bresp; reg [rsp_fifo_bits-1:0] fifo_bresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response reg enable_write_bresp; reg [int_cntr_width-1:0] rd_bresp_cnt = 0; integer wr_latency_count; reg wr_delayed; wire bresp_fifo_empty; /* keep track of count values */ reg[7:0] wcount; reg[5:0] wacount; /* Qos*/ reg [axi_qos_width-1:0] ar_qos, aw_qos; initial begin if(DEBUG_INFO) begin if(enable_this_port) $display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, slave_name); else $display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, slave_name); end end /*--------------------------------------------------------------------------------*/ /* Store the Clock cycle time period */ always@(S_RESETN) begin if(S_RESETN) begin @(posedge S_ACLK); s_aclk_period = $time; @(posedge S_ACLK); s_aclk_period = $time - s_aclk_period; end end /*--------------------------------------------------------------------------------*/ initial slave.set_disable_reset_value_checks(1); initial begin repeat(2) @(posedge S_ACLK); if(!enable_this_port) begin slave.set_channel_level_info(0); slave.set_function_level_info(0); end slave.RESPONSE_TIMEOUT = 0; end /*--------------------------------------------------------------------------------*/ /* Set Latency type to be used */ task set_latency_type; input[1:0] lat; begin if(enable_this_port) latency_type = lat; else begin //if(DEBUG_INFO) $display("[%0d] : %0s : %0s : Port is disabled. \'Latency Profile\' will not be set...",$time, DISP_WARN, slave_name); end end endtask /*--------------------------------------------------------------------------------*/ /* Set ARQoS to be used */ task set_arqos; input[axi_qos_width-1:0] qos; begin if(enable_this_port) ar_qos = qos; else begin if(DEBUG_INFO) $display("[%0d] : %0s : %0s : Port is disabled. \'ARQOS\' will not be set...",$time, DISP_WARN, slave_name); end end endtask /*--------------------------------------------------------------------------------*/ /* Set AWQoS to be used */ task set_awqos; input[axi_qos_width-1:0] qos; begin if(enable_this_port) aw_qos = qos; else begin if(DEBUG_INFO) $display("[%0d] : %0s : %0s : Port is disabled. \'AWQOS\' will not be set...",$time, DISP_WARN, slave_name); end end endtask /*--------------------------------------------------------------------------------*/ /* get the wr latency number */ function [31:0] get_wr_lat_number; input dummy; reg[1:0] temp; begin case(latency_type) BEST_CASE : get_wr_lat_number = afi_wr_min; AVG_CASE : get_wr_lat_number = afi_wr_avg; WORST_CASE : get_wr_lat_number = afi_wr_max; default : begin // RANDOM_CASE temp = $random; case(temp) 2\'b00 : get_wr_lat_number = ($random()%10+ afi_wr_min); 2\'b01 : get_wr_lat_number = ($random()%40+ afi_wr_avg); default : get_wr_lat_number = ($random()%60+ afi_wr_max); endcase end endcase end endfunction /*--------------------------------------------------------------------------------*/ /* get the rd latency number */ function [31:0] get_rd_lat_number; input dummy; reg[1:0] temp; begin case(latency_type) BEST_CASE : get_rd_lat_number = afi_rd_min; AVG_CASE : get_rd_lat_number = afi_rd_avg; WORST_CASE : get_rd_lat_number = afi_rd_max; default : begin // RANDOM_CASE temp = $random; case(temp) 2\'b00 : get_rd_lat_number = ($random()%10+ afi_rd_min); 2\'b01 : get_rd_lat_number = ($random()%40+ afi_rd_avg); default : get_rd_lat_number = ($random()%60+ afi_rd_max); endcase end endcase end endfunction /*--------------------------------------------------------------------------------*/ /* Check for any WRITE/READs when this port is disabled */ always@(S_AWVALID or S_WVALID or S_ARVALID) begin if((S_AWVALID | S_WVALID | S_ARVALID) && !enable_this_port) begin $display("[%0d] : %0s : %0s : Port is disabled. AXI transaction is initiated on this port ...\ Simulation will halt ..",$time, DISP_ERR, slave_name); $stop; end end /*--------------------------------------------------------------------------------*/ assign net_ARVALID = enable_this_port ? S_ARVALID : 1\'b0; assign net_AWVALID = enable_this_port ? S_AWVALID : 1\'b0; assign net_WVALID = enable_this_port ? S_WVALID : 1\'b0; assign wr_fifo_empty = (wr_fifo_wr_ptr === wr_fifo_rd_ptr)?1\'b1: 1\'b0; assign bresp_fifo_empty = (wr_bresp_cnt === rd_bresp_cnt)?1\'b1:1\'b0; assign bresp_fifo_full = ((wr_bresp_cnt[int_cntr_width-1] !== rd_bresp_cnt[int_cntr_width-1]) && (wr_bresp_cnt[int_cntr_width-2:0] === rd_bresp_cnt[int_cntr_width-2:0]))?1\'b1:1\'b0; assign S_WCOUNT = wcount; assign S_WACOUNT = wacount; // FIFO_STATUS (only if AFI port) 1- full function automatic wrfifo_full ; input [axi_len_width-1:0] fifo_space_exp; integer fifo_space_left; begin fifo_space_left = afi_fifo_locations - wcount; if(fifo_space_left < fifo_space_exp) wrfifo_full = 1; else wrfifo_full = 0; end endfunction /*--------------------------------------------------------------------------------*/ /* Store the awvalid receive time --- necessary for calculating the bresp latency */ always@(negedge S_RESETN or S_AWID or S_AWADDR or S_AWVALID ) begin if(!S_RESETN) aw_time_cnt <= 0; else begin if(S_AWVALID) begin awvalid_receive_time[aw_time_cnt] <= $time; awvalid_flag[aw_time_cnt] <= 1\'b1; aw_time_cnt <= aw_time_cnt + 1; end end // else end /// always /*--------------------------------------------------------------------------------*/ always@(posedge S_ACLK) begin if(net_AWVALID && S_AWREADY) begin if(S_AWQOS === 0) awqos[aw_cnt[int_cntr_width-2:0]] = aw_qos; else awqos[aw_cnt[int_cntr_width-2:0]] = S_AWQOS; end end /* Address Write Channel handshake*/ always@(negedge S_RESETN or posedge S_ACLK) begin if(!S_RESETN) begin aw_cnt <= 0; wacount <= 0; end else begin if(S_AWVALID && !wrfifo_full(S_AWLEN+1)) begin slave.RECEIVE_WRITE_ADDRESS(0, id_invalid, awaddr[aw_cnt[int_cntr_width-2:0]], awlen[aw_cnt[int_cntr_width-2:0]], awsize[aw_cnt[int_cntr_width-2:0]], awbrst[aw_cnt[int_cntr_width-2:0]], awlock[aw_cnt[int_cntr_width-2:0]], awcache[aw_cnt[int_cntr_width-2:0]], awprot[aw_cnt[int_cntr_width-2:0]], awid[aw_cnt[int_cntr_width-2:0]]); /// sampled valid ID. aw_flag[aw_cnt[int_cntr_width-2:0]] <= 1\'b1; aw_cnt <= aw_cnt + 1; wacount <= wacount + 1; end // if (!aw_fifo_full) end /// if else end /// always /*--------------------------------------------------------------------------------*/ /* Write Data Channel Handshake */ always@(negedge S_RESETN or posedge S_ACLK) begin if(!S_RESETN) begin wd_cnt <= 0; end else begin if(aw_flag[wd_cnt[int_cntr_width-2:0]]) begin if(S_WVALID && !wrfifo_full(awlen[wd_cnt[int_cntr_width-2:0]] + 1)) begin slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]); wlast_flag[wd_cnt[int_cntr_width-2:0]] <= 1\'b1; wd_cnt <= wd_cnt + 1; end end else begin if(!wrfifo_full(axi_burst_len) && S_WVALID) begin slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]); wlast_flag[wd_cnt[int_cntr_width-2:0]] <= 1\'b1; wd_cnt <= wd_cnt + 1; end end /// if end /// else end /// always /*--------------------------------------------------------------------------------*/ /* Align the wrap data for write transaction */ task automatic get_wrap_aligned_wr_data; output [(data_bus_width*axi_burst_len)-1:0] aligned_data; output [addr_width-1:0] start_addr; /// aligned start address input [addr_width-1:0] addr; input [(data_bus_width*axi_burst_len)-1:0] b_data; input [max_burst_bytes_width:0] v_bytes; reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data; integer wrp_bytes; integer i; begin start_addr = (addr/v_bytes) * v_bytes; wrp_bytes = addr - start_addr; wrp_data = b_data; temp_data = 0; wrp_data = wrp_data << ((data_bus_width*axi_burst_len) - (v_bytes*8)); while(wrp_bytes > 0) begin /// get the data that is wrapped temp_data = temp_data << 8; temp_data[7:0] = wrp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8]; wrp_data = wrp_data << 8; wrp_bytes = wrp_bytes - 1; end wrp_bytes = addr - start_addr; wrp_data = b_data << (wrp_bytes*8); aligned_data = (temp_data | wrp_data); end endtask /*--------------------------------------------------------------------------------*/ /* Calculate the Response for each read/write transaction */ function [axi_rsp_width-1:0] calculate_resp; input [addr_width-1:0] awaddr; input [axi_prot_width-1:0] awprot; reg [axi_rsp_width-1:0] rsp; begin rsp = AXI_OK; /* Address Decode */ if(decode_address(awaddr) === INVALID_MEM_TYPE) begin rsp = AXI_SLV_ERR; //slave error $display("[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) ",$time, DISP_ERR, slave_name, awaddr); end else if(decode_address(awaddr) === REG_MEM) begin rsp = AXI_SLV_ERR; //slave error $display("[%0d] : %0s : %0s : AXI Access to Register Map(0x%0h) is not allowed through this port.",$time, DISP_ERR, slave_name, awaddr); end if(secure_access_enabled && awprot[1]) rsp = AXI_DEC_ERR; // decode error calculate_resp = rsp; end endfunction /*--------------------------------------------------------------------------------*/ reg[max_burst_bits-1:0] temp_wr_data; /* Store the Write response for each write transaction */ always@(negedge S_RESETN or posedge S_ACLK) begin if(!S_RESETN) begin wr_fifo_wr_ptr <= 0; wcount <= 0; end else begin enable_write_bresp = aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] && wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]]; /* calculate bresp only when AWVALID && WLAST is received */ if(enable_write_bresp) begin aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] <= 0; wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] <= 0; bresp = calculate_resp(awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], awprot[wr_fifo_wr_ptr[int_cntr_width-2:0]]); /* Fill AFI_WR_data FIFO */ if(bresp === AXI_OK ) begin if(awbrst[wr_fifo_wr_ptr[int_cntr_width-2:0]]=== AXI_WRAP) begin /// wrap type? then align the data get_wrap_aligned_wr_data(aligned_wr_data, aligned_wr_addr, awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]],burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]]); /// gives wrapped start address end else begin aligned_wr_data = burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]]; aligned_wr_addr = awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]] ; end valid_data_bytes = burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]]; end else valid_data_bytes = 0; temp_wr_data = aligned_wr_data; wr_fifo[wr_fifo_wr_ptr[int_cntr_width-2:0]] = {awqos[wr_fifo_wr_ptr[int_cntr_width-2:0]], awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]], awid[wr_fifo_wr_ptr[int_cntr_width-2:0]], bresp, temp_wr_data, aligned_wr_addr, valid_data_bytes}; wcount <= wcount + awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]]+1; wr_fifo_wr_ptr <= wr_fifo_wr_ptr + 1; end end // else end // always /*--------------------------------------------------------------------------------*/ /* Send Write Response Channel handshake */ always@(negedge S_RESETN or posedge S_ACLK) begin if(!S_RESETN) begin rd_bresp_cnt <= 0; wr_latency_count = get_wr_lat_number(1); wr_delayed = 0; bresp_time_cnt <= 0; end else begin wr_delayed = 1\'b0; if(awvalid_flag[bresp_time_cnt] && (($time - awvalid_receive_time[bresp_time_cnt])/s_aclk_period >= wr_latency_count)) wr_delayed = 1; if(!bresp_fifo_empty && wr_delayed) begin slave.SEND_WRITE_RESPONSE(fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb], // ID fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_msb : rsp_lsb] // Response ); wr_delayed = 0; awvalid_flag[bresp_time_cnt] = 1\'b0; bresp_time_cnt <= bresp_time_cnt+1; rd_bresp_cnt <= rd_bresp_cnt + 1; wr_latency_count = get_wr_lat_number(1); end end // else end//always /*--------------------------------------------------------------------------------*/ /* Write Response Channel handshake */ reg wr_int_state; /* Reading from the wr_fifo and sending to Interconnect fifo*/ always@(negedge S_RESETN or posedge S_ACLK) begin if(!S_RESETN) begin wr_int_state <= 1\'b0; wr_bresp_cnt <= 0; wr_fifo_rd_ptr <= 0; end else begin case(wr_int_state) 1\'b0 : begin wr_int_state <= 1\'b0; if(!temp_wr_intr_fifo_full && !bresp_fifo_full && !wr_fifo_empty) begin wr_intr_fifo.write_mem({wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_qos_msb:wr_afi_qos_lsb], wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_data_msb:wr_afi_bytes_lsb]}); /// qos, data, address and valid_bytes wr_int_state <= 1\'b1; /* start filling the write response fifo at the same time */ fifo_bresp[wr_bresp_cnt[int_cntr_width-2:0]] <= wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_id_msb:wr_afi_rsp_lsb]; // ID and Resp wcount <= wcount - (wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_ln_msb:wr_afi_ln_lsb] + 1); /// burst length wacount <= wacount - 1; wr_fifo_rd_ptr <= wr_fifo_rd_ptr + 1; wr_bresp_cnt <= wr_bresp_cnt+1; end end 1\'b1 : begin wr_int_state <= 0; end endcase end end /*--------------------------------------------------------------------------------*/ /*-------------------------------- WRITE HANDSHAKE END ----------------------------------------*/ /*-------------------------------- READ HANDSHAKE ---------------------------------------------*/ /* READ CHANNELS */ /* Store the arvalid receive time --- necessary for calculating latency in sending the rresp latency */ reg [7:0] ar_time_cnt = 0,rresp_time_cnt = 0; real arvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new arvalid is received reg arvalid_flag[0:max_outstanding_transactions]; // store the time when a new arvalid is received reg [int_cntr_width-1:0] ar_cnt = 0;// counter for arvalid info /* various FIFOs for storing the ADDR channel info */ reg [axi_size_width-1:0] arsize [0:max_outstanding_transactions-1]; reg [axi_prot_width-1:0] arprot [0:max_outstanding_transactions-1]; reg [axi_brst_type_width-1:0] arbrst [0:max_outstanding_transactions-1]; reg [axi_len_width-1:0] arlen [0:max_outstanding_transactions-1]; reg [axi_cache_width-1:0] arcache [0:max_outstanding_transactions-1]; reg [axi_lock_width-1:0] arlock [0:max_outstanding_transactions-1]; reg ar_flag [0:max_outstanding_transactions-1]; reg [addr_width-1:0] araddr [0:max_outstanding_transactions-1]; reg [id_bus_width-1:0] arid [0:max_outstanding_transactions-1]; reg [axi_qos_width-1:0] arqos [0:max_outstanding_transactions-1]; wire ar_fifo_full; // indicates arvalid_fifo is full (max outstanding transactions reached) reg [int_cntr_width-1:0] wr_rresp_cnt = 0; reg [axi_rsp_width-1:0] rresp; reg [rsp_fifo_bits-1:0] fifo_rresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response reg enable_write_rresp; /* Send Read Response & Data Channel handshake */ integer rd_latency_count; reg rd_delayed; reg [rd_afi_fifo_bits-1:0] read_fifo[0:max_outstanding_transactions-1]; /// Read Burst Data, addr, size, burst, len, RID, RRESP, valid_bytes reg [int_cntr_width-1:0] rd_fifo_wr_ptr = 0, rd_fifo_rd_ptr = 0; wire read_fifo_full; reg [7:0] rcount; reg [2:0] racount; wire rd_intr_fifo_full, rd_intr_fifo_empty; wire read_fifo_empty; /* signals to communicate with interconnect RD_FIFO model */ reg rd_req, invalid_rd_req; /* REad control Info 56:25 : Address (32) 24:22 : Size (3) 21:20 : BRST (2) 19:16 : LEN (4) 15:10 : RID (6) 9:8 : RRSP (2) 7:0 : byte cnt (8) */ reg [rd_info_bits-1:0] read_control_info; reg [(data_bus_width*axi_burst_len)-1:0] aligned_rd_data; reg temp_rd_intr_fifo_empty; processing_system7_bfm_v2_0_intr_rd_mem rd_intr_fifo(SW_CLK, S_RESETN, rd_intr_fifo_full, rd_intr_fifo_empty, rd_req, invalid_rd_req, read_control_info , RD_DATA_OCM, RD_DATA_DDR, RD_DATA_VALID_OCM, RD_DATA_VALID_DDR); assign read_fifo_empty = (rd_fifo_wr_ptr === rd_fifo_rd_ptr)?1\'b1: 1\'b0; assign S_RCOUNT = rcount; assign S_RACOUNT = racount; /* Register the asynch signal empty coming from Interconnect READ FIFO */ always@(posedge S_ACLK) temp_rd_intr_fifo_empty = rd_intr_fifo_empty; // FIFO_STATUS (only if AFI port) 1- full function automatic rdfifo_full ; input [axi_len_width-1:0] fifo_space_exp; integer fifo_space_left; begin fifo_space_left = afi_fifo_locations - rcount; if(fifo_space_left < fifo_space_exp) rdfifo_full = 1; else rdfifo_full = 0; end endfunction /* Store the arvalid receive time --- necessary for calculating the bresp latency */ always@(negedge S_RESETN or S_ARID or S_ARADDR or S_ARVALID ) begin if(!S_RESETN) ar_time_cnt <= 0; else begin if(S_ARVALID) begin arvalid_receive_time[ar_time_cnt] <= $time; arvalid_flag[ar_time_cnt] <= 1\'b1; ar_time_cnt <= ar_time_cnt + 1; end end // else end /// always /*--------------------------------------------------------------------------------*/ always@(posedge S_ACLK) begin if(net_ARVALID && S_ARREADY) begin if(S_ARQOS === 0) arqos[aw_cnt[int_cntr_width-2:0]] = ar_qos; else arqos[aw_cnt[int_cntr_width-2:0]] = S_ARQOS; end end /* Address Read Channel handshake*/ always@(negedge S_RESETN or posedge S_ACLK) begin if(!S_RESETN) begin ar_cnt <= 0; racount <= 0; end else begin if(S_ARVALID && !rdfifo_full(S_ARLEN+1)) begin /// if AFI read fifo is not full slave.RECEIVE_READ_ADDRESS(0, id_invalid, araddr[ar_cnt[int_cntr_width-2:0]], arlen[ar_cnt[int_cntr_width-2:0]], arsize[ar_cnt[int_cntr_width-2:0]], arbrst[ar_cnt[int_cntr_width-2:0]], arlock[ar_cnt[int_cntr_width-2:0]], arcache[ar_cnt[int_cntr_width-2:0]], arprot[ar_cnt[int_cntr_width-2:0]], arid[ar_cnt[int_cntr_width-2:0]]); /// sampled valid ID. ar_flag[ar_cnt[int_cntr_width-2:0]] <= 1\'b1; ar_cnt <= ar_cnt+1; racount <= racount + 1; end /// if(!ar_fifo_full) end /// if else end /// always*/ /*--------------------------------------------------------------------------------*/ /* Align Wrap data for read transaction*/ task automatic get_wrap_aligned_rd_data; output [(data_bus_width*axi_burst_len)-1:0] aligned_data; input [addr_width-1:0] addr; input [(data_bus_width*axi_burst_len)-1:0] b_data; input [max_burst_bytes_width:0] v_bytes; reg [addr_width-1:0] start_addr; reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data; integer wrp_bytes; integer i; begin start_addr = (addr/v_bytes) * v_bytes; wrp_bytes = addr - start_addr; wrp_data = b_data; temp_data = 0; while(wrp_bytes > 0) begin /// get the data that is wrapped temp_data = temp_data >> 8; temp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8] = wrp_data[7:0]; wrp_data = wrp_data >> 8; wrp_bytes = wrp_bytes - 1; end temp_data = temp_data >> ((data_bus_width*axi_burst_len) - (v_bytes*8)); wrp_bytes = addr - start_addr; wrp_data = b_data >> (wrp_bytes*8); aligned_data = (temp_data | wrp_data); end endtask /*--------------------------------------------------------------------------------*/ parameter RD_DATA_REQ = 1\'b0, WAIT_RD_VALID = 1\'b1; reg rd_fifo_state; reg [addr_width-1:0] temp_read_address; reg [max_burst_bytes_width:0] temp_rd_valid_bytes; /* get the data from memory && also calculate the rresp*/ always@(negedge S_RESETN or posedge SW_CLK) begin if(!S_RESETN)begin wr_rresp_cnt <=0; rd_fifo_state <= RD_DATA_REQ; temp_rd_valid_bytes = 0; temp_read_address <= 0; RD_REQ_DDR <= 1\'b0; RD_REQ_OCM <= 1\'b0; rd_req <= 0; invalid_rd_req<= 0; RD_QOS <= 0; end else begin case(rd_fifo_state) RD_DATA_REQ : begin rd_fifo_state <= RD_DATA_REQ; RD_REQ_DDR <= 1\'b0; RD_REQ_OCM <= 1\'b0; invalid_rd_req <= 0; if(ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] && !rd_intr_fifo_full) begin /// check the rd_fifo_bytes, interconnect fifo full condition ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] <= 0; rresp = calculate_resp(araddr[wr_rresp_cnt[int_cntr_width-2:0]],arprot[wr_rresp_cnt[int_cntr_width-2:0]]); temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_cntr_width-2:0]]+1)*(2**arsize[wr_rresp_cnt[int_cntr_width-2:0]]);//data_bus_width/8; if(arbrst[wr_rresp_cnt[int_cntr_width-2:0]] === AXI_WRAP) /// wrap begin temp_read_address = (araddr[wr_rresp_cnt[int_cntr_width-2:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes; else temp_read_address = araddr[wr_rresp_cnt[int_cntr_width-2:0]]; if(rresp === AXI_OK) begin case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_cntr_width-2:0]]); OCM_MEM : RD_REQ_OCM <= 1; DDR_MEM : RD_REQ_DDR <= 1; default : invalid_rd_req <= 1; endcase end else invalid_rd_req <= 1; RD_ADDR <= temp_read_address; ///araddr[wr_rresp_cnt[int_cntr_width-2:0]]; RD_BYTES <= temp_rd_valid_bytes; RD_QOS <= arqos[wr_rresp_cnt[int_cntr_width-2:0]]; rd_fifo_state <= WAIT_RD_VALID; rd_req <= 1; racount <= racount - 1; read_control_info <= {araddr[wr_rresp_cnt[int_cntr_width-2:0]], arsize[wr_rresp_cnt[int_cntr_width-2:0]], arbrst[wr_rresp_cnt[int_cntr_width-2:0]], arlen[wr_rresp_cnt[int_cntr_width-2:0]], arid[wr_rresp_cnt[int_cntr_width-2:0]], rresp, temp_rd_valid_bytes }; wr_rresp_cnt <= wr_rresp_cnt + 1; end end WAIT_RD_VALID : begin rd_fifo_state <= WAIT_RD_VALID; rd_req <= 0; if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd_req) begin ///temp_dec == 2\'b11) begin RD_REQ_DDR <= 1\'b0; RD_REQ_OCM <= 1\'b0; invalid_rd_req <= 0; rd_fifo_state <= RD_DATA_REQ; end end endcase end /// else end /// always /*--------------------------------------------------------------------------------*/ /* thread to fill in the AFI RD_FIFO */ reg[rd_afi_fifo_bits-1:0] temp_rd_data;//Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes reg tmp_state; always@(negedge S_RESETN or posedge S_ACLK) begin if(!S_RESETN)begin rd_fifo_wr_ptr <= 0; rcount <= 0; tmp_state <= 0; end else begin case(tmp_state) 0 : begin tmp_state <= 0; if(!temp_rd_intr_fifo_empty) begin rd_intr_fifo.read_mem(temp_rd_data); tmp_state <= 1; end end 1 : begin tmp_state <= 1; if(!rdfifo_full(temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1)) begin read_fifo[rd_fifo_wr_ptr[int_cntr_width-2:0]] = temp_rd_data; rd_fifo_wr_ptr = rd_fifo_wr_ptr + 1; rcount <= rcount + temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1; /// Burst length tmp_state <= 0; end end endcase end end /*--------------------------------------------------------------------------------*/ reg[max_burst_bytes_width:0] rd_v_b; reg[rd_afi_fifo_bits-1:0] tmp_fifo_rd; /// Data, addr, size, burst, len, RID, RRESP,valid_bytes reg[(data_bus_width*axi_burst_len)-1:0] temp_read_data; reg[(axi_rsp_width*axi_burst_len)-1:0] temp_read_rsp; /* Read Data Channel handshake */ always@(negedge S_RESETN or posedge S_ACLK) begin if(!S_RESETN)begin rd_fifo_rd_ptr <= 0; rd_latency_count <= get_rd_lat_number(1); rd_delayed = 0; rresp_time_cnt <= 0; rd_v_b = 0; end else begin if(arvalid_flag[rresp_time_cnt] && ((($time - arvalid_receive_time[rresp_time_cnt])/s_aclk_period) >= rd_latency_count)) begin rd_delayed = 1; end if(!read_fifo_empty && rd_delayed)begin rd_delayed = 0; arvalid_flag[rresp_time_cnt] = 1\'b0; tmp_fifo_rd = read_fifo[rd_fifo_rd_ptr[int_cntr_width-2:0]]; rd_v_b = (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+1)*(2**tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb]); temp_read_data = tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb]; if(tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb] === AXI_WRAP) begin get_wrap_aligned_rd_data(aligned_rd_data, tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb], tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb], rd_v_b); temp_read_data = aligned_rd_data; end temp_read_rsp = 0; repeat(axi_burst_len) begin temp_read_rsp = temp_read_rsp >> axi_rsp_width; temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = tmp_fifo_rd[rd_afi_rsp_msb : rd_afi_rsp_lsb]; end slave.SEND_READ_BURST_RESP_CTRL(tmp_fifo_rd[rd_afi_id_msb : rd_afi_id_lsb], tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb], tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb], tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb], tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb], temp_read_data, temp_read_rsp); rcount <= rcount - (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+ 1) ; rresp_time_cnt <= rresp_time_cnt+1; rd_latency_count <= get_rd_lat_number(1); rd_fifo_rd_ptr <= rd_fifo_rd_ptr+1; end end /// else end /// always endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: Write Data Response Down-Sizer // Collect MI-side responses and set the SI-side response to the most critical // level (in descending order): // DECERR, SLVERROR and OKAY. // EXOKAY cannot occur for split transactions. // // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // wr_upsizer // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module axi_protocol_converter_v2_1_b_downsizer # ( parameter C_FAMILY = "none", // FPGA Family. Current version: virtex6 or spartan6. parameter integer C_AXI_ID_WIDTH = 4, // Width of all ID signals on SI and MI side of converter. // Range: >= 1. parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, // 1 = Propagate all USER signals, 0 = Don\xef\xbf\xbdt propagate. parameter integer C_AXI_BUSER_WIDTH = 1 // Width of BUSER signals. // Range: >= 1. ) ( // Global Signals input wire ARESET, input wire ACLK, // Command Interface input wire cmd_valid, input wire cmd_split, input wire [4-1:0] cmd_repeat, output wire cmd_ready, // Slave Interface Write Response Ports output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID, output wire [2-1:0] S_AXI_BRESP, output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, output wire S_AXI_BVALID, input wire S_AXI_BREADY, // Master Interface Write Response Ports input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID, input wire [2-1:0] M_AXI_BRESP, input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER, input wire M_AXI_BVALID, output wire M_AXI_BREADY ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Constants for packing levels. localparam [2-1:0] C_RESP_OKAY = 2\'b00; localparam [2-1:0] C_RESP_EXOKAY = 2\'b01; localparam [2-1:0] C_RESP_SLVERROR = 2\'b10; localparam [2-1:0] C_RESP_DECERR = 2\'b11; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// // Throttling help signals. wire cmd_ready_i; wire pop_mi_data; wire mi_stalling; // Repeat handling related. reg [4-1:0] repeat_cnt_pre; reg [4-1:0] repeat_cnt; wire [4-1:0] next_repeat_cnt; reg first_mi_word; wire last_word; // Ongoing split transaction. wire load_bresp; wire need_to_update_bresp; reg [2-1:0] S_AXI_BRESP_ACC; // Internal signals for MI-side. wire M_AXI_BREADY_I; // Internal signals for SI-side. wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID_I; reg [2-1:0] S_AXI_BRESP_I; wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER_I; wire S_AXI_BVALID_I; wire S_AXI_BREADY_I; ///////////////////////////////////////////////////////////////////////////// // Handle interface handshaking: // // The MI-side BRESP is popped when at once for split transactions, except // for the last cycle that behaves like a "normal" transaction. // A "normal" BRESP is popped once the SI-side is able to use it, // // ///////////////////////////////////////////////////////////////////////////// // Pop word from MI-side. assign M_AXI_BREADY_I = M_AXI_BVALID & ~mi_stalling; assign M_AXI_BREADY = M_AXI_BREADY_I; // Indicate when there is a BRESP available @ SI-side. assign S_AXI_BVALID_I = M_AXI_BVALID & last_word; // Get MI-side data. assign pop_mi_data = M_AXI_BVALID & M_AXI_BREADY_I; // Signal that the command is done (so that it can be poped from command queue). assign cmd_ready_i = cmd_valid & pop_mi_data & last_word; assign cmd_ready = cmd_ready_i; // Detect when MI-side is stalling. assign mi_stalling = (~S_AXI_BREADY_I & last_word); ///////////////////////////////////////////////////////////////////////////// // Handle the accumulation of BRESP. // // Forward the accumulated or MI-side BRESP value depending on state: // * MI-side BRESP is forwarded untouched when it is a non split cycle. // (MI-side BRESP value is also used when updating the accumulated for // the last access during a split access). // * The accumulated BRESP is for a split transaction. // // The accumulated BRESP register is updated for each MI-side response that // is used. // ///////////////////////////////////////////////////////////////////////////// // Force load accumulated BRESPs to first value assign load_bresp = (cmd_split & first_mi_word); // Update if more critical. assign need_to_update_bresp = ( M_AXI_BRESP > S_AXI_BRESP_ACC ); // Select accumultated or direct depending on setting. always @ * begin if ( cmd_split ) begin if ( load_bresp || need_to_update_bresp ) begin S_AXI_BRESP_I = M_AXI_BRESP; end else begin S_AXI_BRESP_I = S_AXI_BRESP_ACC; end end else begin S_AXI_BRESP_I = M_AXI_BRESP; end end // Accumulate MI-side BRESP. always @ (posedge ACLK) begin if (ARESET) begin S_AXI_BRESP_ACC <= C_RESP_OKAY; end else begin if ( pop_mi_data ) begin S_AXI_BRESP_ACC <= S_AXI_BRESP_I; end end end ///////////////////////////////////////////////////////////////////////////// // Keep track of BRESP repeat counter. // // Last BRESP word is either: // * The first and only word when not merging. // * The last value when merging. // // The internal counter is taken from the external command interface during // the first response when merging. The counter is updated each time a // BRESP is popped from the MI-side interface. // ///////////////////////////////////////////////////////////////////////////// // Determine last BRESP cycle. assign last_word = ( ( repeat_cnt == 4\'b0 ) & ~first_mi_word ) | ~cmd_split; // Select command reapeat or counted repeat value. always @ * begin if ( first_mi_word ) begin repeat_cnt_pre = cmd_repeat; end else begin repeat_cnt_pre = repeat_cnt; end end // Calculate next repeat counter value. assign next_repeat_cnt = repeat_cnt_pre - 1\'b1; // Keep track of the repeat count. always @ (posedge ACLK) begin if (ARESET) begin repeat_cnt <= 4\'b0; first_mi_word <= 1\'b1; end else begin if ( pop_mi_data ) begin repeat_cnt <= next_repeat_cnt; first_mi_word <= last_word; end end end ///////////////////////////////////////////////////////////////////////////// // BID Handling ///////////////////////////////////////////////////////////////////////////// assign S_AXI_BID_I = M_AXI_BID; ///////////////////////////////////////////////////////////////////////////// // USER Data bits // // The last USER bits are simply taken from the last BRESP that is merged. // Ground USER bits when unused. ///////////////////////////////////////////////////////////////////////////// // Select USER bits. assign S_AXI_BUSER_I = {C_AXI_BUSER_WIDTH{1\'b0}}; ///////////////////////////////////////////////////////////////////////////// // SI-side output handling ///////////////////////////////////////////////////////////////////////////// // TODO: registered? assign S_AXI_BID = S_AXI_BID_I; assign S_AXI_BRESP = S_AXI_BRESP_I; assign S_AXI_BUSER = S_AXI_BUSER_I; assign S_AXI_BVALID = S_AXI_BVALID_I; assign S_AXI_BREADY_I = S_AXI_BREADY; endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_processing_system7_bfm.v * * Date : 2012-11 * * Description : Processing_system7_bfm Top (zynq_bfm top) * *****************************************************************************/ module processing_system7_bfm_v2_0_processing_system7_bfm ( CAN0_PHY_TX, CAN0_PHY_RX, CAN1_PHY_TX, CAN1_PHY_RX, ENET0_GMII_TX_EN, ENET0_GMII_TX_ER, ENET0_MDIO_MDC, ENET0_MDIO_O, ENET0_MDIO_T, ENET0_PTP_DELAY_REQ_RX, ENET0_PTP_DELAY_REQ_TX, ENET0_PTP_PDELAY_REQ_RX, ENET0_PTP_PDELAY_REQ_TX, ENET0_PTP_PDELAY_RESP_RX, ENET0_PTP_PDELAY_RESP_TX, ENET0_PTP_SYNC_FRAME_RX, ENET0_PTP_SYNC_FRAME_TX, ENET0_SOF_RX, ENET0_SOF_TX, ENET0_GMII_TXD, ENET0_GMII_COL, ENET0_GMII_CRS, ENET0_EXT_INTIN, ENET0_GMII_RX_CLK, ENET0_GMII_RX_DV, ENET0_GMII_RX_ER, ENET0_GMII_TX_CLK, ENET0_MDIO_I, ENET0_GMII_RXD, ENET1_GMII_TX_EN, ENET1_GMII_TX_ER, ENET1_MDIO_MDC, ENET1_MDIO_O, ENET1_MDIO_T, ENET1_PTP_DELAY_REQ_RX, ENET1_PTP_DELAY_REQ_TX, ENET1_PTP_PDELAY_REQ_RX, ENET1_PTP_PDELAY_REQ_TX, ENET1_PTP_PDELAY_RESP_RX, ENET1_PTP_PDELAY_RESP_TX, ENET1_PTP_SYNC_FRAME_RX, ENET1_PTP_SYNC_FRAME_TX, ENET1_SOF_RX, ENET1_SOF_TX, ENET1_GMII_TXD, ENET1_GMII_COL, ENET1_GMII_CRS, ENET1_EXT_INTIN, ENET1_GMII_RX_CLK, ENET1_GMII_RX_DV, ENET1_GMII_RX_ER, ENET1_GMII_TX_CLK, ENET1_MDIO_I, ENET1_GMII_RXD, GPIO_I, GPIO_O, GPIO_T, I2C0_SDA_I, I2C0_SDA_O, I2C0_SDA_T, I2C0_SCL_I, I2C0_SCL_O, I2C0_SCL_T, I2C1_SDA_I, I2C1_SDA_O, I2C1_SDA_T, I2C1_SCL_I, I2C1_SCL_O, I2C1_SCL_T, PJTAG_TCK, PJTAG_TMS, PJTAG_TD_I, PJTAG_TD_T, PJTAG_TD_O, SDIO0_CLK, SDIO0_CLK_FB, SDIO0_CMD_O, SDIO0_CMD_I, SDIO0_CMD_T, SDIO0_DATA_I, SDIO0_DATA_O, SDIO0_DATA_T, SDIO0_LED, SDIO0_CDN, SDIO0_WP, SDIO0_BUSPOW, SDIO0_BUSVOLT, SDIO1_CLK, SDIO1_CLK_FB, SDIO1_CMD_O, SDIO1_CMD_I, SDIO1_CMD_T, SDIO1_DATA_I, SDIO1_DATA_O, SDIO1_DATA_T, SDIO1_LED, SDIO1_CDN, SDIO1_WP, SDIO1_BUSPOW, SDIO1_BUSVOLT, SPI0_SCLK_I, SPI0_SCLK_O, SPI0_SCLK_T, SPI0_MOSI_I, SPI0_MOSI_O, SPI0_MOSI_T, SPI0_MISO_I, SPI0_MISO_O, SPI0_MISO_T, SPI0_SS_I, SPI0_SS_O, SPI0_SS1_O, SPI0_SS2_O, SPI0_SS_T, SPI1_SCLK_I, SPI1_SCLK_O, SPI1_SCLK_T, SPI1_MOSI_I, SPI1_MOSI_O, SPI1_MOSI_T, SPI1_MISO_I, SPI1_MISO_O, SPI1_MISO_T, SPI1_SS_I, SPI1_SS_O, SPI1_SS1_O, SPI1_SS2_O, SPI1_SS_T, UART0_DTRN, UART0_RTSN, UART0_TX, UART0_CTSN, UART0_DCDN, UART0_DSRN, UART0_RIN, UART0_RX, UART1_DTRN, UART1_RTSN, UART1_TX, UART1_CTSN, UART1_DCDN, UART1_DSRN, UART1_RIN, UART1_RX, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, TTC0_CLK0_IN, TTC0_CLK1_IN, TTC0_CLK2_IN, TTC1_WAVE0_OUT, TTC1_WAVE1_OUT, TTC1_WAVE2_OUT, TTC1_CLK0_IN, TTC1_CLK1_IN, TTC1_CLK2_IN, WDT_CLK_IN, WDT_RST_OUT, TRACE_CLK, TRACE_CTL, TRACE_DATA, USB0_PORT_INDCTL, USB1_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB1_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT, USB1_VBUS_PWRFAULT, SRAM_INTIN, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST, M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR, M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS, M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK, M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST, M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP, M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, M_AXI_GP1_ARVALID, M_AXI_GP1_AWVALID, M_AXI_GP1_BREADY, M_AXI_GP1_RREADY, M_AXI_GP1_WLAST, M_AXI_GP1_WVALID, M_AXI_GP1_ARID, M_AXI_GP1_AWID, M_AXI_GP1_WID, M_AXI_GP1_ARBURST, M_AXI_GP1_ARLOCK, M_AXI_GP1_ARSIZE, M_AXI_GP1_AWBURST, M_AXI_GP1_AWLOCK, M_AXI_GP1_AWSIZE, M_AXI_GP1_ARPROT, M_AXI_GP1_AWPROT, M_AXI_GP1_ARADDR, M_AXI_GP1_AWADDR, M_AXI_GP1_WDATA, M_AXI_GP1_ARCACHE, M_AXI_GP1_ARLEN, M_AXI_GP1_ARQOS, M_AXI_GP1_AWCACHE, M_AXI_GP1_AWLEN, M_AXI_GP1_AWQOS, M_AXI_GP1_WSTRB, M_AXI_GP1_ACLK, M_AXI_GP1_ARREADY, M_AXI_GP1_AWREADY, M_AXI_GP1_BVALID, M_AXI_GP1_RLAST, M_AXI_GP1_RVALID, M_AXI_GP1_WREADY, M_AXI_GP1_BID, M_AXI_GP1_RID, M_AXI_GP1_BRESP, M_AXI_GP1_RRESP, M_AXI_GP1_RDATA, S_AXI_GP0_ARREADY, S_AXI_GP0_AWREADY, S_AXI_GP0_BVALID, S_AXI_GP0_RLAST, S_AXI_GP0_RVALID, S_AXI_GP0_WREADY, S_AXI_GP0_BRESP, S_AXI_GP0_RRESP, S_AXI_GP0_RDATA, S_AXI_GP0_BID, S_AXI_GP0_RID, S_AXI_GP0_ACLK, S_AXI_GP0_ARVALID, S_AXI_GP0_AWVALID, S_AXI_GP0_BREADY, S_AXI_GP0_RREADY, S_AXI_GP0_WLAST, S_AXI_GP0_WVALID, S_AXI_GP0_ARBURST, S_AXI_GP0_ARLOCK, S_AXI_GP0_ARSIZE, S_AXI_GP0_AWBURST, S_AXI_GP0_AWLOCK, S_AXI_GP0_AWSIZE, S_AXI_GP0_ARPROT, S_AXI_GP0_AWPROT, S_AXI_GP0_ARADDR, S_AXI_GP0_AWADDR, S_AXI_GP0_WDATA, S_AXI_GP0_ARCACHE, S_AXI_GP0_ARLEN, S_AXI_GP0_ARQOS, S_AXI_GP0_AWCACHE, S_AXI_GP0_AWLEN, S_AXI_GP0_AWQOS, S_AXI_GP0_WSTRB, S_AXI_GP0_ARID, S_AXI_GP0_AWID, S_AXI_GP0_WID, S_AXI_GP1_ARREADY, S_AXI_GP1_AWREADY, S_AXI_GP1_BVALID, S_AXI_GP1_RLAST, S_AXI_GP1_RVALID, S_AXI_GP1_WREADY, S_AXI_GP1_BRESP, S_AXI_GP1_RRESP, S_AXI_GP1_RDATA, S_AXI_GP1_BID, S_AXI_GP1_RID, S_AXI_GP1_ACLK, S_AXI_GP1_ARVALID, S_AXI_GP1_AWVALID, S_AXI_GP1_BREADY, S_AXI_GP1_RREADY, S_AXI_GP1_WLAST, S_AXI_GP1_WVALID, S_AXI_GP1_ARBURST, S_AXI_GP1_ARLOCK, S_AXI_GP1_ARSIZE, S_AXI_GP1_AWBURST, S_AXI_GP1_AWLOCK, S_AXI_GP1_AWSIZE, S_AXI_GP1_ARPROT, S_AXI_GP1_AWPROT, S_AXI_GP1_ARADDR, S_AXI_GP1_AWADDR, S_AXI_GP1_WDATA, S_AXI_GP1_ARCACHE, S_AXI_GP1_ARLEN, S_AXI_GP1_ARQOS, S_AXI_GP1_AWCACHE, S_AXI_GP1_AWLEN, S_AXI_GP1_AWQOS, S_AXI_GP1_WSTRB, S_AXI_GP1_ARID, S_AXI_GP1_AWID, S_AXI_GP1_WID, S_AXI_ACP_AWREADY, S_AXI_ACP_ARREADY, S_AXI_ACP_BVALID, S_AXI_ACP_RLAST, S_AXI_ACP_RVALID, S_AXI_ACP_WREADY, S_AXI_ACP_BRESP, S_AXI_ACP_RRESP, S_AXI_ACP_BID, S_AXI_ACP_RID, S_AXI_ACP_RDATA, S_AXI_ACP_ACLK, S_AXI_ACP_ARVALID, S_AXI_ACP_AWVALID, S_AXI_ACP_BREADY, S_AXI_ACP_RREADY, S_AXI_ACP_WLAST, S_AXI_ACP_WVALID, S_AXI_ACP_ARID, S_AXI_ACP_ARPROT, S_AXI_ACP_AWID, S_AXI_ACP_AWPROT, S_AXI_ACP_WID, S_AXI_ACP_ARADDR, S_AXI_ACP_AWADDR, S_AXI_ACP_ARCACHE, S_AXI_ACP_ARLEN, S_AXI_ACP_ARQOS, S_AXI_ACP_AWCACHE, S_AXI_ACP_AWLEN, S_AXI_ACP_AWQOS, S_AXI_ACP_ARBURST, S_AXI_ACP_ARLOCK, S_AXI_ACP_ARSIZE, S_AXI_ACP_AWBURST, S_AXI_ACP_AWLOCK, S_AXI_ACP_AWSIZE, S_AXI_ACP_ARUSER, S_AXI_ACP_AWUSER, S_AXI_ACP_WDATA, S_AXI_ACP_WSTRB, S_AXI_HP0_ARREADY, S_AXI_HP0_AWREADY, S_AXI_HP0_BVALID, S_AXI_HP0_RLAST, S_AXI_HP0_RVALID, S_AXI_HP0_WREADY, S_AXI_HP0_BRESP, S_AXI_HP0_RRESP, S_AXI_HP0_BID, S_AXI_HP0_RID, S_AXI_HP0_RDATA, S_AXI_HP0_RCOUNT, S_AXI_HP0_WCOUNT, S_AXI_HP0_RACOUNT, S_AXI_HP0_WACOUNT, S_AXI_HP0_ACLK, S_AXI_HP0_ARVALID, S_AXI_HP0_AWVALID, S_AXI_HP0_BREADY, S_AXI_HP0_RDISSUECAP1_EN, S_AXI_HP0_RREADY, S_AXI_HP0_WLAST, S_AXI_HP0_WRISSUECAP1_EN, S_AXI_HP0_WVALID, S_AXI_HP0_ARBURST, S_AXI_HP0_ARLOCK, S_AXI_HP0_ARSIZE, S_AXI_HP0_AWBURST, S_AXI_HP0_AWLOCK, S_AXI_HP0_AWSIZE, S_AXI_HP0_ARPROT, S_AXI_HP0_AWPROT, S_AXI_HP0_ARADDR, S_AXI_HP0_AWADDR, S_AXI_HP0_ARCACHE, S_AXI_HP0_ARLEN, S_AXI_HP0_ARQOS, S_AXI_HP0_AWCACHE, S_AXI_HP0_AWLEN, S_AXI_HP0_AWQOS, S_AXI_HP0_ARID, S_AXI_HP0_AWID, S_AXI_HP0_WID, S_AXI_HP0_WDATA, S_AXI_HP0_WSTRB, S_AXI_HP1_ARREADY, S_AXI_HP1_AWREADY, S_AXI_HP1_BVALID, S_AXI_HP1_RLAST, S_AXI_HP1_RVALID, S_AXI_HP1_WREADY, S_AXI_HP1_BRESP, S_AXI_HP1_RRESP, S_AXI_HP1_BID, S_AXI_HP1_RID, S_AXI_HP1_RDATA, S_AXI_HP1_RCOUNT, S_AXI_HP1_WCOUNT, S_AXI_HP1_RACOUNT, S_AXI_HP1_WACOUNT, S_AXI_HP1_ACLK, S_AXI_HP1_ARVALID, S_AXI_HP1_AWVALID, S_AXI_HP1_BREADY, S_AXI_HP1_RDISSUECAP1_EN, S_AXI_HP1_RREADY, S_AXI_HP1_WLAST, S_AXI_HP1_WRISSUECAP1_EN, S_AXI_HP1_WVALID, S_AXI_HP1_ARBURST, S_AXI_HP1_ARLOCK, S_AXI_HP1_ARSIZE, S_AXI_HP1_AWBURST, S_AXI_HP1_AWLOCK, S_AXI_HP1_AWSIZE, S_AXI_HP1_ARPROT, S_AXI_HP1_AWPROT, S_AXI_HP1_ARADDR, S_AXI_HP1_AWADDR, S_AXI_HP1_ARCACHE, S_AXI_HP1_ARLEN, S_AXI_HP1_ARQOS, S_AXI_HP1_AWCACHE, S_AXI_HP1_AWLEN, S_AXI_HP1_AWQOS, S_AXI_HP1_ARID, S_AXI_HP1_AWID, S_AXI_HP1_WID, S_AXI_HP1_WDATA, S_AXI_HP1_WSTRB, S_AXI_HP2_ARREADY, S_AXI_HP2_AWREADY, S_AXI_HP2_BVALID, S_AXI_HP2_RLAST, S_AXI_HP2_RVALID, S_AXI_HP2_WREADY, S_AXI_HP2_BRESP, S_AXI_HP2_RRESP, S_AXI_HP2_BID, S_AXI_HP2_RID, S_AXI_HP2_RDATA, S_AXI_HP2_RCOUNT, S_AXI_HP2_WCOUNT, S_AXI_HP2_RACOUNT, S_AXI_HP2_WACOUNT, S_AXI_HP2_ACLK, S_AXI_HP2_ARVALID, S_AXI_HP2_AWVALID, S_AXI_HP2_BREADY, S_AXI_HP2_RDISSUECAP1_EN, S_AXI_HP2_RREADY, S_AXI_HP2_WLAST, S_AXI_HP2_WRISSUECAP1_EN, S_AXI_HP2_WVALID, S_AXI_HP2_ARBURST, S_AXI_HP2_ARLOCK, S_AXI_HP2_ARSIZE, S_AXI_HP2_AWBURST, S_AXI_HP2_AWLOCK, S_AXI_HP2_AWSIZE, S_AXI_HP2_ARPROT, S_AXI_HP2_AWPROT, S_AXI_HP2_ARADDR, S_AXI_HP2_AWADDR, S_AXI_HP2_ARCACHE, S_AXI_HP2_ARLEN, S_AXI_HP2_ARQOS, S_AXI_HP2_AWCACHE, S_AXI_HP2_AWLEN, S_AXI_HP2_AWQOS, S_AXI_HP2_ARID, S_AXI_HP2_AWID, S_AXI_HP2_WID, S_AXI_HP2_WDATA, S_AXI_HP2_WSTRB, S_AXI_HP3_ARREADY, S_AXI_HP3_AWREADY, S_AXI_HP3_BVALID, S_AXI_HP3_RLAST, S_AXI_HP3_RVALID, S_AXI_HP3_WREADY, S_AXI_HP3_BRESP, S_AXI_HP3_RRESP, S_AXI_HP3_BID, S_AXI_HP3_RID, S_AXI_HP3_RDATA, S_AXI_HP3_RCOUNT, S_AXI_HP3_WCOUNT, S_AXI_HP3_RACOUNT, S_AXI_HP3_WACOUNT, S_AXI_HP3_ACLK, S_AXI_HP3_ARVALID, S_AXI_HP3_AWVALID, S_AXI_HP3_BREADY, S_AXI_HP3_RDISSUECAP1_EN, S_AXI_HP3_RREADY, S_AXI_HP3_WLAST, S_AXI_HP3_WRISSUECAP1_EN, S_AXI_HP3_WVALID, S_AXI_HP3_ARBURST, S_AXI_HP3_ARLOCK, S_AXI_HP3_ARSIZE, S_AXI_HP3_AWBURST, S_AXI_HP3_AWLOCK, S_AXI_HP3_AWSIZE, S_AXI_HP3_ARPROT, S_AXI_HP3_AWPROT, S_AXI_HP3_ARADDR, S_AXI_HP3_AWADDR, S_AXI_HP3_ARCACHE, S_AXI_HP3_ARLEN, S_AXI_HP3_ARQOS, S_AXI_HP3_AWCACHE, S_AXI_HP3_AWLEN, S_AXI_HP3_AWQOS, S_AXI_HP3_ARID, S_AXI_HP3_AWID, S_AXI_HP3_WID, S_AXI_HP3_WDATA, S_AXI_HP3_WSTRB, DMA0_DATYPE, DMA0_DAVALID, DMA0_DRREADY, DMA0_ACLK, DMA0_DAREADY, DMA0_DRLAST, DMA0_DRVALID, DMA0_DRTYPE, DMA1_DATYPE, DMA1_DAVALID, DMA1_DRREADY, DMA1_ACLK, DMA1_DAREADY, DMA1_DRLAST, DMA1_DRVALID, DMA1_DRTYPE, DMA2_DATYPE, DMA2_DAVALID, DMA2_DRREADY, DMA2_ACLK, DMA2_DAREADY, DMA2_DRLAST, DMA2_DRVALID, DMA3_DRVALID, DMA3_DATYPE, DMA3_DAVALID, DMA3_DRREADY, DMA3_ACLK, DMA3_DAREADY, DMA3_DRLAST, DMA2_DRTYPE, DMA3_DRTYPE, FTMD_TRACEIN_DATA, FTMD_TRACEIN_VALID, FTMD_TRACEIN_CLK, FTMD_TRACEIN_ATID, FTMT_F2P_TRIG, FTMT_F2P_TRIGACK, FTMT_F2P_DEBUG, FTMT_P2F_TRIGACK, FTMT_P2F_TRIG, FTMT_P2F_DEBUG, FCLK_CLK3, FCLK_CLK2, FCLK_CLK1, FCLK_CLK0, FCLK_CLKTRIG3_N, FCLK_CLKTRIG2_N, FCLK_CLKTRIG1_N, FCLK_CLKTRIG0_N, FCLK_RESET3_N, FCLK_RESET2_N, FCLK_RESET1_N, FCLK_RESET0_N, FPGA_IDLE_N, DDR_ARB, IRQ_F2P, Core0_nFIQ, Core0_nIRQ, Core1_nFIQ, Core1_nIRQ, EVENT_EVENTO, EVENT_STANDBYWFE, EVENT_STANDBYWFI, EVENT_EVENTI, MIO, DDR_Clk, DDR_Clk_n, DDR_CKE, DDR_CS_n, DDR_RAS_n, DDR_CAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_ODT, DDR_DRSTB, DDR_DQ, DDR_DM, DDR_DQS, DDR_DQS_n, DDR_VRN, DDR_VRP, PS_SRSTB, PS_CLK, PS_PORB, IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC0, IRQ_P2F_DMAC1, IRQ_P2F_DMAC2, IRQ_P2F_DMAC3, IRQ_P2F_DMAC4, IRQ_P2F_DMAC5, IRQ_P2F_DMAC6, IRQ_P2F_DMAC7, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1 ); /* parameters for gen_clk */ parameter C_FCLK_CLK0_FREQ = 50; parameter C_FCLK_CLK1_FREQ = 50; parameter C_FCLK_CLK3_FREQ = 50; parameter C_FCLK_CLK2_FREQ = 50; parameter C_HIGH_OCM_EN = 0; /* parameters for HP ports */ parameter C_USE_S_AXI_HP0 = 0; parameter C_USE_S_AXI_HP1 = 0; parameter C_USE_S_AXI_HP2 = 0; parameter C_USE_S_AXI_HP3 = 0; parameter C_S_AXI_HP0_DATA_WIDTH = 32; parameter C_S_AXI_HP1_DATA_WIDTH = 32; parameter C_S_AXI_HP2_DATA_WIDTH = 32; parameter C_S_AXI_HP3_DATA_WIDTH = 32; parameter C_M_AXI_GP0_THREAD_ID_WIDTH = 12; parameter C_M_AXI_GP1_THREAD_ID_WIDTH = 12; parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP = 0; parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP = 0; /* Do we need these parameter C_S_AXI_HP0_ENABLE_HIGHOCM = 0; parameter C_S_AXI_HP1_ENABLE_HIGHOCM = 0; parameter C_S_AXI_HP2_ENABLE_HIGHOCM = 0; parameter C_S_AXI_HP3_ENABLE_HIGHOCM = 0; */ parameter C_S_AXI_HP0_BASEADDR = 32\'h0000_0000; parameter C_S_AXI_HP1_BASEADDR = 32\'h0000_0000; parameter C_S_AXI_HP2_BASEADDR = 32\'h0000_0000; parameter C_S_AXI_HP3_BASEADDR = 32\'h0000_0000; parameter C_S_AXI_HP0_HIGHADDR = 32\'hFFFF_FFFF; parameter C_S_AXI_HP1_HIGHADDR = 32\'hFFFF_FFFF; parameter C_S_AXI_HP2_HIGHADDR = 32\'hFFFF_FFFF; parameter C_S_AXI_HP3_HIGHADDR = 32\'hFFFF_FFFF; /* parameters for GP and ACP ports */ parameter C_USE_M_AXI_GP0 = 0; parameter C_USE_M_AXI_GP1 = 0; parameter C_USE_S_AXI_GP0 = 1; parameter C_USE_S_AXI_GP1 = 1; /* Do we need this? parameter C_M_AXI_GP0_ENABLE_HIGHOCM = 0; parameter C_M_AXI_GP1_ENABLE_HIGHOCM = 0; parameter C_S_AXI_GP0_ENABLE_HIGHOCM = 0; parameter C_S_AXI_GP1_ENABLE_HIGHOCM = 0; parameter C_S_AXI_ACP_ENABLE_HIGHOCM = 0;*/ parameter C_S_AXI_GP0_BASEADDR = 32\'h0000_0000; parameter C_S_AXI_GP1_BASEADDR = 32\'h0000_0000; parameter C_S_AXI_GP0_HIGHADDR = 32\'hFFFF_FFFF; parameter C_S_AXI_GP1_HIGHADDR = 32\'hFFFF_FFFF; parameter C_USE_S_AXI_ACP = 1; parameter C_S_AXI_ACP_BASEADDR = 32\'h0000_0000; parameter C_S_AXI_ACP_HIGHADDR = 32\'hFFFF_FFFF; `include "processing_system7_bfm_v2_0_local_params.v" output CAN0_PHY_TX; input CAN0_PHY_RX; output CAN1_PHY_TX; input CAN1_PHY_RX; output ENET0_GMII_TX_EN; output ENET0_GMII_TX_ER; output ENET0_MDIO_MDC; output ENET0_MDIO_O; output ENET0_MDIO_T; output ENET0_PTP_DELAY_REQ_RX; output ENET0_PTP_DELAY_REQ_TX; output ENET0_PTP_PDELAY_REQ_RX; output ENET0_PTP_PDELAY_REQ_TX; output ENET0_PTP_PDELAY_RESP_RX; output ENET0_PTP_PDELAY_RESP_TX; output ENET0_PTP_SYNC_FRAME_RX; output ENET0_PTP_SYNC_FRAME_TX; output ENET0_SOF_RX; output ENET0_SOF_TX; output [7:0] ENET0_GMII_TXD; input ENET0_GMII_COL; input ENET0_GMII_CRS; input ENET0_EXT_INTIN; input ENET0_GMII_RX_CLK; input ENET0_GMII_RX_DV; input ENET0_GMII_RX_ER; input ENET0_GMII_TX_CLK; input ENET0_MDIO_I; input [7:0] ENET0_GMII_RXD; output ENET1_GMII_TX_EN; output ENET1_GMII_TX_ER; output ENET1_MDIO_MDC; output ENET1_MDIO_O; output ENET1_MDIO_T; output ENET1_PTP_DELAY_REQ_RX; output ENET1_PTP_DELAY_REQ_TX; output ENET1_PTP_PDELAY_REQ_RX; output ENET1_PTP_PDELAY_REQ_TX; output ENET1_PTP_PDELAY_RESP_RX; output ENET1_PTP_PDELAY_RESP_TX; output ENET1_PTP_SYNC_FRAME_RX; output ENET1_PTP_SYNC_FRAME_TX; output ENET1_SOF_RX; output ENET1_SOF_TX; output [7:0] ENET1_GMII_TXD; input ENET1_GMII_COL; input ENET1_GMII_CRS; input ENET1_EXT_INTIN; input ENET1_GMII_RX_CLK; input ENET1_GMII_RX_DV; input ENET1_GMII_RX_ER; input ENET1_GMII_TX_CLK; input ENET1_MDIO_I; input [7:0] ENET1_GMII_RXD; input [63:0] GPIO_I; output [63:0] GPIO_O; output [63:0] GPIO_T; input I2C0_SDA_I; output I2C0_SDA_O; output I2C0_SDA_T; input I2C0_SCL_I; output I2C0_SCL_O; output I2C0_SCL_T; input I2C1_SDA_I; output I2C1_SDA_O; output I2C1_SDA_T; input I2C1_SCL_I; output I2C1_SCL_O; output I2C1_SCL_T; input PJTAG_TCK; input PJTAG_TMS; input PJTAG_TD_I; output PJTAG_TD_T; output PJTAG_TD_O; output SDIO0_CLK; input SDIO0_CLK_FB; output SDIO0_CMD_O; input SDIO0_CMD_I; output SDIO0_CMD_T; input [3:0] SDIO0_DATA_I; output [3:0] SDIO0_DATA_O; output [3:0] SDIO0_DATA_T; output SDIO0_LED; input SDIO0_CDN; input SDIO0_WP; output SDIO0_BUSPOW; output [2:0] SDIO0_BUSVOLT; output SDIO1_CLK; input SDIO1_CLK_FB; output SDIO1_CMD_O; input SDIO1_CMD_I; output SDIO1_CMD_T; input [3:0] SDIO1_DATA_I; output [3:0] SDIO1_DATA_O; output [3:0] SDIO1_DATA_T; output SDIO1_LED; input SDIO1_CDN; input SDIO1_WP; output SDIO1_BUSPOW; output [2:0] SDIO1_BUSVOLT; input SPI0_SCLK_I; output SPI0_SCLK_O; output SPI0_SCLK_T; input SPI0_MOSI_I; output SPI0_MOSI_O; output SPI0_MOSI_T; input SPI0_MISO_I; output SPI0_MISO_O; output SPI0_MISO_T; input SPI0_SS_I; output SPI0_SS_O; output SPI0_SS1_O; output SPI0_SS2_O; output SPI0_SS_T; input SPI1_SCLK_I; output SPI1_SCLK_O; output SPI1_SCLK_T; input SPI1_MOSI_I; output SPI1_MOSI_O; output SPI1_MOSI_T; input SPI1_MISO_I; output SPI1_MISO_O; output SPI1_MISO_T; input SPI1_SS_I; output SPI1_SS_O; output SPI1_SS1_O; output SPI1_SS2_O; output SPI1_SS_T; output UART0_DTRN; output UART0_RTSN; output UART0_TX; input UART0_CTSN; input UART0_DCDN; input UART0_DSRN; input UART0_RIN; input UART0_RX; output UART1_DTRN; output UART1_RTSN; output UART1_TX; input UART1_CTSN; input UART1_DCDN; input UART1_DSRN; input UART1_RIN; input UART1_RX; output TTC0_WAVE0_OUT; output TTC0_WAVE1_OUT; output TTC0_WAVE2_OUT; input TTC0_CLK0_IN; input TTC0_CLK1_IN; input TTC0_CLK2_IN; output TTC1_WAVE0_OUT; output TTC1_WAVE1_OUT; output TTC1_WAVE2_OUT; input TTC1_CLK0_IN; input TTC1_CLK1_IN; input TTC1_CLK2_IN; input WDT_CLK_IN; output WDT_RST_OUT; input TRACE_CLK; output TRACE_CTL; output [31:0] TRACE_DATA; output [1:0] USB0_PORT_INDCTL; output [1:0] USB1_PORT_INDCTL; output USB0_VBUS_PWRSELECT; output USB1_VBUS_PWRSELECT; input USB0_VBUS_PWRFAULT; input USB1_VBUS_PWRFAULT; input SRAM_INTIN; output M_AXI_GP0_ARVALID; output M_AXI_GP0_AWVALID; output M_AXI_GP0_BREADY; output M_AXI_GP0_RREADY; output M_AXI_GP0_WLAST; output M_AXI_GP0_WVALID; output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_ARID; output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_AWID; output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_WID; output [1:0] M_AXI_GP0_ARBURST; output [1:0] M_AXI_GP0_ARLOCK; output [2:0] M_AXI_GP0_ARSIZE; output [1:0] M_AXI_GP0_AWBURST; output [1:0] M_AXI_GP0_AWLOCK; output [2:0] M_AXI_GP0_AWSIZE; output [2:0] M_AXI_GP0_ARPROT; output [2:0] M_AXI_GP0_AWPROT; output [31:0] M_AXI_GP0_ARADDR; output [31:0] M_AXI_GP0_AWADDR; output [31:0] M_AXI_GP0_WDATA; output [3:0] M_AXI_GP0_ARCACHE; output [3:0] M_AXI_GP0_ARLEN; output [3:0] M_AXI_GP0_ARQOS; output [3:0] M_AXI_GP0_AWCACHE; output [3:0] M_AXI_GP0_AWLEN; output [3:0] M_AXI_GP0_AWQOS; output [3:0] M_AXI_GP0_WSTRB; input M_AXI_GP0_ACLK; input M_AXI_GP0_ARREADY; input M_AXI_GP0_AWREADY; input M_AXI_GP0_BVALID; input M_AXI_GP0_RLAST; input M_AXI_GP0_RVALID; input M_AXI_GP0_WREADY; input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_BID; input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_RID; input [1:0] M_AXI_GP0_BRESP; input [1:0] M_AXI_GP0_RRESP; input [31:0] M_AXI_GP0_RDATA; output M_AXI_GP1_ARVALID; output M_AXI_GP1_AWVALID; output M_AXI_GP1_BREADY; output M_AXI_GP1_RREADY; output M_AXI_GP1_WLAST; output M_AXI_GP1_WVALID; output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_ARID; output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_AWID; output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_WID; output [1:0] M_AXI_GP1_ARBURST; output [1:0] M_AXI_GP1_ARLOCK; output [2:0] M_AXI_GP1_ARSIZE; output [1:0] M_AXI_GP1_AWBURST; output [1:0] M_AXI_GP1_AWLOCK; output [2:0] M_AXI_GP1_AWSIZE; output [2:0] M_AXI_GP1_ARPROT; output [2:0] M_AXI_GP1_AWPROT; output [31:0] M_AXI_GP1_ARADDR; output [31:0] M_AXI_GP1_AWADDR; output [31:0] M_AXI_GP1_WDATA; output [3:0] M_AXI_GP1_ARCACHE; output [3:0] M_AXI_GP1_ARLEN; output [3:0] M_AXI_GP1_ARQOS; output [3:0] M_AXI_GP1_AWCACHE; output [3:0] M_AXI_GP1_AWLEN; output [3:0] M_AXI_GP1_AWQOS; output [3:0] M_AXI_GP1_WSTRB; input M_AXI_GP1_ACLK; input M_AXI_GP1_ARREADY; input M_AXI_GP1_AWREADY; input M_AXI_GP1_BVALID; input M_AXI_GP1_RLAST; input M_AXI_GP1_RVALID; input M_AXI_GP1_WREADY; input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_BID; input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_RID; input [1:0] M_AXI_GP1_BRESP; input [1:0] M_AXI_GP1_RRESP; input [31:0] M_AXI_GP1_RDATA; output S_AXI_GP0_ARREADY; output S_AXI_GP0_AWREADY; output S_AXI_GP0_BVALID; output S_AXI_GP0_RLAST; output S_AXI_GP0_RVALID; output S_AXI_GP0_WREADY; output [1:0] S_AXI_GP0_BRESP; output [1:0] S_AXI_GP0_RRESP; output [31:0] S_AXI_GP0_RDATA; output [5:0] S_AXI_GP0_BID; output [5:0] S_AXI_GP0_RID; input S_AXI_GP0_ACLK; input S_AXI_GP0_ARVALID; input S_AXI_GP0_AWVALID; input S_AXI_GP0_BREADY; input S_AXI_GP0_RREADY; input S_AXI_GP0_WLAST; input S_AXI_GP0_WVALID; input [1:0] S_AXI_GP0_ARBURST; input [1:0] S_AXI_GP0_ARLOCK; input [2:0] S_AXI_GP0_ARSIZE; input [1:0] S_AXI_GP0_AWBURST; input [1:0] S_AXI_GP0_AWLOCK; input [2:0] S_AXI_GP0_AWSIZE; input [2:0] S_AXI_GP0_ARPROT; input [2:0] S_AXI_GP0_AWPROT; input [31:0] S_AXI_GP0_ARADDR; input [31:0] S_AXI_GP0_AWADDR; input [31:0] S_AXI_GP0_WDATA; input [3:0] S_AXI_GP0_ARCACHE; input [3:0] S_AXI_GP0_ARLEN; input [3:0] S_AXI_GP0_ARQOS; input [3:0] S_AXI_GP0_AWCACHE; input [3:0] S_AXI_GP0_AWLEN; input [3:0] S_AXI_GP0_AWQOS; input [3:0] S_AXI_GP0_WSTRB; input [5:0] S_AXI_GP0_ARID; input [5:0] S_AXI_GP0_AWID; input [5:0] S_AXI_GP0_WID; output S_AXI_GP1_ARREADY; output S_AXI_GP1_AWREADY; output S_AXI_GP1_BVALID; output S_AXI_GP1_RLAST; output S_AXI_GP1_RVALID; output S_AXI_GP1_WREADY; output [1:0] S_AXI_GP1_BRESP; output [1:0] S_AXI_GP1_RRESP; output [31:0] S_AXI_GP1_RDATA; output [5:0] S_AXI_GP1_BID; output [5:0] S_AXI_GP1_RID; input S_AXI_GP1_ACLK; input S_AXI_GP1_ARVALID; input S_AXI_GP1_AWVALID; input S_AXI_GP1_BREADY; input S_AXI_GP1_RREADY; input S_AXI_GP1_WLAST; input S_AXI_GP1_WVALID; input [1:0] S_AXI_GP1_ARBURST; input [1:0] S_AXI_GP1_ARLOCK; input [2:0] S_AXI_GP1_ARSIZE; input [1:0] S_AXI_GP1_AWBURST; input [1:0] S_AXI_GP1_AWLOCK; input [2:0] S_AXI_GP1_AWSIZE; input [2:0] S_AXI_GP1_ARPROT; input [2:0] S_AXI_GP1_AWPROT; input [31:0] S_AXI_GP1_ARADDR; input [31:0] S_AXI_GP1_AWADDR; input [31:0] S_AXI_GP1_WDATA; input [3:0] S_AXI_GP1_ARCACHE; input [3:0] S_AXI_GP1_ARLEN; input [3:0] S_AXI_GP1_ARQOS; input [3:0] S_AXI_GP1_AWCACHE; input [3:0] S_AXI_GP1_AWLEN; input [3:0] S_AXI_GP1_AWQOS; input [3:0] S_AXI_GP1_WSTRB; input [5:0] S_AXI_GP1_ARID; input [5:0] S_AXI_GP1_AWID; input [5:0] S_AXI_GP1_WID; output S_AXI_ACP_AWREADY; output S_AXI_ACP_ARREADY; output S_AXI_ACP_BVALID; output S_AXI_ACP_RLAST; output S_AXI_ACP_RVALID; output S_AXI_ACP_WREADY; output [1:0] S_AXI_ACP_BRESP; output [1:0] S_AXI_ACP_RRESP; output [2:0] S_AXI_ACP_BID; output [2:0] S_AXI_ACP_RID; output [63:0] S_AXI_ACP_RDATA; input S_AXI_ACP_ACLK; input S_AXI_ACP_ARVALID; input S_AXI_ACP_AWVALID; input S_AXI_ACP_BREADY; input S_AXI_ACP_RREADY; input S_AXI_ACP_WLAST; input S_AXI_ACP_WVALID; input [2:0] S_AXI_ACP_ARID; input [2:0] S_AXI_ACP_ARPROT; input [2:0] S_AXI_ACP_AWID; input [2:0] S_AXI_ACP_AWPROT; input [2:0] S_AXI_ACP_WID; input [31:0] S_AXI_ACP_ARADDR; input [31:0] S_AXI_ACP_AWADDR; input [3:0] S_AXI_ACP_ARCACHE; input [3:0] S_AXI_ACP_ARLEN; input [3:0] S_AXI_ACP_ARQOS; input [3:0] S_AXI_ACP_AWCACHE; input [3:0] S_AXI_ACP_AWLEN; input [3:0] S_AXI_ACP_AWQOS; input [1:0] S_AXI_ACP_ARBURST; input [1:0] S_AXI_ACP_ARLOCK; input [2:0] S_AXI_ACP_ARSIZE; input [1:0] S_AXI_ACP_AWBURST; input [1:0] S_AXI_ACP_AWLOCK; input [2:0] S_AXI_ACP_AWSIZE; input [4:0] S_AXI_ACP_ARUSER; input [4:0] S_AXI_ACP_AWUSER; input [63:0] S_AXI_ACP_WDATA; input [7:0] S_AXI_ACP_WSTRB; output S_AXI_HP0_ARREADY; output S_AXI_HP0_AWREADY; output S_AXI_HP0_BVALID; output S_AXI_HP0_RLAST; output S_AXI_HP0_RVALID; output S_AXI_HP0_WREADY; output [1:0] S_AXI_HP0_BRESP; output [1:0] S_AXI_HP0_RRESP; output [5:0] S_AXI_HP0_BID; output [5:0] S_AXI_HP0_RID; output [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_RDATA; output [7:0] S_AXI_HP0_RCOUNT; output [7:0] S_AXI_HP0_WCOUNT; output [2:0] S_AXI_HP0_RACOUNT; output [5:0] S_AXI_HP0_WACOUNT; input S_AXI_HP0_ACLK; input S_AXI_HP0_ARVALID; input S_AXI_HP0_AWVALID; input S_AXI_HP0_BREADY; input S_AXI_HP0_RDISSUECAP1_EN; input S_AXI_HP0_RREADY; input S_AXI_HP0_WLAST; input S_AXI_HP0_WRISSUECAP1_EN; input S_AXI_HP0_WVALID; input [1:0] S_AXI_HP0_ARBURST; input [1:0] S_AXI_HP0_ARLOCK; input [2:0] S_AXI_HP0_ARSIZE; input [1:0] S_AXI_HP0_AWBURST; input [1:0] S_AXI_HP0_AWLOCK; input [2:0] S_AXI_HP0_AWSIZE; input [2:0] S_AXI_HP0_ARPROT; input [2:0] S_AXI_HP0_AWPROT; input [31:0] S_AXI_HP0_ARADDR; input [31:0] S_AXI_HP0_AWADDR; input [3:0] S_AXI_HP0_ARCACHE; input [3:0] S_AXI_HP0_ARLEN; input [3:0] S_AXI_HP0_ARQOS; input [3:0] S_AXI_HP0_AWCACHE; input [3:0] S_AXI_HP0_AWLEN; input [3:0] S_AXI_HP0_AWQOS; input [5:0] S_AXI_HP0_ARID; input [5:0] S_AXI_HP0_AWID; input [5:0] S_AXI_HP0_WID; input [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_WDATA; input [C_S_AXI_HP0_DATA_WIDTH/8-1:0] S_AXI_HP0_WSTRB; output S_AXI_HP1_ARREADY; output S_AXI_HP1_AWREADY; output S_AXI_HP1_BVALID; output S_AXI_HP1_RLAST; output S_AXI_HP1_RVALID; output S_AXI_HP1_WREADY; output [1:0] S_AXI_HP1_BRESP; output [1:0] S_AXI_HP1_RRESP; output [5:0] S_AXI_HP1_BID; output [5:0] S_AXI_HP1_RID; output [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_RDATA; output [7:0] S_AXI_HP1_RCOUNT; output [7:0] S_AXI_HP1_WCOUNT; output [2:0] S_AXI_HP1_RACOUNT; output [5:0] S_AXI_HP1_WACOUNT; input S_AXI_HP1_ACLK; input S_AXI_HP1_ARVALID; input S_AXI_HP1_AWVALID; input S_AXI_HP1_BREADY; input S_AXI_HP1_RDISSUECAP1_EN; input S_AXI_HP1_RREADY; input S_AXI_HP1_WLAST; input S_AXI_HP1_WRISSUECAP1_EN; input S_AXI_HP1_WVALID; input [1:0] S_AXI_HP1_ARBURST; input [1:0] S_AXI_HP1_ARLOCK; input [2:0] S_AXI_HP1_ARSIZE; input [1:0] S_AXI_HP1_AWBURST; input [1:0] S_AXI_HP1_AWLOCK; input [2:0] S_AXI_HP1_AWSIZE; input [2:0] S_AXI_HP1_ARPROT; input [2:0] S_AXI_HP1_AWPROT; input [31:0] S_AXI_HP1_ARADDR; input [31:0] S_AXI_HP1_AWADDR; input [3:0] S_AXI_HP1_ARCACHE; input [3:0] S_AXI_HP1_ARLEN; input [3:0] S_AXI_HP1_ARQOS; input [3:0] S_AXI_HP1_AWCACHE; input [3:0] S_AXI_HP1_AWLEN; input [3:0] S_AXI_HP1_AWQOS; input [5:0] S_AXI_HP1_ARID; input [5:0] S_AXI_HP1_AWID; input [5:0] S_AXI_HP1_WID; input [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_WDATA; input [C_S_AXI_HP1_DATA_WIDTH/8-1:0] S_AXI_HP1_WSTRB; output S_AXI_HP2_ARREADY; output S_AXI_HP2_AWREADY; output S_AXI_HP2_BVALID; output S_AXI_HP2_RLAST; output S_AXI_HP2_RVALID; output S_AXI_HP2_WREADY; output [1:0] S_AXI_HP2_BRESP; output [1:0] S_AXI_HP2_RRESP; output [5:0] S_AXI_HP2_BID; output [5:0] S_AXI_HP2_RID; output [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_RDATA; output [7:0] S_AXI_HP2_RCOUNT; output [7:0] S_AXI_HP2_WCOUNT; output [2:0] S_AXI_HP2_RACOUNT; output [5:0] S_AXI_HP2_WACOUNT; input S_AXI_HP2_ACLK; input S_AXI_HP2_ARVALID; input S_AXI_HP2_AWVALID; input S_AXI_HP2_BREADY; input S_AXI_HP2_RDISSUECAP1_EN; input S_AXI_HP2_RREADY; input S_AXI_HP2_WLAST; input S_AXI_HP2_WRISSUECAP1_EN; input S_AXI_HP2_WVALID; input [1:0] S_AXI_HP2_ARBURST; input [1:0] S_AXI_HP2_ARLOCK; input [2:0] S_AXI_HP2_ARSIZE; input [1:0] S_AXI_HP2_AWBURST; input [1:0] S_AXI_HP2_AWLOCK; input [2:0] S_AXI_HP2_AWSIZE; input [2:0] S_AXI_HP2_ARPROT; input [2:0] S_AXI_HP2_AWPROT; input [31:0] S_AXI_HP2_ARADDR; input [31:0] S_AXI_HP2_AWADDR; input [3:0] S_AXI_HP2_ARCACHE; input [3:0] S_AXI_HP2_ARLEN; input [3:0] S_AXI_HP2_ARQOS; input [3:0] S_AXI_HP2_AWCACHE; input [3:0] S_AXI_HP2_AWLEN; input [3:0] S_AXI_HP2_AWQOS; input [5:0] S_AXI_HP2_ARID; input [5:0] S_AXI_HP2_AWID; input [5:0] S_AXI_HP2_WID; input [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_WDATA; input [C_S_AXI_HP2_DATA_WIDTH/8-1:0] S_AXI_HP2_WSTRB; output S_AXI_HP3_ARREADY; output S_AXI_HP3_AWREADY; output S_AXI_HP3_BVALID; output S_AXI_HP3_RLAST; output S_AXI_HP3_RVALID; output S_AXI_HP3_WREADY; output [1:0] S_AXI_HP3_BRESP; output [1:0] S_AXI_HP3_RRESP; output [5:0] S_AXI_HP3_BID; output [5:0] S_AXI_HP3_RID; output [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_RDATA; output [7:0] S_AXI_HP3_RCOUNT; output [7:0] S_AXI_HP3_WCOUNT; output [2:0] S_AXI_HP3_RACOUNT; output [5:0] S_AXI_HP3_WACOUNT; input S_AXI_HP3_ACLK; input S_AXI_HP3_ARVALID; input S_AXI_HP3_AWVALID; input S_AXI_HP3_BREADY; input S_AXI_HP3_RDISSUECAP1_EN; input S_AXI_HP3_RREADY; input S_AXI_HP3_WLAST; input S_AXI_HP3_WRISSUECAP1_EN; input S_AXI_HP3_WVALID; input [1:0] S_AXI_HP3_ARBURST; input [1:0] S_AXI_HP3_ARLOCK; input [2:0] S_AXI_HP3_ARSIZE; input [1:0] S_AXI_HP3_AWBURST; input [1:0] S_AXI_HP3_AWLOCK; input [2:0] S_AXI_HP3_AWSIZE; input [2:0] S_AXI_HP3_ARPROT; input [2:0] S_AXI_HP3_AWPROT; input [31:0] S_AXI_HP3_ARADDR; input [31:0] S_AXI_HP3_AWADDR; input [3:0] S_AXI_HP3_ARCACHE; input [3:0] S_AXI_HP3_ARLEN; input [3:0] S_AXI_HP3_ARQOS; input [3:0] S_AXI_HP3_AWCACHE; input [3:0] S_AXI_HP3_AWLEN; input [3:0] S_AXI_HP3_AWQOS; input [5:0] S_AXI_HP3_ARID; input [5:0] S_AXI_HP3_AWID; input [5:0] S_AXI_HP3_WID; input [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_WDATA; input [C_S_AXI_HP3_DATA_WIDTH/8-1:0] S_AXI_HP3_WSTRB; output [1:0] DMA0_DATYPE; output DMA0_DAVALID; output DMA0_DRREADY; input DMA0_ACLK; input DMA0_DAREADY; input DMA0_DRLAST; input DMA0_DRVALID; input [1:0] DMA0_DRTYPE; output [1:0] DMA1_DATYPE; output DMA1_DAVALID; output DMA1_DRREADY; input DMA1_ACLK; input DMA1_DAREADY; input DMA1_DRLAST; input DMA1_DRVALID; input [1:0] DMA1_DRTYPE; output [1:0] DMA2_DATYPE; output DMA2_DAVALID; output DMA2_DRREADY; input DMA2_ACLK; input DMA2_DAREADY; input DMA2_DRLAST; input DMA2_DRVALID; input DMA3_DRVALID; output [1:0] DMA3_DATYPE; output DMA3_DAVALID; output DMA3_DRREADY; input DMA3_ACLK; input DMA3_DAREADY; input DMA3_DRLAST; input [1:0] DMA2_DRTYPE; input [1:0] DMA3_DRTYPE; input [31:0] FTMD_TRACEIN_DATA; input FTMD_TRACEIN_VALID; input FTMD_TRACEIN_CLK; input [3:0] FTMD_TRACEIN_ATID; input [3:0] FTMT_F2P_TRIG; output [3:0] FTMT_F2P_TRIGACK; input [31:0] FTMT_F2P_DEBUG; input [3:0] FTMT_P2F_TRIGACK; output [3:0] FTMT_P2F_TRIG; output [31:0] FTMT_P2F_DEBUG; output FCLK_CLK3; output FCLK_CLK2; output FCLK_CLK1; output FCLK_CLK0; input FCLK_CLKTRIG3_N; input FCLK_CLKTRIG2_N; input FCLK_CLKTRIG1_N; input FCLK_CLKTRIG0_N; output FCLK_RESET3_N; output FCLK_RESET2_N; output FCLK_RESET1_N; output FCLK_RESET0_N; input FPGA_IDLE_N; input [3:0] DDR_ARB; input [irq_width-1:0] IRQ_F2P; input Core0_nFIQ; input Core0_nIRQ; input Core1_nFIQ; input Core1_nIRQ; output EVENT_EVENTO; output [1:0] EVENT_STANDBYWFE; output [1:0] EVENT_STANDBYWFI; input EVENT_EVENTI; inout [53:0] MIO; inout DDR_Clk; inout DDR_Clk_n; inout DDR_CKE; inout DDR_CS_n; inout DDR_RAS_n; inout DDR_CAS_n; output DDR_WEB; inout [2:0] DDR_BankAddr; inout [14:0] DDR_Addr; inout DDR_ODT; inout DDR_DRSTB; inout [31:0] DDR_DQ; inout [3:0] DDR_DM; inout [3:0] DDR_DQS; inout [3:0] DDR_DQS_n; inout DDR_VRN; inout DDR_VRP; /* Reset Input & Clock Input */ input PS_SRSTB; input PS_CLK; input PS_PORB; output IRQ_P2F_DMAC_ABORT; output IRQ_P2F_DMAC0; output IRQ_P2F_DMAC1; output IRQ_P2F_DMAC2; output IRQ_P2F_DMAC3; output IRQ_P2F_DMAC4; output IRQ_P2F_DMAC5; output IRQ_P2F_DMAC6; output IRQ_P2F_DMAC7; output IRQ_P2F_SMC; output IRQ_P2F_QSPI; output IRQ_P2F_CTI; output IRQ_P2F_GPIO; output IRQ_P2F_USB0; output IRQ_P2F_ENET0; output IRQ_P2F_ENET_WAKE0; output IRQ_P2F_SDIO0; output IRQ_P2F_I2C0; output IRQ_P2F_SPI0; output IRQ_P2F_UART0; output IRQ_P2F_CAN0; output IRQ_P2F_USB1; output IRQ_P2F_ENET1; output IRQ_P2F_ENET_WAKE1; output IRQ_P2F_SDIO1; output IRQ_P2F_I2C1; output IRQ_P2F_SPI1; output IRQ_P2F_UART1; output IRQ_P2F_CAN1; /* Internal wires/nets used for connectivity */ wire net_rstn; wire net_sw_clk; wire net_ocm_clk; wire net_arbiter_clk; wire net_axi_mgp0_rstn; wire net_axi_mgp1_rstn; wire net_axi_gp0_rstn; wire net_axi_gp1_rstn; wire net_axi_hp0_rstn; wire net_axi_hp1_rstn; wire net_axi_hp2_rstn; wire net_axi_hp3_rstn; wire net_axi_acp_rstn; wire [4:0] net_axi_acp_awuser; wire [4:0] net_axi_acp_aruser; /* Dummy */ assign net_axi_acp_awuser = S_AXI_ACP_AWUSER; assign net_axi_acp_aruser = S_AXI_ACP_ARUSER; /* Global variables */ reg DEBUG_INFO = 1; reg STOP_ON_ERROR = 1; /* local variable acting as semaphore for wait_mem_update and wait_reg_update task */ reg mem_update_key = 1; reg reg_update_key_0 = 1; reg reg_update_key_1 = 1; /* assignments and semantic checks for unused ports */ `include "processing_system7_bfm_v2_0_unused_ports.v" /* include api definition */ `include "processing_system7_bfm_v2_0_apis.v" /* Reset Generator */ processing_system7_bfm_v2_0_gen_reset gen_rst(.por_rst_n(PS_PORB), .sys_rst_n(PS_SRSTB), .rst_out_n(net_rstn), .m_axi_gp0_clk(M_AXI_GP0_ACLK), .m_axi_gp1_clk(M_AXI_GP1_ACLK), .s_axi_gp0_clk(S_AXI_GP0_ACLK), .s_axi_gp1_clk(S_AXI_GP1_ACLK), .s_axi_hp0_clk(S_AXI_HP0_ACLK), .s_axi_hp1_clk(S_AXI_HP1_ACLK), .s_axi_hp2_clk(S_AXI_HP2_ACLK), .s_axi_hp3_clk(S_AXI_HP3_ACLK), .s_axi_acp_clk(S_AXI_ACP_ACLK), .m_axi_gp0_rstn(net_axi_mgp0_rstn), .m_axi_gp1_rstn(net_axi_mgp1_rstn), .s_axi_gp0_rstn(net_axi_gp0_rstn), .s_axi_gp1_rstn(net_axi_gp1_rstn), .s_axi_hp0_rstn(net_axi_hp0_rstn), .s_axi_hp1_rstn(net_axi_hp1_rstn), .s_axi_hp2_rstn(net_axi_hp2_rstn), .s_axi_hp3_rstn(net_axi_hp3_rstn), .s_axi_acp_rstn(net_axi_acp_rstn), .fclk_reset3_n(FCLK_RESET3_N), .fclk_reset2_n(FCLK_RESET2_N), .fclk_reset1_n(FCLK_RESET1_N), .fclk_reset0_n(FCLK_RESET0_N), .fpga_acp_reset_n(), ////S_AXI_ACP_ARESETN), (These are removed from Zynq IP) .fpga_gp_m0_reset_n(), ////M_AXI_GP0_ARESETN), .fpga_gp_m1_reset_n(), ////M_AXI_GP1_ARESETN), .fpga_gp_s0_reset_n(), ////S_AXI_GP0_ARESETN), .fpga_gp_s1_reset_n(), ////S_AXI_GP1_ARESETN), .fpga_hp_s0_reset_n(), ////S_AXI_HP0_ARESETN), .fpga_hp_s1_reset_n(), ////S_AXI_HP1_ARESETN), .fpga_hp_s2_reset_n(), ////S_AXI_HP2_ARESETN), .fpga_hp_s3_reset_n() ////S_AXI_HP3_ARESETN) ); /* Clock Generator */ processing_system7_bfm_v2_0_gen_clock #(C_FCLK_CLK3_FREQ, C_FCLK_CLK2_FREQ, C_FCLK_CLK1_FREQ, C_FCLK_CLK0_FREQ) gen_clk(.ps_clk(PS_CLK), .sw_clk(net_sw_clk), .fclk_clk3(FCLK_CLK3), .fclk_clk2(FCLK_CLK2), .fclk_clk1(FCLK_CLK1), .fclk_clk0(FCLK_CLK0) ); wire net_wr_ack_ocm_gp0, net_wr_ack_ddr_gp0, net_wr_ack_ocm_gp1, net_wr_ack_ddr_gp1; wire net_wr_dv_ocm_gp0, net_wr_dv_ddr_gp0, net_wr_dv_ocm_gp1, net_wr_dv_ddr_gp1; wire [max_burst_bits-1:0] net_wr_data_gp0, net_wr_data_gp1; wire [addr_width-1:0] net_wr_addr_gp0, net_wr_addr_gp1; wire [max_burst_bytes_width:0] net_wr_bytes_gp0, net_wr_bytes_gp1; wire [axi_qos_width-1:0] net_wr_qos_gp0, net_wr_qos_gp1; wire net_rd_req_ddr_gp0, net_rd_req_ddr_gp1; wire net_rd_req_ocm_gp0, net_rd_req_ocm_gp1; wire net_rd_req_reg_gp0, net_rd_req_reg_gp1; wire [addr_width-1:0] net_rd_addr_gp0, net_rd_addr_gp1; wire [max_burst_bytes_width:0] net_rd_bytes_gp0, net_rd_bytes_gp1; wire [max_burst_bits-1:0] net_rd_data_ddr_gp0, net_rd_data_ddr_gp1; wire [max_burst_bits-1:0] net_rd_data_ocm_gp0, net_rd_data_ocm_gp1; wire [max_burst_bits-1:0] net_rd_data_reg_gp0, net_rd_data_reg_gp1; wire net_rd_dv_ddr_gp0, net_rd_dv_ddr_gp1; wire net_rd_dv_ocm_gp0, net_rd_dv_ocm_gp1; wire net_rd_dv_reg_gp0, net_rd_dv_reg_gp1; wire [axi_qos_width-1:0] net_rd_qos_gp0, net_rd_qos_gp1; wire net_wr_ack_ddr_hp0, net_wr_ack_ddr_hp1, net_wr_ack_ddr_hp2, net_wr_ack_ddr_hp3; wire net_wr_ack_ocm_hp0, net_wr_ack_ocm_hp1, net_wr_ack_ocm_hp2, net_wr_ack_ocm_hp3; wire net_wr_dv_ddr_hp0, net_wr_dv_ddr_hp1, net_wr_dv_ddr_hp2, net_wr_dv_ddr_hp3; wire net_wr_dv_ocm_hp0, net_wr_dv_ocm_hp1, net_wr_dv_ocm_hp2, net_wr_dv_ocm_hp3; wire [max_burst_bits-1:0] net_wr_data_hp0, net_wr_data_hp1, net_wr_data_hp2, net_wr_data_hp3; wire [addr_width-1:0] net_wr_addr_hp0, net_wr_addr_hp1, net_wr_addr_hp2, net_wr_addr_hp3; wire [max_burst_bytes_width:0] net_wr_bytes_hp0, net_wr_bytes_hp1, net_wr_bytes_hp2, net_wr_bytes_hp3; wire [axi_qos_width-1:0] net_wr_qos_hp0, net_wr_qos_hp1, net_wr_qos_hp2, net_wr_qos_hp3; wire net_rd_req_ddr_hp0, net_rd_req_ddr_hp1, net_rd_req_ddr_hp2, net_rd_req_ddr_hp3; wire net_rd_req_ocm_hp0, net_rd_req_ocm_hp1, net_rd_req_ocm_hp2, net_rd_req_ocm_hp3; wire [addr_width-1:0] net_rd_addr_hp0, net_rd_addr_hp1, net_rd_addr_hp2, net_rd_addr_hp3; wire [max_burst_bytes_width:0] net_rd_bytes_hp0, net_rd_bytes_hp1, net_rd_bytes_hp2, net_rd_bytes_hp3; wire [max_burst_bits-1:0] net_rd_data_ddr_hp0, net_rd_data_ddr_hp1, net_rd_data_ddr_hp2, net_rd_data_ddr_hp3; wire [max_burst_bits-1:0] net_rd_data_ocm_hp0, net_rd_data_ocm_hp1, net_rd_data_ocm_hp2, net_rd_data_ocm_hp3; wire net_rd_dv_ddr_hp0, net_rd_dv_ddr_hp1, net_rd_dv_ddr_hp2, net_rd_dv_ddr_hp3; wire net_rd_dv_ocm_hp0, net_rd_dv_ocm_hp1, net_rd_dv_ocm_hp2, net_rd_dv_ocm_hp3; wire [axi_qos_width-1:0] net_rd_qos_hp0, net_rd_qos_hp1, net_rd_qos_hp2, net_rd_qos_hp3; wire net_wr_ack_ddr_acp,net_wr_ack_ocm_acp; wire net_wr_dv_ddr_acp,net_wr_dv_ocm_acp; wire [max_burst_bits-1:0] net_wr_data_acp; wire [addr_width-1:0] net_wr_addr_acp; wire [max_burst_bytes_width:0] net_wr_bytes_acp; wire [axi_qos_width-1:0] net_wr_qos_acp; wire net_rd_req_ddr_acp, net_rd_req_ocm_acp; wire [addr_width-1:0] net_rd_addr_acp; wire [max_burst_bytes_width:0] net_rd_bytes_acp; wire [max_burst_bits-1:0] net_rd_data_ddr_acp; wire [max_burst_bits-1:0] net_rd_data_ocm_acp; wire net_rd_dv_ddr_acp,net_rd_dv_ocm_acp; wire [axi_qos_width-1:0] net_rd_qos_acp; wire ocm_wr_ack_port0; wire ocm_wr_dv_port0; wire ocm_rd_req_port0; wire ocm_rd_dv_port0; wire [addr_width-1:0] ocm_wr_addr_port0; wire [max_burst_bits-1:0] ocm_wr_data_port0; wire [max_burst_bytes_width:0] ocm_wr_bytes_port0; wire [addr_width-1:0] ocm_rd_addr_port0; wire [max_burst_bits-1:0] ocm_rd_data_port0; wire [max_burst_bytes_width:0] ocm_rd_bytes_port0; wire [axi_qos_width-1:0] ocm_wr_qos_port0; wire [axi_qos_width-1:0] ocm_rd_qos_port0; wire ocm_wr_ack_port1; wire ocm_wr_dv_port1; wire ocm_rd_req_port1; wire ocm_rd_dv_port1; wire [addr_width-1:0] ocm_wr_addr_port1; wire [max_burst_bits-1:0] ocm_wr_data_port1; wire [max_burst_bytes_width:0] ocm_wr_bytes_port1; wire [addr_width-1:0] ocm_rd_addr_port1; wire [max_burst_bits-1:0] ocm_rd_data_port1; wire [max_burst_bytes_width:0] ocm_rd_bytes_port1; wire [axi_qos_width-1:0] ocm_wr_qos_port1; wire [axi_qos_width-1:0] ocm_rd_qos_port1; wire ddr_wr_ack_port0; wire ddr_wr_dv_port0; wire ddr_rd_req_port0; wire ddr_rd_dv_port0; wire[addr_width-1:0] ddr_wr_addr_port0; wire[max_burst_bits-1:0] ddr_wr_data_port0; wire[max_burst_bytes_width:0] ddr_wr_bytes_port0; wire[addr_width-1:0] ddr_rd_addr_port0; wire[max_burst_bits-1:0] ddr_rd_data_port0; wire[max_burst_bytes_width:0] ddr_rd_bytes_port0; wire [axi_qos_width-1:0] ddr_wr_qos_port0; wire [axi_qos_width-1:0] ddr_rd_qos_port0; wire ddr_wr_ack_port1; wire ddr_wr_dv_port1; wire ddr_rd_req_port1; wire ddr_rd_dv_port1; wire[addr_width-1:0] ddr_wr_addr_port1; wire[max_burst_bits-1:0] ddr_wr_data_port1; wire[max_burst_bytes_width:0] ddr_wr_bytes_port1; wire[addr_width-1:0] ddr_rd_addr_port1; wire[max_burst_bits-1:0] ddr_rd_data_port1; wire[max_burst_bytes_width:0] ddr_rd_bytes_port1; wire[axi_qos_width-1:0] ddr_wr_qos_port1; wire[axi_qos_width-1:0] ddr_rd_qos_port1; wire ddr_wr_ack_port2; wire ddr_wr_dv_port2; wire ddr_rd_req_port2; wire ddr_rd_dv_port2; wire[addr_width-1:0] ddr_wr_addr_port2; wire[max_burst_bits-1:0] ddr_wr_data_port2; wire[max_burst_bytes_width:0] ddr_wr_bytes_port2; wire[addr_width-1:0] ddr_rd_addr_port2; wire[max_burst_bits-1:0] ddr_rd_data_port2; wire[max_burst_bytes_width:0] ddr_rd_bytes_port2; wire[axi_qos_width-1:0] ddr_wr_qos_port2; wire[axi_qos_width-1:0] ddr_rd_qos_port2; wire ddr_wr_ack_port3; wire ddr_wr_dv_port3; wire ddr_rd_req_port3; wire ddr_rd_dv_port3; wire[addr_width-1:0] ddr_wr_addr_port3; wire[max_burst_bits-1:0] ddr_wr_data_port3; wire[max_burst_bytes_width:0] ddr_wr_bytes_port3; wire[addr_width-1:0] ddr_rd_addr_port3; wire[max_burst_bits-1:0] ddr_rd_data_port3; wire[max_burst_bytes_width:0] ddr_rd_bytes_port3; wire[axi_qos_width-1:0] ddr_wr_qos_port3; wire[axi_qos_width-1:0] ddr_rd_qos_port3; wire reg_rd_req_port0; wire reg_rd_dv_port0; wire[addr_width-1:0] reg_rd_addr_port0; wire[max_burst_bits-1:0] reg_rd_data_port0; wire[max_burst_bytes_width:0] reg_rd_bytes_port0; wire [axi_qos_width-1:0] reg_rd_qos_port0; wire reg_rd_req_port1; wire reg_rd_dv_port1; wire[addr_width-1:0] reg_rd_addr_port1; wire[max_burst_bits-1:0] reg_rd_data_port1; wire[max_burst_bytes_width:0] reg_rd_bytes_port1; wire [axi_qos_width-1:0] reg_rd_qos_port1; wire [11:0] M_AXI_GP0_AWID_FULL; wire [11:0] M_AXI_GP0_WID_FULL; wire [11:0] M_AXI_GP0_ARID_FULL; wire [11:0] M_AXI_GP0_BID_FULL; wire [11:0] M_AXI_GP0_RID_FULL; wire [11:0] M_AXI_GP1_AWID_FULL; wire [11:0] M_AXI_GP1_WID_FULL; wire [11:0] M_AXI_GP1_ARID_FULL; wire [11:0] M_AXI_GP1_BID_FULL; wire [11:0] M_AXI_GP1_RID_FULL; function [5:0] compress_id; \tinput [11:0] id; \t\tbegin \t\t\tcompress_id = id[5:0]; \t\tend endfunction function [11:0] uncompress_id; \tinput [5:0] id; \t\tbegin \t\t uncompress_id = {6\'b110000, id[5:0]}; \t\tend endfunction assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL; assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL; assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL; assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID; assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID; assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL; assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL; assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL; assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID; assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID; processing_system7_bfm_v2_0_interconnect_model icm ( .rstn(net_rstn), .sw_clk(net_sw_clk), .w_qos_gp0(net_wr_qos_gp0), .w_qos_gp1(net_wr_qos_gp1), .w_qos_hp0(net_wr_qos_hp0), .w_qos_hp1(net_wr_qos_hp1), .w_qos_hp2(net_wr_qos_hp2), .w_qos_hp3(net_wr_qos_hp3), .r_qos_gp0(net_rd_qos_gp0), .r_qos_gp1(net_rd_qos_gp1), .r_qos_hp0(net_rd_qos_hp0), .r_qos_hp1(net_rd_qos_hp1), .r_qos_hp2(net_rd_qos_hp2), .r_qos_hp3(net_rd_qos_hp3), /* GP Slave ports access */ .wr_ack_ddr_gp0(net_wr_ack_ddr_gp0), .wr_ack_ocm_gp0(net_wr_ack_ocm_gp0), .wr_data_gp0(net_wr_data_gp0), .wr_addr_gp0(net_wr_addr_gp0), .wr_bytes_gp0(net_wr_bytes_gp0), .wr_dv_ddr_gp0(net_wr_dv_ddr_gp0), .wr_dv_ocm_gp0(net_wr_dv_ocm_gp0), .rd_req_ddr_gp0(net_rd_req_ddr_gp0), .rd_req_ocm_gp0(net_rd_req_ocm_gp0), .rd_req_reg_gp0(net_rd_req_reg_gp0), .rd_addr_gp0(net_rd_addr_gp0), .rd_bytes_gp0(net_rd_bytes_gp0), .rd_data_ddr_gp0(net_rd_data_ddr_gp0), .rd_data_ocm_gp0(net_rd_data_ocm_gp0), .rd_data_reg_gp0(net_rd_data_reg_gp0), .rd_dv_ddr_gp0(net_rd_dv_ddr_gp0), .rd_dv_ocm_gp0(net_rd_dv_ocm_gp0), .rd_dv_reg_gp0(net_rd_dv_reg_gp0), .wr_ack_ddr_gp1(net_wr_ack_ddr_gp1), .wr_ack_ocm_gp1(net_wr_ack_ocm_gp1), .wr_data_gp1(net_wr_data_gp1), .wr_addr_gp1(net_wr_addr_gp1), .wr_bytes_gp1(net_wr_bytes_gp1), .wr_dv_ddr_gp1(net_wr_dv_ddr_gp1), .wr_dv_ocm_gp1(net_wr_dv_ocm_gp1), .rd_req_ddr_gp1(net_rd_req_ddr_gp1), .rd_req_ocm_gp1(net_rd_req_ocm_gp1), .rd_req_reg_gp1(net_rd_req_reg_gp1), .rd_addr_gp1(net_rd_addr_gp1), .rd_bytes_gp1(net_rd_bytes_gp1), .rd_data_ddr_gp1(net_rd_data_ddr_gp1), .rd_data_ocm_gp1(net_rd_data_ocm_gp1), .rd_data_reg_gp1(net_rd_data_reg_gp1), .rd_dv_ddr_gp1(net_rd_dv_ddr_gp1), .rd_dv_ocm_gp1(net_rd_dv_ocm_gp1), .rd_dv_reg_gp1(net_rd_dv_reg_gp1), /* HP Slave ports access */ .wr_ack_ddr_hp0(net_wr_ack_ddr_hp0), .wr_ack_ocm_hp0(net_wr_ack_ocm_hp0), .wr_data_hp0(net_wr_data_hp0), .wr_addr_hp0(net_wr_addr_hp0), .wr_bytes_hp0(net_wr_bytes_hp0), .wr_dv_ddr_hp0(net_wr_dv_ddr_hp0), .wr_dv_ocm_hp0(net_wr_dv_ocm_hp0), .rd_req_ddr_hp0(net_rd_req_ddr_hp0), .rd_req_ocm_hp0(net_rd_req_ocm_hp0), .rd_addr_hp0(net_rd_addr_hp0), .rd_bytes_hp0(net_rd_bytes_hp0), .rd_data_ddr_hp0(net_rd_data_ddr_hp0), .rd_data_ocm_hp0(net_rd_data_ocm_hp0), .rd_dv_ddr_hp0(net_rd_dv_ddr_hp0), .rd_dv_ocm_hp0(net_rd_dv_ocm_hp0), .wr_ack_ddr_hp1(net_wr_ack_ddr_hp1), .wr_ack_ocm_hp1(net_wr_ack_ocm_hp1), .wr_data_hp1(net_wr_data_hp1), .wr_addr_hp1(net_wr_addr_hp1), .wr_bytes_hp1(net_wr_bytes_hp1), .wr_dv_ddr_hp1(net_wr_dv_ddr_hp1), .wr_dv_ocm_hp1(net_wr_dv_ocm_hp1), .rd_req_ddr_hp1(net_rd_req_ddr_hp1), .rd_req_ocm_hp1(net_rd_req_ocm_hp1), .rd_addr_hp1(net_rd_addr_hp1), .rd_bytes_hp1(net_rd_bytes_hp1), .rd_data_ddr_hp1(net_rd_data_ddr_hp1), .rd_data_ocm_hp1(net_rd_data_ocm_hp1), .rd_dv_ocm_hp1(net_rd_dv_ocm_hp1), .rd_dv_ddr_hp1(net_rd_dv_ddr_hp1), .wr_ack_ddr_hp2(net_wr_ack_ddr_hp2), .wr_ack_ocm_hp2(net_wr_ack_ocm_hp2), .wr_data_hp2(net_wr_data_hp2), .wr_addr_hp2(net_wr_addr_hp2), .wr_bytes_hp2(net_wr_bytes_hp2), .wr_dv_ocm_hp2(net_wr_dv_ocm_hp2), .wr_dv_ddr_hp2(net_wr_dv_ddr_hp2), .rd_req_ddr_hp2(net_rd_req_ddr_hp2), .rd_req_ocm_hp2(net_rd_req_ocm_hp2), .rd_addr_hp2(net_rd_addr_hp2), .rd_bytes_hp2(net_rd_bytes_hp2), .rd_data_ddr_hp2(net_rd_data_ddr_hp2), .rd_data_ocm_hp2(net_rd_data_ocm_hp2), .rd_dv_ddr_hp2(net_rd_dv_ddr_hp2), .rd_dv_ocm_hp2(net_rd_dv_ocm_hp2), .wr_ack_ocm_hp3(net_wr_ack_ocm_hp3), .wr_ack_ddr_hp3(net_wr_ack_ddr_hp3), .wr_data_hp3(net_wr_data_hp3), .wr_addr_hp3(net_wr_addr_hp3), .wr_bytes_hp3(net_wr_bytes_hp3), .wr_dv_ddr_hp3(net_wr_dv_ddr_hp3), .wr_dv_ocm_hp3(net_wr_dv_ocm_hp3), .rd_req_ddr_hp3(net_rd_req_ddr_hp3), .rd_req_ocm_hp3(net_rd_req_ocm_hp3), .rd_addr_hp3(net_rd_addr_hp3), .rd_bytes_hp3(net_rd_bytes_hp3), .rd_data_ddr_hp3(net_rd_data_ddr_hp3), .rd_data_ocm_hp3(net_rd_data_ocm_hp3), .rd_dv_ddr_hp3(net_rd_dv_ddr_hp3), .rd_dv_ocm_hp3(net_rd_dv_ocm_hp3), /* Goes to port 1 of DDR */ .ddr_wr_ack_port1(ddr_wr_ack_port1), .ddr_wr_dv_port1(ddr_wr_dv_port1), .ddr_rd_req_port1(ddr_rd_req_port1), .ddr_rd_dv_port1 (ddr_rd_dv_port1), .ddr_wr_addr_port1(ddr_wr_addr_port1), .ddr_wr_data_port1(ddr_wr_data_port1), .ddr_wr_bytes_port1(ddr_wr_bytes_port1), .ddr_rd_addr_port1(ddr_rd_addr_port1), .ddr_rd_data_port1(ddr_rd_data_port1), .ddr_rd_bytes_port1(ddr_rd_bytes_port1), .ddr_wr_qos_port1(ddr_wr_qos_port1), .ddr_rd_qos_port1(ddr_rd_qos_port1), /* Goes to port2 of DDR */ .ddr_wr_ack_port2 (ddr_wr_ack_port2), .ddr_wr_dv_port2 (ddr_wr_dv_port2), .ddr_rd_req_port2 (ddr_rd_req_port2), .ddr_rd_dv_port2 (ddr_rd_dv_port2), .ddr_wr_addr_port2(ddr_wr_addr_port2), .ddr_wr_data_port2(ddr_wr_data_port2), .ddr_wr_bytes_port2(ddr_wr_bytes_port2), .ddr_rd_addr_port2(ddr_rd_addr_port2), .ddr_rd_data_port2(ddr_rd_data_port2), .ddr_rd_bytes_port2(ddr_rd_bytes_port2), .ddr_wr_qos_port2 (ddr_wr_qos_port2), .ddr_rd_qos_port2 (ddr_rd_qos_port2), /* Goes to port3 of DDR */ .ddr_wr_ack_port3 (ddr_wr_ack_port3), .ddr_wr_dv_port3 (ddr_wr_dv_port3), .ddr_rd_req_port3 (ddr_rd_req_port3), .ddr_rd_dv_port3 (ddr_rd_dv_port3), .ddr_wr_addr_port3(ddr_wr_addr_port3), .ddr_wr_data_port3(ddr_wr_data_port3), .ddr_wr_bytes_port3(ddr_wr_bytes_port3), .ddr_rd_addr_port3(ddr_rd_addr_port3), .ddr_rd_data_port3(ddr_rd_data_port3), .ddr_rd_bytes_port3(ddr_rd_bytes_port3), .ddr_wr_qos_port3 (ddr_wr_qos_port3), .ddr_rd_qos_port3 (ddr_rd_qos_port3), /* Goes to port 0 of OCM */ .ocm_wr_ack_port1 (ocm_wr_ack_port1), .ocm_wr_dv_port1 (ocm_wr_dv_port1), .ocm_rd_req_port1 (ocm_rd_req_port1), .ocm_rd_dv_port1 (ocm_rd_dv_port1), .ocm_wr_addr_port1(ocm_wr_addr_port1), .ocm_wr_data_port1(ocm_wr_data_port1), .ocm_wr_bytes_port1(ocm_wr_bytes_port1), .ocm_rd_addr_port1(ocm_rd_addr_port1), .ocm_rd_data_port1(ocm_rd_data_port1), .ocm_rd_bytes_port1(ocm_rd_bytes_port1), .ocm_wr_qos_port1(ocm_wr_qos_port1), .ocm_rd_qos_port1(ocm_rd_qos_port1), /* Goes to port 0 of REG */ .reg_rd_qos_port1 (reg_rd_qos_port1) , .reg_rd_req_port1 (reg_rd_req_port1), .reg_rd_dv_port1 (reg_rd_dv_port1), .reg_rd_addr_port1(reg_rd_addr_port1), .reg_rd_data_port1(reg_rd_data_port1), .reg_rd_'b'bytes_port1(reg_rd_bytes_port1) ); processing_system7_bfm_v2_0_ddrc ddrc ( .rstn(net_rstn), .sw_clk(net_sw_clk), /* Goes to port 0 of DDR */ .ddr_wr_ack_port0 (ddr_wr_ack_port0), .ddr_wr_dv_port0 (ddr_wr_dv_port0), .ddr_rd_req_port0 (ddr_rd_req_port0), .ddr_rd_dv_port0 (ddr_rd_dv_port0), .ddr_wr_addr_port0(net_wr_addr_acp), .ddr_wr_data_port0(net_wr_data_acp), .ddr_wr_bytes_port0(net_wr_bytes_acp), .ddr_rd_addr_port0(net_rd_addr_acp), .ddr_rd_bytes_port0(net_rd_bytes_acp), .ddr_rd_data_port0(ddr_rd_data_port0), .ddr_wr_qos_port0 (net_wr_qos_acp), .ddr_rd_qos_port0 (net_rd_qos_acp), /* Goes to port 1 of DDR */ .ddr_wr_ack_port1 (ddr_wr_ack_port1), .ddr_wr_dv_port1 (ddr_wr_dv_port1), .ddr_rd_req_port1 (ddr_rd_req_port1), .ddr_rd_dv_port1 (ddr_rd_dv_port1), .ddr_wr_addr_port1(ddr_wr_addr_port1), .ddr_wr_data_port1(ddr_wr_data_port1), .ddr_wr_bytes_port1(ddr_wr_bytes_port1), .ddr_rd_addr_port1(ddr_rd_addr_port1), .ddr_rd_data_port1(ddr_rd_data_port1), .ddr_rd_bytes_port1(ddr_rd_bytes_port1), .ddr_wr_qos_port1 (ddr_wr_qos_port1), .ddr_rd_qos_port1 (ddr_rd_qos_port1), /* Goes to port2 of DDR */ .ddr_wr_ack_port2 (ddr_wr_ack_port2), .ddr_wr_dv_port2 (ddr_wr_dv_port2), .ddr_rd_req_port2 (ddr_rd_req_port2), .ddr_rd_dv_port2 (ddr_rd_dv_port2), .ddr_wr_addr_port2(ddr_wr_addr_port2), .ddr_wr_data_port2(ddr_wr_data_port2), .ddr_wr_bytes_port2(ddr_wr_bytes_port2), .ddr_rd_addr_port2(ddr_rd_addr_port2), .ddr_rd_data_port2(ddr_rd_data_port2), .ddr_rd_bytes_port2(ddr_rd_bytes_port2), .ddr_wr_qos_port2 (ddr_wr_qos_port2), .ddr_rd_qos_port2 (ddr_rd_qos_port2), /* Goes to port3 of DDR */ .ddr_wr_ack_port3 (ddr_wr_ack_port3), .ddr_wr_dv_port3 (ddr_wr_dv_port3), .ddr_rd_req_port3 (ddr_rd_req_port3), .ddr_rd_dv_port3 (ddr_rd_dv_port3), .ddr_wr_addr_port3(ddr_wr_addr_port3), .ddr_wr_data_port3(ddr_wr_data_port3), .ddr_wr_bytes_port3(ddr_wr_bytes_port3), .ddr_rd_addr_port3(ddr_rd_addr_port3), .ddr_rd_data_port3(ddr_rd_data_port3), .ddr_rd_bytes_port3(ddr_rd_bytes_port3), .ddr_wr_qos_port3 (ddr_wr_qos_port3), .ddr_rd_qos_port3 (ddr_rd_qos_port3) ); processing_system7_bfm_v2_0_ocmc ocmc ( .rstn(net_rstn), .sw_clk(net_sw_clk), /* Goes to port 0 of OCM */ .ocm_wr_ack_port0 (ocm_wr_ack_port0), .ocm_wr_dv_port0 (ocm_wr_dv_port0), .ocm_rd_req_port0 (ocm_rd_req_port0), .ocm_rd_dv_port0 (ocm_rd_dv_port0), .ocm_wr_addr_port0(net_wr_addr_acp), .ocm_wr_data_port0(net_wr_data_acp), .ocm_wr_bytes_port0(net_wr_bytes_acp), .ocm_rd_addr_port0(net_rd_addr_acp), .ocm_rd_bytes_port0(net_rd_bytes_acp), .ocm_rd_data_port0(ocm_rd_data_port0), .ocm_wr_qos_port0 (net_wr_qos_acp), .ocm_rd_qos_port0 (net_rd_qos_acp), /* Goes to port 1 of OCM */ .ocm_wr_ack_port1 (ocm_wr_ack_port1), .ocm_wr_dv_port1 (ocm_wr_dv_port1), .ocm_rd_req_port1 (ocm_rd_req_port1), .ocm_rd_dv_port1 (ocm_rd_dv_port1), .ocm_wr_addr_port1(ocm_wr_addr_port1), .ocm_wr_data_port1(ocm_wr_data_port1), .ocm_wr_bytes_port1(ocm_wr_bytes_port1), .ocm_rd_addr_port1(ocm_rd_addr_port1), .ocm_rd_data_port1(ocm_rd_data_port1), .ocm_rd_bytes_port1(ocm_rd_bytes_port1), .ocm_wr_qos_port1(ocm_wr_qos_port1), .ocm_rd_qos_port1(ocm_rd_qos_port1) ); processing_system7_bfm_v2_0_regc regc ( .rstn(net_rstn), .sw_clk(net_sw_clk), /* Goes to port 0 of REG */ .reg_rd_req_port0 (reg_rd_req_port0), .reg_rd_dv_port0 (reg_rd_dv_port0), .reg_rd_addr_port0(net_rd_addr_acp), .reg_rd_bytes_port0(net_rd_bytes_acp), .reg_rd_data_port0(reg_rd_data_port0), .reg_rd_qos_port0 (net_rd_qos_acp), /* Goes to port 1 of REG */ .reg_rd_req_port1 (reg_rd_req_port1), .reg_rd_dv_port1 (reg_rd_dv_port1), .reg_rd_addr_port1(reg_rd_addr_port1), .reg_rd_data_port1(reg_rd_data_port1), .reg_rd_bytes_port1(reg_rd_bytes_port1), .reg_rd_qos_port1(reg_rd_qos_port1) ); /* include axi_gp port instantiations */ `include "processing_system7_bfm_v2_0_axi_gp.v" /* include axi_hp port instantiations */ `include "processing_system7_bfm_v2_0_axi_hp.v" /* include axi_acp port instantiations */ `include "processing_system7_bfm_v2_0_axi_acp.v" endmodule
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // // DO NOT MODIFY THIS FILE. // IP VLNV: xilinx.com:ip:processing_system7:5.5 // IP Revision: 0 (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2014.4" *) (* CHECK_LICENSE_TYPE = "base_zynq_design_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) (* CORE_GENERATION_INFO = "base_zynq_design_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=0,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TRANS_CHECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=1,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=true,C_FCLK_CLK1_BUF=true,C_FCLK_CLK2_BUF=true,C_FCLK_CLK3_BUF=false,C_PACKAGE_NAME=clg484}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) module base_zynq_design_processing_system7_0_0 ( ENET0_PTP_DELAY_REQ_RX, ENET0_PTP_DELAY_REQ_TX, ENET0_PTP_PDELAY_REQ_RX, ENET0_PTP_PDELAY_REQ_TX, ENET0_PTP_PDELAY_RESP_RX, ENET0_PTP_PDELAY_RESP_TX, ENET0_PTP_SYNC_FRAME_RX, ENET0_PTP_SYNC_FRAME_TX, ENET0_SOF_RX, ENET0_SOF_TX, I2C1_SDA_I, I2C1_SDA_O, I2C1_SDA_T, I2C1_SCL_I, I2C1_SCL_O, I2C1_SCL_T, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST, M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR, M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS, M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK, M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST, M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP, M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, IRQ_F2P, DMA0_DATYPE, DMA0_DAVALID, DMA0_DRREADY, DMA2_DATYPE, DMA2_DAVALID, DMA2_DRREADY, DMA0_ACLK, DMA0_DAREADY, DMA0_DRLAST, DMA0_DRVALID, DMA2_ACLK, DMA2_DAREADY, DMA2_DRLAST, DMA2_DRVALID, DMA0_DRTYPE, DMA2_DRTYPE, FCLK_CLK0, FCLK_CLK1, FCLK_CLK2, FCLK_RESET0_N, FCLK_RESET1_N, FCLK_RESET2_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB ); (* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 DELAY_REQ_RX" *) output wire ENET0_PTP_DELAY_REQ_RX; (* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 DELAY_REQ_TX" *) output wire ENET0_PTP_DELAY_REQ_TX; (* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_REQ_RX" *) output wire ENET0_PTP_PDELAY_REQ_RX; (* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_REQ_TX" *) output wire ENET0_PTP_PDELAY_REQ_TX; (* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_RESP_RX" *) output wire ENET0_PTP_PDELAY_RESP_RX; (* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_RESP_TX" *) output wire ENET0_PTP_PDELAY_RESP_TX; (* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SYNC_FRAME_RX" *) output wire ENET0_PTP_SYNC_FRAME_RX; (* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SYNC_FRAME_TX" *) output wire ENET0_PTP_SYNC_FRAME_TX; (* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SOF_RX" *) output wire ENET0_SOF_RX; (* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SOF_TX" *) output wire ENET0_SOF_TX; (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_1 SDA_I" *) input wire I2C1_SDA_I; (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_1 SDA_O" *) output wire I2C1_SDA_O; (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_1 SDA_T" *) output wire I2C1_SDA_T; (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_1 SCL_I" *) input wire I2C1_SCL_I; (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_1 SCL_O" *) output wire I2C1_SCL_O; (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_1 SCL_T" *) output wire I2C1_SCL_T; output wire TTC0_WAVE0_OUT; output wire TTC0_WAVE1_OUT; output wire TTC0_WAVE2_OUT; (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *) output wire [1 : 0] USB0_PORT_INDCTL; (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) output wire USB0_VBUS_PWRSELECT; (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) input wire USB0_VBUS_PWRFAULT; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) output wire M_AXI_GP0_ARVALID; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) output wire M_AXI_GP0_AWVALID; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) output wire M_AXI_GP0_BREADY; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) output wire M_AXI_GP0_RREADY; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) output wire M_AXI_GP0_WLAST; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) output wire M_AXI_GP0_WVALID; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) output wire [11 : 0] M_AXI_GP0_ARID; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) output wire [11 : 0] M_AXI_GP0_AWID; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) output wire [11 : 0] M_AXI_GP0_WID; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) output wire [1 : 0] M_AXI_GP0_ARBURST; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) output wire [1 : 0] M_AXI_GP0_ARLOCK; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) output wire [2 : 0] M_AXI_GP0_ARSIZE; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) output wire [1 : 0] M_AXI_GP0_AWBURST; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) output wire [1 : 0] M_AXI_GP0_AWLOCK; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) output wire [2 : 0] M_AXI_GP0_AWSIZE; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) output wire [2 : 0] M_AXI_GP0_ARPROT; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) output wire [2 : 0] M_AXI_GP0_AWPROT; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) output wire [31 : 0] M_AXI_GP0_ARADDR; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) output wire [31 : 0] M_AXI_GP0_AWADDR; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) output wire [31 : 0] M_AXI_GP0_WDATA; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) output wire [3 : 0] M_AXI_GP0_ARCACHE; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) output wire [3 : 0] M_AXI_GP0_ARLEN; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) output wire [3 : 0] M_AXI_GP0_ARQOS; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) output wire [3 : 0] M_AXI_GP0_AWCACHE; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output wire [3 : 0] M_AXI_GP0_AWLEN; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output wire [3 : 0] M_AXI_GP0_AWQOS; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output wire [3 : 0] M_AXI_GP0_WSTRB; (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) input wire M_AXI_GP0_ACLK; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input wire M_AXI_GP0_ARREADY; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input wire M_AXI_GP0_AWREADY; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input wire M_AXI_GP0_BVALID; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) input wire M_AXI_GP0_RLAST; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) input wire M_AXI_GP0_RVALID; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) input wire M_AXI_GP0_WREADY; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) input wire [11 : 0] M_AXI_GP0_BID; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input wire [11 : 0] M_AXI_GP0_RID; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input wire [1 : 0] M_AXI_GP0_BRESP; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input wire [1 : 0] M_AXI_GP0_RRESP; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) input wire [31 : 0] M_AXI_GP0_RDATA; (* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *) input wire [0 : 0] IRQ_F2P; (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 DMA0_ACK TUSER" *) output wire [1 : 0] DMA0_DATYPE; (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 DMA0_ACK TVALID" *) output wire DMA0_DAVALID; (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 DMA0_REQ TREADY" *) output wire DMA0_DRREADY; (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 DMA2_ACK TUSER" *) output wire [1 : 0] DMA2_DATYPE; (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 DMA2_ACK TVALID" *) output wire DMA2_DAVALID; (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 DMA2_REQ TREADY" *) output wire DMA2_DRREADY; (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 DMA0_ACLK CLK" *) input wire DMA0_ACLK; (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 DMA0_ACK TREADY" *) input wire DMA0_DAREADY; (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 DMA0_REQ TLAST" *) input wire DMA0_DRLAST; (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 DMA0_REQ TVALID" *) input wire DMA0_DRVALID; (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 DMA2_ACLK CLK" *) input wire DMA2_ACLK; (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 DMA2_ACK TREADY" *) input wire DMA2_DAREADY; (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 DMA2_REQ TLAST" *) input wire DMA2_DRLAST; (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 DMA2_REQ TVALID" *) input wire DMA2_DRVALID; (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 DMA0_REQ TUSER" *) input wire [1 : 0] DMA0_DRTYPE; (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 DMA2_REQ TUSER" *) input wire [1 : 0] DMA2_DRTYPE; (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) output wire FCLK_CLK0; (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK1 CLK" *) output wire FCLK_CLK1; (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK2 CLK" *) output wire FCLK_CLK2; (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) output wire FCLK_RESET0_N; (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET1_N RST" *) output wire FCLK_RESET1_N; (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET2_N RST" *) output wire FCLK_RESET2_N; (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout wire [53 : 0] MIO; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout wire DDR_CAS_n; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout wire DDR_CKE; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout wire DDR_Clk_n; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout wire DDR_Clk; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout wire DDR_CS_n; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout wire DDR_DRSTB; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout wire DDR_ODT; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout wire DDR_RAS_n; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout wire DDR_WEB; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout wire [2 : 0] DDR_BankAddr; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout wire [14 : 0] DDR_Addr; (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout wire DDR_VRN; (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout wire DDR_VRP; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout wire [3 : 0] DDR_DM; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout wire [31 : 0] DDR_DQ; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout wire [3 : 0] DDR_DQS_n; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) inout wire [3 : 0] DDR_DQS; (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout wire PS_SRSTB; (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout wire PS_CLK; (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) inout wire PS_PORB; processing_system7_v5_5_processing_system7 #( .C_EN_EMIO_PJTAG(0), .C_EN_EMIO_ENET0(0), .C_EN_EMIO_ENET1(0), .C_EN_EMIO_TRACE(0), .C_INCLUDE_TRACE_BUFFER(0), .C_TRACE_BUFFER_FIFO_SIZE(128), .USE_TRACE_DATA_EDGE_DETECTOR(0), .C_TRACE_PIPELINE_WIDTH(8), .C_TRACE_BUFFER_CLOCK_DELAY(12), .C_EMIO_GPIO_WIDTH(64), .C_INCLUDE_ACP_TRANS_CHECK(0), .C_USE_DEFAULT_ACP_USER_VAL(0), .C_S_AXI_ACP_ARUSER_VAL(31), .C_S_AXI_ACP_AWUSER_VAL(31), .C_M_AXI_GP0_ID_WIDTH(12), .C_M_AXI_GP0_ENABLE_STATIC_REMAP(0), .C_M_AXI_GP1_ID_WIDTH(12), .C_M_AXI_GP1_ENABLE_STATIC_REMAP(0), .C_S_AXI_GP0_ID_WIDTH(6), .C_S_AXI_GP1_ID_WIDTH(6), .C_S_AXI_ACP_ID_WIDTH(3), .C_S_AXI_HP0_ID_WIDTH(6), .C_S_AXI_HP0_DATA_WIDTH(64), .C_S_AXI_HP1_ID_WIDTH(6), .C_S_AXI_HP1_DATA_WIDTH(64), .C_S_AXI_HP2_ID_WIDTH(6), .C_S_AXI_HP2_DATA_WIDTH(64), .C_S_AXI_HP3_ID_WIDTH(6), .C_S_AXI_HP3_DATA_WIDTH(64), .C_M_AXI_GP0_THREAD_ID_WIDTH(12), .C_M_AXI_GP1_THREAD_ID_WIDTH(12), .C_NUM_F2P_INTR_INPUTS(1), .C_IRQ_F2P_MODE("DIRECT"), .C_DQ_WIDTH(32), .C_DQS_WIDTH(4), .C_DM_WIDTH(4), .C_MIO_PRIMITIVE(54), .C_TRACE_INTERNAL_WIDTH(2), .C_PS7_SI_REV("PRODUCTION"), .C_FCLK_CLK0_BUF("true"), .C_FCLK_CLK1_BUF("true"), .C_FCLK_CLK2_BUF("true"), .C_FCLK_CLK3_BUF("false"), .C_PACKAGE_NAME("clg484") ) inst ( .CAN0_PHY_TX(), .CAN0_PHY_RX(1\'B0), .CAN1_PHY_TX(), .CAN1_PHY_RX(1\'B0), .ENET0_GMII_TX_EN(), .ENET0_GMII_TX_ER(), .ENET0_MDIO_MDC(), .ENET0_MDIO_O(), .ENET0_MDIO_T(), .ENET0_PTP_DELAY_REQ_RX(ENET0_PTP_DELAY_REQ_RX), .ENET0_PTP_DELAY_REQ_TX(ENET0_PTP_DELAY_REQ_TX), .ENET0_PTP_PDELAY_REQ_RX(ENET0_PTP_PDELAY_REQ_RX), .ENET0_PTP_PDELAY_REQ_TX(ENET0_PTP_PDELAY_REQ_TX), .ENET0_PTP_PDELAY_RESP_RX(ENET0_PTP_PDELAY_RESP_RX), .ENET0_PTP_PDELAY_RESP_TX(ENET0_PTP_PDELAY_RESP_TX), .ENET0_PTP_SYNC_FRAME_RX(ENET0_PTP_SYNC_FRAME_RX), .ENET0_PTP_SYNC_FRAME_TX(ENET0_PTP_SYNC_FRAME_TX), .ENET0_SOF_RX(ENET0_SOF_RX), .ENET0_SOF_TX(ENET0_SOF_TX), .ENET0_GMII_TXD(), .ENET0_GMII_COL(1\'B0), .ENET0_GMII_CRS(1\'B0), .ENET0_GMII_RX_CLK(1\'B0), .ENET0_GMII_RX_DV(1\'B0), .ENET0_GMII_RX_ER(1\'B0), .ENET0_GMII_TX_CLK(1\'B0), .ENET0_MDIO_I(1\'B0), .ENET0_EXT_INTIN(1\'B0), .ENET0_GMII_RXD(8\'B0), .ENET1_GMII_TX_EN(), .ENET1_GMII_TX_ER(), .ENET1_MDIO_MDC(), .ENET1_MDIO_O(), .ENET1_MDIO_T(), .ENET1_PTP_DELAY_REQ_RX(), .ENET1_PTP_DELAY_REQ_TX(), .ENET1_PTP_PDELAY_REQ_RX(), .ENET1_PTP_PDELAY_REQ_TX(), .ENET1_PTP_PDELAY_RESP_RX(), .ENET1_PTP_PDELAY_RESP_TX(), .ENET1_PTP_SYNC_FRAME_RX(), .ENET1_PTP_SYNC_FRAME_TX(), .ENET1_SOF_RX(), .ENET1_SOF_TX(), .ENET1_GMII_TXD(), .ENET1_GMII_COL(1\'B0), .ENET1_GMII_CRS(1\'B0), .ENET1_GMII_RX_CLK(1\'B0), .ENET1_GMII_RX_DV(1\'B0), .ENET1_GMII_RX_ER(1\'B0), .ENET1_GMII_TX_CLK(1\'B0), .ENET1_MDIO_I(1\'B0), .ENET1_EXT_INTIN(1\'B0), .ENET1_GMII_RXD(8\'B0), .GPIO_I(64\'B0), .GPIO_O(), .GPIO_T(), .I2C0_SDA_I(1\'B0), .I2C0_SDA_O(), .I2C0_SDA_T(), .I2C0_SCL_I(1\'B0), .I2C0_SCL_O(), .I2C0_SCL_T(), .I2C1_SDA_I(I2C1_SDA_I), .I2C1_SDA_O(I2C1_SDA_O), .I2C1_SDA_T(I2C1_SDA_T), .I2C1_SCL_I(I2C1_SCL_I), .I2C1_SCL_O(I2C1_SCL_O), .I2C1_SCL_T(I2C1_SCL_T), .PJTAG_TCK(1\'B0), .PJTAG_TMS(1\'B0), .PJTAG_TDI(1\'B0), .PJTAG_TDO(), .SDIO0_CLK(), .SDIO0_CLK_FB(1\'B0), .SDIO0_CMD_O(), .SDIO0_CMD_I(1\'B0), .SDIO0_CMD_T(), .SDIO0_DATA_I(4\'B0), .SDIO0_DATA_O(), .SDIO0_DATA_T(), .SDIO0_LED(), .SDIO0_CDN(1\'B0), .SDIO0_WP(1\'B0), .SDIO0_BUSPOW(), .SDIO0_BUSVOLT(), .SDIO1_CLK(), .SDIO1_CLK_FB(1\'B0), .SDIO1_CMD_O(), .SDIO1_CMD_I(1\'B0), .SDIO1_CMD_T(), .SDIO1_DATA_I(4\'B0), .SDIO1_DATA_O(), .SDIO1_DATA_T(), .SDIO1_LED(), .SDIO1_CDN(1\'B0), .SDIO1_WP(1\'B0), .SDIO1_BUSPOW(), .SDIO1_BUSVOLT(), .SPI0_SCLK_I(1\'B0), .SPI0_SCLK_O(), .SPI0_SCLK_T(), .SPI0_MOSI_I(1\'B0), .SPI0_MOSI_O(), .SPI0_MOSI_T(), .SPI0_MISO_I(1\'B0), .SPI0_MISO_O(), .SPI0_MISO_T(), .SPI0_SS_I(1\'B0), .SPI0_SS_O(), .SPI0_SS1_O(), .SPI0_SS2_O(), .SPI0_SS_T(), .SPI1_SCLK_I(1\'B0), .SPI1_SCLK_O(), .SPI1_SCLK_T(), .SPI1_MOSI_I(1\'B0), .SPI1_MOSI_O(), .SPI1_MOSI_T(), .SPI1_MISO_I(1\'B0), .SPI1_MISO_O(), .SPI1_MISO_T(), .SPI1_SS_I(1\'B0), .SPI1_SS_O(), .SPI1_SS1_O(), .SPI1_SS2_O(), .SPI1_SS_T(), .UART0_DTRN(), .UART0_RTSN(), .UART0_TX(), .UART0_CTSN(1\'B0), .UART0_DCDN(1\'B0), .UART0_DSRN(1\'B0), .UART0_RIN(1\'B0), .UART0_RX(1\'B1), .UART1_DTRN(), .UART1_RTSN(), .UART1_TX(), .UART1_CTSN(1\'B0), .UART1_DCDN(1\'B0), .UART1_DSRN(1\'B0), .UART1_RIN(1\'B0), .UART1_RX(1\'B1), .TTC0_WAVE0_OUT(TTC0_WAVE0_OUT), .TTC0_WAVE1_OUT(TTC0_WAVE1_OUT), .TTC0_WAVE2_OUT(TTC0_WAVE2_OUT), .TTC0_CLK0_IN(1\'B0), .TTC0_CLK1_IN(1\'B0), .TTC0_CLK2_IN(1\'B0), .TTC1_WAVE0_OUT(), .TTC1_WAVE1_OUT(), .TTC1_WAVE2_OUT(), .TTC1_CLK0_IN(1\'B0), .TTC1_CLK1_IN(1\'B0), .TTC1_CLK2_IN(1\'B0), .WDT_CLK_IN(1\'B0), .WDT_RST_OUT(), .TRACE_CLK(1\'B0), .TRACE_CLK_OUT(), .TRACE_CTL(), .TRACE_DATA(), .USB0_PORT_INDCTL(USB0_PORT_INDCTL), .USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT), .USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT), .USB1_PORT_INDCTL(), .USB1_VBUS_PWRSELECT(), .USB1_VBUS_PWRFAULT(1\'B0), .SRAM_INTIN(1\'B0), .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID), .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID), .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY), .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY), .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST), .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID), .M_AXI_GP0_ARID(M_AXI_GP0_ARID), .M_AXI_GP0_AWID(M_AXI_GP0_AWID), .M_AXI_GP0_WID(M_AXI_GP0_WID), .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST), .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK), .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE), .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST), .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK), .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE), .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT), .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT), .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR), .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR), .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA), .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE), .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN), .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS), .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE), .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN), .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS), .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB), .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK), .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY), .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY), .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID), .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST), .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID), .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY), .M_AXI_GP0_BID(M_AXI_GP0_BID), .M_AXI_GP0_RID(M_AXI_GP0_RID), .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP), .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP), .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA), .M_AXI_GP1_ARVALID(), .M_AXI_GP1_AWVALID(), .M_AXI_GP1_BREADY(), .M_AXI_GP1_RREADY(), .M_AXI_GP1_WLAST(), .M_AXI_GP1_WVALID(), .M_AXI_GP1_ARID(), .M_AXI_GP1_AWID(), .M_AXI_GP1_WID(), .M_AXI_GP1_ARBURST(), .M_AXI_GP1_ARLOCK(), .M_AXI_GP1_ARSIZE(), .M_AXI_GP1_AWBURST(), .M_AXI_GP1_AWLOCK(), .M_AXI_GP1_AWSIZE(), .M_AXI_GP1_ARPROT(), .M_AXI_GP1_AWPROT(), .M_AXI_GP1_ARADDR(), .M_AXI_GP1_AWADDR(), .M_AXI_GP1_WDATA(), .M_AXI_GP1_ARCACHE(), .M_AXI_GP1_ARLEN(), .M_AXI_GP1_ARQOS(), .M_AXI_GP1_AWCACHE(), .M_AXI_GP1_AWLEN(), .M_AXI_GP1_AWQOS(), .M_AXI_GP1_WSTRB(), .M_AXI_GP1_ACLK(1\'B0), .M_AXI_GP1_ARREADY(1\'B0), .M_AXI_GP1_AWREADY(1\'B0), .M_AXI_GP1_BVALID(1\'B0), .M_AXI_GP1_RLAST(1\'B0), .M_AXI_GP1_RVALID(1\'B0), .M_AXI_GP1_WREADY(1\'B0), .M_AXI_GP1_BID(12\'B0), .M_AXI_GP1_RID(12\'B0), .M_AXI_GP1_BRESP(2\'B0), .M_AXI_GP1_RRESP(2\'B0), .M_AXI_GP1_RDATA(32\'B0), .S_AXI_GP0_ARREADY(), .S_AXI_GP0_AWREADY(), .S_AXI_GP0_BVALID(), .S_AXI_GP0_RLAST(), .S_AXI_GP0_RVALID(), .S_AXI_GP0_WREADY(), .S_AXI_GP0_BRESP(), .S_AXI_GP0_RRESP(), .S_AXI_GP0_RDATA(), .S_AXI_GP0_BID(), .S_AXI_GP0_RID(), .S_AXI_GP0_ACLK(1\'B0), .S_AXI_GP0_ARVALID(1\'B0), .S_AXI_GP0_AWVALID(1\'B0), .S_AXI_GP0_BREADY(1\'B0), .S_AXI_GP0_RREADY(1\'B0), .S_AXI_GP0_WLAST(1\'B0), .S_AXI_GP0_WVALID(1\'B0), .S_AXI_GP0_ARBURST(2\'B0), .S_AXI_GP0_ARLOCK(2\'B0), .S_AXI_GP0_ARSIZE(3\'B0), .S_AXI_GP0_AWBURST(2\'B0), .S_AXI_GP0_AWLOCK(2\'B0), .S_AXI_GP0_AWSIZE(3\'B0), .S_AXI_GP0_ARPROT(3\'B0), .S_AXI_GP0_AWPROT(3\'B0), .S_AXI_GP0_ARADDR(32\'B0), .S_AXI_GP0_AWADDR(32\'B0), .S_AXI_GP0_WDATA(32\'B0), .S_AXI_GP0_ARCACHE(4\'B0), .S_AXI_GP0_ARLEN(4\'B0), .S_AXI_GP0_ARQOS(4\'B0), .S_AXI_GP0_AWCACHE(4\'B0), .S_AXI_GP0_AWLEN(4\'B0), .S_AXI_GP0_AWQOS(4\'B0), .S_AXI_GP0_WSTRB(4\'B0), .S_AXI_GP0_ARID(6\'B0), .S_AXI_GP0_AWID(6\'B0), .S_AXI_GP0_WID(6\'B0), .S_AXI_GP1_ARREADY(), .S_AXI_GP1_AWREADY(), .S_AXI_GP1_BVALID(), .S_AXI_GP1_RLAST(), .S_AXI_GP1_RVALID(), .S_AXI_GP1_WREADY(), .S_AXI_GP1_BRESP(), .S_AXI_GP1_RRESP(), .S_AXI_GP1_RDATA(), .S_AXI_GP1_BID(), .S_AXI_GP1_RID(), .S_AXI_GP1_ACLK(1\'B0), .S_AXI_GP1_ARVALID(1\'B0), .S_AXI_GP1_AWVALID(1\'B0), .S_AXI_GP1_BREADY(1\'B0), .S_AXI_GP1_RREADY(1\'B0), .S_AXI_GP1_WLAST(1\'B0), .S_AXI_GP1_WVALID(1\'B0), .S_AXI_GP1_ARBURST(2\'B0), .S_AXI_GP1_ARLOCK(2\'B0), .S_AXI_GP1_ARSIZE(3\'B0), .S_AXI_GP1_AWBURST(2\'B0), .S_AXI_GP1_AWLOCK(2\'B0), .S_AXI_GP1_AWSIZE(3\'B0), .S_AXI_GP1_ARPROT(3\'B0), .S_AXI_GP1_AWPROT(3\'B0), .S_AXI_GP1_ARADDR(32\'B0), .S_AXI_GP1_AWADDR(32\'B0), .S_AXI_GP1_WDATA(32\'B0), .S_AXI_GP1_ARCACHE(4\'B0), .S_AXI_GP1_ARLEN(4\'B0), .S_AXI_GP1_ARQOS(4\'B0), .S_AXI_GP1_AWCACHE(4\'B0), .S_AXI_GP1_AWLEN(4\'B0), .S_AXI_GP1_AWQOS(4\'B0), .S_AXI_GP1_WSTRB(4\'B0), .S_AXI_GP1_ARID(6\'B0), .S_AXI_GP1_AWID(6\'B0), .S_AXI_GP1_WID(6\'B0), .S_AXI_ACP_ARREADY(), .S_AXI_ACP_AWREADY(), .S_AXI_ACP_BVALID(), .S_AXI_ACP_RLAST(), .S_AXI_ACP_RVALID(), .S_AXI_ACP_WREADY(), .S_AXI_ACP_BRESP(), .S_AXI_ACP_RRESP(), .S_AXI_ACP_BID(), .S_AXI_ACP_RID(), .S_AXI_ACP_RDATA(), .S_AXI_ACP_ACLK(1\'B0), .S_AXI_ACP_ARVALID(1\'B0), .S_AXI_ACP_AWVALID(1\'B0), .S_AXI_ACP_BREADY(1\'B0), .S_AXI_ACP_RREADY(1\'B0), .S_AXI_ACP_WLAST(1\'B0), .S_AXI_ACP_WVALID(1\'B0), .S_AXI_ACP_ARID(3\'B0), .S_AXI_ACP_ARPROT(3\'B0), .S_AXI_ACP_AWID(3\'B0), .S_AXI_ACP_AWPROT(3\'B0), .S_AXI_ACP_WID(3\'B0), .S_AXI_ACP_ARADDR(32\'B0), .S_AXI_ACP_AWADDR(32\'B0), .S_AXI_ACP_ARCACHE(4\'B0), .S_AXI_ACP_ARLEN(4\'B0), .S_AXI_ACP_ARQOS(4\'B0), .S_AXI_ACP_AWCACHE(4\'B0), .S_AXI_ACP_AWLEN(4\'B0), .S_AXI_ACP_AWQOS(4\'B0), .S_AXI_ACP_ARBURST(2\'B0), .S_AXI_ACP_ARLOCK(2\'B0), .S_AXI_ACP_ARSIZE(3\'B0), .S_AXI_ACP_AWBURST(2\'B0), .S_AXI_ACP_AWLOCK(2\'B0), .S_AXI_ACP_AWSIZE(3\'B0), .S_AXI_ACP_ARUSER(5\'B0), .S_AXI_ACP_AWUSER(5\'B0), .S_AXI_ACP_WDATA(64\'B0), .S_AXI_ACP_WSTRB(8\'B0), .S_AXI_HP0_ARREADY(), .S_AXI_HP0_AWREADY(), .S_AXI_HP0_BVALID(), .S_AXI_HP0_RLAST(), .S_AXI_HP0_RVALID(), .S_AXI_HP0_WREADY(), .S_AXI_HP0_BRESP(), .S_AXI_HP0_RRESP(), .S_AXI_HP0_BID(), .S_AXI_HP0_RID(), .S_AXI_HP0_RDATA(), .S_AXI_HP0_RCOUNT(), .S_AXI_HP0_WCOUNT(), .S_AXI_HP0_RACOUNT(), .S_AXI_HP0_WACOUNT(), .S_AXI_HP0_ACLK(1\'B0), .S_AXI_HP0_ARVALID(1\'B0), .S_AXI_HP0_AWVALID(1\'B0), .S_AXI_HP0_BREADY(1\'B0), .S_AXI_HP0_RDISSUECAP1_EN(1\'B0), .S_AXI_HP0_RREADY(1\'B0), .S_AXI_HP0_WLAST(1\'B0), .S_AXI_HP0_WRISSUECAP1_EN(1\'B0), .S_AXI_HP0_WVALID(1\'B0), .S_AXI_HP0_ARBURST(2\'B0), .S_AXI_HP0_ARLOCK(2\'B0), .S_AXI_HP0_ARSIZE(3\'B0), .S_AXI_HP0_AWBURST(2\'B0), .S_AXI_HP0_AWLOCK(2\'B0), .S_AXI_HP0_AWSIZE(3\'B0), .S_AXI_HP0_ARPROT(3\'B0), .S_AXI_HP0_AWPROT(3\'B0), .S_AXI_HP0_ARADDR(32\'B0), .S_AXI_HP0_AWADDR(32\'B0), .S_AXI_HP0_ARCACHE(4\'B0), .S_AXI_HP0_ARLEN(4\'B0), .S_AXI_HP0_ARQOS(4\'B0), .S_AXI_HP0_AWCACHE(4\'B0), .S_AXI_HP0_AWLEN(4\'B0), .S_AXI_HP0_AWQOS(4\'B0), .S_AXI_HP0_ARID(6\'B0), .S_AXI_HP0_AWID(6\'B0), .S_AXI_HP0_WID(6\'B0), .S_AXI_HP0_WDATA(64\'B0), .S_AXI_HP0_WSTRB(8\'B0), .S_AXI_HP1_ARREADY(), .S_AXI_HP1_AWREADY(), .S_AXI_HP1_BVALID(), .S_AXI_HP1_RLAST(), .S_AXI_HP1_RVALID(), .S_AXI_HP1_WREADY(), .S_AXI_HP1_BRESP(), .S_AXI_HP1_RRESP(), .S_AXI_HP1_BID(), .S_AXI_HP1_RID(), .S_AXI_HP1_RDATA(), .S_AXI_HP1_RCOUNT(), .S_AXI_HP1_WCOUNT(), .S_AXI_HP1_RACOUNT(), .S_AXI_HP1_WACOUNT(), .S_AXI_HP1_ACLK(1\'B0), .S_AXI_HP1_ARVALID(1\'B0), .S_AXI_HP1_AWVALID(1\'B0), .S_AXI_HP1_BREADY(1\'B0), .S_AXI_HP1_RDISSUECAP1_EN(1\'B0), .S_AXI_HP1_RREADY(1\'B0), .S_AXI_HP1_WLAST(1\'B0), .S_AXI_HP1_WRISSUECAP1_EN(1\'B0), .S_AXI_HP1_WVALID(1\'B0), .S_AXI_HP1_ARBURST(2\'B0), .S_AXI_HP1_ARLOCK(2\'B0), .S_AXI_HP1_ARSIZE(3\'B0), .S_AXI_HP1_AWBURST(2\'B0), .S_AXI_HP1_AWLOCK(2\'B0), .S_AXI_HP1_AWSIZE(3\'B0), .S_AXI_HP1_ARPROT(3\'B0), .S_AXI_HP1_AWPROT(3\'B0), .S_AXI_HP1_ARADDR(32\'B0), .S_AXI_HP1_AWADDR(32\'B0), .S_AXI_HP1_ARCACHE(4\'B0), .S_AXI_HP1_ARLEN(4\'B0), .S_AXI_HP1_ARQOS(4\'B0), .S_AXI_HP1_AWCACHE(4\'B0), .S_AXI_HP1_AWLEN(4\'B0), .S_AXI_HP1_AWQOS(4\'B0), .S_AXI_HP1_ARID(6\'B0), .S_AXI_HP1_AWID(6\'B0), .S_AXI_HP1_WID(6\'B0), .S_AXI_HP1_WDATA(64\'B0), .S_AXI_HP1_WSTRB(8\'B0), .S_AXI_HP2_ARREADY(), .S_AXI_HP2_AWREADY(), .S_AXI_HP2_BVALID(), .S_AXI_HP2_RLAST(), .S_AXI_HP2_RVALID(), .S_AXI_HP2_WREADY(), .S_AXI_HP2_BRESP(), .S_AXI_HP2_RRESP(), .S_AXI_HP2_BID(), .S_AXI_HP2_RID(), .S_AXI_HP2_RDATA(), .S_AXI_HP2_RCOUNT(), .S_AXI_HP2_WCOUNT(), .S_AXI_HP2_RACOUNT(), .S_AXI_HP2_WACOUNT(), .S_AXI_HP2_ACLK(1\'B0), .S_AXI_HP2_ARVALID(1\'B0), .S_AXI_HP2_AWVALID(1\'B0), .S_AXI_HP2_BREADY(1\'B0), .S_AXI_HP2_RDISSUECAP1_EN(1\'B0), .S_AXI_HP2_RREADY(1\'B0), .S_AXI_HP2_WLAST(1\'B0), .S_AXI_HP2_WRISSUECAP1_EN(1\'B0), .S_AXI_HP2_WVALID(1\'B0), .S_AXI_HP2_ARBURST(2\'B0), .S_AXI_HP2_ARLOCK(2\'B0), .S_AXI_HP2_ARSIZE(3\'B0), .S_AXI_HP2_AWBURST(2\'B0), .S_AXI_HP2_AWLOCK(2\'B0), .S_AXI_HP2_AWSIZE(3\'B0), .S_AXI_HP2_ARPROT(3\'B0), .S_AXI_HP2_AWPROT(3\'B0), .S_AXI_HP2_ARADDR(32\'B0), .S_AXI_HP2_AWADDR(32\'B0), .S_AXI_HP2_ARCACHE(4\'B0), .S_AXI_HP2_ARLEN(4\'B0), .S_AXI_HP2_ARQOS(4\'B0), .S_AXI_HP2_AWCACHE(4\'B0), .S_AXI_HP2_AWLEN(4\'B0), .S_AXI_HP2_AWQOS(4\'B0), .S_AXI_HP2_ARID(6\'B0), .S_AXI_HP2_AWID(6\'B0), .S_AXI_HP2_WID(6\'B0), .S_AXI_HP2_WDATA(64\'B0), .S_AXI_HP2_WSTRB(8\'B0), .S_AXI_HP3_ARREADY(), .S_AXI_HP3_AWREADY(), .S_AXI_HP3_BVALID(), .S_AXI_HP3_RLAST(), .S_AXI_HP3_RVALID(), .S_AXI_HP3_WREADY(), .S_AXI_HP3_BRESP(), .S_AXI_HP3_RRESP(), .S_AXI_HP3_BID(), .S_AXI_HP3_RID(), .S_AXI_HP3_RDATA(), .S_AXI_HP3_RCOUNT(), .S_AXI_HP3_WCOUNT(), .S_AXI_HP3_RACOUNT(), .S_AXI_HP3_WACOUNT(), .S_AXI_HP3_ACLK(1\'B0), .S_AXI_HP3_ARVALID(1\'B0), .S_AXI_HP3_AWVALID(1\'B0), .S_AXI_HP3_BREADY(1\'B0), .S_AXI_HP3_RDISSUECAP1_EN(1\'B0), .S_AXI_HP3_RREADY(1\'B0), .S_AXI_HP3_WLAST(1\'B0), .S_AXI_HP3_WRISSUECAP1_EN(1\'B0), .S_AXI_HP3_WVALID(1\'B0), .S_AXI_HP3_ARBURST(2\'B0), .S_AXI_HP3_ARLOCK(2\'B0), .S_AXI_HP3_ARSIZE(3\'B0), .S_AXI_HP3_AWBURST(2\'B0), .S_AXI_HP3_AWLOCK(2\'B0), .S_AXI_HP3_AWSIZE(3\'B0), .S_AXI_HP3_ARPROT(3\'B0), .S_AXI_HP3_AWPROT(3\'B0), .S_AXI_HP3_ARADDR(32\'B0), .S_AXI_HP3_AWADDR(32\'B0), .S_AXI_HP3_ARCACHE(4\'B0), .S_AXI_HP3_ARLEN(4\'B0), .S_AXI_HP3_ARQOS(4\'B0), .S_AXI_HP3_AWCACHE(4\'B0), .S_AXI_HP3_AWLEN(4\'B0), .S_AXI_HP3_AWQOS(4\'B0), .S_AXI_HP3_ARID(6\'B0), .S_AXI_HP3_AWID(6\'B0), .S_AXI_HP3_WID(6\'B0), .S_AXI_HP3_WDATA(64\'B0), .S_AXI_HP3_WSTRB(8\'B0), .IRQ_P2F_DMAC_ABORT(), .IRQ_P2F_DMAC0(), .IRQ_P2F_DMAC1(), .IRQ_P2F_DMAC2(), .IRQ_P2F_DMAC3(), .IRQ_P2F_DMAC4(), .IRQ_P2F_DMAC5(), .IRQ_P2F_DMAC6(), .IRQ_P2F_DMAC7(), .IRQ_P2F_SMC(), .IRQ_P2F_QSPI(), .IRQ_P2F_CTI(), .IRQ_P2F_GPIO(), .IRQ_P2F_USB0(), .IRQ_P2F_ENET0(), .IRQ_P2F_ENET_WAKE0(), .IRQ_P2F_SDIO0(), .IRQ_P2F_I2C0(), .IRQ_P2F_SPI0(), .IRQ_P2F_UART0(), .IRQ_P2F_CAN0(), .IRQ_P2F_USB1(), .IRQ_P2F_ENET1(), .IRQ_P2F_ENET_WAKE1(), .IRQ_P2F_SDIO1(), .IRQ_P2F_I2C1(), .IRQ_P2F_SPI1(), .IRQ_P2F_UART1(), .IRQ_P2F_CAN1(), .IRQ_F2P(IRQ_F2P), .Core0_nFIQ(1\'B0), .Core0_nIRQ(1\'B0), .Core1_nFIQ(1\'B0), .Core1_nIRQ(1\'B0), .DMA0_DATYPE(DMA0_DATYPE), .DMA0_DAVALID(DMA0_DAVALID), .DMA0_DRREADY(DMA0_DRREADY), .DMA1_DATYPE(), .DMA1_DAVALID(), .DMA1_DRREADY(), .DMA2_DATYPE(DMA2_DATYPE), .DMA2_DAVALID(DMA2_DAVALID), .DMA2_DRREADY(DMA2_DRREADY), .DMA3_DATYPE(), .DMA3_DAVALID(), .DMA3_DRREADY(), .DMA0_ACLK(DMA0_ACLK), .DMA0_DAREADY(DMA0_DAREADY), .DMA0_DRLAST(DMA0_DRLAST), .DMA0_DRVALID(DMA0_DRVALID), .DMA1_ACLK(1\'B0), .DMA1_DAREADY(1\'B0), .DMA1_DRLAST(1\'B0), .DMA1_DRVALID(1\'B0), .DMA2_ACLK(DMA2_ACLK), .DMA2_DAREADY(DMA2_DAREADY), .DMA2_DRLAST(DMA2_DRLAST), .DMA2_DRVALID(DMA2_DRVALID), .DMA3_ACLK(1\'B0), .DMA3_DAREADY(1\'B0), .DMA3_DRLAST(1\'B0), .DMA3_DRVALID(1\'B0), .DMA0_DRTYPE(DMA0_DRTYPE), .DMA1_DRTYPE(2\'B0), .DMA2_DRTYPE(DMA2_DRTYPE), .DMA3_DRTYPE(2\'B0), .FCLK_CLK0(FCLK_CLK0), .FCLK_CLK1(FCLK_CLK1), .FCLK_CLK2(FCLK_CLK2), .FCLK_CLK3(), .FCLK_CLKTRIG0_N(1\'B0), .FCLK_CLKTRIG1_N(1\'B0), .FCLK_CLKTRIG2_N(1\'B0), .FCLK_CLKTRIG3_N(1\'B0), .FCLK_RESET0_N(FCLK_RESET0_N), .FCLK_RESET1_N(FCLK_RESET1_N), .FCLK_RESET2_N(FCLK_RESET2_N), .FCLK_RESET3_N(), .FTMD_TRACEIN_DATA(32\'B0), .FTMD_TRACEIN_VALID(1\'B0), .FTMD_TRACEIN_CLK(1\'B0), .FTMD_TRACEIN_ATID(4\'B0), .FTMT_F2P_TRIG_0(1\'B0), .FTMT_F2P_TRIGACK_0(), .FTMT_F2P_TRIG_1(1\'B0), .FTMT_F2P_TRIGACK_1(), .FTMT_F2P_TRIG_2(1\'B0), .FTMT_F2P_TRIGACK_2(), .FTMT_F2P_TRIG_3(1\'B0), .FTMT_F2P_TRIGACK_3(), .FTMT_F2P_DEBUG(32\'B0), .FTMT_P2F_TRIGACK_0(1\'B0), .FTMT_P2F_TRIG_0(), .FTMT_P2F_TRIGACK_1(1\'B0), .FTMT_P2F_TRIG_1(), .FTMT_P2F_TRIGACK_2(1\'B0), .FTMT_P2F_TRIG_2(), .FTMT_P2F_TRIGACK_3(1\'B0), .FTMT_P2F_TRIG_3(), .FTMT_P2F_DEBUG(), .FPGA_IDLE_N(1\'B0), .EVENT_EVENTO(), .EVENT_STANDBYWFE(), .EVENT_STANDBYWFI(), .EVENT_EVENTI(1\'B0), .DDR_ARB(4\'B0), .MIO(MIO), .DDR_CAS_n(DDR_CAS_n), .DDR_CKE(DDR_CKE), .DDR_Clk_n(DDR_Clk_n), .DDR_Clk(DDR_Clk), .DDR_CS_n(DDR_CS_n), .DDR_DRSTB(DDR_DRSTB), .DDR_ODT(DDR_ODT), .DDR_RAS_n(DDR_RAS_n), .DDR_WEB(DDR_WEB), .DDR_BankAddr(DDR_BankAddr), .DDR_Addr(DDR_Addr), .DDR_VRN(DDR_VRN), .DDR_VRP(DDR_VRP), .DDR_DM(DDR_DM), .DDR_DQ(DDR_DQ), .DDR_DQS_n(DDR_DQS_n), .DDR_DQS(DDR_DQS), .PS_SRSTB(PS_SRSTB), .PS_CLK(PS_CLK), .PS_PORB(PS_PORB) ); endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_sparse_mem.v * * Date : 2012-11 * * Description : Sparse Memory Model * *****************************************************************************/ /*** WA for CR # 695818 ***/ `ifdef XILINX_SIMULATOR `define XSIM_ISIM `endif `ifdef XILINX_ISIM `define XSIM_ISIM `endif module processing_system7_bfm_v2_0_sparse_mem(); `include "processing_system7_bfm_v2_0_local_params.v" parameter mem_size = 32\'h4000_0000; /// 1GB mem size parameter xsim_mem_size = 32\'h1000_0000; ///256 MB mem size (x4 for XSIM/ISIM) `ifdef XSIM_ISIM reg [data_width-1:0] ddr_mem0 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem reg [data_width-1:0] ddr_mem1 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem reg [data_width-1:0] ddr_mem2 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem reg [data_width-1:0] ddr_mem3 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem `else reg /*sparse*/ [data_width-1:0] ddr_mem [0:(mem_size/mem_width)-1]; // \'h10_0000 to \'h3FFF_FFFF - 1G mem `endif event mem_updated; reg check_we; reg [addr_width-1:0] check_up_add; reg [data_width-1:0] updated_data; /* preload memory from file */ task automatic pre_load_mem_from_file; input [(max_chars*8)-1:0] file_name; input [addr_width-1:0] start_addr; input [int_width-1:0] no_of_bytes; `ifdef XSIM_ISIM case(start_addr[31:28]) 4\'d0 : $readmemh(file_name,ddr_mem0,start_addr>>shft_addr_bits); 4\'d1 : $readmemh(file_name,ddr_mem1,start_addr>>shft_addr_bits); 4\'d2 : $readmemh(file_name,ddr_mem2,start_addr>>shft_addr_bits); 4\'d3 : $readmemh(file_name,ddr_mem3,start_addr>>shft_addr_bits); endcase `else $readmemh(file_name,ddr_mem,start_addr>>shft_addr_bits); `endif endtask /* preload memory with some random data */ task automatic pre_load_mem; input [1:0] data_type; input [addr_width-1:0] start_addr; input [int_width-1:0] no_of_bytes; integer i; reg [addr_width-1:0] addr; begin addr = start_addr >> shft_addr_bits; for (i = 0; i < no_of_bytes; i = i + mem_width) begin case(data_type) ALL_RANDOM : set_data(addr , $random); ALL_ZEROS : set_data(addr , 32\'h0000_0000); ALL_ONES : set_data(addr , 32\'hFFFF_FFFF); default : set_data(addr , $random); endcase addr = addr+1; end end endtask /* wait for memory update at certain location */ task automatic wait_mem_update; input[addr_width-1:0] address; output[data_width-1:0] dataout; begin check_up_add = address >> shft_addr_bits; check_we = 1; @(mem_updated); dataout = updated_data; check_we = 0; end endtask /* internal task to write data in memory */ task automatic set_data; input [addr_width-1:0] addr; input [data_width-1:0] data; begin if(check_we && (addr === check_up_add)) begin updated_data = data; -> mem_updated; end `ifdef XSIM_ISIM case(addr[31:26]) 6\'d0 : ddr_mem0[addr[25:0]] = data; 6\'d1 : ddr_mem1[addr[25:0]] = data; 6\'d2 : ddr_mem2[addr[25:0]] = data; 6\'d3 : ddr_mem3[addr[25:0]] = data; endcase `else ddr_mem[addr] = data; `endif end endtask /* internal task to read data from memory */ task automatic get_data; input [addr_width-1:0] addr; output [data_width-1:0] data; begin `ifdef XSIM_ISIM case(addr[31:26]) 6\'d0 : data = ddr_mem0[addr[25:0]]; 6\'d1 : data = ddr_mem1[addr[25:0]]; 6\'d2 : data = ddr_mem2[addr[25:0]]; 6\'d3 : data = ddr_mem3[addr[25:0]]; endcase `else data = ddr_mem[addr]; `endif end endtask /* Write memory */ task write_mem; input [max_burst_bits-1 :0] data; input [addr_width-1:0] start_addr; input [max_burst_bytes_width:0] no_of_bytes; reg [addr_width-1:0] addr; reg [max_burst_bits-1 :0] wr_temp_data; reg [data_width-1:0] pre_pad_data,post_pad_data,temp_data; integer bytes_left; integer pre_pad_bytes; integer post_pad_bytes; begin addr = start_addr >> shft_addr_bits; wr_temp_data = data; `ifdef XLNX_INT_DBG $display("[%0d] : %0s : Writing DDR Memory starting address (0x%0h) with %0d bytes.\ Data (0x%0h)",$time, DISP_INT_INFO, start_addr, no_of_bytes, data); `endif temp_data = wr_temp_data[data_width-1:0]; bytes_left = no_of_bytes; /* when the no. of bytes to be updated is less than mem_width */ if(bytes_left < mem_width) begin /* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/ if(start_addr[shft_addr_bits-1:0] > 0) begin //temp_data = ddr_mem[addr]; get_data(addr,temp_data); pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0]; repeat(pre_pad_bytes) temp_data = temp_data << 8; repeat(pre_pad_bytes) begin temp_data = temp_data >> 8; temp_data[data_width-1:data_width-8] = wr_temp_data[7:0]; wr_temp_data = wr_temp_data >> 8; end bytes_left = bytes_left + pre_pad_bytes; end /* This is needed for post padding the data ...*/ post_pad_bytes = mem_width - bytes_left; //post_pad_data = ddr_mem[addr]; get_data(addr,post_pad_data); repeat(post_pad_bytes) temp_data = temp_data << 8; repeat(bytes_left) post_pad_data = post_pad_data >> 8; repeat(post_pad_bytes) begin temp_data = temp_data >> 8; temp_data[data_width-1:data_width-8] = post_pad_data[7:0]; post_pad_data = post_pad_data >> 8; end //ddr_mem[addr] = temp_data; set_data(addr,temp_data); end else begin /* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/ if(start_addr[shft_addr_bits-1:0] > 0) begin //temp_data = ddr_mem[addr]; get_data(addr,temp_data); pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0]; repeat(pre_pad_bytes) temp_data = temp_data << 8; repeat(pre_pad_bytes) begin temp_data = temp_data >> 8; temp_data[data_width-1:data_width-8] = wr_temp_data[7:0]; wr_temp_data = wr_temp_data >> 8; bytes_left = bytes_left -1; end end else begin wr_temp_data = wr_temp_data >> data_width; bytes_left = bytes_left - mem_width; end /* first data word end */ //ddr_mem[addr] = temp_data; set_data(addr,temp_data); addr = addr + 1; while(bytes_left > (mem_width-1) ) begin /// for unaliged address necessary to check for mem_wd-1 , accordingly we have to pad post bytes. //ddr_mem[addr] = wr_temp_data[data_width-1:0]; set_data(addr,wr_temp_data[data_width-1:0]); addr = addr+1; wr_temp_data = wr_temp_data >> data_width; bytes_left = bytes_left - mem_width; end //post_pad_data = ddr_mem[addr]; get_data(addr,post_pad_data); post_pad_bytes = mem_width - bytes_left; /* This is needed for last transfer in unaliged burst */ if(bytes_left > 0) begin temp_data = wr_temp_data[data_width-1:0]; repeat(post_pad_bytes) temp_data = temp_data << 8; repeat(bytes_left) post_pad_data = post_pad_data >> 8; repeat(post_pad_bytes) begin temp_data = temp_data >> 8; temp_data[data_width-1:data_width-8] = post_pad_data[7:0]; post_pad_data = post_pad_data >> 8; end //ddr_mem[addr] = temp_data; set_data(addr,temp_data); end end `ifdef XLNX_INT_DBG $display("[%0d] : %0s : DONE -> Writing DDR Memory starting address (0x%0h)",$time, DISP_INT_INFO, start_addr ); `endif end endtask /* read_memory */ task read_mem; output[max_burst_bits-1 :0] data; input [addr_width-1:0] start_addr; input [max_burst_bytes_width :0] no_of_bytes; integer i; reg [addr_width-1:0] addr; reg [data_width-1:0] temp_rd_data; reg [max_burst_bits-1:0] temp_data; integer pre_bytes; integer bytes_left; begin addr = start_addr >> shft_addr_bits; pre_bytes = start_addr[shft_addr_bits-1:0]; bytes_left = no_of_bytes; `ifdef XLNX_INT_DBG $display("[%0d] : %0s : Reading DDR Memory starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes ); `endif /* Get first data ... if unaligned address */ //temp_data[(max_burst * max_data_burst)-1 : (max_burst * max_data_burst)- data_width] = ddr_mem[addr]; get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]); if(no_of_bytes < mem_width ) begin temp_data = temp_data >> (pre_bytes * 8); repeat(max_burst_bytes - mem_width) temp_data = temp_data >> 8; end else begin bytes_left = bytes_left - (mem_width - pre_bytes); addr = addr+1; /* Got first data */ while (bytes_left > (mem_width-1) ) begin temp_data = temp_data >> data_width; //temp_data[(max_burst * max_data_burst)-1 : (max_burst * max_data_burst)- data_width] = ddr_mem[addr]; get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]); addr = addr+1; bytes_left = bytes_left - mem_width; end /* Get last valid data in the burst*/ //temp_rd_data = ddr_mem[addr]; get_data(addr,temp_rd_data); while(bytes_left > 0) begin temp_data = temp_data >> 8; temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0]; temp_rd_data = temp_rd_data >> 8; bytes_left = bytes_left - 1; end /* align to the brst_byte length */ repeat(max_burst_bytes - no_of_bytes) temp_data = temp_data >> 8; end data = temp_data; `ifdef XLNX_INT_DBG $display("[%0d] : %0s : DONE -> Reading DDR Memory starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data ); `endif end endtask /* backdoor read to memory */ task peek_mem_to_file; input [(max_chars*8)-1:0] file_name; input [addr_width-1:0] start_addr; input [int_width-1:0] no_of_bytes; integer rd_fd; integer bytes; reg [addr_width-1:0] addr; reg [data_width-1:0] rd_data; begin rd_fd = $fopen(file_name,"w"); bytes = no_of_bytes; addr = start_addr >> shft_addr_bits; while (bytes > 0) begin get_data(addr,rd_data); $fdisplayh(rd_fd,rd_data); bytes = bytes - 4; addr = addr + 1; end end endtask endmodule
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // // DO NOT MODIFY THIS FILE. // IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1 // IP Revision: 4 `timescale 1ns/1ps (* DowngradeIPIdentifiedWarnings = "yes" *) module base_zynq_design_auto_pc_1 ( aclk, aresetn, s_axi_awid, s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid, m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_arid, m_axi_araddr, m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready ); (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *) input wire aclk; (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *) input wire aresetn; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input wire [11 : 0] s_axi_awid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input wire [31 : 0] s_axi_awaddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input wire [3 : 0] s_axi_awlen; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input wire [2 : 0] s_axi_awsize; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input wire [1 : 0] s_axi_awburst; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input wire [1 : 0] s_axi_awlock; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input wire [3 : 0] s_axi_awcache; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input wire [2 : 0] s_axi_awprot; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *) input wire [3 : 0] s_axi_awqos; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input wire s_axi_awvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output wire s_axi_awready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *) input wire [11 : 0] s_axi_wid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input wire [31 : 0] s_axi_wdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input wire [3 : 0] s_axi_wstrb; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input wire s_axi_wlast; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input wire s_axi_wvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output wire s_axi_wready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) output wire [11 : 0] s_axi_bid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output wire [1 : 0] s_axi_bresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output wire s_axi_bvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input wire s_axi_bready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) input wire [11 : 0] s_axi_arid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input wire [31 : 0] s_axi_araddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input wire [3 : 0] s_axi_arlen; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input wire [2 : 0] s_axi_arsize; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input wire [1 : 0] s_axi_arburst; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input wire [1 : 0] s_axi_arlock; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input wire [3 : 0] s_axi_arcache; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input wire [2 : 0] s_axi_arprot; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) input wire [3 : 0] s_axi_arqos; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input wire s_axi_arvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output wire s_axi_arready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) output wire [11 : 0] s_axi_rid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output wire [31 : 0] s_axi_rdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output wire [1 : 0] s_axi_rresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output wire s_axi_rlast; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output wire s_axi_rvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input wire s_axi_rready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *) output wire [11 : 0] m_axi_awid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output wire [31 : 0] m_axi_awaddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *) output wire [7 : 0] m_axi_awlen; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *) output wire [2 : 0] m_axi_awsize; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *) output wire [1 : 0] m_axi_awburst; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *) output wire [0 : 0] m_axi_awlock; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *) output wire [3 : 0] m_axi_awcache; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output wire [2 : 0] m_axi_awprot; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *) output wire [3 : 0] m_axi_awregion; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *) output wire [3 : 0] m_axi_awqos; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output wire m_axi_awvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input wire m_axi_awready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output wire [31 : 0] m_axi_wdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output wire [3 : 0] m_axi_wstrb; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *) output wire m_axi_wlast; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output wire m_axi_wvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input wire m_axi_wready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *) input wire [11 : 0] m_axi_bid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input wire [1 : 0] m_axi_bresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input wire m_axi_bvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output wire m_axi_bready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *) output wire [11 : 0] m_axi_arid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output wire [31 : 0] m_axi_araddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) output wire [7 : 0] m_axi_arlen; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *) output wire [2 : 0] m_axi_arsize; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *) output wire [1 : 0] m_axi_arburst; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *) output wire [0 : 0] m_axi_arlock; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *) output wire [3 : 0] m_axi_arcache; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output wire [2 : 0] m_axi_arprot; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *) output wire [3 : 0] m_axi_arregion; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *) output wire [3 : 0] m_axi_arqos; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output wire m_axi_arvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input wire m_axi_arready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *) input wire [11 : 0] m_axi_rid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input wire [31 : 0] m_axi_rdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input wire [1 : 0] m_axi_rresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *) input wire m_axi_rlast; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input wire m_axi_rvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) output wire m_axi_rready; axi_protocol_converter_v2_1_axi_protocol_converter #( .C_FAMILY("zynq"), .C_M_AXI_PROTOCOL(0), .C_S_AXI_PROTOCOL(1), .C_IGNORE_ID(0), .C_AXI_ID_WIDTH(12), .C_AXI_ADDR_WIDTH(32), .C_AXI_DATA_WIDTH(32), .C_AXI_SUPPORTS_WRITE(1), .C_AXI_SUPPORTS_READ(1), .C_AXI_SUPPORTS_USER_SIGNALS(0), .C_AXI_AWUSER_WIDTH(1), .C_AXI_ARUSER_WIDTH(1), .C_AXI_WUSER_WIDTH(1), .C_AXI_RUSER_WIDTH(1), .C_AXI_BUSER_WIDTH(1), .C_TRANSLATION_MODE(2) ) inst ( .aclk(aclk), .aresetn(aresetn), .s_axi_awid(s_axi_awid), .s_axi_awaddr(s_axi_awaddr), .s_axi_awlen(s_axi_awlen), .s_axi_awsize(s_axi_awsize), .s_axi_awburst(s_axi_awburst), .s_axi_awlock(s_axi_awlock), .s_axi_awcache(s_axi_awcache), .s_axi_awprot(s_axi_awprot), .s_axi_awregion(4\'H0), .s_axi_awqos(s_axi_awqos), .s_axi_awuser(1\'H0), .s_axi_awvalid(s_axi_awvalid), .s_axi_awready(s_axi_awready), .s_axi_wid(s_axi_wid), .s_axi_wdata(s_axi_wdata), .s_axi_wstrb(s_axi_wstrb), .s_axi_wlast(s_axi_wlast), .s_axi_wuser(1\'H0), .s_axi_wvalid(s_axi_wvalid), .s_axi_wready(s_axi_wready), .s_axi_bid(s_axi_bid), .s_axi_bresp(s_axi_bresp), .s_axi_buser(), .s_axi_bvalid(s_axi_bvalid), .s_axi_bready(s_axi_bready), .s_axi_arid(s_axi_arid), .s_axi_araddr(s_axi_araddr), .s_axi_arlen(s_axi_arlen), .s_axi_arsize(s_axi_arsize), .s_axi_arburst(s_axi_arburst), .s_axi_arlock(s_axi_arlock), .s_axi_arcache(s_axi_arcache), .s_axi_arprot(s_axi_arprot), .s_axi_arregion(4\'H0), .s_axi_arqos(s_axi_arqos), .s_axi_aruser(1\'H0), .s_axi_arvalid(s_axi_arvalid), .s_axi_arready(s_axi_arready), .s_axi_rid(s_axi_rid), .s_axi_rdata(s_axi_rdata), .s_axi_rresp(s_axi_rresp), .s_axi_rlast(s_axi_rlast), .s_axi_ruser(), .s_axi_rvalid(s_axi_rvalid), .s_axi_rready(s_axi_rready), .m_axi_awid(m_axi_awid), .m_axi_awaddr(m_axi_awaddr), .m_axi_awlen(m_axi_awlen), .m_axi_awsize(m_axi_awsize), .m_axi_awburst(m_axi_awburst), .m_axi_awlock(m_axi_awlock), .m_axi_awcache(m_axi_awcache), .m_axi_awprot(m_axi_awprot), .m_axi_awregion(m_axi_awregion), .m_axi_awqos(m_axi_awqos), .m_axi_awuser(), .m_axi_awvalid(m_axi_awvalid), .m_axi_awready(m_axi_awready), .m_axi_wid(), .m_axi_wdata(m_axi_wdata), .m_axi_wstrb(m_axi_wstrb), .m_axi_wlast(m_axi_wlast), .m_axi_wuser(), .m_axi_wvalid(m_axi_wvalid), .m_axi_wready(m_axi_wready), .m_axi_bid(m_axi_bid), .m_axi_bresp(m_axi_bresp), .m_axi_buser(1\'H0), .m_axi_bvalid(m_axi_bvalid), .m_axi_bready(m_axi_bready), .m_axi_arid(m_axi_arid), .m_axi_araddr(m_axi_araddr), .m_axi_arlen(m_axi_arlen), .m_axi_arsize(m_axi_arsize), .m_axi_arburst(m_axi_arburst), .m_axi_arlock(m_axi_arlock), .m_axi_arcache(m_axi_arcache), .m_axi_arprot(m_axi_arprot), .m_axi_arregion(m_axi_arregion), .m_axi_arqos(m_axi_arqos), .m_axi_aruser(), .m_axi_arvalid(m_axi_arvalid), .m_axi_arready(m_axi_arready), .m_axi_rid(m_axi_rid), .m_axi_rdata(m_axi_rdata), .m_axi_rresp(m_axi_rresp), .m_axi_rlast(m_axi_rlast), .m_axi_ruser(1\'H0), .m_axi_rvalid(m_axi_rvalid), .m_axi_rready(m_axi_rready) ); endmodule
// -- (c) Copyright 2011-2014 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // File name: axi_crossbar.v //----------------------------------------------------------------------------- `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_crossbar_v2_1_axi_crossbar # ( parameter C_FAMILY = "rtl", // FPGA Base Family. Current version: virtex6 or spartan6. parameter integer C_NUM_SLAVE_SLOTS = 1, // Number of Slave Interface (SI) slots for connecting // to master IP. Range: 1-16. parameter integer C_NUM_MASTER_SLOTS = 2, // Number of Master Interface (MI) slots for connecting // to slave IP. Range: 1-16. parameter integer C_AXI_ID_WIDTH = 1, // Width of ID signals propagated by the Interconnect. // Width of ID signals produced on all MI slots. // Range: 1-32. parameter integer C_AXI_ADDR_WIDTH = 32, // Width of s_axi_awaddr, s_axi_araddr, m_axi_awaddr and // m_axi_araddr for all SI/MI slots. // Range: 1-64. parameter integer C_AXI_DATA_WIDTH = 32, // Data width of the internal interconnect write and read // data paths. // Range: 32, 64, 128, 256, 512, 1024. parameter integer C_AXI_PROTOCOL = 0, // 0 = "AXI4", // 1 = "AXI3", // 2 = "AXI4LITE" // Propagate WID only when C_AXI_PROTOCOL = 1. parameter integer C_NUM_ADDR_RANGES = 1, // Number of BASE/HIGH_ADDR pairs per MI slot. // Range: 1-16. parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = 128\'h00000000001000000000000000000000, // Base address of each range of each MI slot. // For unused ranges, set C_M_AXI_BASE_ADDR[mm*aa*64 +: C_AXI_ADDR_WIDTH] = {C_AXI_ADDR_WIDTH{1\'b1}}. // (Bit positions above C_AXI_ADDR_WIDTH are ignored.) // Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit64}}. parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*32-1:0] C_M_AXI_ADDR_WIDTH = 64\'H0000000c0000000c, // Number of low-order address bits that are used to select locations within each address range of each MI slot. // The High address of each range is derived as BASE_ADDR + 2**C_M_AXI_ADDR_WIDTH -1. // For used address ranges, C_M_AXI_ADDR_WIDTH must be > 0. // For unused ranges, set C_M_AXI_ADDR_WIDTH to 32\'h00000000. // Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit32}}. // Range: 0 - C_AXI_ADDR_WIDTH. parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_BASE_ID = 32\'h00000000, // Base ID of each SI slot. // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 0 to 2**C_AXI_ID_WIDTH-1. parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_THREAD_ID_WIDTH = 32\'h00000000, // Number of low-order ID bits a connected master may vary to select a transaction thread. // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 0 - C_AXI_ID_WIDTH. parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, // 1 = Propagate all USER signals, 0 = Dont propagate. parameter integer C_AXI_AWUSER_WIDTH = 1, // Width of AWUSER signals for all SI slots and MI slots. // Range: 1-1024. parameter integer C_AXI_ARUSER_WIDTH = 1, // Width of ARUSER signals for all SI slots and MI slots. // Range: 1-1024. parameter integer C_AXI_WUSER_WIDTH = 1, // Width of WUSER signals for all SI slots and MI slots. // Range: 1-1024. parameter integer C_AXI_RUSER_WIDTH = 1, // Width of RUSER signals for all SI slots and MI slots. // Range: 1-1024. parameter integer C_AXI_BUSER_WIDTH = 1, // Width of BUSER signals for all SI slots and MI slots. // Range: 1-1024. parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_CONNECTIVITY = 64\'hFFFFFFFFFFFFFFFF, // Multi-pathway write connectivity from each SI slot (N) to each // MI slot (M): // 0 = no pathway required; 1 = pathway required. (Valid only for SAMD) // Format: C_NUM_MASTER_SLOTS{Bit32}; parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_CONNECTIVITY = 64\'hFFFFFFFFFFFFFFFF, // Multi-pathway read connectivity from each SI slot (N) to each // MI slot (M): // 0 = no pathway required; 1 = pathway required. (Valid only for SAMD) // Format: C_NUM_MASTER_SLOTS{Bit32}; parameter integer C_R_REGISTER = 0, // Insert register slice on R channel in the crossbar. (Valid only for SASD) // Range: Reg-slice type (0-8). parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_SINGLE_THREAD = 32\'h00000000, // 0 = Implement separate command queues per ID thread. // 1 = Force corresponding SI slot to be single-threaded. (Valid only for SAMD) // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 0, 1 parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_WRITE_ACCEPTANCE = 32\'H00000002, // Maximum number of active write transactions that each SI // slot can accept. (Valid only for SAMD) // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 1-32. parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_READ_ACCEPTANCE = 32\'H00000002, // Maximum number of active read transactions that each SI // slot can accept. (Valid only for SAMD) // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 1-32. parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_ISSUING = 64\'H0000000400000004, // Maximum number of data-active write transactions that // each MI slot can generate at any one time. (Valid only for SAMD) // Format: C_NUM_MASTER_SLOTS{Bit32}; // Range: 1-32. parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_ISSUING = 64\'H0000000400000004, // Maximum number of active read transactions that // each MI slot can generate at any one time. (Valid only for SAMD) // Format: C_NUM_MASTER_SLOTS{Bit32}; // Range: 1-32. parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY = 32\'h00000000, // Arbitration priority among each SI slot. // Higher values indicate higher priority. // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 0-15. parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE = 32\'h00000000, // Indicates whether each MI slot connects to a secure slave // (allows only TrustZone secure access). // Format: C_NUM_MASTER_SLOTS{Bit32}. // Range: 0, 1 parameter integer C_CONNECTIVITY_MODE = 1 // 0 = Shared-Address Shared-Data (SASD). // 1 = Shared-Address Multi-Data (SAMD). // Default 1 (on) for simulation; default 0 (off) for implementation. ) ( // Global Signals input wire aclk, input wire aresetn, // Slave Interface Write Address Ports input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_awid, input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen, input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_awsize, input wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_awburst, input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock, input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_awcache, input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_awprot, // input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_awregion, input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_awqos, input wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_awvalid, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_awready, // Slave Interface Write Data Ports input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_wid, input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] s_axi_wdata, input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wlast, input wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] s_axi_wuser, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wvalid, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wready, // Slave Interface Write Response Ports output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_bid, output wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_bresp, output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] s_axi_buser, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_bvalid, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_bready, // Slave Interface Read Address Ports input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_arid, input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] s_axi_araddr, input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen, input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_arsize, input wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_arburst, input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock, input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_arcache, input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_arprot, // input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_arregion, input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_arqos, input wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_arvalid, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_arready, // Slave Interface Read Data Ports output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_rid, output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] s_axi_rdata, output wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_rresp, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rlast, output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] s_axi_ruser, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rvalid, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rready, // Master Interface Write Address Port output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_awid, output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen, output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_awsize, output wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_awburst, output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock, output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awcache, output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_awprot, output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awregion, output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awqos, output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_awvalid, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_awready, // Master Interface Write Data Ports output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_wid, output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] m_axi_wdata, output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wlast, output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] m_axi_wuser, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wvalid, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wready, // Master Interface Write Response Ports input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_bid, input wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_bresp, input wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] m_axi_buser, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_bvalid, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_bready, // Master Interface Read Address Port output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_arid, output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] m_axi_araddr, output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen, output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_arsize, output wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_arburst, output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock, output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arcache, output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_arprot, output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arregion, output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arqos, output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_arvalid, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_arready, // Master Interface Read Data Ports input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_rid, input wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] m_axi_rdata, input wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_rresp, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rlast, input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] m_axi_ruser, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rvalid, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rready ); localparam [64:0] P_ONES = {65{1\'b1}}; localparam [C_NUM_SLAVE_SLOTS*64-1:0] P_S_AXI_BASE_ID = f_base_id(0); localparam [C_NUM_SLAVE_SLOTS*64-1:0] P_S_AXI_HIGH_ID = f_high_id(0); localparam integer P_AXI4 = 0; localparam integer P_AXI3 = 1; localparam integer P_AXILITE = 2; localparam [2:0] P_AXILITE_SIZE = 3\'b010; localparam [1:0] P_INCR = 2\'b01; localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_WRITE = f_m_supports_write(0); localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_READ = f_m_supports_read(0); localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_WRITE = f_s_supports_write(0); localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_READ = f_s_supports_read(0); localparam integer C_DEBUG = 1; localparam integer P_RANGE_CHECK = 1; // 1 (non-zero) = Detect and issue DECERR on the following conditions: // a. address range mismatch (no valid MI slot) // b. Burst or >32-bit transfer to AxiLite slave // c. TrustZone access violation // d. R/W direction unsupported by target // 0 = Pass all transactions (no DECERR): // a. Omit DECERR detection and response logic // b. Omit address decoder and propagate s_axi_a*REGION to m_axi_a*REGION // when C_NUM_MASTER_SLOTS=1 and C_NUM_ADDR_RANGES=1. // c. Unpredictable target MI-slot if address mismatch and >1 MI-slot // d. Transaction corruption if any burst or >32-bit transfer to AxiLite slave // Illegal combination: P_RANGE_CHECK = 0 && C_M_AXI_SECURE != 0. localparam integer P_ADDR_DECODE = ((P_RANGE_CHECK == 1) || (C_NUM_MASTER_SLOTS > 1) || (C_NUM_ADDR_RANGES > 1)) ? 1 : 0; // Always 1 localparam [C_NUM_MASTER_SLOTS*32-1:0] P_M_AXI_ERR_MODE = {C_NUM_MASTER_SLOTS{32\'h00000000}}; // Transaction error detection (per MI-slot) // 0 = None; 1 = AXI4Lite burst violation // Format: C_NUM_MASTER_SLOTS{Bit32}; localparam integer P_LEN = (C_AXI_PROTOCOL == P_AXI3) ? 4 : 8; localparam integer P_LOCK = (C_AXI_PROTOCOL == P_AXI3) ? 2 : 1; localparam P_FAMILY = ((C_FAMILY == "virtex7") || (C_FAMILY == "kintex7") || (C_FAMILY == "artix7") || (C_FAMILY == "zynq")) ? C_FAMILY : "rtl"; function integer f_ceil_log2 ( input integer x ); integer acc; begin acc=0; while ((2**acc) < x) acc = acc + 1; f_ceil_log2 = acc; end endfunction // Widths of all write issuance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit) function [(C_NUM_MASTER_SLOTS+1)*32-1:0] f_write_issue_width_vec (input null_arg); integer mi; reg [(C_NUM_MASTER_SLOTS+1)*32-1:0] result; begin result = 0; for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin result[mi*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32\'h0 : f_ceil_log2(C_M_AXI_WRITE_ISSUING[mi*32+:32]); end result[C_NUM_MASTER_SLOTS*32+:32] = 32\'h0; f_write_issue_width_vec = result; end endfunction // Widths of all read issuance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit) function [(C_NUM_MASTER_SLOTS+1)*32-1:0] f_read_issue_width_vec (input null_arg); integer mi; reg [(C_NUM_MASTER_SLOTS+1)*32-1:0] result; begin result = 0; for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin result[mi*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32\'h0 : f_ceil_log2(C_M_AXI_READ_ISSUING[mi*32+:32]); end result[C_NUM_MASTER_SLOTS*32+:32] = 32\'h0; f_read_issue_width_vec = result; end endfunction // Widths of all write acceptance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit) function [C_NUM_SLAVE_SLOTS*32-1:0] f_write_accept_width_vec (input null_arg); integer si; reg [C_NUM_SLAVE_SLOTS*32-1:0] result; begin result = 0; for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin result[si*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32\'h0 : f_ceil_log2(C_S_AXI_WRITE_ACCEPTANCE[si*32+:32]); end f_write_accept_width_vec = result; end endfunction // Widths of all read acceptance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit) function [C_NUM_SLAVE_SLOTS*32-1:0] f_read_accept_width_vec (input null_arg); integer si; reg [C_NUM_SLAVE_SLOTS*32-1:0] result; begin result = 0; for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin result[si*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32\'h0 : f_ceil_log2(C_S_AXI_READ_ACCEPTANCE[si*32+:32]); end f_read_accept_width_vec = result; end endfunction // Convert C_S_AXI_BASE_ID vector from Bit32 to Bit64 format function [C_NUM_SLAVE_SLOTS*64-1:0] f_base_id (input null_arg); integer si; reg [C_NUM_SLAVE_SLOTS*64-1:0] result; begin result = 0; for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin result[si*64+:C_AXI_ID_WIDTH] = C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH]; end f_base_id = result; end endfunction // Construct P_S_HIGH_ID vector function [C_NUM_SLAVE_SLOTS*64-1:0] f_high_id (input null_arg); integer si; reg [C_NUM_SLAVE_SLOTS*64-1:0] result; begin result = 0; for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin result[si*64+:C_AXI_ID_WIDTH] = (C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] : ({1\'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1\'b1}} : (C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] | ~(P_ONES << {1\'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]})); end f_high_id = result; end endfunction // Construct P_M_HIGH_ADDR vector function [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] f_high_addr (input null_arg); integer ar; reg [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] result; begin result = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1\'b0}}; for (ar=0; ar<C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES; ar=ar+1) begin result[ar*64+:C_AXI_ADDR_WIDTH] = (C_M_AXI_ADDR_WIDTH[ar*32+:32] == 0) ? 64\'h00000000_00000000 : ({1\'b0, C_M_AXI_ADDR_WIDTH[ar*32+:31]} >= C_AXI_ADDR_WIDTH) ? {C_AXI_ADDR_WIDTH{1\'b1}} : (C_M_AXI_BASE_ADDR[ar*64+:C_AXI_ADDR_WIDTH] | ~(P_ONES << {1\'b0, C_M_AXI_ADDR_WIDTH[ar*32+:7]})); end f_high_addr = result; end endfunction // Generate a mask of valid ID bits for a given SI slot. function [C_AXI_ID_WIDTH-1:0] f_thread_id_mask (input integer si); begin f_thread_id_mask = (C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? {C_AXI_ID_WIDTH{1\'b0}} : ({1\'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1\'b1}} : ({C_AXI_ID_WIDTH{1\'b0}} | ~(P_ONES << {1\'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]})); end endfunction // Isolate thread bits of input S_ID and add to BASE_ID to form MI-side ID value // only for end-point SI-slots function [C_AXI_ID_WIDTH-1:0] f_extend_ID ( input [C_AXI_ID_WIDTH-1:0] s_id, input integer si ); begin f_extend_ID = (C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] : ({1\'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? s_id : (C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] | (s_id & ~(P_ONES << {1\'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]}))); end endfunction // Bit vector of SI slots with at least one write connection. function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_write (input null_arg); integer mi; reg [C_NUM_SLAVE_SLOTS-1:0] result; begin result = {C_NUM_SLAVE_SLOTS{1\'b0}}; for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin result = result | C_M_AXI_WRITE_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS]; end f_s_supports_write = result; end endfunction // Bit vector of SI slots with at least one read connection. function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_read (input null_arg); integer mi; reg [C_NUM_SLAVE_SLOTS-1:0] result; begin result = {C_NUM_SLAVE_SLOTS{1\'b0}}; for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin result = result | C_M_AXI_READ_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS]; end f_s_supports_read = result; end endfunction // Bit vector of MI slots with at least one write connection. function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_write (input null_arg); integer mi; begin for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin f_m_supports_write[mi] = (|C_M_AXI_WRITE_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS]); end end endfunction // Bit vector of MI slots with at least one read connection. function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_read (input null_arg); integer mi; begin for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin f_m_supports_read[mi] = (|C_M_AXI_READ_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS]); end end endfunction wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_awid ; wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] si_cb_awaddr ; wire [C_NUM_SLAVE_SLOTS*8-1:0] si_cb_awlen ; wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_awsize ; wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_awburst ; wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_awlock ; wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_awcache ; wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_awprot ; // wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_awregion ; wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_awqos ; wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] si_cb_awuser ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_awvalid ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_awready ; wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_wid ; wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] si_cb_wdata ; wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] si_cb_wstrb ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wlast ; wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] si_cb_wuser ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wvalid ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wready ; wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_bid ; wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_bresp ; wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] si_cb_buser ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_bvalid ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_bready ; wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_arid ; wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] si_cb_araddr ; wire [C_NUM_SLAVE_SLOTS*8-1:0] si_cb_arlen ; wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_arsize ; wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_arburst ; wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_arlock ; wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_arcache ; wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_arprot ; // wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_arregion ; wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_arqos ; wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] si_cb_aruser ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_arvalid ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_arready ; wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_rid ; wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] si_cb_rdata ; wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_rresp ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rlast ; wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] si_cb_ruser ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rvalid ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rready ; wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_awid ; wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] cb_mi_awaddr ; wire [C_NUM_MASTER_SLOTS*8-1:0] cb_mi_awlen ; wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_awsize ; wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_awburst ; wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_awlock ; wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_awcache ; wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_awprot ; wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_awregion ; wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_awqos ; wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] cb_mi_awuser ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_awvalid ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_awready ; wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_wid ; wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] cb_mi_wdata ; wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] cb_mi_wstrb ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wlast ; wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] cb_mi_wuser ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wvalid ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wready ; wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_bid ; wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_bresp ; wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] cb_mi_buser ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_bvalid ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_bready ; wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_arid ; wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] cb_mi_araddr ; wire [C_NUM_MASTER_SLOTS*8-1:0] cb_mi_arlen ; wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_arsize ; wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_arburst ; wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_arlock ; wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_arcache ; wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_arprot ; wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_arregion ; wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_arqos ; wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] cb_mi_aruser ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_arvalid ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_arready ; wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_rid ; wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] cb_mi_rdata ; wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_rresp ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rlast ; wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] cb_mi_ruser ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rvalid ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rready ; genvar slot; generate for (slot=0;slot<C_NUM_SLAVE_SLOTS;slot=slot+1) begin : gen_si_tieoff assign si_cb_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (s_axi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ; assign si_cb_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ; assign si_cb_awlen[slot*8+:8] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awlen[slot*P_LEN+:P_LEN] : 0 ; assign si_cb_awsize[slot*3+:3] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awsize[slot*3+:3] : P_AXILITE_SIZE ; assign si_cb_awburst[slot*2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awburst[slot*2+:2] : P_INCR ; assign si_cb_awlock[slot*2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? {1\'b0, s_axi_awlock[slot*P_LOCK+:1]} : 0 ; assign si_cb_awcache[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awcache[slot*4+:4] : 0 ; assign si_cb_awprot[slot*3+:3] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awprot[slot*3+:3] : 0 ; assign si_cb_awqos[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awqos[slot*4+:4] : 0 ; // assign si_cb_awregion[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_awregion[slot*4+:4] : 0 ; assign si_cb_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] : 0 ; assign si_cb_awvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awvalid[slot*1+:1] : 0 ; assign si_cb_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI3) ) ? (s_axi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ; assign si_cb_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ; assign si_cb_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ; assign si_cb_wlast[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_wlast[slot*1+:1] : 1\'b1 ; assign si_cb_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] : 0 ; assign si_cb_wvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wvalid[slot*1+:1] : 0 ; assign si_cb_bready[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_bready[slot*1+:1] : 0 ; assign si_cb_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (s_axi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ; assign si_cb_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ; assign si_cb_arlen[slot*8+:8] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arlen[slot*P_LEN+:P_LEN] : 0 ; assign si_cb_arsize[slot*3+:3] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arsize[slot*3+:3] : P_AXILITE_SIZE ; assign si_cb_arburst[slot*2+:2] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arburst[slot*2+:2] : P_INCR ; assign si_cb_arlock[slot*2+:2] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? {1\'b0, s_axi_arlock[slot*P_LOCK+:1]} : 0 ; assign si_cb_arcache[slot*4+:4] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arcache[slot*4+:4] : 0 ; assign si_cb_arprot[slot*3+:3] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_arprot[slot*3+:3] : 0 ; assign si_cb_arqos[slot*4+:4] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arqos[slot*4+:4] : 0 ; // assign si_cb_arregion[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_arregion[slot*4+:4] : 0 ; assign si_cb_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] : 0 ; assign si_cb_arvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_arvalid[slot*1+:1] : 0 ; assign si_cb_rready[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_rready[slot*1+:1] : 0 ; assign s_axi_awready[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_awready[slot*1+:1] : 0 ; assign s_axi_wready[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_wready[slot*1+:1] : 0 ; assign s_axi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (si_cb_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ; assign s_axi_bresp[slot*2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_bresp[slot*2+:2] : 0 ; assign s_axi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] : 0 ; assign s_axi_bvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_bvalid[slot*1+:1] : 0 ; assign s_axi_arready[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_arready[slot*1+:1] : 0 ; assign s_axi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (si_cb_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ; assign s_axi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ; assign s_axi_rresp[slot*2+:2] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rresp[slot*2+:2] : 0 ; assign s_axi_rlast[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cb_rlast[slot*1+:1] : 0 ; assign s_axi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] : 0 ; assign s_axi_rvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rvalid[slot*1+:1] : 0 ; end // gen_si_tieoff for (slot=0;slot<C_NUM_MASTER_SLOTS;slot=slot+1) begin : gen_mi_tieoff assign m_axi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ; assign m_axi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ; assign m_axi_awlen[slot*P_LEN+:P_LEN] = (~P_M_AXI_SUPPORTS_WRITE[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4 ) ? cb_mi_awlen[slot*8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_awlen[slot*8+:4] : 0 ; assign m_axi_awsize[slot*3+:3] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awsize[slot*3+:3] : 0 ; assign m_axi_awburst[slot*2+:2] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awburst[slot*2+:2] : 0 ; assign m_axi_awlock[slot*P_LOCK+:P_LOCK] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awlock[slot*2+:1] : 0 ; assign m_axi_awcache[slot*4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awcache[slot*4+:4] : 0 ; assign m_axi_awprot[slot*3+:3] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awprot[slot*3+:3] : 0 ; assign m_axi_awregion[slot*4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? cb_mi_awregion[slot*4+:4] : 0 ; assign m_axi_awqos[slot*4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awqos[slot*4+:4] : 0 ; assign m_axi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] : 0 ; assign m_axi_awvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awvalid[slot*1+:1] : 0 ; assign m_axi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ; assign m_axi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ; assign m_axi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ; assign m_axi_wlast[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_wlast[slot*1+:1] : 0 ; assign m_axi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] : 0 ; assign m_axi_wvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wvalid[slot*1+:1] : 0 ; assign m_axi_bready[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_bready[slot*1+:1] : 0 ; assign m_axi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ; assign m_axi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ; assign m_axi_arlen[slot*P_LEN+:P_LEN] = (~P_M_AXI_SUPPORTS_READ[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4 ) ? cb_mi_arlen[slot*8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_arlen[slot*8+:4] : 0 ; assign m_axi_arsize[slot*3+:3] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arsize[slot*3+:3] : 0 ; assign m_axi_arburst[slot*2+:2] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arburst[slot*2+:2] : 0 ; assign m_axi_arlock[slot*P_LOCK+:P_LOCK] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arlock[slot*2+:1] : 0 ; assign m_axi_arcache[slot*4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arcache[slot*4+:4] : 0 ; assign m_axi_arprot[slot*3+:3] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_arprot[slot*3+:3] : 0 ; assign m_axi_arregion[slot*4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? cb_mi_arregion[slot*4+:4] : 0 ; assign m_axi_arqos[slot*4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arqos[slot*4+:4] : 0 ; assign m_axi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] : 0 ; assign m_axi_arvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_arvalid[slot*1+:1] : 0 ; assign m_axi_rready[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_rready[slot*1+:1] : 0 ; assign cb_mi_awready[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_awready[slot*1+:1] : 0 ; assign cb_mi_wready[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_wready[slot*1+:1] : 0 ; assign cb_mi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ; assign cb_mi_bresp[slot*2+:2] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_bresp[slot*2+:2] : 0 ; assign cb_mi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] : 0 ; assign cb_mi_bvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_bvalid[slot*1+:1] : 0 ; assign cb_mi_arready[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_arready[slot*1+:1] : 0 ; assign cb_mi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ; assign cb_mi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ; assign cb_mi_rresp[slot*2+:2] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rresp[slot*2+:2] : 0 ; assign cb_mi_rlast[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rlast[slot*1+:1] : 1\'b1 ; assign cb_mi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] : 0 ; assign cb_mi_rvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rvalid[slot*1+:1] : 0 ; end // gen_mi_tieoff if ((C_CONNECTIVITY_MODE==0) || (C_AXI_PROTOCOL==P_AXILITE)) begin : gen_sasd axi_crossbar_v2_1_crossbar_sasd # ( .C_FAMILY (P_FAMILY), .C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS), .C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS), .C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH), .C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH), .C_AXI_PROTOCOL (C_AXI_PROTOCOL), .C_M_AXI_BASE_ADDR (C_M_AXI_BASE_ADDR), .C_M_AXI_HIGH_ADDR (f_high_addr(0)), .C_S_AXI_BASE_ID (P_S_AXI_BASE_ID), .C_S_AXI_HIGH_ID (P_S_AXI_HIGH_ID), .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS), .C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH), .C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH), .C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH), .C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH), .C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH), .C_S_AXI_SUPPORTS_WRITE (P_S_AXI_SUPPORTS_WRITE), .C_S_AXI_SUPPORTS_READ (P_S_AXI_SUPPORTS_READ), .C_M_AXI_SUPPORTS_WRITE (P_M_AXI_SUPPORTS_WRITE), .C_M_AXI_SUPPORTS_READ (P_M_AXI_SUPPORTS_READ), .C_S_AXI_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY), .C_M_AXI_SECURE (C_M_AXI_SECURE), .C_R_REGISTER (C_R_REGISTER), .C_RANGE_CHECK (P_RANGE_CHECK), .C_ADDR_DECODE (P_ADDR_DECODE), .C_M_AXI_ERR_MODE (P_M_AXI_ERR_MODE), .C_DEBUG (C_DEBUG) ) crossbar_sasd_0 ( .ACLK (aclk), .ARESETN (aresetn), .S_AXI_AWID (si_cb_awid ), .S_AXI_AWADDR (si_cb_awaddr ), .S_AXI_AWLEN (si_cb_awlen ), .S_AXI_AWSIZE (si_cb_awsize ), .S_AXI_AWBURST (si_cb_awburst ), .S_AXI_AWLOCK (si_cb_awlock ), .S_AXI_AWCACHE (si_cb_awcache ), .S_AXI_AWPROT (si_cb_awprot ), // .S_AXI_AWREGION (si_cb_awregion ), .S_AXI_AWQOS (si_cb_awqos ), .S_AXI_AWUSER (si_cb_awuser ), .S_AXI_AWVALID (si_cb_awvalid ), .S_AXI_AWREADY (si_cb_awready ), .S_AXI_WID (si_cb_wid ), .S_AXI_WDATA (si_cb_wdata ), .S_AXI_WSTRB (si_cb_wstrb ), .S_AXI_WLAST (si_cb_wlast ), .S_AXI_WUSER (si_cb_wuser ), .S_AXI_WVALID (si_cb_wvalid ), .S_AXI_WREADY (si_cb_wready ), .S_AXI_BID (si_cb_bid ), .S_AXI_BRESP (si_cb_bresp ), .S_AXI_BUSER (si_cb_buser ), .S_AXI_BVALID (si_cb_bvalid ), .S_AXI_BREADY (si_cb_bready ), .S_AXI_ARID (si_cb_arid ), .S_AXI_ARADDR (si_cb_araddr ), .S_AXI_ARLEN (si_cb_arlen ), .S_AXI_ARSIZE (si_cb_arsize ), .S_AXI_ARBURST (si_cb_arburst ), .S_AXI_ARLOCK (si_cb_arlock ), .S_AXI_ARCACHE (si_cb_arcache ), .S_AXI_ARPROT (si_cb_arprot ), // .S_AXI_ARREGION (si_cb_arregion ), .S_AXI_ARQOS (si_cb_arqos ), .S_AXI_ARUSER (si_cb_aruser ), .S_AXI_ARVALID (si_cb_arvalid ), .S_AXI_ARREADY (si_cb_arready ), .S_AXI_RID (si_cb_rid ), .S_AXI_RDATA (si_cb_rdata ), .S_AXI_RRESP (si_cb_rresp ), .S_AXI_RLAST (si_cb_rlast ), .S_AXI_RUSER (si_cb_ruser ), .S_AXI_RVALID (si_cb_rvalid ), .S_AXI_RREADY (si_cb_rready ), .M_AXI_AWID (cb_mi_awid ), .M_AXI_AWADDR (cb_mi_awaddr ), .M_AXI_AWLEN (cb_mi_awlen ), .M_AXI_AWSIZE (cb_mi_awsize ), .M_AXI_AWBURST (cb_mi_awburst ), .M_AXI_AWLOCK (cb_mi_awlock ), .M_AXI_AWCACHE (cb_mi_awcache ), .M_AXI_AW'b'PROT (cb_mi_awprot ), .M_AXI_AWREGION (cb_mi_awregion ), .M_AXI_AWQOS (cb_mi_awqos ), .M_AXI_AWUSER (cb_mi_awuser ), .M_AXI_AWVALID (cb_mi_awvalid ), .M_AXI_AWREADY (cb_mi_awready ), .M_AXI_WID (cb_mi_wid ), .M_AXI_WDATA (cb_mi_wdata ), .M_AXI_WSTRB (cb_mi_wstrb ), .M_AXI_WLAST (cb_mi_wlast ), .M_AXI_WUSER (cb_mi_wuser ), .M_AXI_WVALID (cb_mi_wvalid ), .M_AXI_WREADY (cb_mi_wready ), .M_AXI_BID (cb_mi_bid ), .M_AXI_BRESP (cb_mi_bresp ), .M_AXI_BUSER (cb_mi_buser ), .M_AXI_BVALID (cb_mi_bvalid ), .M_AXI_BREADY (cb_mi_bready ), .M_AXI_ARID (cb_mi_arid ), .M_AXI_ARADDR (cb_mi_araddr ), .M_AXI_ARLEN (cb_mi_arlen ), .M_AXI_ARSIZE (cb_mi_arsize ), .M_AXI_ARBURST (cb_mi_arburst ), .M_AXI_ARLOCK (cb_mi_arlock ), .M_AXI_ARCACHE (cb_mi_arcache ), .M_AXI_ARPROT (cb_mi_arprot ), .M_AXI_ARREGION (cb_mi_arregion ), .M_AXI_ARQOS (cb_mi_arqos ), .M_AXI_ARUSER (cb_mi_aruser ), .M_AXI_ARVALID (cb_mi_arvalid ), .M_AXI_ARREADY (cb_mi_arready ), .M_AXI_RID (cb_mi_rid ), .M_AXI_RDATA (cb_mi_rdata ), .M_AXI_RRESP (cb_mi_rresp ), .M_AXI_RLAST (cb_mi_rlast ), .M_AXI_RUSER (cb_mi_ruser ), .M_AXI_RVALID (cb_mi_rvalid ), .M_AXI_RREADY (cb_mi_rready ) ); end else begin : gen_samd axi_crossbar_v2_1_crossbar # ( .C_FAMILY (P_FAMILY), .C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS), .C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS), .C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_S_AXI_THREAD_ID_WIDTH (C_S_AXI_THREAD_ID_WIDTH), .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH), .C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH), .C_AXI_PROTOCOL (C_AXI_PROTOCOL), .C_M_AXI_BASE_ADDR (C_M_AXI_BASE_ADDR), .C_M_AXI_HIGH_ADDR (f_high_addr(0)), .C_S_AXI_BASE_ID (P_S_AXI_BASE_ID), .C_S_AXI_HIGH_ID (P_S_AXI_HIGH_ID), .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS), .C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH), .C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH), .C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH), .C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH), .C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH), .C_S_AXI_SUPPORTS_WRITE (P_S_AXI_SUPPORTS_WRITE), .C_S_AXI_SUPPORTS_READ (P_S_AXI_SUPPORTS_READ), .C_M_AXI_SUPPORTS_WRITE (P_M_AXI_SUPPORTS_WRITE), .C_M_AXI_SUPPORTS_READ (P_M_AXI_SUPPORTS_READ), .C_M_AXI_WRITE_CONNECTIVITY (C_M_AXI_WRITE_CONNECTIVITY), .C_M_AXI_READ_CONNECTIVITY (C_M_AXI_READ_CONNECTIVITY), .C_S_AXI_SINGLE_THREAD (C_S_AXI_SINGLE_THREAD), .C_S_AXI_WRITE_ACCEPTANCE (C_S_AXI_WRITE_ACCEPTANCE), .C_S_AXI_READ_ACCEPTANCE (C_S_AXI_READ_ACCEPTANCE), .C_M_AXI_WRITE_ISSUING (C_M_AXI_WRITE_ISSUING), .C_M_AXI_READ_ISSUING (C_M_AXI_READ_ISSUING), .C_S_AXI_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY), .C_M_AXI_SECURE (C_M_AXI_SECURE), .C_RANGE_CHECK (P_RANGE_CHECK), .C_ADDR_DECODE (P_ADDR_DECODE), .C_W_ISSUE_WIDTH (f_write_issue_width_vec(0) ), .C_R_ISSUE_WIDTH (f_read_issue_width_vec(0) ), .C_W_ACCEPT_WIDTH (f_write_accept_width_vec(0)), .C_R_ACCEPT_WIDTH (f_read_accept_width_vec(0)), .C_M_AXI_ERR_MODE (P_M_AXI_ERR_MODE), .C_DEBUG (C_DEBUG) ) crossbar_samd ( .ACLK (aclk), .ARESETN (aresetn), .S_AXI_AWID (si_cb_awid ), .S_AXI_AWADDR (si_cb_awaddr ), .S_AXI_AWLEN (si_cb_awlen ), .S_AXI_AWSIZE (si_cb_awsize ), .S_AXI_AWBURST (si_cb_awburst ), .S_AXI_AWLOCK (si_cb_awlock ), .S_AXI_AWCACHE (si_cb_awcache ), .S_AXI_AWPROT (si_cb_awprot ), // .S_AXI_AWREGION (si_cb_awregion ), .S_AXI_AWQOS (si_cb_awqos ), .S_AXI_AWUSER (si_cb_awuser ), .S_AXI_AWVALID (si_cb_awvalid ), .S_AXI_AWREADY (si_cb_awready ), .S_AXI_WID (si_cb_wid ), .S_AXI_WDATA (si_cb_wdata ), .S_AXI_WSTRB (si_cb_wstrb ), .S_AXI_WLAST (si_cb_wlast ), .S_AXI_WUSER (si_cb_wuser ), .S_AXI_WVALID (si_cb_wvalid ), .S_AXI_WREADY (si_cb_wready ), .S_AXI_BID (si_cb_bid ), .S_AXI_BRESP (si_cb_bresp ), .S_AXI_BUSER (si_cb_buser ), .S_AXI_BVALID (si_cb_bvalid ), .S_AXI_BREADY (si_cb_bready ), .S_AXI_ARID (si_cb_arid ), .S_AXI_ARADDR (si_cb_araddr ), .S_AXI_ARLEN (si_cb_arlen ), .S_AXI_ARSIZE (si_cb_arsize ), .S_AXI_ARBURST (si_cb_arburst ), .S_AXI_ARLOCK (si_cb_arlock ), .S_AXI_ARCACHE (si_cb_arcache ), .S_AXI_ARPROT (si_cb_arprot ), // .S_AXI_ARREGION (si_cb_arregion ), .S_AXI_ARQOS (si_cb_arqos ), .S_AXI_ARUSER (si_cb_aruser ), .S_AXI_ARVALID (si_cb_arvalid ), .S_AXI_ARREADY (si_cb_arready ), .S_AXI_RID (si_cb_rid ), .S_AXI_RDATA (si_cb_rdata ), .S_AXI_RRESP (si_cb_rresp ), .S_AXI_RLAST (si_cb_rlast ), .S_AXI_RUSER (si_cb_ruser ), .S_AXI_RVALID (si_cb_rvalid ), .S_AXI_RREADY (si_cb_rready ), .M_AXI_AWID (cb_mi_awid ), .M_AXI_AWADDR (cb_mi_awaddr ), .M_AXI_AWLEN (cb_mi_awlen ), .M_AXI_AWSIZE (cb_mi_awsize ), .M_AXI_AWBURST (cb_mi_awburst ), .M_AXI_AWLOCK (cb_mi_awlock ), .M_AXI_AWCACHE (cb_mi_awcache ), .M_AXI_AWPROT (cb_mi_awprot ), .M_AXI_AWREGION (cb_mi_awregion ), .M_AXI_AWQOS (cb_mi_awqos ), .M_AXI_AWUSER (cb_mi_awuser ), .M_AXI_AWVALID (cb_mi_awvalid ), .M_AXI_AWREADY (cb_mi_awready ), .M_AXI_WID (cb_mi_wid ), .M_AXI_WDATA (cb_mi_wdata ), .M_AXI_WSTRB (cb_mi_wstrb ), .M_AXI_WLAST (cb_mi_wlast ), .M_AXI_WUSER (cb_mi_wuser ), .M_AXI_WVALID (cb_mi_wvalid ), .M_AXI_WREADY (cb_mi_wready ), .M_AXI_BID (cb_mi_bid ), .M_AXI_BRESP (cb_mi_bresp ), .M_AXI_BUSER (cb_mi_buser ), .M_AXI_BVALID (cb_mi_bvalid ), .M_AXI_BREADY (cb_mi_bready ), .M_AXI_ARID (cb_mi_arid ), .M_AXI_ARADDR (cb_mi_araddr ), .M_AXI_ARLEN (cb_mi_arlen ), .M_AXI_ARSIZE (cb_mi_arsize ), .M_AXI_ARBURST (cb_mi_arburst ), .M_AXI_ARLOCK (cb_mi_arlock ), .M_AXI_ARCACHE (cb_mi_arcache ), .M_AXI_ARPROT (cb_mi_arprot ), .M_AXI_ARREGION (cb_mi_arregion ), .M_AXI_ARQOS (cb_mi_arqos ), .M_AXI_ARUSER (cb_mi_aruser ), .M_AXI_ARVALID (cb_mi_arvalid ), .M_AXI_ARREADY (cb_mi_arready ), .M_AXI_RID (cb_mi_rid ), .M_AXI_RDATA (cb_mi_rdata ), .M_AXI_RRESP (cb_mi_rresp ), .M_AXI_RLAST (cb_mi_rlast ), .M_AXI_RUSER (cb_mi_ruser ), .M_AXI_RVALID (cb_mi_rvalid ), .M_AXI_RREADY (cb_mi_rready ) ); end // gen_samd // end // gen_crossbar endgenerate endmodule `default_nettype wire
/***************************************************************************** * File : processing_system7_bfm_v2_0_regc.v * * Date : 2012-11 * * Description : Controller for Register Map Memory * *****************************************************************************/ module processing_system7_bfm_v2_0_regc( rstn, sw_clk, /* Goes to port 0 of REG */ reg_rd_req_port0, reg_rd_dv_port0, reg_rd_addr_port0, reg_rd_data_port0, reg_rd_bytes_port0, reg_rd_qos_port0, /* Goes to port 1 of REG */ reg_rd_req_port1, reg_rd_dv_port1, reg_rd_addr_port1, reg_rd_data_port1, reg_rd_bytes_port1, reg_rd_qos_port1 ); input rstn; input sw_clk; input reg_rd_req_port0; output reg_rd_dv_port0; input[31:0] reg_rd_addr_port0; output[1023:0] reg_rd_data_port0; input[7:0] reg_rd_bytes_port0; input [3:0] reg_rd_qos_port0; input reg_rd_req_port1; output reg_rd_dv_port1; input[31:0] reg_rd_addr_port1; output[1023:0] reg_rd_data_port1; input[7:0] reg_rd_bytes_port1; input[3:0] reg_rd_qos_port1; wire [3:0] rd_qos; reg [1023:0] rd_data; wire [31:0] rd_addr; wire [7:0] rd_bytes; reg rd_dv; wire rd_req; processing_system7_bfm_v2_0_arb_rd reg_read_ports ( .rstn(rstn), .sw_clk(sw_clk), .qos1(reg_rd_qos_port0), .qos2(reg_rd_qos_port1), .prt_req1(reg_rd_req_port0), .prt_req2(reg_rd_req_port1), .prt_data1(reg_rd_data_port0), .prt_data2(reg_rd_data_port1), .prt_addr1(reg_rd_addr_port0), .prt_addr2(reg_rd_addr_port1), .prt_bytes1(reg_rd_bytes_port0), .prt_bytes2(reg_rd_bytes_port1), .prt_dv1(reg_rd_dv_port0), .prt_dv2(reg_rd_dv_port1), .prt_qos(rd_qos), .prt_req(rd_req), .prt_data(rd_data), .prt_addr(rd_addr), .prt_bytes(rd_bytes), .prt_dv(rd_dv) ); processing_system7_bfm_v2_0_reg_map regm(); reg state; always@(posedge sw_clk or negedge rstn) begin if(!rstn) begin rd_dv <= 0; state <= 0; end else begin case(state) 0:begin state <= 0; rd_dv <= 0; if(rd_req) begin regm.read_reg_mem(rd_data,rd_addr, rd_bytes); rd_dv <= 1; state <= 1; end end 1:begin rd_dv <= 0; state <= 0; end endcase end /// if end// always endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_gen_reset.v * * Date : 2012-11 * * Description : Module that generates FPGA_RESETs and synchronizes RESETs to the * respective clocks. *****************************************************************************/ module processing_system7_bfm_v2_0_gen_reset( por_rst_n, sys_rst_n, rst_out_n, m_axi_gp0_clk, m_axi_gp1_clk, s_axi_gp0_clk, s_axi_gp1_clk, s_axi_hp0_clk, s_axi_hp1_clk, s_axi_hp2_clk, s_axi_hp3_clk, s_axi_acp_clk, m_axi_gp0_rstn, m_axi_gp1_rstn, s_axi_gp0_rstn, s_axi_gp1_rstn, s_axi_hp0_rstn, s_axi_hp1_rstn, s_axi_hp2_rstn, s_axi_hp3_rstn, s_axi_acp_rstn, fclk_reset3_n, fclk_reset2_n, fclk_reset1_n, fclk_reset0_n, fpga_acp_reset_n, fpga_gp_m0_reset_n, fpga_gp_m1_reset_n, fpga_gp_s0_reset_n, fpga_gp_s1_reset_n, fpga_hp_s0_reset_n, fpga_hp_s1_reset_n, fpga_hp_s2_reset_n, fpga_hp_s3_reset_n ); input por_rst_n; input sys_rst_n; input m_axi_gp0_clk; input m_axi_gp1_clk; input s_axi_gp0_clk; input s_axi_gp1_clk; input s_axi_hp0_clk; input s_axi_hp1_clk; input s_axi_hp2_clk; input s_axi_hp3_clk; input s_axi_acp_clk; output m_axi_gp0_rstn; output m_axi_gp1_rstn; output s_axi_gp0_rstn; output s_axi_gp1_rstn; output s_axi_hp0_rstn; output s_axi_hp1_rstn; output s_axi_hp2_rstn; output s_axi_hp3_rstn; output s_axi_acp_rstn; output rst_out_n; output fclk_reset3_n; output fclk_reset2_n; output fclk_reset1_n; output fclk_reset0_n; output fpga_acp_reset_n; output fpga_gp_m0_reset_n; output fpga_gp_m1_reset_n; output fpga_gp_s0_reset_n; output fpga_gp_s1_reset_n; output fpga_hp_s0_reset_n; output fpga_hp_s1_reset_n; output fpga_hp_s2_reset_n; output fpga_hp_s3_reset_n; reg [31:0] fabric_rst_n; reg r_m_axi_gp0_rstn; reg r_m_axi_gp1_rstn; reg r_s_axi_gp0_rstn; reg r_s_axi_gp1_rstn; reg r_s_axi_hp0_rstn; reg r_s_axi_hp1_rstn; reg r_s_axi_hp2_rstn; reg r_s_axi_hp3_rstn; reg r_s_axi_acp_rstn; assign rst_out_n = por_rst_n & sys_rst_n; assign fclk_reset0_n = !fabric_rst_n[0]; assign fclk_reset1_n = !fabric_rst_n[1]; assign fclk_reset2_n = !fabric_rst_n[2]; assign fclk_reset3_n = !fabric_rst_n[3]; assign fpga_acp_reset_n = !fabric_rst_n[24]; assign fpga_hp_s3_reset_n = !fabric_rst_n[23]; assign fpga_hp_s2_reset_n = !fabric_rst_n[22]; assign fpga_hp_s1_reset_n = !fabric_rst_n[21]; assign fpga_hp_s0_reset_n = !fabric_rst_n[20]; assign fpga_gp_s1_reset_n = !fabric_rst_n[17]; assign fpga_gp_s0_reset_n = !fabric_rst_n[16]; assign fpga_gp_m1_reset_n = !fabric_rst_n[13]; assign fpga_gp_m0_reset_n = !fabric_rst_n[12]; assign m_axi_gp0_rstn = (!por_rst_n & !sys_rst_n)? 1'b0 : r_m_axi_gp0_rstn; assign m_axi_gp1_rstn = (!por_rst_n & !sys_rst_n)? 1'b0 : r_m_axi_gp1_rstn; assign s_axi_gp0_rstn = (!por_rst_n & !sys_rst_n)? 1'b0 : r_s_axi_gp0_rstn; assign s_axi_gp1_rstn = (!por_rst_n & !sys_rst_n)? 1'b0 : r_s_axi_gp1_rstn; assign s_axi_hp0_rstn = (!por_rst_n & !sys_rst_n)? 1'b0 : r_s_axi_hp0_rstn; assign s_axi_hp1_rstn = (!por_rst_n & !sys_rst_n)? 1'b0 : r_s_axi_hp1_rstn; assign s_axi_hp2_rstn = (!por_rst_n & !sys_rst_n)? 1'b0 : r_s_axi_hp2_rstn; assign s_axi_hp3_rstn = (!por_rst_n & !sys_rst_n)? 1'b0 : r_s_axi_hp3_rstn; assign s_axi_acp_rstn = (!por_rst_n & !sys_rst_n)? 1'b0 : r_s_axi_acp_rstn; task fpga_soft_reset; input[31:0] reset_ctrl; begin fabric_rst_n[0] = reset_ctrl[0]; fabric_rst_n[1] = reset_ctrl[1]; fabric_rst_n[2] = reset_ctrl[2]; fabric_rst_n[3] = reset_ctrl[3]; fabric_rst_n[12] = reset_ctrl[12]; fabric_rst_n[13] = reset_ctrl[13]; fabric_rst_n[16] = reset_ctrl[16]; fabric_rst_n[17] = reset_ctrl[17]; fabric_rst_n[20] = reset_ctrl[20]; fabric_rst_n[21] = reset_ctrl[21]; fabric_rst_n[22] = reset_ctrl[22]; fabric_rst_n[23] = reset_ctrl[23]; fabric_rst_n[24] = reset_ctrl[24]; end endtask always@(negedge por_rst_n or negedge sys_rst_n) fabric_rst_n = 32'h01f3_300f; initial begin r_m_axi_gp0_rstn = 1'b0; r_m_axi_gp1_rstn = 1'b0; r_s_axi_gp0_rstn = 1'b0; r_s_axi_gp1_rstn = 1'b0; r_s_axi_hp0_rstn = 1'b0; r_s_axi_hp1_rstn = 1'b0; r_s_axi_hp2_rstn = 1'b0; r_s_axi_hp3_rstn = 1'b0; r_s_axi_acp_rstn = 1'b0; end always@(posedge m_axi_gp0_clk) r_m_axi_gp0_rstn = por_rst_n & sys_rst_n; always@(posedge m_axi_gp1_clk) r_m_axi_gp1_rstn = por_rst_n & sys_rst_n; always@(posedge s_axi_gp0_clk) r_s_axi_gp0_rstn = por_rst_n & sys_rst_n; always@(posedge s_axi_gp1_clk) r_s_axi_gp1_rstn = por_rst_n & sys_rst_n; always@(posedge s_axi_hp0_clk) r_s_axi_hp0_rstn = por_rst_n & sys_rst_n; always@(posedge s_axi_hp1_clk) r_s_axi_hp1_rstn = por_rst_n & sys_rst_n; always@(posedge s_axi_hp2_clk) r_s_axi_hp2_rstn = por_rst_n & sys_rst_n; always@(posedge s_axi_hp3_clk) r_s_axi_hp3_rstn = por_rst_n & sys_rst_n; always@(posedge s_axi_acp_clk) r_s_axi_acp_rstn = por_rst_n & sys_rst_n; endmodule
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // // DO NOT MODIFY THIS FILE. // IP VLNV: xilinx.com:ip:axi_crossbar:2.1 // IP Revision: 5 (* X_CORE_INFO = "axi_crossbar_v2_1_axi_crossbar,Vivado 2014.4" *) (* CHECK_LICENSE_TYPE = "base_zynq_design_xbar_0,axi_crossbar_v2_1_axi_crossbar,{}" *) (* CORE_GENERATION_INFO = "base_zynq_design_xbar_0,axi_crossbar_v2_1_axi_crossbar,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_NUM_SLAVE_SLOTS=1,C_NUM_MASTER_SLOTS=2,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_PROTOCOL=0,C_NUM_ADDR_RANGES=1,C_M_AXI_BASE_ADDR=0x00000000400000000000000041200000,C_M_AXI_ADDR_WIDTH=0x0000000d00000010,C_S_AXI_BASE_ID=0x00000000,C_S_AXI_THREAD_ID_WIDTH=0x0000000c,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0xFFFFFFFFFFFFFFFF,C_M_AXI_READ_CONNECTIVITY=0xFFFFFFFFFFFFFFFF,C_R_REGISTER=0,C_S_AXI_SINGLE_THREAD=0x00000000,C_S_AXI_WRITE_ACCEPTANCE=0x00000001,C_S_AXI_READ_ACCEPTANCE=0x00000001,C_M_AXI_WRITE_ISSUING=0x0000000100000001,C_M_AXI_READ_ISSUING=0x0000000100000001,C_S_AXI_ARB_PRIORITY=0x00000000,C_M_AXI_SECURE=0x00000000,C_CONNECTIVITY_MODE=0}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) module base_zynq_design_xbar_0 ( aclk, aresetn, s_axi_awid, s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid, m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready ); (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) input wire aclk; (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) input wire aresetn; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWID" *) input wire [11 : 0] s_axi_awid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *) input wire [31 : 0] s_axi_awaddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN" *) input wire [7 : 0] s_axi_awlen; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE" *) input wire [2 : 0] s_axi_awsize; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST" *) input wire [1 : 0] s_axi_awburst; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK" *) input wire [0 : 0] s_axi_awlock; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE" *) input wire [3 : 0] s_axi_awcache; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *) input wire [2 : 0] s_axi_awprot; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS" *) input wire [3 : 0] s_axi_awqos; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *) input wire [0 : 0] s_axi_awvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *) output wire [0 : 0] s_axi_awready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *) input wire [31 : 0] s_axi_wdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *) input wire [3 : 0] s_axi_wstrb; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST" *) input wire [0 : 0] s_axi_wlast; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *) input wire [0 : 0] s_axi_wvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *) output wire [0 : 0] s_axi_wready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BID" *) output wire [11 : 0] s_axi_bid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *) output wire [1 : 0] s_axi_bresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *) output wire [0 : 0] s_axi_bvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *) input wire [0 : 0] s_axi_bready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARID" *) input wire [11 : 0] s_axi_arid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *) input wire [31 : 0] s_axi_araddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN" *) input wire [7 : 0] s_axi_arlen; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE" *) input wire [2 : 0] s_axi_arsize; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST" *) input wire [1 : 0] s_axi_arburst; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK" *) input wire [0 : 0] s_axi_arlock; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE" *) input wire [3 : 0] s_axi_arcache; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *) input wire [2 : 0] s_axi_arprot; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS" *) input wire [3 : 0] s_axi_arqos; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *) input wire [0 : 0] s_axi_arvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *) output wire [0 : 0] s_axi_arready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RID" *) output wire [11 : 0] s_axi_rid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *) output wire [31 : 0] s_axi_rdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *) output wire [1 : 0] s_axi_rresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST" *) output wire [0 : 0] s_axi_rlast; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *) output wire [0 : 0] s_axi_rvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) input wire [0 : 0] s_axi_rready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32]" *) output wire [63 : 0] m_axi_awaddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLEN [7:0] [15:8]" *) output wire [15 : 0] m_axi_awlen; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE [2:0] [5:3]" *) output wire [5 : 0] m_axi_awsize; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI AWBURST [1:0] [3:2]" *) output wire [3 : 0] m_axi_awburst; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK [0:0] [1:1]" *) output wire [1 : 0] m_axi_awlock; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE [3:0] [7:4]" *) output wire [7 : 0] m_axi_awcache; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3]" *) output wire [5 : 0] m_axi_awprot; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREGION [3:0] [7:4]" *) output wire [7 : 0] m_axi_awregion; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWQOS [3:0] [7:4]" *) output wire [7 : 0] m_axi_awqos; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1]" *) output wire [1 : 0] m_axi_awvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1]" *) input wire [1 : 0] m_axi_awready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32]" *) output wire [63 : 0] m_axi_wdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4]" *) output wire [7 : 0] m_axi_wstrb; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WLAST [0:0] [1:1]" *) output wire [1 : 0] m_axi_wlast; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1]" *) output wire [1 : 0] m_axi_wvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1]" *) input wire [1 : 0] m_axi_wready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2]" *) input wire [3 : 0] m_axi_bresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1]" *) input wire [1 : 0] m_axi_bvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1]" *) output wire [1 : 0] m_axi_bready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32]" *) output wire [63 : 0] m_axi_araddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLEN [7:0] [15:8]" *) output wire [15 : 0] m_axi_arlen; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE [2:0] [5:3]" *) output wire [5 : 0] m_axi_arsize; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI ARBURST [1:0] [3:2]" *) output wire [3 : 0] m_axi_arburst; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK [0:0] [1:1]" *) output wire [1 : 0] m_axi_arlock; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE [3:0] [7:4]" *) output wire [7 : 0] m_axi_arcache; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3]" *) output wire [5 : 0] m_axi_arprot; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREGION [3:0] [7:4]" *) output wire [7 : 0] m_axi_arregion; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARQOS [3:0] [7:4]" *) output wire [7 : 0] m_axi_arqos; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1]" *) output wire [1 : 0] m_axi_arvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1]" *) input wire [1 : 0] m_axi_arready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32]" *) input wire [63 : 0] m_axi_rdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2]" *) input wire [3 : 0] m_axi_rresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RLAST [0:0] [1:1]" *) input wire [1 : 0] m_axi_rlast; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1]" *) input wire [1 : 0] m_axi_rvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1]" *) output wire [1 : 0] m_axi_rready; axi_crossbar_v2_1_axi_crossbar #( .C_FAMILY("zynq"), .C_NUM_SLAVE_SLOTS(1), .C_NUM_MASTER_SLOTS(2), .C_AXI_ID_WIDTH(12), .C_AXI_ADDR_WIDTH(32), .C_AXI_DATA_WIDTH(32), .C_AXI_PROTOCOL(0), .C_NUM_ADDR_RANGES(1), .C_M_AXI_BASE_ADDR(128\'H00000000400000000000000041200000), .C_M_AXI_ADDR_WIDTH(64\'H0000000d00000010), .C_S_AXI_BASE_ID(32\'H00000000), .C_S_AXI_THREAD_ID_WIDTH(32\'H0000000c), .C_AXI_SUPPORTS_USER_SIGNALS(0), .C_AXI_AWUSER_WIDTH(1), .C_AXI_ARUSER_WIDTH(1), .C_AXI_WUSER_WIDTH(1), .C_AXI_RUSER_WIDTH(1), .C_AXI_BUSER_WIDTH(1), .C_M_AXI_WRITE_CONNECTIVITY(64\'HFFFFFFFFFFFFFFFF), .C_M_AXI_READ_CONNECTIVITY(64\'HFFFFFFFFFFFFFFFF), .C_R_REGISTER(0), .C_S_AXI_SINGLE_THREAD(32\'H00000000), .C_S_AXI_WRITE_ACCEPTANCE(32\'H00000001), .C_S_AXI_READ_ACCEPTANCE(32\'H00000001), .C_M_AXI_WRITE_ISSUING(64\'H0000000100000001), .C_M_AXI_READ_ISSUING(64\'H0000000100000001), .C_S_AXI_ARB_PRIORITY(32\'H00000000), .C_M_AXI_SECURE(32\'H00000000), .C_CONNECTIVITY_MODE(0) ) inst ( .aclk(aclk), .aresetn(aresetn), .s_axi_awid(s_axi_awid), .s_axi_awaddr(s_axi_awaddr), .s_axi_awlen(s_axi_awlen), .s_axi_awsize(s_axi_awsize), .s_axi_awburst(s_axi_awburst), .s_axi_awlock(s_axi_awlock), .s_axi_awcache(s_axi_awcache), .s_axi_awprot(s_axi_awprot), .s_axi_awqos(s_axi_awqos), .s_axi_awuser(1\'H0), .s_axi_awvalid(s_axi_awvalid), .s_axi_awready(s_axi_awready), .s_axi_wid(12\'H000), .s_axi_wdata(s_axi_wdata), .s_axi_wstrb(s_axi_wstrb), .s_axi_wlast(s_axi_wlast), .s_axi_wuser(1\'H0), .s_axi_wvalid(s_axi_wvalid), .s_axi_wready(s_axi_wready), .s_axi_bid(s_axi_bid), .s_axi_bresp(s_axi_bresp), .s_axi_buser(), .s_axi_bvalid(s_axi_bvalid), .s_axi_bready(s_axi_bready), .s_axi_arid(s_axi_arid), .s_axi_araddr(s_axi_araddr), .s_axi_arlen(s_axi_arlen), .s_axi_arsize(s_axi_arsize), .s_axi_arburst(s_axi_arburst), .s_axi_arlock(s_axi_arlock), .s_axi_arcache(s_axi_arcache), .s_axi_arprot(s_axi_arprot), .s_axi_arqos(s_axi_arqos), .s_axi_aruser(1\'H0), .s_axi_arvalid(s_axi_arvalid), .s_axi_arready(s_axi_arready), .s_axi_rid(s_axi_rid), .s_axi_rdata(s_axi_rdata), .s_axi_rresp(s_axi_rresp), .s_axi_rlast(s_axi_rlast), .s_axi_ruser(), .s_axi_rvalid(s_axi_rvalid), .s_axi_rready(s_axi_rready), .m_axi_awid(), .m_axi_awaddr(m_axi_awaddr), .m_axi_awlen(m_axi_awlen), .m_axi_awsize(m_axi_awsize), .m_axi_awburst(m_axi_awburst), .m_axi_awlock(m_axi_awlock), .m_axi_awcache(m_axi_awcache), .m_axi_awprot(m_axi_awprot), .m_axi_awregion(m_axi_awregion), .m_axi_awqos(m_axi_awqos), .m_axi_awuser(), .m_axi_awvalid(m_axi_awvalid), .m_axi_awready(m_axi_awready), .m_axi_wid(), .m_axi_wdata(m_axi_wdata), .m_axi_wstrb(m_axi_wstrb), .m_axi_wlast(m_axi_wlast), .m_axi_wuser(), .m_axi_wvalid(m_axi_wvalid), .m_axi_wready(m_axi_wready), .m_axi_bid(24\'H000000), .m_axi_bresp(m_axi_bresp), .m_axi_buser(2\'H0), .m_axi_bvalid(m_axi_bvalid), .m_axi_bready(m_axi_bready), .m_axi_arid(), .m_axi_araddr(m_axi_araddr), .m_axi_arlen(m_axi_arlen), .m_axi_arsize(m_axi_arsize), .m_axi_arburst(m_axi_arburst), .m_axi_arlock(m_axi_arlock), .m_axi_arcache(m_axi_arcache), .m_axi_arprot(m_axi_arprot), .m_axi_arregion(m_axi_arregion), .m_axi_arqos(m_axi_arqos), .m_axi_aruser(), .m_axi_arvalid(m_axi_arvalid), .m_axi_arready(m_axi_arready), .m_axi_rid(24\'H000000), .m_axi_rdata(m_axi_rdata), .m_axi_rresp(m_axi_rresp), .m_axi_rlast(m_axi_rlast), .m_axi_ruser(2\'H0), .m_axi_rvalid(m_axi_rvalid), .m_axi_rready(m_axi_rready) ); endmodule
/////////////////////////////////////////////////////////////////////////////// // // File name: axi_protocol_converter_v2_1_b2s_wr_cmd_fsm.v // /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_protocol_converter_v2_1_b2s_wr_cmd_fsm ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire clk , input wire reset , output wire s_awready , input wire s_awvalid , output wire m_awvalid , input wire m_awready , // signal to increment to the next mc transaction output wire next , // signal to the fsm there is another transaction required input wire next_pending , // Write Data portion has completed or Read FIFO has a slot available (not // full) output wire b_push , input wire b_full , output wire a_push ); //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// // States localparam SM_IDLE = 2\'b00; localparam SM_CMD_EN = 2\'b01; localparam SM_CMD_ACCEPTED = 2\'b10; localparam SM_DONE_WAIT = 2\'b11; //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// reg [1:0] state; // synthesis attribute MAX_FANOUT of state is 20; reg [1:0] next_state; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL /////////////////////////////////////////////////////////////////////////////// always @(posedge clk) begin if (reset) begin state <= SM_IDLE; end else begin state <= next_state; end end // Next state transitions. always @( * ) begin next_state = state; case (state) SM_IDLE: if (s_awvalid) begin next_state = SM_CMD_EN; end else next_state = state; SM_CMD_EN: if (m_awready & next_pending) next_state = SM_CMD_ACCEPTED; else if (m_awready & ~next_pending & b_full) next_state = SM_DONE_WAIT; else if (m_awready & ~next_pending & ~b_full) next_state = SM_IDLE; else next_state = state; SM_CMD_ACCEPTED: next_state = SM_CMD_EN; SM_DONE_WAIT: if (!b_full) next_state = SM_IDLE; else next_state = state; default: next_state = SM_IDLE; endcase end // Assign outputs based on current state. assign m_awvalid = (state == SM_CMD_EN); assign next = ((state == SM_CMD_ACCEPTED) | (((state == SM_CMD_EN) | (state == SM_DONE_WAIT)) & (next_state == SM_IDLE))) ; assign a_push = (state == SM_IDLE); assign s_awready = ((state == SM_CMD_EN) | (state == SM_DONE_WAIT)) & (next_state == SM_IDLE); assign b_push = ((state == SM_CMD_EN) | (state == SM_DONE_WAIT)) & (next_state == SM_IDLE); endmodule `default_nettype wire
// (c) Copyright 2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // axis to vector // A generic module to merge all axi signals into one signal called payload. // This is strictly wires, so no clk, reset, aclken, valid/ready are required. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_infrastructure_v1_1_axi2vector # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// parameter integer C_AXI_PROTOCOL = 0, parameter integer C_AXI_ID_WIDTH = 4, parameter integer C_AXI_ADDR_WIDTH = 32, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0, parameter integer C_AXI_AWUSER_WIDTH = 1, parameter integer C_AXI_WUSER_WIDTH = 1, parameter integer C_AXI_BUSER_WIDTH = 1, parameter integer C_AXI_ARUSER_WIDTH = 1, parameter integer C_AXI_RUSER_WIDTH = 1, parameter integer C_AWPAYLOAD_WIDTH = 61, parameter integer C_WPAYLOAD_WIDTH = 73, parameter integer C_BPAYLOAD_WIDTH = 6, parameter integer C_ARPAYLOAD_WIDTH = 61, parameter integer C_RPAYLOAD_WIDTH = 69 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// // Slave Interface Write Address Ports input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid, input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen, input wire [3-1:0] s_axi_awsize, input wire [2-1:0] s_axi_awburst, input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock, input wire [4-1:0] s_axi_awcache, input wire [3-1:0] s_axi_awprot, input wire [4-1:0] s_axi_awregion, input wire [4-1:0] s_axi_awqos, input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser, // Slave Interface Write Data Ports input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid, input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata, input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, input wire s_axi_wlast, input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser, // Slave Interface Write Response Ports output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid, output wire [2-1:0] s_axi_bresp, output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser, // Slave Interface Read Address Ports input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid, input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr, input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen, input wire [3-1:0] s_axi_arsize, input wire [2-1:0] s_axi_arburst, input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock, input wire [4-1:0] s_axi_arcache, input wire [3-1:0] s_axi_arprot, input wire [4-1:0] s_axi_arregion, input wire [4-1:0] s_axi_arqos, input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser, // Slave Interface Read Data Ports output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid, output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata, output wire [2-1:0] s_axi_rresp, output wire s_axi_rlast, output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser, // payloads output wire [C_AWPAYLOAD_WIDTH-1:0] s_awpayload, output wire [C_WPAYLOAD_WIDTH-1:0] s_wpayload, input wire [C_BPAYLOAD_WIDTH-1:0] s_bpayload, output wire [C_ARPAYLOAD_WIDTH-1:0] s_arpayload, input wire [C_RPAYLOAD_WIDTH-1:0] s_rpayload ); //////////////////////////////////////////////////////////////////////////////// // Functions //////////////////////////////////////////////////////////////////////////////// `include "axi_infrastructure_v1_1_header.vh" //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// // AXI4, AXI4LITE, AXI3 packing assign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr; assign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot; assign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata; assign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb; assign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH]; assign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr; assign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot; assign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH]; assign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH]; generate if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] = s_axi_awsize; assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst; assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache; assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] = s_axi_awlen; assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] = s_axi_awlock; assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] = s_axi_awid; assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] = s_axi_awqos; assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] = s_axi_wlast; if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] = s_axi_wid; end else begin : gen_no_axi3_wid_packing end assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH]; assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] = s_axi_arsize; assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst; assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache; assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] = s_axi_arlen; assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] = s_axi_arlock; assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] = s_axi_arid; assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] = s_axi_arqos; assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH]; assign s_axi_rid = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH]; if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion; assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion; end else begin : gen_no_region_signals end if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser; assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] = s_axi_wuser; assign s_axi_buser = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH]; assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser; assign s_axi_ruser = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH]; end else begin : gen_no_user_signals assign s_axi_buser = \'b0; assign s_axi_ruser = \'b0; end end else begin : gen_axi4lite_packing assign s_axi_bid = \'b0; assign s_axi_buser = \'b0; assign s_axi_rlast = 1\'b1; assign s_axi_rid = \'b0; assign s_axi_ruser = \'b0; end endgenerate endmodule `default_nettype wire
//----------------------------------------------- // This is the simplest form of inferring the // simple/SRL(16/32)CE in a Xilinx FPGA. //----------------------------------------------- `timescale 1ns / 100ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_protocol_converter_v2_1_b2s_simple_fifo # ( parameter C_WIDTH = 8, parameter C_AWIDTH = 4, parameter C_DEPTH = 16 ) ( input wire clk, // Main System Clock (Sync FIFO) input wire rst, // FIFO Counter Reset (Clk input wire wr_en, // FIFO Write Enable (Clk) input wire rd_en, // FIFO Read Enable (Clk) input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk) output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk) output wire a_full, output wire full, // FIFO FULL Status (Clk) output wire a_empty, output wire empty // FIFO EMPTY Status (Clk) ); /////////////////////////////////////// // FIFO Local Parameters /////////////////////////////////////// localparam [C_AWIDTH-1:0] C_EMPTY = ~(0); localparam [C_AWIDTH-1:0] C_EMPTY_PRE = (0); localparam [C_AWIDTH-1:0] C_FULL = C_EMPTY-1; localparam [C_AWIDTH-1:0] C_FULL_PRE = (C_DEPTH < 8) ? C_FULL-1 : C_FULL-(C_DEPTH/8); /////////////////////////////////////// // FIFO Internal Signals /////////////////////////////////////// reg [C_WIDTH-1:0] memory [C_DEPTH-1:0]; reg [C_AWIDTH-1:0] cnt_read; // synthesis attribute MAX_FANOUT of cnt_read is 10; /////////////////////////////////////// // Main simple FIFO Array /////////////////////////////////////// always @(posedge clk) begin : BLKSRL integer i; if (wr_en) begin for (i = 0; i < C_DEPTH-1; i = i + 1) begin memory[i+1] <= memory[i]; end memory[0] <= din; end end /////////////////////////////////////// // Read Index Counter // Up/Down Counter // *** Notice that there is no *** // *** OVERRUN protection. *** /////////////////////////////////////// always @(posedge clk) begin if (rst) cnt_read <= C_EMPTY; else if ( wr_en & !rd_en) cnt_read <= cnt_read + 1\'b1; else if (!wr_en & rd_en) cnt_read <= cnt_read - 1\'b1; end /////////////////////////////////////// // Status Flags / Outputs // These could be registered, but would // increase logic in order to pre-decode // FULL/EMPTY status. /////////////////////////////////////// assign full = (cnt_read == C_FULL); assign empty = (cnt_read == C_EMPTY); assign a_full = ((cnt_read >= C_FULL_PRE) && (cnt_read != C_EMPTY)); assign a_empty = (cnt_read == C_EMPTY_PRE); assign dout = (C_DEPTH == 1) ? memory[0] : memory[cnt_read]; endmodule // axi_protocol_converter_v2_1_b2s_simple_fifo `default_nettype wire
/////////////////////////////////////////////////////////////////////////////// // // File name: axi_protocol_converter_v2_1_b2s.v // // Description: // To handle AXI4 transactions to external memory on Virtex-6 architectures // requires a bridge to convert the AXI4 transactions to the memory // controller(MC) user interface. The MC user interface has bidirectional // data path and supports data width of 256/128/64/32 bits. // The bridge is designed to allow AXI4 IP masters to communicate with // the MC user interface. // // // Specifications: // AXI4 Slave Side: // Configurable data width of 32, 64, 128, 256 // Read acceptance depth is: // Write acceptance depth is: // // Structure: // axi_protocol_converter_v2_1_b2s // WRITE_BUNDLE // aw_channel_0 // cmd_translator_0 // rd_cmd_fsm_0 // w_channel_0 // b_channel_0 // READ_BUNDLE // ar_channel_0 // cmd_translator_0 // rd_cmd_fsm_0 // r_channel_0 // /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_protocol_converter_v2_1_b2s #( parameter C_S_AXI_PROTOCOL = 0, // Width of all master and slave ID signals. // Range: >= 1. parameter integer C_AXI_ID_WIDTH = 4, parameter integer C_AXI_ADDR_WIDTH = 30, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_SUPPORTS_WRITE = 1, parameter integer C_AXI_SUPPORTS_READ = 1 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// // AXI Slave Interface // Slave Interface System Signals input wire aclk , input wire aresetn , // Slave Interface Write Address Ports input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid , input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr , input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen, input wire [2:0] s_axi_awsize , input wire [1:0] s_axi_awburst , input wire [2:0] s_axi_awprot , input wire s_axi_awvalid , output wire s_axi_awready , // Slave Interface Write Data Ports input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata , input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb , input wire s_axi_wlast , input wire s_axi_wvalid , output wire s_axi_wready , // Slave Interface Write Response Ports output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid , output wire [1:0] s_axi_bresp , output wire s_axi_bvalid , input wire s_axi_bready , // Slave Interface Read Address Ports input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid , input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr , input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen, input wire [2:0] s_axi_arsize , input wire [1:0] s_axi_arburst , input wire [2:0] s_axi_arprot , input wire s_axi_arvalid , output wire s_axi_arready , // Slave Interface Read Data Ports output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid , output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata , output wire [1:0] s_axi_rresp , output wire s_axi_rlast , output wire s_axi_rvalid , input wire s_axi_rready , // Slave Interface Write Address Ports output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr , output wire [2:0] m_axi_awprot , output wire m_axi_awvalid , input wire m_axi_awready , // Slave Interface Write Data Ports output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata , output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb , output wire m_axi_wvalid , input wire m_axi_wready , // Slave Interface Write Response Ports input wire [1:0] m_axi_bresp , input wire m_axi_bvalid , output wire m_axi_bready , // Slave Interface Read Address Ports output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr , output wire [2:0] m_axi_arprot , output wire m_axi_arvalid , input wire m_axi_arready , // Slave Interface Read Data Ports input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata , input wire [1:0] m_axi_rresp , input wire m_axi_rvalid , output wire m_axi_rready ); //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL reg areset_d1; always @(posedge aclk) areset_d1 <= ~aresetn; // AW/W/B channel internal communication wire b_push; wire [C_AXI_ID_WIDTH-1:0] b_awid; wire [7:0] b_awlen; wire b_full; wire [C_AXI_ID_WIDTH-1:0] si_rs_awid; wire [C_AXI_ADDR_WIDTH-1:0] si_rs_awaddr; wire [8-1:0] si_rs_awlen; wire [3-1:0] si_rs_awsize; wire [2-1:0] si_rs_awburst; wire [3-1:0] si_rs_awprot; wire si_rs_awvalid; wire si_rs_awready; wire [C_AXI_DATA_WIDTH-1:0] si_rs_wdata; wire [C_AXI_DATA_WIDTH/8-1:0] si_rs_wstrb; wire si_rs_wlast; wire si_rs_wvalid; wire si_rs_wready; wire [C_AXI_ID_WIDTH-1:0] si_rs_bid; wire [2-1:0] si_rs_bresp; wire si_rs_bvalid; wire si_rs_bready; wire [C_AXI_ID_WIDTH-1:0] si_rs_arid; wire [C_AXI_ADDR_WIDTH-1:0] si_rs_araddr; wire [8-1:0] si_rs_arlen; wire [3-1:0] si_rs_arsize; wire [2-1:0] si_rs_arburst; wire [3-1:0] si_rs_arprot; wire si_rs_arvalid; wire si_rs_arready; wire [C_AXI_ID_WIDTH-1:0] si_rs_rid; wire [C_AXI_DATA_WIDTH-1:0] si_rs_rdata; wire [2-1:0] si_rs_rresp; wire si_rs_rlast; wire si_rs_rvalid; wire si_rs_rready; wire [C_AXI_ADDR_WIDTH-1:0] rs_mi_awaddr; wire rs_mi_awvalid; wire rs_mi_awready; wire [C_AXI_DATA_WIDTH-1:0] rs_mi_wdata; wire [C_AXI_DATA_WIDTH/8-1:0] rs_mi_wstrb; wire rs_mi_wvalid; wire rs_mi_wready; wire [2-1:0] rs_mi_bresp; wire rs_mi_bvalid; wire rs_mi_bready; wire [C_AXI_ADDR_WIDTH-1:0] rs_mi_araddr; wire rs_mi_arvalid; wire rs_mi_arready; wire [C_AXI_DATA_WIDTH-1:0] rs_mi_rdata; wire [2-1:0] rs_mi_rresp; wire rs_mi_rvalid; wire rs_mi_rready; axi_register_slice_v2_1_axi_register_slice #( .C_AXI_PROTOCOL ( C_S_AXI_PROTOCOL ) , .C_AXI_ID_WIDTH ( C_AXI_ID_WIDTH ) , .C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) , .C_AXI_DATA_WIDTH ( C_AXI_DATA_WIDTH ) , .C_AXI_SUPPORTS_USER_SIGNALS ( 0 ) , .C_AXI_AWUSER_WIDTH ( 1 ) , .C_AXI_ARUSER_WIDTH ( 1 ) , .C_AXI_WUSER_WIDTH ( 1 ) , .C_AXI_RUSER_WIDTH ( 1 ) , .C_AXI_BUSER_WIDTH ( 1 ) , .C_REG_CONFIG_AW ( 1 ) , .C_REG_CONFIG_AR ( 1 ) , .C_REG_CONFIG_W ( 0 ) , .C_REG_CONFIG_R ( 1 ) , .C_REG_CONFIG_B ( 1 ) ) SI_REG ( .aresetn ( aresetn ) , .aclk ( aclk ) , .s_axi_awid ( s_axi_awid ) , .s_axi_awaddr ( s_axi_awaddr ) , .s_axi_awlen ( s_axi_awlen ) , .s_axi_awsize ( s_axi_awsize ) , .s_axi_awburst ( s_axi_awburst ) , .s_axi_awlock ( {((C_S_AXI_PROTOCOL == 1) ? 2 : 1){1\'b0}} ) , .s_axi_awcache ( 4\'h0 ) , .s_axi_awprot ( s_axi_awprot ) , .s_axi_awqos ( 4\'h0 ) , .s_axi_awuser ( 1\'b0 ) , .s_axi_awvalid ( s_axi_awvalid ) , .s_axi_awready ( s_axi_awready ) , .s_axi_awregion ( 4\'h0 ) , .s_axi_wid ( {C_AXI_ID_WIDTH{1\'b0}} ) , .s_axi_wdata ( s_axi_wdata ) , .s_axi_wstrb ( s_axi_wstrb ) , .s_axi_wlast ( s_axi_wlast ) , .s_axi_wuser ( 1\'b0 ) , .s_axi_wvalid ( s_axi_wvalid ) , .s_axi_wready ( s_axi_wready ) , .s_axi_bid ( s_axi_bid ) , .s_axi_bresp ( s_axi_bresp ) , .s_axi_buser ( ) , .s_axi_bvalid ( s_axi_bvalid ) , .s_axi_bready ( s_axi_bready ) , .s_axi_arid ( s_axi_arid ) , .s_axi_araddr ( s_axi_araddr ) , .s_axi_arlen ( s_axi_arlen ) , .s_axi_arsize ( s_axi_arsize ) , .s_axi_arburst ( s_axi_arburst ) , .s_axi_arlock ( {((C_S_AXI_PROTOCOL == 1) ? 2 : 1){1\'b0}} ) , .s_axi_arcache ( 4\'h0 ) , .s_axi_arprot ( s_axi_arprot ) , .s_axi_arqos ( 4\'h0 ) , .s_axi_aruser ( 1\'b0 ) , .s_axi_arvalid ( s_axi_arvalid ) , .s_axi_arready ( s_axi_arready ) , .s_axi_arregion ( 4\'h0 ) , .s_axi_rid ( s_axi_rid ) , .s_axi_rdata ( s_axi_rdata ) , .s_axi_rresp ( s_axi_rresp ) , .s_axi_rlast ( s_axi_rlast ) , .s_axi_ruser ( ) , .s_axi_rvalid ( s_axi_rvalid ) , .s_axi_rready ( s_axi_rready ) , .m_axi_awid ( si_rs_awid ) , .m_axi_awaddr ( si_rs_awaddr ) , .m_axi_awlen ( si_rs_awlen[((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] ) , .m_axi_awsize ( si_rs_awsize ) , .m_axi_awburst ( si_rs_awburst ) , .m_axi_awlock ( ) , .m_axi_awcache ( ) , .m_axi_awprot ( si_rs_awprot ) , .m_axi_awqos ( ) , .m_axi_awuser ( ) , .m_axi_awvalid ( si_rs_awvalid ) , .m_axi_awready ( si_rs_awready ) , .m_axi_awregion ( ) , .m_axi_wid ( ) , .m_axi_wdata ( si_rs_wdata ) , .m_axi_wstrb ( si_rs_wstrb ) , .m_axi_wlast ( si_rs_wlast ) , .m_axi_wuser ( ) , .m_axi_wvalid ( si_rs_wvalid ) , .m_axi_wready ( si_rs_wready ) , .m_axi_bid ( si_rs_bid ) , .m_axi_bresp ( si_rs_bresp ) , .m_axi_buser ( 1\'b0 ) , .m_axi_bvalid ( si_rs_bvalid ) , .m_axi_bready ( si_rs_bready ) , .m_axi_arid ( si_rs_arid ) , .m_axi_araddr ( si_rs_araddr ) , .m_axi_arlen ( si_rs_arlen[((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] ) , .m_axi_arsize ( si_rs_arsize ) , .m_axi_arburst ( si_rs_arburst ) , .m_axi_arlock ( ) , .m_axi_arcache ( ) , .m_axi_arprot ( si_rs_arprot ) , .m_axi_arqos ( ) , .m_axi_aruser ( ) , .m_axi_arvalid ( si_rs_arvalid ) , .m_axi_arready ( si_rs_arready ) , .m_axi_arregion ( ) , .m_axi_rid ( si_rs_rid ) , .m_axi_rdata ( si_rs_rdata ) , .m_axi_rresp ( si_rs_rresp ) , .m_axi_rlast ( si_rs_rlast ) , .m_axi_ruser ( 1\'b0 ) , .m_axi_rvalid ( si_rs_rvalid ) , .m_axi_rready ( si_rs_rready ) ); generate if (C_AXI_SUPPORTS_WRITE == 1) begin : WR axi_protocol_converter_v2_1_b2s_aw_channel # ( .C_ID_WIDTH ( C_AXI_ID_WIDTH ), .C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ) aw_channel_0 ( .clk ( aclk ) , .reset ( areset_d1 ) , .s_awid ( si_rs_awid ) , .s_awaddr ( si_rs_awaddr ) , .s_awlen ( (C_S_AXI_PROTOCOL == 1) ? {4\'h0,si_rs_awlen[3:0]} : si_rs_awlen), .s_awsize ( si_rs_awsize ) , .s_awburst ( si_rs_awburst ) , .s_awvalid ( si_rs_awvalid ) , .s_awready ( si_rs_awready ) , .m_awvalid ( rs_mi_awvalid ) , .m_awaddr ( rs_mi_awaddr ) , .m_awready ( rs_mi_awready ) , .b_push ( b_push ) , .b_awid ( b_awid ) , .b_awlen ( b_awlen ) , .b_full ( b_full ) ); axi_protocol_converter_v2_1_b2s_b_channel # ( .C_ID_WIDTH ( C_AXI_ID_WIDTH ) ) b_channel_0 ( .clk ( aclk ) , .reset ( areset_d1 ) , .s_bid ( si_rs_bid ) , .s_bresp ( si_rs_bresp ) , .s_bvalid ( si_rs_bvalid ) , .s_bready ( si_rs_bready ) , .m_bready ( rs_mi_bready ) , .m_bvalid ( rs_mi_bvalid ) , .m_bresp ( rs_mi_bresp ) , .b_push ( b_push ) , .b_awid ( b_awid ) , .b_awlen ( b_awlen ) , .b_full ( b_full ) , .b_resp_rdy ( si_rs_awready ) ); assign rs_mi_wdata = si_rs_wdata; assign rs_mi_wstrb = si_rs_wstrb; assign rs_mi_wvalid = si_rs_wvalid; assign si_rs_wready = rs_mi_wready; end else begin : NO_WR assign rs_mi_awaddr = {C_AXI_ADDR_WIDTH{1\'b0}}; assign rs_mi_awvalid = 1\'b0; assign si_rs_awready = 1\'b0; assign rs_mi_wdata = {C_AXI_DATA_WIDTH{1\'b0}}; assign rs_mi_wstrb = {C_AXI_DATA_WIDTH/8{1\'b0}}; assign rs_mi_wvalid = 1\'b0; assign si_rs_wready = 1\'b0; assign rs_mi_bready = 1\'b0; assign si_rs_bvalid = 1\'b0; assign si_rs_bresp = 2\'b00; assign si_rs_bid = {C_AXI_ID_WIDTH{1\'b0}}; end endgenerate // AR/R channel communication wire r_push ; wire [C_AXI_ID_WIDTH-1:0] r_arid ; wire r_rlast ; wire r_full ; generate if (C_AXI_SUPPORTS_READ == 1) begin : RD axi_protocol_converter_v2_1_b2s_ar_channel # ( .C_ID_WIDTH ( C_AXI_ID_WIDTH ), .C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ) ar_channel_0 ( .clk ( aclk ) , .reset ( areset_d1 ) , .s_arid ( si_rs_arid ) , .s_araddr ( si_rs_araddr ) , .s_arlen ( (C_S_AXI_PROTOCOL == 1) ? {4\'h0,si_rs_arlen[3:0]} : si_rs_arlen), .s_arsize ( si_rs_arsize ) , .s_arburst ( si_rs_arburst ) , .s_arvalid ( si_rs_arvalid ) , .s_arready ( si_rs_arready ) , .m_arvalid ( rs_mi_arvalid ) , .m_araddr ( rs_mi_araddr ) , .m_arready ( rs_mi_arready ) , .r_push ( r_push ) , .r_arid ( r_arid ) , .r_rlast ( r_rlast ) , .r_full ( r_full ) ); axi_protocol_converter_v2_1_b2s_r_channel # ( .C_ID_WIDTH ( C_AXI_ID_WIDTH ), .C_DATA_WIDTH ( C_AXI_DATA_WIDTH ) ) r_channel_0 ( .clk ( aclk ) , .reset ( areset_d1 ) , .s_rid ( si_rs_rid ) , .s_rdata ( si_rs_rdata ) , .s_rresp ( si_rs_rresp ) , .s_rlast ( si_rs_rlast ) , .s_rvalid ( si_rs_rvalid ) , .s_rready ( si_rs_rready ) , .m_rvalid ( rs_mi_rvalid ) , .m_rready ( rs_mi_rready ) , .m_rdata ( rs_mi_rdata ) , .m_rresp ( rs_mi_rresp ) , .r_push ( r_push ) , .r_full ( r_full ) , .r_arid ( r_arid ) , .r_rlast ( r_rlast ) ); end else begin : NO_RD assign rs_mi_araddr = {C_AXI_ADDR_WIDTH{1\'b0}}; assign rs_mi_arvalid = 1\'b0; assign si_rs_arready = 1\'b0; assign si_rs_rlast = 1\'b1; assign si_rs_rdata = {C_AXI_DATA_WIDTH{1\'b0}}; assign si_rs_rvalid = 1\'b0; assign si_rs_rresp = 2\'b00; assign si_rs_rid = {C_AXI_ID_WIDTH{1\'b0}}; assign rs_mi_rready = 1\'b0; end endgenerate axi_register_slice_v2_1_axi_register_slice #( .C_AXI_PROTOCOL ( 2 ) , .C_AXI_ID_WIDTH ( 1 ) , .C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) , .C_AXI_DATA_WIDTH ( C_AXI_DATA_WIDTH ) , .C_AXI_SUPPORTS_USER_SIGNALS ( 0 ) , .C_AXI_AWUSER_WIDTH ( 1 ) , .C_AXI_ARUSER_WIDTH ( 1 ) , .C_AXI_WUSER_WIDTH ( 1 ) , .C_AXI_RUSER_WIDTH ( 1 ) , .C_AXI_BUSER_WIDTH ( 1 ) , .C_REG_CONFIG_AW ( 0 ) , .C_REG_CONFIG_AR ( 0 ) , .C_REG_CONFIG_W ( 0 ) , .C_REG_CONFIG_R ( 0 ) , .C_REG_CONFIG_B ( 0 ) ) MI_REG ( .aresetn ( aresetn ) , .aclk ( aclk ) , .s_axi_awid ( 1\'b0 ) , .s_axi_awaddr ( rs_mi_awaddr ) , .s_axi_awlen ( 8\'h00 ) , .s_axi_awsize ( 3\'b000 ) , .s_axi_awburst ( 2\'b01 ) , .s_axi_awlock ( 1\'b0 ) , .s_axi_awcache ( 4\'h0 ) , .s_axi_awprot ( si_rs_awprot ) , .s_axi_awqos ( 4\'h0 ) , .s_axi_awuser ( 1\'b0 ) , .s_axi_awvalid ( rs_mi_awvalid ) , .s_axi_awready ( rs_mi_awready ) , .s_axi_awregion ( 4\'h0 ) , .s_axi_wid ( 1\'b0 ) , .s_axi_wdata ( rs_mi_wdata ) , .s_axi_wstrb ( rs_mi_wstrb ) , .s_axi_wlast ( 1\'b1 ) , .s_axi_wuser ( 1\'b0 ) , .s_axi_wvalid ( rs_mi_wvalid ) , .s_axi_wready ( rs_mi_wready ) , .s_axi_bid ( ) , .s_axi_bresp ( rs_mi_bresp ) , .s_axi_buser ( ) , .s_axi_bvalid ( rs_mi_bvalid ) , .s_axi_bready ( rs_mi_bready ) , .s_axi_arid ( 1\'b0 ) , .s_axi_araddr ( rs_mi_araddr ) , .s_axi_arlen ( 8\'h00 ) , .s_axi_arsize ( 3\'b000 ) , .s_axi_arburst ( 2\'b01 ) , .s_axi_arlock ( 1\'b0 ) , .s_axi_arcache ( 4\'h0 ) , .s_axi_arprot ( si_rs_arprot ) , .s_axi_arqos ( 4\'h0 ) , .s_axi_aruser ( 1\'b0 ) , .s_axi_arvalid ( rs_mi_arvalid ) , .s_axi_arready ( rs_mi_arready ) , .s_axi_arregion ( 4\'h0 ) , .s_axi_rid ( ) , .s_axi_rdata ( rs_mi_rdata ) , .s_axi_rresp ( rs_mi_rresp ) , .s_axi_rlast ( ) , .s_axi_ruser ( ) , .s_axi_rvalid ( rs_mi_rvalid ) , .s_axi_rready ( rs_mi_rready ) , .m_axi_awid ( ) , .m_axi_awaddr ( m_axi_awaddr ) , .m_axi_awlen ( ) , .m_axi_awsize ( ) , .m_axi_awburst ( ) , .m_axi_awlock ( ) , .m_axi_awcache ( ) , .m_axi_awprot ( m_axi_awprot ) , .m_axi_awqos ( ) , .m_axi_awuser ( ) , .m_axi_awvalid ( m_axi_awvalid ) , .m_axi_awready ( m_axi_awready ) , .m_axi_awregion ( ) , .m_axi_wid ( ) , .m_axi_wdata ( m_axi_wdata ) , .m_axi_wstrb ( m_axi_wstrb ) , .m_axi_wlast ( ) , .m_axi_wuser ( ) , .m_axi_wvalid ( m_axi_wvalid ) , .m_axi_wready ( m_axi_wready ) , .m_axi_bid ( 1\'b0 ) , .m_axi_bresp ( m_axi_bresp ) , .m_axi_buser ( 1\'b0 ) , .m_axi_bvalid ( m_axi_bvalid ) , .m_axi_bready ( m_axi_bready ) , .m_axi_arid ( ) , .m_axi_araddr ( m_axi_araddr ) , .m_axi_arlen ( ) , .m_axi_arsize ( ) , .m_axi_arburst ( ) , .m_axi_arlock ( ) , .m_axi_arcache ( ) , .m_axi_arprot ( m_axi_arprot ) , .m_axi_arqos ( ) , .m_axi_aruser ( ) , .m_axi_arvalid ( m_axi_arvalid ) , .m_axi_arready ( m_axi_arready ) , .m_axi_arregion ( ) , .m_axi_rid ( 1\'b0 ) , .m_axi_rdata ( m_axi_rdata ) , .m_axi_rresp ( m_axi_rresp ) , .m_axi_rlast ( 1\'b1 ) , .m_axi_ruser ( 1\'b0 ) , .m_axi_rvalid ( m_axi_rvalid ) , .m_axi_rready ( m_axi_rready ) ); endmodule `default_nettype wire
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: // Optimized COMPARATOR with generic_baseblocks_v2_1_carry logic. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module generic_baseblocks_v2_1_comparator_sel_mask # ( parameter C_FAMILY = "virtex6", // FPGA Family. Current version: virtex6 or spartan6. parameter integer C_DATA_WIDTH = 4 // Data width for comparator. ) ( input wire CIN, input wire S, input wire [C_DATA_WIDTH-1:0] A, input wire [C_DATA_WIDTH-1:0] B, input wire [C_DATA_WIDTH-1:0] M, input wire [C_DATA_WIDTH-1:0] V, output wire COUT ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// // Generate variable for bit vector. genvar lut_cnt; ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Bits per LUT for this architecture. localparam integer C_BITS_PER_LUT = 1; // Constants for packing levels. localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT; // localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT : C_DATA_WIDTH; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// wire [C_FIX_DATA_WIDTH-1:0] a_local; wire [C_FIX_DATA_WIDTH-1:0] b_local; wire [C_FIX_DATA_WIDTH-1:0] m_local; wire [C_FIX_DATA_WIDTH-1:0] v_local; wire [C_NUM_LUT-1:0] sel; wire [C_NUM_LUT:0] carry_local; ///////////////////////////////////////////////////////////////////////////// // ///////////////////////////////////////////////////////////////////////////// generate // Assign input to local vectors. assign carry_local[0] = CIN; // Extend input data to fit. if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}}; assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}}; assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}}; assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}}; end else begin : NO_EXTENDED_DATA assign a_local = A; assign b_local = B; assign m_local = M; assign v_local = V; end // Instantiate one generic_baseblocks_v2_1_carry and per level. for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL // Create the local select signal assign sel[lut_cnt] = ( ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) == ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1\'b0 ) ) | ( ( ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) == ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1\'b1 ) ); // Instantiate each LUT level. generic_baseblocks_v2_1_carry_and # ( .C_FAMILY(C_FAMILY) ) compare_inst ( .COUT (carry_local[lut_cnt+1]), .CIN (carry_local[lut_cnt]), .S (sel[lut_cnt]) ); end // end for lut_cnt // Assign output from local vector. assign COUT = carry_local[C_NUM_LUT]; endgenerate endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: // Optimized COMPARATOR with generic_baseblocks_v2_1_carry logic. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module generic_baseblocks_v2_1_comparator # ( parameter C_FAMILY = "virtex6", // FPGA Family. Current version: virtex6 or spartan6. parameter integer C_DATA_WIDTH = 4 // Data width for comparator. ) ( input wire CIN, input wire [C_DATA_WIDTH-1:0] A, input wire [C_DATA_WIDTH-1:0] B, output wire COUT ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// // Generate variable for bit vector. genvar bit_cnt; ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Bits per LUT for this architecture. localparam integer C_BITS_PER_LUT = 3; // Constants for packing levels. localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT; // localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT : C_DATA_WIDTH; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// wire [C_FIX_DATA_WIDTH-1:0] a_local; wire [C_FIX_DATA_WIDTH-1:0] b_local; wire [C_NUM_LUT-1:0] sel; wire [C_NUM_LUT:0] carry_local; ///////////////////////////////////////////////////////////////////////////// // ///////////////////////////////////////////////////////////////////////////// generate // Assign input to local vectors. assign carry_local[0] = CIN; // Extend input data to fit. if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}}; assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}}; end else begin : NO_EXTENDED_DATA assign a_local = A; assign b_local = B; end // Instantiate one generic_baseblocks_v2_1_carry and per level. for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL // Create the local select signal assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ); // Instantiate each LUT level. generic_baseblocks_v2_1_carry_and # ( .C_FAMILY(C_FAMILY) ) compare_inst ( .COUT (carry_local[bit_cnt+1]), .CIN (carry_local[bit_cnt]), .S (sel[bit_cnt]) ); end // end for bit_cnt // Assign output from local vector. assign COUT = carry_local[C_NUM_LUT]; endgenerate endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_reg_init.v * * Date : 2012-11 * * Description : Initialize register default values. * *****************************************************************************/ // Register default value info for chip pele_ps // This code was auto-generated by xregdb.py ver. 0.68, Thu Jul 12 10:32:25 2012 // 54 modules, 2532 registers. // ************************************************************ // Module afi0 AFI // doc version: 1.1 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( afi0__AFI_RDCHAN_CTRL, val_afi0__AFI_RDCHAN_CTRL); set_reset_data( afi0__AFI_RDCHAN_ISSUINGCAP, val_afi0__AFI_RDCHAN_ISSUINGCAP); set_reset_data( afi0__AFI_RDQOS, val_afi0__AFI_RDQOS); set_reset_data( afi0__AFI_RDDATAFIFO_LEVEL, val_afi0__AFI_RDDATAFIFO_LEVEL); set_reset_data( afi0__AFI_RDDEBUG, val_afi0__AFI_RDDEBUG); set_reset_data( afi0__AFI_WRCHAN_CTRL, val_afi0__AFI_WRCHAN_CTRL); set_reset_data( afi0__AFI_WRCHAN_ISSUINGCAP, val_afi0__AFI_WRCHAN_ISSUINGCAP); set_reset_data( afi0__AFI_WRQOS, val_afi0__AFI_WRQOS); set_reset_data( afi0__AFI_WRDATAFIFO_LEVEL, val_afi0__AFI_WRDATAFIFO_LEVEL); set_reset_data( afi0__AFI_WRDEBUG, val_afi0__AFI_WRDEBUG); // ************************************************************ // Module afi1 AFI // doc version: 1.1 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( afi1__AFI_RDCHAN_CTRL, val_afi1__AFI_RDCHAN_CTRL); set_reset_data( afi1__AFI_RDCHAN_ISSUINGCAP, val_afi1__AFI_RDCHAN_ISSUINGCAP); set_reset_data( afi1__AFI_RDQOS, val_afi1__AFI_RDQOS); set_reset_data( afi1__AFI_RDDATAFIFO_LEVEL, val_afi1__AFI_RDDATAFIFO_LEVEL); set_reset_data( afi1__AFI_RDDEBUG, val_afi1__AFI_RDDEBUG); set_reset_data( afi1__AFI_WRCHAN_CTRL, val_afi1__AFI_WRCHAN_CTRL); set_reset_data( afi1__AFI_WRCHAN_ISSUINGCAP, val_afi1__AFI_WRCHAN_ISSUINGCAP); set_reset_data( afi1__AFI_WRQOS, val_afi1__AFI_WRQOS); set_reset_data( afi1__AFI_WRDATAFIFO_LEVEL, val_afi1__AFI_WRDATAFIFO_LEVEL); set_reset_data( afi1__AFI_WRDEBUG, val_afi1__AFI_WRDEBUG); // ************************************************************ // Module afi2 AFI // doc version: 1.1 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( afi2__AFI_RDCHAN_CTRL, val_afi2__AFI_RDCHAN_CTRL); set_reset_data( afi2__AFI_RDCHAN_ISSUINGCAP, val_afi2__AFI_RDCHAN_ISSUINGCAP); set_reset_data( afi2__AFI_RDQOS, val_afi2__AFI_RDQOS); set_reset_data( afi2__AFI_RDDATAFIFO_LEVEL, val_afi2__AFI_RDDATAFIFO_LEVEL); set_reset_data( afi2__AFI_RDDEBUG, val_afi2__AFI_RDDEBUG); set_reset_data( afi2__AFI_WRCHAN_CTRL, val_afi2__AFI_WRCHAN_CTRL); set_reset_data( afi2__AFI_WRCHAN_ISSUINGCAP, val_afi2__AFI_WRCHAN_ISSUINGCAP); set_reset_data( afi2__AFI_WRQOS, val_afi2__AFI_WRQOS); set_reset_data( afi2__AFI_WRDATAFIFO_LEVEL, val_afi2__AFI_WRDATAFIFO_LEVEL); set_reset_data( afi2__AFI_WRDEBUG, val_afi2__AFI_WRDEBUG); // ************************************************************ // Module afi3 AFI // doc version: 1.1 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( afi3__AFI_RDCHAN_CTRL, val_afi3__AFI_RDCHAN_CTRL); set_reset_data( afi3__AFI_RDCHAN_ISSUINGCAP, val_afi3__AFI_RDCHAN_ISSUINGCAP); set_reset_data( afi3__AFI_RDQOS, val_afi3__AFI_RDQOS); set_reset_data( afi3__AFI_RDDATAFIFO_LEVEL, val_afi3__AFI_RDDATAFIFO_LEVEL); set_reset_data( afi3__AFI_RDDEBUG, val_afi3__AFI_RDDEBUG); set_reset_data( afi3__AFI_WRCHAN_CTRL, val_afi3__AFI_WRCHAN_CTRL); set_reset_data( afi3__AFI_WRCHAN_ISSUINGCAP, val_afi3__AFI_WRCHAN_ISSUINGCAP); set_reset_data( afi3__AFI_WRQOS, val_afi3__AFI_WRQOS); set_reset_data( afi3__AFI_WRDATAFIFO_LEVEL, val_afi3__AFI_WRDATAFIFO_LEVEL); set_reset_data( afi3__AFI_WRDEBUG, val_afi3__AFI_WRDEBUG); // ************************************************************ // Module can0 can // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( can0__SRR, val_can0__SRR); set_reset_data( can0__MSR, val_can0__MSR); set_reset_data( can0__BRPR, val_can0__BRPR); set_reset_data( can0__BTR, val_can0__BTR); set_reset_data( can0__ECR, val_can0__ECR); set_reset_data( can0__ESR, val_can0__ESR); set_reset_data( can0__SR, val_can0__SR); set_reset_data( can0__ISR, val_can0__ISR); set_reset_data( can0__IER, val_can0__IER); set_reset_data( can0__ICR, val_can0__ICR); set_reset_data( can0__TCR, val_can0__TCR); set_reset_data( can0__WIR, val_can0__WIR); set_reset_data( can0__TXFIFO_ID, val_can0__TXFIFO_ID); set_reset_data( can0__TXFIFO_DLC, val_can0__TXFIFO_DLC); set_reset_data( can0__TXFIFO_DATA1, val_can0__TXFIFO_DATA1); set_reset_data( can0__TXFIFO_DATA2, val_can0__TXFIFO_DATA2); set_reset_data( can0__TXHPB_ID, val_can0__TXHPB_ID); set_reset_data( can0__TXHPB_DLC, val_can0__TXHPB_DLC); set_reset_data( can0__TXHPB_DATA1, val_can0__TXHPB_DATA1); set_reset_data( can0__TXHPB_DATA2, val_can0__TXHPB_DATA2); set_reset_data( can0__RXFIFO_ID, val_can0__RXFIFO_ID); set_reset_data( can0__RXFIFO_DLC, val_can0__RXFIFO_DLC); set_reset_data( can0__RXFIFO_DATA1, val_can0__RXFIFO_DATA1); set_reset_data( can0__RXFIFO_DATA2, val_can0__RXFIFO_DATA2); set_reset_data( can0__AFR, val_can0__AFR); set_reset_data( can0__AFMR1, val_can0__AFMR1); set_reset_data( can0__AFIR1, val_can0__AFIR1); set_reset_data( can0__AFMR2, val_can0__AFMR2); set_reset_data( can0__AFIR2, val_can0__AFIR2); set_reset_data( can0__AFMR3, val_can0__AFMR3); set_reset_data( can0__AFIR3, val_can0__AFIR3); set_reset_data( can0__AFMR4, val_can0__AFMR4); set_reset_data( can0__AFIR4, val_can0__AFIR4); // ************************************************************ // Module can1 can // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( can1__SRR, val_can1__SRR); set_reset_data( can1__MSR, val_can1__MSR); set_reset_data( can1__BRPR, val_can1__BRPR); set_reset_data( can1__BTR, val_can1__BTR); set_reset_data( can1__ECR, val_can1__ECR); set_reset_data( can1__ESR, val_can1__ESR); set_reset_data( can1__SR, val_can1__SR); set_reset_data( can1__ISR, val_can1__ISR); set_reset_data( can1__IER, val_can1__IER); set_reset_data( can1__ICR, val_can1__ICR); set_reset_data( can1__TCR, val_can1__TCR); set_reset_data( can1__WIR, val_can1__WIR); set_reset_data( can1__TXFIFO_ID, val_can1__TXFIFO_ID); set_reset_data( can1__TXFIFO_DLC, val_can1__TXFIFO_DLC); set_reset_data( can1__TXFIFO_DATA1, val_can1__TXFIFO_DATA1); set_reset_data( can1__TXFIFO_DATA2, val_can1__TXFIFO_DATA2); set_reset_data( can1__TXHPB_ID, val_can1__TXHPB_ID); set_reset_data( can1__TXHPB_DLC, val_can1__TXHPB_DLC); set_reset_data( can1__TXHPB_DATA1, val_can1__TXHPB_DATA1); set_reset_data( can1__TXHPB_DATA2, val_can1__TXHPB_DATA2); set_reset_data( can1__RXFIFO_ID, val_can1__RXFIFO_ID); set_reset_data( can1__RXFIFO_DLC, val_can1__RXFIFO_DLC); set_reset_data( can1__RXFIFO_DATA1, val_can1__RXFIFO_DATA1); set_reset_data( can1__RXFIFO_DATA2, val_can1__RXFIFO_DATA2); set_reset_data( can1__AFR, val_can1__AFR); set_reset_data( can1__AFMR1, val_can1__AFMR1); set_reset_data( can1__AFIR1, val_can1__AFIR1); set_reset_data( can1__AFMR2, val_can1__AFMR2); set_reset_data( can1__AFIR2, val_can1__AFIR2); set_reset_data( can1__AFMR3, val_can1__AFMR3); set_reset_data( can1__AFIR3, val_can1__AFIR3); set_reset_data( can1__AFMR4, val_can1__AFMR4); set_reset_data( can1__AFIR4, val_can1__AFIR4); // ************************************************************ // Module ddrc ddrc // doc version: 1.25 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( ddrc__ddrc_ctrl, val_ddrc__ddrc_ctrl); set_reset_data( ddrc__Two_rank_cfg, val_ddrc__Two_rank_cfg); set_reset_data( ddrc__HPR_reg, val_ddrc__HPR_reg); set_reset_data( ddrc__LPR_reg, val_ddrc__LPR_reg); set_reset_data( ddrc__WR_reg, val_ddrc__WR_reg); set_reset_data( ddrc__DRAM_param_reg0, val_ddrc__DRAM_param_reg0); set_reset_data( ddrc__DRAM_param_reg1, val_ddrc__DRAM_param_reg1); set_reset_data( ddrc__DRAM_param_reg2, val_ddrc__DRAM_param_reg2); set_reset_data( ddrc__DRAM_param_reg3, val_ddrc__DRAM_param_reg3); set_reset_data( ddrc__DRAM_param_reg4, val_ddrc__DRAM_param_reg4); set_reset_data( ddrc__DRAM_init_param, val_ddrc__DRAM_init_param); set_reset_data( ddrc__DRAM_EMR_reg, val_ddrc__DRAM_EMR_reg); set_reset_data( ddrc__DRAM_EMR_MR_reg, val_ddrc__DRAM_EMR_MR_reg); set_reset_data( ddrc__DRAM_burst8_rdwr, val_ddrc__DRAM_burst8_rdwr); set_reset_data( ddrc__DRAM_disable_DQ, val_ddrc__DRAM_disable_DQ); set_reset_data( ddrc__DRAM_addr_map_bank, val_ddrc__DRAM_addr_map_bank); set_reset_data( ddrc__DRAM_addr_map_col, val_ddrc__DRAM_addr_map_col); set_reset_data( ddrc__DRAM_addr_map_row, val_ddrc__DRAM_addr_map_row); set_reset_data( ddrc__DRAM_ODT_reg, val_ddrc__DRAM_ODT_reg); set_reset_data( ddrc__phy_dbg_reg, val_ddrc__phy_dbg_reg); set_reset_data( ddrc__phy_cmd_timeout_rddata_cpt, val_ddrc__phy_cmd_timeout_rddata_cpt); set_reset_data( ddrc__mode_sts_reg, val_ddrc__mode_sts_reg); set_reset_data( ddrc__DLL_calib, val_ddrc__DLL_calib); set_reset_data( ddrc__ODT_delay_hold, val_ddrc__ODT_delay_hold); set_reset_data( ddrc__ctrl_reg1, val_ddrc__ctrl_reg1); set_reset_data( ddrc__ctrl_reg2, val_ddrc__ctrl_reg2); set_reset_data( ddrc__ctrl_reg3, val_ddrc__ctrl_reg3); set_reset_data( ddrc__ctrl_reg4, val_ddrc__ctrl_reg4); set_reset_data( ddrc__ctrl_reg5, val_ddrc__ctrl_reg5); set_reset_data( ddrc__ctrl_reg6, val_ddrc__ctrl_reg6); set_reset_data( ddrc__CHE_REFRESH_TIMER01, val_ddrc__CHE_REFRESH_TIMER01); set_reset_data( ddrc__CHE_T_ZQ, val_ddrc__CHE_T_ZQ); set_reset_data( ddrc__CHE_T_ZQ_Short_Interval_Reg, val_ddrc__CHE_T_ZQ_Short_Interval_Reg); set_reset_data( ddrc__deep_pwrdwn_reg, val_ddrc__deep_pwrdwn_reg); set_reset_data( ddrc__reg_2c, val_ddrc__reg_2c); set_reset_data( ddrc__reg_2d, val_ddrc__reg_2d); set_reset_data( ddrc__dfi_timing, val_ddrc__dfi_timing); set_reset_data( ddrc__refresh_timer_2, val_ddrc__refresh_timer_2); set_reset_data( ddrc__nc_timing, val_ddrc__nc_timing); set_reset_data( ddrc__CHE_ECC_CONTROL_REG_OFFSET, val_ddrc__CHE_ECC_CONTROL_REG_OFFSET); set_reset_data( ddrc__CHE_CORR_ECC_LOG_REG_OFFSET, val_ddrc__CHE_CORR_ECC_LOG_REG_OFFSET); set_reset_data( ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET, val_ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET); set_reset_data( ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET, val_ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET); set_reset_data( ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET, val_ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET); set_reset_data( ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET, val_ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET); set_reset_data( ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET); set_reset_data( ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET); set_reset_data( ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET); set_reset_data( ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET); set_reset_data( ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET); set_reset_data( ddrc__CHE_ECC_STATS_REG_OFFSET, val_ddrc__CHE_ECC_STATS_REG_OFFSET); set_reset_data( ddrc__ECC_scrub, val_ddrc__ECC_scrub); set_reset_data( ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET, val_ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET); set_reset_data( ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET, val_ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET); set_reset_data( ddrc__phy_rcvr_enable, val_ddrc__phy_rcvr_enable); set_reset_data( ddrc__PHY_Config0, val_ddrc__PHY_Config0); set_reset_data( ddrc__PHY_Config1, val_ddrc__PHY_Config1); set_reset_data( ddrc__PHY_Config2, val_ddrc__PHY_Config2); set_reset_data( ddrc__PHY_Config3, val_ddrc__PHY_Config3); set_reset_data( ddrc__phy_init_ratio0, val_ddrc__phy_init_ratio0); set_reset_data( ddrc__phy_init_ratio1, val_ddrc__phy_init_ratio1); set_reset_data( ddrc__phy_init_ratio2, val_ddrc__phy_init_ratio2); set_reset_data( ddrc__phy_init_ratio3, val_ddrc__phy_init_ratio3); set_reset_data( ddrc__phy_rd_dqs_cfg0, val_ddrc__phy_rd_dqs_cfg0); set_reset_data( ddrc__phy_rd_dqs_cfg1, val_ddrc__phy_rd_dqs_cfg1); set_reset_data( ddrc__phy_rd_dqs_cfg2, val_ddrc__phy_rd_dqs_cfg2); set_reset_data( ddrc__phy_rd_dqs_cfg3, val_ddrc__phy_rd_dqs_cfg3); set_reset_data( ddrc__phy_wr_dqs_cfg0, val_ddrc__phy_wr_dqs_cfg0); set_reset_data( ddrc__phy_wr_dqs_cfg1, val_ddrc__phy_wr_dqs_cfg1); set_reset_data( ddrc__phy_wr_dqs_cfg2, val_ddrc__phy_wr_dqs_cfg2); set_reset_data( ddrc__phy_wr_dqs_cfg3, val_ddrc__phy_wr_dqs_cfg3); set_reset_data( ddrc__phy_we_cfg0, val_ddrc__phy_we_cfg0); set_reset_data( ddrc__phy_we_cfg1, val_ddrc__phy_we_cfg1); set_reset_data( ddrc__phy_we_cfg2, val_ddrc__phy_we_cfg2); set_reset_data( ddrc__phy_we_cfg3, val_ddrc__phy_we_cfg3); set_reset_data( ddrc__wr_data_slv0, val_ddrc__wr_data_slv0); set_reset_data( ddrc__wr_data_slv1, val_ddrc__wr_data_slv1); set_reset_data( ddrc__wr_data_slv2, val_ddrc__wr_data_slv2); set_reset_data( ddrc__wr_data_slv3, val_ddrc__wr_data_slv3); set_reset_data( ddrc__reg_64, val_ddrc__reg_64); set_reset_data( ddrc__reg_65, val_ddrc__reg_65); set_reset_data( ddrc__reg69_6a0, val_ddrc__reg69_6a0); set_reset_data( ddrc__reg69_6a1, val_ddrc__reg69_6a1); set_reset_data( ddrc__reg6c_6d2, val_ddrc__reg6c_6d2); set_reset_data( ddrc__reg6c_6d3, val_ddrc__reg6c_6d3); set_reset_data( ddrc__reg6e_710, val_ddrc__reg6e_710); set_reset_data( ddrc__reg6e_711, val_ddrc__reg6e_711); set_reset_data( ddrc__reg6e_712, val_ddrc__reg6e_712); set_reset_data( ddrc__reg6e_713, val_ddrc__reg6e_713); set_reset_data( ddrc__phy_dll_sts0, val_ddrc__phy_dll_sts0); set_reset_data( ddrc__phy_dll_sts1, val_ddrc__phy_dll_sts1); set_reset_data( ddrc__phy_dll_sts2, val_ddrc__phy_dll_sts2); set_reset_data( ddrc__phy_dll_sts3, val_ddrc__phy_dll_sts3); set_reset_data( ddrc__dll_lock_sts, val_ddrc__dll_lock_sts); set_reset_data( ddrc__phy_ctrl_sts, val_ddrc__phy_ctrl_sts); set_reset_data( ddrc__phy_ctrl_sts_reg2, val_ddrc__phy_ctrl_sts_reg2); set_reset_data( ddrc__axi_id, val_ddrc__axi_id); set_reset_data( ddrc__page_mask, val_ddrc__page_mask); set_reset_data( ddrc__axi_priority_wr_port0, val_ddrc__axi_priority_wr_port0); set_reset_data( ddrc__axi_priority_wr_port1, val_ddrc__axi_priority_wr_port1); set_reset_data( ddrc__axi_priority_wr_port2, val_ddrc__axi_priority_wr_port2); set_reset_data( ddrc__axi_priority_wr_port3, val_ddrc__axi_priority_wr_port3); set_reset_data( ddrc__axi_priority_rd_port0, val_ddrc__axi_priority_rd_port0); set_reset_data( ddrc__axi_priority_rd_port1, val_ddrc__axi_priority_rd_port1); set_reset_data( ddrc__axi_priority_rd_port2, val_ddrc__axi_priority_rd_port2); set_reset_data( ddrc__axi_priority_rd_port3, val_ddrc__axi_priority_rd_port3); set_reset_data( ddrc__AHB_priority_cfg0, val_ddrc__AHB_priority_cfg0); set_reset_data( ddrc__AHB_priority_cfg1, val_ddrc__AHB_priority_cfg1); set_reset_data( ddrc__AHB_priority_cfg2, val_ddrc__AHB_priority_cfg2); set_reset_data( ddrc__AHB_priority_cfg3, val_ddrc__AHB_priority_cfg3); set_reset_data( ddrc__perf_mon0, val_ddrc__perf_mon0); set_reset_data( ddrc__perf_mon1, val_ddrc__perf_mon1); set_reset_data( ddrc__perf_mon2, val_ddrc__perf_mon2); set_reset_data( ddrc__perf_mon3, val_ddrc__perf_mon3); set_reset_data( ddrc__perf_mon20, val_ddrc__perf_mon20); set_reset_data( ddrc__perf_mon21, val_ddrc__perf_mon21); set_reset_data( ddrc__perf_mon22, val_ddrc__perf_mon22); set_reset_data( ddrc__perf_mon23, val_ddrc__perf_mon23); set_reset_data( ddrc__perf_mon30, val_ddrc__perf_mon30); set_reset_data( ddrc__perf_mon31, val_ddrc__perf_mon31); set_reset_data( ddrc__perf_mon32, val_ddrc__perf_mon32); set_reset_data( ddrc__perf_mon33, val_ddrc__perf_mon33); set_reset_data( ddrc__trusted_mem_cfg, val_ddrc__trusted_mem_cfg); set_reset_data( ddrc__excl_access_cfg0, val_ddrc__excl_access_cfg0); set_reset_data( ddrc__excl_access_cfg1, val_ddrc__excl_access_cfg1); set_reset_data( ddrc__excl_access_cfg2, val_ddrc__excl_access_cfg2); set_reset_data( ddrc__excl_access_cfg3, val_ddrc__excl_access_cfg3); set_reset_data( ddrc__mode_reg_read, val_ddrc__mode_reg_read); set_reset_data( ddrc__lpddr_ctrl0, val_ddrc__lpddr_ctrl0); set_reset_data( ddrc__lpddr_ctrl1, val_ddrc__lpddr_ctrl1); set_reset_data( ddrc__lpddr_ctrl2, val_ddrc__lpddr_ctrl2); set_reset_data( ddrc__lpddr_ctrl3, val_ddrc__lpddr_ctrl3); set_reset_data( ddrc__phy_wr_lvl_fsm, val_ddrc__phy_wr_lvl_fsm); set_reset_data( ddrc__phy_rd_lvl_fsm, val_ddrc__phy_rd_lvl_fsm); set_reset_data( ddrc__phy_gate_lvl_fsm, val_ddrc__phy_gate_lvl_fsm); // ************************************************************ // Module debug_axim axim // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( debug_axim__GLOBAL_CTRL, val_debug_axim__GLOBAL_CTRL); set_reset_data( debug_axim__GLOBAL_STATUS, val_debug_axim__GLOBAL_STATUS); set_reset_data( debug_axim__FILTER_CTRL, val_debug_axim__FILTER_CTRL); set_reset_data( debug_axim__TRIGGER_CTRL, val_debug_axim__TRIGGER_CTRL); set_reset_data( debug_axim__TRIGGER_STATUS, val_debug_axim__TRIGGER_STATUS); set_reset_data( debug_axim__PACKET_CTRL, val_debug_axim__PACKET_CTRL); set_reset_data( debug_axim__TOUT_CTRL, val_debug_axim__TOUT_CTRL); set_reset_data( debug_axim__TOUT_THRESH, val_debug_axim__TOUT_THRESH); set_reset_data( debug_axim__FIFO_CURRENT, val_debug_axim__FIFO_CURRENT); set_reset_data( debug_axim__FIFO_HYSTER, val_debug_axim__FIFO_HYSTER); set_reset_data( debug_axim__SYNC_CURRENT, val_debug_axim__SYNC_CURRENT); set_reset_data( debug_axim__SYNC_RELOAD, val_debug_axim__SYNC_RELOAD); set_reset_data( debug_axim__TSTMP_CURRENT, val_debug_axim__TSTMP_CURRENT); set_reset_data( debug_axim__ADDR0_MASK, val_debug_axim__ADDR0_MASK); set_reset_data( debug_axim__ADDR0_LOWER, val_debug_axim__ADDR0_LOWER); set_reset_data( debug_axim__ADDR0_UPPER, val_debug_axim__ADDR0_UPPER); set_reset_data( debug_axim__ADDR0_MISC, val_debug_axim__ADDR0_MISC); set_reset_data( debug_axim__ADDR1_MASK, val_debug_axim__ADDR1_MASK); set_reset_data( debug_axim__ADDR1_LOWER, val_debug_axim__ADDR1_LOWER); set_reset_data( debug_axim__ADDR1_UPPER, val_debug_axim__ADDR1_UPPER); set_reset_data( debug_axim__ADDR1_MISC, val_debug_axim__ADDR1_MISC); set_reset_data( debug_axim__ADDR2_MASK, val_debug_axim__ADDR2_MASK); set_reset_data( debug_axim__ADDR2_LOWER, val_debug_axim__ADDR2_LOWER); set_reset_data( debug_axim__ADDR2_UPPER, val_debug_axim__ADDR2_UPPER); set_reset_data( debug_axim__ADDR2_MISC, val_debug_axim__ADDR2_MISC); set_reset_data( debug_axim__ADDR3_MASK, val_debug_axim__ADDR3_MASK); set_reset_data( debug_axim__ADDR3_LOWER, val_debug_axim__ADDR3_LOWER); set_reset_data( debug_axim__ADDR3_UPPER, val_debug_axim__ADDR3_UPPER); set_reset_data( debug_axim__ADDR3_MISC, val_debug_axim__ADDR3_MISC); set_reset_data( debug_axim__ID0_MASK, val_debug_axim__ID0_MASK); set_reset_data( debug_axim__ID0_LOWER, val_debug_axim__ID0_LOWER); set_reset_data( debug_axim__ID0_UPPER, val_debug_axim__ID0_UPPER); set_reset_data( debug_axim__ID0_MISC, val_debug_axim__ID0_MISC); set_reset_data( debug_axim__ID1_MASK, val_debug_axim__ID1_MASK); set_reset_data( debug_axim__ID1_LOWER, val_debug_axim__ID1_LOWER); set_reset_data( debug_axim__ID1_UPPER, val_debug_axim__ID1_UPPER); set_reset_data( debug_axim__ID1_MISC, val_debug_axim__ID1_MISC); set_reset_data( debug_axim__ID2_MASK, val_debug_axim__ID2_MASK); set_reset_data( debug_axim__ID2_LOWER, val_debug_axim__ID2_LOWER); set_reset_data( debug_axim__ID2_UPPER, val_debug_axim__ID2_UPPER); set_reset_data( debug_axim__ID2_MISC, val_debug_axim__ID2_MISC); set_reset_data( debug_axim__ID3_MASK, val_debug_axim__ID3_MASK); set_reset_data( debug_axim__ID3_LOWER, val_debug_axim__ID3_LOWER); set_reset_data( debug_axim__ID3_UPPER, val_debug_axim__ID3_UPPER); set_reset_data( debug_axim__ID3_MISC, val_debug_axim__ID3_MISC); set_reset_data( debug_axim__AXI_SEL, val_debug_axim__AXI_SEL); set_reset_data( debug_axim__IT_TRIGOUT, val_debug_axim__IT_TRIGOUT); set_reset_data( debug_axim__IT_TRIGOUTACK, val_debug_axim__IT_TRIGOUTACK); set_reset_data( debug_axim__IT_TRIGIN, val_debug_axim__IT_TRIGIN); set_reset_data( debug_axim__IT_TRIGINACK, val_debug_axim__IT_TRIGINACK); set_reset_data( debug_axim__IT_ATBDATA, val_debug_axim__IT_ATBDATA); set_reset_data( debug_axim__IT_ATBSTATUS, val_debug_axim__IT_ATBSTATUS); set_reset_data( debug_axim__IT_ATBCTRL1, val_debug_axim__IT_ATBCTRL1); set_reset_data( debug_axim__IT_ATBCTRL0, val_debug_axim__IT_ATBCTRL0); set_reset_data( debug_axim__IT_CTRL, val_debug_axim__IT_CTRL); set_reset_data( debug_axim__CLAIM_SET, val_debug_axim__CLAIM_SET); set_reset_data( debug_axim__CLAIM_CLEAR, val_debug_axim__CLAIM_CLEAR); set_reset_data( debug_axim__LOCK_ACCESS, val_debug_axim__LOCK_ACCESS); set_reset_data( debug_axim__LOCK_STATUS, val_debug_axim__LOCK_STATUS); set_reset_data( debug_axim__AUTH_STATUS, val_debug_axim__AUTH_STATUS); set_reset_data( debug_axim__DEV_ID, val_debug_axim__DEV_ID); set_reset_data( debug_axim__DEV_TYPE, val_debug_axim__DEV_TYPE); set_reset_data( debug_axim__PERIPHID4, val_debug_axim__PERIPHID4); set_reset_data( debug_axim__PERIPHID5, val_debug_axim__PERIPHID5); set_reset_data( debug_axim__PERIPHID6, val_debug_axim__PERIPHID6); set_reset_data( debug_axim__PERIPHID7, val_debug_axim__PERIPHID7); set_reset_data( debug_axim__PERIPHID0, val_debug_axim__PERIPHID0); set_reset_data( debug_axim__PERIPHID1, val_debug_axim__PERIPHID1); set_reset_data( debug_axim__PERIPHID2, val_debug_axim__PERIPHID2); set_reset_data( debug_axim__PERIPHID3, val_debug_axim__PERIPHID3); set_reset_data( debug_axim__COMPID0, val_debug_axim__COMPID0); set_reset_data( debug_axim__COMPID1, val_debug_axim__COMPID1); set_reset_data( debug_axim__COMPID2, val_debug_axim__COMPID2); set_reset_data( debug_axim__COMPID3, val_debug_axim__COMPID3); // ************************************************************ // Module debug_cpu_cti0 cti // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( debug_cpu_cti0__CTICONTROL, val_debug_cpu_cti0__CTICONTROL); set_reset_data( debug_cpu_cti0__CTIINTACK, val_debug_cpu_cti0__CTIINTACK); set_reset_data( debug_cpu_cti0__CTIAPPSET, val_debug_cpu_cti0__CTIAPPSET); set_reset_data( debug_cpu_cti0__CTIAPPCLEAR, val_debug_cpu_cti0__CTIAPPCLEAR); set_reset_data( debug_cpu_cti0__CTIAPPPULSE, val_debug_cpu_cti0__CTIAPPPULSE); set_reset_data( debug_cpu_cti0__CTIINEN0, val_debug_cpu_cti0__CTIINEN0); set_reset_data( debug_cpu_cti0__CTIINEN1, val_debug_cpu_cti0__CTIINEN1); set_reset_data( debug_cpu_cti0__CTIINEN2, val_debug_cpu_cti0__CTIINEN2); set_reset_data( debug_cpu_cti0__CTIINEN3, val_debug_cpu_cti0__CTIINEN3); set_reset_data( debug_cpu_cti0__CTIINEN4, val_debug_cpu_cti0__CTIINEN4); set_reset_data( debug_cpu_cti0__CTIINEN5, val_debug_cpu_cti0__CTIINEN5); set_reset_data( debug_cpu_cti0__CTIINEN6, val_debug_cpu_cti0__CTIINEN6); set_reset_data( debug_cpu_cti0__CTIINEN7, val_debug_cpu_cti0__CTIINEN7); set_reset_data( debug_cpu_cti0__CTIOUTEN0, val_debug_cpu_cti0__CTIOUTEN0); set_reset_data( debug_cpu_cti0__CTIOUTEN1, val_debug_cpu_cti0__CTIOUTEN1); set_reset_data( debug_cpu_cti0__CTIOUTEN2, val_debug_cpu_cti0__CTIOUTEN2); set_reset_data( debug_cpu_cti0__CTIOUTEN3, val_debug_cpu_cti0__CTIOUTEN3); set_reset_data( debug_cpu_cti0__CTIOUTEN4, val_debug_cpu_cti0__CTIOUTEN4); set_reset_data( debug_cpu_cti0__CTIOUTEN5, val_debug_cpu_cti0__CTIOUTEN5); set_reset_data( debug_cpu_cti0__CTIOUTEN6, val_debug_cpu_cti0__CTIOUTEN6); set_reset_data( debug_cpu_cti0__CTIOUTEN7, val_debug_cpu_cti0__CTIOUTEN7); set_reset_data( debug_cpu_cti0__CTITRIGINSTATUS, val_debug_cpu_cti0__CTITRIGINSTATUS); set_reset_data( debug_cpu_cti0__CTITRIGOUTSTATUS, val_debug_cpu_cti0__CTITRIGOUTSTATUS); set_reset_data( debug_cpu_cti0__CTICHINSTATUS, val_debug_cpu_cti0__CTICHINSTATUS); set_reset_data( debug_cpu_cti0__CTICHOUTSTATUS, val_debug_cpu_cti0__CTICHOUTSTATUS); set_reset_data( debug_cpu_cti0__CTIGATE, val_debug_cpu_cti0__CTIGATE); set_reset_data( debug_cpu_cti0__ASICCTL, val_debug_cpu_cti0__ASICCTL); set_reset_data( debug_cpu_cti0__ITCHINACK, val_debug_cpu_cti0__ITCHINACK); set_reset_data( debug_cpu_cti0__ITTRIGINACK, val_debug_cpu_cti0__ITTRIGINACK); set_reset_data( debug_cpu_cti0__ITCHOUT, val_debug_cpu_cti0__ITCHOUT); set_reset_data( debug_cpu_cti0__ITTRIGOUT, val_debug_cpu_cti0__ITTRIGOUT); set_reset_data( debug_cpu_cti0__ITCHOUTACK, val_debug_cpu_cti0__ITCHOUTACK); set_reset_data( debug_cpu_cti0__ITTRIGOUTACK, val_debug_cpu_cti0__ITTRIGOUTACK); set_reset_data( debug_cpu_cti0__ITCHIN, val_debug_cpu_cti0__ITCHIN); set_reset_data( debug_cpu_cti0__ITTRIGIN, val_debug_cpu_cti0__ITTRIGIN); set_reset_data( debug_cpu_cti0__ITCTRL, val_debug_cpu_cti0__ITCTRL); set_reset_data( debug_cpu_cti0__CTSR, val_debug_cpu_cti0__CTSR); set_reset_data( debug_cpu_cti0__CTCR, val_debug_cpu_cti0__CTCR); set_reset_data( debug_cpu_cti0__LAR, val_debug_cpu_cti0__LAR); set_reset_data( debug_cpu_cti0__LSR, val_debug_cpu_cti0__LSR); set_reset_data( debug_cpu_cti0__ASR, val_debug_cpu_cti0__ASR); set_reset_data( debug_cpu_cti0__DEVID, val_debug_cpu_cti0__DEVID); set_reset_data( debug_cpu_cti0__DTIR, val_debug_cpu_cti0__DTIR); set_reset_data( debug_cpu_cti0__PERIPHID4, val_debug_cpu_cti0__PERIPHID4); set_reset_data( debug_cpu_cti0__PERIPHID5, val_debug_cpu_cti0__PERIPHID5); set_reset_data( debug_cpu_cti0__PERIPHID6, val_debug_cpu_cti0__PERIPHID6); set_reset_data( debug_cpu_cti0__PERIPHID7, val_debug_cpu_cti0__PERIPHID7); set_reset_data( debug_cpu_cti0__PERIPHID0, val_debug_cpu_cti0__PERIPHID0); set_reset_data( debug_cpu_cti0__PERIPHID1, val_debug_cpu_cti0__PERIPHID1); set_reset_data( debug_cpu_cti0__PERIPHID2, val_debug_cpu_cti0__PERIPHID2); set_reset_data( debug_cpu_cti0__PERIPHID3, val_debug_cpu_cti0__PERIPHID3); set_reset_data( debug_cpu_cti0__COMPID0, val_debug_cpu_cti0__COMPID0); set_reset_data( debug_cpu_cti0__COMPID1, val_debug_cpu_cti0__COMPID1); set_reset_data( debug_cpu_cti0__COMPID2, val_debug_cpu_cti0__COMPID2); set_reset_data( debug_cpu_cti0__COMPID3, val_debug_cpu_cti0__COMPID3); // ************************************************************ // Module debug_cpu_cti1 cti // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( debug_cpu_cti1__CTICONTROL, val_debug_cpu_cti1__CTICONTROL); set_reset_data( debug_cpu_cti1__CTIINTACK, val_debug_cpu_cti1__CTIINTACK); set_reset_data( debug_cpu_cti1__CTIAPPSET, val_debug_cpu_cti1__CTIAPPSET); set_reset_data( debug_cpu_cti1__CTIAPPCLEAR, val_debug_cpu_cti1__CTIAPPCLEAR); set_reset_data( debug_cpu_cti1__CTIAPPPULSE, val_debug_cpu_cti1__CTIAPPPULSE); set_reset_data( debug_cpu_cti1__CTIINEN0, val_debug_cpu_cti1__CTIINEN0); set_reset_data( debug_cpu_cti1__CTIINEN1, val_debug_cpu_cti1__CTIINEN1); set_reset_data( debug_cpu_cti1__CTIINEN2, val_debug_cpu_cti1__CTIINEN2); set_reset_data( debug_cpu_cti1__CTIINEN3, val_debug_cpu_cti1__CTIINEN3); set_reset_data( debug_cpu_cti1__CTIINEN4, val_debug_cpu_cti1__CTIINEN4); set_reset_data( debug_cpu_cti1__CTIINEN5, val_debug_cpu_cti1__CTIINEN5); set_reset_data( debug_cpu_cti1__CTIINEN6, val_debug_cpu_cti1__CTIINEN6); set_reset_data( debug_cpu_cti1__CTIINEN7, val_debug_cpu_cti1__CTIINEN7); set_reset_data( debug_cpu_cti1__CTIOUTEN0, val_debug_cpu_cti1__CTIOUTEN0); set_reset_data( debug_cpu_cti1__CTIOUTEN1, val_debug_cpu_cti1__CTIOUTEN1); set_reset_data( debug_cpu_cti1__CTIOUTEN2, val_debug_cpu_cti1__CTIOUTEN2); set_reset_data( debug_cpu_cti1__CTIOUTEN3, val_debug_cpu_cti1__CTIOUTEN3); set_reset_data( debug_cpu_cti1__CTIOUTEN4, val_debug_cpu_cti1__CTIOUTEN4); set_reset_data( debug_cpu_cti1__CTIOUTEN5, val_debug_cpu_cti1__CTIOUTEN5); set_reset_data( debug_cpu_cti1__CTIOUTEN6, val_debug_cpu_cti1__CTIOUTEN6); set_reset_data( debug_cpu_cti1__CTIOUTEN7, val_debug_cpu_cti1__CTIOUTEN7); set_reset_data( debug_cpu_cti1__CTITRIGINSTATUS, val_debug_cpu_cti1__CTITRIGINSTATUS); set_reset_data( debug_cpu_cti1__CTITRIGOUTSTATUS, val_debug_cpu_cti1__CTITRIGOUTSTATUS); set_reset_data( debug_cpu_cti1__CTICHINSTATUS, val_debug_cpu_cti1__CTICHINSTATUS); set_reset_data( debug_cpu_cti1__CTICHOUTSTATUS, val_debug_cpu_cti1__CTICHOUTSTATUS); set_reset_data( debug_cpu_cti1__CTIGATE, val_debug_cpu_cti1__CTIGATE); set_reset_data( debug_cpu_cti1__ASICCTL, val_debug_cpu_cti1__ASICCTL); set_reset_data( debug_cpu_cti1__ITCHINACK, val_debug_cpu_cti1__ITCHINACK); set_reset_data( debug_cpu_cti1__ITTRIGINACK, val_debug_cpu_cti1__ITTRIGINACK); set_reset_data( debug_cpu_cti1__ITCHOUT, val_debug_cpu_cti1__ITCHOUT); set_reset_data( debug_cpu_cti1__ITTRIGOUT, val_debug_cpu_cti1__ITTRIGOUT); set_reset_data( debug_cpu_cti1__ITCHOUTACK, val_debug_cpu_cti1__ITCHOUTACK); set_reset_data( debug_cpu_cti1__ITTRIGOUTACK, val_debug_cpu_cti1__ITTRIGOUTACK); set_reset_data( debug_cpu_cti1__ITCHIN, val_debug_cpu_cti1__ITCHIN); set_reset_data( debug_cpu_cti1__ITTRIGIN, val_debug_cpu_cti1__ITTRIGIN); set_reset_data( debug_cpu_cti1__ITCTRL, val_debug_cpu_cti1__ITCTRL); set_reset_data( debug_cpu_cti1__CTSR, val_debug_cpu_cti1__CTSR); set_reset_data( debug_cpu_cti1__CTCR, val_debug_cpu_cti1__CTCR); set_reset_data( debug_cpu_cti1__LAR, val_debug_cpu_cti1__LAR); set_reset_data( debug_cpu_cti1__LSR, val_debug_cpu_cti1__LSR); set_reset_data( debug_cpu_cti1__ASR, val_debug_cpu_cti1__ASR); set_reset_data( debug_cpu_cti1__DEVID, val_debug_cpu_cti1__DEVID); set_reset_data( debug_cpu_cti1__DTIR, val_debug_cpu_cti1__DTIR); set_reset_data( debug_cpu_cti1__PERIPHID4, val_debug_cpu_cti1__PERIPHID4); set_reset_data( debug_cpu_cti1__PERIPHID5, val_debug_cpu_cti1__PERIPHID5); set_reset_data( debug_cpu_cti1__PERIPHID6, val_debug_cpu_cti1__PERIPHID6); set_reset_data( debug_cpu_cti1__PERIPHID7, val_debug_cpu_cti1__PERIPHID7); set_reset_data( debug_cpu_cti1__PERIPHID0, val_debug_cpu_cti1__PERIPHID0); set_reset_data( debug_cpu_cti1__PERIPHID1, val_debug_cpu_cti1__PERIPHID1); set_reset_data( debug_cpu_cti1__PERIPHID2, val_debug_cpu_cti1__PERIPHID2); set_reset_data( debug_cpu_cti1__PERIPHID3, val_debug_cpu_cti1__PERIPHID3); set_reset_data( debug_cpu_cti1__COMPID0, val_debug_cpu_cti1__COMPID0); set_reset_data( debug_cpu_cti1__COMPID1, val_debug_cpu_cti1__COMPID1); set_reset_data( debug_cpu_cti1__COMPID2, val_debug_cpu_cti1__COMPID2); set_reset_data( debug_cpu_cti1__COMPID3, val_debug_cpu_cti1__COMPID3); // ************************************************************ // Module debug_cpu_pmu0 cortexa9_pmu // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( debug_cpu_pmu0__PMXEVCNTR0, val_debug_cpu_pmu0__PMXEVCNTR0); set_reset_data( debug_cpu_pmu0__PMXEVCNTR1, val_debug_cpu_pmu0__PMXEVCNTR1); set_reset_data( debug_cpu_pmu0__PMXEVCNTR2, val_debug_cpu_pmu0__PMXEVCNTR2); set_reset_data( debug_cpu_pmu0__PMXEVCNTR3, val_debug_cpu_pmu0__PMXEVCNTR3); set_reset_data( debug_cpu_pmu0__PMXEVCNTR4, val_debug_cpu_pmu0__PMXEVCNTR4); set_reset_data( debug_cpu_pmu0__PMXEVCNTR5, val_debug_cpu_pmu0__PMXEVCNTR5); set_reset_data( debug_cpu_pmu0__PMCCNTR, val_debug_cpu_pmu0__PMCCNTR); set_reset_data( debug_cpu_pmu0__PMXEVTYPER0, val_debug_cpu_pmu0__PMXEVTYPER0); set_reset_data( debug_cpu_pmu0__PMXEVTYPER1, val_debug_cpu_pmu0__PMXEVTYPER1); set_reset_data( debug_cpu_pmu0__PMXEVTYPER2, val_debug_cpu_pmu0__PMXEVTYPER2); set_reset_data( debug_cpu_pmu0__PMXEVTYPER3, val_debug_cpu_pmu0__PMXEVTYPER3); set_reset_data( debug_cpu_pmu0__PMXEVTYPER4, val_debug_cpu_pmu0__PMXEVTYPER4); set_reset_data( debug_cpu_pmu0__PMXEVTYPER5, val_debug_cpu_pmu0__PMXEVTYPER5); set_reset_data( debug_cpu_pmu0__PMCNTENSET, val_debug_cpu_pmu0__PMCNTENSET); set_reset_data( debug_cpu_pmu0__PMCNTENCLR, val_debug_cpu_pmu0__PMCNTENCLR); set_reset_data( debug_cpu_pmu0__PMINTENSET, val_debug_cpu_pmu0__PMINTENSET); set_reset_data( debug_cpu_pmu0__PMINTENCLR, val_debug_cpu_pmu0__PMINTENCLR); set_reset_data( debug_cpu_pmu0__PMOVSR, val_debug_cpu_pmu0__PMOVSR); set_reset_data( debug_cpu_pmu0__PMSWINC, val_debug_cpu_pmu0__PMSWINC); set_reset_data( debug_cpu_pmu0__PMCR, val_debug_cpu_pmu0__PMCR); set_reset_data( debug_cpu_pmu0__PMUSERENR, val_debug_cpu_pmu0__PMUSERENR); // ************************************************************ // Module debug_cpu_pmu1 cortexa9_pmu // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( debug_cpu_pmu1__PMXEVCNTR0, val_debug_cpu_pmu1__PMXEVCNTR0); set_reset_data( debug_cpu_pmu1__PMXEVCNTR1, val_debug_cpu_pmu1__PMXEVCNTR1); set_reset_data( debug_cpu_pmu1__PMXEVCNTR2, val_debug_cpu_pmu1__PMXEVCNTR2); set_reset_data( debug_cpu_pmu1__PMXEVCNTR3, val_debug_cpu_pmu1__PMXEVCNTR3); set_reset_data( debug_cpu_pmu1__PMXEVCNTR4, val_debug_cpu_pmu1__PMXEVCNTR4); set_reset_data( debug_cpu_pmu1__PMXEVCNTR5, val_debug_cpu_pmu1__PMXEVCNTR5); set_reset_data( debug_cpu_pmu1__PMCCNTR, val_debug_cpu_pmu1__PMCCNTR); set_reset_data( debug_cpu_pmu1__PMXEVTYPER0, val_debug_cpu_pmu1__PMXEVTYPER0); set_reset_data( debug_cpu_pmu1__PMXEVTYPER1, val_debug_cpu_pmu1__PMXEVTYPER1); set_reset_data( debug_cpu_pmu1__PMXEVTYPER2, val_debug_cpu_pmu1__PMXEVTYPER2); set_reset_data( debug_cpu_pmu1__PMXEVTYPER3, val_debug_cpu_pmu1__PMXEVTYPER3); set_reset_data( debug_cpu_pmu1__PMXEVTYPER4, val_debug_cpu_pmu1__PMXEVTYPER4); set_reset_data( debug_cpu_pmu1__PMXEVTYPER5, val_debug_cpu_pmu1__PMXEVTYPER5); set_reset_data( debug_cpu_pmu1__PMCNTENSET, val_debug_cpu_pmu1__PMCNTENSET); set_reset_data( debug_cpu_pmu1__PMCNTENCLR, val_debug_cpu_pmu1__PMCNTENCLR); set_reset_data( debug_cpu_pmu1__PMINTENSET, val_debug_cpu_pmu1__PMINTENSET); set_reset_data( debug_cpu_pmu1__PMINTENCLR, val_debug_cpu_pmu1__PMINTENCLR); set_reset_data( debug_cpu_pmu1__PMOVSR, val_debug_cpu_pmu1__PMOVSR); set_reset_data( debug_cpu_pmu1__PMSWINC, val_debug_cpu_pmu1__PMSWINC); set_reset_data( debug_cpu_pmu1__PMCR, val_debug_cpu_pmu1__PMCR); set_reset_data( debug_cpu_pmu1__PMUSERENR, val_debug_cpu_pmu1__PMUSERENR); // ************************************************************ // Module debug_cpu_ptm0 ptm // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( debug_cpu_ptm0__ETMCR, val_debug_cpu_ptm0__ETMCR); set_reset_data( debug_cpu_ptm0__ETMCCR, val_debug_cpu_ptm0__ETMCCR); set_reset_data( debug_cpu_ptm0__ETMTRIGGER, val_debug_cpu_ptm0__ETMTRIGGER); set_reset_data( debug_cpu_ptm0__ETMSR, val_debug_cpu_ptm0__ETMSR); set_reset_data( debug_cpu_ptm0__ETMSCR, val_debug_cpu_ptm0__ETMSCR); set_reset_data( debug_cpu_ptm0__ETMTSSCR, val_debug_cpu_ptm0__ETMTSSCR); set_reset_data( debug_cpu_ptm0__ETMTECR1, val_debug_cpu_ptm0__ETMTECR1); set_reset_data( debug_cpu_ptm0__ETMACVR1, val_debug_cpu_ptm0__ETMACVR1); set_reset_data( debug_cpu_ptm0__ETMACVR2, val_debug_cpu_ptm0__ETMACVR2); set_reset_data( debug_cpu_ptm0__ETMACVR3, val_debug_cpu_ptm0__ETMACVR3); set_reset_data( debug_cpu_ptm0__ETMACVR4, val_debug_cpu_ptm0__ETMACVR4); set_reset_data( debug_cpu_ptm0__ETMACVR5, val_debug_cpu_ptm0__ETMACVR5); set_reset_data( debug_cpu_ptm0__ETMACVR6, val_debug_cpu_ptm0__ETMACVR6); set_reset_data( debug_cpu_ptm0__ETMACVR7, val_debug_cpu_ptm0__ETMACVR7); set_reset_data( debug_cpu_ptm0__ETMACVR8, val_debug_cpu_ptm0__ETMACVR8); set_reset_data( debug_cpu_ptm0__ETMACTR1, val_debug_cpu_ptm0__ETMACTR1); set_reset_data( debug_cpu_ptm0__ETMACTR2, val_debug_cpu_ptm0__ETMACTR2); set_reset_data( debug_cpu_ptm0__ETMACTR3, val_debug_cpu_ptm0__ETMACTR3); set_reset_data( debug_cpu_ptm0__ETMACTR4, val_debug_cpu_ptm0__ETMACTR4); set_reset_data( debug_cpu_ptm0__ETMACTR5, val_debug_cpu_ptm0__ETMACTR5); set_reset_data( debug_cpu_ptm0__ETMACTR6, val_debug_cpu_ptm0__ETMACTR6); set_reset_data( debug_cpu_ptm0__ETMACTR7, val_debug_cpu_ptm0__ETMACTR7); set_reset_data( debug_cpu_ptm0__ETMACTR8, val_debug_cpu_ptm0__ETMACTR8); set_reset_data( debug_cpu_ptm0__ETMCNTRLDVR1, val_debug_cpu_ptm0__ETMCNTRLDVR1); set_reset_data( debug_cpu_ptm0__ETMCNTRLDVR2, val_debug_cpu_ptm0__ETMCNTRLDVR2); set_reset_data( debug_cpu_ptm0__ETMCNTENR1, val_debug_cpu_ptm0__ETMCNTENR1); set_reset_data( debug_cpu_ptm0__ETMCNTENR2, val_debug_cpu_ptm0__ETMCNTENR2); set_reset_data( debug_cpu_ptm0__ETMCNTRLDEVR1, val_debug_cpu_ptm0__ETMCNTRLDEVR1); set_reset_data( debug_cpu_ptm0__ETMCNTRLDEVR2, val_debug_cpu_ptm0__ETMCNTRLDEVR2); set_reset_data( debug_cpu_ptm0__ETMCNTVR1, val_debug_cpu_ptm0__ETMCNTVR1); set_reset_data( debug_cpu_ptm0__ETMCNTVR2, val_debug_cpu_ptm0__ETMCNTVR2); set_reset_data( debug_cpu_ptm0__ETMSQ12EVR, val_debug_cpu_ptm0__ETMSQ12EVR); set_reset_data( debug_cpu_ptm0__ETMSQ21EVR, val_debug_cpu_ptm0__ETMSQ21EVR); set_reset_data( debug_cpu_ptm0__ETMSQ23EVR, val_debug_cpu_ptm0__ETMSQ23EVR); set_reset_data( debug_cpu_ptm0__ETMSQ31EVR, val_debug_cpu_ptm0__ETMSQ31EVR); set_reset_data( debug_cpu_ptm0__ETMSQ32EVR, val_debug_cpu_ptm0__ETMSQ32EVR); set_reset_data( debug_cpu_ptm0__ETMSQ13EVR, val_debug_cpu_ptm0__ETMSQ13EVR); set_reset_data( debug_cpu_ptm0__ETMSQR, val_debug_cpu_ptm0__ETMSQR); set_reset_data( debug_cpu_ptm0__ETMEXTOUTEVR1, val_debug_cpu_ptm0__ETMEXTOUTEVR1); set_reset_data( debug_cpu_ptm0__ETMEXTOUTEVR2, val_debug_cpu_ptm0__ETMEXTOUTEVR2); set_reset_data( debug_cpu_ptm0__ETMCIDCVR1, val_debug_cpu_ptm0__ETMCIDCVR1); set_reset_data( debug_cpu_ptm0__ETMCIDCMR, val_debug_cpu_ptm0__ETMCIDCMR); set_reset_data( debug_cpu_ptm0__ETMSYNCFR, val_debug_cpu_ptm0__ETMSYNCFR); set_reset_data( debug_cpu_ptm0__ETMIDR, val_debug_cpu_ptm0__ETMIDR); set_reset_data( debug_cpu_ptm0__ETMCCER, val_debug_cpu_ptm0__ETMCCER); set_reset_data( debug_cpu_ptm0__ETMEXTINSELR, val_debug_cpu_ptm0__ETMEXTINSELR); set_reset_data( debug_cpu_ptm0__ETMAUXCR, val_debug_cpu_ptm0__ETMAUXCR); set_reset_data( debug_cpu_ptm0__ETMTRACEIDR, val_debug_cpu_ptm0__ETMTRACEIDR); set_reset_data( debug_cpu_ptm0__OSLSR, val_debug_cpu_ptm0__OSLSR); set_reset_data( debug_cpu_ptm0__ETMPDSR, val_debug_cpu_ptm0__ETMPDSR); set_reset_data( debug_cpu_ptm0__ITMISCOUT, val_debug_cpu_ptm0__ITMISCOUT); set_reset_data( debug_cpu_ptm0__ITMISCIN, val_debug_cpu_ptm0__ITMISCIN); set_reset_data( debug_cpu_ptm0__ITTRIGGER, val_debug_cpu_ptm0__ITTRIGGER); set_reset_data( debug_cpu_ptm0__ITATBDATA0, val_debug_cpu_ptm0__ITATBDATA0); set_reset_data( debug_cpu_ptm0__ITATBCTR2, val_debug_cpu_ptm0__ITATBCTR2); set_reset_data( debug_cpu_ptm0__ITATBID, val_debug_cpu_ptm0__ITATBID); set_reset_data( debug_cpu_ptm0__ITATBCTR0, val_debug_cpu_ptm0__ITATBCTR0); set_reset_data( debug_cpu_ptm0__ETMITCTRL, val_debug_cpu_ptm0__ETMITCTRL); set_reset_data( debug_cpu_ptm0__CTSR, val_debug_cpu_ptm0__CTSR); set_reset_data( debug_cpu_ptm0__CTCR, val_debug_cpu_ptm0__CTCR); set_reset_data( debug_cpu_ptm0__LAR, val_debug_cpu_ptm0__LAR); set_reset_data( debug_cpu_ptm0__LSR, val_debug_cpu_ptm0__LSR); set_reset_data( debug_cpu_ptm0__ASR, val_debug_cpu_ptm0__ASR); set_reset_data( debug_cpu_ptm0__DEVID, val_debug_cpu_ptm0__DEVID); set_reset_data( debug_cpu_ptm0__DTIR, val_debug_cpu_ptm0__DTIR); set_reset_data( debug_cpu_ptm0__PERIPHID4, val_debug_cpu_ptm0__PERIPHID4); set_reset_data( debug_cpu_ptm0__PERIPHID5, val_debug_cpu_ptm0__PERIPHID5); set_reset_data( debug_cpu_ptm0__PERIPHID6, val_debug_cpu_ptm0__PERIPHID6); set_reset_data( debug_cpu_ptm0__PERIPHID7, val_debug_cpu_ptm0__PERIPHID7); set_reset_data( debug_cpu_ptm0__PERIPHID0, val_debug_cpu_ptm0__PERIPHID0); set_reset_data( debug_cpu_ptm0__PERIPHID1, val_debug_cpu_ptm0__PERIPHID1); set_reset_data( debug_cpu_ptm0__PERIPHID2, val_debug_cpu_ptm0__PERIPHID2); set_reset_data( debug_cpu_ptm0__PERIPHID3, val_debug_cpu_ptm0__PERIPHID3); set_reset_data( debug_cpu_ptm0__COMPID0, val_debug_cpu_ptm0__COMPID0); set_reset_data( debug_cpu_ptm0__COMPID1, val_debug_cpu_ptm0__COMPID1); set_reset_data( debug_cpu_ptm0__COMPID2, val_debug_cpu_ptm0__COMPID2); set_reset_data( debug_cpu_ptm0__COMPID3, val_debug_cpu_ptm0__COMPID3); // ************************************************************ // Module debug_cpu_ptm1 ptm // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( debug_cpu_ptm1__ETMCR, val_debug_cpu_ptm1__ETMCR); set_reset_data( debug_cpu_ptm1__ETMCCR, val_debug_cpu_ptm1__ETMCCR); set_reset_data( debug_cpu_ptm1__ETMTRIGGER, val_debug_cpu_ptm1__ETMTRIGGER); set_reset_data( debug_cpu_ptm1__ETMSR, val_debug_cpu_ptm1__ETMSR); set_reset_data( debug_cpu_ptm1__ETMSCR, val_debug_cpu_ptm1__ETMSCR); set_reset_data( debug_cpu_ptm1__ETMTSSCR, val_debug_cpu_ptm1__ETMTSSCR); set_reset_data( debug_cpu_ptm1__ETMTECR1, val_debug_cpu_ptm1__ETMTECR1); set_reset_data( debug_cpu_ptm1__ETMACVR1, val_debug_cpu_ptm1__ETMACVR1); set_reset_data( debug_cpu_ptm1__ETMACVR2, val_debug_cpu_ptm1__ETMACVR2); set_reset_data( debug_cpu_ptm1__ETMACVR3, val_debug_cpu_ptm1__ETMACVR3); set_reset_data( debug_cpu_ptm1__ETMACVR4, val_debug_cpu_ptm1__ETMACVR4); set_reset_data( debug_cpu_ptm1__ETMACVR5, val_debug_cpu_ptm1__ETMACVR5); set_reset_data( debug_cpu_ptm1__ETMACVR6, val_debug_cpu_ptm1__ETMACVR6); set_reset_data( debug_cpu_ptm1__ETMACVR7, val_debug_cpu_ptm1__ETMACVR7); set_reset_data( debug_cpu_ptm1__ETMACVR8, val_debug_cpu_ptm1__ETMACVR8); set_reset_data( debug_cpu_ptm1__ETMACTR1, val_debug_cpu_ptm1__ETMACTR1); set_reset_data( debug_cpu_ptm1__ETMACTR2, val_debug_cpu_ptm1__ETMACTR2); set_reset_data( debug_cpu_ptm1__ETMACTR3, val_debug_cpu_ptm1__ETMACTR3); set_reset_data( debug_cpu_ptm1__ETMACTR4, val_debug_cpu_ptm1__ETMACTR4); set_reset_data( debug_cpu_ptm1__ETMACTR5, val_debug_cpu_ptm1__ETMACTR5); set_reset_data( debug_cpu_ptm1__ETMACTR6, val_debug_cpu_ptm1__ETMACTR6); set_reset_data( debug_cpu_ptm1__ETMACTR7, val_debug_cpu_ptm1__ETMACTR7); set_reset_data( debug_cpu_ptm1__ETMACTR8, val_debug_cpu_ptm1__ETMACTR8); set_reset_data( debug_cpu_ptm1__ETMCNTRLDVR1, val_debug_cpu_ptm1__ETMCNTRLDVR1); set_reset_data( debug_cpu_ptm1__ETMCNTRLDVR2, val_debug_cpu_ptm1__ETMCNTRLDVR2); set_reset_data( debug_cpu_ptm1__ETMCNTENR1, val_debug_cpu_ptm1__ETMCNTENR1); set_reset_data( debug_cpu_ptm1__ETMCNTENR2, val_debug_cpu_ptm1__ETMCNTENR2); set_reset_data( debug_cpu_ptm1__ETMCNTRLDEVR1, val_debug_cpu_ptm1__ETMCNTRLDEVR1); set_reset_data( debug_cpu_ptm1__ETMCNTRLDEVR2, val_debug_cpu_ptm1__ETMCNTRLDEVR2); set_reset_data( debug_cpu_ptm1__ETMCNTVR1, val_debug_cpu_ptm1__ETMCNTVR1); set_reset_data( debug_cpu_ptm1__ETMCNTVR2, val_debug_cpu_ptm1__ETMCNTVR2); set_reset_data( debug_cpu_ptm1__ETMSQ12EVR, val_debug_cpu_ptm1__ETMSQ12EVR); set_reset_data( debug_cpu_ptm1__ETMSQ21EVR, val_debug_cpu_ptm1__ETMSQ21EVR); set_reset_data( debug_cpu_ptm1__ETMSQ23EVR, val_debug_cpu_ptm1__ETMSQ23EVR); set_reset_data( debug_cpu_ptm1__ETMSQ31EVR, val_debug_cpu_ptm1__ETMSQ31EVR); set_reset_data( debug_cpu_ptm1__ETMSQ32EVR, val_debug_cpu_ptm1__ETMSQ32EVR); set_reset_data( debug_cpu_ptm1__ETMSQ13EVR, val_debug_cpu_ptm1__ETMSQ13EVR); set_reset_data( debug_cpu_ptm1__ETMSQR, val_debug_cpu_ptm1__ETMSQR); set_reset_data( debug_cpu_ptm1__ETMEXTOUTEVR1, val_debug_cpu_ptm1__ETMEXTOUTEVR1); set_reset_data( debug_cpu_ptm1__ETMEXTOUTEVR2, val_debug_cpu_ptm1__ETMEXTOUTEVR2); set_reset_data( debug_cpu_ptm1__ETMCIDCVR1, val_debug_cpu_ptm1__ETMCIDCVR1); set_reset_data( debug_cpu_ptm1__ETMCIDCMR, val_debug_cpu_ptm1__ETMCIDCMR); set_reset_data( debug_cpu_ptm1__ETMSYNCFR, val_debug_cpu_ptm1__ETMSYNCFR); set_reset_data( debug_cpu_ptm1__ETMIDR, val_debug_cpu_ptm1__ETMIDR); set_reset_data( debug_cpu_ptm1__ETMCCER, val_debug_cpu_ptm1__ETMCCER); set_reset_data( debug_cpu_ptm1__ETMEXTINSELR, val_debug_cpu_ptm1__ETMEXTINSELR); set_reset_data( debug_cpu_ptm1__ETMAUXCR, val_debug_cpu_ptm1__ETMAUXCR); set_reset_data( debug_cpu_ptm1__ETMTRACEIDR, val_debug_cpu_ptm1__ETMTRACEIDR); set_reset_data( debug_cpu_ptm1__OSLSR, val_debug_cpu_ptm1__OSLSR); set_reset_data( debug_cpu_ptm1__ETMPDSR, val_debug_cpu_ptm1__ETMPDSR); set_reset_data( debug_cpu_ptm1__ITMISCOUT, val_debug_cpu_ptm1__ITMISCOUT); set_reset_data( debug_cpu_ptm1__ITMISCIN, val_debug_cpu_ptm1__ITMISCIN); set_reset_data( debug_cpu_ptm1__ITTRIGGER, val_debug_cpu_ptm1__ITTRIGGER); set_reset_data( debug_cpu_ptm1__ITATBDATA0, val_debug_cpu_ptm1__ITATBDATA0); set_reset_data( debug_cpu_ptm1__ITATBCTR2, val_debug_cpu_ptm1__ITATBCTR2); set_reset_data( debug_cpu_ptm1__ITATBID, val_debug_cpu_ptm1__ITATBID); set_reset_data( debug_cpu_ptm1__ITATBCTR0, val_debug_cpu_ptm1__ITATBCTR0); set_reset_data( debug_cpu_ptm1__ETMITCTRL, val_debug_cpu_ptm1__ETMITCTRL); set_reset_data( debug_cpu_ptm1__CTSR, val_debug_cpu_ptm1__CTSR); set_reset_data( debug_cpu_ptm1__CTCR, val_debug_cpu_ptm1__CTCR); set_reset_data( debug_cpu_ptm1__LAR, val_debug_cpu_ptm1__LAR); set_reset_data( debug_cpu_ptm1__LSR, val_debug_cpu_ptm1__LSR); set_reset_data( debug_cpu_ptm1__ASR, val_debug_cpu_ptm1__ASR); set_reset_data( debug_cpu_ptm1__DEVID, val_debug_cpu_ptm1__DEVID); set_reset_data( debug_cpu_ptm1__DTIR, val_debug_cpu_ptm1__DTIR); set_reset_data( debug_cpu_ptm1__PERIPHID4, val_debug_cpu_ptm1__PERIPHID4); set_reset_data( debug_cpu_ptm1__PERIPHID5, val_debug_cpu_ptm1__PERIPHID5); set_reset_data( debug_cpu_ptm1__PERIPHID6, val_debug_cpu_ptm1__PERIPHID6); set_reset_data( debug_cpu_ptm1__PERIPHID7, val_debug_cpu_ptm1__PERIPHID7); set_reset_data( debug_cpu_ptm1__PERIPHID0, val_debug_cpu_ptm1__PERIPHID0); set_reset_data( debug_cpu_ptm1__PERIPHID1, val_debug_cpu_ptm1__PERIPHID1); set_reset_data( debug_cpu_ptm1__PERIPHID2, val_debug_cpu_ptm1__PERIPHID2); set_reset_data( debug_cpu_ptm1__PERIPHID3, val_debug_cpu_ptm1__PERIPHID3); set_reset_data( debug_cpu_ptm1__COMPID0, val_debug_cpu_ptm1__COMPID0); set_reset_data( debug_cpu_ptm1__COMPID1, val_debug_cpu_ptm1__COMPID1); set_reset_data( debug_cpu_ptm1__COMPID2, val_debug_cpu_ptm1__COMPID2); set_reset_data( debug_cpu_ptm1__COMPID3, val_debug_cpu_ptm1__COMPID3); // ************************************************************ // Module debug_cti_axim cti // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( debug_cti_axim__CTICONTROL, val_debug_cti_axim__CTICONTROL); set_reset_data( debug_cti_axim__CTIINTACK, val_debug_cti_axim__CTIINTACK); set_reset_data( debug_cti_axim__CTIAPPSET, val_debug_cti_axim__CTIAPPSET); set_reset_data( debug_cti_axim__CTIAPPCLEAR, val_debug_cti_axim__CTIAPPCLEAR); set_reset_data( debug_cti_axim__CTIAPPPULSE, val_debug_cti_axim__CTIAPPPULSE); set_reset_data( debug_cti_axim__CTIINEN0, val_debug_cti_axim__CTIINEN0); set_reset_data( debug_cti_axim__CTIINEN1, val_debug_cti_axim__CTIINEN1); set_reset_data( debug_cti_axim__CTIINEN2, val_debug_cti_axim__CTIINEN2); set_reset_data( debug_cti_axim__CTIINEN3, val_debug_cti_axim__CTIINEN3); set_reset_data( debug_cti_axim__CTIINEN4, val_debug_cti_axim__CTIINEN4); set_reset_data( debug_cti_axim__CTIINEN5, val_debug_cti_axim__CTIINEN5); set_reset_data( debug_cti_axim__CTIINEN6, val_debug_cti_axim__CTIINEN6); set_reset_data( debug_cti_axim__CTIINEN7, val_debug_cti_axim__CTIINEN7); set_reset_data( debug_cti_axim__CTIOUTEN0, val_debug_cti_axim__CTIOUTEN0); set_reset_data( debug_cti_axim__CTIOUTEN1, val_debug_cti_axim__CTIOUTEN1); set_reset_data( debug_cti_axim__CTIOUTEN2, val_debug_cti_axim__CTIOUTEN2); set_reset_data( debug_cti_axim__CTIOUTEN3, val_debug_cti_axim__CTIOUTEN3); set_reset_data( debug_cti_axim__CTIOUTEN4, val_debug_cti_axim__CTIOUTEN4); set_reset_data( debug_cti_axim__CTIOUTEN5, val_debug_cti_axim__CTIOUTEN5); set_reset_data( debug_cti_axim__CTIOUTEN6, val_debug_cti_axim__CTIOUTEN6); set_reset_data( debug_cti_axim__CTIOUTEN7, val_debug_cti_axim__CTIOUTEN7); set_reset_data( debug_cti_axim__CTITRIGINSTATUS, val_debug_cti_axim__CTITRIGINSTATUS); set_reset_data( debug_cti_axim__CTITRIGOUTSTATUS, val_debug_cti_axim__CTITRIGOUTSTATUS); set_reset_data( debug_cti_axim__CTICHINSTATUS, val_debug_cti_axim__CTICHINSTATUS); set_reset_data( debug_cti_axim__CTICHOUTSTATUS, val_debug_cti_axim__CTICHOUTSTATUS); set_reset_data( debug_cti_axim__CTIGATE, val_debug_cti_axim__CTIGATE); set_reset_data( debug_cti_axim__ASICCTL, val_debug_cti_axim__ASICCTL); set_reset_data( debug_cti_axim__ITCHINACK, val_debug_cti_axim__ITCHINACK); set_reset_data( debug_cti_axim__ITTRIGINACK, val_debug_cti_axim__ITTRIGINACK); set_reset_data( debug_cti_axim__ITCHOUT, val_debug_cti_axim__ITCHOUT); set_reset_data( debug_cti_axim__ITTRIGOUT, val_debug_cti_axim__ITTRIGOUT); set_reset_data( debug_cti_axim__ITCHOUTACK, val_debug_cti_axim__ITCHOUTACK); set_reset_data( debug_cti_axim__ITTRIGOUTACK, val_debug_cti_axim__ITTRIGOUTACK); set_reset_data( debug_cti_axim__ITCHIN, val_debug_cti_axim__ITCHIN); set_reset_data( debug_cti_axim__ITTRIGIN, val_debug_cti_axim__ITTRIGIN); set_reset_data( debug_cti_axim__ITCTRL, val_debug_cti_axim__ITCTRL); set_reset_data( debug_cti_axim__CTSR, val_debug_cti_axim__CTSR); set_reset_data( debug_cti_axim__CTCR, val_debug_cti_axim__CTCR); set_reset_data( debug_cti_axim__LAR, val_debug_cti_axim__LAR); set_reset_data( debug_cti_axim__LSR, val_debug_cti_axim__LSR); set_reset_data( debug_cti_axim__ASR, val_debug_cti_axim__ASR); set_reset_data( debug_cti_axim__DEVID, val_debug_cti_axim__DEVID); set_reset_data( debug_cti_axim__DTIR, val_debug_cti_axim__DTIR); set_reset_data( debug_cti_axim__PERIPHID4, val_debug_cti_axim__PERIPHID4); set_reset_data( debug_cti_axim__PERIPHID5, val_debug_cti_axim__PERIPHID5); set_reset_data( debug_cti_axim__PERIPHID6, val_debug_cti_axim__PERIPHID6); set_reset_data( debug_cti_axim__PERIPHID7, val_debug_cti_axim__PERIPHID7); set_reset_data( debug_cti_axim__PERIPHID0, val_debug_cti_axim__PERIPHID0); set_reset_data( debug_cti_axim__PERIPHID1, val_debug_cti_axim__PERIPHID1); set_reset_data( debug_cti_axim__PERIPHID2, val_debug_cti_axim__PERIPHID2); set_reset_data( debug_cti_axim__PERIPHID3, val_debug_cti_axim__PERIPHID3); set_reset_data( debug_cti_axim__COMPID0, val_debug_cti_axim__COMPID0); set_reset_data( debug_cti_axim__COMPID1, val_debug_cti_axim__COMPID1); set_reset_data( debug_cti_axim__COMPID2, val_debug_cti_axim__COMPID2); set_reset_data( debug_cti_axim__COMPID3, val_debug_cti_axim__COMPID3); // ************************************************************ // Module debug_cti_etb_tpiu cti // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( debug_cti_etb_tpiu__CTICONTROL, val_debug_cti_etb_tpiu__CTICONTROL); set_reset_data( debug_cti_etb_tpiu__CTIINTACK, val_debug_cti_etb_tpiu__CTIINTACK); set_reset_data( debug_cti_etb_tpiu__CTIAPPSET, val_debug_cti_etb_tpiu__CTIAPPSET); set_reset_data( debug_cti_etb_tpiu__CTIAPPCLEAR, val_debug_cti_etb_tpiu__CTIAPPCLEAR); set_reset_data( debug_cti_etb_tpiu__CTIAPPPULSE, val_debug_cti_etb_tpiu__CTIAPPPULSE); set_reset_data( debug_cti_etb_tpiu__CTIINEN0, val_debug_cti_etb_tpiu__CTIINEN0); set_reset_data( debug_cti_etb_tpiu__CTIINEN1, val_debug_cti_etb_tpiu__CTIINEN1); set_reset_data( debug_cti_etb_tpiu__CTIINEN2, val_debug_cti_etb_tpiu__CTIINEN2); set_reset_data( debug_cti_etb_tpiu__CTIINEN3, val_debug_cti_etb_tpiu__CTIINEN3); set_reset_data( debug_cti_etb_tpiu__CTIINEN4, val_debug_cti_etb_tpiu__CTIINEN4); set_reset_data( debug_cti_etb_tpiu__CTIINEN5, val_debug_cti_etb_tpiu__CTIINEN5); set_reset_data( debug_cti_etb_tpiu__CTIINEN6, val_debug_cti_etb_tpiu__CTIINEN6); set_reset_data( debug_cti_etb_tpiu__CTIINEN7, val_debug_cti_etb_tpiu__CTIINEN7); set_reset_data( debug_cti_etb_tpiu__CTIOUTEN0, val_debug_cti_etb_tpiu__CTIOUTEN0); set_reset_data( debug_cti_etb_tpiu__CTIOUTEN1, val_debug_cti_etb_tpiu__CTIOUTEN1); set_reset_data( debug_cti_etb_tpiu__CTIOUTEN2, val_debug_cti_etb_tpiu__CTIOUTEN2); set_reset_data( debug_cti_etb_tpiu__CTIOUTEN3, val_debug_cti_etb_tpiu__CTIOUTEN3); set_reset_data( debug_cti_etb_tpiu__CTIOUTEN4, val_debug_cti_etb_tpiu__CTIOUTEN4); set_reset_data( debug_cti_etb_tpiu__CTIOUTEN5, val_debug_cti_etb_tpiu__CTIOUTEN5); set_reset_data( debug_cti_etb_tpiu__CTIOUTEN6, val_debug_cti_etb_tpiu__CTIOUTEN6); set_reset_data( debug_cti_etb_tpiu__CTIOUTEN7, val_debug_cti_etb_tpiu__CTIOUTEN7); set_reset_data( debug_cti_etb_tpiu__CTITRIGINSTATUS, val_debug_cti_etb_tpiu__CTITRIGINSTATUS); set_reset_data( debug_cti_etb_tpiu__CTITRIGOUTSTATUS, val_debug_cti_etb_tpiu__CTITRIGOUTSTATUS); set_reset_data( debug_cti_etb_tpiu__CTICHINSTATUS, val_debug_cti_etb_tpiu__CTICHINSTATUS); set_reset_data( debug_cti_etb_tpiu__CTICHOUTSTATUS, val_debug_cti_etb_tpiu__CTICHOUTSTATUS); set_reset_data( debug_cti_etb_tpiu__CTIGATE, val_debug_cti_etb_tpiu__CTIGATE); set_reset_data( debug_cti_etb_tpiu__ASICCTL, val_debug_cti_etb_tpiu__ASICCTL); set_reset_data( debug_cti_etb_tpiu__ITCHINACK, val_debug_cti_etb_tpiu__ITCHINACK); set_reset_data( debug_cti_etb_tpiu__ITTRIGINACK, val_debug_cti_etb_tpiu__ITTRIGINACK); set_reset_data( debug_cti_etb_tpiu__ITCHOUT, val_debug_cti_etb_tpiu__ITCHOUT); set_reset_data( debug_cti_etb_tpiu__ITTRIGOUT, val_debug_cti_etb_tpiu__ITTRIGOUT); set_reset_data( debug_cti_etb_tpiu__ITCHOUTACK, val_debug_cti_etb_tpiu__ITCHOUTACK); set_reset_data( debug_cti_etb_tpiu__ITTRIGOUTACK, val_debug_cti_etb_tpiu__ITTRIGOUTACK); set_reset_data( debug_cti_etb_tpiu__ITCHIN, val_debug_cti_etb_tpiu__ITCHIN); set_reset_data( debug_cti_etb_tpiu__ITTRIGIN, val_debug_cti_etb_tpiu__ITTRIGIN); set_reset_data( debug_cti_etb_tpiu__ITCTRL, val_debug_cti_etb_tpiu__ITCTRL); set_reset_data( debug_cti_etb_tpiu__CTSR, val_debug_cti_etb_tpiu__CTSR); set_reset_data( debug_cti_etb_tpiu__CTCR, val_debug_cti_etb_tpiu__CTCR); set_reset_data( debug_cti_etb_tpiu__LAR, val_debug_cti_etb_tpiu__LAR); set_reset_data( debug_cti_etb_tpiu__LSR, val_debug_cti_etb_tpiu__LSR); set_reset_data( debug_cti_etb_tpiu__ASR, val_debug_cti_etb_tpiu__ASR); set_reset_data( debug_cti_etb_tpiu__DEVID, val_debug_cti_etb_tpiu__DEVID); set_reset_data( debug_cti_etb_tpiu__DTIR, val_debug_cti_etb_tpiu__DTIR); set_reset_data( debug_cti_etb_tpiu__PERIPHID4, val_debug_cti_etb_tpiu__PERIPHID4); set_reset_data( debug_cti_etb_tpiu__PERIPHID5, val_debug_cti_etb_tpiu__PERIPHID5); set_reset_data( debug_cti_etb_tpiu__PERIPHID6, val_debug_cti_etb_tpiu__PERIPHID6); set_reset_data( debug_cti_etb_tpiu__PERIPHID7, val_debug_cti_etb_tpiu__PERIPHID7); set_reset_data( debug_cti_etb_tpiu__PERIPHID0, val_debug_cti_etb_tpiu__PERIPHID0); set_reset_data( debug_cti_etb_tpiu__PERIPHID1, val_debug_cti_etb_tpiu__PERIPHID1); set_reset_data( debug_cti_etb_tpiu__PERIPHID2, val_debug_cti_etb_tpiu__PERIPHID2); set_reset_data( debug_cti_etb_tpiu__PERIPHID3, val_debug_cti_etb_tpiu__PERIPHID3); set_reset_data( debug_cti_etb_tpiu__COMPID0, val_debug_cti_etb_tpiu__COMPID0); set_reset_data( debug_cti_etb_tpiu__COMPID1, val_debug_cti_etb_tpiu__COMPID1); set_reset_data( debug_cti_etb_tpiu__COMPID2, val_debug_cti_etb_tpiu__COMPID2); set_reset_data( debug_cti_etb_tpiu__COMPID3, val_debug_cti_etb_tpiu__COMPID3); // ************************************************************ // Module debug_cti_ftm cti // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( debug_cti_ftm__CTICONTROL, val_debug_cti_ftm__CTICONTROL); set_reset_data( debug_cti_ftm__CTIINTACK, val_debug_cti_ftm__CTIINTACK); set_reset_data( debug_cti_ftm__CTIAPPSET, val_debug_cti_ftm__CTIAPPSET); set_reset_data( debug_cti_ftm__CTIAPPCLEAR, val_debug_cti_ftm__CTIAPPCLEAR); set_reset_data( debug_cti_ftm__CTIAPPPULSE, val_debug_cti_ftm__CTIAPPPULSE); set_reset_data( debug_cti_ftm__CTIINEN0, val_debug_cti_ftm__CTIINEN0); set_reset_data( debug_cti_ftm__CTIINEN1, val_debug_cti_ftm__CTIINEN1); set_reset_data( debug_cti_ftm__CTIINEN2, val_debug_cti_ftm__CTIINEN2); set_reset_data( debug_cti_ftm__CTIINEN3, val_debug_cti_ftm__CTIINEN3); set_reset_data( debug_cti_ftm__CTIINEN4, val_debug_cti_ftm__CTIINEN4); set_reset_data( debug_cti_ftm__CTIINEN5, val_debug_cti_ftm__CTIINEN5); set_reset_data( debug_cti_ftm__CTIINEN6, val_debug_cti_ftm__CTIINEN6); set_reset_data( debug_cti_ftm__CTIINEN7, val_debug_cti_ftm__CTIINEN7); set_reset_data( debug_cti_ftm__CTIOUTEN0, val_debug_cti_ftm__CTIOUTEN0); set_reset_data( debug_cti_ftm__CTIOUTEN1, val_debug_cti_ftm__CTIOUTEN1); set_reset_data( debug_cti_ftm__CTIOUTEN2, val_debug_cti_ftm__CTIOUTEN2); set_reset_data( debug_cti_ftm__CTIOUTEN3, val_debug_cti_ftm__CTIOUTEN3); set_reset_data( debug_cti_ftm__CTIOUTEN4, val_debug_cti_ftm__CTIOUTEN4); set_reset_data( debug_cti_ftm__CTIOUTEN5, val_debug_cti_ftm__CTIOUTEN5); set_reset_data( debug_cti_ftm__CTIOUTEN6, val_debug_cti_ftm__CTIOUTEN6); set_reset_data( debug_cti_ftm__CTIOUTEN7, val_debug_cti_ftm__CTIOUTEN7); set_reset_data( debug_cti_ftm__CTITRIGINSTATUS, val_debug_cti_ftm__CTITRIGINSTATUS); set_reset_data( debug_cti_ftm__CTITRIGOUTSTATUS, val_debug_cti_ftm__CTITRIGOUTSTATUS); set_reset_data( debug_cti_ftm__CTICHINSTATUS, val_debug_cti_ftm__CTICHINSTATUS); set_reset_data( debug_cti_ftm__CTICHOUTSTATUS, val_debug_cti_ftm__CTICHOUTSTATUS); set_reset_data( debug_cti_ftm__CTIGATE, val_debug_cti_ftm__CTIGATE); set_reset_data( debug_cti_ftm__ASICCTL, val_debug_cti_ftm__ASICCTL); set_reset_data( debug_cti_ftm__ITCHINACK, val_debug_cti_ftm__ITCHINACK); set_reset_data( debug_cti_ftm__ITTRIGINACK, val_debug_cti_ftm__ITTRIGINACK); set_reset_data( debug_cti_ftm__ITCHOUT, val_debug_cti_ftm__ITCHOUT); set_reset_data( debug_cti_ftm__ITTRIGOUT, val_debug_cti_ftm__ITTRIGOUT); set_reset_data( debug_cti_ftm__ITCHOUTACK, val_debug_cti_ftm__ITCHOUTACK); set_reset_data( debug_cti_ftm__ITTRIGOUTACK, val_debug_cti_ftm__ITTRIGOUTACK); set_reset_data( debug_cti_ftm__ITCHIN, val_debug_cti_ftm__ITCHIN); set_reset_data( debug_cti_ftm__ITTRIGIN, val_debug_cti_ftm__ITTRIGIN); set_reset_data( debug_cti_ftm__ITCTRL, val_debug_cti_ftm__ITCTRL); set_reset_data( debug_cti_ftm__CTSR, val_debug_cti_ftm__CTSR); set_reset_data( debug_cti_ftm__CTCR, val_debug_cti_ftm__CTCR); set_reset_data( debug_cti_ftm__LAR, val_debug_cti_ftm__LAR); set_reset_data( debug_cti_ftm__LSR, val_debug_cti_ftm__LSR); set_reset_data( debug_cti_ftm__ASR, val_debug_cti_ftm__ASR); set_reset_data( debug_cti_ftm__DEVID, val_debug_cti_ftm__DEVID); set_reset_data( debug_cti_ftm__DTIR, val_debug_cti_ftm__DTIR); set_reset_data( debug_cti_ftm__PERIPHID4, val_debug_cti_ftm__PERIPHID4); set_reset_data( debug_cti_ftm__PERIPHID5, val_debug_cti_ftm__PERIPHID5); set_reset_data( debug_cti_ftm__PERIPHID6, val_debug_cti_ftm__PERIPHID6); set_reset_data( debug_cti_ftm__PERIPHID7, val_debug_cti_ftm__PERIPHID7); set_reset_data( debug_cti_ftm__PERIPHID0, val_debug_cti_ftm__PERIPHID0); set_reset_data( debug_cti_ftm__PERIPHID1, val_debug_cti_ftm__PERIPHID1); set_reset_data( debug_cti_ftm__PERIPHID2, val_debug_cti_ftm__PERIPHID2); set_reset_data( debug_cti_ftm__PERIPHID3, val_debug_cti_ftm__PERIPHID3); set_reset_data( debug_cti_ftm__COMPID0, val_debug_cti_ftm__COMPID0); set_reset_data( debug_cti_ftm__COMPID1, val_debug_cti_ftm__COMPID1); set_reset_data( debug_cti_ftm__COMPID2, val_debug_cti_ftm__COMPID2); set_reset_data( debug_cti_ftm__COMPID3, val_debug_cti_ftm__COMPID3); // ************************************************************ // Module debug_dap_rom dap // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( debug_dap_rom__ROMENTRY00, val_debug_dap_rom__ROMENTRY00); set_reset_data( debug_dap_rom__ROMENTRY01, val_debug_dap_rom__ROMENTRY01); set_reset_data( debug_dap_rom__ROMENTRY02, val_debug_dap_rom__ROMENTRY02); set_reset_data( debug_dap_rom__ROMENTRY03, val_debug_dap_rom__ROMENTRY03); set_reset_data( debug_dap_rom__ROMENTRY04, val_debug_dap_rom__ROMENTRY04); set_reset_data( debug_dap_rom__ROMENTRY05, val_debug_dap_rom__ROMENTRY05); set_reset_data( debug_dap_rom__ROMENTRY06, val_debug_dap_rom__ROMENTRY06); set_reset_data( debug_dap_rom__ROMENTRY07, val_debug_dap_rom__ROMENTRY07); set_reset_data( debug_dap_rom__ROMENTRY08, val_debug_dap_rom__ROMENTRY08); set_reset_data( debug_dap_rom__ROMENTRY09, val_debug_dap_rom__ROMENTRY09); set_reset_data( debug_dap_rom__ROMENTRY10, val_debug_dap_rom__ROMENTRY10); set_reset_data( debug_dap_rom__ROMENTRY11, val_debug_dap_rom__ROMENTRY11); set_reset_data( debug_dap_rom__ROMENTRY12, val_debug_dap_rom__ROMENTRY12); set_reset_data( debug_dap_rom__ROMENTRY13, val_debug_dap_rom__ROMENTRY13); set_reset_data( debug_dap_rom__ROMENTRY14, val_debug_dap_rom__ROMENTRY14); set_reset_data( debug_dap_rom__ROMENTRY15, val_debug_dap_rom__ROMENTRY15); set_reset_data( debug_dap_rom__PERIPHID4, val_debug_dap_rom__PERIPHID4); set_reset_data( debug_dap_rom__PERIPHID5, val_debug_dap_rom__PERIPHID5); set_reset_data( debug_dap_rom__PERIPHID6, val_debug_dap_rom__PERIPHID6); set_reset_data( debug_dap_rom__PERIPHID7, val_debug_dap_rom__PERIPHID7); set_reset_data( debug_dap_rom__PERIPHID0, val_debug_dap_rom__PERIPHID0); set_reset_data( debug_dap_rom__PERIPHID1, val_debug_dap_rom__PERIPHID1); set_reset_data( debug_dap_rom__PERIPHID2, val_debug_dap_rom__PERIPHID2); set_reset_data( debug_dap_rom__PERIPHID3, val_debug_dap_rom__PERIPHID3); set_reset_data( debug_dap_rom__COMPID0, val_debug_dap_rom__COMPID0); set_reset_data( debug_dap_rom__COMPID1, val_debug_dap_rom__COMPID1); set_reset_data( debug_dap_rom__COMPID2, val_debug_dap_rom__COMPID2); set_reset_data( debug_dap_rom__COMPID3, val_debug_dap_rom__COMPID3); // ************************************************************ // Module debug_etb etb // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( debug_etb__RDP, val_debug_etb__RDP); set_reset_data( debug_etb__STS, val_debug_etb__STS); set_reset_data( debug_etb__RRD, val_debug_etb__RRD); set_reset_data( debug_etb__RRP, val_debug_etb__RRP); set_reset_data( debug_etb__RWP, val_debug_etb__RWP); set_reset_data( debug_etb__TRG, val_debug_etb__TRG); set_reset_data( debug_etb__CTL, val_debug_etb__CTL); set_reset_data( debug_etb__RWD, val_debug_etb__RWD); set_reset_data( debug_etb__FFSR, val_debug_etb__FFSR); set_reset_data( debug_etb__FFCR, val_debug_etb__FFCR); set_reset_data( debug_etb__ITMISCOP0, val_debug_etb__ITMISCOP0); set_reset_data( debug_etb__ITTRFLINACK, val_debug_etb__ITTRFLINACK); set_reset_data( debug_etb__ITTRFLIN, val_debug_etb__ITTRFLIN); set_reset_data( debug_etb__ITATBDATA0, val_debug_etb__ITATBDATA0); set_reset_data( debug_etb__ITATBCTR2, val_debug_etb__ITATBCTR2); set_reset_data( debug_etb__ITATBCTR1, val_debug_etb__ITATBCTR1); set_reset_data( debug_etb__ITATBCTR0, val_debug_etb__ITATBCTR0); set_reset_data( debug_etb__IMCR, val_debug_etb__IMCR); set_reset_data( debug_etb__CTSR, val_debug_etb__CTSR); set_reset_data( debug_etb__CTCR, val_debug_etb__CTCR); set_reset_data( debug_etb__LAR, val_debug_etb__LAR); set_reset_data( debug_etb__LSR, val_debug_etb__LSR); set_reset_data( debug_etb__ASR, val_debug_etb__ASR); set_reset_data( debug_etb__DEVID, val_debug_etb__DEVID); set_reset_data( debug_etb__DTIR, val_debug_etb__DTIR); set_reset_data( debug_etb__PERIPHID4, val_debug_etb__PERIPHID4); set_reset_data( debug_etb__PERIPHID5, val_debug_etb__PERIPHID5); set_reset_data( debug_etb__PERIPHID6, val_debug_etb__PERIPHID6); set_reset_data( debug_etb__PERIPHID7, val_debug_etb__PERIPHID7); set_reset_data( debug_etb__PERIPHID0, val_debug_etb__PERIPHID0); set_reset_data( debug_etb__PERIPHID1, val_debug_etb__PERIPHID1); set_reset_data( debug_etb__PERIPHID2, val_debug_etb__PERIPHID2); set_reset_data( debug_etb__PERIPHID3, val_debug_etb__PERIPHID3); set_reset_data( debug_etb__COMPID0, val_debug_etb__COMPID0); set_reset_data( debug_etb__COMPID1, val_debug_etb__COMPID1); set_reset_data( debug_etb__COMPID2, val_debug_etb__COMPID2); set_reset_data( debug_etb__COMPID3, val_debug_etb__COMPID3); // ************************************************************ // Module debug_ftm ftm // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( debug_ftm__FTMGLBCTRL, val_debug_ftm__FTMGLBCTRL); set_reset_data( debug_ftm__FTMSTATUS, val_debug_ftm__FTMSTATUS); set_reset_data( debug_ftm__FTMCONTROL, val_debug_ftm__FTMCONTROL); set_reset_data( debug_ftm__FTMP2FDBG0, val_debug_ftm__FTMP2FDBG0); set_reset_data( debug_ftm__FTMP2FDBG1, val_debug_ftm__FTMP2FDBG1); set_reset_data( debug_ftm__FTMP2FDBG2, val_debug_ftm__FTMP2FDBG2); set_reset_data( debug_ftm__FTMP2FDBG3, val_debug_ftm__FTMP2FDBG3); set_reset_data( debug_ftm__FTMF2PDBG0, val_debug_ftm__FTMF2PDBG0); set_reset_data( debug_ftm__FTMF2PDBG1, val_debug_ftm__FTMF2PDBG1); set_reset_data( debug_ftm__FTMF2PDBG2, val_debug_ftm__FTMF2PDBG2); set_reset_data( debug_ftm__FTMF2PDBG3, val_debug_ftm__FTMF2PDBG3); set_reset_data( debug_ftm__CYCOUNTPRE, val_debug_ftm__CYCOUNTPRE); set_reset_data( debug_ftm__FTMSYNCRELOAD, val_debug_ftm__FTMSYNCRELOAD); set_reset_data( debug_ftm__FTMSYNCCOUT, val_debug_ftm__FTMSYNCCOUT); set_reset_data( debug_ftm__FTMATID, val_debug_ftm__FTMATID); set_reset_data( debug_ftm__FTMITTRIGOUTACK, val_debug_ftm__FTMITTRIGOUTACK); set_reset_data( debug_ftm__FTMITTRIGGER, val_debug_ftm__FTMITTRIGGER); set_reset_data( debug_ftm__FTMITTRACEDIS, val_debug_ftm__FTMITTRACEDIS); set_reset_data( debug_ftm__FTMITCYCCOUNT, val_debug_ftm__FTMITCYCCOUNT); set_reset_data( debug_ftm__FTMITATBDATA0, val_debug_ftm__FTMITATBDATA0); set_reset_data( debug_ftm__FTMITATBCTR2, val_debug_ftm__FTMITATBCTR2); set_reset_data( debug_ftm__FTMITATBCTR1, val_debug_ftm__FTMITATBCTR1); set_reset_data( debug_ftm__FTMITATBCTR0, val_debug_ftm__FTMITATBCTR0); set_reset_data( debug_ftm__FTMITCR, val_debug_ftm__FTMITCR); set_reset_data( debug_ftm__CLAIMTAGSET, val_debug_ftm__CLAIMTAGSET); set_reset_data( debug_ftm__CLAIMTAGCLR, val_debug_ftm__CLAIMTAGCLR); set_reset_data( debug_ftm__LOCK_ACCESS, val_debug_ftm__LOCK_ACCESS); set_reset_data( debug_ftm__LOCK_STATUS, val_debug_ftm__LOCK_STATUS); set_reset_data( debug_ftm__FTMAUTHSTATUS, val_debug_ftm__FTMAUTHSTATUS); set_reset_data( debug_ftm__FTMDEVID, val_debug_ftm__FTMDEVID); set_reset_data( debug_ftm__FTMDEV_TYPE, val_debug_ftm__FTMDEV_TYPE); set_reset_data( debug_ftm__FTMPERIPHID4, val_debug_ftm__FTMPERIPHID4); set_reset_data( debug_ftm__FTMPERIPHID5, val_debug_ftm__FTMPERIPHID5); set_reset_data( debug_ftm__FTMPERIPHID6, val_debug_ftm__FTMPERIPHID6); set_reset_data( debug_ftm__FTMPERIPHID7, val_debug_ftm__FTMPERIPHID7); set_reset_data( debug_ftm__FTMPERIPHID0, val_debug_ftm__FTMPERIPHID0); set_reset_data( debug_ftm__FTMPERIPHID1, val_debug_ftm__FTMPERIPHID1); set_reset_data( debug_ftm__FTMPERIPHID2, val_debug_ftm__FTMPERIPHID2); set_reset_data( debug_ftm__FTMPERIPHID3, val_debug_ftm__FTMPERIPHID3); set_reset_data( debug_ftm__FTMCOMPONID0, val_debug_ftm__FTMCOMPONID0); set_reset_data( debug_ftm__FTMCOMPONID1, val_debug_ftm__FTMCOMPONID1); set_reset_data( debug_ftm__FTMCOMPONID2, val_debug_ftm__FTMCOMPONID2); set_reset_data( debug_ftm__FTMCOMPONID3, val_debug_ftm__FTMCOMPONID3); // ************************************************************ // Module debug_funnel funnel // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( debug_funnel__Control, val_debug_funnel__Control); set_reset_data( debug_funnel__PriControl, val_debug_funnel__PriControl); set_reset_data( debug_funnel__ITATBDATA0, val_debug_funnel__ITATBDATA0); set_reset_data( debug_funnel__ITATBCTR2, val_debug_funnel__ITATBCTR2); set_reset_data( debug_funnel__ITATBCTR1, val_debug_funnel__ITATBCTR1); set_reset_data( debug_funnel__ITATBCTR0, val_debug_funnel__ITATBCTR0); set_reset_data( debug_funnel__IMCR, val_debug_funnel__IMCR); set_reset_data( debug_funnel__CTSR, val_debug_funnel__CTSR); set_reset_data( debug_funnel__CTCR, val_debug_funnel__CTCR); set_reset_data( debug_funnel__LAR, val_debug_funnel__LAR); set_reset_data( debug_funnel__LSR, val_debug_funnel__LSR); set_reset_data( debug_funnel__ASR, val_debug_funnel__ASR); set_reset_data( debug_funnel__DEVID, val_debug_funnel__DEVID); set_reset_data( debug_funnel__DTIR, val_debug_funnel__DTIR); set_reset_data( debug_funnel__PERIPHID4, val_debug_funnel__PERIPHID4); set_reset_data( debug_funnel__PERIPHID5, val_debug_funnel__PERIPHID5); set_reset_data( debug_funnel__PERIPHID6, val_debug_funnel__PERIPHID6); set_reset_data( debug_funnel__PERIPHID7, val_debug_funnel__PERIPHID7); set_reset_data( debug_funnel__PERIPHID0, val_debug_funnel__PERIPHID0); set_reset_data( debug_funnel__PERIPHID1, val_debug_funnel__PERIPHID1); set_reset_data( debug_funnel__PERIPHID2, val_debug_funnel__PERIPHID2); set_reset_data( debug_funnel__PERIPHID3, val_debug_funnel__PERIPHID3); set_reset_data( debug_funnel__COMPID0, val_debug_funnel__COMPID0); set_reset_data( debug_funnel__COMPID1, val_debug_funnel__COMPID1); set_reset_data( debug_funnel__COMPID2, val_debug_funnel__COMPID2); set_reset_data( debug_funnel__COMPID3, val_debug_funnel__COMPID3); // ************************************************************ // Module debug_itm itm // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( debug_itm__StimPort00, val_debug_itm__StimPort00); set_reset_data( debug_itm__StimPort01, val_debug_itm__StimPort01); set_reset_data( debug_itm__StimPort02, val_debug_itm__StimPort02); set_reset_data( debug_itm__StimPort03, val_debug_itm__StimPort03); set_reset_data( debug_itm__StimPort04, val_debug_itm__StimPort04); set_reset_data( debug_itm__StimPort05, val_debug_itm__StimPort05); set_reset_data( debug_itm__StimPort06, val_debug_itm__StimPort06); set_reset_data( debug_itm__StimPort07, val_debug_itm__StimPort07); set_reset_data( debug_itm__StimPort08, val_debug_itm__StimPort08); set_reset_data( debug_itm__StimPort09, val_debug_itm__StimPort09); set_reset_data( debug_itm__StimPort10, val_debug_itm__StimPort10); set_reset_data( debug_itm__StimPort11, val_debug_itm__StimPort11); set_reset_data( debug_itm__StimPort12, val_debug_itm__StimPort12); set_reset_data( debug_itm__StimPort13, val_debug_itm__StimPort13); set_reset_data( debug_itm__StimPort14, val_debug_itm__StimPort14); set_reset_data( debug_itm__StimPort15, val_debug_itm__StimPort15); set_reset_data( debug_itm__StimPort16, val_debug_itm__StimPort16); set_reset_data( debug_itm__StimPort17, val_debug_itm__StimPort17); set_reset_data( debug_itm__StimPort18, val_debug_itm__StimPort18); set_reset_data( debug_itm__StimPort19, val_debug_itm__StimPort19); set_reset_data( debug_itm__StimPort20, val_debug_itm__StimPort20); set_reset_data( debug_itm__StimPort21, val_debug_itm__StimPort21); set_reset_data( debug_itm__StimPort22, val_debug_itm__StimPort22); set_reset_data( debug_itm__StimPort23, val_debug_itm__StimPort23); set_reset_data( debug_itm__StimPort24, val_debug_itm__StimPort24); set_reset_data( debug_itm__StimPort25, val_debug_itm__StimPort25); set_reset_data( debug_itm__StimPort26, val_debug_itm__StimPort26); set_reset_data( debug_itm__StimPort27, val_debug_itm__StimPort27); set_reset_data( debug_itm__StimPort28, val_debug_itm__StimPort28); set_reset_data( debug_itm__StimPort29, val_debug_itm__StimPort29); set_reset_data( debug_itm__StimPort30, val_debug_itm__StimPort30); set_reset_data( debug_itm__StimPort31, val_debug_itm__StimPort31); set_reset_data( debug_itm__TER, val_debug_itm__TER); set_reset_data( debug_itm__TTR, val_debug_itm__TTR); set_reset_data( debug_itm__CR, val_debug_itm__CR); set_reset_data( debug_itm__SCR, val_debug_itm__SCR); set_reset_data( debug_itm__ITTRIGOUTACK, val_debug_itm__ITTRIGOUTACK); set_reset_data( debug_itm__ITTRIGOUT, val_debug_itm__ITTRIGOUT); set_reset_data( debug_itm__ITATBDATA0, val_debug_itm__ITATBDATA0); set_reset_data( debug_itm__ITATBCTR2, val_debug_itm__ITATBCTR2); set_reset_data( debug_itm__ITATABCTR1, val_debug_itm__ITATABCTR1); set_reset_data( debug_itm__ITATBCTR0, val_debug_itm__ITATBCTR0); set_reset_data( debug_itm__IMCR, val_debug_itm__IMCR); set_reset_data( debug_itm__CTSR, val_debug_itm__CTSR); set_reset_data( debug_itm__CTCR, val_debug_itm__CTCR); set_reset_data( debug_itm__LAR, val_debug_itm__LAR); set_reset_data( debug_itm__LSR, val_debug_itm__LSR); set_reset_data( debug_itm__ASR, val_debug_itm__ASR); set_reset_data( debug_itm__DEVID, val_debug_itm__DEVID); set_reset_data( debug_itm__DTIR, val_debug_itm__DTIR); set_reset_data( debug_itm__PERIPHID4, val_debug_itm__PERIPHID4); set_reset_data( debug_itm__PERIPHID5, val_debug_itm__PERIPHID5); set_reset_data( debug_itm__PERIPHID6, val_debug_itm__PERIPHID6); set_reset_data( debug_itm__PERIPHID7, val_debug_itm__PERIPHID7); set_reset_data( debug_itm__PERIPHID0, val_debug_itm__PERIPHID0); set_reset_data( debug_itm__PERIPHID1, val_debug_itm__PERIPHID1); set_reset_data( debug_itm__PERIPHID2, val_debug_itm__PERIPHID2); set_reset_data( debug_itm__PERIPHID3, val_debug_itm__PERIPHID3); set_reset_data( debug_itm__COMPID0, val_debug_itm__COMPID0); set_reset_data( debug_itm__COMPID1, val_debug_itm__COMPID1); set_reset_data( debug_itm__COMPID2, val_debug_itm__COMPID2); set_reset_data( debug_itm__COMPID3, val_debug_itm__COMPID3); // ************************************************************ // Module debug_tpiu tpiu // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( debug_tpiu__SuppSize, val_debug_tpiu__SuppSize); set_reset_data( debug_tpiu__CurrentSize, val_debug_tpiu__CurrentSize); set_reset_data( debug_tpiu__SuppTrigMode, val_debug_tpiu__SuppTrigMode); set_reset_data( debug_tpiu__TrigCount, val_debug_tpiu__TrigCount); set_reset_data( debug_tpiu__TrigMult, val_debug_tpiu__TrigMult); set_reset_data( debug_tpiu__SuppTest, val_debug_tpiu__SuppTest); set_reset_data( debug_tpiu__CurrentTest, val_debug_tpiu__CurrentTest); set_reset_data( debug_tpiu__TestRepeatCount, val_debug_tpiu__TestRepeatCount); set_reset_data( debug_tpiu__FFSR, val_debug_tpiu__FFSR); set_reset_data( debug_tpiu__FFCR, val_debug_tpiu__FFCR); set_reset_data( debug_tpiu__FormatSyncCount, val_debug_tpiu__FormatSyncCount); set_reset_data( debug_tpiu__EXTCTLIn, val_debug_tpiu__EXTCTLIn); set_reset_data( debug_tpiu__EXTCTLOut, val_debug_tpiu__EXTCTLOut); set_reset_data( debug_tpiu__ITTRFLINACK, val_debug_tpiu__ITTRFLINACK); set_reset_data( debug_tpiu__ITTRFLIN, val_debug_tpiu__ITTRFLIN); set_reset_data( debug_tpiu__ITATBDATA0, val_debug_tpiu__ITATBDATA0); set_reset_data( debug_tpiu__ITATBCTR2, val_debug_tpiu__ITATBCTR2); set_reset_data( debug_tpiu__ITATBCTR1, val_debug_tpiu__ITATBCTR1); set_reset_data( debug_tpiu__ITATBCTR0, val_debug_tpiu__ITATBCTR0); set_reset_data( debug_tpiu__IMCR, val_debug_tpiu__IMCR); set_reset_data( debug_tpiu__CTSR, val_debug_tpiu__CTSR); set_reset_data( debug_tpiu__CTCR, val_debug_tpiu__CTCR); set_reset_data( debug_tpiu__LAR, val_debug_tpiu__LAR); set_reset_data( debug_tpiu__LSR, val_debug_tpiu__LSR); set_reset_data( debug_tpiu__ASR, val_debug_tpiu__ASR); set_reset_data( debug_tpiu__DEVID, val_debug_tpiu__DEVID); set_reset_data( debug_tpiu__DTIR, val_debug_tpiu__DTIR); set_reset_data( debug_tpiu__PERIPHID4, val_debug_tpiu__PERIPHID4); set_reset_data( debug_tpiu__PERIPHID5, val_debug_tpiu__PERIPHID5); set_reset_data( debug_tpiu__PERIPHID6, val_debug_tpiu__PERIPHID6); set_reset_data( debug_tpiu__PERIPHID7, val_debug_tpiu__PERIPHID7); set_reset_data( debug_tpiu__PERIPHID0, val_debug_tpiu__PERIPHID0); set_reset_data( debug_tpiu__PERIPHID1, val_debug_tpiu__PERIPHID1); set_reset_data( debug_tpiu__PERIPHID2, val_debug_tpiu__PERIPHID2); set_reset_data( debug_tpiu__PERIPHID3, val_debug_tpiu__PERIPHID3); set_reset_data( debug_tpiu__COMPID0, val_debug_tpiu__COMPID0); set_reset_data( debug_tpiu__COMPID1, val_debug_tpiu__COMPID1); set_reset_data( debug_tpiu__COMPID2, val_debug_tpiu__COMPID2); set_reset_data( debug_tpiu__COMPID3, val_debug_tpiu__COMPID3); // ************************************************************ // Module devcfg devcfg // doc version: 1.1 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( devcfg__CTRL, val_devcfg__CTRL); set_reset_data( devcfg__LOCK, val_devcfg__LOCK); set_reset_data( devcfg__CFG, val_devcfg__CFG); set_reset_data( devcfg__INT_STS, val_devcfg__INT_STS); set_reset_data( devcfg__INT_MASK, val_devcfg__INT_MASK); set_reset_data( devcfg__STATUS, val_devcfg__STATUS); set_reset_data( devcfg__DMA_SRC_ADDR, val_devcfg__DMA_SRC_ADDR); set_reset_data( devcfg__DMA_DST_ADDR, val_devcfg__DMA_DST_ADDR); set_reset_data( devcfg__DMA_SRC_LEN, val_devcfg__DMA_SRC_LEN); set_reset_data( devcfg__DMA_DEST_LEN, val_devcfg__DMA_DEST_LEN); set_reset_data( devcfg__ROM_SHADOW, val_devcfg__ROM_SHADOW); set_reset_data( devcfg__MULTIBOOT_ADDR, val_devcfg__MULTIBOOT_ADDR); set_reset_data( devcfg__SW_ID, val_devcfg__SW_ID); set_reset_data( devcfg__UNLOCK, val_devcfg__UNLOCK); set_reset_data( devcfg__MCTRL, val_devcfg__MCTRL); set_reset_data( devcfg__XADCIF_CFG, val_devcfg__XADCIF_CFG); set_reset_data( devcfg__XADCIF_INT_STS, val_devcfg__XADCIF_INT_STS); set_reset_data( devcfg__XADCIF_INT_MASK, val_devcfg__XADCIF_INT_MASK); set_reset_data( devcfg__XADCIF_MSTS, val_devcfg__XADCIF_MSTS); set_reset_data( devcfg__XADCIF_CMDFIFO, val_devcfg__XADCIF_CMDFIFO); set_reset_data( devcfg__XADCIF_RDFIFO, val_devcfg__XADCIF_RDFIFO); set_reset_data( devcfg__XADCIF_MCTL, val_devcfg__XADCIF_MCTL); // ************************************************************ // Module dmac0_ns dmac // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( dmac0_ns__DSR, val_dmac0_ns__DSR); set_reset_data( dmac0_ns__DPC, val_dmac0_ns__DPC); set_reset_data( dmac0_ns__INTEN, val_dmac0_ns__INTEN); set_reset_data( dmac0_ns__INT_EVENT_RIS, val_dmac0_ns__INT_EVENT_RIS); set_reset_data( dmac0_ns__INTMIS, val_dmac0_ns__INTMIS); set_reset_data( dmac0_ns__INTCLR, val_dmac0_ns__INTCLR); set_reset_data( dmac0_ns__FSRD, val_dmac0_ns__FSRD); set_reset_data( dmac0_ns__FSRC, val_dmac0_ns__'b'FSRC); set_reset_data( dmac0_ns__FTRD, val_dmac0_ns__FTRD); set_reset_data( dmac0_ns__FTR0, val_dmac0_ns__FTR0); set_reset_data( dmac0_ns__FTR1, val_dmac0_ns__FTR1); set_reset_data( dmac0_ns__FTR2, val_dmac0_ns__FTR2); set_reset_data( dmac0_ns__FTR3, val_dmac0_ns__FTR3); set_reset_data( dmac0_ns__FTR4, val_dmac0_ns__FTR4); set_reset_data( dmac0_ns__FTR5, val_dmac0_ns__FTR5); set_reset_data( dmac0_ns__FTR6, val_dmac0_ns__FTR6); set_reset_data( dmac0_ns__FTR7, val_dmac0_ns__FTR7); set_reset_data( dmac0_ns__CSR0, val_dmac0_ns__CSR0); set_reset_data( dmac0_ns__CPC0, val_dmac0_ns__CPC0); set_reset_data( dmac0_ns__CSR1, val_dmac0_ns__CSR1); set_reset_data( dmac0_ns__CPC1, val_dmac0_ns__CPC1); set_reset_data( dmac0_ns__CSR2, val_dmac0_ns__CSR2); set_reset_data( dmac0_ns__CPC2, val_dmac0_ns__CPC2); set_reset_data( dmac0_ns__CSR3, val_dmac0_ns__CSR3); set_reset_data( dmac0_ns__CPC3, val_dmac0_ns__CPC3); set_reset_data( dmac0_ns__CSR4, val_dmac0_ns__CSR4); set_reset_data( dmac0_ns__CPC4, val_dmac0_ns__CPC4); set_reset_data( dmac0_ns__CSR5, val_dmac0_ns__CSR5); set_reset_data( dmac0_ns__CPC5, val_dmac0_ns__CPC5); set_reset_data( dmac0_ns__CSR6, val_dmac0_ns__CSR6); set_reset_data( dmac0_ns__CPC6, val_dmac0_ns__CPC6); set_reset_data( dmac0_ns__CSR7, val_dmac0_ns__CSR7); set_reset_data( dmac0_ns__CPC7, val_dmac0_ns__CPC7); set_reset_data( dmac0_ns__SAR0, val_dmac0_ns__SAR0); set_reset_data( dmac0_ns__DAR0, val_dmac0_ns__DAR0); set_reset_data( dmac0_ns__CCR0, val_dmac0_ns__CCR0); set_reset_data( dmac0_ns__LC0_0, val_dmac0_ns__LC0_0); set_reset_data( dmac0_ns__LC1_0, val_dmac0_ns__LC1_0); set_reset_data( dmac0_ns__SAR1, val_dmac0_ns__SAR1); set_reset_data( dmac0_ns__DAR1, val_dmac0_ns__DAR1); set_reset_data( dmac0_ns__CCR1, val_dmac0_ns__CCR1); set_reset_data( dmac0_ns__LC0_1, val_dmac0_ns__LC0_1); set_reset_data( dmac0_ns__LC1_1, val_dmac0_ns__LC1_1); set_reset_data( dmac0_ns__SAR2, val_dmac0_ns__SAR2); set_reset_data( dmac0_ns__DAR2, val_dmac0_ns__DAR2); set_reset_data( dmac0_ns__CCR2, val_dmac0_ns__CCR2); set_reset_data( dmac0_ns__LC0_2, val_dmac0_ns__LC0_2); set_reset_data( dmac0_ns__LC1_2, val_dmac0_ns__LC1_2); set_reset_data( dmac0_ns__SAR3, val_dmac0_ns__SAR3); set_reset_data( dmac0_ns__DAR3, val_dmac0_ns__DAR3); set_reset_data( dmac0_ns__CCR3, val_dmac0_ns__CCR3); set_reset_data( dmac0_ns__LC0_3, val_dmac0_ns__LC0_3); set_reset_data( dmac0_ns__LC1_3, val_dmac0_ns__LC1_3); set_reset_data( dmac0_ns__SAR4, val_dmac0_ns__SAR4); set_reset_data( dmac0_ns__DAR4, val_dmac0_ns__DAR4); set_reset_data( dmac0_ns__CCR4, val_dmac0_ns__CCR4); set_reset_data( dmac0_ns__LC0_4, val_dmac0_ns__LC0_4); set_reset_data( dmac0_ns__LC1_4, val_dmac0_ns__LC1_4); set_reset_data( dmac0_ns__SAR5, val_dmac0_ns__SAR5); set_reset_data( dmac0_ns__DAR5, val_dmac0_ns__DAR5); set_reset_data( dmac0_ns__CCR5, val_dmac0_ns__CCR5); set_reset_data( dmac0_ns__LC0_5, val_dmac0_ns__LC0_5); set_reset_data( dmac0_ns__LC1_5, val_dmac0_ns__LC1_5); set_reset_data( dmac0_ns__SAR6, val_dmac0_ns__SAR6); set_reset_data( dmac0_ns__DAR6, val_dmac0_ns__DAR6); set_reset_data( dmac0_ns__CCR6, val_dmac0_ns__CCR6); set_reset_data( dmac0_ns__LC0_6, val_dmac0_ns__LC0_6); set_reset_data( dmac0_ns__LC1_6, val_dmac0_ns__LC1_6); set_reset_data( dmac0_ns__SAR7, val_dmac0_ns__SAR7); set_reset_data( dmac0_ns__DAR7, val_dmac0_ns__DAR7); set_reset_data( dmac0_ns__CCR7, val_dmac0_ns__CCR7); set_reset_data( dmac0_ns__LC0_7, val_dmac0_ns__LC0_7); set_reset_data( dmac0_ns__LC1_7, val_dmac0_ns__LC1_7); set_reset_data( dmac0_ns__DBGSTATUS, val_dmac0_ns__DBGSTATUS); set_reset_data( dmac0_ns__DBGCMD, val_dmac0_ns__DBGCMD); set_reset_data( dmac0_ns__DBGINST0, val_dmac0_ns__DBGINST0); set_reset_data( dmac0_ns__DBGINST1, val_dmac0_ns__DBGINST1); set_reset_data( dmac0_ns__CR0, val_dmac0_ns__CR0); set_reset_data( dmac0_ns__CR1, val_dmac0_ns__CR1); set_reset_data( dmac0_ns__CR2, val_dmac0_ns__CR2); set_reset_data( dmac0_ns__CR3, val_dmac0_ns__CR3); set_reset_data( dmac0_ns__CR4, val_dmac0_ns__CR4); set_reset_data( dmac0_ns__CRD, val_dmac0_ns__CRD); set_reset_data( dmac0_ns__WD, val_dmac0_ns__WD); set_reset_data( dmac0_ns__periph_id_0, val_dmac0_ns__periph_id_0); set_reset_data( dmac0_ns__periph_id_1, val_dmac0_ns__periph_id_1); set_reset_data( dmac0_ns__periph_id_2, val_dmac0_ns__periph_id_2); set_reset_data( dmac0_ns__periph_id_3, val_dmac0_ns__periph_id_3); set_reset_data( dmac0_ns__pcell_id_0, val_dmac0_ns__pcell_id_0); set_reset_data( dmac0_ns__pcell_id_1, val_dmac0_ns__pcell_id_1); set_reset_data( dmac0_ns__pcell_id_2, val_dmac0_ns__pcell_id_2); set_reset_data( dmac0_ns__pcell_id_3, val_dmac0_ns__pcell_id_3); // ************************************************************ // Module dmac0_s dmac // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( dmac0_s__DSR, val_dmac0_s__DSR); set_reset_data( dmac0_s__DPC, val_dmac0_s__DPC); set_reset_data( dmac0_s__INTEN, val_dmac0_s__INTEN); set_reset_data( dmac0_s__INT_EVENT_RIS, val_dmac0_s__INT_EVENT_RIS); set_reset_data( dmac0_s__INTMIS, val_dmac0_s__INTMIS); set_reset_data( dmac0_s__INTCLR, val_dmac0_s__INTCLR); set_reset_data( dmac0_s__FSRD, val_dmac0_s__FSRD); set_reset_data( dmac0_s__FSRC, val_dmac0_s__FSRC); set_reset_data( dmac0_s__FTRD, val_dmac0_s__FTRD); set_reset_data( dmac0_s__FTR0, val_dmac0_s__FTR0); set_reset_data( dmac0_s__FTR1, val_dmac0_s__FTR1); set_reset_data( dmac0_s__FTR2, val_dmac0_s__FTR2); set_reset_data( dmac0_s__FTR3, val_dmac0_s__FTR3); set_reset_data( dmac0_s__FTR4, val_dmac0_s__FTR4); set_reset_data( dmac0_s__FTR5, val_dmac0_s__FTR5); set_reset_data( dmac0_s__FTR6, val_dmac0_s__FTR6); set_reset_data( dmac0_s__FTR7, val_dmac0_s__FTR7); set_reset_data( dmac0_s__CSR0, val_dmac0_s__CSR0); set_reset_data( dmac0_s__CPC0, val_dmac0_s__CPC0); set_reset_data( dmac0_s__CSR1, val_dmac0_s__CSR1); set_reset_data( dmac0_s__CPC1, val_dmac0_s__CPC1); set_reset_data( dmac0_s__CSR2, val_dmac0_s__CSR2); set_reset_data( dmac0_s__CPC2, val_dmac0_s__CPC2); set_reset_data( dmac0_s__CSR3, val_dmac0_s__CSR3); set_reset_data( dmac0_s__CPC3, val_dmac0_s__CPC3); set_reset_data( dmac0_s__CSR4, val_dmac0_s__CSR4); set_reset_data( dmac0_s__CPC4, val_dmac0_s__CPC4); set_reset_data( dmac0_s__CSR5, val_dmac0_s__CSR5); set_reset_data( dmac0_s__CPC5, val_dmac0_s__CPC5); set_reset_data( dmac0_s__CSR6, val_dmac0_s__CSR6); set_reset_data( dmac0_s__CPC6, val_dmac0_s__CPC6); set_reset_data( dmac0_s__CSR7, val_dmac0_s__CSR7); set_reset_data( dmac0_s__CPC7, val_dmac0_s__CPC7); set_reset_data( dmac0_s__SAR0, val_dmac0_s__SAR0); set_reset_data( dmac0_s__DAR0, val_dmac0_s__DAR0); set_reset_data( dmac0_s__CCR0, val_dmac0_s__CCR0); set_reset_data( dmac0_s__LC0_0, val_dmac0_s__LC0_0); set_reset_data( dmac0_s__LC1_0, val_dmac0_s__LC1_0); set_reset_data( dmac0_s__SAR1, val_dmac0_s__SAR1); set_reset_data( dmac0_s__DAR1, val_dmac0_s__DAR1); set_reset_data( dmac0_s__CCR1, val_dmac0_s__CCR1); set_reset_data( dmac0_s__LC0_1, val_dmac0_s__LC0_1); set_reset_data( dmac0_s__LC1_1, val_dmac0_s__LC1_1); set_reset_data( dmac0_s__SAR2, val_dmac0_s__SAR2); set_reset_data( dmac0_s__DAR2, val_dmac0_s__DAR2); set_reset_data( dmac0_s__CCR2, val_dmac0_s__CCR2); set_reset_data( dmac0_s__LC0_2, val_dmac0_s__LC0_2); set_reset_data( dmac0_s__LC1_2, val_dmac0_s__LC1_2); set_reset_data( dmac0_s__SAR3, val_dmac0_s__SAR3); set_reset_data( dmac0_s__DAR3, val_dmac0_s__DAR3); set_reset_data( dmac0_s__CCR3, val_dmac0_s__CCR3); set_reset_data( dmac0_s__LC0_3, val_dmac0_s__LC0_3); set_reset_data( dmac0_s__LC1_3, val_dmac0_s__LC1_3); set_reset_data( dmac0_s__SAR4, val_dmac0_s__SAR4); set_reset_data( dmac0_s__DAR4, val_dmac0_s__DAR4); set_reset_data( dmac0_s__CCR4, val_dmac0_s__CCR4); set_reset_data( dmac0_s__LC0_4, val_dmac0_s__LC0_4); set_reset_data( dmac0_s__LC1_4, val_dmac0_s__LC1_4); set_reset_data( dmac0_s__SAR5, val_dmac0_s__SAR5); set_reset_data( dmac0_s__DAR5, val_dmac0_s__DAR5); set_reset_data( dmac0_s__CCR5, val_dmac0_s__CCR5); set_reset_data( dmac0_s__LC0_5, val_dmac0_s__LC0_5); set_reset_data( dmac0_s__LC1_5, val_dmac0_s__LC1_5); set_reset_data( dmac0_s__SAR6, val_dmac0_s__SAR6); set_reset_data( dmac0_s__DAR6, val_dmac0_s__DAR6); set_reset_data( dmac0_s__CCR6, val_dmac0_s__CCR6); set_reset_data( dmac0_s__LC0_6, val_dmac0_s__LC0_6); set_reset_data( dmac0_s__LC1_6, val_dmac0_s__LC1_6); set_reset_data( dmac0_s__SAR7, val_dmac0_s__SAR7); set_reset_data( dmac0_s__DAR7, val_dmac0_s__DAR7); set_reset_data( dmac0_s__CCR7, val_dmac0_s__CCR7); set_reset_data( dmac0_s__LC0_7, val_dmac0_s__LC0_7); set_reset_data( dmac0_s__LC1_7, val_dmac0_s__LC1_7); set_reset_data( dmac0_s__DBGSTATUS, val_dmac0_s__DBGSTATUS); set_reset_data( dmac0_s__DBGCMD, val_dmac0_s__DBGCMD); set_reset_data( dmac0_s__DBGINST0, val_dmac0_s__DBGINST0); set_reset_data( dmac0_s__DBGINST1, val_dmac0_s__DBGINST1); set_reset_data( dmac0_s__CR0, val_dmac0_s__CR0); set_reset_data( dmac0_s__CR1, val_dmac0_s__CR1); set_reset_data( dmac0_s__CR2, val_dmac0_s__CR2); set_reset_data( dmac0_s__CR3, val_dmac0_s__CR3); set_reset_data( dmac0_s__CR4, val_dmac0_s__CR4); set_reset_data( dmac0_s__CRD, val_dmac0_s__CRD); set_reset_data( dmac0_s__WD, val_dmac0_s__WD); set_reset_data( dmac0_s__periph_id_0, val_dmac0_s__periph_id_0); set_reset_data( dmac0_s__periph_id_1, val_dmac0_s__periph_id_1); set_reset_data( dmac0_s__periph_id_2, val_dmac0_s__periph_id_2); set_reset_data( dmac0_s__periph_id_3, val_dmac0_s__periph_id_3); set_reset_data( dmac0_s__pcell_id_0, val_dmac0_s__pcell_id_0); set_reset_data( dmac0_s__pcell_id_1, val_dmac0_s__pcell_id_1); set_reset_data( dmac0_s__pcell_id_2, val_dmac0_s__pcell_id_2); set_reset_data( dmac0_s__pcell_id_3, val_dmac0_s__pcell_id_3); // ************************************************************ // Module efuse_ctrl efuse_ctrl // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( efuse_ctrl__WR_LOCK, val_efuse_ctrl__WR_LOCK); set_reset_data( efuse_ctrl__WR_UNLOCK, val_efuse_ctrl__WR_UNLOCK); set_reset_data( efuse_ctrl__WR_LOCKSTA, val_efuse_ctrl__WR_LOCKSTA); set_reset_data( efuse_ctrl__CFG, val_efuse_ctrl__CFG); set_reset_data( efuse_ctrl__STATUS, val_efuse_ctrl__STATUS); set_reset_data( efuse_ctrl__CONTROL, val_efuse_ctrl__CONTROL); set_reset_data( efuse_ctrl__PGM_STBW, val_efuse_ctrl__PGM_STBW); set_reset_data( efuse_ctrl__RD_STBW, val_efuse_ctrl__RD_STBW); // ************************************************************ // Module gem0 GEM // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( gem0__net_ctrl, val_gem0__net_ctrl); set_reset_data( gem0__net_cfg, val_gem0__net_cfg); set_reset_data( gem0__net_status, val_gem0__net_status); set_reset_data( gem0__user_io, val_gem0__user_io); set_reset_data( gem0__dma_cfg, val_gem0__dma_cfg); set_reset_data( gem0__tx_status, val_gem0__tx_status); set_reset_data( gem0__rx_qbar, val_gem0__rx_qbar); set_reset_data( gem0__tx_qbar, val_gem0__tx_qbar); set_reset_data( gem0__rx_status, val_gem0__rx_status); set_reset_data( gem0__intr_status, val_gem0__intr_status); set_reset_data( gem0__intr_en, val_gem0__intr_en); set_reset_data( gem0__intr_dis, val_gem0__intr_dis); set_reset_data( gem0__intr_mask, val_gem0__intr_mask); set_reset_data( gem0__phy_maint, val_gem0__phy_maint); set_reset_data( gem0__rx_pauseq, val_gem0__rx_pauseq); set_reset_data( gem0__tx_pauseq, val_gem0__tx_pauseq); set_reset_data( gem0__tx_partial_st_fwd, val_gem0__tx_partial_st_fwd); set_reset_data( gem0__rx_partial_st_fwd, val_gem0__rx_partial_st_fwd); set_reset_data( gem0__hash_bot, val_gem0__hash_bot); set_reset_data( gem0__hash_top, val_gem0__hash_top); set_reset_data( gem0__spec_addr1_bot, val_gem0__spec_addr1_bot); set_reset_data( gem0__spec_addr1_top, val_gem0__spec_addr1_top); set_reset_data( gem0__spec_addr2_bot, val_gem0__spec_addr2_bot); set_reset_data( gem0__spec_addr2_top, val_gem0__spec_addr2_top); set_reset_data( gem0__spec_addr3_bot, val_gem0__spec_addr3_bot); set_reset_data( gem0__spec_addr3_top, val_gem0__spec_addr3_top); set_reset_data( gem0__spec_addr4_bot, val_gem0__spec_addr4_bot); set_reset_data( gem0__spec_addr4_top, val_gem0__spec_addr4_top); set_reset_data( gem0__type_id_match1, val_gem0__type_id_match1); set_reset_data( gem0__type_id_match2, val_gem0__type_id_match2); set_reset_data( gem0__type_id_match3, val_gem0__type_id_match3); set_reset_data( gem0__type_id_match4, val_gem0__type_id_match4); set_reset_data( gem0__wake_on_lan, val_gem0__wake_on_lan); set_reset_data( gem0__ipg_stretch, val_gem0__ipg_stretch); set_reset_data( gem0__stacked_vlan, val_gem0__stacked_vlan); set_reset_data( gem0__tx_pfc_pause, val_gem0__tx_pfc_pause); set_reset_data( gem0__spec_addr1_mask_bot, val_gem0__spec_addr1_mask_bot); set_reset_data( gem0__spec_addr1_mask_top, val_gem0__spec_addr1_mask_top); set_reset_data( gem0__module_id, val_gem0__module_id); set_reset_data( gem0__octets_tx_bot, val_gem0__octets_tx_bot); set_reset_data( gem0__octets_tx_top, val_gem0__octets_tx_top); set_reset_data( gem0__frames_tx, val_gem0__frames_tx); set_reset_data( gem0__broadcast_frames_tx, val_gem0__broadcast_frames_tx); set_reset_data( gem0__multi_frames_tx, val_gem0__multi_frames_tx); set_reset_data( gem0__pause_frames_tx, val_gem0__pause_frames_tx); set_reset_data( gem0__frames_64b_tx, val_gem0__frames_64b_tx); set_reset_data( gem0__frames_65to127b_tx, val_gem0__frames_65to127b_tx); set_reset_data( gem0__frames_128to255b_tx, val_gem0__frames_128to255b_tx); set_reset_data( gem0__frames_256to511b_tx, val_gem0__frames_256to511b_tx); set_reset_data( gem0__frames_512to1023b_tx, val_gem0__frames_512to1023b_tx); set_reset_data( gem0__frames_1024to1518b_tx, val_gem0__frames_1024to1518b_tx); set_reset_data( gem0__frames_gt1518b_tx, val_gem0__frames_gt1518b_tx); set_reset_data( gem0__tx_under_runs, val_gem0__tx_under_runs); set_reset_data( gem0__single_collisn_frames, val_gem0__single_collisn_frames); set_reset_data( gem0__multi_collisn_frames, val_gem0__multi_collisn_frames); set_reset_data( gem0__excessive_collisns, val_gem0__excessive_collisns); set_reset_data( gem0__late_collisns, val_gem0__late_collisns); set_reset_data( gem0__deferred_tx_frames, val_gem0__deferred_tx_frames); set_reset_data( gem0__carrier_sense_errs, val_gem0__carrier_sense_errs); set_reset_data( gem0__octets_rx_bot, val_gem0__octets_rx_bot); set_reset_data( gem0__octets_rx_top, val_gem0__octets_rx_top); set_reset_data( gem0__frames_rx, val_gem0__frames_rx); set_reset_data( gem0__bdcast_fames_rx, val_gem0__bdcast_fames_rx); set_reset_data( gem0__multi_frames_rx, val_gem0__multi_frames_rx); set_reset_data( gem0__pause_rx, val_gem0__pause_rx); set_reset_data( gem0__frames_64b_rx, val_gem0__frames_64b_rx); set_reset_data( gem0__frames_65to127b_rx, val_gem0__frames_65to127b_rx); set_reset_data( gem0__frames_128to255b_rx, val_gem0__frames_128to255b_rx); set_reset_data( gem0__frames_256to511b_rx, val_gem0__frames_256to511b_rx); set_reset_data( gem0__frames_512to1023b_rx, val_gem0__frames_512to1023b_rx); set_reset_data( gem0__frames_1024to1518b_rx, val_gem0__frames_1024to1518b_rx); set_reset_data( gem0__frames_gt1518b_rx, val_gem0__frames_gt1518b_rx); set_reset_data( gem0__undersz_rx, val_gem0__undersz_rx); set_reset_data( gem0__oversz_rx, val_gem0__oversz_rx); set_reset_data( gem0__jab_rx, val_gem0__jab_rx); set_reset_data( gem0__fcs_errors, val_gem0__fcs_errors); set_reset_data( gem0__length_field_errors, val_gem0__length_field_errors); set_reset_data( gem0__rx_symbol_errors, val_gem0__rx_symbol_errors); set_reset_data( gem0__align_errors, val_gem0__align_errors); set_reset_data( gem0__rx_resource_errors, val_gem0__rx_resource_errors); set_reset_data( gem0__rx_overrun_errors, val_gem0__rx_overrun_errors); set_reset_data( gem0__ip_hdr_csum_errors, val_gem0__ip_hdr_csum_errors); set_reset_data( gem0__tcp_csum_errors, val_gem0__tcp_csum_errors); set_reset_data( gem0__udp_csum_errors, val_gem0__udp_csum_errors); set_reset_data( gem0__timer_strobe_s, val_gem0__timer_strobe_s); set_reset_data( gem0__timer_strobe_ns, val_gem0__timer_strobe_ns); set_reset_data( gem0__timer_s, val_gem0__timer_s); set_reset_data( gem0__timer_ns, val_gem0__timer_ns); set_reset_data( gem0__timer_adjust, val_gem0__timer_adjust); set_reset_data( gem0__timer_incr, val_gem0__timer_incr); set_reset_data( gem0__ptp_tx_s, val_gem0__ptp_tx_s); set_reset_data( gem0__ptp_tx_ns, val_gem0__ptp_tx_ns); set_reset_data( gem0__ptp_rx_s, val_gem0__ptp_rx_s); set_reset_data( gem0__ptp_rx_ns, val_gem0__ptp_rx_ns); set_reset_data( gem0__ptp_peer_tx_s, val_gem0__ptp_peer_tx_s); set_reset_data( gem0__ptp_peer_tx_ns, val_gem0__ptp_peer_tx_ns); set_reset_data( gem0__ptp_peer_rx_s, val_gem0__ptp_peer_rx_s); set_reset_data( gem0__ptp_peer_rx_ns, val_gem0__ptp_peer_rx_ns); set_reset_data( gem0__pcs_ctrl, val_gem0__pcs_ctrl); set_reset_data( gem0__pcs_status, val_gem0__pcs_status); set_reset_data( gem0__pcs_upper_phy_id, val_gem0__pcs_upper_phy_id); set_reset_data( gem0__pcs_lower_phy_id, val_gem0__pcs_lower_phy_id); set_reset_data( gem0__pcs_autoneg_ad, val_gem0__pcs_autoneg_ad); set_reset_data( gem0__pcs_autoneg_ability, val_gem0__pcs_autoneg_ability); set_reset_data( gem0__pcs_autonec_exp, val_gem0__pcs_autonec_exp); set_reset_data( gem0__pcs_autoneg_next_pg, val_gem0__pcs_autoneg_next_pg); set_reset_data( gem0__pcs_autoneg_pnext_pg, val_gem0__pcs_autoneg_pnext_pg); set_reset_data( gem0__pcs_extended_status, val_gem0__pcs_extended_status); set_reset_data( gem0__design_cfg1, val_gem0__design_cfg1); set_reset_data( gem0__design_cfg2, val_gem0__design_cfg2); set_reset_data( gem0__design_cfg3, val_gem0__design_cfg3); set_reset_data( gem0__design_cfg4, val_gem0__design_cfg4); set_reset_data( gem0__design_cfg5, val_gem0__design_cfg5); set_reset_data( gem0__design_cfg6, val_gem0__design_cfg6); set_reset_data( gem0__design_cfg7, val_gem0__design_cfg7); set_reset_data( gem0__isr_pq1, val_gem0__isr_pq1); set_reset_data( gem0__isr_pq2, val_gem0__isr_pq2); set_reset_data( gem0__isr_pq3, val_gem0__isr_pq3); set_reset_data( gem0__isr_pq4, val_gem0__isr_pq4); set_reset_data( gem0__isr_pq5, val_gem0__isr_pq5); set_reset_data( gem0__isr_pq6, val_gem0__isr_pq6); set_reset_data( gem0__isr_pq7, val_gem0__isr_pq7); set_reset_data( gem0__tx_qbar_q1, val_gem0__tx_qbar_q1); set_reset_data( gem0__tx_qbar_q2, val_gem0__tx_qbar_q2); set_reset_data( gem0__tx_qbar_q3, val_gem0__tx_qbar_q3); set_reset_data( gem0__tx_qbar_q4, val_gem0__tx_qbar_q4); set_reset_data( gem0__tx_qbar_q5, val_gem0__tx_qbar_q5); set_reset_data( gem0__tx_qbar_q6, val_gem0__tx_qbar_q6); set_reset_data( gem0__tx_qbar_q7, val_gem0__tx_qbar_q7); set_reset_data( gem0__rx_qbar_q1, val_gem0__rx_qbar_q1); set_reset_data( gem0__rx_qbar_q2, val_gem0__rx_qbar_q2); set_reset_data( gem0__rx_qbar_q3, val_gem0__rx_qbar_q3); set_reset_data( gem0__rx_qbar_q4, val_gem0__rx_qbar_q4); set_reset_data( gem0__rx_qbar_q5, val_gem0__rx_qbar_q5); set_reset_data( gem0__rx_qbar_q6, val_gem0__rx_qbar_q6); set_reset_data( gem0__rx_qbar_q7, val_gem0__rx_qbar_q7); set_reset_data( gem0__rx_bufsz_q1, val_gem0__rx_bufsz_q1); set_reset_data( gem0__rx_bufsz_q2, val_gem0__rx_bufsz_q2); set_reset_data( gem0__rx_bufsz_q3, val_gem0__rx_bufsz_q3); set_reset_data( gem0__rx_bufsz_q4, val_gem0__rx_bufsz_q4); set_reset_data( gem0__rx_bufsz_q5, val_gem0__rx_bufsz_q5); set_reset_data( gem0__rx_bufsz_q6, val_gem0__rx_bufsz_q6); set_reset_data( gem0__rx_bufsz_q7, val_gem0__rx_bufsz_q7); set_reset_data( gem0__screen_t1_r0, val_gem0__screen_t1_r0); set_reset_data( gem0__screen_t1_r1, val_gem0__screen_t1_r1); set_reset_data( gem0__screen_t1_r2, val_gem0__screen_t1_r2); set_reset_data( gem0__screen_t1_r3, val_gem0__screen_t1_r3); set_reset_data( gem0__screen_t1_r4, val_gem0__screen_t1_r4); set_reset_data( gem0__screen_t1_r5, val_gem0__screen_t1_r5); set_reset_data( gem0__screen_t1_r6, val_gem0__screen_t1_r6); set_reset_data( gem0__screen_t1_r7, val_gem0__screen_t1_r7); set_reset_data( gem0__screen_t1_r8, val_gem0__screen_t1_r8); set_reset_data( gem0__screen_t1_r9, val_gem0__screen_t1_r9); set_reset_data( gem0__screen_t1_r10, val_gem0__screen_t1_r10); set_reset_data( gem0__screen_t1_r11, val_gem0__screen_t1_r11); set_reset_data( gem0__screen_t1_r12, val_gem0__screen_t1_r12); set_reset_data( gem0__screen_t1_r13, val_gem0__screen_t1_r13); set_reset_data( gem0__screen_t1_r14, val_gem0__screen_t1_r14); set_reset_data( gem0__screen_t1_r15, val_gem0__screen_t1_r15); set_reset_data( gem0__screen_t2_r0, val_gem0__screen_t2_r0); set_reset_data( gem0__screen_t2_r1, val_gem0__screen_t2_r1); set_reset_data( gem0__screen_t2_r2, val_gem0__screen_t2_r2); set_reset_data( gem0__screen_t2_r3, val_gem0__screen_t2_r3); set_reset_data( gem0__screen_t2_r4, val_gem0__screen_t2_r4); set_reset_data( gem0__screen_t2_r5, val_gem0__screen_t2_r5); set_reset_data( gem0__screen_t2_r6, val_gem0__screen_t2_r6); set_reset_data( gem0__screen_t2_r7, val_gem0__screen_t2_r7); set_reset_data( gem0__screen_t2_r8, val_gem0__screen_t2_r8); set_reset_data( gem0__screen_t2_r9, val_gem0__screen_t2_r9); set_reset_data( gem0__screen_t2_r10, val_gem0__screen_t2_r10); set_reset_data( gem0__screen_t2_r11, val_gem0__screen_t2_r11); set_reset_data( gem0__screen_t2_r12, val_gem0__screen_t2_r12); set_reset_data( gem0__screen_t2_r13, val_gem0__screen_t2_r13); set_reset_data( gem0__screen_t2_r14, val_gem0__screen_t2_r14); set_reset_data( gem0__screen_t2_r15, val_gem0__screen_t2_r15); set_reset_data( gem0__intr_en_pq1, val_gem0__intr_en_pq1); set_reset_data( gem0__intr_en_pq2, val_gem0__intr_en_pq2); set_reset_data( gem0__intr_en_pq3, val_gem0__intr_en_pq3); set_reset_data( gem0__intr_en_pq4, val_gem0__intr_en_pq4); set_reset_data( gem0__intr_en_pq5, val_gem0__intr_en_pq5); set_reset_data( gem0__intr_en_pq6, val_gem0__intr_en_pq6); set_reset_data( gem0__intr_en_pq7, val_gem0__intr_en_pq7); set_reset_data( gem0__intr_dis_pq1, val_gem0__intr_dis_pq1); set_reset_data( gem0__intr_dis_pq2, val_gem0__intr_dis_pq2); set_reset_data( gem0__intr_dis_pq3, val_gem0__intr_dis_pq3); set_reset_data( gem0__intr_dis_pq4, val_gem0__intr_dis_pq4); set_reset_data( gem0__intr_dis_pq5, val_gem0__intr_dis_pq5); set_reset_data( gem0__intr_dis_pq6, val_gem0__intr_dis_pq6); set_reset_data( gem0__intr_dis_pq7, val_gem0__intr_dis_pq7); set_reset_data( gem0__intr_mask_pq1, val_gem0__intr_mask_pq1); set_reset_data( gem0__intr_mask_pq2, val_gem0__intr_mask_pq2); set_reset_data( gem0__intr_mask_pq3, val_gem0__intr_mask_pq3); set_reset_data( gem0__intr_mask_pq4, val_gem0__intr_mask_pq4); set_reset_data( gem0__intr_mask_pq5, val_gem0__intr_mask_pq5); set_reset_data( gem0__intr_mask_pq6, val_gem0__intr_mask_pq6); set_reset_data( gem0__intr_mask_pq7, val_gem0__intr_mask_pq7); // ************************************************************ // Module gem1 GEM // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( gem1__net_ctrl, val_gem1__net_ctrl); set_reset_data( gem1__net_cfg, val_gem1__net_cfg); set_reset_data( gem1__net_status, val_gem1__net_status); set_reset_data( gem1__user_io, val_gem1__user_io); set_reset_data( gem1__dma_cfg, val_gem1__dma_cfg); set_reset_data( gem1__tx_status, val_gem1__tx_status); set_reset_data( gem1__rx_qbar, val_gem1__rx_qbar); set_reset_data( gem1__tx_qbar, val_gem1__tx_qbar); set_reset_data( gem1__rx_status, val_gem1__rx_status); set_reset_data( gem1__intr_status, val_gem1__intr_status); set_reset_data( gem1__intr_en, val_gem1__intr_en); set_reset_data( gem1__intr_dis, val_gem1__intr_dis); set_reset_data( gem1__intr_mask, val_gem1__intr_mask); set_reset_data( gem1__phy_maint, val_gem1__phy_maint); set_reset_data( gem1__rx_pauseq, val_gem1__rx_pauseq); set_reset_data( gem1__tx_pauseq, val_gem1__tx_pauseq); set_reset_data( gem1__tx_partial_st_fwd, val_gem1__tx_partial_st_fwd); set_reset_data( gem1__rx_partial_st_fwd, val_gem1__rx_partial_st_fwd); set_reset_data( gem1__hash_bot, val_gem1__hash_bot); set_reset_data( gem1__hash_top, val_gem1__hash_top); set_reset_data( gem1__spec_addr1_bot, val_gem1__spec_addr1_bot); set_reset_data( gem1__spec_addr1_top, val_gem1__spec_addr1_top); set_reset_data( gem1__spec_addr2_bot, val_gem1__spec_addr2_bot); set_reset_data( gem1__spec_addr2_top, val_gem1__spec_addr2_top); set_reset_data( gem1__spec_addr3_bot, val_gem1__spec_addr3_bot); set_reset_data( gem1__spec_addr3_top, val_gem1__spec_addr3_top); set_reset_data( gem1__spec_addr4_bot, val_gem1__spec_addr4_bot); set_reset_data( gem1__spec_addr4_top, val_gem1__spec_addr4_top); set_reset_data( gem1__type_id_match1, val_gem1__type_id_match1); set_reset_data( gem1__type_id_match2, val_gem1__type_id_match2); set_reset_data( gem1__type_id_match3, val_gem1__type_id_match3); set_reset_data( gem1__type_id_match4, val_gem1__type_id_match4); set_reset_data( gem1__wake_on_lan, val_gem1__wake_on_lan); set_reset_data( gem1__ipg_stretch, val_gem1__ipg_stretch); set_reset_data( gem1__stacked_vlan, val_gem1__stacked_vlan); set_reset_data( gem1__tx_pfc_pause, val_gem1__tx_pfc_pause); set_reset_data( gem1__spec_addr1_mask_bot, val_gem1__spec_addr1_mask_bot); set_reset_data( gem1__spec_addr1_mask_top, val_gem1__spec_addr1_mask_top); set_reset_data( gem1__module_id, val_gem1__module_id); set_reset_data( gem1__octets_tx_bot, val_gem1__octets_tx_bot); set_reset_data( gem1__octets_tx_top, val_gem1__octets_tx_top); set_reset_data( gem1__frames_tx, val_gem1__frames_tx); set_reset_data( gem1__broadcast_frames_tx, val_gem1__broadcast_frames_tx); set_reset_data( gem1__multi_frames_tx, val_gem1__multi_frames_tx); set_reset_data( gem1__pause_frames_tx, val_gem1__pause_frames_tx); set_reset_data( gem1__frames_64b_tx, val_gem1__frames_64b_tx); set_reset_data( gem1__frames_65to127b_tx, val_gem1__frames_65to127b_tx); set_reset_data( gem1__frames_128to255b_tx, val_gem1__frames_128to255b_tx); set_reset_data( gem1__frames_256to511b_tx, val_gem1__frames_256to511b_tx); set_reset_data( gem1__frames_512to1023b_tx, val_gem1__frames_512to1023b_tx); set_reset_data( gem1__frames_1024to1518b_tx, val_gem1__frames_1024to1518b_tx); set_reset_data( gem1__frames_gt1518b_tx, val_gem1__frames_gt1518b_tx); set_reset_data( gem1__tx_under_runs, val_gem1__tx_under_runs); set_reset_data( gem1__single_collisn_frames, val_gem1__single_collisn_frames); set_reset_data( gem1__multi_collisn_frames, val_gem1__multi_collisn_frames); set_reset_data( gem1__excessive_collisns, val_gem1__excessive_collisns); set_reset_data( gem1__late_collisns, val_gem1__late_collisns); set_reset_data( gem1__deferred_tx_frames, val_gem1__deferred_tx_frames); set_reset_data( gem1__carrier_sense_errs, val_gem1__carrier_sense_errs); set_reset_data( gem1__octets_rx_bot, val_gem1__octets_rx_bot); set_reset_data( gem1__octets_rx_top, val_gem1__octets_rx_top); set_reset_data( gem1__frames_rx, val_gem1__frames_rx); set_reset_data( gem1__bdcast_fames_rx, val_gem1__bdcast_fames_rx); set_reset_data( gem1__multi_frames_rx, val_gem1__multi_frames_rx); set_reset_data( gem1__pause_rx, val_gem1__pause_rx); set_reset_data( gem1__frames_64b_rx, val_gem1__frames_64b_rx); set_reset_data( gem1__frames_65to127b_rx, val_gem1__frames_65to127b_rx); set_reset_data( gem1__frames_128to255b_rx, val_gem1__frames_128to255b_rx); set_reset_data( gem1__frames_256to511b_rx, val_gem1__frames_256to511b_rx); set_reset_data( gem1__frames_512to1023b_rx, val_gem1__frames_512to1023b_rx); set_reset_data( gem1__frames_1024to1518b_rx, val_gem1__frames_1024to1518b_rx); set_reset_data( gem1__frames_gt1518b_rx, val_gem1__frames_gt1518b_rx); set_reset_data( gem1__undersz_rx, val_gem1__undersz_rx); set_reset_data( gem1__oversz_rx, val_gem1__oversz_rx); set_reset_data( gem1__jab_rx, val_gem1__jab_rx); set_reset_data( gem1__fcs_errors, val_gem1__fcs_errors); set_reset_data( gem1__length_field_errors, val_gem1__length_field_errors); set_reset_data( gem1__rx_symbol_errors, val_gem1__rx_symbol_errors); set_reset_data( gem1__align_errors, val_gem1__align_errors); set_reset_data( gem1__rx_resource_errors, val_gem1__rx_resource_errors); set_reset_data( gem1__rx_overrun_errors, val_gem1__rx_overrun_errors); set_reset_data( gem1__ip_hdr_csum_errors, val_gem1__ip_hdr_csum_errors); set_reset_data( gem1__tcp_csum_errors, val_gem1__tcp_csum_errors); set_reset_data( gem1__udp_csum_errors, val_gem1__udp_csum_errors); set_reset_data( gem1__timer_strobe_s, val_gem1__timer_strobe_s); set_reset_data( gem1__timer_strobe_ns, val_gem1__timer_strobe_ns); set_reset_data( gem1__timer_s, val_gem1__timer_s); set_reset_data( gem1__timer_ns, val_gem1__timer_ns); set_reset_data( gem1__timer_adjust, val_gem1__timer_adjust); set_reset_data( gem1__timer_incr, val_gem1__timer_incr); set_reset_data( gem1__ptp_tx_s, val_gem1__ptp_tx_s); set_reset_data( gem1__ptp_tx_ns, val_gem1__ptp_tx_ns); set_reset_data( gem1__ptp_rx_s, val_gem1__ptp_rx_s); set_reset_data( gem1__ptp_rx_ns, val_gem1__ptp_rx_ns); set_reset_data( gem1__ptp_peer_tx_s, val_gem1__ptp_peer_tx_s); set_reset_data( gem1__ptp_peer_tx_ns, val_gem1__ptp_peer_tx_ns); set_reset_data( gem1__ptp_peer_rx_s, val_gem1__ptp_peer_rx_s); set_reset_data( gem1__ptp_peer_rx_ns, val_gem1__ptp_peer_rx_ns); set_reset_data( gem1__pcs_ctrl, val_gem1__pcs_ctrl); set_reset_data( gem1__pcs_status, val_gem1__pcs_status); set_reset_data( gem1__pcs_upper_phy_id, val_gem1__pcs_upper_phy_id); set_reset_data( gem1__pcs_lower_phy_id, val_gem1__pcs_lower_phy_id); set_reset_data( gem1__pcs_autoneg_ad, val_gem1__pcs_autoneg_ad); set_reset_data( gem1__pcs_autoneg_ability, val_gem1__pcs_autoneg_ability); set_reset_data( gem1__pcs_autonec_exp, val_gem1__pcs_autonec_exp); set_reset_data( gem1__pcs_autoneg_next_pg, val_gem1__pcs_autoneg_next_pg); set_reset_data( gem1__pcs_autoneg_pnext_pg, val_gem1__pcs_autoneg_pnext_pg); set_reset_data( gem1__pcs_extended_status, val_gem1__pcs_extended_status); set_reset_data( gem1__design_cfg1, val_gem1__design_cfg1); set_reset_data( gem1__design_cfg2, val_gem1__design_cfg2); set_reset_data( gem1__design_cfg3, val_gem1__design_cfg3); set_reset_data( gem1__design_cfg4, val_gem1__design_cfg4); set_reset_data( gem1__design_cfg5, val_gem1__design_cfg5); set_reset_data( gem1__design_cfg6, val_gem1__design_cfg6); set_reset_data( gem1__design_cfg7, val_gem1__design_cfg7); set_reset_data( gem1__isr_pq1, val_gem1__isr_pq1); set_reset_data( gem1__isr_pq2, val_gem1__isr_pq2); set_reset_data( gem1__isr_pq3, val_gem1__isr_pq3); set_reset_data( gem1__isr_pq4, val_gem1__isr_pq4); set_reset_data( gem1__isr_pq5, val_gem1__isr_pq5); set_reset_data( gem1__isr_pq6, val_gem1__isr_pq6); set_reset_data( gem1__isr_pq7, val_gem1__isr_pq7); set_reset_data( gem1__tx_qbar_q1, val_gem1__tx_qbar_q1); set_reset_data( gem1__tx_qbar_q2, val_gem1__tx_qbar_q2); set_reset_data( gem1__tx_qbar_q3, val_gem1__tx_qbar_q3); set_reset_data( gem1__tx_qbar_q4, val_gem1__tx_qbar_q4); set_reset_data( gem1__tx_qbar_q5, val_gem1__tx_qbar_q5); set_reset_data( gem1__tx_qbar_q6, val_gem1__tx_qbar_q6); set_reset_data( gem1__tx_qbar_q7, val_gem1__tx_qbar_q7); set_reset_data( gem1__rx_qbar_q1, val_gem1__rx_qbar_q1); set_reset_data( gem1__rx_qbar_q2, val_gem1__rx_qbar_q2); set_reset_data( gem1__rx_qbar_q3, val_gem1__rx_qbar_q3); set_reset_data( gem1__rx_qbar_q4, val_gem1__rx_qbar_q4); set_reset_data( gem1__rx_qbar_q5, val_gem1__rx_qbar_q5); set_reset_data( gem1__rx_qbar_q6, val_gem1__rx_qbar_q6); set_reset_data( gem1__rx_qbar_q7, val_gem1__rx_qbar_q7); set_reset_data( gem1__rx_bufsz_q1, val_gem1__rx_bufsz_q1); set_reset_data( gem1__rx_bufsz_q2, val_gem1__rx_bufsz_q2); set_reset_data( gem1__rx_bufsz_q3, val_gem1__rx_bufsz_q3); set_reset_data( gem1__rx_bufsz_q4, val_gem1__rx_bufsz_q4); set_reset_data( gem1__rx_bufsz_q5, val_gem1__rx_bufsz_q5); set_reset_data( gem1__rx_bufsz_q6, val_gem1__rx_bufsz_q6); set_reset_data( gem1__rx_bufsz_q7, val_gem1__rx_bufsz_q7); set_reset_data( gem1__screen_t1_r0, val_gem1__screen_t1_r0); set_reset_data( gem1__screen_t1_r1, val_gem1__screen_t1_r1); set_reset_data( gem1__screen_t1_r2, val_gem1__screen_t1_r2); set_reset_data( gem1__screen_t1_r3, val_gem1__screen_t1_r3); set_reset_data( gem1__screen_t1_r4, val_gem1__screen_t1_r4); set_reset_data( gem1__screen_t1_r5, val_gem1__screen_t1_r5); set_reset_data( gem1__screen_t1_r6, val_gem1__screen_t1_r6); set_reset_data( gem1__screen_t1_r7, val_gem1__screen_t1_r7); set_reset_data( gem1__screen_t1_r8, val_gem1__screen_t1_r8); set_reset_data( gem1__screen_t1_r9, val_gem1__screen_t1_r9); set_reset_data( gem1__screen_t1_r10, val_gem1__screen_t1_r10); set_reset_data( gem1__screen_t1_r11, val_gem1__screen_t1_r11); set_reset_data( gem1__screen_t1_r12, val_gem1__screen_t1_r12); set_reset_data( gem1__screen_t1_r13, val_gem1__screen_t1_r13); set_reset_data( gem1__screen_t1_r14, val_gem1__screen_t1_r14); set_reset_data( gem1__screen_t1_r15, val_gem1__screen_t1_r15); set_reset_data( gem1__screen_t2_r0, val_gem1__screen_t2_r0); set_reset_data( gem1__screen_t2_r1, val_gem1__screen_t2_r1); set_reset_data( gem1__screen_t2_r2, val_gem1__screen_t2_r2); set_reset_data( gem1__screen_t2_r3, val_gem1__screen_t2_r3); set_reset_data( gem1__screen_t2_r4, val_gem1__screen_t2_r4); set_reset_data( gem1__screen_t2_r5, val_gem1__screen_t2_r5); set_reset_data( gem1__screen_t2_r6, val_gem1__screen_t2_r6); set_reset_data( gem1__screen_t2_r7, val_gem1__screen_t2_r7); set_reset_data( gem1__screen_t2_r8, val_gem1__screen_t2_r8); set_reset_data( gem1__screen_t2_r9, val_gem1__screen_t2_r9); set_reset_data( gem1__screen_t2_r10, val_gem1__screen_t2_r10); set_reset_data( gem1__screen_t2_r11, val_gem1__screen_t2_r11); set_reset_data( gem1__screen_t2_r12, val_gem1__screen_t2_r12); set_reset_data( gem1__screen_t2_r13, val_gem1__screen_t2_r13); set_reset_data( gem1__screen_t2_r14, val_gem1__screen_t2_r14); set_reset_data( gem1__screen_t2_r15, val_gem1__screen_t2_r15); set_reset_data( gem1__intr_en_pq1, val_gem1__intr_en_pq1); set_reset_data( gem1__intr_en_pq2, val_gem1__intr_en_pq2); set_reset_data( gem1__intr_en_pq3, val_gem1__intr_en_pq3); set_reset_data( gem1__intr_en_pq4, val_gem1__intr_en_pq4); set_reset_data( gem1__intr_en_pq5, val_gem1__intr_en_pq5); set_reset_data( gem1__intr_en_pq6, val_gem1__intr_en_pq6); set_reset_data( gem1__intr_en_pq7, val_gem1__intr_en_pq7); set_reset_data( gem1__intr_dis_pq1, val_gem1__intr_dis_pq1); set_reset_data( gem1__intr_dis_pq2, val_gem1__intr_dis_pq2); set_reset_data( gem1__intr_dis_pq3, val_gem1__intr_dis_pq3); set_reset_data( gem1__intr_dis_pq4, val_gem1__intr_dis_pq4); set_reset_data( gem1__intr_dis_pq5, val_gem1__intr_dis_pq5); set_reset_data( gem1__intr_dis_pq6, val_gem1__intr_dis_pq6); set_reset_data( gem1__intr_dis_pq7, val_gem1__intr_dis_pq7); set_reset_data( gem1__intr_mask_pq1, val_gem1__intr_mask_pq1); set_reset_data( gem1__intr_mask_pq2, val_gem1__intr_mask_pq2); set_reset_data( gem1__intr_mask_pq3, val_gem1__intr_mask_pq3); set_reset_data( gem1__intr_mask_pq4, val_gem1__intr_mask_pq4); set_reset_data( gem1__intr_mask_pq5, val_gem1__intr_mask_pq5); set_reset_data( gem1__intr_mask_pq6, val_gem1__intr_mask_pq6); set_reset_data( gem1__intr_mask_pq7, val_gem1__intr_mask_pq7); // ************************************************************ // Module gpio gpio // doc version: // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( gpio__MASK_DATA_0_LSW, val_gpio__MASK_DATA_0_LSW); set_reset_data( gpio__MASK_DATA_0_MSW, val_gpio__MASK_DATA_0_MSW); set_reset_data( gpio__MASK_DATA_1_LSW, val_gpio__MASK_DATA_1_LSW); set_reset_data( gpio__MASK_DATA_1_MSW, val_gpio__MASK_DATA_1_MSW); set_reset_data( gpio__MASK_DATA_2_LSW, val_gpio__MASK_DATA_2_LSW); set_reset_data( gpio__MASK_DATA_2_MSW, val_gpio__MASK_DATA_2_MSW); set_reset_data( gpio__MASK_DATA_3_LSW, val_gpio__MASK_DATA_3_LSW); set_reset_data( gpio__MASK_DATA_3_MSW, val_gpio__MASK_DATA_3_MSW); set_reset_data( gpio__DATA_0, val_gpio__DATA_0); set_reset_data( gpio__DATA_1, val_gpio__DATA_1); set_reset_data( gpio__DATA_2, val_gpio__DATA_2); set_reset_data( gpio__DATA_3, val_gpio__DATA_3); set_reset_data( gpio__DATA_0_RO, val_gpio__DATA_0_RO); set_reset_data( gpio__DATA_1_RO, val_gpio__DATA_1_RO); set_reset_data( gpio__DATA_2_RO, val_gpio__DATA_2_RO); set_reset_data( gpio__DATA_3_RO, val_gpio__DATA_3_RO); set_reset_data( gpio__BYPM_0, val_gpio__BYPM_0); set_reset_data( gpio__DIRM_0, val_gpio__DIRM_0); set_reset_data( gpio__OEN_0, val_gpio__OEN_0); set_reset_data( gpio__INT_MASK_0, val_gpio__INT_MASK_0); set_reset_data( gpio__INT_EN_0, val_gpio__INT_EN_0); set_reset_data( gpio__INT_DIS_0, val_gpio__INT_DIS_0); set_reset_data( gpio__INT_STAT_0, val_gpio__INT_STAT_0); set_reset_data( gpio__INT_TYPE_0, val_gpio__INT_TYPE_0); set_reset_data( gpio__INT_POLARITY_0, val_gpio__INT_POLARITY_0); set_reset_data( gpio__INT_ANY_0, val_gpio__INT_ANY_0); set_reset_data( gpio__BYPM_1, val_gpio__BYPM_1); set_reset_data( gpio__DIRM_1, val_gpio__DIRM_1); set_reset_data( gpio__OEN_1, val_gpio__OEN_1); set_reset_data( gpio__INT_MASK_1, val_gpio__INT_MASK_1); set_reset_data( gpio__INT_EN_1, val_gpio__INT_EN_1); set_reset_data( gpio__INT_DIS_1, val_gpio__INT_DIS_1); set_reset_data( gpio__INT_STAT_1, val_gpio__INT_STAT_1); set_reset_data( gpio__INT_TYPE_1, val_gpio__INT_TYPE_1); set_reset_data( gpio__INT_POLARITY_1, val_gpio__INT_POLARITY_1); set_reset_data( gpio__INT_ANY_1, val_gpio__INT_ANY_1); set_reset_data( gpio__BYPM_2, val_gpio__BYPM_2); set_reset_data( gpio__DIRM_2, val_gpio__DIRM_2); set_reset_data( gpio__OEN_2, val_gpio__OEN_2); set_reset_data( gpio__INT_MASK_2, val_gpio__INT_MASK_2); set_reset_data( gpio__INT_EN_2, val_gpio__INT_EN_2); set_reset_data( gpio__INT_DIS_2, val_gpio__INT_DIS_2); set_reset_data( gpio__INT_STAT_2, val_gpio__INT_STAT_2); set_reset_data( gpio__INT_TYPE_2, val_gpio__INT_TYPE_2); set_reset_data( gpio__INT_POLARITY_2, val_gpio__INT_POLARITY_2); set_reset_data( gpio__INT_ANY_2, val_gpio__INT_ANY_2); set_reset_data( gpio__BYPM_3, val_gpio__BYPM_3); set_reset_data( gpio__DIRM_3, val_gpio__DIRM_3); set_reset_data( gpio__OEN_3, val_gpio__OEN_3); set_reset_data( gpio__INT_MASK_3, val_gpio__INT_MASK_3); set_reset_data( gpio__INT_EN_3, val_gpio__INT_EN_3); set_reset_data( gpio__INT_DIS_3, val_gpio__INT_DIS_3); set_reset_data( gpio__INT_STAT_3, val_gpio__INT_STAT_3); set_reset_data( gpio__INT_TYPE_3, val_gpio__INT_TYPE_3); set_reset_data( gpio__INT_POLARITY_3, val_gpio__INT_POLARITY_3); set_reset_data( gpio__INT_ANY_3, val_gpio__INT_ANY_3); // ************************************************************ // Module gpv_iou_switch gpv_iou_switch // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( gpv_iou_switch__Remap, val_gpv_iou_switch__Remap); set_reset_data( gpv_iou_switch__security2_sdio0, val_gpv_iou_switch__security2_sdio0); set_reset_data( gpv_iou_switch__security3_sdio1, val_gpv_iou_switch__security3_sdio1); set_reset_data( gpv_iou_switch__security4_qspi, val_gpv_iou_switch__security4_qspi); set_reset_data( gpv_iou_switch__security5_miou, val_gpv_iou_switch__security5_miou); set_reset_data( gpv_iou_switch__security6_apb_slaves, val_gpv_iou_switch__security6_apb_slaves); set_reset_data( gpv_iou_switch__security7_smc, val_gpv_iou_switch__security7_smc); set_reset_data( gpv_iou_switch__peripheral_id4, val_gpv_iou_switch__peripheral_id4); set_reset_data( gpv_iou_switch__peripheral_id5, val_gpv_iou_switch__peripheral_id5); set_reset_data( gpv_iou_switch__peripheral_id6, val_gpv_iou_switch__peripheral_id6); set_reset_data( gpv_iou_switch__peripheral_id7, val_gpv_iou_switch__peripheral_id7); set_reset_data( gpv_iou_switch__peripheral_id0, val_gpv_iou_switch__peripheral_id0); set_reset_data( gpv_iou_switch__peripheral_id1, val_gpv_iou_switch__peripheral_id1); set_reset_data( gpv_iou_switch__peripheral_id2, val_gpv_iou_switch__peripheral_id2); set_reset_data( gpv_iou_switch__peripheral_id3, val_gpv_iou_switch__peripheral_id3); set_reset_data( gpv_iou_switch__component_id0, val_gpv_iou_switch__component_id0); set_reset_data( gpv_iou_switch__component_id1, val_gpv_iou_switch__component_id1); set_reset_data( gpv_iou_switch__component_id2, val_gpv_iou_switch__component_id2); set_reset_data( gpv_iou_switch__component_id3, val_gpv_iou_switch__component_id3); set_reset_data( gpv_iou_switch__fn_mod_bm_iss_sdio0, val_gpv_iou_switch__fn_mod_bm_iss_sdio0); set_reset_data( gpv_iou_switch__ahb_cntl_sdio0, val_gpv_iou_switch__ahb_cntl_sdio0); set_reset_data( gpv_iou_switch__fn_mod_bm_iss_sdio1, val_gpv_iou_switch__fn_mod_bm_iss_sdio1); set_reset_data( gpv_iou_switch__ahb_cntl_sdio1, val_gpv_iou_switch__ahb_cntl_sdio1); set_reset_data( gpv_iou_switch__fn_mod_bm_iss_qspi, val_gpv_iou_switch__fn_mod_bm_iss_qspi); set_reset_data( gpv_iou_switch__fn_mod_bm_iss_miou, val_gpv_iou_switch__fn_mod_bm_iss_miou); set_reset_data( gpv_iou_switch__fn_mod_bm_iss_smc, val_gpv_iou_switch__fn_mod_bm_iss_smc); set_reset_data( gpv_iou_switch__fn_mod_ahb_gem0, val_gpv_iou_switch__fn_mod_ahb_gem0); set_reset_data( gpv_iou_switch__read_qos_gem0, val_gpv_iou_switch__read_qos_gem0); set_reset_data( gpv_iou_switch__write_qos_gem0, val_gpv_iou_switch__write_qos_gem0); set_reset_data( gpv_iou_switch__fn_mod_iss_gem0, val_gpv_iou_switch__fn_mod_iss_gem0); set_reset_data( gpv_iou_switch__fn_mod_ahb_gem1, val_gpv_iou_switch__fn_mod_ahb_gem1); set_reset_data( gpv_iou_switch__read_qos_gem1, val_gpv_iou_switch__read_qos_gem1); set_reset_data( gpv_iou_switch__write_qos_gem1, val_gpv_iou_switch__write_qos_gem1); set_reset_data( gpv_iou_switch__fn_mod_iss_gem1, val_gpv_iou_switch__fn_mod_iss_gem1); set_reset_data( gpv_iou_switch__fn_mod_ahb_usb0, val_gpv_iou_switch__fn_mod_ahb_usb0); set_reset_data( gpv_iou_switch__read_qos_usb0, val_gpv_iou_switch__read_qos_usb0); set_reset_data( gpv_iou_switch__write_qos_usb0, val_gpv_iou_switch__write_qos_usb0); set_reset_data( gpv_iou_switch__fn_mod_iss_usb0, val_gpv_iou_switch__fn_mod_iss_usb0); set_reset_data( gpv_iou_switch__fn_mod_ahb_usb1, val_gpv_iou_switch__fn_mod_ahb_usb1); set_reset_data( gpv_iou_switch__read_qos_usb1, val_gpv_iou_switch__read_qos_usb1); set_reset_data( gpv_iou_switch__write_qos_usb1, val_gpv_iou_switch__write_qos_usb1); set_reset_data( gpv_iou_switch__fn_mod_iss_usb1, val_gpv_iou_switch__fn_mod_iss_usb1); set_reset_data( gpv_iou_switch__fn_mod_ahb_sdio0, val_gpv_iou_switch__fn_mod_ahb_sdio0); set_reset_data( gpv_iou_switch__read_qos_sdio0, val_gpv_iou_switch__read_qos_sdio0); set_reset_data( gpv_iou_switch__write_qos_sdio0, val_gpv_iou_switch__write_qos_sdio0); set_reset_data( gpv_iou_switch__fn_mod_iss_sdio0, val_gpv_iou_switch__fn_mod_iss_sdio0); set_reset_data( gpv_iou_switch__fn_mod_ahb_sdio1, val_gpv_iou_switch__fn_mod_ahb_sdio1); set_reset_data( gpv_iou_switch__read_qos_sdio1, val_gpv_iou_switch__read_qos_sdio1); set_reset_data( gpv_iou_switch__write_qos_sdio1, val_gpv_iou_switch__write_qos_sdio1); set_reset_data( gpv_iou_switch__fn_mod_iss_sdio1, val_gpv_iou_switch__fn_mod_iss_sdio1); set_reset_data( gpv_iou_switch__fn_mod_iss_siou, val_gpv_iou_switch__fn_mod_iss_siou); // ************************************************************ // Module gpv_qos301_cpu qos301 // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( gpv_qos301_cpu__qos_cntl, val_gpv_qos301_cpu__qos_cntl); set_reset_data( gpv_qos301_cpu__max_ot, val_gpv_qos301_cpu__max_ot); set_reset_data( gpv_qos301_cpu__max_comb_ot, val_gpv_qos301_cpu__max_comb_ot); set_reset_data( gpv_qos301_cpu__aw_p, val_gpv_qos301_cpu__aw_p); set_reset_data( gpv_qos301_cpu__aw_b, val_gpv_qos301_cpu__aw_b); set_reset_data( gpv_qos301_cpu__aw_r, val_gpv_qos301_cpu__aw_r); set_reset_data( gpv_qos301_cpu__ar_p, val_gpv_qos301_cpu__ar_p); set_reset_data( gpv_qos301_cpu__ar_b, val_gpv_qos301_cpu__ar_b); set_reset_data( gpv_qos301_cpu__ar_r, val_gpv_qos301_cpu__ar_r); // ************************************************************ // Module gpv_qos301_dmac qos301 // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( gpv_qos301_dmac__qos_cntl, val_gpv_qos301_dmac__qos_cntl); set_reset_data( gpv_qos301_dmac__max_ot, val_gpv_qos301_dmac__max_ot); set_reset_data( gpv_qos301_dmac__max_comb_ot, val_gpv_qos301_dmac__max_comb_ot); set_reset_data( gpv_qos301_dmac__aw_p, val_gpv_qos301_dmac__aw_p); set_reset_data( gpv_qos301_dmac__aw_b, val_gpv_qos301_dmac__aw_b); set_reset_data( gpv_qos301_dmac__aw_r, val_gpv_qos301_dmac__aw_r); set_reset_data( gpv_qos301_dmac__ar_p, val_gpv_qos301_dmac__ar_p); set_reset_data( gpv_qos301_dmac__ar_b, val_gpv_qos301_dmac__ar_b); set_reset_data( gpv_qos301_dmac__ar_r, val_gpv_qos301_dmac__ar_r); // ************************************************************ // Module gpv_qos301_iou qos301 // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( gpv_qos301_iou__qos_cntl, val_gpv_qos301_iou__qos_cntl); set_reset_data( gpv_qos301_iou__max_ot, val_gpv_qos301_iou__max_ot); set_reset_data( gpv_qos301_iou__max_comb_ot, val_gpv_qos301_iou__max_comb_ot); set_reset_data( gpv_qos301_iou__aw_p, val_gpv_qos301_iou__aw_p); set_reset_data( gpv_qos301_iou__aw_b, val_gpv_qos301_iou__aw_b); set_reset_data( gpv_qos301_iou__aw_r, val_gpv_qos301_iou__aw_r); set_reset_data( gpv_qos301_iou__ar_p, val_gpv_qos301_iou__ar_p); set_reset_data( gpv_qos301_iou__ar_b, val_gpv_qos301_iou__ar_b); set_reset_data( gpv_qos301_iou__ar_r, val_gpv_qos301_iou__ar_r); // ************************************************************ // Module gpv_trustzone nic301_addr_region_ctrl_registers // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( gpv_trustzone__Remap, val_gpv_trustzone__Remap); set_reset_data( gpv_trustzone__security_fssw_s0, val_gpv_trustzone__security_fssw_s0); set_reset_data( gpv_trustzone__security_fssw_s1, val_gpv_trustzone__security_fssw_s1); set_reset_data( gpv_trustzone__security_apb, val_gpv_trustzone__security_apb); // ************************************************************ // Module i2c0 IIC // doc version: 1.2 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( i2c0__Control_reg0, val_i2c0__Control_reg0); set_reset_data( i2c0__Status_reg0, val_i2c0__Status_reg0); set_reset_data( i2c0__I2C_address_reg0, val_i2c0__I2C_address_reg0); set_reset_data( i2c0__I2C_data_reg0, val_i2c0__I2C_data_reg0); set_reset_data( i2c0__Interrupt_status_reg0, val_i2c0__Interrupt_status_reg0); set_reset_data( i2c0__Transfer_size_reg0, val_i2c0__Transfer_size_reg0); set_reset_data( i2c0__Slave_mon_pause_reg0, val_i2c0__Slave_mon_pause_reg0); set_reset_data( i2c0__Time_out_reg0, val_i2c0__Time_out_reg0); set_reset_data( i2c0__Intrpt_mask_reg0, val_i2c0__Intrpt_mask_reg0); set_reset_data( i2c0__Intrpt_enable_reg0, val_i2c0__Intrpt_enable_reg0); set_reset_data( i2c0__Intrpt_disable_reg0, val_i2c0__Intrpt_disable_reg0); // ************************************************************ // Module i2c1 IIC // doc version: 1.2 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( i2c1__Control_reg0, val_i2c1__Control_reg0); set_reset_data( i2c1__Status_reg0, val_i2c1__Status_reg0); set_reset_data( i2c1__I2C_address_reg0, val_i2c1__I2C_address_reg0); set_reset_data( i2c1__I2C_data_reg0, val_i2c1__I2C_data_reg0); set_reset_data( i2c1__Interrupt_status_reg0, val_i2c1__Interrupt_status_reg0); set_reset_data( i2c1__Transfer_size_reg0, val_i2c1__Transfer_size_reg0); set_reset_data( i2c1__Slave_mon_pause_reg0, val_i2c1__Slave_mon_pause_reg0); set_reset_data( i2c1__Time_out_reg0, val_i2c1__Time_out_reg0); set_reset_data( i2c1__Intrpt_mask_reg0, val_i2c1__Intrpt_mask_reg0); set_reset_data( i2c1__Intrpt_enable_reg0, val_i2c1__Intrpt_enable_reg0); set_reset_data( i2c1__Intrpt_disable_reg0, val_i2c1__Intrpt_disable_reg0); // ************************************************************ // Module l2cache L2Cpl310 // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( l2cache__reg0_cache_id, val_l2cache__reg0_cache_id); set_reset_data( l2cache__reg0_cache_type, val_l2cache__reg0_cache_type); set_reset_data( l2cache__reg1_control, val_l2cache__reg1_control); set_reset_data( l2cache__reg1_aux_control, val_l2cache__reg1_aux_control); set_reset_data( l2cache__reg1_tag_ram_control, val_l2cache__reg1_tag_ram_control); set_reset_data( l2cache__reg1_data_ram_control, val_l2cache__reg1_data_ram_control); set_reset_data( l2cache__reg2_ev_counter_ctrl, val_l2cache__reg2_ev_counter_ctrl); set_reset_data( l2cache__reg2_ev_counter1_cfg, val_l2cache__reg2_ev_counter1_cfg); set_reset_data( l2cache__reg2_ev_counter0_cfg, val_l2cache__reg2_ev_counter0_cfg); set_reset_data( l2cache__reg2_ev_counter1, val_l2cache__reg2_ev_counter1); set_reset_data( l2cache__reg2_ev_counter0, val_l2cache__reg2_ev_counter0); set_reset_data( l2cache__reg2_int_mask, val_l2cache__reg2_int_mask); set_reset_data( l2cache__reg2_int_mask_status, val_l2cache__reg2_int_mask_status); set_reset_data( l2cache__reg2_int_raw_status, val_l2cache__reg2_int_raw_status); set_reset_data( l2cache__reg2_int_clear, val_l2cache__reg2_int_clear); set_reset_data( l2cache__reg7_cache_sync, val_l2cache__reg7_cache_sync); set_reset_data( l2cache__reg7_inv_pa, val_l2cache__reg7_inv_pa); set_reset_data( l2cache__reg7_inv_way, val_l2cache__reg7_inv_way); set_reset_data( l2cache__reg7_clean_pa, val_l2cache__reg7_clean_pa); set_reset_data( l2cache__reg7_clean_index, val_l2cache__reg7_clean_index); set_reset_data( l2cache__reg7_clean_way, val_l2cache__reg7_clean_way); set_reset_data( l2cache__reg7_clean_inv_pa, val_l2cache__reg7_clean_inv_pa); set_reset_data( l2cache__reg7_clean_inv_index, val_l2cache__reg7_clean_inv_index); set_reset_data( l2cache__reg7_clean_inv_way, val_l2cache__reg7_clean_inv_way); set_reset_data( l2cache__reg9_d_lockdown0, val_l2cache__reg9_d_lockdown0); set_reset_data( l2cache__reg9_i_lockdown0, val_l2cache__reg9_i_lockdown0); set_reset_data( l2cache__reg9_d_lockdown1, val_l2cache__reg9_d_lockdown1); set_reset_data( l2cache__reg9_i_lockdown1, val_l2cache__reg9_i_lockdown1); set_reset_data( l2cache__reg9_d_lockdown2, val_l2cache__reg9_d_lockdown2); set_reset_data( l2cache__reg9_i_lockdown2, val_l2cache__reg9_i_lockdown2); set_reset_data( l2cache__reg9_d_lockdown3, val_l2cache__reg9_d_lockdown3); set_reset_data( l2cache__reg9_i_lockdown3, val_l2cache__reg9_i_lockdown3); set_reset_data( l2cache__reg9_d_lockdown4, val_l2cache__reg9_d_lockdown4); set_reset_data( l2cache__reg9_i_lockdown4, val_l2cache__reg9_i_lockdown4); set_reset_data( l2cache__reg9_d_lockdown5, val_l2cache__reg9_d_lockdown5); set_reset_data( l2cache__reg9_i_lockdown5, val_l2cache__reg9_i_lockdown5); set_reset_data( l2cache__reg9_d_lockdown6, val_l2cache__reg9_d_lockdown6); set_reset_data( l2cache__reg9_i_lockdown6, val_l2cache__reg9_i_lockdown6); set_reset_data( l2cache__reg9_d_lockdown7, val_l2cache__reg9_d_lockdown7); set_reset_data( l2cache__reg9_i_lockdown7, val_l2cache__reg9_i_lockdown7); set_reset_data( l2cache__reg9_lock_line_en, val_l2cache__reg9_lock_line_en); set_reset_data( l2cache__reg9_unlock_way, val_l2cache__reg9_unlock_way); set_reset_data( l2cache__reg12_addr_filtering_start, val_l2cache__reg12_addr_filtering_start); set_reset_data( l2cache__reg12_addr_filtering_end, val_l2cache__reg12_addr_filtering_end); set_reset_data( l2cache__reg15_debug_ctrl, val_l2cache__reg15_debug_ctrl); set_reset_data( l2cache__reg15_prefetch_ctrl, val_l2cache__reg15_prefetch_ctrl); set_reset_data( l2cache__reg15_power_ctrl, val_l2cache__reg15_power_ctrl); // ************************************************************ // Module mpcore mpcore // doc version: 1.3 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( mpcore__SCU_CONTROL_REGISTER, val_mpcore__SCU_CONTROL_REGISTER); set_reset_data( mpcore__SCU_CONFIGURATION_REGISTER, val_mpcore__SCU_CONFIGURATION_REGISTER); set_reset_data( mpcore__SCU_CPU_Power_Status_Register, val_mpcore__SCU_CPU_Power_Status_Register); set_reset_data( mpcore__SCU_Invalidate_All_Registers_in_Secure_State, val_mpcore__SCU_Invalidate_All_Registers_in_Secure_State); set_reset_data( mpcore__Filtering_Start_Address_Register, val_mpcore__Filtering_Start_Address_Register); set_reset_data( mpcore__Filtering_End_Address_Register, val_mpcore__Filtering_End_Address_Register); set_reset_data( mpcore__SCU_Access_Control_Register_SAC, val_mpcore__SCU_Access_Control_Register_SAC); set_reset_data( mpcore__SCU_Non_secure_Access_Control_Register, val_mpcore__SCU_Non_secure_Access_Control_Register); set_reset_data( mpcore__ICCICR, val_mpcore__ICCICR); set_reset_data( mpcore__ICCPMR, val_mpcore__ICCPMR); set_reset_data( mpcore__ICCBPR, val_mpcore__ICCBPR); set_reset_data( mpcore__ICCIAR, val_mpcore__ICCIAR); set_reset_data( mpcore__ICCEOIR, val_mpcore__ICCEOIR); set_reset_data( mpcore__ICCRPR, val_mpcore__ICCRPR); set_reset_data( mpcore__ICCHPIR, val_mpcore__ICCHPIR); set_reset_data( mpcore__ICCABPR, val_mpcore__ICCABPR); set_reset_data( mpcore__ICCIDR, val_mpcore__ICCIDR); set_reset_data( mpcore__Global_Timer_Counter_Register0, val_mpcore__Global_Timer_Counter_Register0); set_reset_data( mpcore__Global_Timer_Counter_Register1, val_mpcore__Global_Timer_Counter_Register1); set_reset_data( mpcore__Global_Timer_Control_Register, val_mpcore__Global_Timer_Control_Register); set_reset_data( mpcore__Global_Timer_Interrupt_Status_Register, val_mpcore__Global_Timer_Interrupt_Status_Register); set_reset_data( mpcore__Comparator_Value_Register0, val_mpcore__Comparator_Value_Register0); set_reset_data( mpcore__Comparator_Value_Register1, val_mpcore__Comparator_Value_Register1); set_reset_data( mpcore__Auto_increment_Register, val_mpcore__Auto_increment_Register); set_reset_data( mpcore__Private_Timer_Load_Register, val_mpcore__Private_Timer_Load_Register); set_reset_data( mpcore__Private_Timer_Counter_Register, val_mpcore__Private_Timer_Counter_Register); set_reset_data( mpcore__Private_Timer_Control_Register, val_mpcore__Private_Timer_Control_Register); set_reset_data( mpcore__Private_Timer_Interrupt_Status_Register, val_mpcore__Private_Timer_Interrupt_Status_Register); set_reset_data( mpcore__Watchdog_Load_Register, val_mpcore__Watchdog_Load_Register); set_reset_data( mpcore__Watchdog_Counter_Register, val_mpcore__Watchdog_Counter_Register); set_reset_data( mpcore__Watchdog_Control_Register, val_mpcore__Watchdog_Control_Register); set_reset_data( mpcore__Watchdog_Interrupt_Status_Register, val_mpcore__Watchdog_Interrupt_Status_Register); set_reset_data( mpcore__Watchdog_Reset_Status_Register, val_mpcore__Watchdog_Reset_Status_Register); set_reset_data( mpcore__Watchdog_Disable_Register, val_mpcore__Watchdog_Disable_Register); set_reset_data( mpcore__ICDDCR, val_mpcore__ICDDCR); set_reset_data( mpcore__ICDICTR, val_mpcore__ICDICTR); set_reset_data( mpcore__ICDIIDR, val_mpcore__ICDIIDR); set_reset_data( mpcore__ICDISR0, val_mpcore__ICDISR0); set_reset_data( mpcore__ICDISR1, val_mpcore__ICDISR1); set_reset_data( mpcore__ICDISR2, val_mpcore__ICDISR2); set_reset_data( mpcore__ICDISER0, val_mpcore__ICDISER0); set_reset_data( mpcore__ICDISER1, val_mpcore__ICDISER1); set_reset_data( mpcore__ICDISER2, val_mpcore__ICDISER2); set_reset_data( mpcore__ICDICER0, val_mpcore__ICDICER0); set_reset_data( mpcore__ICDICER1, val_mpcore__ICDICER1); set_reset_data( mpcore__ICDICER2, val_mpcore__ICDICER2); set_reset_data( mpcore__ICDISPR0, val_mpcore__ICDISPR0); set_reset_data( mpcore__ICDISPR1, val_mpcore__ICDISPR1); set_reset_data( mpcore__ICDISPR2, val_mpcore__ICDISPR2); set_reset_data( mpcore__ICDICPR0, val_mpcore__ICDICPR0); set_reset_data( mpcore__ICDICPR1, val_mpcore__ICDICPR1); set_reset_data( mpcore__ICDICPR2, val_mpcore__ICDICPR2); set_reset_data( mpcore__ICDABR0, val_mpcore__ICDABR0); set_reset_data( mpcore__ICDABR1, val_mpcore__ICDABR1); set_reset_data( mpcore__ICDABR2, val_mpcore__ICDABR2); set_reset_data( mpcore__ICDIPR0, val_mpcore__ICDIPR0); set_reset_data( mpcore__ICDIPR1, val_mpcore__ICDIPR1); set_reset_data( mpcore__ICDIPR2, val_mpcore__ICDIPR2); set_reset_data( mpcore__ICDIPR3, val_mpcore__ICDIPR3); set_reset_data( mpcore__ICDIPR4, val_mpcore__ICDIPR4); set_reset_data( mpcore__ICDIPR5, val_mpcore__ICDIPR5); set_reset_data( mpcore__ICDIPR6, val_mpcore__ICDIPR6); set_reset_data( mpcore__ICDIPR7, val_mpcore__ICDIPR7); set_reset_data( mpcore__ICDIPR8, val_mpcore__ICDIPR8); set_reset_data( mpcore__ICDIPR9, val_mpcore__ICDIPR9); set_reset_data( mpcore__ICDIPR10, val_mpcore__ICDIPR10); set_reset_data( mpcore__ICDIPR11, val_mpcore__ICDIPR11); set_reset_data( mpcore__ICDIPR12, val_mpcore__ICDIPR12); set_reset_data( mpcore__ICDIPR13, val_mpcore__ICDIPR13); set_reset_data( mpcore__ICDIPR14, val_mpcore__ICDIPR14); set_reset_data( mpcore__ICDIPR15, val_mpcore__ICDIPR15); set_reset_data( mpcore__ICDIPR16, val_mpcore__ICDIPR16); set_reset_data( mpcore__ICDIPR17, val_mpcore__ICDIPR17); set_reset_data( mpcore__ICDIPR18, val_mpcore__ICDIPR18); set_reset_data( mpcore__ICDIPR19, val_mpcore__ICDIPR19); set_reset_data( mpcore__ICDIPR20, val_mpcore__ICDIPR20); set_reset_data( mpcore__ICDIPR21, val_mpcore__ICDIPR21); set_reset_data( mpcore__ICDIPR22, val_mpcore__ICDIPR22); set_reset_data( mpcore__ICDIPR23, val_mpcore__ICDIPR23); set_reset_data( mpcore__ICDIPTR0, val_mpcore__ICDIPTR0); set_reset_data( mpcore__ICDIPTR1, val_mpcore__ICDIPTR1); set_reset_data( mpcore__ICDIPTR2, val_mpcore__ICDIPTR2); set_reset_data( mpcore__ICDIPTR3, val_mpcore__ICDIPTR3); set_reset_data( mpcore__ICDIPTR4, val_mpcore__ICDIPTR4); set_reset_data( mpcore__ICDIPTR5, val_mpcore__ICDIPTR5); set_reset_data( mpcore__ICDIPTR6, val_mpcore__ICDIPTR6); set_reset_data( mpcore__ICDIPTR7, val_mpcore__ICDIPTR7); set_reset_data( mpcore__ICDIPTR8, val_mpcore__ICDIPTR8); set_reset_data( mpcore__ICDIPTR9, val_mpcore__ICDIPTR9); set_reset_data( mpcore__ICDIPTR10, val_mpcore__ICDIPTR10); set_reset_data( mpcore__ICDIPTR11, val_mpcore__ICDIPTR11); set_reset_data( mpcore__ICDIPTR12, val_mpcore__ICDIPTR12); set_reset_data( mpcore__ICDIPTR13, val_mpcore__ICDIPTR13); set_reset_data( mpcore__ICDIPTR14, val_mpcore__ICDIPTR14); set_reset_data( mpcore__ICDIPTR15, val_mpcore__ICDIPTR15); set_reset_data( mpcore__ICDIPTR16, val_mpcore__ICDIPTR16); set_reset_data( mpcore__ICDIPTR17, val_mpcore__ICDIPTR17); set_reset_data( mpcore__ICDIPTR18, val_mpcore__ICDIPTR18); set_reset_data( mpcore__ICDIPTR19, val_mpcore__ICDIPTR19); set_reset_data( mpcore__ICDIPTR20, val_mpcore__ICDIPTR20); set_reset_data( mpcore__ICDIPTR21, val_mpcore__ICDIPTR21); set_reset_data( mpcore__ICDIPTR22, val_mpcore__ICDIPTR22); set_reset_data( mpcore__ICDIPTR23, val_mpcore__ICDIPTR23); set_reset_data( mpcore__ICDICFR0, val_mpcore__ICDICFR0); set_reset_data( mpcore__ICDICFR1, val_mpcore__ICDICFR1); set_reset_data( mpcore__ICDICFR2, val_mpcore__ICDICFR2); set_reset_data( mpcore__ICDICFR3, val_mpcore__ICDICFR3); set_reset_data( mpcore__ICDICFR4, val_mpcore__ICDICFR4); set_reset_data( mpcore__ICDICFR5, val_mpcore__ICDICFR5); set_reset_data( mpcore__ppi_status, val_mpcore__ppi_status); set_reset_data( mpcore__spi_status_0, val_mpcore__spi_status_0); set_reset_data( mpcore__spi_status_1, val_mpcore__spi_status_1); set_reset_data( mpcore__ICDSGIR, val_mpcore__ICDSGIR); set_reset_data( mpcore__ICPIDR4, val_mpcore__ICPIDR4); set_reset_data( mpcore__ICPIDR5, val_mpcore__ICPIDR5); set_reset_data( mpcore__ICPIDR6, val_mpcore__ICPIDR6); set_reset_data( mpcore__ICPIDR7, val_mpcore__ICPIDR7); set_reset_data( mpcore__ICPIDR0, val_mpcore__ICPIDR0); set_reset_data( mpcore__ICPIDR1, val_mpcore__ICPIDR1); set_reset_data( mpcore__ICPIDR2, val_mpcore__ICPIDR2); set_reset_data( mpcore__ICPIDR3, val_mpcore__ICPIDR3); set_reset_data( mpcore__ICCIDR0, val_mpcore__ICCIDR0); set_reset_data( mpcore__ICCIDR1, val_mpcore__ICCIDR1); set_reset_data( mpcore__ICCIDR2, val_mpcore__ICCIDR2); set_reset_data( mpcore__ICCIDR3, val_mpcore__ICCIDR3); // ************************************************************ // Module ocm ocm // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( ocm__OCM_PARITY_CTRL, val_ocm__OCM_PARITY_CTRL); set_reset_data( ocm__OCM_PARITY_ERRADDRESS, val_ocm__OCM_PARITY_ERRADDRESS); set_reset_data( ocm__OCM_IRQ_STS, val_ocm__OCM_IRQ_STS); set_reset_data( ocm__OCM_CONTROL, val_ocm__OCM_CONTROL); // ************************************************************ // Module qspi qspi // doc version: 0.8, based on 11/01/10 Linear Quad-SPI Controller /// Design Specification document // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( qspi__Config_reg, val_qspi__Config_reg); set_reset_data( qspi__Intr_status_REG, val_qspi__Intr_status_REG); set_reset_data( qspi__Intrpt_en_REG, val_qspi__Intrpt_en_REG); set_reset_data( qspi__Intrpt_dis_REG, val_qspi__Intrpt_dis_REG); set_reset_data( qspi__Intrpt_mask_REG, val_qspi__Intrpt_mask_REG); set_reset_data( qspi__En_REG, val_qspi__En_REG); set_reset_data( qspi__Delay_REG, val_qspi__Delay_REG); set_reset_data( qspi__TXD0, val_qspi__TXD0); set_reset_data( qspi__Rx_data_REG, val_qspi__Rx_data_REG); set_reset_data( qspi__Slave_Idle_count_REG, val_qspi__Slave_Idle_count_REG); set_reset_data( qspi__TX_thres_REG, val_qspi__TX_thres_REG); set_reset_data( qspi__RX_thres_REG, val_qspi__RX_thres_REG); set_reset_data( qspi__GPIO, val_qspi__GPIO); set_reset_data( qspi__LPBK_DLY_ADJ, val_qspi__LPBK_DLY_ADJ); set_reset_data( qspi__TXD1, val_qspi__TXD1); set_reset_data( qspi__TXD2, val_qspi__TXD2); set_reset_data( qspi__TXD3, val_qspi__TXD3); set_reset_data( qspi__LQSPI_CFG, val_qspi__LQSPI_CFG); set_reset_data( qspi__LQSPI_STS, val_qspi__LQSPI_STS); set_reset_data( qspi__MOD_ID, val_qspi__MOD_ID); // ************************************************************ // Module sd0 sdio // doc version: 4.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( sd0__SDMA_system_address_register, val_sd0__SDMA_system_address_register); set_reset_data( sd0__Block_Size_Block_Count, val_sd0__Block_Size_Block_Count); set_reset_data( sd0__Argument, val_sd0__Argument); set_reset_data( sd0__Transfer_Mode_Command, val_sd0__Transfer_Mode_Command); set_reset_data( sd0__Response0, val_sd0__Response0); set_reset_data( sd0__Response1, val_sd0__Response1); set_reset_data( sd0__Response2, val_sd0__Response2); set_reset_data( sd0__Response3, val_sd0__Response3); set_reset_data( sd0__Buffer_Data_Port, val_sd0__Buffer_Data_Port); set_reset_data( sd0__Present_State, val_sd0__Present_State); set_reset_data( sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control, val_sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control); set_reset_data( sd0__Clock_Control_Timeout_control_Software_reset, val_sd0__Clock_Control_Timeout_control_Software_reset); set_reset_data( sd0__Normal_interrupt_status_Error_interrupt_status, val_sd0__Normal_interrupt_status_Error_interrupt_status); set_reset_data( sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable, val_sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable); set_reset_data( sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable, val_sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable); set_reset_data( sd0__Auto_CMD12_error_status, val_sd0__Auto_CMD12_error_status); set_reset_data( sd0__Capabilities, val_sd0__Capabilities); set_reset_data( sd0__Maximum_current_capabilities, val_sd0__Maximum_current_capabilities); set_reset_data( sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status, val_sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status); set_reset_data( sd0__ADMA_error_status, val_sd0__ADMA_error_status); set_reset_data( sd0__ADMA_system_address, val_sd0__ADMA_system_address); set_reset_data( sd0__Boot_Timeout_control, val_sd0__Boot_Timeout_control); set_reset_data( sd0__Debug_Selection, val_sd0__Debug_Selection); set_reset_data( sd0__SPI_interrupt_support, val_sd0__SPI_interrupt_support); set_reset_data( sd0__Slot_interrupt_status_Host_controller_version, val_sd0__Slot_interrupt_status_Host_controller_version); // ************************************************************ // Module sd1 sdio // doc version: 4.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( sd1__SDMA_system_address_register, val_sd1__SDMA_system_address_register); set_reset_data( sd1__Block_Size_Block_Count, val_sd1__Block_Size_Block_Count); set_reset_data( sd1__Argument, val_sd1__Argument); set_reset_data( sd1__Transfer_Mode_Command, val_sd1__Transfer_Mode_Command); set_reset_data( sd1__Response0, val_sd1__Response0); set_reset_data( sd1__Response1, val_sd1__Response1); set_reset_data( sd1__Response2, val_sd1__Response2); set_reset_data( sd1__Response3, val_sd1__Response3); set_reset_data( sd1__Buffer_Data_Port, val_sd1__Buffer_Data_Port); set_reset_data( sd1__Present_State, val_sd1__Present_State); set_reset_data( sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control, val_sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control); set_reset_data( sd1__Clock_Control_Timeout_control_Software_reset, val_sd1__Clock_Control_Timeout_control_Software_reset); set_reset_data( sd1__Normal_interrupt_status_Error_interrupt_status, val_sd1__Normal_interrupt_status_Error_interrupt_status); set_reset_data( sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable, val_sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable); set_reset_data( sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable, val_sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable); set_reset_data( sd1__Auto_CMD12_error_status, val_sd1__Auto_CMD12_error_status); set_reset_data( sd1__Capabilities, val_sd1__Capabilities); set_reset_data( sd1__Maximum_current_capabilities, val_sd1__Maximum_current_capabilities); set_reset_data( sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status, val_sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status); set_reset_data( sd1__ADMA_error_status, val_sd1__ADMA_error_status); set_reset_data( sd1__ADMA_system_address, val_sd1__ADMA_system_address); set_reset_data( sd1__Boot_Timeout_control, val_sd1__Boot_Timeout_control); set_reset_data( sd1__Debug_Selection, val_sd1__Debug_Selection); set_reset_data( sd1__SPI_interrupt_support, val_sd1__SPI_interrupt_support); set_reset_data( sd1__Slot_interrupt_status_Host_controller_version, val_sd1__Slot_interrupt_status_Host_controller_version); // ************************************************************ // Module slcr slcr // doc version: 1.3, based on 11/18/2010 SLCR_spec.doc // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( slcr__SCL, val_slcr__SCL); set_reset_data( slcr__SLCR_LOCK, val_slcr__SLCR_LOCK); set_reset_data( slcr__SLCR_UNLOCK, val_slcr__SLCR_UNLOCK); set_reset_data( slcr__SLCR_LOCKSTA, val_slcr__SLCR_LOCKSTA); set_reset_data( slcr__ARM_PLL_CTRL, val_slcr__ARM_PLL_CTRL); set_reset_data( slcr__DDR_PLL_CTRL, val_slcr__DDR_PLL_CTRL); set_reset_data( slcr__IO_PLL_CTRL, val_slcr__IO_PLL_CTRL); set_reset_data( slcr__PLL_STATUS, val_slcr__PLL_STATUS); set_reset_data( slcr__ARM_PLL_CFG, val_slcr__ARM_PLL_CFG); set_reset_data( slcr__DDR_PLL_CFG, val_slcr__DDR_PLL_CFG); set_reset_data( slcr__IO_PLL_CFG, val_slcr__IO_PLL_CFG); set_reset_data( slcr__PLL_BG_CTRL, val_slcr__PLL_BG_CTRL); set_reset_data( slcr__ARM_CLK_CTRL, val_slcr__ARM_CLK_CTRL); set_reset_data( slcr__DDR_CLK_CTRL, val_slcr__DDR_CLK_CTRL); set_reset_data( slcr__DCI_CLK_CTRL, val_slcr__DCI_CLK_CTRL); set_reset_data( slcr__APER_CLK_CTRL, val_slcr__APER_CLK_CTRL); set_reset_data( slcr__USB0_CLK_CTRL, val_slcr__USB0_CLK_CTRL); set_reset_data( slcr__USB1_CLK_CTRL, val_slcr__USB1_CLK_CTRL); set_reset_data( slcr__GEM0_RCLK_CTRL, val_slcr__GEM0_RCLK_CTRL); set_reset_data( slcr__GEM1_RCLK_CTRL, val_slcr__GEM1_RCLK_CTRL); set_reset_data( slcr__GEM0_CLK_CTRL, val_slcr__GEM0_CLK_CTRL); set_reset_data( slcr__GEM1_CLK_CTRL, val_slcr__GEM1_CLK_CTRL); set_reset_data( slcr__SMC_CLK_CTRL, val_slcr__SMC_CLK_CTRL); set_reset_data( slcr__LQSPI_CLK_CTRL, val_slcr__LQSPI_CLK_CTRL); set_reset_data( slcr__SDIO_CLK_CTRL, val_slcr__SDIO_CLK_CTRL); set_reset_data( slcr__UART_CLK_CTRL, val_slcr__UART_CLK_CTRL); set_reset_data( slcr__SPI_CLK_CTRL, val_slcr__SPI_CLK_CTRL); set_reset_data( slcr__CAN_CLK_CTRL, val_slcr__CAN_CLK_CTRL); set_reset_data( slcr__CAN_MIOCLK_CTRL, val_slcr__CAN_MIOCLK_CTRL); set_reset_data( slcr__DBG_CLK_CTRL, val_slcr__DBG_CLK_CTRL); set_reset_data( slcr__PCAP_CLK_CTRL, val_slcr__PCAP_CLK_CTRL); set_reset_data( slcr__TOPSW_CLK_CTRL, val_slcr__TOPSW_CLK_CTRL); set_reset_data( slcr__FPGA0_CLK_CTRL, val_slcr__FPGA0_CLK_CTRL); set_reset_data( slcr__FPGA0_THR_CTRL, val_slcr__FPGA0_THR_CTRL); set_reset_data( slcr__FPGA0_THR_CNT, val_slcr__FPGA0_THR_CNT); set_reset_data( slcr__FPGA0_THR_STA, val_slcr__FPGA0_THR_STA); set_reset_data( slcr__FPGA1_CLK_CTRL, val_slcr__FPGA1_CLK_CTRL); set_reset_data( slcr__FPGA1_THR_CTRL, val_slcr__FPGA1_THR_CTRL); set_reset_data( slcr__FPGA1_THR_CNT, val_slcr__FPGA1_THR_CNT); set_reset_data( slcr__FPGA1_THR_STA, val_slcr__FPGA1_THR_STA); set_reset_data( slcr__FPGA2_CLK_CTRL, val_slcr__FPGA2_CLK_CTRL); set_reset_data( slcr__FPGA2_THR_CTRL, val_slcr__FPGA2_THR_CTRL); set_reset_data( slcr__FPGA2_THR_CNT, val_slcr__FPGA2_THR_CNT); set_reset_data( slcr__FPGA2_THR_STA, val_slcr__FPGA2_THR_STA); set_reset_data( slcr__FPGA3_CLK_CTRL, val_slcr__FPGA3_CLK_CTRL); set_reset_data( slcr__FPGA3_THR_CTRL, val_slcr__FPGA3_THR_CTRL); set_reset_data( slcr__FPGA3_THR_CNT, val_slcr__FPGA3_THR_CNT); set_reset_data( slcr__FPGA3_THR_STA, val_slcr__FPGA3_THR_STA); set_reset_data( slcr__SRST_UART_CTRL, val_slcr__SRST_UART_CTRL); set_reset_data( slcr__BANDGAP_TRIM, val_slcr__BANDGAP_TRIM); set_reset_data( slcr__CC_TEST, val_slcr__CC_TEST); set_reset_data( slcr__PLL_'b'PREDIVISOR, val_slcr__PLL_PREDIVISOR); set_reset_data( slcr__CLK_621_TRUE, val_slcr__CLK_621_TRUE); set_reset_data( slcr__PICTURE_DBG, val_slcr__PICTURE_DBG); set_reset_data( slcr__PICTURE_DBG_UCNT, val_slcr__PICTURE_DBG_UCNT); set_reset_data( slcr__PICTURE_DBG_LCNT, val_slcr__PICTURE_DBG_LCNT); set_reset_data( slcr__PSS_RST_CTRL, val_slcr__PSS_RST_CTRL); set_reset_data( slcr__DDR_RST_CTRL, val_slcr__DDR_RST_CTRL); set_reset_data( slcr__TOPSW_RST_CTRL, val_slcr__TOPSW_RST_CTRL); set_reset_data( slcr__DMAC_RST_CTRL, val_slcr__DMAC_RST_CTRL); set_reset_data( slcr__USB_RST_CTRL, val_slcr__USB_RST_CTRL); set_reset_data( slcr__GEM_RST_CTRL, val_slcr__GEM_RST_CTRL); set_reset_data( slcr__SDIO_RST_CTRL, val_slcr__SDIO_RST_CTRL); set_reset_data( slcr__SPI_RST_CTRL, val_slcr__SPI_RST_CTRL); set_reset_data( slcr__CAN_RST_CTRL, val_slcr__CAN_RST_CTRL); set_reset_data( slcr__I2C_RST_CTRL, val_slcr__I2C_RST_CTRL); set_reset_data( slcr__UART_RST_CTRL, val_slcr__UART_RST_CTRL); set_reset_data( slcr__GPIO_RST_CTRL, val_slcr__GPIO_RST_CTRL); set_reset_data( slcr__LQSPI_RST_CTRL, val_slcr__LQSPI_RST_CTRL); set_reset_data( slcr__SMC_RST_CTRL, val_slcr__SMC_RST_CTRL); set_reset_data( slcr__OCM_RST_CTRL, val_slcr__OCM_RST_CTRL); set_reset_data( slcr__DEVCI_RST_CTRL, val_slcr__DEVCI_RST_CTRL); set_reset_data( slcr__FPGA_RST_CTRL, val_slcr__FPGA_RST_CTRL); set_reset_data( slcr__A9_CPU_RST_CTRL, val_slcr__A9_CPU_RST_CTRL); set_reset_data( slcr__RS_AWDT_CTRL, val_slcr__RS_AWDT_CTRL); set_reset_data( slcr__RST_REASON, val_slcr__RST_REASON); set_reset_data( slcr__RST_REASON_CLR, val_slcr__RST_REASON_CLR); set_reset_data( slcr__REBOOT_STATUS, val_slcr__REBOOT_STATUS); set_reset_data( slcr__BOOT_MODE, val_slcr__BOOT_MODE); set_reset_data( slcr__APU_CTRL, val_slcr__APU_CTRL); set_reset_data( slcr__WDT_CLK_SEL, val_slcr__WDT_CLK_SEL); set_reset_data( slcr__TZ_OCM_RAM0, val_slcr__TZ_OCM_RAM0); set_reset_data( slcr__TZ_OCM_RAM1, val_slcr__TZ_OCM_RAM1); set_reset_data( slcr__TZ_OCM_ROM, val_slcr__TZ_OCM_ROM); set_reset_data( slcr__TZ_DDR_RAM, val_slcr__TZ_DDR_RAM); set_reset_data( slcr__TZ_DMA_NS, val_slcr__TZ_DMA_NS); set_reset_data( slcr__TZ_DMA_IRQ_NS, val_slcr__TZ_DMA_IRQ_NS); set_reset_data( slcr__TZ_DMA_PERIPH_NS, val_slcr__TZ_DMA_PERIPH_NS); set_reset_data( slcr__TZ_GEM, val_slcr__TZ_GEM); set_reset_data( slcr__TZ_SDIO, val_slcr__TZ_SDIO); set_reset_data( slcr__TZ_USB, val_slcr__TZ_USB); set_reset_data( slcr__TZ_FPGA_M, val_slcr__TZ_FPGA_M); set_reset_data( slcr__TZ_FPGA_AFI, val_slcr__TZ_FPGA_AFI); set_reset_data( slcr__DBG_CTRL, val_slcr__DBG_CTRL); set_reset_data( slcr__PSS_IDCODE, val_slcr__PSS_IDCODE); set_reset_data( slcr__DDR_URGENT, val_slcr__DDR_URGENT); set_reset_data( slcr__DDR_CAL_START, val_slcr__DDR_CAL_START); set_reset_data( slcr__DDR_REF_START, val_slcr__DDR_REF_START); set_reset_data( slcr__DDR_CMD_STA, val_slcr__DDR_CMD_STA); set_reset_data( slcr__DDR_URGENT_SEL, val_slcr__DDR_URGENT_SEL); set_reset_data( slcr__DDR_DFI_STATUS, val_slcr__DDR_DFI_STATUS); set_reset_data( slcr__MIO_PIN_00, val_slcr__MIO_PIN_00); set_reset_data( slcr__MIO_PIN_01, val_slcr__MIO_PIN_01); set_reset_data( slcr__MIO_PIN_02, val_slcr__MIO_PIN_02); set_reset_data( slcr__MIO_PIN_03, val_slcr__MIO_PIN_03); set_reset_data( slcr__MIO_PIN_04, val_slcr__MIO_PIN_04); set_reset_data( slcr__MIO_PIN_05, val_slcr__MIO_PIN_05); set_reset_data( slcr__MIO_PIN_06, val_slcr__MIO_PIN_06); set_reset_data( slcr__MIO_PIN_07, val_slcr__MIO_PIN_07); set_reset_data( slcr__MIO_PIN_08, val_slcr__MIO_PIN_08); set_reset_data( slcr__MIO_PIN_09, val_slcr__MIO_PIN_09); set_reset_data( slcr__MIO_PIN_10, val_slcr__MIO_PIN_10); set_reset_data( slcr__MIO_PIN_11, val_slcr__MIO_PIN_11); set_reset_data( slcr__MIO_PIN_12, val_slcr__MIO_PIN_12); set_reset_data( slcr__MIO_PIN_13, val_slcr__MIO_PIN_13); set_reset_data( slcr__MIO_PIN_14, val_slcr__MIO_PIN_14); set_reset_data( slcr__MIO_PIN_15, val_slcr__MIO_PIN_15); set_reset_data( slcr__MIO_PIN_16, val_slcr__MIO_PIN_16); set_reset_data( slcr__MIO_PIN_17, val_slcr__MIO_PIN_17); set_reset_data( slcr__MIO_PIN_18, val_slcr__MIO_PIN_18); set_reset_data( slcr__MIO_PIN_19, val_slcr__MIO_PIN_19); set_reset_data( slcr__MIO_PIN_20, val_slcr__MIO_PIN_20); set_reset_data( slcr__MIO_PIN_21, val_slcr__MIO_PIN_21); set_reset_data( slcr__MIO_PIN_22, val_slcr__MIO_PIN_22); set_reset_data( slcr__MIO_PIN_23, val_slcr__MIO_PIN_23); set_reset_data( slcr__MIO_PIN_24, val_slcr__MIO_PIN_24); set_reset_data( slcr__MIO_PIN_25, val_slcr__MIO_PIN_25); set_reset_data( slcr__MIO_PIN_26, val_slcr__MIO_PIN_26); set_reset_data( slcr__MIO_PIN_27, val_slcr__MIO_PIN_27); set_reset_data( slcr__MIO_PIN_28, val_slcr__MIO_PIN_28); set_reset_data( slcr__MIO_PIN_29, val_slcr__MIO_PIN_29); set_reset_data( slcr__MIO_PIN_30, val_slcr__MIO_PIN_30); set_reset_data( slcr__MIO_PIN_31, val_slcr__MIO_PIN_31); set_reset_data( slcr__MIO_PIN_32, val_slcr__MIO_PIN_32); set_reset_data( slcr__MIO_PIN_33, val_slcr__MIO_PIN_33); set_reset_data( slcr__MIO_PIN_34, val_slcr__MIO_PIN_34); set_reset_data( slcr__MIO_PIN_35, val_slcr__MIO_PIN_35); set_reset_data( slcr__MIO_PIN_36, val_slcr__MIO_PIN_36); set_reset_data( slcr__MIO_PIN_37, val_slcr__MIO_PIN_37); set_reset_data( slcr__MIO_PIN_38, val_slcr__MIO_PIN_38); set_reset_data( slcr__MIO_PIN_39, val_slcr__MIO_PIN_39); set_reset_data( slcr__MIO_PIN_40, val_slcr__MIO_PIN_40); set_reset_data( slcr__MIO_PIN_41, val_slcr__MIO_PIN_41); set_reset_data( slcr__MIO_PIN_42, val_slcr__MIO_PIN_42); set_reset_data( slcr__MIO_PIN_43, val_slcr__MIO_PIN_43); set_reset_data( slcr__MIO_PIN_44, val_slcr__MIO_PIN_44); set_reset_data( slcr__MIO_PIN_45, val_slcr__MIO_PIN_45); set_reset_data( slcr__MIO_PIN_46, val_slcr__MIO_PIN_46); set_reset_data( slcr__MIO_PIN_47, val_slcr__MIO_PIN_47); set_reset_data( slcr__MIO_PIN_48, val_slcr__MIO_PIN_48); set_reset_data( slcr__MIO_PIN_49, val_slcr__MIO_PIN_49); set_reset_data( slcr__MIO_PIN_50, val_slcr__MIO_PIN_50); set_reset_data( slcr__MIO_PIN_51, val_slcr__MIO_PIN_51); set_reset_data( slcr__MIO_PIN_52, val_slcr__MIO_PIN_52); set_reset_data( slcr__MIO_PIN_53, val_slcr__MIO_PIN_53); set_reset_data( slcr__MIO_FMIO_GEM_SEL, val_slcr__MIO_FMIO_GEM_SEL); set_reset_data( slcr__MIO_LOOPBACK, val_slcr__MIO_LOOPBACK); set_reset_data( slcr__MIO_MST_TRI0, val_slcr__MIO_MST_TRI0); set_reset_data( slcr__MIO_MST_TRI1, val_slcr__MIO_MST_TRI1); set_reset_data( slcr__SD0_WP_CD_SEL, val_slcr__SD0_WP_CD_SEL); set_reset_data( slcr__SD1_WP_CD_SEL, val_slcr__SD1_WP_CD_SEL); set_reset_data( slcr__LVL_SHFTR_EN, val_slcr__LVL_SHFTR_EN); set_reset_data( slcr__OCM_CFG, val_slcr__OCM_CFG); set_reset_data( slcr__CPU0_RAM0, val_slcr__CPU0_RAM0); set_reset_data( slcr__CPU0_RAM1, val_slcr__CPU0_RAM1); set_reset_data( slcr__CPU0_RAM2, val_slcr__CPU0_RAM2); set_reset_data( slcr__CPU1_RAM0, val_slcr__CPU1_RAM0); set_reset_data( slcr__CPU1_RAM1, val_slcr__CPU1_RAM1); set_reset_data( slcr__CPU1_RAM2, val_slcr__CPU1_RAM2); set_reset_data( slcr__SCU_RAM, val_slcr__SCU_RAM); set_reset_data( slcr__L2C_RAM, val_slcr__L2C_RAM); set_reset_data( slcr__IOU_RAM_GEM01, val_slcr__IOU_RAM_GEM01); set_reset_data( slcr__IOU_RAM_USB01, val_slcr__IOU_RAM_USB01); set_reset_data( slcr__IOU_RAM_SDIO0, val_slcr__IOU_RAM_SDIO0); set_reset_data( slcr__IOU_RAM_SDIO1, val_slcr__IOU_RAM_SDIO1); set_reset_data( slcr__IOU_RAM_CAN0, val_slcr__IOU_RAM_CAN0); set_reset_data( slcr__IOU_RAM_CAN1, val_slcr__IOU_RAM_CAN1); set_reset_data( slcr__IOU_RAM_LQSPI, val_slcr__IOU_RAM_LQSPI); set_reset_data( slcr__DMAC_RAM, val_slcr__DMAC_RAM); set_reset_data( slcr__AFI0_RAM0, val_slcr__AFI0_RAM0); set_reset_data( slcr__AFI0_RAM1, val_slcr__AFI0_RAM1); set_reset_data( slcr__AFI0_RAM2, val_slcr__AFI0_RAM2); set_reset_data( slcr__AFI1_RAM0, val_slcr__AFI1_RAM0); set_reset_data( slcr__AFI1_RAM1, val_slcr__AFI1_RAM1); set_reset_data( slcr__AFI1_RAM2, val_slcr__AFI1_RAM2); set_reset_data( slcr__AFI2_RAM0, val_slcr__AFI2_RAM0); set_reset_data( slcr__AFI2_RAM1, val_slcr__AFI2_RAM1); set_reset_data( slcr__AFI2_RAM2, val_slcr__AFI2_RAM2); set_reset_data( slcr__AFI3_RAM0, val_slcr__AFI3_RAM0); set_reset_data( slcr__AFI3_RAM1, val_slcr__AFI3_RAM1); set_reset_data( slcr__AFI3_RAM2, val_slcr__AFI3_RAM2); set_reset_data( slcr__OCM_RAM, val_slcr__OCM_RAM); set_reset_data( slcr__OCM_ROM0, val_slcr__OCM_ROM0); set_reset_data( slcr__OCM_ROM1, val_slcr__OCM_ROM1); set_reset_data( slcr__DEVCI_RAM, val_slcr__DEVCI_RAM); set_reset_data( slcr__CSG_RAM, val_slcr__CSG_RAM); set_reset_data( slcr__GPIOB_CTRL, val_slcr__GPIOB_CTRL); set_reset_data( slcr__GPIOB_CFG_CMOS18, val_slcr__GPIOB_CFG_CMOS18); set_reset_data( slcr__GPIOB_CFG_CMOS25, val_slcr__GPIOB_CFG_CMOS25); set_reset_data( slcr__GPIOB_CFG_CMOS33, val_slcr__GPIOB_CFG_CMOS33); set_reset_data( slcr__GPIOB_CFG_LVTTL, val_slcr__GPIOB_CFG_LVTTL); set_reset_data( slcr__GPIOB_CFG_HSTL, val_slcr__GPIOB_CFG_HSTL); set_reset_data( slcr__GPIOB_DRVR_BIAS_CTRL, val_slcr__GPIOB_DRVR_BIAS_CTRL); set_reset_data( slcr__DDRIOB_ADDR0, val_slcr__DDRIOB_ADDR0); set_reset_data( slcr__DDRIOB_ADDR1, val_slcr__DDRIOB_ADDR1); set_reset_data( slcr__DDRIOB_DATA0, val_slcr__DDRIOB_DATA0); set_reset_data( slcr__DDRIOB_DATA1, val_slcr__DDRIOB_DATA1); set_reset_data( slcr__DDRIOB_DIFF0, val_slcr__DDRIOB_DIFF0); set_reset_data( slcr__DDRIOB_DIFF1, val_slcr__DDRIOB_DIFF1); set_reset_data( slcr__DDRIOB_CLOCK, val_slcr__DDRIOB_CLOCK); set_reset_data( slcr__DDRIOB_DRIVE_SLEW_ADDR, val_slcr__DDRIOB_DRIVE_SLEW_ADDR); set_reset_data( slcr__DDRIOB_DRIVE_SLEW_DATA, val_slcr__DDRIOB_DRIVE_SLEW_DATA); set_reset_data( slcr__DDRIOB_DRIVE_SLEW_DIFF, val_slcr__DDRIOB_DRIVE_SLEW_DIFF); set_reset_data( slcr__DDRIOB_DRIVE_SLEW_CLOCK, val_slcr__DDRIOB_DRIVE_SLEW_CLOCK); set_reset_data( slcr__DDRIOB_DDR_CTRL, val_slcr__DDRIOB_DDR_CTRL); set_reset_data( slcr__DDRIOB_DCI_CTRL, val_slcr__DDRIOB_DCI_CTRL); set_reset_data( slcr__DDRIOB_DCI_STATUS, val_slcr__DDRIOB_DCI_STATUS); // ************************************************************ // Module smcc pl353 // doc version: 1.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( smcc__memc_status, val_smcc__memc_status); set_reset_data( smcc__memif_cfg, val_smcc__memif_cfg); set_reset_data( smcc__memc_cfg_set, val_smcc__memc_cfg_set); set_reset_data( smcc__memc_cfg_clr, val_smcc__memc_cfg_clr); set_reset_data( smcc__direct_cmd, val_smcc__direct_cmd); set_reset_data( smcc__set_cycles, val_smcc__set_cycles); set_reset_data( smcc__set_opmode, val_smcc__set_opmode); set_reset_data( smcc__refresh_period_0, val_smcc__refresh_period_0); set_reset_data( smcc__refresh_period_1, val_smcc__refresh_period_1); set_reset_data( smcc__sram_cycles0_0, val_smcc__sram_cycles0_0); set_reset_data( smcc__opmode0_0, val_smcc__opmode0_0); set_reset_data( smcc__sram_cycles0_1, val_smcc__sram_cycles0_1); set_reset_data( smcc__opmode0_1, val_smcc__opmode0_1); set_reset_data( smcc__nand_cycles1_0, val_smcc__nand_cycles1_0); set_reset_data( smcc__opmode1_0, val_smcc__opmode1_0); set_reset_data( smcc__user_status, val_smcc__user_status); set_reset_data( smcc__user_config, val_smcc__user_config); set_reset_data( smcc__ecc_status_0, val_smcc__ecc_status_0); set_reset_data( smcc__ecc_memcfg_0, val_smcc__ecc_memcfg_0); set_reset_data( smcc__ecc_memcommand1_0, val_smcc__ecc_memcommand1_0); set_reset_data( smcc__ecc_memcommand2_0, val_smcc__ecc_memcommand2_0); set_reset_data( smcc__ecc_addr0_0, val_smcc__ecc_addr0_0); set_reset_data( smcc__ecc_addr1_0, val_smcc__ecc_addr1_0); set_reset_data( smcc__ecc_value0_0, val_smcc__ecc_value0_0); set_reset_data( smcc__ecc_value1_0, val_smcc__ecc_value1_0); set_reset_data( smcc__ecc_value2_0, val_smcc__ecc_value2_0); set_reset_data( smcc__ecc_value3_0, val_smcc__ecc_value3_0); set_reset_data( smcc__ecc_status_1, val_smcc__ecc_status_1); set_reset_data( smcc__ecc_memcfg_1, val_smcc__ecc_memcfg_1); set_reset_data( smcc__ecc_memcommand1_1, val_smcc__ecc_memcommand1_1); set_reset_data( smcc__ecc_memcommand2_1, val_smcc__ecc_memcommand2_1); set_reset_data( smcc__ecc_addr0_1, val_smcc__ecc_addr0_1); set_reset_data( smcc__ecc_addr1_1, val_smcc__ecc_addr1_1); set_reset_data( smcc__ecc_value0_1, val_smcc__ecc_value0_1); set_reset_data( smcc__ecc_value1_1, val_smcc__ecc_value1_1); set_reset_data( smcc__ecc_value2_1, val_smcc__ecc_value2_1); set_reset_data( smcc__ecc_value3_1, val_smcc__ecc_value3_1); set_reset_data( smcc__integration_test, val_smcc__integration_test); set_reset_data( smcc__periph_id_0, val_smcc__periph_id_0); set_reset_data( smcc__periph_id_1, val_smcc__periph_id_1); set_reset_data( smcc__periph_id_2, val_smcc__periph_id_2); set_reset_data( smcc__periph_id_3, val_smcc__periph_id_3); set_reset_data( smcc__pcell_id_0, val_smcc__pcell_id_0); set_reset_data( smcc__pcell_id_1, val_smcc__pcell_id_1); set_reset_data( smcc__pcell_id_2, val_smcc__pcell_id_2); set_reset_data( smcc__pcell_id_3, val_smcc__pcell_id_3); // ************************************************************ // Module spi0 SPI // doc version: 1.2 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( spi0__Config_reg0, val_spi0__Config_reg0); set_reset_data( spi0__Intr_status_reg0, val_spi0__Intr_status_reg0); set_reset_data( spi0__Intrpt_en_reg0, val_spi0__Intrpt_en_reg0); set_reset_data( spi0__Intrpt_dis_reg0, val_spi0__Intrpt_dis_reg0); set_reset_data( spi0__Intrpt_mask_reg0, val_spi0__Intrpt_mask_reg0); set_reset_data( spi0__En_reg0, val_spi0__En_reg0); set_reset_data( spi0__Delay_reg0, val_spi0__Delay_reg0); set_reset_data( spi0__Tx_data_reg0, val_spi0__Tx_data_reg0); set_reset_data( spi0__Rx_data_reg0, val_spi0__Rx_data_reg0); set_reset_data( spi0__Slave_Idle_count_reg0, val_spi0__Slave_Idle_count_reg0); set_reset_data( spi0__TX_thres_reg0, val_spi0__TX_thres_reg0); set_reset_data( spi0__RX_thres_reg0, val_spi0__RX_thres_reg0); set_reset_data( spi0__Mod_id_reg0, val_spi0__Mod_id_reg0); // ************************************************************ // Module spi1 SPI // doc version: 1.2 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( spi1__Config_reg0, val_spi1__Config_reg0); set_reset_data( spi1__Intr_status_reg0, val_spi1__Intr_status_reg0); set_reset_data( spi1__Intrpt_en_reg0, val_spi1__Intrpt_en_reg0); set_reset_data( spi1__Intrpt_dis_reg0, val_spi1__Intrpt_dis_reg0); set_reset_data( spi1__Intrpt_mask_reg0, val_spi1__Intrpt_mask_reg0); set_reset_data( spi1__En_reg0, val_spi1__En_reg0); set_reset_data( spi1__Delay_reg0, val_spi1__Delay_reg0); set_reset_data( spi1__Tx_data_reg0, val_spi1__Tx_data_reg0); set_reset_data( spi1__Rx_data_reg0, val_spi1__Rx_data_reg0); set_reset_data( spi1__Slave_Idle_count_reg0, val_spi1__Slave_Idle_count_reg0); set_reset_data( spi1__TX_thres_reg0, val_spi1__TX_thres_reg0); set_reset_data( spi1__RX_thres_reg0, val_spi1__RX_thres_reg0); set_reset_data( spi1__Mod_id_reg0, val_spi1__Mod_id_reg0); // ************************************************************ // Module swdt swdt // doc version: 2.1 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( swdt__MODE, val_swdt__MODE); set_reset_data( swdt__CONTROL, val_swdt__CONTROL); set_reset_data( swdt__RESTART, val_swdt__RESTART); set_reset_data( swdt__STATUS, val_swdt__STATUS); // ************************************************************ // Module ttc0 ttc // doc version: 2.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( ttc0__Clock_Control_1, val_ttc0__Clock_Control_1); set_reset_data( ttc0__Clock_Control_2, val_ttc0__Clock_Control_2); set_reset_data( ttc0__Clock_Control_3, val_ttc0__Clock_Control_3); set_reset_data( ttc0__Counter_Control_1, val_ttc0__Counter_Control_1); set_reset_data( ttc0__Counter_Control_2, val_ttc0__Counter_Control_2); set_reset_data( ttc0__Counter_Control_3, val_ttc0__Counter_Control_3); set_reset_data( ttc0__Counter_Value_1, val_ttc0__Counter_Value_1); set_reset_data( ttc0__Counter_Value_2, val_ttc0__Counter_Value_2); set_reset_data( ttc0__Counter_Value_3, val_ttc0__Counter_Value_3); set_reset_data( ttc0__Interval_Counter_1, val_ttc0__Interval_Counter_1); set_reset_data( ttc0__Interval_Counter_2, val_ttc0__Interval_Counter_2); set_reset_data( ttc0__Interval_Counter_3, val_ttc0__Interval_Counter_3); set_reset_data( ttc0__Match_1_Counter_1, val_ttc0__Match_1_Counter_1); set_reset_data( ttc0__Match_1_Counter_2, val_ttc0__Match_1_Counter_2); set_reset_data( ttc0__Match_1_Counter_3, val_ttc0__Match_1_Counter_3); set_reset_data( ttc0__Match_2_Counter_1, val_ttc0__Match_2_Counter_1); set_reset_data( ttc0__Match_2_Counter_2, val_ttc0__Match_2_Counter_2); set_reset_data( ttc0__Match_2_Counter_3, val_ttc0__Match_2_Counter_3); set_reset_data( ttc0__Match_3_Counter_1, val_ttc0__Match_3_Counter_1); set_reset_data( ttc0__Match_3_Counter_2, val_ttc0__Match_3_Counter_2); set_reset_data( ttc0__Match_3_Counter_3, val_ttc0__Match_3_Counter_3); set_reset_data( ttc0__Interrupt_Register_1, val_ttc0__Interrupt_Register_1); set_reset_data( ttc0__Interrupt_Register_2, val_ttc0__Interrupt_Register_2); set_reset_data( ttc0__Interrupt_Register_3, val_ttc0__Interrupt_Register_3); set_reset_data( ttc0__Interrupt_Enable_1, val_ttc0__Interrupt_Enable_1); set_reset_data( ttc0__Interrupt_Enable_2, val_ttc0__Interrupt_Enable_2); set_reset_data( ttc0__Interrupt_Enable_3, val_ttc0__Interrupt_Enable_3); set_reset_data( ttc0__Event_Control_Timer_1, val_ttc0__Event_Control_Timer_1); set_reset_data( ttc0__Event_Control_Timer_2, val_ttc0__Event_Control_Timer_2); set_reset_data( ttc0__Event_Control_Timer_3, val_ttc0__Event_Control_Timer_3); set_reset_data( ttc0__Event_Register_1, val_ttc0__Event_Register_1); set_reset_data( ttc0__Event_Register_2, val_ttc0__Event_Register_2); set_reset_data( ttc0__Event_Register_3, val_ttc0__Event_Register_3); // ************************************************************ // Module ttc1 ttc // doc version: 2.0 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( ttc1__Clock_Control_1, val_ttc1__Clock_Control_1); set_reset_data( ttc1__Clock_Control_2, val_ttc1__Clock_Control_2); set_reset_data( ttc1__Clock_Control_3, val_ttc1__Clock_Control_3); set_reset_data( ttc1__Counter_Control_1, val_ttc1__Counter_Control_1); set_reset_data( ttc1__Counter_Control_2, val_ttc1__Counter_Control_2); set_reset_data( ttc1__Counter_Control_3, val_ttc1__Counter_Control_3); set_reset_data( ttc1__Counter_Value_1, val_ttc1__Counter_Value_1); set_reset_data( ttc1__Counter_Value_2, val_ttc1__Counter_Value_2); set_reset_data( ttc1__Counter_Value_3, val_ttc1__Counter_Value_3); set_reset_data( ttc1__Interval_Counter_1, val_ttc1__Interval_Counter_1); set_reset_data( ttc1__Interval_Counter_2, val_ttc1__Interval_Counter_2); set_reset_data( ttc1__Interval_Counter_3, val_ttc1__Interval_Counter_3); set_reset_data( ttc1__Match_1_Counter_1, val_ttc1__Match_1_Counter_1); set_reset_data( ttc1__Match_1_Counter_2, val_ttc1__Match_1_Counter_2); set_reset_data( ttc1__Match_1_Counter_3, val_ttc1__Match_1_Counter_3); set_reset_data( ttc1__Match_2_Counter_1, val_ttc1__Match_2_Counter_1); set_reset_data( ttc1__Match_2_Counter_2, val_ttc1__Match_2_Counter_2); set_reset_data( ttc1__Match_2_Counter_3, val_ttc1__Match_2_Counter_3); set_reset_data( ttc1__Match_3_Counter_1, val_ttc1__Match_3_Counter_1); set_reset_data( ttc1__Match_3_Counter_2, val_ttc1__Match_3_Counter_2); set_reset_data( ttc1__Match_3_Counter_3, val_ttc1__Match_3_Counter_3); set_reset_data( ttc1__Interrupt_Register_1, val_ttc1__Interrupt_Register_1); set_reset_data( ttc1__Interrupt_Register_2, val_ttc1__Interrupt_Register_2); set_reset_data( ttc1__Interrupt_Register_3, val_ttc1__Interrupt_Register_3); set_reset_data( ttc1__Interrupt_Enable_1, val_ttc1__Interrupt_Enable_1); set_reset_data( ttc1__Interrupt_Enable_2, val_ttc1__Interrupt_Enable_2); set_reset_data( ttc1__Interrupt_Enable_3, val_ttc1__Interrupt_Enable_3); set_reset_data( ttc1__Event_Control_Timer_1, val_ttc1__Event_Control_Timer_1); set_reset_data( ttc1__Event_Control_Timer_2, val_ttc1__Event_Control_Timer_2); set_reset_data( ttc1__Event_Control_Timer_3, val_ttc1__Event_Control_Timer_3); set_reset_data( ttc1__Event_Register_1, val_ttc1__Event_Register_1); set_reset_data( ttc1__Event_Register_2, val_ttc1__Event_Register_2); set_reset_data( ttc1__Event_Register_3, val_ttc1__Event_Register_3); // ************************************************************ // Module uart0 UART // doc version: 1.2 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( uart0__Control_reg0, val_uart0__Control_reg0); set_reset_data( uart0__mode_reg0, val_uart0__mode_reg0); set_reset_data( uart0__Intrpt_en_reg0, val_uart0__Intrpt_en_reg0); set_reset_data( uart0__Intrpt_dis_reg0, val_uart0__Intrpt_dis_reg0); set_reset_data( uart0__Intrpt_mask_reg0, val_uart0__Intrpt_mask_reg0); set_reset_data( uart0__Chnl_int_sts_reg0, val_uart0__Chnl_int_sts_reg0); set_reset_data( uart0__Baud_rate_gen_reg0, val_uart0__Baud_rate_gen_reg0); set_reset_data( uart0__Rcvr_timeout_reg0, val_uart0__Rcvr_timeout_reg0); set_reset_data( uart0__Rcvr_FIFO_trigger_level0, val_uart0__Rcvr_FIFO_trigger_level0); set_reset_data( uart0__Modem_ctrl_reg0, val_uart0__Modem_ctrl_reg0); set_reset_data( uart0__Modem_sts_reg0, val_uart0__Modem_sts_reg0); set_reset_data( uart0__Channel_sts_reg0, val_uart0__Channel_sts_reg0); set_reset_data( uart0__TX_RX_FIFO0, val_uart0__TX_RX_FIFO0); set_reset_data( uart0__Baud_rate_divider_reg0, val_uart0__Baud_rate_divider_reg0); set_reset_data( uart0__Flow_delay_reg0, val_uart0__Flow_delay_reg0); set_reset_data( uart0__IR_min_rcv_pulse_wdth0, val_uart0__IR_min_rcv_pulse_wdth0); set_reset_data( uart0__IR_transmitted_pulse_wdth0, val_uart0__IR_transmitted_pulse_wdth0); set_reset_data( uart0__Tx_FIFO_trigger_level0, val_uart0__Tx_FIFO_trigger_level0); // ************************************************************ // Module uart1 UART // doc version: 1.2 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( uart1__Control_reg0, val_uart1__Control_reg0); set_reset_data( uart1__mode_reg0, val_uart1__mode_reg0); set_reset_data( uart1__Intrpt_en_reg0, val_uart1__Intrpt_en_reg0); set_reset_data( uart1__Intrpt_dis_reg0, val_uart1__Intrpt_dis_reg0); set_reset_data( uart1__Intrpt_mask_reg0, val_uart1__Intrpt_mask_reg0); set_reset_data( uart1__Chnl_int_sts_reg0, val_uart1__Chnl_int_sts_reg0); set_reset_data( uart1__Baud_rate_gen_reg0, val_uart1__Baud_rate_gen_reg0); set_reset_data( uart1__Rcvr_timeout_reg0, val_uart1__Rcvr_timeout_reg0); set_reset_data( uart1__Rcvr_FIFO_trigger_level0, val_uart1__Rcvr_FIFO_trigger_level0); set_reset_data( uart1__Modem_ctrl_reg0, val_uart1__Modem_ctrl_reg0); set_reset_data( uart1__Modem_sts_reg0, val_uart1__Modem_sts_reg0); set_reset_data( uart1__Channel_sts_reg0, val_uart1__Channel_sts_reg0); set_reset_data( uart1__TX_RX_FIFO0, val_uart1__TX_RX_FIFO0); set_reset_data( uart1__Baud_rate_divider_reg0, val_uart1__Baud_rate_divider_reg0); set_reset_data( uart1__Flow_delay_reg0, val_uart1__Flow_delay_reg0); set_reset_data( uart1__IR_min_rcv_pulse_wdth0, val_uart1__IR_min_rcv_pulse_wdth0); set_reset_data( uart1__IR_transmitted_pulse_wdth0, val_uart1__IR_transmitted_pulse_wdth0); set_reset_data( uart1__Tx_FIFO_trigger_level0, val_uart1__Tx_FIFO_trigger_level0); // ************************************************************ // Module usb0 usb // doc version: 1.3 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( usb0__ID, val_usb0__ID); set_reset_data( usb0__HWGENERAL, val_usb0__HWGENERAL); set_reset_data( usb0__HWHOST, val_usb0__HWHOST); set_reset_data( usb0__HWDEVICE, val_usb0__HWDEVICE); set_reset_data( usb0__HWTXBUF, val_usb0__HWTXBUF); set_reset_data( usb0__HWRXBUF, val_usb0__HWRXBUF); set_reset_data( usb0__GPTIMER0LD, val_usb0__GPTIMER0LD); set_reset_data( usb0__GPTIMER0CTRL, val_usb0__GPTIMER0CTRL); set_reset_data( usb0__GPTIMER1LD, val_usb0__GPTIMER1LD); set_reset_data( usb0__GPTIMER1CTRL, val_usb0__GPTIMER1CTRL); set_reset_data( usb0__SBUSCFG, val_usb0__SBUSCFG); set_reset_data( usb0__CAPLENGTH_HCIVERSION, val_usb0__CAPLENGTH_HCIVERSION); set_reset_data( usb0__HCSPARAMS, val_usb0__HCSPARAMS); set_reset_data( usb0__HCCPARAMS, val_usb0__HCCPARAMS); set_reset_data( usb0__DCIVERSION, val_usb0__DCIVERSION); set_reset_data( usb0__DCCPARAMS, val_usb0__DCCPARAMS); set_reset_data( usb0__USBCMD, val_usb0__USBCMD); set_reset_data( usb0__USBSTS, val_usb0__USBSTS); set_reset_data( usb0__USBINTR, val_usb0__USBINTR); set_reset_data( usb0__FRINDEX, val_usb0__FRINDEX); set_reset_data( usb0__PERIODICLISTBASE_DEVICEADDR, val_usb0__PERIODICLISTBASE_DEVICEADDR); set_reset_data( usb0__ASYNCLISTADDR_ENDPOINTLISTADDR, val_usb0__ASYNCLISTADDR_ENDPOINTLISTADDR); set_reset_data( usb0__TTCTRL, val_usb0__TTCTRL); set_reset_data( usb0__BURSTSIZE, val_usb0__BURSTSIZE); set_reset_data( usb0__TXFILLTUNING, val_usb0__TXFILLTUNING); set_reset_data( usb0__TXTTFILLTUNING, val_usb0__TXTTFILLTUNING); set_reset_data( usb0__IC_USB, val_usb0__IC_USB); set_reset_data( usb0__ULPI_VIEWPORT, val_usb0__ULPI_VIEWPORT); set_reset_data( usb0__ENDPTNAK, val_usb0__ENDPTNAK); set_reset_data( usb0__ENDPTNAKEN, val_usb0__ENDPTNAKEN); set_reset_data( usb0__CONFIGFLAG, val_usb0__CONFIGFLAG); set_reset_data( usb0__PORTSC1, val_usb0__PORTSC1); set_reset_data( usb0__OTGSC, val_usb0__OTGSC); set_reset_data( usb0__USBMODE, val_usb0__USBMODE); set_reset_data( usb0__ENDPTSETUPSTAT, val_usb0__ENDPTSETUPSTAT); set_reset_data( usb0__ENDPTPRIME, val_usb0__ENDPTPRIME); set_reset_data( usb0__ENDPTFLUSH, val_usb0__ENDPTFLUSH); set_reset_data( usb0__ENDPTSTAT, val_usb0__ENDPTSTAT); set_reset_data( usb0__ENDPTCOMPLETE, val_usb0__ENDPTCOMPLETE); set_reset_data( usb0__ENDPTCTRL0, val_usb0__ENDPTCTRL0); set_reset_data( usb0__ENDPTCTRL1, val_usb0__ENDPTCTRL1); set_reset_data( usb0__ENDPTCTRL2, val_usb0__ENDPTCTRL2); set_reset_data( usb0__ENDPTCTRL3, val_usb0__ENDPTCTRL3); set_reset_data( usb0__ENDPTCTRL4, val_usb0__ENDPTCTRL4); set_reset_data( usb0__ENDPTCTRL5, val_usb0__ENDPTCTRL5); set_reset_data( usb0__ENDPTCTRL6, val_usb0__ENDPTCTRL6); set_reset_data( usb0__ENDPTCTRL7, val_usb0__ENDPTCTRL7); set_reset_data( usb0__ENDPTCTRL8, val_usb0__ENDPTCTRL8); set_reset_data( usb0__ENDPTCTRL9, val_usb0__ENDPTCTRL9); set_reset_data( usb0__ENDPTCTRL10, val_usb0__ENDPTCTRL10); set_reset_data( usb0__ENDPTCTRL11, val_usb0__ENDPTCTRL11); set_reset_data( usb0__ENDPTCTRL12, val_usb0__ENDPTCTRL12); // ************************************************************ // Module usb1 usb // doc version: 1.3 // ************************************************************ // ADDRESS DEVFALUE MASK NAME set_reset_data( usb1__ID, val_usb1__ID); set_reset_data( usb1__HWGENERAL, val_usb1__HWGENERAL); set_reset_data( usb1__HWHOST, val_usb1__HWHOST); set_reset_data( usb1__HWDEVICE, val_usb1__HWDEVICE); set_reset_data( usb1__HWTXBUF, val_usb1__HWTXBUF); set_reset_data( usb1__HWRXBUF, val_usb1__HWRXBUF); set_reset_data( usb1__GPTIMER0LD, val_usb1__GPTIMER0LD); set_reset_data( usb1__GPTIMER0CTRL, val_usb1__GPTIMER0CTRL); set_reset_data( usb1__GPTIMER1LD, val_usb1__GPTIMER1LD); set_reset_data( usb1__GPTIMER1CTRL, val_usb1__GPTIMER1CTRL); set_reset_data( usb1__SBUSCFG, val_usb1__SBUSCFG); set_reset_data( usb1__CAPLENGTH_HCIVERSION, val_usb1__CAPLENGTH_HCIVERSION); set_reset_data( usb1__HCSPARAMS, val_usb1__HCSPARAMS); set_reset_data( usb1__HCCPARAMS, val_usb1__HCCPARAMS); set_reset_data( usb1__DCIVERSION, val_usb1__DCIVERSION); set_reset_data( usb1__DCCPARAMS, val_usb1__DCCPARAMS); set_reset_data( usb1__USBCMD, val_usb1__USBCMD); set_reset_data( usb1__USBSTS, val_usb1__USBSTS); set_reset_data( usb1__USBINTR, val_usb1__USBINTR); set_reset_data( usb1__FRINDEX, val_usb1__FRINDEX); set_reset_data( usb1__PERIODICLISTBASE_DEVICEADDR, val_usb1__PERIODICLISTBASE_DEVICEADDR); set_reset_data( usb1__ASYNCLISTADDR_ENDPOINTLISTADDR, val_usb1__ASYNCLISTADDR_ENDPOINTLISTADDR); set_reset_data( usb1__TTCTRL, val_usb1__TTCTRL); set_reset_data( usb1__BURSTSIZE, val_usb1__BURSTSIZE); set_reset_data( usb1__TXFILLTUNING, val_usb1__TXFILLTUNING); set_reset_data( usb1__TXTTFILLTUNING, val_usb1__TXTTFILLTUNING); set_reset_data( usb1__IC_USB, val_usb1__IC_USB); set_reset_data( usb1__ULPI_VIEWPORT, val_usb1__ULPI_VIEWPORT); set_reset_data( usb1__ENDPTNAK, val_usb1__ENDPTNAK); set_reset_data( usb1__ENDPTNAKEN, val_usb1__ENDPTNAKEN); set_reset_data( usb1__CONFIGFLAG, val_usb1__CONFIGFLAG); set_reset_data( usb1__PORTSC1, val_usb1__PORTSC1); set_reset_data( usb1__OTGSC, val_usb1__OTGSC); set_reset_data( usb1__USBMODE, val_usb1__USBMODE); set_reset_data( usb1__ENDPTSETUPSTAT, val_usb1__ENDPTSETUPSTAT); set_reset_data( usb1__ENDPTPRIME, val_usb1__ENDPTPRIME); set_reset_data( usb1__ENDPTFLUSH, val_usb1__ENDPTFLUSH); set_reset_data( usb1__ENDPTSTAT, val_usb1__ENDPTSTAT); set_reset_data( usb1__ENDPTCOMPLETE, val_usb1__ENDPTCOMPLETE); set_reset_data( usb1__ENDPTCTRL0, val_usb1__ENDPTCTRL0); set_reset_data( usb1__ENDPTCTRL1, val_usb1__ENDPTCTRL1); set_reset_data( usb1__ENDPTCTRL2, val_usb1__ENDPTCTRL2); set_reset_data( usb1__ENDPTCTRL3, val_usb1__ENDPTCTRL3); set_reset_data( usb1__ENDPTCTRL4, val_usb1__ENDPTCTRL4); set_reset_data( usb1__ENDPTCTRL5, val_usb1__ENDPTCTRL5); set_reset_data( usb1__ENDPTCTRL6, val_usb1__ENDPTCTRL6); set_reset_data( usb1__ENDPTCTRL7, val_usb1__ENDPTCTRL7); set_reset_data( usb1__ENDPTCTRL8, val_usb1__ENDPTCTRL8); set_reset_data( usb1__ENDPTCTRL9, val_usb1__ENDPTCTRL9); set_reset_data( usb1__ENDPTCTRL10, val_usb1__ENDPTCTRL10); set_reset_data( usb1__ENDPTCTRL11, val_usb1__ENDPTCTRL11); set_reset_data( usb1__ENDPTCTRL12, val_usb1__ENDPTCTRL12);
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: // Optimized AND with generic_baseblocks_v2_1_carry logic. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module generic_baseblocks_v2_1_carry_and # ( parameter C_FAMILY = "virtex6" // FPGA Family. Current version: virtex6 or spartan6. ) ( input wire CIN, input wire S, output wire COUT ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Instantiate or use RTL code ///////////////////////////////////////////////////////////////////////////// generate if ( C_FAMILY == "rtl" ) begin : USE_RTL assign COUT = CIN & S; end else begin : USE_FPGA MUXCY and_inst ( .O (COUT), .CI (CIN), .DI (1\'b0), .S (S) ); end endgenerate endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: Address Write Channel for ATC // // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // aw_atc // //-------------------------------------------------------------------------- `timescale 1ps/1ps module processing_system7_v5_5_aw_atc # ( parameter C_FAMILY = "rtl", // FPGA Family. Current version: virtex6, spartan6 or later. parameter integer C_AXI_ID_WIDTH = 4, // Width of all ID signals on SI and MI side of checker. // Range: >= 1. parameter integer C_AXI_ADDR_WIDTH = 32, // Width of all ADDR signals on SI and MI side of checker. // Range: 32. parameter integer C_AXI_AWUSER_WIDTH = 1, // Width of AWUSER signals. // Range: >= 1. parameter integer C_FIFO_DEPTH_LOG = 4 ) ( // Global Signals input wire ARESET, input wire ACLK, // Command Interface output reg cmd_w_valid, output wire cmd_w_check, output wire [C_AXI_ID_WIDTH-1:0] cmd_w_id, input wire cmd_w_ready, input wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr, input wire cmd_b_ready, // Slave Interface Write Address Port input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID, input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR, input wire [4-1:0] S_AXI_AWLEN, input wire [3-1:0] S_AXI_AWSIZE, input wire [2-1:0] S_AXI_AWBURST, input wire [2-1:0] S_AXI_AWLOCK, input wire [4-1:0] S_AXI_AWCACHE, input wire [3-1:0] S_AXI_AWPROT, input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER, input wire S_AXI_AWVALID, output wire S_AXI_AWREADY, // Master Interface Write Address Port output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID, output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR, output wire [4-1:0] M_AXI_AWLEN, output wire [3-1:0] M_AXI_AWSIZE, output wire [2-1:0] M_AXI_AWBURST, output wire [2-1:0] M_AXI_AWLOCK, output wire [4-1:0] M_AXI_AWCACHE, output wire [3-1:0] M_AXI_AWPROT, output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER, output wire M_AXI_AWVALID, input wire M_AXI_AWREADY ); ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Constants for burst types. localparam [2-1:0] C_FIX_BURST = 2\'b00; localparam [2-1:0] C_INCR_BURST = 2\'b01; localparam [2-1:0] C_WRAP_BURST = 2\'b10; // Constants for size. localparam [3-1:0] C_OPTIMIZED_SIZE = 3\'b011; // Constants for length. localparam [4-1:0] C_OPTIMIZED_LEN = 4\'b0011; // Constants for cacheline address. localparam [4-1:0] C_NO_ADDR_OFFSET = 5\'b0; // Command FIFO settings localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1; localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG; ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// integer index; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// // Transaction properties. wire access_is_incr; wire access_is_wrap; wire access_is_coherent; wire access_optimized_size; wire incr_addr_boundary; wire incr_is_optimized; wire wrap_is_optimized; wire access_is_optimized; // Command FIFO. wire cmd_w_push; reg cmd_full; reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr; wire [C_FIFO_DEPTH_LOG-1:0] all_addr_ptr; reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0]; ///////////////////////////////////////////////////////////////////////////// // Transaction Decode: // // Detect if transaction is of correct typ, size and length to qualify as // an optimized transaction that has to be checked for errors. // ///////////////////////////////////////////////////////////////////////////// // Transaction burst type. assign access_is_incr = ( S_AXI_AWBURST == C_INCR_BURST ); assign access_is_wrap = ( S_AXI_AWBURST == C_WRAP_BURST ); // Transaction has to be Coherent. assign access_is_coherent = ( S_AXI_AWUSER[0] == 1\'b1 ) & ( S_AXI_AWCACHE[1] == 1\'b1 ); // Transaction cacheline boundary address. assign incr_addr_boundary = ( S_AXI_AWADDR[4:0] == C_NO_ADDR_OFFSET ); // Transaction length & size. assign access_optimized_size = ( S_AXI_AWSIZE == C_OPTIMIZED_SIZE ) & ( S_AXI_AWLEN == C_OPTIMIZED_LEN ); // Transaction is optimized. assign incr_is_optimized = access_is_incr & access_is_coherent & access_optimized_size & incr_addr_boundary; assign wrap_is_optimized = access_is_wrap & access_is_coherent & access_optimized_size; assign access_is_optimized = ( incr_is_optimized | wrap_is_optimized ); ///////////////////////////////////////////////////////////////////////////// // Command FIFO: // // Since supported write interleaving is only 1, it is safe to use only a // simple SRL based FIFO as a command queue. // ///////////////////////////////////////////////////////////////////////////// // Determine when transaction infromation is pushed to the FIFO. assign cmd_w_push = S_AXI_AWVALID & M_AXI_AWREADY & ~cmd_full; // SRL FIFO Pointer. always @ (posedge ACLK) begin if (ARESET) begin addr_ptr <= {C_FIFO_DEPTH_LOG{1\'b1}}; end else begin if ( cmd_w_push & ~cmd_w_ready ) begin addr_ptr <= addr_ptr + 1; end else if ( ~cmd_w_push & cmd_w_ready ) begin addr_ptr <= addr_ptr - 1; end end end // Total number of buffered commands. assign all_addr_ptr = addr_ptr + cmd_b_addr + 2; // FIFO Flags. always @ (posedge ACLK) begin if (ARESET) begin cmd_full <= 1\'b0; cmd_w_valid <= 1\'b0; end else begin if ( cmd_w_push & ~cmd_w_ready ) begin cmd_w_valid <= 1\'b1; end else if ( ~cmd_w_push & cmd_w_ready ) begin cmd_w_valid <= ( addr_ptr != 0 ); end if ( cmd_w_push & ~cmd_b_ready ) begin // Going to full. cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-3 ); end else if ( ~cmd_w_push & cmd_b_ready ) begin // Pop in middle of queue doesn\'t affect full status. cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-2 ); end end end // Infere SRL for storage. always @ (posedge ACLK) begin if ( cmd_w_push ) begin for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin data_srl[index+1] <= data_srl[index]; end data_srl[0] <= {access_is_optimized, S_AXI_AWID}; end end // Get current transaction info. assign {cmd_w_check, cmd_w_id} = data_srl[addr_ptr]; ///////////////////////////////////////////////////////////////////////////// // Transaction Throttling: // // Stall commands if FIFO is full. // ///////////////////////////////////////////////////////////////////////////// // Propagate masked valid. assign M_AXI_AWVALID = S_AXI_AWVALID & ~cmd_full; // Return ready with push back. assign S_AXI_AWREADY = M_AXI_AWREADY & ~cmd_full; ///////////////////////////////////////////////////////////////////////////// // Address Write propagation: // // All information is simply forwarded on from the SI- to MI-Side untouched. // ///////////////////////////////////////////////////////////////////////////// // 1:1 mapping. assign M_AXI_AWID = S_AXI_AWID; assign M_AXI_AWADDR = S_AXI_AWADDR; assign M_AXI_AWLEN = S_AXI_AWLEN; assign M_AXI_AWSIZE = S_AXI_AWSIZE; assign M_AXI_AWBURST = S_AXI_AWBURST; assign M_AXI_AWLOCK = S_AXI_AWLOCK; assign M_AXI_AWCACHE = S_AXI_AWCACHE; assign M_AXI_AWPROT = S_AXI_AWPROT; assign M_AXI_AWUSER = S_AXI_AWUSER; endmodule
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // File name: wdata_mux.v // // Description: // Contains MI-side write command queue. // SI-slot index selected by AW arbiter is pushed onto queue when S_AVALID transfer is received. // Queue is popped when WLAST data beat is transferred. // W-channel input from SI-slot selected by queue output is transferred to MI-side output . //-------------------------------------------------------------------------- // // Structure: // wdata_mux // axic_reg_srl_fifo // mux_enc // //----------------------------------------------------------------------------- `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_crossbar_v2_1_wdata_mux # ( parameter C_FAMILY = "none", // FPGA Family. parameter integer C_WMESG_WIDTH = 1, // Width of W-channel payload. parameter integer C_NUM_SLAVE_SLOTS = 1, // Number of S_* ports. parameter integer C_SELECT_WIDTH = 1, // Width of ASELECT. parameter integer C_FIFO_DEPTH_LOG = 0 // Queue depth = 2**C_FIFO_DEPTH_LOG. ) ( // System Signals input wire ACLK, input wire ARESET, // Slave Data Ports input wire [C_NUM_SLAVE_SLOTS*C_WMESG_WIDTH-1:0] S_WMESG, input wire [C_NUM_SLAVE_SLOTS-1:0] S_WLAST, input wire [C_NUM_SLAVE_SLOTS-1:0] S_WVALID, output wire [C_NUM_SLAVE_SLOTS-1:0] S_WREADY, // Master Data Ports output wire [C_WMESG_WIDTH-1:0] M_WMESG, output wire M_WLAST, output wire M_WVALID, input wire M_WREADY, // Write Command Ports input wire [C_SELECT_WIDTH-1:0] S_ASELECT, // SI-slot index from AW arbiter input wire S_AVALID, output wire S_AREADY ); localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5; // Max depth = 32 // Decode select input to 1-hot function [C_NUM_SLAVE_SLOTS-1:0] f_decoder ( input [C_SELECT_WIDTH-1:0] sel ); integer i; begin for (i=0; i<C_NUM_SLAVE_SLOTS; i=i+1) begin f_decoder[i] = (sel == i); end end endfunction wire m_valid_i; wire m_last_i; wire [C_NUM_SLAVE_SLOTS-1:0] m_select_hot; wire [C_SELECT_WIDTH-1:0] m_select_enc; wire m_avalid; wire m_aready; generate if (C_NUM_SLAVE_SLOTS>1) begin : gen_wmux // SI-side write command queue axi_data_fifo_v2_1_axic_reg_srl_fifo # ( .C_FAMILY (C_FAMILY), .C_FIFO_WIDTH (C_SELECT_WIDTH), .C_FIFO_DEPTH_LOG (P_FIFO_DEPTH_LOG), .C_USE_FULL (0) ) wmux_aw_fifo ( .ACLK (ACLK), .ARESET (ARESET), .S_MESG (S_ASELECT), .S_VALID (S_AVALID), .S_READY (S_AREADY), .M_MESG (m_select_enc), .M_VALID (m_avalid), .M_READY (m_aready) ); assign m_select_hot = f_decoder(m_select_enc); // Instantiate MUX generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (C_NUM_SLAVE_SLOTS), .C_SEL_WIDTH (C_SELECT_WIDTH), .C_DATA_WIDTH (C_WMESG_WIDTH) ) mux_w ( .S (m_select_enc), .A (S_WMESG), .O (M_WMESG), .OE (1\'b1) ); assign m_last_i = |(S_WLAST & m_select_hot); assign m_valid_i = |(S_WVALID & m_select_hot); assign m_aready = m_valid_i & m_avalid & m_last_i & M_WREADY; assign M_WLAST = m_last_i; assign M_WVALID = m_valid_i & m_avalid; assign S_WREADY = m_select_hot & {C_NUM_SLAVE_SLOTS{m_avalid & M_WREADY}}; end else begin : gen_no_wmux assign S_AREADY = 1\'b1; assign M_WVALID = S_WVALID; assign S_WREADY = M_WREADY; assign M_WLAST = S_WLAST; assign M_WMESG = S_WMESG; end endgenerate endmodule `default_nettype wire
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // File name: crossbar_sasd.v // // Description: // This module is a M-master to N-slave AXI axi_crossbar_v2_1_crossbar switch. // Single transaction issuing, single arbiter (both W&R), single data pathways. // The interface of this module consists of a vectored slave and master interface // in which all slots are sized and synchronized to the native width and clock // of the interconnect, and are all AXI4 protocol. // All width, clock and protocol conversions are done outside this block, as are // any pipeline registers or data FIFOs. // This module contains all arbitration, decoders and channel multiplexing logic. // It also contains the diagnostic registers and control interface. // //-------------------------------------------------------------------------- // // Structure: // crossbar_sasd // addr_arbiter_sasd // mux_enc // addr_decoder // comparator_static // splitter // mux_enc // axic_register_slice // decerr_slave // //----------------------------------------------------------------------------- `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_crossbar_v2_1_crossbar_sasd # ( parameter C_FAMILY = "none", parameter integer C_NUM_SLAVE_SLOTS = 1, parameter integer C_NUM_MASTER_SLOTS = 1, parameter integer C_NUM_ADDR_RANGES = 1, parameter integer C_AXI_ID_WIDTH = 1, parameter integer C_AXI_ADDR_WIDTH = 32, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_PROTOCOL = 0, parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1\'b1}}, parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_HIGH_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1\'b0}}, parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_BASE_ID = {C_NUM_SLAVE_SLOTS*64{1\'b0}}, parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_HIGH_ID = {C_NUM_SLAVE_SLOTS*64{1\'b0}}, parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, parameter integer C_AXI_AWUSER_WIDTH = 1, parameter integer C_AXI_ARUSER_WIDTH = 1, parameter integer C_AXI_WUSER_WIDTH = 1, parameter integer C_AXI_RUSER_WIDTH = 1, parameter integer C_AXI_BUSER_WIDTH = 1, parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_WRITE = {C_NUM_SLAVE_SLOTS{1\'b1}}, parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_READ = {C_NUM_SLAVE_SLOTS{1\'b1}}, parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_WRITE = {C_NUM_MASTER_SLOTS{1\'b1}}, parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_READ = {C_NUM_MASTER_SLOTS{1\'b1}}, parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY = {C_NUM_SLAVE_SLOTS{32\'h00000000}}, parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE = {C_NUM_MASTER_SLOTS{32\'h00000000}}, parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_ERR_MODE = {C_NUM_MASTER_SLOTS{32\'h00000000}}, parameter integer C_R_REGISTER = 0, parameter integer C_RANGE_CHECK = 0, parameter integer C_ADDR_DECODE = 0, parameter integer C_DEBUG = 1 ) ( // Global Signals input wire ACLK, input wire ARESETN, // Slave Interface Write Address Ports input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_AWID, input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR, input wire [C_NUM_SLAVE_SLOTS*8-1:0] S_AXI_AWLEN, input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_AWSIZE, input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_AWBURST, input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_AWLOCK, input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWCACHE, input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_AWPROT, // input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWREGION, input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWQOS, input wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_AWVALID, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_AWREADY, // Slave Interface Write Data Ports input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_WID, input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA, input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WLAST, input wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WVALID, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WREADY, // Slave Interface Write Response Ports output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_BID, output wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_BRESP, output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_BVALID, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_BREADY, // Slave Interface Read Address Ports input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_ARID, input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR, input wire [C_NUM_SLAVE_SLOTS*8-1:0] S_AXI_ARLEN, input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_ARSIZE, input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_ARBURST, input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_ARLOCK, input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARCACHE, input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_ARPROT, // input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARREGION, input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARQOS, input wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_ARVALID, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_ARREADY, // Slave Interface Read Data Ports output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_RID, output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA, output wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_RRESP, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RLAST, output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RVALID, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RREADY, // Master Interface Write Address Port output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_AWID, output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR, output wire [C_NUM_MASTER_SLOTS*8-1:0] M_AXI_AWLEN, output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_AWSIZE, output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_AWBURST, output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_AWLOCK, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWCACHE, output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_AWPROT, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWREGION, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWQOS, output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_AWVALID, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_AWREADY, // Master Interface Write Data Ports output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_WID, output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA, output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WLAST, output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WVALID, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WREADY, // Master Interface Write Response Ports input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_BID, // Unused input wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_BRESP, input wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_BVALID, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_BREADY, // Master Interface Read Address Port output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_ARID, output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR, output wire [C_NUM_MASTER_SLOTS*8-1:0] M_AXI_ARLEN, output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_ARSIZE, output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_ARBURST, output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_ARLOCK, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARCACHE, output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_ARPROT, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARREGION, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARQOS, output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_ARVALID, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_ARREADY, // Master Interface Read Data Ports input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_RID, // Unused input wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA, input wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_RRESP, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RLAST, input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RVALID, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RREADY ); localparam integer P_AXI4 = 0; localparam integer P_AXI3 = 1; localparam integer P_AXILITE = 2; localparam integer P_NUM_MASTER_SLOTS_DE = C_RANGE_CHECK ? C_NUM_MASTER_SLOTS+1 : C_NUM_MASTER_SLOTS; localparam integer P_NUM_MASTER_SLOTS_LOG = (C_NUM_MASTER_SLOTS>1) ? f_ceil_log2(C_NUM_MASTER_SLOTS) : 1; localparam integer P_NUM_MASTER_SLOTS_DE_LOG = (P_NUM_MASTER_SLOTS_DE>1) ? f_ceil_log2(P_NUM_MASTER_SLOTS_DE) : 1; localparam integer P_NUM_SLAVE_SLOTS_LOG = (C_NUM_SLAVE_SLOTS>1) ? f_ceil_log2(C_NUM_SLAVE_SLOTS) : 1; localparam integer P_AXI_AUSER_WIDTH = (C_AXI_AWUSER_WIDTH > C_AXI_ARUSER_WIDTH) ? C_AXI_AWUSER_WIDTH : C_AXI_ARUSER_WIDTH; localparam integer P_AXI_WID_WIDTH = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 1; localparam integer P_AMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+2+4+4 + P_AXI_AUSER_WIDTH + 4; localparam integer P_BMESG_WIDTH = 2 + C_AXI_BUSER_WIDTH; localparam integer P_RMESG_WIDTH = 1+2 + C_AXI_DATA_WIDTH + C_AXI_RUSER_WIDTH; localparam integer P_WMESG_WIDTH = 1 + C_AXI_DATA_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_WUSER_WIDTH + P_AXI_WID_WIDTH; localparam [31:0] P_AXILITE_ERRMODE = 32\'h00000001; localparam integer P_NONSECURE_BIT = 1; localparam [C_NUM_MASTER_SLOTS-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE); // Mask of secure MI-slots localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXILITE_MASK = f_m_axilite(0); // Mask of axilite rule-check MI-slots localparam [1:0] P_FIXED = 2\'b00; localparam integer P_BYPASS = 0; localparam integer P_LIGHTWT = 7; localparam integer P_FULLY_REG = 1; localparam integer P_R_REG_CONFIG = C_R_REGISTER == 8 ? // "Automatic" reg-slice (C_RANGE_CHECK ? ((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHTWT : P_FULLY_REG) : P_BYPASS) : // Bypass if no R-channel mux C_R_REGISTER; localparam P_DECERR = 2\'b11; //--------------------------------------------------------------------------- // Functions //--------------------------------------------------------------------------- // Ceiling of log2(x) function integer f_ceil_log2 ( input integer x ); integer acc; begin acc=0; while ((2**acc) < x) acc = acc + 1; f_ceil_log2 = acc; end endfunction // Isolate thread bits of input S_ID and add to BASE_ID (RNG00) to form MI-side ID value // only for end-point SI-slots function [C_AXI_ID_WIDTH-1:0] f_extend_ID ( input [C_AXI_ID_WIDTH-1:0] s_id, input integer slot ); begin f_extend_ID = C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] | (s_id & (C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] ^ C_S_AXI_HIGH_ID[slot*64+:C_AXI_ID_WIDTH])); end endfunction // Convert Bit32 vector of range [0,1] to Bit1 vector on MI function [C_NUM_MASTER_SLOTS-1:0] f_bit32to1_mi (input [C_NUM_MASTER_SLOTS*32-1:0] vec32); integer mi; begin for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin f_bit32to1_mi[mi] = vec32[mi*32]; end end endfunction // AxiLite error-checking mask (on MI) function [C_NUM_MASTER_SLOTS-1:0] f_m_axilite ( input integer null_arg ); integer mi; begin for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin f_m_axilite[mi] = (C_M_AXI_ERR_MODE[mi*32+:32] == P_AXILITE_ERRMODE); end end endfunction genvar gen_si_slot; genvar gen_mi_slot; wire [C_NUM_SLAVE_SLOTS*P_AMESG_WIDTH-1:0] si_awmesg ; wire [C_NUM_SLAVE_SLOTS*P_AMESG_WIDTH-1:0] si_armesg ; wire [P_AMESG_WIDTH-1:0] aa_amesg ; wire [C_AXI_ID_WIDTH-1:0] mi_aid ; wire [C_AXI_ADDR_WIDTH-1:0] mi_aaddr ; wire [8-1:0] mi_alen ; wire [3-1:0] mi_asize ; wire [2-1:0] mi_alock ; wire [3-1:0] mi_aprot ; wire [2-1:0] mi_aburst ; wire [4-1:0] mi_acache ; wire [4-1:0] mi_aregion ; wire [4-1:0] mi_aqos ; wire [P_AXI_AUSER_WIDTH-1:0] mi_auser ; wire [4-1:0] target_region ; wire [C_NUM_SLAVE_SLOTS*1-1:0] aa_grant_hot ; wire [P_NUM_SLAVE_SLOTS_LOG-1:0] aa_grant_enc ; wire aa_grant_rnw ; wire aa_grant_any ; wire [C_NUM_MASTER_SLOTS-1:0] target_mi_hot ; wire [P_NUM_MASTER_SLOTS_LOG-1:0] target_mi_enc ; reg [P_NUM_MASTER_SLOTS_DE-1:0] m_atarget_hot ; reg [P_NUM_MASTER_SLOTS_DE_LOG-1:0] m_atarget_enc ; wire [P_NUM_MASTER_SLOTS_DE_LOG-1:0] m_atarget_enc_comb ; wire match; wire any_error ; wire [7:0] m_aerror_i ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_awvalid ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_awready ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_arvalid ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_arready ; wire aa_awvalid ; wire aa_awready ; wire aa_arvalid ; wire aa_arready ; wire mi_awvalid_en; wire mi_awready_mux; wire mi_arvalid_en; wire mi_arready_mux; wire w_transfer_en; wire w_complete_mux; wire b_transfer_en; wire b_complete_mux; wire r_transfer_en; wire r_complete_mux; wire target_secure; wire target_write; wire target_read; wire target_axilite; wire [P_BMESG_WIDTH-1:0] si_bmesg ; wire [P_NUM_MASTER_SLOTS_DE*P_BMESG_WIDTH-1:0] mi_bmesg ; wire [P_NUM_MASTER_SLOTS_DE*2-1:0] mi_bresp ; wire [P_NUM_MASTER_SLOTS_DE*C_AXI_BUSER_WIDTH-1:0] mi_buser ; wire [2-1:0] si_bresp ; wire [C_AXI_BUSER_WIDTH-1:0] si_buser ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_bvalid ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_bready ; wire aa_bvalid ; wire aa_bready ; wire si_bready ; wire [C_NUM_SLAVE_SLOTS-1:0] si_bvalid; wire [P_RMESG_WIDTH-1:0] aa_rmesg ; wire [P_RMESG_WIDTH-1:0] sr_rmesg ; wire [P_NUM_MASTER_SLOTS_DE*P_RMESG_WIDTH-1:0] mi_rmesg ; wire [P_NUM_MASTER_SLOTS_DE*2-1:0] mi_rresp ; wire [P_NUM_MASTER_SLOTS_DE*C_AXI_RUSER_WIDTH-1:0] mi_ruser ; wire [P_NUM_MASTER_SLOTS_DE*C_AXI_DATA_WIDTH-1:0] mi_rdata ; wire [P_NUM_MASTER_SLOTS_DE*1-1:0] mi_rlast ; wire [2-1:0] si_rresp ; wire [C_AXI_RUSER_WIDTH-1:0] si_ruser ; wire [C_AXI_DATA_WIDTH-1:0] si_rdata ; wire si_rlast ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_rvalid ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_rready ; wire aa_rvalid ; wire aa_rready ; wire sr_rvalid ; wire si_rready ; wire sr_rready ; wire [C_NUM_SLAVE_SLOTS-1:0] si_rvalid; wire [C_NUM_SLAVE_SLOTS*P_WMESG_WIDTH-1:0] si_wmesg ; wire [P_WMESG_WIDTH-1:0] mi_wmesg ; wire [C_AXI_ID_WIDTH-1:0] mi_wid ; wire [C_AXI_DATA_WIDTH-1:0] mi_wdata ; wire [C_AXI_DATA_WIDTH/8-1:0] mi_wstrb ; wire [C_AXI_WUSER_WIDTH-1:0] mi_wuser ; wire [1-1:0] mi_wlast ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_wvalid ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_wready ; wire aa_wvalid ; wire aa_wready ; wire [C_NUM_SLAVE_SLOTS-1:0] si_wready; reg [7:0] debug_r_beat_cnt_i; reg [7:0] debug_w_beat_cnt_i; reg [7:0] debug_aw_trans_seq_i; reg [7:0] debug_ar_trans_seq_i; reg aresetn_d = 1\'b0; // Reset delay register always @(posedge ACLK) begin if (~ARESETN) begin aresetn_d <= 1\'b0; end else begin aresetn_d <= ARESETN; end end wire reset; assign reset = ~aresetn_d; generate axi_crossbar_v2_1_addr_arbiter_sasd # ( .C_FAMILY (C_FAMILY), .C_NUM_S (C_NUM_SLAVE_SLOTS), .C_NUM_S_LOG (P_NUM_SLAVE_SLOTS_LOG), .C_AMESG_WIDTH (P_AMESG_WIDTH), .C_GRANT_ENC (1), .C_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY) ) addr_arbiter_inst ( .ACLK (ACLK), .ARESET (reset), // Vector of SI-side AW command request inputs .S_AWMESG (si_awmesg), .S_ARMESG (si_armesg), .S_AWVALID (S_AXI_AWVALID), .S_AWREADY (S_AXI_AWREADY), .S_ARVALID (S_AXI_ARVALID), .S_ARREADY (S_AXI_ARREADY), .M_GRANT_ENC (aa_grant_enc), .M_GRANT_HOT (aa_grant_hot), // SI-slot 1-hot mask of granted command .M_GRANT_ANY (aa_grant_any), .M_GRANT_RNW (aa_grant_rnw), .M_AMESG (aa_amesg), // Either S_AWMESG or S_ARMESG, as indicated by M_AWVALID and M_ARVALID. .M_AWVALID (aa_awvalid), .M_AWREADY (aa_awready), .M_ARVALID (aa_arvalid), .M_ARREADY (aa_arready) ); if (C_ADDR_DECODE) begin : gen_addr_decoder axi_crossbar_v2_1_addr_decoder # ( .C_FAMILY (C_FAMILY), .C_NUM_TARGETS (C_NUM_MASTER_SLOTS), .C_NUM_TARGETS_LOG (P_NUM_MASTER_SLOTS_LOG), .C_NUM_RANGES (C_NUM_ADDR_RANGES), .C_ADDR_WIDTH (C_AXI_ADDR_WIDTH), .C_TARGET_ENC (1), .C_TARGET_HOT (1), .C_REGION_ENC (1), .C_BASE_ADDR (C_M_AXI_BASE_ADDR), .C_HIGH_ADDR (C_M_AXI_HIGH_ADDR), .C_TARGET_QUAL ({C_NUM_MASTER_SLOTS{1\'b1}}), .C_RESOLUTION (2) ) addr_decoder_inst ( .ADDR (mi_aaddr), .TARGET_HOT (target_mi_hot), .TARGET_ENC (target_mi_enc), .MATCH (match), .REGION (target_region) ); end else begin : gen_no_addr_decoder assign target_mi_hot = 1; assign match = 1\'b1; assign target_region = 4\'b0000; end // gen_addr_decoder // AW-channel arbiter command transfer completes upon completion of both M-side AW-channel transfer and B channel completion. axi_crossbar_v2_1_splitter # ( .C_NUM_M (3) ) splitter_aw ( .ACLK (ACLK), .ARESET (reset), .S_VALID (aa_awvalid), .S_READY (aa_awready), .M_VALID ({mi_awvalid_en, w_transfer_en, b_transfer_en}), .M_READY ({mi_awready_mux, w_complete_mux, b_complete_mux}) ); // AR-channel arbiter command transfer completes upon completion of both M-side AR-channel transfer and R channel completion. axi_crossbar_v2_1_splitter # ( .C_NUM_M (2) ) splitter_ar ( .ACLK (ACLK), .ARESET (reset), .S_VALID (aa_arvalid), .S_READY (aa_arready), .M_VALID ({mi_arvalid_en, r_transfer_en}), .M_READY ({mi_arready_mux, r_complete_mux}) ); assign target_secure = |(target_mi_hot & P_M_SECURE_MASK); assign target_write = |(target_mi_hot & C_M_AXI_SUPPORTS_WRITE); assign target_read = |(target_mi_hot & C_M_AXI_SUPPORTS_READ); assign target_axilite = |(target_mi_hot & P_M_AXILITE_MASK); assign any_error = C_RANGE_CHECK && (m_aerror_i != 0); // DECERR if error-detection enabled and any error condition. assign m_aerror_i[0] = ~match; // Invalid target address assign m_aerror_i[1] = target_secure && mi_aprot[P_NONSECURE_BIT]; // TrustZone violation assign m_aerror_i[2] = target_axilite && ((mi_alen != 0) || (mi_asize[1:0] == 2\'b11) || (mi_asize[2] == 1\'b1)); // AxiLite access violation assign m_aerror_i[3] = (~aa_grant_rnw && ~target_write) || (aa_grant_rnw && ~target_read); // R/W direction unsupported by target assign m_aerror_i[7:4] = 4\'b0000; // Reserved assign m_atarget_enc_comb = any_error ? (P_NUM_MASTER_SLOTS_DE-1) : target_mi_enc; // Select MI slot or decerr_slave always @(posedge ACLK) begin if (reset) begin m_atarget_hot <= 0; m_atarget_enc <= 0; end else begin m_atarget_hot <= {P_NUM_MASTER_SLOTS_DE{aa_grant_any}} & (any_error ? {1\'b1, {C_NUM_MASTER_SLOTS{1\'b0}}} : {1\'b0, target_mi_hot}); // Select MI slot or decerr_slave m_atarget_enc <= m_atarget_enc_comb; end end // Receive AWREADY from targeted MI. generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (P_NUM_MASTER_SLOTS_DE), .C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG), .C_DATA_WIDTH (1) ) mi_awready_mux_inst ( .S (m_atarget_enc), .A (mi_awready), .O (mi_awready_mux), .OE (mi_awvalid_en) ); // Receive ARREADY from targeted MI. generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (P_NUM_MASTER_SLOTS_DE), .C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG), .C_DATA_WIDTH (1) ) mi_arready_mux_inst ( .S (m_atarget_enc), .A (mi_arready), .O (mi_arready_mux), .OE (mi_arvalid_en) ); assign mi_awvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{mi_awvalid_en}}; // Assert AWVALID on targeted MI. assign mi_arvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{mi_arvalid_en}}; // Assert ARVALID on targeted MI. assign M_AXI_AWVALID = mi_awvalid[0+:C_NUM_MASTER_SLOTS]; // Propagate to MI slots. assign M_AXI_ARVALID = mi_arvalid[0+:C_NUM_MASTER_SLOTS]; // Propagate to MI slots. assign mi_awready[0+:C_NUM_MASTER_SLOTS] = M_AXI_AWREADY; // Copy from MI slots. assign mi_arready[0+:C_NUM_MASTER_SLOTS] = M_AXI_ARREADY; // Copy from MI slots. // Receive WREADY from targeted MI. generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (P_NUM_MASTER_SLOTS_DE), .C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG), .C_DATA_WIDTH (1) ) mi_wready_mux_inst ( .S (m_atarget_enc), .A (mi_wready), .O (aa_wready), .OE (w_transfer_en) ); assign mi_wvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_wvalid}}; // Assert WVALID on targeted MI. assign si_wready = aa_grant_hot & {C_NUM_SLAVE_SLOTS{aa_wready}}; // Assert WREADY on granted SI. assign S_AXI_WREADY = si_wready; assign w_complete_mux = aa_wready & aa_wvalid & mi_wlast; // W burst complete on on designated SI/MI. // Receive RREADY from granted SI. generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (C_NUM_SLAVE_SLOTS), .C_SEL_WIDTH (P_NUM_SLAVE_SLOTS_LOG), .C_DATA_WIDTH (1) ) si_rready_mux_inst ( .S (aa_grant_enc), .A (S_AXI_RREADY), .O (si_rready), .OE (r_transfer_en) ); assign sr_rready = si_rready & r_transfer_en; assign mi_rready = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_rready}}; // Assert RREADY on targeted MI. assign si_rvalid = aa_grant_hot & {C_NUM_SLAVE_SLOTS{sr_rvalid}}; // Assert RVALID on granted SI. assign S_AXI_RVALID = si_rvalid; assign r_complete_mux = sr_rready & sr_rvalid & si_rlast; // R burst complete on on designated SI/MI. // Receive BREADY from granted SI. generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (C_NUM_SLAVE_SLOTS), .C_SEL_WIDTH (P_NUM_SLAVE_SLOTS_LOG), .C_DATA_WIDTH (1) ) si_bready_mux_inst ( .S (aa_grant_enc), .A (S_AXI_BREADY), .O (si_bready), .OE (b_transfer_en) ); assign aa_bready = si_bready & b_transfer_en; assign mi_bready = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_bready}}; // Assert BREADY on targeted MI. assign si_bvalid = aa_grant_hot & {C_NUM_SLAVE_SLOTS{aa_bvalid}}; // Assert BVALID on granted SI. assign S_AXI_BVALID = si_bvalid; assign b_complete_mux = aa_bready & aa_bvalid; // B transfer complete on on designated SI/MI. for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_si_amesg assign si_armesg[gen_si_slot*P_AMESG_WIDTH +: P_AMESG_WIDTH] = { // Concatenate from MSB to LSB 4\'b0000, // S_AXI_ARREGION[gen_si_slot*4+:4], S_AXI_ARUSER[gen_si_slot*C_AXI_ARUSER_WIDTH +: C_AXI_ARUSER_WIDTH], S_AXI_ARQOS[gen_si_slot*4+:4], S_AXI_ARCACHE[gen_si_slot*4+:4], S_AXI_ARBURST[gen_si_slot*2+:2], S_AXI_ARPROT[gen_si_slot*3+:3], S_AXI_ARLOCK[gen_si_slot*2+:2], S_AXI_ARSIZE[gen_si_slot*3+:3], S_AXI_ARLEN[gen_si_slot*8+:8], S_AXI_ARADDR[gen_si_slot*C_AXI_ADDR_WIDTH +: C_AXI_ADDR_WIDTH], f_extend_ID(S_AXI_ARID[gen_si_slot*C_AXI_ID_WIDTH +: C_AXI_ID_WIDTH], gen_si_slot) }; assign si_awmesg[gen_si_slot*P_AMESG_WIDTH +: P_AMESG_WIDTH] = { // Concatenate from MSB to LSB 4\'b0000, // S_AXI_AWREGION[gen_si_slot*4+:4], S_AXI_AWUSER[gen_si_slot*C_AXI_AWUSER_WIDTH +: C_AXI_AWUSER_WIDTH], S_AXI_AWQOS[gen_si_slot*4+:4], S_AXI_AWCACHE[gen_si_slot*4+:4], S_AXI_AWBURST[gen_si_slot*2+:2], S_AXI_AWPROT[gen_si_slot*3+:3], S_AXI_AWLOCK[gen_si_slot*2+:2], S_AXI_AWSIZE[gen_si_slot*3+:3], S_AXI_AWLEN[gen_si_slot*8+:8], S_AXI_AWADDR[gen_si_slot*C_AXI_ADDR_WIDTH +: C_AXI_ADDR_WIDTH], f_extend_ID(S_AXI_AWID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot) }; end // gen_si_amesg assign mi_aid = aa_amesg[0 +: C_AXI_ID_WIDTH]; assign mi_aaddr = aa_amesg[C_AXI_ID_WIDTH +: C_AXI_ADDR_WIDTH]; assign mi_alen = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +: 8]; assign mi_asize = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +: 3]; assign mi_alock = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +: 2]; assign mi_aprot = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +: 3]; assign mi_aburst = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +: 2]; assign mi_acache = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2 +: 4]; assign mi_aqos = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4 +: 4]; assign mi_auser = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4+4 +: P_AXI_AUSER_WIDTH]; assign mi_aregion = (C_ADDR_DECODE != 0) ? target_region : aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4+4+P_AXI_AUSER_WIDTH +: 4]; // Broadcast AW transfer payload to all MI-slots assign M_AXI_AWID = {C_NUM_MASTER_SLOTS{mi_aid}}; assign M_AXI_AWADDR = {C_NUM_MASTER_SLOTS{mi_aaddr}}; assign M_AXI_AWLEN = {C_NUM_MASTER_SLOTS{mi_alen }}; assign M_AXI_AWSIZE = {C_NUM_MASTER_SLOTS{mi_asize}}; assign M_AXI_AWLOCK = {C_NUM_MASTER_SLOTS{mi_alock}}; assign M_AXI_AWPROT = {C_NUM_MASTER_SLOTS{mi_aprot}}; assign M_AXI_AWREGION = {C_NUM_MASTER_SLOTS{mi_aregion}}; assign M_AXI_AWBURST = {C_NUM_MASTER_SLOTS{mi_aburst}}; assign M_AXI_AWCACHE = {C_NUM_MASTER_SLOTS{mi_acache}}; assign M_AXI_AWQOS = {C_NUM_MASTER_SLOTS{mi_aqos }}; assign M_AXI_AWUSER = {C_NUM_MASTER_SLOTS{mi_auser[0+:C_AXI_AWUSER_WIDTH] }}; // Broadcast AR transfer payload to all MI-slots assign M_AXI_ARID = {C_NUM_MASTER_SLOTS{mi_aid}}; assign M_AXI_ARADDR = {C_NUM_MASTER_SLOTS{mi_aaddr}}; assign M_AXI_ARLEN = {C_NUM_MASTER_SLOTS{mi_alen }}; assign M_AXI_ARSIZE = {C_NUM_MASTER_SLOTS{mi_asize}}; assign M_AXI_ARLOCK = {C_NUM_MASTER_SLOTS{mi_alock}}; assign M_AXI_ARPROT = {C_NUM_MASTER_SLOTS{mi_aprot}}; assign M_AXI_ARREGION = {C_NUM_MASTER_SLOTS{mi_aregion}}; assign M_AXI_ARBURST = {C_NUM_MASTER_SLOTS{mi_aburst}}; assign M_AXI_ARCACHE = {C_NUM_MASTER_SLOTS{mi_acache}}; assign M_AXI_ARQOS = {C_NUM_MASTER_SLOTS{mi_aqos }}; assign M_AXI_ARUSER = {C_NUM_MASTER_SLOTS{mi_auser[0+:C_AXI_ARUSER_WIDTH] }}; // W-channel MI handshakes assign M_AXI_WVALID = mi_wvalid[0+:C_NUM_MASTER_SLOTS]; assign mi_wready[0+:C_NUM_MASTER_SLOTS] = M_AXI_WREADY; // Broadcast W transfer payload to all MI-slots assign M_AXI_WLAST = {C_NUM_MASTER_SLOTS{mi_wlast}}; assign M_AXI_WUSER = {C_NUM_MASTER_SLOTS{mi_wuser}}; assign M_AXI_WDATA = {C_NUM_MASTER_SLOTS{mi_wdata}}; assign M_AXI_WSTRB = {C_NUM_MASTER_SLOTS{mi_wstrb}}; assign M_AXI_WID = {C_NUM_MASTER_SLOTS{mi_wid}}; // Broadcast R transfer payload to all SI-slots assign S_AXI_RLAST = {C_NUM_SLAVE_SLOTS{si_rlast}}; assign S_AXI_RRESP = {C_NUM_SLAVE_SLOTS{si_rresp}}; assign S_AXI_RUSER = {C_NUM_SLAVE_SLOTS{si_ruser}}; assign S_AXI_RDATA = {C_NUM_SLAVE_SLOTS{si_rdata}}; assign S_AXI_RID = {C_NUM_SLAVE_SLOTS{mi_aid}}; // Broadcast B transfer payload to all SI-slots assign S_AXI_BRESP = {C_NUM_SLAVE_SLOTS{si_bresp}}; assign S_AXI_BUSER = {C_NUM_SLAVE_SLOTS{si_buser}}; assign S_AXI_BID = {C_NUM_SLAVE_SLOTS{mi_aid}}; if (C_NUM_SLAVE_SLOTS>1) begin : gen_wmux // SI WVALID mux. generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (C_NUM_SLAVE_SLOTS), .C_SEL_WIDTH (P_NUM_SLAVE_SLOTS_LOG), .C_DATA_WIDTH (1) ) si_w_valid_mux_inst ( .S (aa_grant_enc), .A (S_AXI_WVALID), .O (aa_wvalid), .OE (w_transfer_en) ); // SI W-channel payload mux generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (C_NUM_SLAVE_SLOTS), .C_SEL_WIDTH (P_NUM_SLAVE_SLOTS_LOG), .C_DATA_WIDTH (P_WMESG_WIDTH) ) si_w_payload_mux_inst ( .S (aa_grant_enc), .A (si_wmesg), .O (mi_wmesg), .OE (1\'b1) ); for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_wmesg assign si_wmesg[gen_si_slot*P_WMESG_WIDTH+:P_WMESG_WIDTH] = { // Concatenate from MSB to LSB ((C_AXI_PROTOCOL == P_AXI3) ? f_extend_ID(S_AXI_WID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot) : 1\'b0), S_AXI_WUSER[gen_si_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH], S_AXI_WSTRB[gen_si_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8], S_AXI_WDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH], S_AXI_WLAST[gen_si_slot*1+:1] }; end // gen_wmesg assign mi_wlast = mi_wmesg[0]; assign mi_wdata = mi_wmesg[1 +: C_AXI_DATA_WIDTH]; assign mi_wstrb = mi_wmesg[1+C_AXI_DATA_WIDTH +: C_AXI_DATA_WIDTH/8]; assign mi_wuser = mi_wmesg[1+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8 +: C_AXI_WUSER_WIDTH]; assign mi_wid = mi_wmesg[1+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8+C_AXI_WUSER_WIDTH +: P_AXI_WID_WIDTH]; end else begin : gen_no_wmux assign aa_wvalid = w_transfer_en & S_AXI_WVALID; assign mi_wlast = S_AXI_WLAST; assign mi_wdata = S_AXI_WDATA; assign mi_wstrb = S_AXI_WSTRB; assign mi_wuser = S_AXI_WUSER; assign mi_wid = S_AXI_WID; end // gen_wmux // Receive RVALID from targeted MI. generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (P_NUM_MASTER_SLOTS_DE), .C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG), .C_DATA_WIDTH (1) ) mi_rvalid_mux_inst ( .S (m_atarget_enc), .A (mi_rvalid), .O (aa_rvalid), .OE (r_transfer_en) ); // MI R-channel payload mux generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (P_NUM_MASTER_SLOTS_DE), .C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG), .C_DATA_WIDTH (P_RMESG_WIDTH) ) mi_rmesg_mux_inst ( .S (m_atarget_enc), .A (mi_rmesg), .O (aa_rmesg), .OE (1\'b1) ); axi_register_slice_v2_1_axic_register_slice # ( .C_FAMILY (C_FAMILY), .C_DATA_WIDTH (P_RMESG_WIDTH), .C_REG_CONFIG (P_R_REG_CONFIG) ) reg_slice_r ( // System Signals .ACLK(ACLK), .ARESET(reset), // Slave side .S_PAYLOAD_DATA(aa_rmesg), .S_VALID(aa_rvalid), .S_READY(aa_rready), // Master side .M_PAYLOAD_DATA(sr_rmesg), .M_VALID(sr_rvalid), .M_READY(sr_rready) ); assign mi_rvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_RVALID; assign mi_rlast[0+:C_NUM_MASTER_SLOTS] = M_AXI_RLAST; assign mi_rresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_RRESP; assign mi_ruser[0+:C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH] = M_AXI_RUSER; assign mi_rdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH] = M_AXI_RDATA; assign M_AXI_RREADY = mi_rready[0+:C_NUM_MASTER_SLOTS]; for (gen_mi_slot=0; gen_mi_slot<P_NUM_MASTER_SLOTS_DE; gen_mi_slot=gen_mi_slot+1) begin : gen_rmesg assign mi_rmesg[gen_mi_slot*P_RMESG_WIDTH+:P_RMESG_WIDTH] = { // Concatenate from MSB to LSB mi_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH], mi_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH], mi_rresp[gen_mi_slot*2+:2], mi_rlast[gen_mi_slot*1+:1] }; end // gen_rmesg assign si_rlast = sr_rmesg[0]; assign si_rresp = sr_rmesg[1 +: 2]; assign si_rdata = sr_rmesg[1+2 +: C_AXI_DATA_WIDTH]; assign si_ruser = sr_rmesg[1+2+C_AXI_DATA_WIDTH +: C_AXI_RUSER_WIDTH]; // Receive BVALID from targeted MI. generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (P_NUM_MASTER_SLOTS_DE), .C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG), .C_DATA_WIDTH (1) ) mi_bvalid_mux_inst ( .S (m_atarget_enc), .A (mi_bvalid), .O (aa_bvalid), .OE (b_transfer_en) ); // MI B-channel payload mux generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (P_NUM_MASTER_SLOTS_DE), .C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG), .C_DATA_WIDTH (P_BMESG_WIDTH) ) mi_bmesg_mux_inst ( .S (m_atarget_enc), .A (mi_bmesg), .O (si_bmesg), .OE (1\'b1) ); assign mi_bvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_BVALID; assign mi_bresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_BRESP; assign mi_buser[0+:C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH] = M_AXI_BUSER; assign M_AXI_BREADY = mi_bready[0+:C_NUM_MASTER_SLOTS]; for (gen_mi_slot=0; gen_mi_slot<P_NUM_MASTER_SLOTS_DE; gen_mi_slot=gen_mi_slot+1) begin : gen_bmesg assign mi_bmesg[gen_mi_slot*P_BMESG_WIDTH+:P_BMESG_WIDTH] = { // Concatenate from MSB to LSB mi_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH], mi_bresp[gen_mi_slot*2+:2] }; end // gen_bmesg assign si_bresp = si_bmesg[0 +: 2]; assign si_buser = si_bmesg[2 +: C_AXI_BUSER_WIDTH]; if (C_DEBUG) begin : gen_debug_trans_seq // DEBUG WRITE TRANSACTION SEQUENCE COUNTER always @(posedge ACLK) begin if (reset) begin debug_aw_trans_seq_i <= 1; end else begin if (aa_awvalid && aa_awready) begin debug_aw_trans_seq_i <= debug_aw_trans_seq_i + 1; end end end // DEBUG READ TRANSACTION SEQUENCE COUNTER always @(posedge ACLK) begin if (reset) begin debug_ar_trans_seq_i <= 1; end else begin if (aa_arvalid && aa_arready) begin debug_ar_trans_seq_i <= debug_ar_trans_seq_i + 1; end end end // DEBUG WRITE BEAT COUNTER always @(posedge ACLK) begin if (reset) begin debug_w_beat_cnt_i <= 0; end else if (aa_wready & aa_wvalid) begin if (mi_wlast) begin debug_w_beat_cnt_i <= 0; end else begin debug_w_beat_cnt_i <= debug_w_beat_cnt_i + 1; end end end // Clocked process // DEBUG READ BEAT COUNTER always @(posedge ACLK) begin if (reset) begin debug_r_beat_cnt_i <= 0; end else if (sr_rready & sr_rvalid) begin if (si_rlast) begin debug_r_beat_cnt_i <= 0; end else begin debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1; end end end // Clocked process end // gen_debug_trans_seq if (C_RANGE_CHECK) begin : gen_decerr // Highest MI-slot (index C_NUM_MASTER_SLOTS) is the error handler axi_crossbar_v2_1_decerr_slave # ( .C_AXI_ID_WIDTH (1), .C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH), .C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH), .C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH), .C_AXI_PROTOCOL (C_AXI_PROTOCOL), .C_R'b"ESP (P_DECERR) ) decerr_slave_inst ( .S_AXI_ACLK (ACLK), .S_AXI_ARESET (reset), .S_AXI_AWID (1'b0), .S_AXI_AWVALID (mi_awvalid[C_NUM_MASTER_SLOTS]), .S_AXI_AWREADY (mi_awready[C_NUM_MASTER_SLOTS]), .S_AXI_WLAST (mi_wlast), .S_AXI_WVALID (mi_wvalid[C_NUM_MASTER_SLOTS]), .S_AXI_WREADY (mi_wready[C_NUM_MASTER_SLOTS]), .S_AXI_BID (), .S_AXI_BRESP (mi_bresp[C_NUM_MASTER_SLOTS*2+:2]), .S_AXI_BUSER (mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]), .S_AXI_BVALID (mi_bvalid[C_NUM_MASTER_SLOTS]), .S_AXI_BREADY (mi_bready[C_NUM_MASTER_SLOTS]), .S_AXI_ARID (1'b0), .S_AXI_ARLEN (mi_alen), .S_AXI_ARVALID (mi_arvalid[C_NUM_MASTER_SLOTS]), .S_AXI_ARREADY (mi_arready[C_NUM_MASTER_SLOTS]), .S_AXI_RID (), .S_AXI_RDATA (mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]), .S_AXI_RRESP (mi_rresp[C_NUM_MASTER_SLOTS*2+:2]), .S_AXI_RUSER (mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]), .S_AXI_RLAST (mi_rlast[C_NUM_MASTER_SLOTS]), .S_AXI_RVALID (mi_rvalid[C_NUM_MASTER_SLOTS]), .S_AXI_RREADY (mi_rready[C_NUM_MASTER_SLOTS]) ); end // gen_decerr endgenerate endmodule `default_nettype wire
// -- (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: This is a generic n-deep SRL instantiation // Verilog-standard: Verilog 2001 // $Revision: // $Date: // //----------------------------------------------------------------------------- `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_data_fifo_v2_1_ndeep_srl # ( parameter C_FAMILY = "rtl", // FPGA Family parameter C_A_WIDTH = 1 // Address Width (>= 1) ) ( input wire CLK, // Clock input wire [C_A_WIDTH-1:0] A, // Address input wire CE, // Clock Enable input wire D, // Input Data output wire Q // Output Data ); localparam integer P_SRLASIZE = 5; localparam integer P_SRLDEPTH = 32; localparam integer P_NUMSRLS = (C_A_WIDTH>P_SRLASIZE) ? (2**(C_A_WIDTH-P_SRLASIZE)) : 1; localparam integer P_SHIFT_DEPTH = 2**C_A_WIDTH; wire [P_NUMSRLS:0] d_i; wire [P_NUMSRLS-1:0] q_i; wire [(C_A_WIDTH>P_SRLASIZE) ? (C_A_WIDTH-1) : (P_SRLASIZE-1) : 0] a_i; genvar i; // Instantiate SRLs in carry chain format assign d_i[0] = D; assign a_i = A; generate \t\t\t\t\t if (C_FAMILY == "rtl") begin : gen_rtl_shifter if (C_A_WIDTH <= P_SRLASIZE) begin : gen_inferred_srl reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1\'b0}}; always @(posedge CLK) if (CE) shift_reg <= {shift_reg[P_SRLDEPTH-2:0], D}; assign Q = shift_reg[a_i]; end else begin : gen_logic_shifter // Very wasteful reg [P_SHIFT_DEPTH-1:0] shift_reg = {P_SHIFT_DEPTH{1\'b0}}; always @(posedge CLK) if (CE) shift_reg <= {shift_reg[P_SHIFT_DEPTH-2:0], D}; assign Q = shift_reg[a_i]; end end else begin : gen_primitive_shifter for (i=0;i<P_NUMSRLS;i=i+1) begin : gen_srls SRLC32E srl_inst ( .CLK (CLK), .A (a_i[P_SRLASIZE-1:0]), .CE (CE), .D (d_i[i]), .Q (q_i[i]), .Q31 (d_i[i+1]) ); end if (C_A_WIDTH>P_SRLASIZE) begin : gen_srl_mux generic_baseblocks_v2_1_nto1_mux # ( .C_RATIO (2**(C_A_WIDTH-P_SRLASIZE)), .C_SEL_WIDTH (C_A_WIDTH-P_SRLASIZE), .C_DATAOUT_WIDTH (1), .C_ONEHOT (0) ) srl_q_mux_inst ( .SEL_ONEHOT ({2**(C_A_WIDTH-P_SRLASIZE){1\'b0}}), .SEL (a_i[C_A_WIDTH-1:P_SRLASIZE]), .IN (q_i), .OUT (Q) ); end else begin : gen_no_srl_mux assign Q = q_i[0]; end end endgenerate endmodule `default_nettype wire
/***************************************************************************** * File : processing_system7_bfm_v2_0_gen_clock.v * * Date : 2012-11 * * Description : Module that generates FCLK clocks and internal clock for Zynq BFM. * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_gen_clock( ps_clk, sw_clk, fclk_clk3, fclk_clk2, fclk_clk1, fclk_clk0 ); input ps_clk; output sw_clk; output fclk_clk3; output fclk_clk2; output fclk_clk1; output fclk_clk0; parameter freq_clk3 = 50; parameter freq_clk2 = 50; parameter freq_clk1 = 50; parameter freq_clk0 = 50; reg clk0 = 1'b0; reg clk1 = 1'b0; reg clk2 = 1'b0; reg clk3 = 1'b0; reg sw_clk = 1'b0; assign fclk_clk0 = clk0; assign fclk_clk1 = clk1; assign fclk_clk2 = clk2; assign fclk_clk3 = clk3; real clk3_p = (1000.00/freq_clk3)/2; real clk2_p = (1000.00/freq_clk2)/2; real clk1_p = (1000.00/freq_clk1)/2; real clk0_p = (1000.00/freq_clk0)/2; always #(clk3_p) clk3 = !clk3; always #(clk2_p) clk2 = !clk2; always #(clk1_p) clk1 = !clk1; always #(clk0_p) clk0 = !clk0; always #(0.5) sw_clk = !sw_clk; endmodule
// (c) Copyright 2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // axi to vector // A generic module to merge all axi signals into one signal called payload. // This is strictly wires, so no clk, reset, aclken, valid/ready are required. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_infrastructure_v1_1_vector2axi # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// parameter integer C_AXI_PROTOCOL = 0, parameter integer C_AXI_ID_WIDTH = 4, parameter integer C_AXI_ADDR_WIDTH = 32, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0, parameter integer C_AXI_AWUSER_WIDTH = 1, parameter integer C_AXI_WUSER_WIDTH = 1, parameter integer C_AXI_BUSER_WIDTH = 1, parameter integer C_AXI_ARUSER_WIDTH = 1, parameter integer C_AXI_RUSER_WIDTH = 1, parameter integer C_AWPAYLOAD_WIDTH = 61, parameter integer C_WPAYLOAD_WIDTH = 73, parameter integer C_BPAYLOAD_WIDTH = 6, parameter integer C_ARPAYLOAD_WIDTH = 61, parameter integer C_RPAYLOAD_WIDTH = 69 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// // Slave Interface Write Address Ports output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid, output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen, output wire [3-1:0] m_axi_awsize, output wire [2-1:0] m_axi_awburst, output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock, output wire [4-1:0] m_axi_awcache, output wire [3-1:0] m_axi_awprot, output wire [4-1:0] m_axi_awregion, output wire [4-1:0] m_axi_awqos, output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser, // Slave Interface Write Data Ports output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid, output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata, output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb, output wire m_axi_wlast, output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser, // Slave Interface Write Response Ports input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid, input wire [2-1:0] m_axi_bresp, input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser, // Slave Interface Read Address Ports output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid, output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr, output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen, output wire [3-1:0] m_axi_arsize, output wire [2-1:0] m_axi_arburst, output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock, output wire [4-1:0] m_axi_arcache, output wire [3-1:0] m_axi_arprot, output wire [4-1:0] m_axi_arregion, output wire [4-1:0] m_axi_arqos, output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser, // Slave Interface Read Data Ports input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid, input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata, input wire [2-1:0] m_axi_rresp, input wire m_axi_rlast, input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser, // payloads input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload, input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload, output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload, input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload, output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload ); //////////////////////////////////////////////////////////////////////////////// // Functions //////////////////////////////////////////////////////////////////////////////// `include "axi_infrastructure_v1_1_header.vh" //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// // AXI4, AXI4LITE, AXI3 packing assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH]; assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH]; assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH]; assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH]; assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp; assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH]; assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH]; assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata; assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp; generate if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ; assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH]; assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH]; assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ; assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ; assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ; assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ; assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ; if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ; end else begin : gen_no_axi3_wid_packing assign m_axi_wid = 1\'b0; end assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid; assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ; assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH]; assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH]; assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ; assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ; assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ; assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ; assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast; assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ; if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH]; assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH]; end else begin : gen_no_region_signals assign m_axi_awregion = \'b0; assign m_axi_arregion = \'b0; end if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH]; assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ; assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ; assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH]; assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ; end else begin : gen_no_user_signals assign m_axi_awuser = \'b0; assign m_axi_wuser = \'b0; assign m_axi_aruser = \'b0; end end else begin : gen_axi4lite_packing assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3\'d2 : 3\'d3; assign m_axi_awburst = \'b0; assign m_axi_awcache = \'b0; assign m_axi_awlen = \'b0; assign m_axi_awlock = \'b0; assign m_axi_awid = \'b0; assign m_axi_awqos = \'b0; assign m_axi_wlast = 1\'b1; assign m_axi_wid = \'b0; assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3\'d2 : 3\'d3; assign m_axi_arburst = \'b0; assign m_axi_arcache = \'b0; assign m_axi_arlen = \'b0; assign m_axi_arlock = \'b0; assign m_axi_arid = \'b0; assign m_axi_arqos = \'b0; assign m_axi_awregion = \'b0; assign m_axi_arregion = \'b0; assign m_axi_awuser = \'b0; assign m_axi_wuser = \'b0; assign m_axi_aruser = \'b0; end endgenerate endmodule `default_nettype wire
// -- (c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: N-deep SRL pipeline element with generic single-channel AXI interfaces. // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // Structure: // axic_srl_fifo // ndeep_srl // nto1_mux //-------------------------------------------------------------------------- `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_data_fifo_v2_1_axic_srl_fifo # ( parameter C_FAMILY = "none", // FPGA Family parameter integer C_FIFO_WIDTH = 1, // Width of S_MESG/M_MESG. parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits // the control logic can be used // on before the control logic // needs to be replicated. parameter integer C_FIFO_DEPTH_LOG = 2, // Depth of FIFO is 2**C_FIFO_DEPTH_LOG. // The minimum size fifo generated is 4-deep. parameter C_USE_FULL = 1 // Prevent overwrite by throttling S_READY. ) ( input wire ACLK, // Clock input wire ARESET, // Reset input wire [C_FIFO_WIDTH-1:0] S_MESG, // Input data input wire S_VALID, // Input data valid output wire S_READY, // Input data ready output wire [C_FIFO_WIDTH-1:0] M_MESG, // Output data output wire M_VALID, // Output data valid input wire M_READY // Output data ready ); localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2; localparam P_EMPTY = {P_FIFO_DEPTH_LOG{1\'b1}}; localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1\'b0}}; localparam P_ALMOSTFULL_TEMP = {P_EMPTY, 1\'b0}; localparam P_ALMOSTFULL = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG]; localparam P_NUM_REPS = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ? (C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT : ((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1; (* syn_keep = "1" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr; (* syn_keep = "1" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i; genvar i; genvar j; reg M_VALID_i; reg S_READY_i; wire push; // FIFO push wire pop; // FIFO pop reg areset_d1; // Reset delay register wire [C_FIFO_WIDTH-1:0] m_axi_mesg_i; // Intermediate SRL data assign M_VALID = M_VALID_i; assign S_READY = C_USE_FULL ? S_READY_i : 1\'b1; assign M_MESG = m_axi_mesg_i; assign push = S_VALID & (C_USE_FULL ? S_READY_i : 1\'b1); assign pop = M_VALID_i & M_READY; always @(posedge ACLK) begin areset_d1 <= ARESET; end generate //--------------------------------------------------------------------------- // Create count of number of elements in FIFOs //--------------------------------------------------------------------------- for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] = push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 : fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1; always @(posedge ACLK) begin if (ARESET) fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <= {P_FIFO_DEPTH_LOG{1\'b1}}; else if (push ^ pop) fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <= fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i]; end end //--------------------------------------------------------------------------- // When FIFO is empty, reset master valid bit. When not empty set valid bit. // When FIFO is full, reset slave ready bit. When not full set ready bit. //--------------------------------------------------------------------------- always @(posedge ACLK) begin if (ARESET) begin M_VALID_i <= 1\'b0; end else if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] == P_ALMOSTEMPTY) && pop && ~push) begin M_VALID_i <= 1\'b0; end else if (push) begin M_VALID_i <= 1\'b1; end end always @(posedge ACLK) begin if (ARESET) begin S_READY_i <= 1\'b0; end else if (areset_d1) begin S_READY_i <= 1\'b1; end else if (C_USE_FULL && ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] == P_ALMOSTFULL) && push && ~pop)) begin S_READY_i <= 1\'b0; end else if (C_USE_FULL && pop) begin S_READY_i <= 1\'b1; end end //--------------------------------------------------------------------------- // Instantiate SRLs //--------------------------------------------------------------------------- for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep axi_data_fifo_v2_1_ndeep_srl # ( .C_FAMILY (C_FAMILY), .C_A_WIDTH (P_FIFO_DEPTH_LOG) ) srl_nx1 ( .CLK (ACLK), .A (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1: P_FIFO_DEPTH_LOG*(i)]), .CE (push), .D (S_MESG[i*C_MAX_CTRL_FANOUT+j]), .Q (m_axi_mesg_i[i*C_MAX_CTRL_FANOUT+j]) ); end end endgenerate endmodule `default_nettype wire
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: Read Data Response AXI3 Slave Converter // Forwards and re-assembles split transactions. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // r_axi3_conv // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module axi_protocol_converter_v2_1_r_axi3_conv # ( parameter C_FAMILY = "none", parameter integer C_AXI_ID_WIDTH = 1, parameter integer C_AXI_ADDR_WIDTH = 32, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, parameter integer C_AXI_RUSER_WIDTH = 1, parameter integer C_SUPPORT_SPLITTING = 1, // Implement transaction splitting logic. // Disabled whan all connected masters are AXI3 and have same or narrower data width. parameter integer C_SUPPORT_BURSTS = 1 // Disabled when all connected masters are AxiLite, // allowing logic to be simplified. ) ( // System Signals input wire ACLK, input wire ARESET, // Command Interface input wire cmd_valid, input wire cmd_split, output wire cmd_ready, // Slave Interface Read Data Ports output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID, output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA, output wire [2-1:0] S_AXI_RRESP, output wire S_AXI_RLAST, output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, output wire S_AXI_RVALID, input wire S_AXI_RREADY, // Master Interface Read Data Ports input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID, input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA, input wire [2-1:0] M_AXI_RRESP, input wire M_AXI_RLAST, input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER, input wire M_AXI_RVALID, output wire M_AXI_RREADY ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Constants for packing levels. localparam [2-1:0] C_RESP_OKAY = 2\'b00; localparam [2-1:0] C_RESP_EXOKAY = 2\'b01; localparam [2-1:0] C_RESP_SLVERROR = 2\'b10; localparam [2-1:0] C_RESP_DECERR = 2\'b11; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// // Throttling help signals. wire cmd_ready_i; wire pop_si_data; wire si_stalling; // Internal MI-side control signals. wire M_AXI_RREADY_I; // Internal signals for SI-side. wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID_I; wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA_I; wire [2-1:0] S_AXI_RRESP_I; wire S_AXI_RLAST_I; wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER_I; wire S_AXI_RVALID_I; wire S_AXI_RREADY_I; ///////////////////////////////////////////////////////////////////////////// // Handle interface handshaking: // // Forward data from MI-Side to SI-Side while a command is available. When // the transaction has completed the command is popped from the Command FIFO. // // ///////////////////////////////////////////////////////////////////////////// // Pop word from SI-side. assign M_AXI_RREADY_I = ~si_stalling & cmd_valid; assign M_AXI_RREADY = M_AXI_RREADY_I; // Indicate when there is data available @ SI-side. assign S_AXI_RVALID_I = M_AXI_RVALID & cmd_valid; // Get SI-side data. assign pop_si_data = S_AXI_RVALID_I & S_AXI_RREADY_I; // Signal that the command is done (so that it can be poped from command queue). assign cmd_ready_i = cmd_valid & pop_si_data & M_AXI_RLAST; assign cmd_ready = cmd_ready_i; // Detect when MI-side is stalling. assign si_stalling = S_AXI_RVALID_I & ~S_AXI_RREADY_I; ///////////////////////////////////////////////////////////////////////////// // Simple AXI signal forwarding: // // USER, ID, DATA and RRESP passes through untouched. // // LAST has to be filtered to remove any intermediate LAST (due to split // trasactions). LAST is only removed for the first parts of a split // transaction. When splitting is unsupported is the LAST filtering completely // completely removed. // ///////////////////////////////////////////////////////////////////////////// // Calculate last, i.e. mask from split transactions. assign S_AXI_RLAST_I = M_AXI_RLAST & ( ~cmd_split | ( C_SUPPORT_SPLITTING == 0 ) ); // Data is passed through. assign S_AXI_RID_I = M_AXI_RID; assign S_AXI_RUSER_I = M_AXI_RUSER; assign S_AXI_RDATA_I = M_AXI_RDATA; assign S_AXI_RRESP_I = M_AXI_RRESP; ///////////////////////////////////////////////////////////////////////////// // SI-side output handling // ///////////////////////////////////////////////////////////////////////////// // TODO: registered? assign S_AXI_RREADY_I = S_AXI_RREADY; assign S_AXI_RVALID = S_AXI_RVALID_I; assign S_AXI_RID = S_AXI_RID_I; assign S_AXI_RDATA = S_AXI_RDATA_I; assign S_AXI_RRESP = S_AXI_RRESP_I; assign S_AXI_RLAST = S_AXI_RLAST_I; assign S_AXI_RUSER = S_AXI_RUSER_I; endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_ocm_mem.v * * Date : 2012-11 * * Description : Mimics OCM model * *****************************************************************************/ module processing_system7_bfm_v2_0_ocm_mem(); `include "processing_system7_bfm_v2_0_local_params.v" parameter mem_size = 32\'h4_0000; /// 256 KB parameter mem_addr_width = clogb2(mem_size/mem_width); reg [data_width-1:0] ocm_memory [0:(mem_size/mem_width)-1]; /// 256 KB memory /* preload memory from file */ task automatic pre_load_mem_from_file; input [(max_chars*8)-1:0] file_name; input [addr_width-1:0] start_addr; input [int_width-1:0] no_of_bytes; $readmemh(file_name,ocm_memory,start_addr>>shft_addr_bits); endtask /* preload memory with some random data */ task automatic pre_load_mem; input [1:0] data_type; input [addr_width-1:0] start_addr; input [int_width-1:0] no_of_bytes; integer i; reg [mem_addr_width-1:0] addr; begin addr = start_addr >> shft_addr_bits; for (i = 0; i < no_of_bytes; i = i + mem_width) begin case(data_type) ALL_RANDOM : ocm_memory[addr] = $random; ALL_ZEROS : ocm_memory[addr] = 32\'h0000_0000; ALL_ONES : ocm_memory[addr] = 32\'hFFFF_FFFF; default : ocm_memory[addr] = $random; endcase addr = addr+1; end end endtask /* Write memory */ task write_mem; input [max_burst_bits-1 :0] data; input [addr_width-1:0] start_addr; input [max_burst_bytes_width:0] no_of_bytes; reg [mem_addr_width-1:0] addr; reg [max_burst_bits-1 :0] wr_temp_data; reg [data_width-1:0] pre_pad_data,post_pad_data,temp_data; integer bytes_left; integer pre_pad_bytes; integer post_pad_bytes; begin addr = start_addr >> shft_addr_bits; wr_temp_data = data; `ifdef XLNX_INT_DBG $display("[%0d] : %0s : Writing OCM Memory starting address (0x%0h) with %0d bytes.\ Data (0x%0h)",$time, DISP_INT_INFO, start_addr, no_of_bytes, data); `endif temp_data = wr_temp_data[data_width-1:0]; bytes_left = no_of_bytes; /* when the no. of bytes to be updated is less than mem_width */ if(bytes_left < mem_width) begin /* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/ if(start_addr[shft_addr_bits-1:0] > 0) begin temp_data = ocm_memory[addr]; pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0]; repeat(pre_pad_bytes) temp_data = temp_data << 8; repeat(pre_pad_bytes) begin temp_data = temp_data >> 8; temp_data[data_width-1:data_width-8] = wr_temp_data[7:0]; wr_temp_data = wr_temp_data >> 8; end bytes_left = bytes_left + pre_pad_bytes; end /* This is needed for post padding the data ...*/ post_pad_bytes = mem_width - bytes_left; post_pad_data = ocm_memory[addr]; repeat(post_pad_bytes) temp_data = temp_data << 8; repeat(bytes_left) post_pad_data = post_pad_data >> 8; repeat(post_pad_bytes) begin temp_data = temp_data >> 8; temp_data[data_width-1:data_width-8] = post_pad_data[7:0]; post_pad_data = post_pad_data >> 8; end ocm_memory[addr] = temp_data; end else begin /* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/ if(start_addr[shft_addr_bits-1:0] > 0) begin temp_data = ocm_memory[addr]; pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0]; repeat(pre_pad_bytes) temp_data = temp_data << 8; repeat(pre_pad_bytes) begin temp_data = temp_data >> 8; temp_data[data_width-1:data_width-8] = wr_temp_data[7:0]; wr_temp_data = wr_temp_data >> 8; bytes_left = bytes_left -1; end end else begin wr_temp_data = wr_temp_data >> data_width; bytes_left = bytes_left - mem_width; end /* first data word end */ ocm_memory[addr] = temp_data; addr = addr + 1; while(bytes_left > (mem_width-1) ) begin /// for unaliged address necessary to check for mem_wd-1 , accordingly we have to pad post bytes. ocm_memory[addr] = wr_temp_data[data_width-1:0]; addr = addr+1; wr_temp_data = wr_temp_data >> data_width; bytes_left = bytes_left - mem_width; end post_pad_data = ocm_memory[addr]; post_pad_bytes = mem_width - bytes_left; /* This is needed for last transfer in unaliged burst */ if(bytes_left > 0) begin temp_data = wr_temp_data[data_width-1:0]; repeat(post_pad_bytes) temp_data = temp_data << 8; repeat(bytes_left) post_pad_data = post_pad_data >> 8; repeat(post_pad_bytes) begin temp_data = temp_data >> 8; temp_data[data_width-1:data_width-8] = post_pad_data[7:0]; post_pad_data = post_pad_data >> 8; end ocm_memory[addr] = temp_data; end end `ifdef XLNX_INT_DBG $display("[%0d] : %0s : DONE -> Writing OCM Memory starting address (0x%0h)",$time, DISP_INT_INFO, start_addr ); `endif end endtask /* read_memory */ task read_mem; output[max_burst_bits-1 :0] data; input [addr_width-1:0] start_addr; input [max_burst_bytes_width:0] no_of_bytes; integer i; reg [mem_addr_width-1:0] addr; reg [data_width-1:0] temp_rd_data; reg [max_burst_bits-1:0] temp_data; integer pre_bytes; integer bytes_left; begin addr = start_addr >> shft_addr_bits; pre_bytes = start_addr[shft_addr_bits-1:0]; bytes_left = no_of_bytes; `ifdef XLNX_INT_DBG $display("[%0d] : %0s : Reading OCM Memory starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes ); `endif /* Get first data ... if unaligned address */ temp_data[max_burst_bits-1 : max_burst_bits-data_width] = ocm_memory[addr]; if(no_of_bytes < mem_width ) begin temp_data = temp_data >> (pre_bytes * 8); repeat(max_burst_bytes - mem_width) temp_data = temp_data >> 8; end else begin bytes_left = bytes_left - (mem_width - pre_bytes); addr = addr+1; /* Got first data */ while (bytes_left > (mem_width-1) ) begin temp_data = temp_data >> data_width; temp_data[max_burst_bits-1 : max_burst_bits-data_width] = ocm_memory[addr]; addr = addr+1; bytes_left = bytes_left - mem_width; end /* Get last valid data in the burst*/ temp_rd_data = ocm_memory[addr]; while(bytes_left > 0) begin temp_data = temp_data >> 8; temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0]; temp_rd_data = temp_rd_data >> 8; bytes_left = bytes_left - 1; end /* align to the brst_byte length */ repeat(max_burst_bytes - no_of_bytes) temp_data = temp_data >> 8; end data = temp_data; `ifdef XLNX_INT_DBG $display("[%0d] : %0s : DONE -> Reading OCM Memory starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data ); `endif end endtask /* backdoor read to memory */ task peek_mem_to_file; input [(max_chars*8)-1:0] file_name; input [addr_width-1:0] start_addr; input [int_width-1:0] no_of_bytes; integer rd_fd; integer bytes; reg [addr_width-1:0] addr; reg [data_width-1:0] rd_data; begin rd_fd = $fopen(file_name,"w"); bytes = no_of_bytes; addr = start_addr >> shft_addr_bits; while (bytes > 0) begin rd_data = ocm_memory[addr]; $fdisplayh(rd_fd,rd_data); bytes = bytes - 4; addr = addr + 1; end end endtask endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: // Optimized COMPARATOR with generic_baseblocks_v2_1_carry logic. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module generic_baseblocks_v2_1_comparator_mask # ( parameter C_FAMILY = "virtex6", // FPGA Family. Current version: virtex6 or spartan6. parameter integer C_DATA_WIDTH = 4 // Data width for comparator. ) ( input wire CIN, input wire [C_DATA_WIDTH-1:0] A, input wire [C_DATA_WIDTH-1:0] B, input wire [C_DATA_WIDTH-1:0] M, output wire COUT ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// // Generate variable for bit vector. genvar lut_cnt; ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Bits per LUT for this architecture. localparam integer C_BITS_PER_LUT = 2; // Constants for packing levels. localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT; // localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT : C_DATA_WIDTH; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// wire [C_FIX_DATA_WIDTH-1:0] a_local; wire [C_FIX_DATA_WIDTH-1:0] b_local; wire [C_FIX_DATA_WIDTH-1:0] m_local; wire [C_NUM_LUT-1:0] sel; wire [C_NUM_LUT:0] carry_local; ///////////////////////////////////////////////////////////////////////////// // ///////////////////////////////////////////////////////////////////////////// generate // Assign input to local vectors. assign carry_local[0] = CIN; // Extend input data to fit. if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}}; assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}}; assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}}; end else begin : NO_EXTENDED_DATA assign a_local = A; assign b_local = B; assign m_local = M; end // Instantiate one generic_baseblocks_v2_1_carry and per level. for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL // Create the local select signal assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) == ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ); // Instantiate each LUT level. generic_baseblocks_v2_1_carry_and # ( .C_FAMILY(C_FAMILY) ) compare_inst ( .COUT (carry_local[lut_cnt+1]), .CIN (carry_local[lut_cnt]), .S (sel[lut_cnt]) ); end // end for lut_cnt // Assign output from local vector. assign COUT = carry_local[C_NUM_LUT]; endgenerate endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_axi_gp.v * * Date : 2012-11 * * Description : Connections for AXI GP ports * *****************************************************************************/ /* IDs for Masters // l2m1 (CPU000) 12'b11_000_000_00_00 12'b11_010_000_00_00 12'b11_011_000_00_00 12'b11_100_000_00_00 12'b11_101_000_00_00 12'b11_110_000_00_00 12'b11_111_000_00_00 // l2m1 (CPU001) 12'b11_000_001_00_00 12'b11_010_001_00_00 12'b11_011_001_00_00 12'b11_100_001_00_00 12'b11_101_001_00_00 12'b11_110_001_00_00 12'b11_111_001_00_00 */ /* AXI -Master GP0 */ processing_system7_bfm_v2_0_axi_master #(C_USE_M_AXI_GP0, // enable axi_mgp0_name,// name axi_mgp_data_width, /// Data Width addr_width, /// Address width axi_mgp_id_width, //// ID Width axi_mgp_outstanding, //// Outstanding transactions axi_mst_excl_support, // EXCL Access Support axi_mgp_wr_id, //WR_ID axi_mgp_rd_id) //RD_ID M_AXI_GP0(.M_RESETN (net_axi_mgp0_rstn), .M_ACLK (M_AXI_GP0_ACLK), // Write Address Channel .M_AWID (M_AXI_GP0_AWID_FULL), .M_AWADDR (M_AXI_GP0_AWADDR), .M_AWLEN (M_AXI_GP0_AWLEN), .M_AWSIZE (M_AXI_GP0_AWSIZE), .M_AWBURST (M_AXI_GP0_AWBURST), .M_AWLOCK (M_AXI_GP0_AWLOCK), .M_AWCACHE (M_AXI_GP0_AWCACHE), .M_AWPROT (M_AXI_GP0_AWPROT), .M_AWVALID (M_AXI_GP0_AWVALID), .M_AWREADY (M_AXI_GP0_AWREADY), // Write Data Channel Signals. .M_WID (M_AXI_GP0_WID_FULL), .M_WDATA (M_AXI_GP0_WDATA), .M_WSTRB (M_AXI_GP0_WSTRB), .M_WLAST (M_AXI_GP0_WLAST), .M_WVALID (M_AXI_GP0_WVALID), .M_WREADY (M_AXI_GP0_WREADY), // Write Response Channel Signals. .M_BID (M_AXI_GP0_BID_FULL), .M_BRESP (M_AXI_GP0_BRESP), .M_BVALID (M_AXI_GP0_BVALID), .M_BREADY (M_AXI_GP0_BREADY), // Read Address Channel Signals. .M_ARID (M_AXI_GP0_ARID_FULL), .M_ARADDR (M_AXI_GP0_ARADDR), .M_ARLEN (M_AXI_GP0_ARLEN), .M_ARSIZE (M_AXI_GP0_ARSIZE), .M_ARBURST (M_AXI_GP0_ARBURST), .M_ARLOCK (M_AXI_GP0_ARLOCK), .M_ARCACHE (M_AXI_GP0_ARCACHE), .M_ARPROT (M_AXI_GP0_ARPROT), .M_ARVALID (M_AXI_GP0_ARVALID), .M_ARREADY (M_AXI_GP0_ARREADY), // Read Data Channel Signals. .M_RID (M_AXI_GP0_RID_FULL), .M_RDATA (M_AXI_GP0_RDATA), .M_RRESP (M_AXI_GP0_RRESP), .M_RLAST (M_AXI_GP0_RLAST), .M_RVALID (M_AXI_GP0_RVALID), .M_RREADY (M_AXI_GP0_RREADY), // Side band signals .M_AWQOS (M_AXI_GP0_AWQOS), .M_ARQOS (M_AXI_GP0_ARQOS) ); /* AXI Master GP1 */ processing_system7_bfm_v2_0_axi_master #(C_USE_M_AXI_GP1, // enable axi_mgp1_name,// name axi_mgp_data_width, /// Data Width addr_width, /// Address width axi_mgp_id_width, //// ID Width axi_mgp_outstanding, //// Outstanding transactions axi_mst_excl_support, // EXCL Access Support axi_mgp_wr_id, //WR_ID axi_mgp_rd_id) //RD_ID M_AXI_GP1(.M_RESETN (net_axi_mgp1_rstn), .M_ACLK (M_AXI_GP1_ACLK), // Write Address Channel .M_AWID (M_AXI_GP1_AWID_FULL), .M_AWADDR (M_AXI_GP1_AWADDR), .M_AWLEN (M_AXI_GP1_AWLEN), .M_AWSIZE (M_AXI_GP1_AWSIZE), .M_AWBURST (M_AXI_GP1_AWBURST), .M_AWLOCK (M_AXI_GP1_AWLOCK), .M_AWCACHE (M_AXI_GP1_AWCACHE), .M_AWPROT (M_AXI_GP1_AWPROT), .M_AWVALID (M_AXI_GP1_AWVALID), .M_AWREADY (M_AXI_GP1_AWREADY), // Write Data Channel Signals. .M_WID (M_AXI_GP1_WID_FULL), .M_WDATA (M_AXI_GP1_WDATA), .M_WSTRB (M_AXI_GP1_WSTRB), .M_WLAST (M_AXI_GP1_WLAST), .M_WVALID (M_AXI_GP1_WVALID), .M_WREADY (M_AXI_GP1_WREADY), // Write Response Channel Signals. .M_BID (M_AXI_GP1_BID_FULL), .M_BRESP (M_AXI_GP1_BRESP), .M_BVALID (M_AXI_GP1_BVALID), .M_BREADY (M_AXI_GP1_BREADY), // Read Address Channel Signals. .M_ARID (M_AXI_GP1_ARID_FULL), .M_ARADDR (M_AXI_GP1_ARADDR), .M_ARLEN (M_AXI_GP1_ARLEN), .M_ARSIZE (M_AXI_GP1_ARSIZE), .M_ARBURST (M_AXI_GP1_ARBURST), .M_ARLOCK (M_AXI_GP1_ARLOCK), .M_ARCACHE (M_AXI_GP1_ARCACHE), .M_ARPROT (M_AXI_GP1_ARPROT), .M_ARVALID (M_AXI_GP1_ARVALID), .M_ARREADY (M_AXI_GP1_ARREADY), // Read Data Channel Signals. .M_RID (M_AXI_GP1_RID_FULL), .M_RDATA (M_AXI_GP1_RDATA), .M_RRESP (M_AXI_GP1_RRESP), .M_RLAST (M_AXI_GP1_RLAST), .M_RVALID (M_AXI_GP1_RVALID), .M_RREADY (M_AXI_GP1_RREADY), // Side band signals .M_AWQOS (M_AXI_GP1_AWQOS), .M_ARQOS (M_AXI_GP1_ARQOS) ); /* AXI Slave GP0 */ processing_system7_bfm_v2_0_axi_slave #(C_USE_S_AXI_GP0, /// enable axi_sgp0_name, //name axi_sgp_data_width, /// data width addr_width, /// address width axi_sgp_id_width, /// ID width C_S_AXI_GP0_BASEADDR,//// base address C_S_AXI_GP0_HIGHADDR,/// Memory size (high_addr - base_addr) axi_sgp_outstanding, // outstanding transactions axi_slv_excl_support, // exclusive access not supported axi_sgp_wr_outstanding, axi_sgp_rd_outstanding) S_AXI_GP0(.S_RESETN (net_axi_gp0_rstn), .S_ACLK (S_AXI_GP0_ACLK), // Write Address Channel .S_AWID (S_AXI_GP0_AWID), .S_AWADDR (S_AXI_GP0_AWADDR), .S_AWLEN (S_AXI_GP0_AWLEN), .S_AWSIZE (S_AXI_GP0_AWSIZE), .S_AWBURST (S_AXI_GP0_AWBURST), .S_AWLOCK (S_AXI_GP0_AWLOCK), .S_AWCACHE (S_AXI_GP0_AWCACHE), .S_AWPROT (S_AXI_GP0_AWPROT), .S_AWVALID (S_AXI_GP0_AWVALID), .S_AWREADY (S_AXI_GP0_AWREADY), // Write Data Channel Signals. .S_WID (S_AXI_GP0_WID), .S_WDATA (S_AXI_GP0_WDATA), .S_WSTRB (S_AXI_GP0_WSTRB), .S_WLAST (S_AXI_GP0_WLAST), .S_WVALID (S_AXI_GP0_WVALID), .S_WREADY (S_AXI_GP0_WREADY), // Write Response Channel Signals. .S_BID (S_AXI_GP0_BID), .S_BRESP (S_AXI_GP0_BRESP), .S_BVALID (S_AXI_GP0_BVALID), .S_BREADY (S_AXI_GP0_BREADY), // Read Address Channel Signals. .S_ARID (S_AXI_GP0_ARID), .S_ARADDR (S_AXI_GP0_ARADDR), .S_ARLEN (S_AXI_GP0_ARLEN), .S_ARSIZE (S_AXI_GP0_ARSIZE), .S_ARBURST (S_AXI_GP0_ARBURST), .S_ARLOCK (S_AXI_GP0_ARLOCK), .S_ARCACHE (S_AXI_GP0_ARCACHE), .S_ARPROT (S_AXI_GP0_ARPROT), .S_ARVALID (S_AXI_GP0_ARVALID), .S_ARREADY (S_AXI_GP0_ARREADY), // Read Data Channel Signals. .S_RID (S_AXI_GP0_RID), .S_RDATA (S_AXI_GP0_RDATA), .S_RRESP (S_AXI_GP0_RRESP), .S_RLAST (S_AXI_GP0_RLAST), .S_RVALID (S_AXI_GP0_RVALID), .S_RREADY (S_AXI_GP0_RREADY), // Side band signals .S_AWQOS (S_AXI_GP0_AWQOS), .S_ARQOS (S_AXI_GP0_ARQOS), .SW_CLK (net_sw_clk), .WR_DATA_ACK_OCM (net_wr_ack_ocm_gp0), .WR_DATA_ACK_DDR (net_wr_ack_ddr_gp0), .WR_DATA (net_wr_data_gp0), .WR_ADDR (net_wr_addr_gp0), .WR_BYTES (net_wr_bytes_gp0), .WR_DATA_VALID_OCM (net_wr_dv_ocm_gp0), .WR_DATA_VALID_DDR (net_wr_dv_ddr_gp0), .WR_QOS (net_wr_qos_gp0), .RD_REQ_DDR (net_rd_req_ddr_gp0), .RD_REQ_OCM (net_rd_req_ocm_gp0), .RD_REQ_REG (net_rd_req_reg_gp0), .RD_ADDR (net_rd_addr_gp0), .RD_DATA_DDR (net_rd_data_ddr_gp0), .RD_DATA_OCM (net_rd_data_ocm_gp0), .RD_DATA_REG (net_rd_data_reg_gp0), .RD_BYTES (net_rd_bytes_gp0), .RD_DATA_VALID_DDR (net_rd_dv_ddr_gp0), .RD_DATA_VALID_OCM (net_rd_dv_ocm_gp0), .RD_DATA_VALID_REG (net_rd_dv_reg_gp0), .RD_QOS (net_rd_qos_gp0) ); /* AXI Slave GP1 */ processing_system7_bfm_v2_0_axi_slave #(C_USE_S_AXI_GP1, /// enable axi_sgp1_name, //name axi_sgp_data_width, /// data width addr_width, /// address width axi_sgp_id_width, /// ID width C_S_AXI_GP1_BASEADDR,//// base address C_S_AXI_GP1_HIGHADDR,/// HIGh_addr axi_sgp_outstanding, // outstanding transactions axi_slv_excl_support, // exclusive access axi_sgp_wr_outstanding, axi_sgp_rd_outstanding) S_AXI_GP1(.S_RESETN (net_axi_gp1_rstn), .S_ACLK (S_AXI_GP1_ACLK), // Write Address Channel .S_AWID (S_AXI_GP1_AWID), .S_AWADDR (S_AXI_GP1_AWADDR), .S_AWLEN (S_AXI_GP1_AWLEN), .S_AWSIZE (S_AXI_GP1_AWSIZE), .S_AWBURST (S_AXI_GP1_AWBURST), .S_AWLOCK (S_AXI_GP1_AWLOCK), .S_AWCACHE (S_AXI_GP1_AWCACHE), .S_AWPROT (S_AXI_GP1_AWPROT), .S_AWVALID (S_AXI_GP1_AWVALID), .S_AWREADY (S_AXI_GP1_AWREADY), // Write Data Channel Signals. .S_WID (S_AXI_GP1_WID), .S_WDATA (S_AXI_GP1_WDATA), .S_WSTRB (S_AXI_GP1_WSTRB), .S_WLAST (S_AXI_GP1_WLAST), .S_WVALID (S_AXI_GP1_WVALID), .S_WREADY (S_AXI_GP1_WREADY), // Write Response Channel Signals. .S_BID (S_AXI_GP1_BID), .S_BRESP (S_AXI_GP1_BRESP), .S_BVALID (S_AXI_GP1_BVALID), .S_BREADY (S_AXI_GP1_BREADY), // Read Address Channel Signals. .S_ARID (S_AXI_GP1_ARID), .S_ARADDR (S_AXI_GP1_ARADDR), .S_ARLEN (S_AXI_GP1_ARLEN), .S_ARSIZE (S_AXI_GP1_ARSIZE), .S_ARBURST (S_AXI_GP1_ARBURST), .S_ARLOCK (S_AXI_GP1_ARLOCK), .S_ARCACHE (S_AXI_GP1_ARCACHE), .S_ARPROT (S_AXI_GP1_ARPROT), .S_ARVALID (S_AXI_GP1_ARVALID), .S_ARREADY (S_AXI_GP1_ARREADY), // Read Data Channel Signals. .S_RID (S_AXI_GP1_RID), .S_RDATA (S_AXI_GP1_RDATA), .S_RRESP (S_AXI_GP1_RRESP), .S_RLAST (S_AXI_GP1_RLAST), .S_RVALID (S_AXI_GP1_RVALID), .S_RREADY (S_AXI_GP1_RREADY), // Side band signals .S_AWQOS (S_AXI_GP1_AWQOS), .S_ARQOS (S_AXI_GP1_ARQOS), .SW_CLK (net_sw_clk), .WR_DATA_ACK_DDR (net_wr_ack_ddr_gp1), .WR_DATA_ACK_OCM (net_wr_ack_ocm_gp1), .WR_DATA (net_wr_data_gp1), .WR_ADDR (net_wr_addr_gp1), .WR_BYTES (net_wr_bytes_gp1), .WR_DATA_VALID_OCM (net_wr_dv_ocm_gp1), .WR_DATA_VALID_DDR (net_wr_dv_ddr_gp1), .WR_QOS (net_wr_qos_gp1), .RD_REQ_OCM (net_rd_req_ocm_gp1), .RD_REQ_DDR (net_rd_req_ddr_gp1), .RD_REQ_REG (net_rd_req_reg_gp1), .RD_ADDR (net_rd_addr_gp1), .RD_DATA_DDR (net_rd_data_ddr_gp1), .RD_DATA_OCM (net_rd_data_ocm_gp1), .RD_DATA_REG (net_rd_data_reg_gp1), .RD_BYTES (net_rd_bytes_gp1), .RD_DATA_VALID_OCM (net_rd_dv_ocm_gp1), .RD_DATA_VALID_DDR (net_rd_dv_ddr_gp1), .RD_DATA_VALID_REG (net_rd_dv_reg_gp1), .RD_QOS (net_rd_qos_gp1) );
/***************************************************************************** * File : processing_system7_bfm_v2_0_ssw_hp.v * * Date : 2012-11 * * Description : SSW switch Model * *****************************************************************************/ module processing_system7_bfm_v2_0_ssw_hp( sw_clk, rstn, w_qos_hp0, r_qos_hp0, w_qos_hp1, r_qos_hp1, w_qos_hp2, r_qos_hp2, w_qos_hp3, r_qos_hp3, wr_ack_ddr_hp0, wr_data_hp0, wr_addr_hp0, wr_bytes_hp0, wr_dv_ddr_hp0, rd_req_ddr_hp0, rd_addr_hp0, rd_bytes_hp0, rd_data_ddr_hp0, rd_dv_ddr_hp0, rd_data_ocm_hp0, wr_ack_ocm_hp0, wr_dv_ocm_hp0, rd_req_ocm_hp0, rd_dv_ocm_hp0, wr_ack_ddr_hp1, wr_data_hp1, wr_addr_hp1, wr_bytes_hp1, wr_dv_ddr_hp1, rd_req_ddr_hp1, rd_addr_hp1, rd_bytes_hp1, rd_data_ddr_hp1, rd_data_ocm_hp1, rd_dv_ddr_hp1, wr_ack_ocm_hp1, wr_dv_ocm_hp1, rd_req_ocm_hp1, rd_dv_ocm_hp1, wr_ack_ddr_hp2, wr_data_hp2, wr_addr_hp2, wr_bytes_hp2, wr_dv_ddr_hp2, rd_req_ddr_hp2, rd_addr_hp2, rd_bytes_hp2, rd_data_ddr_hp2, rd_data_ocm_hp2, rd_dv_ddr_hp2, wr_ack_ocm_hp2, wr_dv_ocm_hp2, rd_req_ocm_hp2, rd_dv_ocm_hp2, wr_ack_ddr_hp3, wr_data_hp3, wr_addr_hp3, wr_bytes_hp3, wr_dv_ddr_hp3, rd_req_ddr_hp3, rd_addr_hp3, rd_bytes_hp3, rd_data_ocm_hp3, rd_data_ddr_hp3, rd_dv_ddr_hp3, wr_ack_ocm_hp3, wr_dv_ocm_hp3, rd_req_ocm_hp3, rd_dv_ocm_hp3, ddr_wr_ack0, ddr_wr_dv0, ddr_rd_req0, ddr_rd_dv0, ddr_rd_qos0, ddr_wr_qos0, ddr_wr_addr0, ddr_wr_data0, ddr_wr_bytes0, ddr_rd_addr0, ddr_rd_data0, ddr_rd_bytes0, ddr_wr_ack1, ddr_wr_dv1, ddr_rd_req1, ddr_rd_dv1, ddr_rd_qos1, ddr_wr_qos1, ddr_wr_addr1, ddr_wr_data1, ddr_wr_bytes1, ddr_rd_addr1, ddr_rd_data1, ddr_rd_bytes1, ocm_wr_ack, ocm_wr_dv, ocm_rd_req, ocm_rd_dv, ocm_wr_qos, ocm_rd_qos, ocm_wr_addr, ocm_wr_data, ocm_wr_bytes, ocm_rd_addr, ocm_rd_data, ocm_rd_bytes ); input sw_clk; input rstn; input [3:0] w_qos_hp0; input [3:0] r_qos_hp0; input [3:0] w_qos_hp1; input [3:0] r_qos_hp1; input [3:0] w_qos_hp2; input [3:0] r_qos_hp2; input [3:0] w_qos_hp3; input [3:0] r_qos_hp3; output [3:0] ddr_rd_qos0; output [3:0] ddr_wr_qos0; output [3:0] ddr_rd_qos1; output [3:0] ddr_wr_qos1; output [3:0] ocm_wr_qos; output [3:0] ocm_rd_qos; output wr_ack_ddr_hp0; input [1023:0] wr_data_hp0; input [31:0] wr_addr_hp0; input [7:0] wr_bytes_hp0; output wr_dv_ddr_hp0; input rd_req_ddr_hp0; input [31:0] rd_addr_hp0; input [7:0] rd_bytes_hp0; output [1023:0] rd_data_ddr_hp0; output rd_dv_ddr_hp0; output wr_ack_ddr_hp1; input [1023:0] wr_data_hp1; input [31:0] wr_addr_hp1; input [7:0] wr_bytes_hp1; output wr_dv_ddr_hp1; input rd_req_ddr_hp1; input [31:0] rd_addr_hp1; input [7:0] rd_bytes_hp1; output [1023:0] rd_data_ddr_hp1; output rd_dv_ddr_hp1; output wr_ack_ddr_hp2; input [1023:0] wr_data_hp2; input [31:0] wr_addr_hp2; input [7:0] wr_bytes_hp2; output wr_dv_ddr_hp2; input rd_req_ddr_hp2; input [31:0] rd_addr_hp2; input [7:0] rd_bytes_hp2; output [1023:0] rd_data_ddr_hp2; output rd_dv_ddr_hp2; output wr_ack_ddr_hp3; input [1023:0] wr_data_hp3; input [31:0] wr_addr_hp3; input [7:0] wr_bytes_hp3; output wr_dv_ddr_hp3; input rd_req_ddr_hp3; input [31:0] rd_addr_hp3; input [7:0] rd_bytes_hp3; output [1023:0] rd_data_ddr_hp3; output rd_dv_ddr_hp3; input ddr_wr_ack0; output ddr_wr_dv0; output [31:0]ddr_wr_addr0; output [1023:0]ddr_wr_data0; output [7:0]ddr_wr_bytes0; input ddr_rd_dv0; input [1023:0] ddr_rd_data0; output ddr_rd_req0; output [31:0] ddr_rd_addr0; output [7:0] ddr_rd_bytes0; input ddr_wr_ack1; output ddr_wr_dv1; output [31:0]ddr_wr_addr1; output [1023:0]ddr_wr_data1; output [7:0]ddr_wr_bytes1; input ddr_rd_dv1; input [1023:0] ddr_rd_data1; output ddr_rd_req1; output [31:0] ddr_rd_addr1; output [7:0] ddr_rd_bytes1; output wr_ack_ocm_hp0; input wr_dv_ocm_hp0; input rd_req_ocm_hp0; output rd_dv_ocm_hp0; output [1023:0] rd_data_ocm_hp0; output wr_ack_ocm_hp1; input wr_dv_ocm_hp1; input rd_req_ocm_hp1; output rd_dv_ocm_hp1; output [1023:0] rd_data_ocm_hp1; output wr_ack_ocm_hp2; input wr_dv_ocm_hp2; input rd_req_ocm_hp2; output rd_dv_ocm_hp2; output [1023:0] rd_data_ocm_hp2; output wr_ack_ocm_hp3; input wr_dv_ocm_hp3; input rd_req_ocm_hp3; output rd_dv_ocm_hp3; output [1023:0] rd_data_ocm_hp3; input ocm_wr_ack; output ocm_wr_dv; output [31:0]ocm_wr_addr; output [1023:0]ocm_wr_data; output [7:0]ocm_wr_bytes; input ocm_rd_dv; input [1023:0] ocm_rd_data; output ocm_rd_req; output [31:0] ocm_rd_addr; output [7:0] ocm_rd_bytes; /* FOR DDR */ processing_system7_bfm_v2_0_arb_hp0_1 ddr_hp01 ( .sw_clk(sw_clk), .rstn(rstn), .w_qos_hp0(w_qos_hp0), .r_qos_hp0(r_qos_hp0), .w_qos_hp1(w_qos_hp1), .r_qos_hp1(r_qos_hp1), .wr_ack_ddr_hp0(wr_ack_ddr_hp0), .wr_data_hp0(wr_data_hp0), .wr_addr_hp0(wr_addr_hp0), .wr_bytes_hp0(wr_bytes_hp0), .wr_dv_ddr_hp0(wr_dv_ddr_hp0), .rd_req_ddr_hp0(rd_req_ddr_hp0), .rd_addr_hp0(rd_addr_hp0), .rd_bytes_hp0(rd_bytes_hp0), .rd_data_ddr_hp0(rd_data_ddr_hp0), .rd_dv_ddr_hp0(rd_dv_ddr_hp0), .wr_ack_ddr_hp1(wr_ack_ddr_hp1), .wr_data_hp1(wr_data_hp1), .wr_addr_hp1(wr_addr_hp1), .wr_bytes_hp1(wr_bytes_hp1), .wr_dv_ddr_hp1(wr_dv_ddr_hp1), .rd_req_ddr_hp1(rd_req_ddr_hp1), .rd_addr_hp1(rd_addr_hp1), .rd_bytes_hp1(rd_bytes_hp1), .rd_data_ddr_hp1(rd_data_ddr_hp1), .rd_dv_ddr_hp1(rd_dv_ddr_hp1), .ddr_wr_ack(ddr_wr_ack0), .ddr_wr_dv(ddr_wr_dv0), .ddr_rd_req(ddr_rd_req0), .ddr_rd_dv(ddr_rd_dv0), .ddr_rd_qos(ddr_rd_qos0), .ddr_wr_qos(ddr_wr_qos0), .ddr_wr_addr(ddr_wr_addr0), .ddr_wr_data(ddr_wr_data0), .ddr_wr_bytes(ddr_wr_bytes0), .ddr_rd_addr(ddr_rd_addr0), .ddr_rd_data(ddr_rd_data0), .ddr_rd_bytes(ddr_rd_bytes0) ); /* FOR DDR */ processing_system7_bfm_v2_0_arb_hp2_3 ddr_hp23 ( .sw_clk(sw_clk), .rstn(rstn), .w_qos_hp2(w_qos_hp2), .r_qos_hp2(r_qos_hp2), .w_qos_hp3(w_qos_hp3), .r_qos_hp3(r_qos_hp3), .wr_ack_ddr_hp2(wr_ack_ddr_hp2), .wr_data_hp2(wr_data_hp2), .wr_addr_hp2(wr_addr_hp2), .wr_bytes_hp2(wr_bytes_hp2), .wr_dv_ddr_hp2(wr_dv_ddr_hp2), .rd_req_ddr_hp2(rd_req_ddr_hp2), .rd_addr_hp2(rd_addr_hp2), .rd_bytes_hp2(rd_bytes_hp2), .rd_data_ddr_hp2(rd_data_ddr_hp2), .rd_dv_ddr_hp2(rd_dv_ddr_hp2), .wr_ack_ddr_hp3(wr_ack_ddr_hp3), .wr_data_hp3(wr_data_hp3), .wr_addr_hp3(wr_addr_hp3), .wr_bytes_hp3(wr_bytes_hp3), .wr_dv_ddr_hp3(wr_dv_ddr_hp3), .rd_req_ddr_hp3(rd_req_ddr_hp3), .rd_addr_hp3(rd_addr_hp3), .rd_bytes_hp3(rd_bytes_hp3), .rd_data_ddr_hp3(rd_data_ddr_hp3), .rd_dv_ddr_hp3(rd_dv_ddr_hp3), .ddr_wr_ack(ddr_wr_ack1), .ddr_wr_dv(ddr_wr_dv1), .ddr_rd_req(ddr_rd_req1), .ddr_rd_dv(ddr_rd_dv1), .ddr_rd_qos(ddr_rd_qos1), .ddr_wr_qos(ddr_wr_qos1), .ddr_wr_addr(ddr_wr_addr1), .ddr_wr_data(ddr_wr_data1), .ddr_wr_bytes(ddr_wr_bytes1), .ddr_rd_addr(ddr_rd_addr1), .ddr_rd_data(ddr_rd_data1), .ddr_rd_bytes(ddr_rd_bytes1) ); /* FOR OCM_WR */ processing_system7_bfm_v2_0_arb_wr_4 ocm_wr_hp( .rstn(rstn), .sw_clk(sw_clk), .qos1(w_qos_hp0), .qos2(w_qos_hp1), .qos3(w_qos_hp2), .qos4(w_qos_hp3), .prt_dv1(wr_dv_ocm_hp0), .prt_dv2(wr_dv_ocm_hp1), .prt_dv3(wr_dv_ocm_hp2), .prt_dv4(wr_dv_ocm_hp3), .prt_data1(wr_data_hp0), .prt_data2(wr_data_hp1), .prt_data3(wr_data_hp2), .prt_data4(wr_data_hp3), .prt_addr1(wr_addr_hp0), .prt_addr2(wr_addr_hp1), .prt_addr3(wr_addr_hp2), .prt_addr4(wr_addr_hp3), .prt_bytes1(wr_bytes_hp0), .prt_bytes2(wr_bytes_hp1), .prt_bytes3(wr_bytes_hp2), .prt_bytes4(wr_bytes_hp3), .prt_ack1(wr_ack_ocm_hp0), .prt_ack2(wr_ack_ocm_hp1), .prt_ack3(wr_ack_ocm_hp2), .prt_ack4(wr_ack_ocm_hp3), .prt_qos(ocm_wr_qos), .prt_req(ocm_wr_dv), .prt_data(ocm_wr_data), .prt_addr(ocm_wr_addr), .prt_bytes(ocm_wr_bytes), .prt_ack(ocm_wr_ack) ); /* FOR OCM_RD */ processing_system7_bfm_v2_0_arb_rd_4 ocm_rd_hp( .rstn(rstn), .sw_clk(sw_clk), .qos1(r_qos_hp0), .qos2(r_qos_hp1), .qos3(r_qos_hp2), .qos4(r_qos_hp3), .prt_req1(rd_req_ocm_hp0), .prt_req2(rd_req_ocm_hp1), .prt_req3(rd_req_ocm_hp2), .prt_req4(rd_req_ocm_hp3), .prt_data1(rd_data_ocm_hp0), .prt_data2(rd_data_ocm_hp1), .prt_data3(rd_data_ocm_hp2), .prt_data4(rd_data_ocm_hp3), .prt_addr1(rd_addr_hp0), .prt_addr2(rd_addr_hp1), .prt_addr3(rd_addr_hp2), .prt_addr4(rd_addr_hp3), .prt_bytes1(rd_bytes_hp0), .prt_bytes2(rd_bytes_hp1), .prt_bytes3(rd_bytes_hp2), .prt_bytes4(rd_bytes_hp3), .prt_dv1(rd_dv_ocm_hp0), .prt_dv2(rd_dv_ocm_hp1), .prt_dv3(rd_dv_ocm_hp2), .prt_dv4(rd_dv_ocm_hp3), .prt_qos(ocm_rd_qos), .prt_req(ocm_rd_req), .prt_data(ocm_rd_data), .prt_addr(ocm_rd_addr), .prt_bytes(ocm_rd_bytes), .prt_dv(ocm_rd_dv) ); endmodule
always @(negedge reset or posedge clk) begin if (reset == 0) begin d_out <= 16'h0000; d_out_mem[resetcount] <= d_out; laststoredvalue <= d_out; end else begin d_out <= d_out + 1'b1; end end always @(bufreadaddr) bufreadval = d_out_mem[bufreadaddr];
module sha256_const(addr, k); input wire [5:0] addr; output wire [31:0] k; wire [63:0] addr_decode; my_decoder decoder(addr, addr_decode); assign k = addr_decode[0] ? 32'h428a2f98 : 32'bz; assign k = addr_decode[1] ? 32'h71374491 : 32'bz; assign k = addr_decode[2] ? 32'hb5c0fbcf : 32'bz; assign k = addr_decode[3] ? 32'he9b5dba5 : 32'bz; assign k = addr_decode[4] ? 32'h3956c25b : 32'bz; assign k = addr_decode[5] ? 32'h59f111f1 : 32'bz; assign k = addr_decode[6] ? 32'h923f82a4 : 32'bz; assign k = addr_decode[7] ? 32'hab1c5ed5 : 32'bz; assign k = addr_decode[8] ? 32'hd807aa98 : 32'bz; assign k = addr_decode[9] ? 32'h12835b01 : 32'bz; assign k = addr_decode[10] ? 32'h243185be : 32'bz; assign k = addr_decode[11] ? 32'h550c7dc3 : 32'bz; assign k = addr_decode[12] ? 32'h72be5d74 : 32'bz; assign k = addr_decode[13] ? 32'h80deb1fe : 32'bz; assign k = addr_decode[14] ? 32'h9bdc06a7 : 32'bz; assign k = addr_decode[15] ? 32'hc19bf174 : 32'bz; assign k = addr_decode[16] ? 32'he49b69c1 : 32'bz; assign k = addr_decode[17] ? 32'hefbe4786 : 32'bz; assign k = addr_decode[18] ? 32'h0fc19dc6 : 32'bz; assign k = addr_decode[19] ? 32'h240ca1cc : 32'bz; assign k = addr_decode[20] ? 32'h2de92c6f : 32'bz; assign k = addr_decode[21] ? 32'h4a7484aa : 32'bz; assign k = addr_decode[22] ? 32'h5cb0a9dc : 32'bz; assign k = addr_decode[23] ? 32'h76f988da : 32'bz; assign k = addr_decode[24] ? 32'h983e5152 : 32'bz; assign k = addr_decode[25] ? 32'ha831c66d : 32'bz; assign k = addr_decode[26] ? 32'hb00327c8 : 32'bz; assign k = addr_decode[27] ? 32'hbf597fc7 : 32'bz; assign k = addr_decode[28] ? 32'hc6e00bf3 : 32'bz; assign k = addr_decode[29] ? 32'hd5a79147 : 32'bz; assign k = addr_decode[30] ? 32'h06ca6351 : 32'bz; assign k = addr_decode[31] ? 32'h14292967 : 32'bz; assign k = addr_decode[32] ? 32'h27b70a85 : 32'bz; assign k = addr_decode[33] ? 32'h2e1b2138 : 32'bz; assign k = addr_decode[34] ? 32'h4d2c6dfc : 32'bz; assign k = addr_decode[35] ? 32'h53380d13 : 32'bz; assign k = addr_decode[36] ? 32'h650a7354 : 32'bz; assign k = addr_decode[37] ? 32'h766a0abb : 32'bz; assign k = addr_decode[38] ? 32'h81c2c92e : 32'bz; assign k = addr_decode[39] ? 32'h92722c85 : 32'bz; assign k = addr_decode[40] ? 32'ha2bfe8a1 : 32'bz; assign k = addr_decode[41] ? 32'ha81a664b : 32'bz; assign k = addr_decode[42] ? 32'hc24b8b70 : 32'bz; assign k = addr_decode[43] ? 32'hc76c51a3 : 32'bz; assign k = addr_decode[44] ? 32'hd192e819 : 32'bz; assign k = addr_decode[45] ? 32'hd6990624 : 32'bz; assign k = addr_decode[46] ? 32'hf40e3585 : 32'bz; assign k = addr_decode[47] ? 32'h106aa070 : 32'bz; assign k = addr_decode[48] ? 32'h19a4c116 : 32'bz; assign k = addr_decode[49] ? 32'h1e376c08 : 32'bz; assign k = addr_decode[50] ? 32'h2748774c : 32'bz; assign k = addr_decode[51] ? 32'h34b0bcb5 : 32'bz; assign k = addr_decode[52] ? 32'h391c0cb3 : 32'bz; assign k = addr_decode[53] ? 32'h4ed8aa4a : 32'bz; assign k = addr_decode[54] ? 32'h5b9cca4f : 32'bz; assign k = addr_decode[55] ? 32'h682e6ff3 : 32'bz; assign k = addr_decode[56] ? 32'h748f82ee : 32'bz; assign k = addr_decode[57] ? 32'h78a5636f : 32'bz; assign k = addr_decode[58] ? 32'h84c87814 : 32'bz; assign k = addr_decode[59] ? 32'h8cc70208 : 32'bz; assign k = addr_decode[60] ? 32'h90befffa : 32'bz; assign k = addr_decode[61] ? 32'ha4506ceb : 32'bz; assign k = addr_decode[62] ? 32'hbef9a3f7 : 32'bz; assign k = addr_decode[63] ? 32'hc67178f2 : 32'bz; endmodule module my_decoder (d,q); input [5:0] d; output [63:0] q; assign q = 1'b1 << d; endmodule
//====================================================================== // // sha256_w_mem_regs.v // ------------------- // The W memory. This version uses 16 32-bit registers as a sliding // window to generate the 64 words. // //====================================================================== module sha256_w_mem( input wire clk, input wire reset_n, input wire [511 : 0] block, input wire init, input wire next, output wire [31 : 0] w ); //---------------------------------------------------------------- // Internal constant and parameter definitions. //---------------------------------------------------------------- parameter CTRL_IDLE = 0; parameter CTRL_UPDATE = 1; //---------------------------------------------------------------- // Registers including update variables and write enable. //---------------------------------------------------------------- reg [31 : 0] w_mem [0 : 15]; reg [31 : 0] w_mem00_new; reg [31 : 0] w_mem01_new; reg [31 : 0] w_mem02_new; reg [31 : 0] w_mem03_new; reg [31 : 0] w_mem04_new; reg [31 : 0] w_mem05_new; reg [31 : 0] w_mem06_new; reg [31 : 0] w_mem07_new; reg [31 : 0] w_mem08_new; reg [31 : 0] w_mem09_new; reg [31 : 0] w_mem10_new; reg [31 : 0] w_mem11_new; reg [31 : 0] w_mem12_new; reg [31 : 0] w_mem13_new; reg [31 : 0] w_mem14_new; reg [31 : 0] w_mem15_new; reg w_mem_we; reg [5 : 0] w_ctr_reg; reg [5 : 0] w_ctr_new; reg w_ctr_we; reg w_ctr_inc; reg w_ctr_rst; reg [1 : 0] sha256_w_mem_ctrl_reg; reg [1 : 0] sha256_w_mem_ctrl_new; reg sha256_w_mem_ctrl_we; //---------------------------------------------------------------- // Wires. //---------------------------------------------------------------- reg [31 : 0] w_tmp; reg [31 : 0] w_new; //---------------------------------------------------------------- // Concurrent connectivity for ports etc. //---------------------------------------------------------------- assign w = w_tmp; //---------------------------------------------------------------- // reg_update // Update functionality for all registers in the core. // All registers are positive edge triggered with synchronous // active low reset. All registers have write enable. //---------------------------------------------------------------- always @ (posedge clk or negedge reset_n) begin : reg_update if (!reset_n) begin w_mem[00] <= 32'h0; w_mem[01] <= 32'h0; w_mem[02] <= 32'h0; w_mem[03] <= 32'h0; w_mem[04] <= 32'h0; w_mem[05] <= 32'h0; w_mem[06] <= 32'h0; w_mem[07] <= 32'h0; w_mem[08] <= 32'h0; w_mem[09] <= 32'h0; w_mem[10] <= 32'h0; w_mem[11] <= 32'h0; w_mem[12] <= 32'h0; w_mem[13] <= 32'h0; w_mem[14] <= 32'h0; w_mem[15] <= 32'h0; w_ctr_reg <= 6'h00; sha256_w_mem_ctrl_reg <= CTRL_IDLE; end else begin if (w_mem_we) begin w_mem[00] <= w_mem00_new; w_mem[01] <= w_mem01_new; w_mem[02] <= w_mem02_new; w_mem[03] <= w_mem03_new; w_mem[04] <= w_mem04_new; w_mem[05] <= w_mem05_new; w_mem[06] <= w_mem06_new; w_mem[07] <= w_mem07_new; w_mem[08] <= w_mem08_new; w_mem[09] <= w_mem09_new; w_mem[10] <= w_mem10_new; w_mem[11] <= w_mem11_new; w_mem[12] <= w_mem12_new; w_mem[13] <= w_mem13_new; w_mem[14] <= w_mem14_new; w_mem[15] <= w_mem15_new; end if (w_ctr_we) w_ctr_reg <= w_ctr_new; if (sha256_w_mem_ctrl_we) sha256_w_mem_ctrl_reg <= sha256_w_mem_ctrl_new; end end // reg_update //---------------------------------------------------------------- // select_w // // Mux for the external read operation. This is where we exract // the W variable. //---------------------------------------------------------------- always @* begin : select_w if (w_ctr_reg < 16) begin w_tmp = w_mem[w_ctr_reg[3 : 0]]; end else begin w_tmp = w_new; end end // select_w //---------------------------------------------------------------- // w_new_logic // // Logic that calculates the next value to be inserted into // the sliding window of the memory. //---------------------------------------------------------------- always @* begin : w_mem_update_logic reg [31 : 0] w_0; reg [31 : 0] w_1; reg [31 : 0] w_9; reg [31 : 0] w_14; reg [31 : 0] d0; reg [31 : 0] d1; w_mem00_new = 32'h0; w_mem01_new = 32'h0; w_mem02_new = 32'h0; w_mem03_new = 32'h0; w_mem04_new = 32'h0; w_mem05_new = 32'h0; w_mem06_new = 32'h0; w_mem07_new = 32'h0; w_mem08_new = 32'h0; w_mem09_new = 32'h0; w_mem10_new = 32'h0; w_mem11_new = 32'h0; w_mem12_new = 32'h0; w_mem13_new = 32'h0; w_mem14_new = 32'h0; w_mem15_new = 32'h0; w_mem_we = 0; w_0 = w_mem[0]; w_1 = w_mem[1]; w_9 = w_mem[9]; w_14 = w_mem[14]; d0 = {w_1[6 : 0], w_1[31 : 7]} ^ {w_1[17 : 0], w_1[31 : 18]} ^ {3'b000, w_1[31 : 3]}; d1 = {w_14[16 : 0], w_14[31 : 17]} ^ {w_14[18 : 0], w_14[31 : 19]} ^ {10'b0000000000, w_14[31 : 10]}; w_new = d1 + w_9 + d0 + w_0; if (init) begin w_mem00_new = block[511 : 480]; w_mem01_new = block[479 : 448]; w_mem02_new = block[447 : 416]; w_mem03_new = block[415 : 384]; w_mem04_new = block[383 : 352]; w_mem05_new = block[351 : 320]; w_mem06_new = block[319 : 288]; w_mem07_new = block[287 : 256]; w_mem08_new = block[255 : 224]; w_mem09_new = block[223 : 192]; w_mem10_new = block[191 : 160]; w_mem11_new = block[159 : 128]; w_mem12_new = block[127 : 96]; w_mem13_new = block[95 : 64]; w_mem14_new = block[63 : 32]; w_mem15_new = block[31 : 0]; w_mem_we = 1; end else if (w_ctr_reg > 15) begin w_mem00_new = w_mem[01]; w_mem01_new = w_mem[02]; w_mem02_new = w_mem[03]; w_mem03_new = w_mem[04]; w_mem04_new = w_mem[05]; w_mem05_new = w_mem[06]; w_mem06_new = w_mem[07]; w_mem07_new = w_mem[08]; w_mem08_new = w_mem[09]; w_mem09_new = w_mem[10]; w_mem10_new = w_mem[11]; w_mem11_new = w_mem[12]; w_mem12_new = w_mem[13]; w_mem13_new = w_mem[14]; w_mem14_new = w_mem[15]; w_mem15_new = w_new; w_mem_we = 1; end end // w_mem_update_logic //---------------------------------------------------------------- // w_ctr // W schedule adress counter. Counts from 0x10 to 0x3f and // is used to expand the block into words. //---------------------------------------------------------------- always @* begin : w_ctr w_ctr_new = 0; w_ctr_we = 0; if (w_ctr_rst) begin w_ctr_new = 6'h00; w_ctr_we = 1; end if (w_ctr_inc) begin w_ctr_new = w_ctr_reg + 6'h01; w_ctr_we = 1; end end // w_ctr //---------------------------------------------------------------- // sha256_w_mem_fsm // Logic for the w shedule FSM. //---------------------------------------------------------------- always @* begin : sha256_w_mem_fsm w_ctr_rst = 0; w_ctr_inc = 0; sha256_w_mem_ctrl_new = CTRL_IDLE; sha256_w_mem_ctrl_we = 0; case (sha256_w_mem_ctrl_reg) CTRL_IDLE: begin if (init) begin w_ctr_rst = 1; sha256_w_mem_ctrl_new = CTRL_UPDATE; sha256_w_mem_ctrl_we = 1; end end CTRL_UPDATE: begin if (next) begin w_ctr_inc = 1; end if (w_ctr_reg == 6'h3f) begin sha256_w_mem_ctrl_new = CTRL_IDLE; sha256_w_mem_ctrl_we = 1; end end endcase // case (sha256_ctrl_reg) end // sha256_ctrl_fsm endmodule // sha256_w_mem //====================================================================== // sha256_mem.v
module sha256_dgt( input wire clk, input wire reset, input wire ctrl, input wire [511:0] blk, output wire ready, output wire [255:0] dgt, ); endmodule
parameter ramaddr_0 = {1'b1,9'd0};
// Taken from http://www.europa.com/~celiac/fsm_samp.html // These are the symbolic names for states parameter [1:0] //synopsys enum state_info S0 = 2'h0, S1 = 2'h1, S2 = 2'h2, S3 = 2'h3; // These are the current state and next state variables reg [1:0] /* synopsys enum state_info */ state; reg [1:0] /* synopsys enum state_info */ next_state; // synopsys state_vector state always @ (state or y or x) begin next_state = state; case (state) // synopsys full_case parallel_case S0: begin if (x) begin next_state = S1; end else begin next_state = S2; end end S1: begin if (y) begin next_state = S2; end else begin next_state = S0; end end S2: begin if (x & y) begin next_state = S3; end else begin next_state = S0; end end S3: begin next_state = S0; end endcase end always @ (posedge clk or posedge reset) begin if (reset) begin state <= S0; end else begin state <= next_state; end end
/* * In Verilog, the following two lines are both valid syntax: * * `define GUEST * `define GUEST <value> * * The first defines "GUEST" as existing, but with no assigned * value. The second defines "GUEST" as existing with an * assigned value. Ctags55 correctly handles both cases, but * Ctags551 - Ctags554 only handles the `define with value * correctly. Here is some test code to demonstrate this: */ `define HOSTA `define HOSTB `define HOSTC `define HOSTD `define GUESTA 1 `define GUESTB 2 `define GUESTC 3 `define GUESTD 4 /* * Ctags55 correctly generates a tag for all `defines in the * code, but Ctags554 does not generate tags for "HOSTB" * or "HOSTD". */
// http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html#RTFToC33 // Digital model of a traffic light // By Dan Hyde August 10, 1995 module traffic; parameter on = 1, off = 0, red_tics = 35, amber_tics = 3, green_tics = 20; reg clock, red, amber, green; // will stop the simulation after 1000 time units initial begin: stop_at #1000; $stop; end // initialize the lights and set up monitoring of registers initial begin: Init red = off; amber = off; green = off; $display(" Time green amber red"); $monitor("%3d %b %b %b", $time, green, amber, red); end // task to wait for \'tics\' positive edge clocks // before turning light off task light; output color; input [31:0] tics; begin repeat(tics) // wait to detect tics positive edges on clock @(posedge clock); color = off; end endtask // waveform for clock period of 2 time units always begin: clock_wave #1 clock = 0; #1 clock = 1; end always begin: main_process red = on; light(red, red_tics); // call task to wait green = on; light(green, green_tics); amber = on; light(amber, amber_tics); end endmodule
// File example.v // // Below is an example of a comment that is mis-parsed by exuberant ctags. // It uses the multi-line comment format, i.e. /* ... */ except that in // this case, the character sequence immediately preceeding the closing // delimiter is an asterisk. (Any even number of asterisks would have the // same problem. // The line immediately afterwards is used to demonstrate the problem. // the module name 'wahoo' isn't recognised, because the parser mistakenly // thinks we are still in a multi-line comment. /* * I am a multi-line comment * I happen to end in a strange * (but legal) way: **/ module wahoo () begin end
/* * **/ module top(outsig, insig); output outsig; input insig; assign outsig = insig; endmodule
/* Bugs item #762027, was opened at 2003-06-27 18:32 Message generated for change (Tracker Item Submitted) made by Item Submitter You can respond by visiting: https://sourceforge.net/tracker/?func=detail&atid=106556&aid=762027&group_id=6556 Category: None Group: None Status: Open Resolution: None Priority: 5 Submitted By: cdic (cdic) Assigned to: Nobody/Anonymous (nobody) Summary: multi-line definition w/o back-slash will be missing Initial Comment: There is a small bug (language verilog): */ wire N_84, N_83; // is ok. wire N_84, N_83; // then N_83 will be missing in tags. /* Thanks for fixing it. cdic */
/************************************************************************** **** * test task one * the line below has 53 asteriks *****************************************************/ task pass_task_1; begin end endtask /************************************************************************** **** * test task one * the line below has 54 asteriks ******************************************************/ task fail_task_2; begin end endtask /************************************************************************** **** * test function one * the line below has 53 asteriks *****************************************************/ function pass_func_1; begin end endfunction /************************************************************************** **** * test function two * the line below has 54 asteriks ******************************************************/ function fail_func_2; begin end endfunction /************************************************************************** **** * test function one * the line below has 53 asteriks *****************************************************/ `define pass_define_1 1'b1; /************************************************************************** **** * test function two * the line below has 54 asteriks ******************************************************/ `define fail_define_2 1'b1;
// somewhat contrived, but i came across a real-life file that caused this // crash. value= hello/ world; // dummy stuff to generate a tag module dummy; endmodule
module main(); parameter PER = 10; parameter WIDTH = 8; reg clk; reg rst; // read channels reg read_en; wire [WIDTH-1:0] read_data; wire read_data_valid; // write channels reg write_en; reg [WIDTH-1:0] write_data; wire write_data_ready; // controls reg read_req; reg [31:0] read_addr; reg [31:0] read_size; reg write_req; reg [31:0] write_addr; reg [31:0] write_size; always begin #(PER/2) clk =~ clk; end tvm_vpi_mem_interface # ( .READ_WIDTH(WIDTH), .WRITE_WIDTH(WIDTH), .ADDR_WIDTH(32), .SIZE_WIDTH(32) ) mem ( .clk(clk), .rst(rst), .read_en(read_en), .read_data_out(read_data), .read_data_valid(read_data_valid), .write_en(write_en), .write_data_in(write_data), .write_data_ready(write_data_ready), .host_read_req(read_req), .host_read_addr(read_addr), .host_read_size(read_size), .host_write_req(write_req), .host_write_addr(write_addr), .host_write_size(write_size) ); initial begin // pass myram to session to hook it up with simulation $tvm_session(clk, mem); end endmodule
`include "tvm_marcos.v" module main(); `TVM_DEFINE_TEST_SIGNAL(clk, rst) wire[3:0] counter; counter counter_unit1(.clk(clk), .rst(rst), .out(counter)); initial begin // This will allow tvm session to be called every cycle. $tvm_session(clk); end endmodule
// Nonstop version of loop // Always keeps looping when increase == true // At end is a signal to indicate the next cycle is end // Use that to signal parent loop to advance. `define NONSTOP_LOOP(iter, width, init, ready, finish, min, extent)\\ reg [width-1:0] iter;\\ wire finish;\\ always@(posedge clk) begin\\ if (rst || init) begin\\ iter <= (min);\\ end else if(ready) begin\\ if (iter != ((extent)-1)) begin\\ iter <= iter + 1;\\ end else begin\\ iter <= (min);\\ end\\ end else begin\\ iter <= iter;\\ end\\ end\\ assign finish = (ready && (iter == (extent) - 1)); // Wrap a nonstop loop to normal loop that loop only once. // Use done signal to control the non-stop body to stop. // The init and done behaves like normal loop `define WRAP_LOOP_ONCE(init, valid, ready, body_finish, body_ready)\\ reg valid;\\ wire body_ready;\\ always@(posedge clk) begin\\ if (rst || init) begin\\ valid <= 1;\\ end else if(body_finish) begin\\ valid <= 0;\\ end else begin\\ valid <= valid;\\ end\\ end\\ assign body_ready = (valid && ready); // Assign dst as src delayed by specific cycles. `define DELAY(dst, src, width, delay, not_stall)\\ reg [(width)*(delay)-1:0] src``_dly_chain;\\ always@(posedge clk) begin\\ if(rst) begin\\ src``_dly_chain <= 0;\\ end else if (not_stall) begin\\ src``_dly_chain[(width)-1:0] <= src;\\ if((delay) != 1) begin\\ src``_dly_chain[(delay)*(width)-1:(width)] <= src``_dly_chain[((delay)-1)*(width)-1:0];\\ end\\ end else begin\\ src``_dly_chain <= src``_dly_chain;\\ end\\ end\\ assign dst = src``_dly_chain[(delay)*(width)-1:((delay)-1)*(width)]; // TVM generate clock signal `define TVM_DEFINE_TEST_SIGNAL(clk, rst)\\ parameter PER = 10;\\ reg clk;\\ reg rst;\\ always begin\\ #(PER/2) clk =~ clk;\\ end // Control logic on buffer/RAM read valid. // This delays the valid signal by one cycle and retain it when write_ready == 0 `define BUFFER_READ_VALID_DELAY(dst, data_valid, write_ready)\\ reg dst;\\ always@(posedge clk) begin\\ if(rst) begin\\ dst <= 0;\\ end else if (write_ready) begin\\ dst <= (data_valid);\\ end else begin\\ dst <= dst;\\ end\\ end\\ // A cache register that add one cycle lag to the ready signal // This allows the signal to flow more smoothly `define CACHE_REG(width, in_data, in_valid, in_ready, out_data, out_valid, out_ready)\\ reg [width-1:0] out_data``_state_;\\ reg [width-1:0] out_data``_overflow_;\\ reg out_valid``_state_;\\ reg out_valid``_overflow_;\\ always@(posedge clk) begin\\ if(rst) begin\\ out_valid``_overflow_ <= 0;\\ out_valid``_state_ <= 0;\\ end else if (out_valid``_overflow_) begin\\ if (out_ready) begin\\ out_valid``_state_ <= 1;\\ out_data``_state_ <= out_data``_overflow_;\\ out_valid``_overflow_ <= 0;\\ out_data``_overflow_ <= 0;\\ end else begin\\ out_valid``_state_ <= 1;\\ out_data``_state_ <= out_data``_state_;\\ out_valid``_overflow_ <= out_valid``_overflow_;\\ out_data``_overflow_ <= out_data``_overflow_;\\ end\\ end else begin\\ if (!out_ready && out_valid``_state_) begin\\ out_valid``_state_ <= 1;\\ out_data``_state_ <= out_data``_state_;\\ out_valid``_overflow_ <= in_valid;\\ out_data``_overflow_ <= in_data;\\ end else begin\\ out_valid``_state_ <= in_valid;\\ out_data``_state_ <= in_data;\\ out_valid``_overflow_ <= out_valid``_overflow_;\\ out_data``_overflow_ <= out_data``_overflow_;\\ end\\ end\\ end\\ // always@ (posedge clk) assign in_ready = !out_valid``_overflow_;\\ assign out_data = out_data``_state_;\\ assign out_valid = out_valid``_state_;
// a counter that counts up // Use as example of testcaase module counter(clk, rst, out); input clk; input rst; output [3:0] out; reg [3:0] counter; assign out = counter; always @(posedge clk) begin if (rst) begin counter <= 0; end else begin counter <= counter +1; end end endmodule
module main(); parameter PER = 10; parameter DATA_WIDTH = 8; parameter ADDR_WIDTH = 8; reg clk; reg rst; // read channels reg [ADDR_WIDTH-1:0] read_addr; wire [DATA_WIDTH-1:0] read_data; // write channels reg [ADDR_WIDTH-1:0] write_addr; reg [DATA_WIDTH-1:0] write_data; reg write_en; // mmap base reg [31:0] mmap_addr; always begin #(PER/2) clk =~ clk; end tvm_vpi_read_mmap # ( .DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH) ) rmmap ( .clk(clk), .rst(rst), .addr(read_addr), .data_out(read_data), .mmap_addr(mmap_addr) ); tvm_vpi_write_mmap # ( .DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH) ) wmmap ( .clk(clk), .rst(rst), .addr(write_addr), .data_in(write_data), .en(write_en), .mmap_addr(mmap_addr) ); initial begin $tvm_session(clk, rmmap, wmmap); end endmodule
module main(); // Parameters parameter PER=10; // In this example we perform a 3x3 convolution of an 8x8 input image // Therefore the window size here is (3-1)*8+3 = 19 parameter IMAGE_WIDTH = 8; parameter KERNEL_WIDTH = 3; // Line buffer parameters parameter DATA_WIDTH = 8; parameter DEPTH = 20; // (3-1)*8+3+1 parameter CNTR_WIDTH = 5; // floor(log(20)) + 1 parameter RD_WINDOW = 19; // (3-1)*8+3 parameter RD_ADVANCE = 1; parameter RD_ADDR_WIDTH = 5; // floor(log(19)) + 1 parameter WR_WINDOW = 1; parameter WR_ADVANCE = 1; parameter WR_ADDR_WIDTH = 1; // Clock & reset reg clk; reg rst; // Read port inputs reg read_advance; reg [RD_ADDR_WIDTH-1:0] read_addr; reg read_ready; // Write port outputs reg write_advance; reg [DATA_WIDTH-1:0] write_data; reg write_valid; // Outputs wire [DATA_WIDTH-1:0] read_data; wire read_valid; wire write_ready; wire [CNTR_WIDTH-1:0] status_counter; // Module instantiation tvm_buffer #( .DATA_WIDTH(DATA_WIDTH), .DEPTH(DEPTH), .CNTR_WIDTH(CNTR_WIDTH), .RD_WINDOW(RD_WINDOW), .RD_ADVANCE(RD_ADVANCE), .RD_ADDR_WIDTH(RD_ADDR_WIDTH), .WR_WINDOW(WR_WINDOW), .WR_ADVANCE(WR_ADVANCE), .WR_ADDR_WIDTH(WR_ADDR_WIDTH) ) uut ( .clk(clk), .rst(rst), .read_advance(read_advance), .read_data(read_data), .read_addr(read_addr), .read_ready(read_ready), .read_valid(read_valid), .write_advance(write_advance), .write_data(write_data), .write_addr({WR_ADDR_WIDTH{1'b0}}), .write_ready(write_ready), .write_valid(write_valid), .status_counter(status_counter) ); // clock generation always begin #(PER/2) clk =~ clk; end // read logic localparam KERNEL_SIZE = KERNEL_WIDTH*KERNEL_WIDTH; reg [3:0] read_counter; always @(posedge clk) begin if (rst) begin read_counter <= KERNEL_SIZE-1; read_advance <= 0; read_addr <= -1; read_ready <= 0; end else begin if (read_valid) begin read_counter <= (read_counter+1)%KERNEL_SIZE; read_ready <= 1; // Only advance at the last inner loop iteration if (read_counter==KERNEL_SIZE-2) begin read_advance <= 1; end else begin read_advance <= 0; end // Read address should describe a loop if (read_counter==KERNEL_SIZE-1) begin read_addr <= 0; end else if (read_counter%KERNEL_WIDTH==KERNEL_WIDTH-1) begin read_addr <= read_addr+IMAGE_WIDTH-KERNEL_WIDTH+1; end else begin read_addr <= read_addr+1; end end else begin read_counter <= read_counter; read_advance <= 0; read_addr <= read_addr; read_ready <= 0; end end end // read_data_valid logic reg read_data_valid; always @(posedge clk) begin if (rst) read_data_valid <= 0; else read_data_valid <= read_ready; end initial begin // This will allow tvm session to be called every cycle. $tvm_session(clk); end endmodule
// Buffer used to add intermediate data buffering in channels // // Data within the read/write window is directly accessible via rd_addr/wr_addr. // The read_advance/write_advance signals update the read/write data pointers by adding RD_WINDOW/WR_WINDOW. // The status_counter indicate how many items are currently in the buffer (only registered after an advance signal is asserted). // The ready/valid signals are used to implement a handshake protocol. // // Usage: create and pass instance to additional arguments of $tvm_session. module tvm_buffer #( parameter DATA_WIDTH = 256, parameter DEPTH = 1024, parameter CNTR_WIDTH = 10, // log base 2 of BUFF_DEPTH parameter RD_WINDOW = 8, // set to 1 for FIFO behavior, or DEPTH for SRAM behavior parameter RD_ADVANCE = 2, // window advance (set to 1 for FIFO behavior) parameter RD_ADDR_WIDTH = 3, // log base 2 of RD_WINDOW parameter WR_WINDOW = 8, // set to 1 for FIFO behavior, or DEPTH for SRAM behavior parameter WR_ADVANCE = 2, // window advance (set to 1 for FIFO behavior) parameter WR_ADDR_WIDTH = 3 // log base 2 of WR_WINDOW ) ( input clk, input rst, // Read ports input read_advance, // Window advance (read pointer) input [RD_ADDR_WIDTH-1:0] read_addr, // Read address offset input read_ready, // Read ready (dequeue) output read_valid, // Read valid (not empty) output [DATA_WIDTH-1:0] read_data, // Read data port // Write ports input write_advance, // Window advance (write pointer) input [WR_ADDR_WIDTH-1:0] write_addr, // Write address offset output write_ready, // Write ready (not full) input write_valid, // Write valid (enqueue) input [DATA_WIDTH-1:0] write_data, // Write data port // Other outputs output [CNTR_WIDTH-1:0] status_counter // Number of elements currently in FIFO ); // Outputs that need to be latched reg read_data; reg status_counter; // Internal registers (read pointer, write pointer) reg[CNTR_WIDTH-1:0] read_ptr; reg[CNTR_WIDTH-1:0] write_ptr; // RAM instance reg [DATA_WIDTH-1:0] ram[DEPTH-1:0]; // Empty and full logic assign read_valid = (status_counter>=RD_WINDOW) ? 1'b1 : 1'b0; assign write_ready = (status_counter<(DEPTH-WR_WINDOW)) ? 1'b1 : 1'b0; // Counter logic (only affected by enq and deq) always @(posedge clk) begin // Case 1: system reset if (rst==1'b1) begin status_counter <= 0; // Case 2: simultaneous write advance and read advance and deq end else if ((write_advance && write_ready) && (read_advance && read_valid)) begin status_counter <= status_counter + (WR_ADVANCE - RD_ADVANCE); // Case 3: write advance end else if (write_advance && write_ready) begin status_counter <= status_counter + WR_ADVANCE; // Case 4: deq end else if (read_advance && read_valid) begin status_counter <= status_counter - RD_ADVANCE; // Default end else begin status_counter <= status_counter; end end // Output logic always @(posedge clk) begin if (rst==1'b1) begin read_data <= 0; end else begin if(read_ready) begin read_data <= ram[(read_ptr+read_addr)%DEPTH]; end else begin read_data <= read_data; end end end // RAM writing logic always @(posedge clk) begin if(write_valid) begin ram[((write_ptr+write_addr)%DEPTH)] <= write_data; end end // Read and write pointer logic always@(posedge clk) begin if (rst==1'b1) begin write_ptr <= 0; read_ptr <= 0; end else begin // Increment write pointer by WR_ADVANCE when asserting write_advance // When performing a write, no need to update the write pointer if (write_advance && write_ready) begin write_ptr <= (write_ptr + WR_ADVANCE) % DEPTH; end else begin write_ptr <= write_ptr; end // Increment read pointer by RD_ADVANCE when asserting read_advance // When performing a read, no need to update the read pointer if(read_advance && read_valid) begin read_ptr <= (read_ptr + RD_ADVANCE) % DEPTH; end else begin read_ptr <= read_ptr; end end end endmodule // tvm_buffer
module main(); // Parameters parameter PER=10; // Double buffer parameters parameter DATA_WIDTH = 8; parameter DEPTH = 32; parameter CNTR_WIDTH = 6; // floor(log(32)) + 1 parameter RD_WINDOW = 16; parameter RD_ADVANCE = 16; parameter RD_ADDR_WIDTH = 5; // floor(log(16)) + 1 parameter WR_WINDOW = 16; parameter WR_ADVANCE = 16; parameter WR_ADDR_WIDTH = 5; // floor(log(16)) + 1 // Clock & reset reg clk; reg rst; // Read port inputs reg read_advance; reg [RD_ADDR_WIDTH-1:0] read_addr; reg read_ready; // Write port outputs reg write_advance; reg [DATA_WIDTH-1:0] write_data; reg [WR_ADDR_WIDTH-1:0] write_addr; reg write_valid; // Outputs wire [DATA_WIDTH-1:0] read_data; wire read_valid; wire write_ready; wire [CNTR_WIDTH-1:0] status_counter; // Module instantiation tvm_buffer #( .DATA_WIDTH(DATA_WIDTH), .DEPTH(DEPTH), .CNTR_WIDTH(CNTR_WIDTH), .RD_WINDOW(RD_WINDOW), .RD_ADVANCE(RD_ADVANCE), .RD_ADDR_WIDTH(RD_ADDR_WIDTH), .WR_WINDOW(WR_WINDOW), .WR_ADVANCE(WR_ADVANCE), .WR_ADDR_WIDTH(WR_ADDR_WIDTH) ) uut ( .clk(clk), .rst(rst), .read_advance(read_advance), .read_data(read_data), .read_addr(read_addr), .read_ready(read_ready), .read_valid(read_valid), .write_advance(write_advance), .write_data(write_data), .write_addr(write_addr), .write_ready(write_ready), .write_valid(write_valid), .status_counter(status_counter) ); // clock generation always begin #(PER/2) clk =~ clk; end // read logic always @(posedge clk) begin if (rst) begin read_advance <= 0; read_addr <= 0; read_ready <= 0; end else begin if (read_valid) begin read_ready <= 1; end else begin read_ready <= 0; end if (read_addr%RD_WINDOW==RD_WINDOW-2) begin read_advance <= 1; end else begin read_advance <= 0; end if (read_ready) begin read_addr <= (read_addr+1) % WR_WINDOW; end else begin read_addr <= read_addr % WR_WINDOW; end end end // read_data_valid logic reg read_data_valid; always @(posedge clk) begin if (rst) read_data_valid <= 0; else read_data_valid <= read_ready; end initial begin // This will allow tvm session to be called every cycle. $tvm_session(clk); end endmodule
// TVM mmap maps virtual DRAM into interface of SRAM. // This allows create testcases that directly access DRAM. // Read only memory map, one cycle read. // Usage: create and pass instance to additional arguments of $tvm_session. module tvm_vpi_read_mmap #( parameter DATA_WIDTH = 8, parameter ADDR_WIDTH = 8, parameter BASE_ADDR_WIDTH = 32 ) ( input clk, input rst, // Read Ports input [ADDR_WIDTH-1:0] addr, // Local offset in terms of number of units output [DATA_WIDTH-1:0] data_out, // The data port for read // Configure port input [BASE_ADDR_WIDTH-1:0] mmap_addr // The base address of memory map. ); reg [DATA_WIDTH-1:0] reg_data; assign data_out = reg_data; endmodule // Write only memory map, one cycle write. // Usage: create and pass instance to additional arguments of $tvm_session. module tvm_vpi_write_mmap #( parameter DATA_WIDTH = 8, parameter ADDR_WIDTH = 8, parameter BASE_ADDR_WIDTH = 32 ) ( input clk, input rst, // Write Ports input [ADDR_WIDTH-1:0] addr, // Local offset in terms of number of units input [DATA_WIDTH-1:0] data_in, // The data port for write input en, // The enable port for write // Configure port input [BASE_ADDR_WIDTH-1:0] mmap_addr // The base address of memap ); endmodule
`include "tvm_marcos.v" module main(); `TVM_DEFINE_TEST_SIGNAL(clk, rst) reg[31:0] in_data; wire[31:0] out_data; wire in_ready; reg in_valid; reg out_ready; wire out_valid; `CACHE_REG(32, in_data, in_valid, in_ready, out_data, out_valid, out_ready) initial begin // This will allow tvm session to be called every cycle. $tvm_session(clk); end endmodule
`include "tvm_marcos.v" module main(); `TVM_DEFINE_TEST_SIGNAL(clk, rst) reg ready; wire lp_ready; `NONSTOP_LOOP(iter0, 4, 0, lp_ready, iter0_finish, 0, 4) `NONSTOP_LOOP(iter1, 4, 0, iter0_finish, iter1_finish, 0, 3) `WRAP_LOOP_ONCE(0, valid, ready, iter1_finish, loop_ready) assign lp_ready = loop_ready; initial begin // This will allow tvm session to be called every cycle. $tvm_session(clk); end endmodule
module main(); // Parameters parameter PER=10; // FIFO parameters parameter DATA_WIDTH = 8; parameter DEPTH = 32; parameter CNTR_WIDTH = 6; // floor(log(32)) + 1 parameter RD_WINDOW = 1; parameter RD_ADVANCE = 1; parameter RD_ADDR_WIDTH = 1; parameter WR_WINDOW = 1; parameter WR_ADVANCE = 1; parameter WR_ADDR_WIDTH = 1; // Clock & reset reg clk; reg rst; // Module inputs reg [DATA_WIDTH-1:0] write_data; // FIFO interface abstraction: // Connect deq to read_advance and read_ready // Connect enq to write_advance and write_valid // Set read_addr and write_addr to 0 reg deq; reg enq; // Module outputs wire [DATA_WIDTH-1:0] read_data; wire read_valid; wire write_ready; wire [CNTR_WIDTH-1:0] status_counter; // Module instantiation tvm_buffer #( .DATA_WIDTH(DATA_WIDTH), .DEPTH(DEPTH), .CNTR_WIDTH(CNTR_WIDTH), .RD_WINDOW(RD_WINDOW), .RD_ADVANCE(RD_ADVANCE), .RD_ADDR_WIDTH(RD_ADDR_WIDTH), .WR_WINDOW(WR_WINDOW), .WR_ADVANCE(WR_ADVANCE), .WR_ADDR_WIDTH(WR_ADDR_WIDTH) ) uut ( .clk(clk), .rst(rst), .read_advance(deq), .read_addr({RD_ADDR_WIDTH{1'b0}}), .read_ready(deq), .read_valid(read_valid), .read_data(read_data), .write_advance(enq), .write_addr({WR_ADDR_WIDTH{1'b0}}), .write_ready(write_ready), .write_valid(enq), .write_data(write_data), .status_counter(status_counter) ); // clock generation always begin #(PER/2) clk =~ clk; end // fifo read logic always @(posedge clk) begin if (rst) deq <= 0; else deq <= read_valid; end // read_data_valid logic reg read_data_valid; always @(posedge clk) begin if (rst) read_data_valid <= 0; else read_data_valid <= deq; end initial begin // This will allow tvm session to be called every cycle. $tvm_session(clk); end endmodule
// Memory controller to access TVM VPI simulated RAM. // // You only see the wires and registers but no logics here. // The real computation is implemented via TVM VPI // // Usage: create and pass instance to additional arguments of $tvm_session. // Then it will be automatically hook up the RAM logic. // module tvm_vpi_mem_interface #( parameter READ_WIDTH = 8, parameter WRITE_WIDTH = 8, parameter ADDR_WIDTH = 32, parameter SIZE_WIDTH = 32 ) ( input clk, input rst, // Read Ports input read_en, // Read buffer enable output [READ_WIDTH-1:0] read_data_out, // The data port for read output read_data_valid, // Read is valid. // Write ports input write_en, // Write buffer enable input [WRITE_WIDTH-1:0] write_data_in, // Input data to write. output write_data_ready, // There are still pending write // Status port // Control signal ports to issue tasks input host_read_req, // Read request input [ADDR_WIDTH-1:0] host_read_addr, // The address to issue a read task input [SIZE_WIDTH-1:0] host_read_size, // The size of a read input host_write_req, // Write request. input [ADDR_WIDTH-1:0] host_write_addr, // The write address input [SIZE_WIDTH-1:0] host_write_size // The write size ); reg [READ_WIDTH-1:0] reg_read_data; reg reg_read_valid; reg reg_write_ready; // The wires up. assign read_data_out = reg_read_data; assign read_data_valid = reg_read_valid; assign write_data_ready = reg_write_ready; endmodule
varying vec3 N; varying vec3 v; varying vec2 tex; attribute vec3 vertexPos; attribute vec3 vertexNormal; attribute vec2 vertexUV; attribute vec2 boneWeight; attribute float boneID; uniform mat4 boneMatrix[10]; void main(void) { N = normalize(gl_NormalMatrix * vertexNormal); vec4 newVertex; newVertex = ((boneMatrix[0] * vec4(vertexPos.xyz, 1.0)) * boneWeight.x); newVertex += ((boneMatrix[int(boneID)] * vec4(vertexPos.xyz, 1.0)) * boneWeight.y); v = vec3(gl_ModelViewMatrix * newVertex); gl_Position = (gl_ModelViewProjectionMatrix * vec4(newVertex.xyz, 1.0)); tex = vertexUV; }
/***************************************************************************** * * * Module: Altera_UP_RS232_Counters * * Description: * * This module reads and writes data to the RS232 connector on Altera's * * DE1 and DE2 Development and Education Boards. * * * *****************************************************************************/ module Altera_UP_RS232_Counters ( \t// Inputs \tclk, \treset, \t \treset_counters, \t// Bidirectionals \t// Outputs \tbaud_clock_rising_edge, \tbaud_clock_falling_edge, \tall_bits_transmitted ); /***************************************************************************** * Parameter Declarations * *****************************************************************************/ parameter BAUD_COUNTER_WIDTH\t= 9; parameter BAUD_TICK_INCREMENT\t= 9'd1; parameter BAUD_TICK_COUNT\t\t= 9'd433; parameter HALF_BAUD_TICK_COUNT\t= 9'd216; parameter TOTAL_DATA_WIDTH\t\t= 11; /***************************************************************************** * Port Declarations * *****************************************************************************/ // Inputs input\t\t\t\tclk; input\t\t\t\treset; input\t\t\t\treset_counters; // Bidirectionals // Outputs output\treg\t\t\tbaud_clock_rising_edge; output\treg\t\t\tbaud_clock_falling_edge; output\treg\t\t\tall_bits_transmitted; /***************************************************************************** * Internal wires and registers Declarations * *****************************************************************************/ // Internal Wires // Internal Registers reg\t\t\t[(BAUD_COUNTER_WIDTH - 1):0]\tbaud_counter; reg\t\t\t[3:0]\tbit_counter; // State Machine Registers /***************************************************************************** * Finite State Machine(s) * *****************************************************************************/ /***************************************************************************** * Sequential logic * *****************************************************************************/ always @(posedge clk) begin \tif (reset == 1'b1) \t\tbaud_counter <= {BAUD_COUNTER_WIDTH{1'b0}}; \telse if (reset_counters) \t\tbaud_counter <= {BAUD_COUNTER_WIDTH{1'b0}}; \telse if (baud_counter == BAUD_TICK_COUNT) \t\tbaud_counter <= {BAUD_COUNTER_WIDTH{1'b0}}; \telse \t\tbaud_counter <= baud_counter + BAUD_TICK_INCREMENT; end always @(posedge clk) begin \tif (reset == 1'b1) \t\tbaud_clock_rising_edge <= 1'b0; \telse if (baud_counter == BAUD_TICK_COUNT) \t\tbaud_clock_rising_edge <= 1'b1; \telse \t\tbaud_clock_rising_edge <= 1'b0; end always @(posedge clk) begin \tif (reset == 1'b1) \t\tbaud_clock_falling_edge <= 1'b0; \telse if (baud_counter == HALF_BAUD_TICK_COUNT) \t\tbaud_clock_falling_edge <= 1'b1; \telse \t\tbaud_clock_falling_edge <= 1'b0; end always @(posedge clk) begin \tif (reset == 1'b1) \t\tbit_counter <= 4'h0; \telse if (reset_counters) \t\tbit_counter <= 4'h0; \telse if (bit_counter == TOTAL_DATA_WIDTH) \t\tbit_counter <= 4'h0; \telse if (baud_counter == BAUD_TICK_COUNT) \t\tbit_counter <= bit_counter + 4'h1; end always @(posedge clk) begin \tif (reset == 1'b1) \t\tall_bits_transmitted <= 1'b0; \telse if (bit_counter == TOTAL_DATA_WIDTH) \t\tall_bits_transmitted <= 1'b1; \telse \t\tall_bits_transmitted <= 1'b0; end /***************************************************************************** * Combinational logic * *****************************************************************************/ /***************************************************************************** * Internal Modules * *****************************************************************************/ endmodule
/***************************************************************************** * * * Module: Altera_UP_RS232_In_Deserializer * * Description: * * This module reads data to the RS232 UART Port. * * * *****************************************************************************/ module Altera_UP_RS232_In_Deserializer ( \t// Inputs \tclk, \treset, \t \tserial_data_in, \treceive_data_en, \t// Bidirectionals \t// Outputs \tfifo_read_available, \treceived_data ); /***************************************************************************** * Parameter Declarations * *****************************************************************************/ parameter BAUD_COUNTER_WIDTH\t= 9; parameter BAUD_TICK_INCREMENT\t= 9'd1; parameter BAUD_TICK_COUNT\t\t= 9'd433; parameter HALF_BAUD_TICK_COUNT\t= 9'd216; parameter TOTAL_DATA_WIDTH\t\t= 11; parameter DATA_WIDTH\t\t\t= 9; /***************************************************************************** * Port Declarations * *****************************************************************************/ // Inputs input\t\t\t\tclk; input\t\t\t\treset; input\t\t\t\tserial_data_in; input\t\t\t\treceive_data_en; // Bidirectionals // Outputs output\treg\t[7:0]\tfifo_read_available; output\t\t[(DATA_WIDTH - 1):0]\treceived_data; /***************************************************************************** * Internal wires and registers Declarations * *****************************************************************************/ // Internal Wires wire\t\t\t\tshift_data_reg_en; wire\t\t\t\tall_bits_received; wire\t\t\t\tfifo_is_empty; wire\t\t\t\tfifo_is_full; wire\t\t[6:0]\tfifo_used; // Internal Registers reg\t\t\t\t\treceiving_data; reg\t\t\t[(TOTAL_DATA_WIDTH - 1):0]\tdata_in_shift_reg; // State Machine Registers /***************************************************************************** * Finite State Machine(s) * *****************************************************************************/ /***************************************************************************** * Sequential logic * *****************************************************************************/ always @(posedge clk) begin \tif (reset == 1'b1) \t\tfifo_read_available <= 8'h00; \telse \t\tfifo_read_available <= {fifo_is_full, fifo_used}; end always @(posedge clk) begin \tif (reset == 1'b1) \t\treceiving_data <= 1'b0; \telse if (all_bits_received == 1'b1) \t\treceiving_data <= 1'b0; \telse if (serial_data_in == 1'b0) \t\treceiving_data <= 1'b1; end always @(posedge clk) begin \tif (reset == 1'b1) \t\tdata_in_shift_reg\t<= {TOTAL_DATA_WIDTH{1'b0}}; \telse if (shift_data_reg_en) \t\tdata_in_shift_reg\t<= \t\t\t{serial_data_in, data_in_shift_reg[(TOTAL_DATA_WIDTH - 1):1]}; end /***************************************************************************** * Combinational logic * *****************************************************************************/ /***************************************************************************** * Internal Modules * *****************************************************************************/ Altera_UP_RS232_Counters RS232_In_Counters ( \t// Inputs \t.clk\t\t\t\t\t\t(clk), \t.reset\t\t\t\t\t\t(reset), \t \t.reset_counters\t\t\t\t(~receiving_data), \t// Bidirectionals \t// Outputs \t.baud_clock_rising_edge\t\t(), \t.baud_clock_falling_edge\t(shift_data_reg_en), \t.all_bits_transmitted\t\t(all_bits_received) ); defparam \tRS232_In_Counters.BAUD_COUNTER_WIDTH\t= BAUD_COUNTER_WIDTH, \tRS232_In_Counters.BAUD_TICK_INCREMENT\t= BAUD_TICK_INCREMENT, \tRS232_In_Counters.BAUD_TICK_COUNT\t\t= BAUD_TICK_COUNT, \tRS232_In_Counters.HALF_BAUD_TICK_COUNT\t= HALF_BAUD_TICK_COUNT, \tRS232_In_Counters.TOTAL_DATA_WIDTH\t\t= TOTAL_DATA_WIDTH; Altera_UP_SYNC_FIFO RS232_In_FIFO ( \t// Inputs \t.clk\t\t\t(clk), \t.reset\t\t\t(reset), \t.write_en\t\t(all_bits_received & ~fifo_is_full), \t.write_data\t\t(data_in_shift_reg[(DATA_WIDTH + 1):1]), \t.read_en\t\t(receive_data_en & ~fifo_is_empty), \t \t// Bidirectionals \t// Outputs \t.fifo_is_empty\t(fifo_is_empty), \t.fifo_is_full\t(fifo_is_full), \t.words_used\t\t(fifo_used), \t.read_data\t\t(received_data) ); defparam \tRS232_In_FIFO.DATA_WIDTH\t= DATA_WIDTH, \tRS232_In_FIFO.DATA_DEPTH\t= 128, \tRS232_In_FIFO.ADDR_WIDTH\t= 7; endmodule
/***************************************************************************** * * * Module: Altera_UP_SYNC_FIFO * * Description: * * This module is a FIFO with same clock for both reads and writes. * * * *****************************************************************************/ module Altera_UP_SYNC_FIFO ( \t// Inputs \tclk, \treset, \twrite_en, \twrite_data, \tread_en, \t \t// Bidirectionals \t// Outputs \tfifo_is_empty, \tfifo_is_full, \twords_used, \tread_data ); /***************************************************************************** * Parameter Declarations * *****************************************************************************/ parameter\tDATA_WIDTH\t= 32; parameter\tDATA_DEPTH\t= 128; parameter\tADDR_WIDTH\t= 7; /***************************************************************************** * Port Declarations * *****************************************************************************/ // Inputs input\t\t\t\tclk; input\t\t\t\treset; input\t\t\t\twrite_en; input\t\t[DATA_WIDTH:1]\twrite_data; input\t\t\t\tread_en; // Bidirectionals // Outputs output\t\t\t\tfifo_is_empty; output\t\t\t\tfifo_is_full; output\t\t[ADDR_WIDTH:1]\twords_used; output\t\t[DATA_WIDTH:1]\tread_data; /***************************************************************************** * Internal wires and registers Declarations * *****************************************************************************/ // Internal Wires // Internal Registers // State Machine Registers /***************************************************************************** * Finite State Machine(s) * *****************************************************************************/ /***************************************************************************** * Sequential logic * *****************************************************************************/ /***************************************************************************** * Combinational logic * *****************************************************************************/ /***************************************************************************** * Internal Modules * *****************************************************************************/ scfifo\tSync_FIFO ( \t// Inputs \t.clock\t\t\t(clk), \t.sclr\t\t\t(reset), \t.data\t\t\t(write_data), \t.wrreq\t\t\t(write_en), \t.rdreq\t\t\t(read_en), \t// Bidirectionals \t// Outputs \t.empty\t\t\t(fifo_is_empty), \t.full\t\t\t(fifo_is_full), \t.usedw\t\t\t(words_used), \t \t.q\t\t\t\t(read_data) \t// Unused \t// synopsys translate_off \t, \t.aclr\t\t\t(), \t.almost_empty\t(), \t.almost_full\t() \t// synopsys translate_on ); defparam \tSync_FIFO.add_ram_output_register\t= "OFF", \tSync_FIFO.intended_device_family\t= "Cyclone IV E", \tSync_FIFO.lpm_numwords\t\t\t\t= DATA_DEPTH, \tSync_FIFO.lpm_showahead\t\t\t\t= "ON", \tSync_FIFO.lpm_type\t\t\t\t\t= "scfifo", \tSync_FIFO.lpm_width\t\t\t\t\t= DATA_WIDTH, \tSync_FIFO.lpm_widthu\t\t\t\t= ADDR_WIDTH, \tSync_FIFO.overflow_checking\t\t\t= "OFF", \tSync_FIFO.underflow_checking\t\t= "OFF", \tSync_FIFO.use_eab\t\t\t\t\t= "ON"; endmodule
/***************************************************************************** * * * Module: Altera_UP_RS232_Out_Serializer * * Description: * * This module writes data to the RS232 UART Port. * * * *****************************************************************************/ module Altera_UP_RS232_Out_Serializer ( \t// Inputs \tclk, \treset, \t \ttransmit_data, \ttransmit_data_en, \t// Bidirectionals \t// Outputs \tfifo_write_space, \tserial_data_out ); /***************************************************************************** * Parameter Declarations * *****************************************************************************/ parameter BAUD_COUNTER_WIDTH\t= 9; parameter BAUD_TICK_INCREMENT\t= 9'd1; parameter BAUD_TICK_COUNT\t\t= 9'd433; parameter HALF_BAUD_TICK_COUNT\t= 9'd216; parameter TOTAL_DATA_WIDTH\t\t= 11; parameter DATA_WIDTH\t\t\t= 9; /***************************************************************************** * Port Declarations * *****************************************************************************/ // Inputs input\t\t\t\tclk; input\t\t\t\treset; input\t\t[DATA_WIDTH:1]\ttransmit_data; input\t\t\t\ttransmit_data_en; // Bidirectionals // Outputs output\treg\t[7:0]\tfifo_write_space; output\treg\t\t\tserial_data_out; /***************************************************************************** * Internal wires and registers Declarations * *****************************************************************************/ // Internal Wires wire\t\t\t\tshift_data_reg_en; wire\t\t\t\tall_bits_transmitted; wire\t\t\t\tread_fifo_en; wire\t\t\t\tfifo_is_empty; wire\t\t\t\tfifo_is_full; wire\t\t[6:0]\tfifo_used; wire\t\t[DATA_WIDTH:1]\tdata_from_fifo; // Internal Registers reg\t\t\t\t\ttransmitting_data; reg\t\t\t[DATA_WIDTH:0]\tdata_out_shift_reg; // State Machine Registers /***************************************************************************** * Finite State Machine(s) * *****************************************************************************/ /***************************************************************************** * Sequential logic * *****************************************************************************/ always @(posedge clk) begin \tif (reset == 1'b1) \t\tfifo_write_space <= 8'h00; \telse \t\tfifo_write_space <= 8'h80 - {fifo_is_full, fifo_used}; end always @(posedge clk) begin \tif (reset == 1'b1) \t\tserial_data_out <= 1'b1; \telse \t\tserial_data_out <= data_out_shift_reg[0]; end always @(posedge clk) begin \tif (reset == 1'b1) \t\ttransmitting_data <= 1'b0; \telse if (all_bits_transmitted == 1'b1) \t\ttransmitting_data <= 1'b0; \telse if (fifo_is_empty == 1'b0) \t\ttransmitting_data <= 1'b1; end always @(posedge clk) begin \tif (reset == 1'b1) \t\tdata_out_shift_reg\t<= {(DATA_WIDTH + 1){1'b1}}; \telse if (read_fifo_en) \t\tdata_out_shift_reg\t<= {data_from_fifo, 1'b0}; \telse if (shift_data_reg_en) \t\tdata_out_shift_reg\t<= \t\t\t{1'b1, data_out_shift_reg[DATA_WIDTH:1]}; end /***************************************************************************** * Combinational logic * *****************************************************************************/ assign read_fifo_en = \t\t\t~transmitting_data & ~fifo_is_empty & ~all_bits_transmitted; /***************************************************************************** * Internal Modules * *****************************************************************************/ Altera_UP_RS232_Counters RS232_Out_Counters ( \t// Inputs \t.clk\t\t\t\t\t\t(clk), \t.reset\t\t\t\t\t\t(reset), \t \t.reset_counters\t\t\t\t(~transmitting_data), \t// Bidirectionals \t// Outputs \t.baud_clock_rising_edge\t\t(shift_data_reg_en), \t.baud_clock_falling_edge\t(), \t.all_bits_transmitted\t\t(all_bits_transmitted) ); defparam \tRS232_Out_Counters.BAUD_COUNTER_WIDTH\t= BAUD_COUNTER_WIDTH, \tRS232_Out_Counters.BAUD_TICK_INCREMENT\t= BAUD_TICK_INCREMENT, \tRS232_Out_Counters.BAUD_TICK_COUNT\t\t= BAUD_TICK_COUNT, \tRS232_Out_Counters.HALF_BAUD_TICK_COUNT\t= HALF_BAUD_TICK_COUNT, \tRS232_Out_Counters.TOTAL_DATA_WIDTH\t\t= TOTAL_DATA_WIDTH; Altera_UP_SYNC_FIFO RS232_Out_FIFO ( \t// Inputs \t.clk\t\t\t(clk), \t.reset\t\t\t(reset), \t.write_en\t\t(transmit_data_en & ~fifo_is_full), \t.write_data\t\t(transmit_data), \t.read_en\t\t(read_fifo_en), \t \t// Bidirectionals \t// Outputs \t.fifo_is_empty\t(fifo_is_empty), \t.fifo_is_full\t(fifo_is_full), \t.words_used\t\t(fifo_used), \t.read_data\t\t(data_from_fifo) ); defparam \tRS232_Out_FIFO.DATA_WIDTH\t= DATA_WIDTH, \tRS232_Out_FIFO.DATA_DEPTH\t= 128, \tRS232_Out_FIFO.ADDR_WIDTH\t= 7; endmodule
`define FREQ_IN_KHZ 18 `define DUTY_CYCLE 85/100 `define PERIOD (50000 / `FREQ_IN_KHZ) `define DUTY_PERIOD (`PERIOD*`DUTY_CYCLE) module pwm(input CLOCK_50, input [0:0]SW, output [7:0]LED, output [7:0]GPIO_1); motor_controller mc0(CLOCK_50, 1'b1, SW[0], `PERIOD, `DUTY_PERIOD, LED[3:0]); motor_controller mc1(CLOCK_50, 1'b0, SW[0], `PERIOD, `DUTY_PERIOD, LED[7:4]); motor_controller mc2(CLOCK_50, 1'b1, SW[0], `PERIOD, `DUTY_PERIOD, {GPIO_1[7], GPIO_1[5], GPIO_1[3], GPIO_1[1]}); endmodule
// -------------------------------------------------------------------- // Copyright (c) 2011 by Terasic Technologies Inc. // -------------------------------------------------------------------- // // Permission: // // Terasic grants permission to use and modify this code for use // in synthesis for all Terasic Development Boards and Altera Development // Kits made by Terasic. Other use of this code, including the selling // ,duplication, or modification of any portion is strictly prohibited. // // Disclaimer: // // This VHDL/Verilog or C/C++ source code is intended as a design reference // which illustrates how these types of functions can be implemented. // It is the user's responsibility to verify their design for // consistency and functionality through the use of formal // verification methods. Terasic provides no warranty regarding the use // or functionality of this code. // // -------------------------------------------------------------------- // // Terasic Technologies Inc // E. Rd Sec. 1. JhuBei City, // HsinChu County, Taiwan // 302 // // web: http://www.terasic.com/ // email: [email protected] // // -------------------------------------------------------------------- module DE0_Nano( \t//////////// CLOCK ////////// \tCLOCK_50, \t//////////// LED ////////// \tLED, \t//////////// KEY ////////// \tKEY, \t//////////// SW ////////// \tSW, \t//////////// SDRAM ////////// \tDRAM_ADDR, \tDRAM_BA, \tDRAM_CAS_N, \tDRAM_CKE, \tDRAM_CLK, \tDRAM_CS_N, \tDRAM_DQ, \tDRAM_DQM, \tDRAM_RAS_N, \tDRAM_WE_N, \t \t//////////// ECPS ////////// \tEPCS_ASDO, \tEPCS_DATA0, \tEPCS_DCLK, \tEPCS_NCSO, \t//////////// Accelerometer and EEPROM ////////// \tG_SENSOR_CS_N, \tG_SENSOR_INT, \tI2C_SCLK, \tI2C_SDAT, \t//////////// ADC ////////// \tADC_CS_N, \tADC_SADDR, \tADC_SCLK, \tADC_SDAT, \t//////////// 2x13 GPIO Header ////////// \tGPIO_2, \tGPIO_2_IN, \t//////////// GPIO_0, GPIO_0 connect to GPIO Default ////////// \tGPIO_0, \tGPIO_0_IN, \t//////////// GPIO_1, GPIO_1 connect to GPIO Default ////////// \tGPIO_1, \tGPIO_1_IN ); //======================================================= // PARAMETER declarations //======================================================= //======================================================= // PORT declarations //======================================================= //////////// CLOCK ////////// input \t\t \t\tCLOCK_50; //////////// LED ////////// output\t\t [7:0]\t\tLED; //////////// KEY ////////// input \t\t [1:0]\t\tKEY; //////////// SW ////////// input \t\t [3:0]\t\tSW; //////////// SDRAM ////////// output\t\t [12:0]\t\tDRAM_ADDR; output\t\t [1:0]\t\tDRAM_BA; output\t\t \t\tDRAM_CAS_N; output\t\t \t\tDRAM_CKE; output\t\t \t\tDRAM_CLK; output\t\t \t\tDRAM_CS_N; inout \t\t [15:0]\t\tDRAM_DQ; output\t\t [1:0]\t\tDRAM_DQM; output\t\t \t\tDRAM_RAS_N; output\t\t \t\tDRAM_WE_N; //////////// EPCS ////////// output\t\t \t\tEPCS_ASDO; input \t\t \t\tEPCS_DATA0; output\t\t \t\tEPCS_DCLK; output\t\t \t\tEPCS_NCSO; //////////// Accelerometer and EEPROM ////////// output\t\t \t\tG_SENSOR_CS_N; input \t\t \t\tG_SENSOR_INT; output\t\t\t\t\t\t\tI2C_SCLK; inout \t\t \t\tI2C_SDAT; //////////// ADC ////////// output\t\t \t\tADC_CS_N; output\t\t \t\tADC_SADDR; output\t\t \t\tADC_SCLK; input \t\t \t\tADC_SDAT; //////////// 2x13 GPIO Header ////////// inout \t\t [12:0]\t\tGPIO_2; input \t\t [2:0]\t\tGPIO_2_IN; //////////// GPIO_0, GPIO_0 connect to GPIO Default ////////// inout \t\t [33:0]\t\tGPIO_0; input \t\t [1:0]\t\tGPIO_0_IN; //////////// GPIO_1, GPIO_1 connect to GPIO Default ////////// inout \t\t [33:0]\t\tGPIO_1; input \t\t [1:0]\t\tGPIO_1_IN; //======================================================= // REG/WIRE declarations //======================================================= wire reset_n; wire select_i2c_clk; wire i2c_clk; wire spi_clk; wire [32:0] gpio_0_wire; wire [33:0] gpio_1_wire; wire [12:0] gpio_2_wire; wire [3:0] led_wire; wire error, power; wire [2:0] voltage_mux; //======================================================= // Structural coding //======================================================= assign reset_n = 1'b1; assign GPIO_1[33] = power; assign {GPIO_1[29], GPIO_1[31], GPIO_1[25]} = voltage_mux; assign LED[3:0] = {2'b10, GPIO_0[33], gpio_2_wire[5]}; global_disable #( .NUM_IN(2+1), .NUM_IOS(34+13+4) ) dis_inst ( .clk(CLOCK_50), .shutdown(~{KEY, power}), .gpio_in({gpio_0_wire, gpio_2_wire, led_wire}), .gpio_out_default({{33{1'b0}}, {7{1'b0}}, {1'b1}, {5{1'b0}}, {4{1'b0}}}), // GPIO_2[5] defaults to 1 .gpio_out({GPIO_0[32:0], GPIO_2, LED[7:4]}) ); // assign IMU reset to low assign gpio_2_wire[9] = 1'b0; DE0_Nano_SOPC DE0_Nano_SOPC_inst( // global signals: .altpll_io(), .altpll_sdram(DRAM_CLK), .altpll_sys(), .clk_50(CLOCK_50), .reset_n(reset_n), \t\t\t // GPIO pins to Avalon slave(s) .GPIO_out_from_the_motor_controller_0({led_wire[3:0], gpio_2_wire[6], gpio_2_wire[8], gpio_0_wire[24], gpio_0_wire[25], gpio_0_wire[18], gpio_0_wire[19], gpio_0_wire[12], gpio_0_wire[13], gpio_0_wire[16], gpio_0_wire[17], gpio_0_wire[10], gpio_0_wire[11], gpio_2_wire[2], gpio_2_wire[4], gpio_0_wire[22], gpio_0_wire[23], gpio_0_wire[4], gpio_0_wire[5], gpio_0_wire[2], gpio_0_wire[0]}), // Clocks for the IMU .sys_clk_to_the_imu_controller_0(CLOCK_50), .ADC_CS_N_from_the_imu_controller_0(ADC_CS_N), .ADC_SADDR_from_the_imu_controller_0(ADC_SADDR), .ADC_SCLK_from_the_imu_controller_0(ADC_SCLK), .ADC_SDAT_to_the_imu_controller_0(ADC_SDAT), // RS232 Signals (add signals later) .UART_RXD_to_the_RS232_0(!power | GPIO_0[33]), // 1 if power is off .UART_TXD_from_the_RS232_0(gpio_2_wire[5]), // Power Management .data_to_the_power_management_slave_0(GPIO_1[27]), .mux_from_the_power_management_slave_0(voltage_mux), .kill_sw_from_the_power_management_slave_0(power), // the_select_i2c_clk .out_port_from_the_select_i2c_clk(select_i2c_clk), // the_altpll_0 .locked_from_the_altpll_0(), .phasedone_from_the_altpll_0(), // the_epcs .data0_to_the_epcs(EPCS_DATA0), .dclk_from_the_epcs(EPCS_DCLK), .sce_from_the_epcs(EPCS_NCSO), .sdo_from_the_epcs(EPCS_ASDO), // the_gsensor_spi .SPI_CS_n_from_the_gsensor_spi(G_SENSOR_CS_N), .SPI_SCLK_from_the_gsensor_spi(spi_clk), .SPI_SDIO_to_and_from_the_gsensor_spi(I2C_SDAT),\t // the_g_sensor_int .in_port_to_the_g_sensor_int(G_SENSOR_INT), // the_i2c_scl .out_port_from_the_i2c_scl(i2c_clk), // the_i2c_sda .bidir_port_to_and_from_the_i2c_sda(I2C_SDAT), // the_key .in_port_to_the_key(KEY), // the_sdram .zs_addr_from_the_sdram(DRAM_ADDR), .zs_ba_from_the_sdram(DRAM_BA), .zs_cas_n_from_the_sdram(DRAM_CAS_N), .zs_cke_from_the_sdram(DRAM_CKE), .zs_cs_n_from_the_sdram(DRAM_CS_N), .zs_dq_to_and_from_the_sdram(DRAM_DQ), .zs_dqm_from_the_sdram(DRAM_DQM), .zs_ras_n_from_the_sdram(DRAM_RAS_N), .zs_we_n_from_the_sdram(DRAM_WE_N), // the_sw .in_port_to_the_sw(SW) ); \t\t\t\t\t\t assign I2C_SCLK = (select_i2c_clk)?i2c_clk:spi_clk; endmodule