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2.1M
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`timescale 1ns/1ps
module top;
reg pass;
reg ina, inb;
wire out;
my_or dut(out, ina, inb);
initial begin
pass = 1\'b1;
ina = 1\'b0;
inb = 1\'b0;
#0.399
if (out !== 1\'bx && out !== 1\'bz) begin
$display("FAILED: gate had incorrect delay, expected x/z, got %b.", out);
pass = 1\'b0;
end
#0.002
if (out !== 1\'b0) begin
$display("FAILED: gate had incorrect delay, expected 0, got %b.", out);
pass = 1\'b0;
end
// Check inertial delays.
ina = 1\'b1;
#0.399
ina = 1\'b0;
#0.002
if (out !== 1\'b0) begin
$display("FAILED: inertial delay, expected 0, got %b.", out);
pass = 1\'b0;
end
// Check that this change is relative to the first edge.
ina = 1\'b1;
#0.200;
inb = 1\'b1;
#0.201;
if (out !== 1\'b1) begin
$display("FAILED: double edge delay, expected 1, got %b.", out);
pass = 1\'b0;
#0.200;
if (out === 1\'b1) begin
$display("FAILED: double edge delay was off second edge.");
end
end
if (pass) $display("PASSED");
end
endmodule
module my_or(out, ina, inb);
output out;
input ina, inb;
or(out, ina, inb);
specify
(ina, inb *> out) = 0.4;
endspecify
endmodule
|
module test;
task automatic foo(input int id);
#1000 $display("task %0d finished at time %0t", id, $time);
endtask
initial begin
$display("main thread started at time %0t", $time);
fork
#1 foo(1);
#2 foo(2);
join_none
#5;
$display("main thread continued at time %0t", $time);
fork
#1 foo(3);
#2 foo(4);
join_any
$display("main thread finished at time %0t", $time);
end
endmodule
|
// Copyright (c) 2015 CERN
// @author Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// \'wait on\' & \'wait until\' test
module vhdl_wait_test;
logic [1:0] a, b;
vhdl_wait dut(a, b);
always @(posedge b[0]) begin
$display("wait 1 acknowledged");
// complete "wait 2"
a[1] = 1\'b0;
end
always @(posedge b[1]) begin
$display("wait 2 acknowledged");
end
initial begin
// complete "wait 1"
a = 2\'b00;
end
endmodule
|
// Check that it is an error to declare a non-ANSI module port with implicit
// packed dimensions if it is later redeclared as an atom2 typed variable. Even
// if the size of the packed dimensions matches that of the size of the atom2
// type.
module test(x);
output [15:0] x;
shortint x;
initial begin
$display("FAILED");
end
endmodule
|
module main;
reg [7:0] mem [0:1];
initial begin
mem[0] = 8\'ha5;
mem[1] = 8\'hf0;
if (mem[0] !== 8\'ha5) begin
\t $display("FAILED");
\t $finish;
end
if (mem[1] !== 8\'hf0) begin
\t $display("FAILED");
\t $finish;
end
if (mem[0][4+:4] !== 5\'ha) begin
\t $display("FAILED");
\t $finish;
end
if (mem[1][4+:4] !== 5\'hf) begin
\t $display("FAILED");
\t $finish;
end
mem[0][4 +: 4] = 4\'hc;
#1 if (mem[0] !== 8\'hc5) begin
\t $display("FAILED");
\t $finish;
end
mem[1][4 +: 4] = 4\'h3;
#1 if (mem[1] !== 8\'h30) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
$finish;
end // initial begin
endmodule // main
|
module check (input unsigned [22:0] a, b, c);
wire [22:0] int_AB;
assign int_AB = a ^ b;
always @(a, b, int_AB, c) begin
#1;
if (int_AB != c) begin
$display("ERROR");
$finish;
end
end
endmodule
module stimulus (output reg unsigned [22:0] A, B);
parameter MAX = 1 << 23;
parameter S = 10000;
int unsigned i;
initial begin
A = 0; B= 0;
for (i=0; i<S; i=i+1) begin
#1 A = {$random} % MAX;
B = {$random} % MAX;
end
end
endmodule
module test;
wire unsigned [22:0] a, b;
wire unsigned [22:0] r;
stimulus stim (.A(a), .B(b));
xor23 duv (.a_i(a), .b_i(b), .c_o(r) );
check check (.a(a), .b(b), .c(r) );
initial begin
#20000;
$display("PASSED");
$finish;
end
endmodule
|
//
// Copyright (c) 2002 Stephen Williams (steve at icarus.com)
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
module main;
reg [3:0] val_drv = 4\'b0101;
wire [3:0] val = val_drv;
initial begin
#50 if (val !== val_drv) begin
\t $display("FAILED -- initial val %b !== %b", val, val_drv);
\t $finish;
end
force val = 4\'b1010;
#1 if (val !== 4\'b1010) begin
\t $display("FAILED -- force 1010 failed, val=%b", val);
\t $finish;
end
// Use force to "lift" the driver.
force val = 4\'bzzzz;
if (val !== 4\'bzzzz) begin
\t $display("FAILED -- force z failed, val=%b", val);
\t $finish;
end
release val;
#1 if (val !== 4\'b0101) begin
\t $display("FAILED -- unforced val = %b", val);
\t $finish;
end
val_drv = 4\'b1010;
#1 if (val !== 4\'b1010) begin
\t $display("FAILED -- val_drv=%b, val=%b", val_drv, val);
\t $finish;
end
$display("PASSED");
end
endmodule
|
//
// Verifies that the PRNG seed streams are unique, well trys anyway.
//
module test;
reg [31:0] rtn;
reg [31:0] pseed, seed1, seed2;
reg [31:0] mem1[3:0], mem2[3:0];
integer i;
initial begin
\tseed1 = 32\'hcafe_babe;
\tseed2 = 32\'hdead_beef;
\t// Isolated stream
\tfor (i = 0; i < 4; i = i + 1) begin
\t mem1[i] = $random(seed1);
\tend
\t// Pull from multiple streams
\tseed1 = 32\'hcafe_babe;
\tseed2 = 32\'hdead_beef;
\tfor (i = 0; i < 4; i = i + 1) begin
\t mem2[i] = $random(seed1);
\t // pull more values from other pools
\t rtn = $random(seed2);
\t rtn = $random;
\tend
\t// Verify the seed1 streams match
\tfor (i = 0; i < 4; i = i + 1) begin
\t if (mem1[i] != mem2[i]) begin
\t\t$display("FAILED %0d: %x != %x", i, mem1[i], mem2[i]);
\t\t$finish;
\t end
\tend
\t$display("PASSED");
\t$finish;
end
endmodule
|
`timescale 100ns/100ps
module dummy;
parameter [1:0] ipval = 2;
endmodule
`timescale 1us/1ns
module top;
parameter [1:0] ipval = 2;
parameter spval = "Help";
parameter rpval = 1.0;
event evt;
reg [1:0] rgval;
reg rgarr [2:0];
wire [1:0] wval;
wire warr [2:0];
integer ival;
real rval;
real rarr [2:0];
time tval;
initial begin:blk
$printtimescale(dummy);
$printtimescale(dummy.ipval);
// These should all print a timescale of 1us / 1ns.
$printtimescale;
$printtimescale(top.ipval);
/* This does not currently work because Icarus does not know how
* to keep the parameter reference in the part select. For now
* it just returns a constant which the runtime will complain
* does not have a vpiModule. */
// $printtimescale(top.ipval[0]);
$printtimescale(top.spval);
/* The same goes here. */
// $printtimescale(top.spval[0]);
$printtimescale(top.rpval);
$printtimescale(top.evt);
$printtimescale(top.rgval);
$printtimescale(top.rgval[0]);
$printtimescale(top.rgarr);
$printtimescale(top.rgarr[0]);
$printtimescale(top.wval);
$printtimescale(top.wval[0]);
$printtimescale(top.warr);
$printtimescale(top.warr[0]);
$printtimescale(top.ival);
$printtimescale(top.ival[1]);
$printtimescale(top.rval);
$printtimescale(top.rarr);
$printtimescale(top.rarr[0]);
$printtimescale(top.tval);
$printtimescale(top.blk);
$printtimescale(top.frk);
$printtimescale(top.tsk);
$printtimescale(top.fnc);
end
initial fork:frk
$write("");
join
task tsk;
begin
end
endtask
function integer fnc;
input integer tmp;
fnc = 2 * tmp;
endfunction
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always reg_lvalue = @ event_identifier constant
// D: There is a dependency here between this and event keyword and ->
module main ;
reg [3:0] value1 ;
event event_ident ;
initial
begin
# 5 -> event_ident ;
end
initial
begin
if(value1 !== 4\'bxxxx)
\t$display("FAILED - always reg_lvalue = @ event_identifier constant\
");
#10 ;
if(value1 != 4\'h5)
\t$display("FAILED - always reg_lvalue = @ event_identifier constant\
");
else
begin
$display("PASSED\
");
$finish ;
end
end
always value1 = repeat ( 5 ) @ event_ident 4\'h5 ;
endmodule
|
module test;
parameter PVALUE = 12;
localparam LVALUE = 88;
enum byte unsigned { UVAL[256] } unsignedbyte_enum;
enum byte { SVAL[100] } signedbyte_enum;
enum { ADD = 10, SUB[5], JMP[6:8]} E1; // page 28 LRM
enum { REGISTER[2] = 1, REGISTER[2:4] = 10 } vr; // page 28 LRM
enum { P[5] = PVALUE, Q, S[3] = LVALUE} par_enum;
enum reg [2:0] { state[8] } bin_enum;
enum integer {IDLE, XX=\'bx, XY=\'b01, YY=\'b10, XZ = 32\'h1x2z3xxz} next_state;
int i;
initial begin
// 1. Default anonymous enum data type should be int
// don\'t know yet how to quickly check this
//
// 1. Checking initialisations
//
// a. If the first name is not assigned it should be zero
if (UVAL0 !== 8\'h0 || SVAL0 !== 8\'h0)
begin
$display ("FAILED - First un-assigned element of enum type was not zero");
$finish;
end
// b. Checking initials E1 and vr
if (ADD != 10 || REGISTER0 != 1)
begin
$display ("FAILED - First initialised elements of enums E1 and vr were not elaborated properly");
$finish;
end
// A name without a value is automatically assigned and increment of the value of the
// previous name (Section 4.10 LRM)
// c. checking initial values for SUB (0-4) in E1
if (SUB0 != 11 || SUB1 != 12 || SUB2 != 13 || SUB3 != 14 || SUB4 != 15)
begin
$display ("FAILED - Initialised elements SUB (0-4) in enum E1 were not elaborated properly");
$finish;
end
// c. checking initial values for JMP (6-8) in E1
if (JMP6 != 16 || JMP7 != 17 || JMP8 != 18)
begin
$display ("FAILED - Initialised elements (6-8) JMP in enum E1 were not elaborated properly");
$finish;
end
// c. checking initial values in vr
if (REGISTER1 != 2 || REGISTER2 != 10 || REGISTER3 != 11 || REGISTER4 != 12)
begin
$display ("FAILED - Initialised elements REGISTER (1-4) in enum vr were not elaborated properly");
$finish;
end
// c. checking hand-picked values in unsignedbyte_enum
if (UVAL23 != 23 || UVAL91 != 91 || UVAL138 != 138 || UVAL207 != 207)
begin
$display ("FAILED - Initialised some UVAL in enum unsignedbyte_enum were not elaborated properly");
$display ("UVAL23 = %0d, UVAL91 = %0d, UVAL138 = %0d, UVAL207 = %0d", UVAL23, UVAL91, UVAL138, UVAL207);
$finish;
end
// c. checking hand-picked values in signedbyte_enum
if (SVAL7 != 7 || SVAL19 != 19 || SVAL87 != 87)
begin
$display ("FAILED - Initialised some SVAL in enum signedbyte_enum were not elaborated properly");
$display ("SVAL7 = %0d, SVAL19 = %0d, SVAL87 = %0d", SVAL7, UVAL91, SVAL19, SVAL87);
$finish;
end
// c. checking final values in unsignedbyte_enum and signedbyte_enum
if (UVAL255 != 255 || SVAL99 != 99)
begin
$display ("FAILED - Initialised final values UVAL and SVAL did not elaborate properly");
$display ("UVAL255 = %0d, SVAL99 = %0d", UVAL255, SVAL99);
$finish;
end
// d. checking xz values in next_state
if (XX !== \'bx || XZ !== 32\'h1x2z3xxz)
begin
$display ("FAILED - Initialised x,z values in next_state did not elaborate properly");
$finish;
end
// e. constants elaborated from parameter
if (P0 != PVALUE+0 || P1 != PVALUE+1 || P2 != PVALUE+2 || P3 != PVALUE+3 || P4 != PVALUE + 4 || Q != PVALUE+5)
begin
$display ("FAILED - Initialised values P in par_enum were not elaborated properly");
$finish;
end
// f. constants elaborated from localparam
if (S0 != LVALUE+0 || S1 != LVALUE+1 || S2 != LVALUE+2)
begin
$display ("FAILED - Initialised values S in par_enum were not elaborated properly");
$finish;
end
#1;
// g. checking num method
if (unsignedbyte_enum.num != 256 || signedbyte_enum.num != 100 ||
E1.num != 9 || vr.num != 5 || par_enum.num != 9 )
begin
$display ("FAILED - The num method does not report as expected");
$finish;
end
// h. checking first method
if (unsignedbyte_enum.first != 0 || signedbyte_enum.first != 0 ||
E1.first != 10 || vr.first != 1 || par_enum.first != PVALUE )
begin
$display ("FAILED - The first method does not report as expected");
$finish;
end
// i. checking last method
if (unsignedbyte_enum.last != 255 || signedbyte_enum.last != 99 ||
E1.last != 18 || vr.last != 12 || par_enum.last != LVALUE+2 )
begin
$display ("FAILED - The last method does not report as expected");
$finish;
end
// checking the next method on unsignedbyte_enum
unsignedbyte_enum = unsignedbyte_enum.first;
for (i=1; i<=255; i=i+1) begin
unsignedbyte_enum = unsignedbyte_enum.next;
if (unsignedbyte_enum != i) begin
$display ("FAILED - The next method does not report as expected for unsignedbyte_enum");
$finish;
end
end
unsignedbyte_enum = unsignedbyte_enum.next;
// checking wrap to the first element for signedbyte_enum
if (unsignedbyte_enum != unsignedbyte_enum.first) begin
$display ("FAILED - The next method did not wrap to the first element for unsignedbyte_enum");
$finish;
end
// checking the next method on signedbyte_enum
signedbyte_enum = signedbyte_enum.first;
for (i=1; i<100; i=i+1) begin
signedbyte_enum = signedbyte_enum.next;
if (signedbyte_enum != i) begin
$display ("FAILED - The next method does not report as expected for signedbyte_enum");
$finish;
end
end
signedbyte_enum = signedbyte_enum.next;
// checking wrap to the first element for signedbyte_enum
if (signedbyte_enum != signedbyte_enum.first) begin
$display ("FAILED - The next method did not wrap to the first element for signedbyte_enum");
$finish;
end
// checking the next method on E1
E1 = E1.first;
for (i=E1.first; i<= E1.last; i=i+1) begin
if (E1 != i) begin
$display ("FAILED - The next method does not report as expected for E1");
$finish;
end
E1 = E1.next;
end
// checking wrap to the first element in E1
if (E1 != E1.first) begin
$display ("FAILED - The next method did not wrap to the first element for E1");
$finish;
end
// checking the next method on vr, manual walk
vr = vr.first;
vr = vr.next;
if (vr != 2) begin
$display ("FAILED - The next method does not report as expected for vr in element REGISTER1");
$finish;
end
vr = vr.next;
if (vr != 10) begin
$display ("FAILED - The next method does not report as expected for vr in element REGISTER2");
$finish;
end
vr = vr.next;
if (vr != 11) begin
$display ("FAILED - The next method does not report as expected for vr in element REGISTER3");
$finish;
end
vr = vr.next;
if (vr != 12) begin
$display ("FAILED - The next method does not report as expected for vr in element REGISTER4");
$finish;
end
// checking wrap to the first element in vr
vr = vr.next;
if (vr != vr.first) begin
$display ("FAILED - The next method did not wrap to the first element for vr");
$finish;
end
// checking the next method for bin_enum
bin_enum = bin_enum.first;
for (i=bin_enum.first; i<= bin_enum.last; i = i+1) begin
if (bin_enum != i) begin
$display ("FAILED - The next method does not report as expected for bin_enum");
$finish;
end
bin_enum = bin_enum.next;
end
// checking wrap to the first element in bin_enum
if (bin_enum != bin_enum.first) begin
$display ("FAILED - The next method did not wrap to the first element for bin_enum");
$finish;
end
$display ("PASSED");
end
endmodule
|
// $ iverilog -Wall simpler.v -o simpler
// $ vvp simpler
// simpler:37: syntax error
`timescale 1ns / 1ns
module simpler;
reg [1:0] cnt=0;
wire result;
defparam \\Mcount_cnt_xor<3>11 .INIT = 4\'hC;
test_lut \\Mcount_cnt_xor<3>11 (
\t.a0(cnt[0]),
\t.a1(cnt[1]),
\t.O(result)
);
initial $display("PASSED");
endmodule
module test_lut (output O, input a0, input a1);
\tparameter INIT = 4\'h0;
\treg tmp;
\talways @(*) tmp = mux ( INIT, {a1, a0});
\tassign O = tmp;
\tfunction mux;
\t\tinput [3:0] d;
\t\tinput [1:0] s;
\t\tmux = d[s];
\tendfunction
endmodule
|
module ts_pad (
inout wire pad,
input wire oe,
input wire op
);
assign pad = oe ? op : 1\'bz;
endmodule
module test();
wire [1:0] bus;
reg oe1 = 1\'b0;
reg oe2 = 1\'b0;
reg oe3 = 1\'b0;
reg oe4 = 1\'b0;
reg oe5 = 1\'b0;
reg oe6 = 1\'b0;
wire op1 = 1\'b0;
wire op2 = 1\'b1;
wire op3 = 1\'b1;
wire op4 = 1\'b0;
wire op5 = 1\'bx;
wire op6 = 1\'bx;
ts_pad pad1(bus[0], oe1, op1);
ts_pad pad2(bus[1], oe2, op2);
ts_pad pad3(bus[0], oe3, op3);
ts_pad pad4(bus[1], oe4, op4);
bufif1(bus[0], op5, oe5);
bufif1(bus[1], op6, oe6);
integer multi;
integer forced;
integer countD;
integer count0;
integer count1;
integer countX;
reg failed = 0;
task check_results;
input integer expected_multi;
input integer expected_forced;
input integer expected_countD;
input integer expected_count0;
input integer expected_count1;
input integer expected_countX;
begin
$write("multi = %0d ", multi);
if (multi !== expected_multi) failed = 1;
if (expected_forced != -1) begin
$write("forced = %0d ", forced);
if (forced !== expected_forced) failed = 1;
end
if (expected_countD != -1) begin
$write("countD = %0d ", countD);
if (countD !== expected_countD) failed = 1;
end
if (expected_count0 != -1) begin
$write("count0 = %0d ", count0);
if (count0 !== expected_count0) failed = 1;
end
if (expected_count1 != -1) begin
$write("count1 = %0d ", count1);
if (count1 !== expected_count1) failed = 1;
end
if (expected_countX != -1) begin
$write("countX = %0d ", countX);
if (countX !== expected_countX) failed = 1;
end
$write("\
");
end
endtask
initial begin
#1;
multi = $countdrivers(bus[0], forced, countD, count0, count1, countX);
check_results(0, 0, 0, 0, 0, 0);
multi = $countdrivers(bus[1], forced, countD, count0, count1, countX);
check_results(0, 0, 0, 0, 0, 0);
multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX);
check_results(0, 0, 0, 0, 0, 0);
multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX);
check_results(0, 0, 0, 0, 0, 0);
$display("");
oe1 = 1\'b1;
#1;
multi = $countdrivers(bus[0], forced, countD, count0, count1, countX);
check_results(0, 0, 1, 1, 0, 0);
multi = $countdrivers(bus[1], forced, countD, count0, count1, countX);
check_results(0, 0, 0, 0, 0, 0);
multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX);
check_results(0, 0, 1, 1, 0, 0);
multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX);
check_results(0, 0, 0, 0, 0, 0);
$display("");
oe2 = 1\'b1;
#1;
multi = $countdrivers(bus[0], forced, countD, count0, count1, countX);
check_results(0, 0, 1, 1, 0, 0);
multi = $countdrivers(bus[1], forced, countD, count0, count1, countX);
check_results(0, 0, 1, 0, 1, 0);
multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX);
check_results(0, 0, 1, 1, 0, 0);
multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX);
check_results(0, 0, 1, 0, 1, 0);
$display("");
oe3 = 1\'b1;
#1;
multi = $countdrivers(bus[0], forced, countD, count0, count1, countX);
check_results(1, 0, 2, 1, 1, 0);
multi = $countdrivers(bus[1], forced, countD, count0, count1, countX);
check_results(0, 0, 1, 0, 1, 0);
multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 1, 1, 0);
multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX);
check_results(0, 0, 1, 0, 1, 0);
$display("");
oe4 = 1\'b1;
#1;
multi = $countdrivers(bus[0], forced, countD, count0, count1, countX);
check_results(1, 0, 2, 1, 1, 0);
multi = $countdrivers(bus[1], forced, countD, count0, count1, countX);
check_results(1, 0, 2, 1, 1, 0);
multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 1, 1, 0);
multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 1, 1, 0);
$display("");
oe5 = 1\'b1;
#1;
multi = $countdrivers(bus[0], forced, countD, count0, count1, countX);
check_results(1, 0, 3, 1, 1, 1);
multi = $countdrivers(bus[1], forced, countD, count0, count1, countX);
check_results(1, 0, 2, 1, 1, 0);
multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX);
check_results(1, 0, 3, 1, 1, 1);
multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 1, 1, 0);
$display("");
oe6 = 1\'b1;
#1;
multi = $countdrivers(bus[0], forced, countD, count0, count1, countX);
check_results(1, 0, 3, 1, 1, 1);
multi = $countdrivers(bus[1], forced, countD, count0, count1, countX);
check_results(1, 0, 3, 1, 1, 1);
multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX);
check_results(1, 0, 3, 1, 1, 1);
multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX);
check_results(1, 0, 3, 1, 1, 1);
$display("");
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
/*
*/
module main;
reg [1:0] sel, in;
reg [1:0] out;
(* ivl_combinational *)
always @*
(* ivl_full_case *) case (sel)
2\'b01: out = 2\'b10;
2\'b10: out = in[0];
2\'b11: out = in[1];
endcase // casex(sel)
(* ivl_synthesis_off *)
initial begin
in = 2\'b10;
sel = 1;
#1 if (out !== 2\'b10) begin
\t $display("FAILED -- sel=%b, out=%b", sel, out);
\t $finish;
end
sel = 2;
#1 if (out !== 2\'b00) begin
\t $display("FAILED -- sel=%b, in=%b, out=%b", sel, in, out);
\t $finish;
end
sel = 3;
#1 if (out !== 2\'b01) begin
\t $display("FAILED -- sel=%b, in=%b, out=%b", sel, in, out);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
module top;
parameter parm = 1.4;
reg [31:0] str;
initial begin
$sformat(str, "R: %d", parm);
if (str !== "R: 1") $display("FAILED: expected \'R: 1\', got %s", str);
else $display("PASSED");
end
endmodule
|
// Check that parameter declared in the module body can not be overridden if the
// module has a parameter port list.
module a #(
parameter A = 1
);
// This behaves like a localparam
parameter B = 1;
initial begin
$display("FAILED");
end
endmodule
module test;
a #(
.A(10),
.B(20) // Error
) i_a();
endmodule
|
// Check that a assignment operator on an integer array entry with an immediate
// index works if it happes after a comparison that sets vvp flag 4 to 0.
module test;
logic [7:0] x[10];
logic a = 1\'b0;
initial begin
x[0] = 10;
if (a == 0) begin
// Make sure that this update happens, even though the compare above
// cleared set vvp flag 4
x[0] += 1;
end
if (x[0] == 11) begin
$display("PASSED");
end else begin
$display("FAILED. Expected 11, got %0d", x[0]);
end
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate unary or ~^(value)
//
module main;
reg [3:0] vect;
reg\terror;
wire\tresult;
assign result = ~^(vect);
initial
begin
error = 0;
for(vect=4\'b0001;vect<4\'b0000;vect = vect << 1)
begin
#1;
if(result !== 1\'b0)
begin
$display("FAILED - Unary xnor ~^(%b)=%b",vect,result);
error = 1\'b1;
end
end
#1;
for(vect=4\'b0011;vect<4\'b0000;vect = vect << 1)
begin
#1;
if(result !== 1\'b0)
begin
$display("FAILED - Unary xnor ~^(%b)=%b",vect,result);
error = 1\'b1;
end
end
#1;
vect = 4\'b0000;
#1;
if(result !== 1\'b1)
begin
$display("FAILED - Unary xnor ~^(%b)=%b",vect,result);
error = 1\'b1;
end
if(error === 0 )
$display("PASSED");
end
endmodule // main
|
// Check that it is an error to declare a non-ANSI task port without implicit
// packed dimensions if it is later redeclared as a vector typed variable and
// the vector type is not a scalar.
module test;
task t;
input [7:0] x;
reg x;
$display("FAILED");
endtask
initial begin
t(10);
end
endmodule
|
module check (input unsigned [103:0] a, b, c);
wire [103:0] int_AB;
assign int_AB = a | b;
always @(a, b, int_AB, c) begin
#1;
if (int_AB !== c) begin
$display("ERROR");
$finish;
end
end
endmodule
module stimulus (output reg unsigned [103:0] A, B);
parameter S = 2000;
int unsigned i;
initial begin
A = 0; B= 0;
// values with 0, 1
for (i=0; i<S; i=i+1) begin
#1 A[103:8] = {$random, $random, $random};
A[7:0] =\t$random % 256;
B[103:8] = {$random, $random, $random};
B[7:0] = $random % 256;
end
// values with x, z
for (i=0; i<S; i=i+1) begin
#1;
A[103:8] = {$random, $random, $random};
A[7:0] =\t$random % 256;
B[103:8] = {$random, $random, $random};
B[7:0] = $random % 256;
A[103:72] = xz_inject (A[103:72]);
A[71:40] = xz_inject (A[71:40]);
B[71:40] = xz_inject (B[71:40]);
B[39:8] = xz_inject (B[39:8]);
end
end
// injects some x, z values on 32 bits arguments
function [31:0] xz_inject (input unsigned [31:0] value);
integer i, temp;
begin
temp = {$random};
for (i=0; i<32; i=i+1)
begin
if (temp[i] == 1\'b1)
begin
temp = $random;
if (temp <= 0)
value[i] = 1\'bx; // \'x noise
else
value[i] = 1\'bz; // \'z noise
end
end
xz_inject = value;
end
endfunction
endmodule
module test;
wire unsigned [103:0] a, b;
wire unsigned [103:0] r;
stimulus stim (.A(a), .B(b));
or104 duv (.a_i(a), .b_i(b), .c_o(r) );
check check (.a(a), .b(b), .c(r) );
initial begin
#120000;
$display("PASSED");
$finish;
end
endmodule
|
`begin_keywords "1364-2005"
module main;
reg [3:0] foo, bar;
reg [1:0] adr;
reg\t bit, rst, clk;
reg\t load_enable, write_enable;
(* ivl_synthesis_on *)
always @(posedge clk or posedge rst)
if (rst) begin
\tfoo <= 0;
end else if (load_enable) begin
\tfoo <= bar;
end else if (write_enable) begin
\tfoo[adr] <= bit;
end
(* ivl_synthesis_off *)
initial begin
rst = 1;
clk = 0;
bar = 4\'bzzzz;
load_enable = 0;
write_enable = 0;
#1 clk = 1;
#1 clk = 0;
if (foo !== 4\'b0000) begin
\t $display("FAILED -- reset foo=%b", foo);
\t $finish;
end
rst = 0;
bar = 4\'b1001;
load_enable = 1;
write_enable = 0;
#1 clk = 1;
#1 clk = 0;
if (foo !== bar) begin
\t $display("FAILED -- load foo=%b, bar=%b", foo, bar);
\t $finish;
end
load_enable = 0;
write_enable = 0;
#1 clk = 1;
#1 clk = 0;
if (foo !== 4\'b1001) begin
\t $display("FAILED -- foo=%b after clk", foo);
\t $finish;
end
adr = 1;
bit = 1;
load_enable = 0;
write_enable = 1;
#1 clk = 1;
#1 clk = 0;
if (foo !== 4\'b1011) begin
\t $display("FAILED -- foo=%b, adr=%b, bit=%b", foo, adr, bit);
\t $finish;
end
$display("PASSED");
$finish;
end
endmodule // main
`end_keywords
|
// Copyright (c) 2016 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for delayed assignment statements.
module vhdl_delay_assign_test;
logic a, b, c;
int passed = 0;
vhdl_delay_assign dut(a, b, c);
always @(b)
begin
if($time == 10) begin
passed = passed + 1;
end else begin
$display("FAILED 1");
$finish();
end
end
always @(c)
begin
if($time == 10) begin
passed = passed + 1;
end else begin
$display("FAILED 2");
$finish();
end
end
initial begin
a = 1;
#11;
if(passed !== 2) begin
$display("FAILED 3");
$finish();
end
$display("PASSED");
end
endmodule
|
`timescale 1ns/1ns
module top;
real rtrig = 0.0;
wire real rtm;
assign rtm = rtrig * $realtime;
initial begin
$monitor(rtm);
#1 rtrig = 1.0;
#1 rtrig = 0.0;
#1 rtrig = 1.0;
#1 rtrig = 0.0;
end
endmodule
|
/* Based on PR#848 */
module err ();
reg clk;
initial begin
clk = 1\'b1;
#3 forever #10 clk=~clk;
end
reg [31:0] mem [10:0];
wire [32:0] kuku = {1\'b0,mem[3]};
always @(posedge clk) begin
if (kuku !== 33\'h0_xx_xx_xx_xx) begin
$display("FAILED -- kuku has wrong value %h", kuku);
$finish;
end
$display("PASSED");
$finish;
end
endmodule
|
`begin_keywords "1364-2005"
module top;
reg svar;
reg sarr [1:0];
reg sout, stmp;
wire wsarr [1:0];
wire wsbslv, wspslv, wsuplv, wsdolv;
wire wsbstr, wspstr, wsuptr, wsdotr;
wire wsbs = svar[0];
wire wsps = svar[0:0];
wire wsup = svar[0+:1];
wire wsdo = svar[0-:1];
wire wsabs = sarr[0][0];
wire wsaps = sarr[0][0:0];
wire wsaup = sarr[0][0+:1];
wire wsado = sarr[0][0-:1];
assign wsbslv[0] = svar;
assign wspslv[0:0] = svar;
assign wsuplv[0+:1] = svar;
assign wsdolv[0-:1] = svar;
assign wsarr[0][0] = svar;
assign wsarr[0][0:0] = svar;
assign wsarr[0][0+:1] = svar;
assign wsarr[0][0-:1] = svar;
tran(wsbstr[0], wsarr[1]);
tran(wspstr[0:0], wsarr[1]);
tran(wsuptr[0+:1], wsarr[1]);
tran(wsdotr[0-:1], wsarr[1]);
submod1 s1 (wsbstr[0], wspstr[0:0], wsuptr[0+:1], wsdotr[0-:1]);
submod2 s2 (wsbstr[0], wspstr[0:0], wsuptr[0+:1], wsdotr[0-:1]);
submod3 s3 (wsbstr[0], wspstr[0:0], wsuptr[0+:1], wsdotr[0-:1]);
task stask;
input a;
reg local;
begin
local = a[0];
local = a[0:0];
local = a[0+:1];
local = a[0-:1];
end
endtask
initial begin
stmp = svar[0];
stmp = svar[0:0];
stmp = svar[0+:1];
stmp = svar[0-:1];
stmp = sarr[0][0];
stmp = sarr[0][0:0];
stmp = sarr[0][0+:1];
stmp = sarr[0][0-:1];
sout[0] = 1\'b0;
sout[0:0] = 1\'b0;
sout[0+:1] = 1\'b0;
sout[0-:1] = 1\'b0;
sarr[0][0] = 1\'b0;
sarr[0][0:0] = 1\'b0;
sarr[0][0+:1] = 1\'b0;
sarr[0][0-:1] = 1\'b0;
end
endmodule
module submod1(arg1, arg2, arg3, arg4);
input arg1, arg2, arg3, arg4;
wire arg1, arg2, arg3, arg4;
initial $display("In submod1 with %b, %b, %b, %b", arg1, arg2, arg3, arg4);
endmodule
module submod2(arg1, arg2, arg3, arg4);
output arg1, arg2, arg3, arg4;
wire arg1, arg2, arg3, arg4;
initial $display("In submod2 with %b, %b, %b, %b", arg1, arg2, arg3, arg4);
endmodule
module submod3(arg1, arg2, arg3, arg4);
inout arg1, arg2, arg3, arg4;
wire arg1, arg2, arg3, arg4;
initial $display("In submod3 with %b, %b, %b, %b", arg1, arg2, arg3, arg4);
endmodule
`end_keywords
|
module modname;
`define macro1(arg1) $display(`"arg1`");
`define macro2(arg1=d1, arg2) $display(`"arg1 arg2`");
initial begin
`macro1(1)
`macro2(1,2)
end
endmodule
|
// Use the default timescale.
module top;
initial begin
$printtimescale(top);
$printtimescale(other);
$printtimescale(other2);
end
endmodule
`timescale 1ms/1ms
// Use the given timescale.
module other;
endmodule
`resetall
// Use the default timescale.
module other2;
endmodule
|
/*
* Copyright (c) 2000 Intrinsity, Inc.
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module test_bufif0 ();
wire t0, t1, t2, t3, t4, t5, t6, t7,
t8, t9, ta, tb, tc, td, te, tf;
reg gnd, vdd, x, z;
reg failed;
wire StH, StL;
assign (strong1, highz0) StH = 1\'bx;
assign (highz1, strong0) StL = 1\'bx;
bufif0 n0 ( t0, gnd, gnd);
bufif0 n1 ( t1, gnd, vdd);
bufif0 n2 ( t2, gnd, x);
bufif0 n3 ( t3, gnd, z);
bufif0 n4 ( t4, vdd, gnd);
bufif0 n5 ( t5, vdd, vdd);
bufif0 n6 ( t6, vdd, x);
bufif0 n7 ( t7, vdd, z);
bufif0 n8 ( t8, x, gnd);
bufif0 n9 ( t9, x, vdd);
bufif0 na ( ta, x, x);
bufif0 nb ( tb, x, z);
bufif0 nc ( tc, z, gnd);
bufif0 nd ( td, z, vdd);
bufif0 ne ( te, z, x);
bufif0 nf ( tf, z, z);
initial begin
assign gnd = 1\'b1;
assign vdd = 1\'b0;
assign x = 1\'b0;
assign z = 1\'b0;
#10;
assign gnd = 1\'b0;
assign vdd = 1\'b1;
assign x = 1\'b1;
assign z = 1\'b1;
#10;
assign gnd = 1\'b0;
assign vdd = 1\'b1;
assign x = 1\'bx;
assign z = 1\'bz;
#10;
failed = 0;
if (t0 !== gnd)
begin
failed = 1;
$display ("FAILED: bufif0 s:%d g:%d d:%d expected:0", gnd, gnd, t0 );
end
if (t1 !== z)
begin
failed = 1;
$display ("FAILED: bufif0 s:%d g:%d d:%d expected:z", gnd, vdd, t1 );
end
if (t2 !== StL)
begin
failed = 1;
$display ("FAILED: bufif0 s:%d g:%d d:%d expected:StL", gnd, x, t2 );
end
if (t3 !== StL)
begin
failed = 1;
$display ("FAILED: bufif0 s:%d g:%d d:%d expected:StL", gnd, x, t3 );
end
if (t4 !== 1\'b1)
begin
failed = 1;
$display ("FAILED: bufif0 s:%d g:%d d:%d expected:1", vdd, gnd, t4 );
end
if (t5 !== z)
begin
failed = 1;
$display ("FAILED: bufif0 s:%d g:%d d:%d expected:z", vdd, vdd, t5 );
end
if (t6 !== StH)
begin
failed = 1;
$display ("FAILED: bufif0 s:%d g:%d d:%d expected:StH", vdd, x, t6 );
end
if (t7 !== StH)
begin
failed = 1;
$display ("FAILED: bufif0 s:%d g:%d d:%d expected:StH", vdd, x, t7 );
end
if (t8 !== 1\'bx)
begin
failed = 1;
$display ("FAILED: bufif0 s:%d g:%d d:%d expected:x", x, gnd, t8 );
end
if (t9 !== 1\'bz)
begin
failed = 1;
$display ("FAILED: bufif0 s:%d g:%d d:%d expected:z", x, vdd, t9 );
end
if (ta !== 1\'bx)
begin
failed = 1;
$display ("FAILED: bufif0 s:%d g:%d d:%d expected:x", x, x, ta );
end
if (tb !== 1\'bx)
begin
failed = 1;
$display ("FAILED: bufif0 s:%d g:%d d:%d expected:x", x, z, tb );
end
if (tc !== 1\'bx)
begin
failed = 1;
$display ("FAILED: bufif0 s:%d g:%d d:%d expected:x", z, gnd, tc );
end
if (td !== 1\'bz)
begin
failed = 1;
$display ("FAILED: bufif0 s:%d g:%d d:%d expected:z", z, vdd, td );
end
if (te !== 1\'bx)
begin
failed = 1;
$display ("FAILED: bufif0 s:%d g:%d d:%d expected:x", z, x, te );
end
if (tf !== 1\'bx)
begin
failed = 1;
$display ("FAILED: bufif0 s:%d g:%d d:%d expected:x", z, z, tf );
end
if (failed == 0)
$display ("PASSED");
end
endmodule
|
// Check that it is not possible to assign a queue with a signed element type to
// a queue with a unsigned element type. Even if they are otherwise identical.
module test;
logic [31:0] q1[$];
logic signed [31:0] q2[$];
initial begin
q1 = q2;
$dispaly("FAILED");
end
endmodule
|
module top_module(
input wire [2:0] N,
input wire [7:0] In,
output reg [7:0] Out
);
wire [7:0] Array[7:0];
assign Array[N][0] = In[0];
assign Array[0][7:1] = In[7:1];
initial begin
Out[0] = Array[0][0];
Out[7:1] = Array[0][7:1];
end
endmodule
|
module test;
string mema[];
string memb[];
reg failed = 0;
initial begin
mema = new[4] (\'{"A","B","C","D"});
$display("%s %s %s %s", mema[0], mema[1], mema[2], mema[3]);
memb = new[4] (mema);
$display("%s %s %s %s", memb[0], memb[1], memb[2], memb[3]);
if (memb[0] != "A" || memb[1] != "B" || memb[2] != "C" || memb[3] != "D") failed = 1;
memb = new[5] (memb);
$display("%s %s %s %s %s", memb[0], memb[1], memb[2], memb[3], memb[4]);
if (memb[0] != "A" || memb[1] != "B" || memb[2] != "C" || memb[3] != "D" || memb[4] != "") failed = 1;
memb = new[3] (memb);
$display("%s %s %s", memb[0], memb[1], memb[2]);
if (memb[0] != "A" || memb[1] != "B" || memb[2] != "C") failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module test();
wire clk;
reg [8:0]\tlowp2_tmp;
reg [8:0]\tlowp2_out;
always @(posedge clk) begin
lowp2_out <= ( {lowp2_tmp[8], lowp2_tmp} ) >> 1;
end
endmodule
|
`define FOO bar
module foo;
initial begin
$display("macro FOO = %s", ``FOO);
end
endmodule
|
// Use the default timescale.
module top;
initial begin
$printtimescale(top);
$printtimescale(other);
$printtimescale(other2);
end
endmodule
`timescale 1ms/1ms
// Use the given timescale.
module other;
endmodule
`resetall
// Use the default timescale.
module other2;
endmodule
|
module top;
// You can\'t have duplicate values!
enum {red = 1, green, blue = 2} light;
enum {first = 2, second = 1, third} nums;
initial $display("FAILED");
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - always release net_lvalue ;
// D: No dependancy
module main ;
wire [3:0] value1 ;
initial
begin
#15;
if(value1 != 4\'h5)
$display("FAILED - 3.1.3H always release net_lvalue;\
");
else
\tbegin
$display("PASSED\
");
\t $finish;
end
end
always release value1 ;
endmodule
|
module top;
initial fork : named_fork
$display("PASSED");
join : named_fork
endmodule
|
module test;
parameter NBytes = 21;
parameter Message = "0H1d2j3i4k 5R6i7k8d9["; // Message to send
integer J;
reg [7:0] RSData;
initial begin
for (J=(NBytes-1); J>=0; J=J-1)
\tbegin
\t RSData = (Message>>(J*8)) & 8\'hFF;
\t $display("RSData=%h", RSData);
\tend
end
endmodule // test
|
`timescale 1ns/1ns
module main;
submodule test();
endmodule // main
`timescale 10ns/1ns
module submodule;
reg [63:0] val;
initial begin
#1 $display("$time = %0d", $time);
val = $time;
if (val !== 64\'d1) begin
\t $display("FAILED -- value is %0d (should be 1)", val);
\t $finish;
end
$display("PASSED");
end
endmodule // submodule
|
module br993a();
reg clk;
reg a;
reg b;
reg [1:0] q;
(* ivl_synthesis_on *)
always @(posedge clk) begin
q <= 0;
if (a) q <= 1;
if (b) q <= 2;
end
(* ivl_synthesis_off *)
reg failed;
initial begin
clk = 0;
a = 0;
b = 0;
#1 clk = 1;
#1 clk = 0;
$display("%d", q);
if (q !== 2\'d0) failed = 1;
a = 1;
b = 0;
#1 clk = 1;
#1 clk = 0;
$display("%d", q);
if (q !== 2\'d1) failed = 1;
a = 1;
b = 1;
#1 clk = 1;
#1 clk = 0;
$display("%d", q);
if (q !== 2\'d2) failed = 1;
a = 0;
b = 1;
#1 clk = 1;
#1 clk = 0;
$display("%d", q);
if (q !== 2\'d2) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
// Check that nested unpacked array types are supported.
module test;
localparam A = 3;
localparam B = 5;
localparam C = 2;
localparam D = 7;
typedef logic [31:0] T1[A];
typedef T1 T2[B][C];
T2 x[D];
T2 y;
bit failed = 1\'b0;
`define check(expr, val) \\
if (expr !== val) begin \\
$display("FAILED: %s, expected %0d, got %0d", `"expr`", val, expr); \\
failed = 1\'b1; \\
end
initial begin
`check($unpacked_dimensions(x), 4)
`check($size(x, 1), A)
`check($size(x, 2), B)
`check($size(x, 3), C)
`check($size(x, 4), D)
`check($unpacked_dimensions(y), 3)
`check($size(y, 1), A)
`check($size(y, 2), B)
`check($size(y, 3), C)
`check($bits(T2), $bits(integer) * A * B * C)
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always event_trigger ;
module main ;
event one_event ;
always @(one_event)
begin
# 1;
$display("saw event");
end
initial
begin
#1 ;
#1 ;
#1 ;
$finish ;
end
always -> one_event ;
endmodule
|
/*
* Copyright (c) 2002 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
reg a, b;
wire res;
has_ports test(res, a, b);
initial begin
a = 0;
b = 0;
#1 $display("has_ports (%b, %b, %b)", res, a, b);
if (res !== (a & b)) begin
\t $display("FAILED");
\t $finish;
end
a = 1;
#1 $display("has_ports (%b, %b, %b)", res, a, b);
if (res !== (a & b)) begin
\t $display("FAILED");
\t $finish;
end
b = 1;
#1 $display("has_ports (%b, %b, %b)", res, a, b);
if (res !== (a & b)) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule // main
module has_ports (output reg o, input wire a, input wire b);
always @* o <= a & b;
endmodule // has_ports
|
module top;
reg [7:0] a;
reg [7:0] b;
reg [7:0] c;
integer retcode;
initial
begin
#0; // avoid T0 race
\t a = 0;
\t b = 0;
\t c = 0;
\t /* Use VPI to set values on these registers */
\t retcode = $example(a, b, c);
end
always @(a)
$display("%t The value of A is: %b", $time, a);
always @(b)
$display("%t The value of B is: %b", $time, b);
always @(c)
$display("%t The value of C is: %b", $time, c);
endmodule // top
|
// test that if the signal doesn't exist, an error is thrown
module m(input a, output b);
assign b = a;
endmodule
module top;
reg a;
// wire b;
m foo(.*);
endmodule
|
// Check behaviour with variable array indices on LHS of procedural
// continuous (reg) assignment. This should be rejected by the compiler.
module top;
reg array1[2:1];
integer index = 1;
initial begin
assign array1[index] = 1'b1;
deassign array1[index];
end
endmodule
|
`timescale 1s/1s
module test(outp, outm, outl, in);
output outp, outm, outl;
input in;
// Check a primitive.
assign #1 outp = ~in;
// Check a multiplexer.
assign #1 outm = in ? in : 1\'b0;
// Check a LPM.
assign #1 outl = in === 1\'b1;
endmodule
// This is not exactly the same as the original code, but it is effectively
// the same and should test the same things that were failing.
`timescale 1ns/100ps
module top;
reg in, passed;
wire outp, outm, outl;
test dut(outp, outm, outl, in);
initial begin
passed = 1\'b1;
#1100000000;
if (outp !== 1\'bx) begin
$display("Failed initial prim. check, expected 1\'bx, got %b.", outp);
passed = 1\'b0;
end
if (outm !== 1\'bx) begin
$display("Failed initial mux. check, expected 1\'bx, got %b.", outm);
passed = 1\'b0;
end
if (outl !== 1\'b0) begin
$display("Failed initial LPM check, expected 1\'b0, got %b.", outl);
passed = 1\'b0;
end
in = 0;
#1100000000;
if (outp !== 1\'b1) begin
$display("Failed in=0 prim. check, expected 1\'b1, got %b.", outp);
passed = 1\'b0;
end
if (outm !== 1\'b0) begin
$display("Failed in=0 mux. check, expected 1\'b0, got %b.", outm);
passed = 1\'b0;
end
if (outl !== 1\'b0) begin
$display("Failed in=0 LPM check, expected 1\'b0, got %b.", outl);
passed = 1\'b0;
end
in = 1;
#1100000000;
if (outp !== 1\'b0) begin
$display("Failed in=1 prim. check, expected 1\'b0, got %b.", outp);
passed = 1\'b0;
end
if (outm !== 1\'b1) begin
$display("Failed in=1 mux. check, expected 1\'b1, got %b.", outm);
passed = 1\'b0;
end
if (outl !== 1\'b1) begin
$display("Failed in=1 LPM check, expected 1\'b1, got %b.", outl);
passed = 1\'b0;
end
if (passed) $display("PASSED");
end
endmodule
|
module copy(input [1:0] out, output [1:0] in);
assign out = in;
endmodule
module top();
reg [2:0] r;
wire [0:0] i1;
wire [1:0] i2;
wire [2:0] i3;
wire [1:0] o1;
wire [1:0] o2;
wire [1:0] o3;
assign i1 = r;
assign i2 = r;
assign i3 = r;
copy copy1(o1, i1);
copy copy2(o2, i2);
copy copy3(o3, i3);
reg failed;
initial begin
failed = 0;
for (r = 0; r < 4; r = r + 1) begin
#1 $display("%b : %b %b : %b %b : %b %b", r[1:0], i1, o1, i2, o2, i3, o3);
if (o1 !== {1\'bz, r[0]}) failed = 1;
if (o2 !== r[1:0]) failed = 1;
if (o3 !== r[1:0]) failed = 1;
end
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module top();
reg CLK;
reg [3:0] D;
reg EN;
reg [3:0] Q;
always @(posedge CLK) begin
if (EN) begin
Q[1] <= D[1];
Q[2] <= ~D[2];
Q[3] <= D[3];
end
end
reg failed;
(* ivl_synthesis_off *)
initial begin
failed = 0;
$monitor("%b %b %b %b", CLK, EN, D, Q);
CLK = 0;
EN = 0;
D = 4\'b0000;
#1 CLK = 1;
#1 CLK = 0;
if (Q !== 4\'bxxxx) failed = 1;
EN = 1;
#1 CLK = 1;
#1 CLK = 0;
if (Q !== 4\'b010x) failed = 1;
EN = 0;
D = 4\'b1111;
#1 CLK = 1;
#1 CLK = 0;
if (Q !== 4\'b010x) failed = 1;
EN = 1;
#1 CLK = 1;
#1 CLK = 0;
if (Q !== 4\'b101x) failed = 1;
#1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module test;
reg clock;
initial begin
clock = 0;
forever #5 clock = !clock;
end
wire [0:31] read_data1 [0:7];
reg [0:31] read_data2 [0:7];
assign read_data1[0] = 0;
assign read_data1[1] = 1;
assign read_data1[2] = 2;
assign read_data1[3] = 3;
assign read_data1[4] = 4;
assign read_data1[5] = 5;
assign read_data1[6] = 6;
assign read_data1[7] = 7;
always @(posedge clock) begin: we
reg [3:0] x;
for (x=0; x<8; x=x+1) begin
read_data2[x[2:0]] <= read_data1[x[2:0]];
end
end
always @(posedge clock) begin: wg
integer i;
#1 for (i=0; i<8; i=i+1) begin
$write("%x ", read_data2[i]);
end
$display;
end
initial begin
#20;
$finish(0);
end
endmodule // test
|
/*
* This tests a trivial class. This tests that simple property
* initializers work, but are overridden by an constructor. It
* also tests the global const property.
*/
program main;
// Trivial examples of classes.
class foo_t ;
const int int_incr = 1;
int int_value = 42;
function new();
\t // The declaration assignments happen before the constructor
\t // is called, so we can refer to them.
\t int_value = int_value + int_incr; // s.b. 43
endfunction
endclass : foo_t // foo_t
foo_t obj1;
foo_t obj2;
initial begin
obj1 = new;
if (obj1.int_incr !== 1) begin
\t $display("FAILED == obj1.int_incr=%0d.", obj1.int_incr);
\t $finish;
end
if (obj1.int_value !== 43) begin
\t $display("FAILED -- obj1.int_value=%0d.", obj1.int_value);
\t $finish;
end
// Try a shallow copy to see that the const propery is handled.
obj2 = new obj1;
if (obj2.int_incr !== 1) begin
\t $display("FAILED == obj2.int_incr=%0d.", obj2.int_incr);
\t $finish;
end
if (obj2.int_value !== 43) begin
\t $display("FAILED -- obj2.int_value=%0d.", obj2.int_value);
\t $finish;
end
$display("PASSED");
$finish;
end
endprogram // main
|
// Check that it is an error to declare a non-ANSI task port with implicit
// packed dimensions if it is later redeclared as a enum typed variable. Even if
// the size of the packed dimensions matches that of the size of the enum type.
typedef enum integer {
A, B
} T;
module test;
task t;
input [31:0] x;
T x;
$display("FAILED");
endtask
initial t(10);
endmodule
|
module top;
specify
specparam s_int = -1;
specparam s_real = -1.0;
endspecify
endmodule
|
/*
* Copyright (c) 2003 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module displaysigned();
reg signed [7:0] foo;
reg [7:0] bar;
initial begin
foo = -8\'sd2;
bar = foo;
$display("foo=%0d bar=%0d $signed(bar)=%0d",
\t foo, bar, $signed(bar));
$finish(0);
end
endmodule
|
// Check that declaring a variable multiple times for a signal that was
// previously declared as a non-ANSI module port is an error.
module test(x);
output x;
reg x;
reg x;
endmodule
|
/*
* Some more detailed tests of the abs() function.
*
* Copyright (C) 2007-2008 Cary R. ([email protected])
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
module main;
reg signed [7:0] a, b;
initial begin
a = 1;
b = -1;
if (abs(0) !== 0) begin
\t $display("FAILED");
\t $finish;
end
if (abs(1) !== 1) begin
\t $display("FAILED");
\t $finish;
end
if (abs(-1) !== 1) begin
\t $display("FAILED");
\t $finish;
end
if (abs(a) !== 1) begin
\t $display("FAILED");
\t $finish;
end
if (abs(b) !== 1) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
module top;
reg passed;
reg signed[95:0] m_one, m_two, zero, one, two;
// Both argument positive.
reg signed[95:0] rem;
wire signed[95:0] wrem = one % two;
// First argument negative.
reg signed[95:0] rem1n;
wire signed[95:0] wrem1n = m_one % two;
// Second argument negative.
reg signed[95:0] rem2n;
wire signed[95:0] wrem2n = one % m_two;
// Both arguments negative.
reg signed[95:0] rembn;
wire signed[95:0] wrembn = m_one % m_two;
// Divide by zero.
reg signed[95:0] remd0;
wire signed[95:0] wremd0 = one % zero;
initial begin
passed = 1\'b1;
m_one = 96\'hffffffffffffffffffffffff;
m_two = 96\'hfffffffffffffffffffffffe;
zero = 96\'h000000000000000000000000;
one = 96\'h000000000000000000000001;
two = 96\'h000000000000000000000002;
#1;
// Both positive.
if (wrem !== 96\'h000000000000000000000001) begin
$display("Failed: CA remainder, expected 96\'h00...01, got %h",
wrem);
passed = 1\'b0;
end
rem = one % two;
if (rem !== 96\'h000000000000000000000001) begin
$display("Failed: remainder, expected 96\'h00...01, got %h",
rem);
passed = 1\'b0;
end
// First negative.
if (wrem1n !== 96\'hffffffffffffffffffffffff) begin
$display("Failed: CA remainder (1n), expected 96\'hff...ff, got %h",
wrem1n);
passed = 1\'b0;
end
rem1n = m_one % two;
if (rem1n !== 96\'hffffffffffffffffffffffff) begin
$display("Failed: remainder (1n), expected 96\'hff...ff, got %h",
rem1n);
passed = 1\'b0;
end
// Second negative.
if (wrem2n !== 96\'h000000000000000000000001) begin
$display("Failed: CA remainder (2n), expected 96\'h00...01, got %h",
wrem2n);
passed = 1\'b0;
end
rem2n = one % m_two;
if (rem2n !== 96\'h000000000000000000000001) begin
$display("Failed: remainder (2n), expected 96\'h00...01, got %h",
rem2n);
passed = 1\'b0;
end
// Both negative.
if (wrembn !== 96\'hffffffffffffffffffffffff) begin
$display("Failed: CA remainder (bn), expected 96\'hff...ff, got %h",
wrembn);
passed = 1\'b0;
end
rembn = m_one % m_two;
if (rembn !== 96\'hffffffffffffffffffffffff) begin
$display("Failed: remainder (bn), expected 96\'hff...ff, got %h",
rembn);
passed = 1\'b0;
end
// Divide by zero.
if (wremd0 !== 96\'hxxxxxxxxxxxxxxxxxxxxxxxx) begin
$display("Failed: CA remainder (d0), expected 96\'hxx...xx, got %h",
wremd0);
passed = 1\'b0;
end
remd0 = one % zero;
if (remd0 !== 96\'hxxxxxxxxxxxxxxxxxxxxxxxx) begin
$display("Failed: remainder (d0), expected 96\'hxx...xx, got %h",
remd0);
passed = 1\'b0;
end
if (passed) $display("PASSED");
end
endmodule
|
nature Voltage;
units = "V";
access = V;
idt_nature = Flux;
abstol = 1e-6;
endnature
nature Flux;
units = "Wb";
access = Phi;
ddt_nature = Voltage;
abstol = 1e-9;
endnature
discipline voltage;
potential Voltage;
enddiscipline
module main;
real value;
voltage out;
analog V(out) <+ abs(value);
initial begin
value = 1.0;
#1 if (V(out) != abs(value)) begin
\t $display("FAILED -- value=%g, res=%g", value, V(out));
\t $finish;
end
value = -1.0;
#1 if (V(out) != abs(value)) begin
\t $display("FAILED -- value=%g, res=%f", value, V(out));
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
module bar(clk, rst, inp, out);
(* this_is_clock = 1 *)
input wire clk;
(* this_is_reset = 1 *)
input wire rst;
input wire inp;
(* an_output_register = 1*)
output reg out;
always @(posedge clk)
if (rst) out <= 1\'d0;
else out <= ~inp;
endmodule
module foo(clk, rst, inp, out);
(* this_is_the_master_clock *)
input wire clk;
input wire rst;
input wire inp;
output wire out;
bar bar_instance (clk, rst, inp, out);
initial begin
$display("PASSED");
end
endmodule
|
`timescale 1 ps / 1 ps
module mux_2_to_1
(
input sel_i,
input [1:0] dat_i,
output dat_o
);
assign dat_o = sel_i && dat_i[1] || ~sel_i && dat_i[0];
endmodule
module mux_n_to_1
#(
parameter sel_w = 4,
parameter n_inputs = 2**sel_w
)
(
input [n_inputs-1:0] inputs_i,
input [sel_w-1:0] sel_i,
output output_o
);
genvar i,j;
generate
if(sel_w == 1) begin
mux_2_to_1 mux_simple
(
.sel_i(sel_i),
.dat_i(inputs_i),
.dat_o(output_o)
);
end else begin
wire [n_inputs-2:0] inter_w;
for(i=0; i<sel_w; i=i+1) begin : SELECT_STAGE
if(i==0) begin
for(j=0; j<n_inputs/2; j=j+1) begin : FIRST_STAGE
mux_2_to_1 mux_first_stage
(
.sel_i(sel_i[i]),
.dat_i(inputs_i[2*j+1:2*j]),
.dat_o(inter_w[j])
);
end
end else begin
for(j=0; j<(n_inputs/(2**(i+1))); j=j+1) begin : INTERMEDIARY_STAGE
mux_2_to_1 mux_intermediary_stages
(
.sel_i(sel_i[i]),
.dat_i(inter_w[ (n_inputs/(2**(i-1)))*((2**(i-1))-1) + 2*j + 1 : (n_inputs/(2**(i-1)))*((2**(i-1))-1) + 2*j ]),
.dat_o(inter_w[ (n_inputs/(2**i))*((2**i)-1) + j ])
);
end
end
end
assign output_o = inter_w[ (n_inputs/(2**(sel_w-1)))*((2**(sel_w-1))-1) ];
end
endgenerate
endmodule
module top;
parameter sel_wid = 3;
parameter num_inputs = 2**sel_wid;
reg [num_inputs-1:0] in;
reg [sel_wid-1:0] sel;
wire out;
integer lp;
reg pass;
mux_n_to_1
#(
.sel_w(sel_wid),
.n_inputs(num_inputs)
)
dut
(
.inputs_i(in),
.sel_i(sel),
.output_o(out)
);
initial begin
pass = 1\'b1;
for (lp = 0; lp < num_inputs; lp = lp + 1) begin
sel = lp;
in = 2**lp;
$display("Checking input %0d;", sel);
#1;
if (out !== 1\'b1) begin
$display(" Failed input high (%b), got %b", in, out);
pass = 1\'b0;
end
in = ~in;
#1;
if (out !== 1\'b0) begin
$display(" Failed input low (%b), got %b", in, out);
pass = 1\'b0;
end
end
if (pass) $display("PASSED");
end
endmodule
|
/*
*/
module main;
reg [1:0] sel, in;
reg [1:0] out;
(* ivl_combinational *)
always @*
casex (sel)
2\'b0?: out = 2\'b10;
2\'b10: out = in[0];
2\'b11: out = in[1];
endcase // casex(sel)
(* ivl_synthesis_off *)
initial begin
in = 2\'b10;
sel = 0;
#1 if (out !== 2\'b10) begin
\t $display("FAILED -- sel=%b, out=%b", sel, out);
\t $finish;
end
sel = 1;
#1 if (out !== 2\'b10) begin
\t $display("FAILED -- sel=%b, out=%b", sel, out);
\t $finish;
end
sel = 2;
#1 if (out !== 2\'b00) begin
\t $display("FAILED -- sel=%b, in=%b, out=%b", sel, in, out);
\t $finish;
end
sel = 3;
#1 if (out !== 2\'b01) begin
\t $display("FAILED -- sel=%b, in=%b, out=%b", sel, in, out);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
/*
* This tests a trivial class. This tests that simple property
* initializers work, but are overridden by an constructor. It
* also tests the global const property.
*/
program main;
// Trivial examples of classes.
class foo_t ;
static int int_incr = 1;
int int_value = 42;
function new();
\t // The declaration assignments happen before the constructor
\t // is called, so we can refer to them.
\t int_value = int_value + int_incr; // s.b. 43
endfunction
endclass : foo_t // foo_t
foo_t obj1;
foo_t obj2;
initial begin
// Static properties do not actually look at the instance, so
// we do not need to create an instance to access them.
if (obj1.int_incr !== 1) begin
\t $display("FAILED == obj1.int_incr=%0d.", obj1.int_incr);
\t $finish;
end
obj1 = new;
if (obj1.int_value !== 43) begin
\t $display("FAILED -- obj1.int_value=%0d.", obj1.int_value);
\t $finish;
end
// Try a shallow copy to see that the const propery is handled.
obj2 = new obj1;
if (obj2.int_value !== 43) begin
\t $display("FAILED -- obj2.int_value=%0d.", obj2.int_value);
\t $finish;
end
obj1.int_incr = 2;
if (obj1.int_incr !== 2) begin
\t $display("FAILED == obj1.int_incr=%0d", obj1.int_incr);
\t $finish;
end
if (obj2.int_incr !== 2) begin
\t $display("FAILED == obj2.int_incr=%0d", obj2.int_incr);
\t $finish;
end
$display("PASSED");
$finish;
end
endprogram // main
|
// Check that it is not possible to assign a dynamic array with a real
// element type to a dynamic array with an int element type.
module test;
int d1[];
real d2[];
initial begin
d1 = d2;
$display("FAILED");
end
endmodule
|
/*
* Copyright (c) 2002 Simon Denman
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
//
// File: DivBug.v
// Author: Simon Denman
// Created: 28/3/02
// Description: integer division bug test
module DivBug ;
\tinteger intX, intY;
initial
begin
intX = -8;
intY = intX / 8;
\t$display("%5d %5d", intX, intY);
end
endmodule
|
module top;
real rvar1, rvar2, rtmp;
wire real wrcon3, wrcon4, wrcon5, wrcon6;
wire real wrcon1 = {2.0, 1.0};
wire real wrcon2 = {rvar1, rvar2};
assign wrcon3 = {2.0, 1.0};
assign wrcon4 = {rvar1, rvar2};
assign {wrcon5, wrcon6} = 1.0;
initial begin
rtmp = {2.0, 1.0};
rtmp = {rvar1, rvar2};
{rvar1, rvar2} = rtmp;
end
endmodule
|
// Check that it is possible to declare the data type for a real type module
// port before the direction for non-ANSI style port declarations.
module test(x);
real x;
output x;
initial begin
if (x == 0.0) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
|
module ivtest
(
input [3:0]\tx,
input [3:0]\ty,
output [3:0]\tz
);
assign z = x ^ y;
endmodule // ivtest
|
// Check that it is possible to declare the data type for a time type module
// port separately from the direction for non-ANSI style port declarations.
// declarations.
module test(x);
output x;
time x;
initial begin
if ($bits(x) == 64) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
reg foo = 0;
initial #10 foo = 1;
initial #1 begin
if (foo !== 1\'b0) begin
\t $display("FAILED -- foo before wait is %b", foo);
\t $finish;
end
// This wait without a statement has caused a few bugs.
wait (foo) ;
if (foo !== 1\'b1) begin
\t $display("FAILED -- foo after wait is %b", foo);
\t $finish;
end
if ($time != 10) begin
\t $display("FAILED -- $time after wait is %t", $time);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
module test( clk, a, b );
input\t\t\t clk;
output [0:0] a;
output b;
reg [0:0] a;
reg b;
integer i = 5;
always @(posedge clk) begin
a[i] <= 1'b0;
b <= 1'b0;
end
endmodule
|
module ge2(output wire out, input wire [1:0] A, input wire [1:0] B);
assign out = A >= B;
endmodule // ge2
|
module test();
wire a;
supply0 b;
supply1 c;
supply1 d;
supply0 e;
wire f;
wire g;
wire h;
wire i;
supply1 j;
supply0 k;
wire l;
supply0 m;
supply1 n;
assign d = 1\'b0;
assign e = 1\'b1;
assign f = 1\'b0;
assign f = 1\'b1;
assign g = 1\'b1;
assign g = 1\'b0;
assign (strong1,strong0) h = 1\'b0;
assign ( weak1, weak0) h = 1\'b1;
assign ( weak1, weak0) i = 1\'b0;
assign (strong1,strong0) i = 1\'b1;
assign (supply1,supply0) j = 1\'b0;
assign (supply1,supply0) k = 1\'b1;
wire [1:0] A = {1\'b1, a};
wire [1:0] B = {1\'b1, b};
wire [1:0] C = {1\'b1, c};
wire [1:0] D = {1\'b1, d};
wire [1:0] E = {1\'b1, e};
wire [1:0] F = {1\'b1, f};
wire [1:0] G = {1\'b1, g};
wire [1:0] H = {1\'b1, h};
wire [1:0] I = {1\'b1, i};
wire [1:0] J = {1\'b1, j};
wire [1:0] K = {1\'b1, k};
wire [1:0] L = {1\'b1, l};
wire [1:0] M = {1\'b1, m};
wire [1:0] N = {1\'b1, n};
reg failed;
initial begin
failed = 0; #1;
$display("A = %b, expect 1z", A); if (A !== 2\'b1z) failed = 1;
$display("B = %b, expect 10", B); if (B !== 2\'b10) failed = 1;
$display("C = %b, expect 11", C); if (C !== 2\'b11) failed = 1;
$display("D = %b, expect 11", D); if (D !== 2\'b11) failed = 1;
$display("E = %b, expect 10", E); if (E !== 2\'b10) failed = 1;
$display("F = %b, expect 1x", F); if (F !== 2\'b1x) failed = 1;
$display("G = %b, expect 1x", G); if (G !== 2\'b1x) failed = 1;
$display("H = %b, expect 10", H); if (H !== 2\'b10) failed = 1;
$display("I = %b, expect 11", I); if (I !== 2\'b11) failed = 1;
$display("J = %b, expect 1x", J); if (J !== 2\'b1x) failed = 1;
$display("K = %b, expect 1x", K); if (K !== 2\'b1x) failed = 1;
force l = 1\'b0; #1;
$display("L = %b, expect 10", L); if (L !== 2\'b10) failed = 1;
force l = 1\'b1; #1;
$display("L = %b, expect 11", L); if (L !== 2\'b11) failed = 1;
force m = 1\'b1; #1;
$display("M = %b, expect 11", M); if (M !== 2\'b11) failed = 1;
force n = 1\'b0; #1;
$display("N = %b, expect 10", N); if (N !== 2\'b10) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module test;
reg [63:0] out;
reg [5:0] in;
integer i = 0;
reg failed = 0;
initial begin
for (i = 0; i < 64; i = i + 1) begin
in = i;
out = 2 ** in;
$display("%d: %b", i, out);
if (out !== 64\'d1 << i)
failed = 1;
end
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
/*
* Copyright (c) 2001 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program combines two events with an event or. The tricky part
* for the vvp target is that there is a mix of posedge and negedge
* events.
*/
module ndFF ( nset, reset, Q );
input nset; // clk negedge set Q=1
input reset; // reset posedge set Q=0
output Q ; // Q output
reg Q ;
always @(negedge nset or posedge reset)
begin
\tif (nset ==1\'b0) Q = 1\'b1;
\telse if (reset==1\'b1) Q = 1\'b0;
end
endmodule
module main;
reg nset, reset;
wire Q;
ndFF dut(nset, reset, Q);
initial begin
#0 nset = 1;
reset = 1;
#1 nset = 0;
#1 if (Q !== 1\'b1) begin
\t $display("FAILED (a) nset=%b, reset=%b, Q=%b", nset, reset, Q);
\t $finish;
end
nset = 1;
#1 if (Q !== 1\'b1) begin
\t $display("FAILED (b) nset=%b, reset=%b, Q=%b", nset, reset, Q);
\t $finish;
end
reset = 0;
#1 if (Q !== 1\'b1) begin
\t $display("FAILED (c) nset=%b, reset=%b, Q=%b", nset, reset, Q);
\t $finish;
end
reset = 1;
#1 if (Q !== 1\'b0) begin
\t $display("FAILED (d) nset=%b, reset=%b, Q=%b", nset, reset, Q);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
/*
* Copyright (c) 2001 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This progam catches the case where the truth value is really the
* reduction-OR of the condition expression, and not just the low bit.
*/
module test;
reg [1:0] foo = 2\'b10;
initial #1 begin
while (foo) begin
\t $display("PASSED");
\t $finish;
end
$display("FAILED -- foo = %b", foo);
end
endmodule // test
|
module bug();
function [7:0] dup;
input [7:0] i;
begin
dup = i;
end
endfunction
wire [7:0] a;
assign a = dup(missing);
endmodule
|
module x;
parameter bar0_low = 5\'d16; // Register Space
reg [31:bar0_low] base_address0;
reg [31:0]\t ad_in_d;
wire [0:5]\t hit_bar;
wire\t\t a = |bar0_low;
wire [31:0]\t e = ad_in_d[31:bar0_low];
wire\t\t b = (base_address0==e);
wire\t\t d = b;
assign\t hit_bar[0] = a ? d : 0;
initial begin
if ($bits(base_address0) != 16) begin
\t $display("FAILED -- $bits(base_address0) = %0d", $bits(base_address0));
\t $finish;
end
$display("PASSED");
end
endmodule
|
module test;
reg clk, reset;
wire [24:0] count;
initial begin
clk = 1\'b0;
forever #25 clk = ~clk;
end
initial begin
reset = 1\'b0;
@(negedge clk);
reset = 1\'b1;
repeat(6) @(negedge clk);
reset = 1\'b0;
end
initial begin
#200000;
#500;
if (count != 2000) begin
$display ("Counting FAILED");
$finish;
end
else begin
$display ("PASSED");
#20;
$finish;
end
end
bigcount duv (.clk(clk), .reset(reset), .count(count) );
endmodule
|
module all;
reg pass;
task automatic check;
input sig;
input val;
input [32*8:1] name;
begin
if (sig !== val) begin
$display("FAILED \\"%0s\\", expected %b, got %b", name, val, sig);
pass = 1\'b0;
end
end
endtask
initial begin
pass = 1\'b1;
#100;
if (pass) $display("PASSED");
end
endmodule
/* Check the wire net type. */
`default_nettype wire
module top_wire;
reg in0, in1;
assign tmp = in0;
assign tmp = in1;
initial begin
in0 = 1\'b0; in1 = 1\'b0;
#1 all.check(tmp, 1\'b0, "wire(0,0)");
in0 = 1\'b0; in1 = 1\'b1;
#1 all.check(tmp, 1\'bx, "wire(0,1)");
in0 = 1\'b0; in1 = 1\'bx;
#1 all.check(tmp, 1\'bx, "wire(0,x)");
in0 = 1\'b0; in1 = 1\'bz;
#1 all.check(tmp, 1\'b0, "wire(0,z)");
in0 = 1\'b1; in1 = 1\'b0;
#1 all.check(tmp, 1\'bx, "wire(1,0)");
in0 = 1\'b1; in1 = 1\'b1;
#1 all.check(tmp, 1\'b1, "wire(1,1)");
in0 = 1\'b1; in1 = 1\'bx;
#1 all.check(tmp, 1\'bx, "wire(1,x)");
in0 = 1\'b1; in1 = 1\'bz;
#1 all.check(tmp, 1\'b1, "wire(1,z)");
in0 = 1\'bx; in1 = 1\'b0;
#1 all.check(tmp, 1\'bx, "wire(x,0)");
in0 = 1\'bx; in1 = 1\'b1;
#1 all.check(tmp, 1\'bx, "wire(x,1)");
in0 = 1\'bx; in1 = 1\'bx;
#1 all.check(tmp, 1\'bx, "wire(x,x)");
in0 = 1\'bx; in1 = 1\'bz;
#1 all.check(tmp, 1\'bx, "wire(x,z)");
in0 = 1\'bz; in1 = 1\'b0;
#1 all.check(tmp, 1\'b0, "wire(z,0)");
in0 = 1\'bz; in1 = 1\'b1;
#1 all.check(tmp, 1\'b1, "wire(z,1)");
in0 = 1\'bz; in1 = 1\'bx;
#1 all.check(tmp, 1\'bx, "wire(z,x)");
in0 = 1\'bz; in1 = 1\'bz;
#1 all.check(tmp, 1\'bz, "wire(z,z)");
end
endmodule
/* Check the tri net type (should be identical to wire). */
`default_nettype tri
module top_tri;
reg in0, in1;
assign tmp = in0;
assign tmp = in1;
initial begin
in0 = 1\'b0; in1 = 1\'b0;
#1 all.check(tmp, 1\'b0, "tri(0,0)");
in0 = 1\'b0; in1 = 1\'b1;
#1 all.check(tmp, 1\'bx, "tri(0,1)");
in0 = 1\'b0; in1 = 1\'bx;
#1 all.check(tmp, 1\'bx, "tri(0,x)");
in0 = 1\'b0; in1 = 1\'bz;
#1 all.check(tmp, 1\'b0, "tri(0,z)");
in0 = 1\'b1; in1 = 1\'b0;
#1 all.check(tmp, 1\'bx, "tri(1,0)");
in0 = 1\'b1; in1 = 1\'b1;
#1 all.check(tmp, 1\'b1, "tri(1,1)");
in0 = 1\'b1; in1 = 1\'bx;
#1 all.check(tmp, 1\'bx, "tri(1,x)");
in0 = 1\'b1; in1 = 1\'bz;
#1 all.check(tmp, 1\'b1, "tri(1,z)");
in0 = 1\'bx; in1 = 1\'b0;
#1 all.check(tmp, 1\'bx, "tri(x,0)");
in0 = 1\'bx; in1 = 1\'b1;
#1 all.check(tmp, 1\'bx, "tri(x,1)");
in0 = 1\'bx; in1 = 1\'bx;
#1 all.check(tmp, 1\'bx, "tri(x,x)");
in0 = 1\'bx; in1 = 1\'bz;
#1 all.check(tmp, 1\'bx, "tri(x,z)");
in0 = 1\'bz; in1 = 1\'b0;
#1 all.check(tmp, 1\'b0, "tri(z,0)");
in0 = 1\'bz; in1 = 1\'b1;
#1 all.check(tmp, 1\'b1, "tri(z,1)");
in0 = 1\'bz; in1 = 1\'bx;
#1 all.check(tmp, 1\'bx, "tri(z,x)");
in0 = 1\'bz; in1 = 1\'bz;
#1 all.check(tmp, 1\'bz, "tri(z,z)");
end
endmodule
/* Check the tri0 net type (should be the same as tri except z,z is 0). */
`default_nettype tri0
module top_tri0;
reg in0, in1;
assign tmp = in0;
assign tmp = in1;
initial begin
in0 = 1\'b0; in1 = 1\'b0;
#1 all.check(tmp, 1\'b0, "tri0(0,0)");
in0 = 1\'b0; in1 = 1\'b1;
#1 all.check(tmp, 1\'bx, "tri0(0,1)");
in0 = 1\'b0; in1 = 1\'bx;
#1 all.check(tmp, 1\'bx, "tri0(0,x)");
in0 = 1\'b0; in1 = 1\'bz;
#1 all.check(tmp, 1\'b0, "tri0(0,z)");
in0 = 1\'b1; in1 = 1\'b0;
#1 all.check(tmp, 1\'bx, "tri0(1,0)");
in0 = 1\'b1; in1 = 1\'b1;
#1 all.check(tmp, 1\'b1, "tri0(1,1)");
in0 = 1\'b1; in1 = 1\'bx;
#1 all.check(tmp, 1\'bx, "tri0(1,x)");
in0 = 1\'b1; in1 = 1\'bz;
#1 all.check(tmp, 1\'b1, "tri0(1,z)");
in0 = 1\'bx; in1 = 1\'b0;
#1 all.check(tmp, 1\'bx, "tri0(x,0)");
in0 = 1\'bx; in1 = 1\'b1;
#1 all.check(tmp, 1\'bx, "tri0(x,1)");
in0 = 1\'bx; in1 = 1\'bx;
#1 all.check(tmp, 1\'bx, "tri0(x,x)");
in0 = 1\'bx; in1 = 1\'bz;
#1 all.check(tmp, 1\'bx, "tri0(x,z)");
in0 = 1\'bz; in1 = 1\'b0;
#1 all.check(tmp, 1\'b0, "tri0(z,0)");
in0 = 1\'bz; in1 = 1\'b1;
#1 all.check(tmp, 1\'b1, "tri0(z,1)");
in0 = 1\'bz; in1 = 1\'bx;
#1 all.check(tmp, 1\'bx, "tri0(z,x)");
in0 = 1\'bz; in1 = 1\'bz;
#1 all.check(tmp, 1\'b0, "tri0(z,z)");
end
endmodule
/* Check the tri1 net type (should be the same as tri except z,z is 1). */
`default_nettype tri1
module top_tri1;
reg in0, in1;
assign tmp = in0;
assign tmp = in1;
initial begin
in0 = 1\'b0; in1 = 1\'b0;
#1 all.check(tmp, 1\'b0, "tri1(0,0)");
in0 = 1\'b0; in1 = 1\'b1;
#1 all.check(tmp, 1\'bx, "tri1(0,1)");
in0 = 1\'b0; in1 = 1\'bx;
#1 all.check(tmp, 1\'bx, "tri1(0,x)");
in0 = 1\'b0; in1 = 1\'bz;
#1 all.check(tmp, 1\'b0, "tri1(0,z)");
in0 = 1\'b1; in1 = 1\'b0;
#1 all.check(tmp, 1\'bx, "tri1(1,0)");
in0 = 1\'b1; in1 = 1\'b1;
#1 all.check(tmp, 1\'b1, "tri1(1,1)");
in0 = 1\'b1; in1 = 1\'bx;
#1 all.check(tmp, 1\'bx, "tri1(1,x)");
in0 = 1\'b1; in1 = 1\'bz;
#1 all.check(tmp, 1\'b1, "tri1(1,z)");
in0 = 1\'bx; in1 = 1\'b0;
#1 all.check(tmp, 1\'bx, "tri1(x,0)");
in0 = 1\'bx; in1 = 1\'b1;
#1 all.check(tmp, 1\'bx, "tri1(x,1)");
in0 = 1\'bx; in1 = 1\'bx;
#1 all.check(tmp, 1\'bx, "tri1(x,x)");
in0 = 1\'bx; in1 = 1\'bz;
#1 all.check(tmp, 1\'bx, "tri1(x,z)");
in0 = 1\'bz; in1 = 1\'b0;
#1 all.check(tmp, 1\'b0, "tri1(z,0)");
in0 = 1\'bz; in1 = 1\'b1;
#1 all.check(tmp, 1\'b1, "tri1(z,1)");
in0 = 1\'bz; in1 = 1\'bx;
#1 all.check(tmp, 1\'bx, "tri1(z,x)");
in0 = 1\'bz; in1 = 1\'bz;
#1 all.check(tmp, 1\'b1, "tri1(z,z)");
end
endmodule
/* Check the wand net type. */
`default_nettype wand
module top_wand;
reg in0, in1;
assign tmp = in0;
assign tmp = in1;
initial begin
in0 = 1\'b0; in1 = 1\'b0;
#1 all.check(tmp, 1\'b0, "wand(0,0)");
in0 = 1\'b0; in1 = 1\'b1;
#1 all.check(tmp, 1\'b0, "wand(0,1)");
in0 = 1\'b0; in1 = 1\'bx;
#1 all.check(tmp, 1\'b0, "wand(0,x)");
in0 = 1\'b0; in1 = 1\'bz;
#1 all.check(tmp, 1\'b0, "wand(0,z)");
in0 = 1\'b1; in1 = 1\'b0;
#1 all.check(tmp, 1\'b0, "wand(1,0)");
in0 = 1\'b1; in1 = 1\'b1;
#1 all.check(tmp, 1\'b1, "wand(1,1)");
in0 = 1\'b1; in1 = 1\'bx;
#1 all.check(tmp, 1\'bx, "wand(1,x)");
in0 = 1\'b1; in1 = 1\'bz;
#1 all.check(tmp, 1\'b1, "wand(1,z)");
in0 = 1\'bx; in1 = 1\'b0;
#1 all.check(tmp, 1\'b0, "wand(x,0)");
in0 = 1\'bx; in1 = 1\'b1;
#1 all.check(tmp, 1\'bx, "wand(x,1)");
in0 = 1\'bx; in1 = 1\'bx;
#1 all.check(tmp, 1\'bx, "wand(x,x)");
in0 = 1\'bx; in1 = 1\'bz;
#1 all.check(tmp, 1\'bx, "wand(x,z)");
in0 = 1\'bz; in1 = 1\'b0;
#1 all.check(tmp, 1\'b0, "wand(z,0)");
in0 = 1\'bz; in1 = 1\'b1;
#1 all.check(tmp, 1\'b1, "wand(z,1)");
in0 = 1\'bz; in1 = 1\'bx;
#1 all.check(tmp, 1\'bx, "wand(z,x)");
in0 = 1\'bz; in1 = 1\'bz;
#1 all.check(tmp, 1\'bz, "wand(z,z)");
end
endmodule
/* Check the triand net type (should be the same as wand). */
`default_nettype triand
module top_triand;
reg in0, in1;
assign tmp = in0;
assign tmp = in1;
initial begin
in0 = 1\'b0; in1 = 1\'b0;
#1 all.check(tmp, 1\'b0, "triand(0,0)");
in0 = 1\'b0; in1 = 1\'b1;
#1 all.check(tmp, 1\'b0, "triand(0,1)");
in0 = 1\'b0; in1 = 1\'bx;
#1 all.check(tmp, 1\'b0, "triand(0,x)");
in0 = 1\'b0; in1 = 1\'bz;
#1 all.check(tmp, 1\'b0, "triand(0,z)");
in0 = 1\'b1; in1 = 1\'b0;
#1 all.check(tmp, 1\'b0, "triand(1,0)");
in0 = 1\'b1; in1 = 1\'b1;
#1 all.check(tmp, 1\'b1, "triand(1,1)");
in0 = 1\'b1; in1 = 1\'bx;
#1 all.check(tmp, 1\'bx, "triand(1,x)");
in0 = 1\'b1; in1 = 1\'bz;
#1 all.check(tmp, 1\'b1, "triand(1,z)");
in0 = 1\'bx; in1 = 1\'b0;
#1 all.check(tmp, 1\'b0, "triand(x,0)");
in0 = 1\'bx; in1 = 1\'b1;
#1 all.check(tmp, 1\'bx, "triand(x,1)");
in0 = 1\'bx; in1 = 1\'bx;
#1 all.check(tmp, 1\'bx, "triand(x,x)");
in0 = 1\'bx; in1 = 1\'bz;
#1 all.check(tmp, 1\'bx, "triand(x,z)");
in0 = 1\'bz; in1 = 1\'b0;
#1 all.check(tmp, 1\'b0, "triand(z,0)");
in0 = 1\'bz; in1 = 1\'b1;
#1 all.check(tmp, 1\'b1, "triand(z,1)");
in0 = 1\'bz; in1 = 1\'bx;
#1 all.check(tmp, 1\'bx, "triand(z,x)");
in0 = 1\'bz; in1 = 1\'bz;
#1 all.check(tmp, 1\'bz, "triand(z,z)");
end
endmodule
/* Check the wor net type. */
`default_nettype wor
module top_wor;
reg in0, in1;
assign tmp = in0;
assign tmp = in1;
initial begin
in0 = 1\'b0; in1 = 1\'b0;
#1 all.check(tmp, 1\'b0, "wor(0,0)");
in0 = 1\'b0; in1 = 1\'b1;
#1 all.check(tmp, 1\'b1, "wor(0,1)");
in0 = 1\'b0; in1 = 1\'bx;
#1 all.check(tmp, 1\'bx, "wor(0,x)");
in0 = 1\'b0; in1 = 1\'bz;
#1 all.check(tmp, 1\'b0, "wor(0,z)");
in0 = 1\'b1; in1 = 1\'b0;
#1 all.check(tmp, 1\'b1, "wor(1,0)");
in0 = 1\'b1; in1 = 1\'b1;
#1 all.check(tmp, 1\'b1, "wor(1,1)");
in0 = 1\'b1; in1 = 1\'bx;
#1 all.check(tmp, 1\'b1, "wor(1,x)");
in0 = 1\'b1; in1 = 1\'bz;
#1 all.check(tmp, 1\'b1, "wor(1,z)");
in0 = 1\'bx; in1 = 1\'b0;
#1 all.check(tmp, 1\'bx, "wor(x,0)");
in0 = 1\'bx; in1 = 1\'b1;
#1 all.check(tmp, 1\'b1, "wor(x,1)");
in0 = 1\'bx; in1 = 1\'bx;
#1 all.check(tmp, 1\'bx, "wor(x,x)");
in0 = 1\'bx; in1 = 1\'bz;
#1 all.check(tmp, 1\'bx, "wor(x,z)");
in0 = 1\'bz; in1 = 1\'b0;
#1 all.check(tmp, 1\'b0, "wor(z,0)");
in0 = 1\'bz; in1 = 1\'b1;
#1 all.check(tmp, 1\'b1, "wor(z,1)");
in0 = 1\'bz; in1 = 1\'bx;
#1 all.check(tmp, 1\'bx, "wor(z,x)");
in0 = 1\'bz; in1 = 1\'bz;
#1 all.check(tmp, 1\'bz, "wor(z,z)");
end
endmodule
/* Check the trior net type (should be the same as wor). */
`default_nettype trior
module top_trior;
reg in0, in1;
assign tmp = in0;
assign tmp = in1;
initial begin
in0 = 1\'b0; in1 = 1\'b0;
#1 all.check(tmp, 1\'b0, "trior(0,0)");
in0 = 1\'b0; in1 = 1\'b1;
#1 all.check(tmp, 1\'b1, "trior(0,1)");
in0 = 1\'b0; in1 = 1\'bx;
#1 all.check(tmp, 1\'bx, "trior(0,x)");
in0 = 1\'b0; in1 = 1\'bz;
#1 all.check(tmp, 1\'b0, "trior(0,z)");
in0 = 1\'b1; in1 = 1\'b0;
#1 all.check(tmp, 1\'b1, "trior(1,0)");
in0 = 1\'b1; in1 = 1\'b1;
#1 all.check(tmp, 1\'b1, "trior(1,1)");
in0 = 1\'b1; in1 = 1\'bx;
#1 all.check(tmp, 1\'b1, "trior(1,x)");
in0 = 1\'b1; in1 = 1\'bz;
#1 all.check(tmp, 1\'b1, "trior(1,z)");
in0 = 1\'bx; in1 = 1\'b0;
#1 all.check(tmp, 1\'bx, "trior(x,0)");
in0 = 1\'bx; in1 = 1\'b1;
#1 all.check(tmp, 1\'b1, "trior(x,1)");
in0 = 1\'bx; in1 = 1\'bx;
#1 all.check(tmp, 1\'bx, "trior(x,x)");
in0 = 1\'bx; in1 = 1\'bz;
#1 all.check(tmp, 1\'bx, "trior(x,z)");
in0 = 1\'bz; in1 = 1\'b0;
#1 all.check(tmp, 1\'b0, "trior(z,0)");
in0 = 1\'bz; in1 = 1\'b1;
#1 all.check(tmp, 1\'b1, "trior(z,1)");
in0 = 1\'bz; in1 = 1\'bx;
#1 all.check(tmp, 1\'bx, "trior(z,x)");
in0 = 1\'bz; in1 = 1\'bz;
#1 all.check(tmp, 1\'bz, "trior(z,z)");
end
endmodule
|
/*
* This is frpm PR#138. It is supposed to generate an error.
*/
module bug;
wire[1:0] dout;
wire[1:0] din;
assign dout = din[3:2];
/* foo.vl:9: bit/part select [3:2] out of range for bug.din */
endmodule
|
module copy(output [1:0] out, input [1:0] in);
assign out = in;
endmodule
module top();
reg [2:0] r;
wire [0:0] i1;
wire [1:0] i2;
wire [2:0] i3;
wire [1:0] o1;
wire [1:0] o2;
wire [1:0] o3;
assign i1 = r;
assign i2 = r;
assign i3 = r;
copy copy1(o1, i1);
copy copy2(o2, i2);
copy copy3(o3, i3);
reg failed;
initial begin
failed = 0;
for (r = 0; r < 4; r = r + 1) begin
#1 $display("%b : %b %b : %b %b : %b %b", r[1:0], i1, o1, i2, o2, i3, o3);
if (o1 !== {1\'b0, r[0]}) failed = 1;
if (o2 !== r[1:0]) failed = 1;
if (o3 !== r[1:0]) failed = 1;
end
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
// Check that it is possible to have multiple instances of a module that defines
// a class and that the actual class types can have different implementations
// based on module parameters.
module M #(
parameter X = 0
);
class C;
function int f;
return X;
endfunction
endclass
C c = new;
endmodule
module test;
M #(10) m1();
M #(20) m2();
initial begin
if (m1.c.f() == 10 && m2.c.f() == 20) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
|
module main;
reg a, b, reset, pass;
always @*
a = b | reset;
always @* begin
b = 1\'b0;
#2;
b = a;
end
initial begin
pass = 1\'b1;
reset = 1\'b1;
#1 if(b !== 1\'b0) begin
$display("FAILED initial zero for 1\'b1, got %b", b);
pass = 1\'b0;
end
#2 if(b !== 1\'b1) begin
$display("FAILED initial set to 1\'b1, got %b", b);
pass = 1\'b0;
end
// Since b is already 1\'b1 reset can not change a to zero.
reset = 1\'b0;
#1 if(b !== 1\'b1) begin
$display("FAILED block of initial zero for 1\'b0, got %b", b);
pass = 1\'b0;
end
#2 if(b !== 1\'b1) begin
$display("FAILED block of initial set to 1\'b0, got %b", b);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
// Tests that it possible to omit the `parameter` keyword in a parameter port
// list before changing the parameter type in SystemVerilog. In Verilog this is
// not allowed and should result in an error.
module a #(parameter real A = 1.0, integer B = 2);
initial begin
if (A == 10.1 && B == 20) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
module test;
a #(.A(10.1), .B(20)) i_a();
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: Function with if clause
//
// D:
//
module main ();
reg [3:0] global_var;
reg [3:0] result;
// Interesting because 2 * 0 is 0 ;-)
function [3:0] my_func ;
input [3:0] a;
begin
if(a == 4\'b0)
my_func = 4\'b0;
else
my_func = a + a;
end
endfunction
initial
begin
global_var = 2;
result = my_func(global_var);
if(result != 4)
begin
$display("FAILED - function didn\'t function!\
");
$finish ;
end
$display("PASSED\
");
$finish ;
end
endmodule
|
program main;
int sum;
logic idx; // Use this to test scope;
initial begin
sum = 0;
idx = 1\'bx;
for (int idx = 0 ; idx < 8 ; idx += 1) begin
\t sum += idx;
end
if (sum != 28) begin
\t $display("FAILED -- sum=%0d", sum);
\t $finish;
end
if (idx !== 1\'bx) begin
\t $display("FAILED -- idx in upper scope became %b", idx);
\t $finish;
end
$display("PASSED");
end // initial begin
endprogram
|
module bug05_integerRem;
reg passed;
reg signed[31:0] reg0;
reg signed[31:0] reg1;
reg signed[31:0] rrem;
wire signed[31:0] dividend=reg0;
wire signed[31:0] divisor=reg1;
wire signed[31:0] remainder;
assign remainder= dividend%divisor;
initial begin
\tpassed = 1\'b1;
\treg0=32\'hffffffff;
\treg1=32\'h0d1f0796;
\t//BUG here: remainder==32\'h06b26fdd, should be 32\'hffffffff
\t#1 if (remainder !== 32\'hffffffff) begin
\t\t$display("Failed: CA remainder, expected 32\'hffffffff, got %h",
\t\t remainder);
\t\tpassed = 1\'b0;
\tend
rrem = reg0 % reg1;
\t#1 if (rrem !== 32\'hffffffff) begin
\t\t$display("Failed: remainder, expected 32\'hffffffff, got %h",
\t\t rrem);
\t\tpassed = 1\'b0;
\tend
\tif (passed) $display("PASSED");
end
endmodule
|
module m1();
parameter p = 0;
endmodule
module m2();
generate
genvar i;
for (i = 0; i < 2; i = i + 1) begin : Loop1
m1 m();
defparam m.p = 1 + i;
end
for (i = 2; i < 4; i = i + 1) begin : Loop2
m1 m();
defparam Loop2[i].m.p = 1 + i;
end
for (i = 4; i < 6; i = i + 1) begin : Loop3
m1 m();
defparam m2.Loop3[i].m.p = 1 + i;
end
endgenerate
reg failed = 0;
initial begin
$display("Loop1[0].m.p = %0d", Loop1[0].m.p);
if (Loop1[0].m.p !== 1) failed = 1;
$display("Loop1[1].m.p = %0d", Loop1[1].m.p);
if (Loop1[1].m.p !== 2) failed = 1;
$display("Loop2[2].m.p = %0d", Loop2[2].m.p);
if (Loop2[2].m.p !== 3) failed = 1;
$display("Loop2[3].m.p = %0d", Loop2[3].m.p);
if (Loop2[3].m.p !== 4) failed = 1;
$display("Loop3[4].m.p = %0d", Loop3[4].m.p);
if (Loop3[4].m.p !== 5) failed = 1;
$display("Loop3[5].m.p = %0d", Loop3[5].m.p);
if (Loop3[5].m.p !== 6) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate variable left shift in always block
module main;
reg globvar;
reg [7:0] var1,var2,var3;
reg error;
wire [7:0] value;
assign value = var1 << var2;
initial
begin
error = 0;
#1 ;
var1 = 8\'h1;
var2 = 8\'h0;
#2;
if(value !== 8\'h1)
begin
error = 1;
\t$display ("FAILED - 1 << 0 is %h",value);
end
#1 ;
var1 = 8\'h1;
var2 = 8\'h1;
#2;
if(value !== 8\'h2)
begin
error = 1;
\t$display ("FAILED - 1 << 1 is %h",value);
end
#1 ;
var1 = 8\'h1;
var2 = 8\'h2;
#2;
if(value !== 8\'h4)
begin
error = 1;
\t$display ("FAILED - 1 << 2 is %h",value);
end
#1 ;
var1 = 8\'h1;
var2 = 8\'h3;
#2;
if(value !== 8\'h8)
begin
error = 1;
\t$display ("FAILED - 1 << 3 is %h",value);
end
#1 ;
var1 = 8\'h1;
var2 = 8\'h4;
#2;
if(value !== 8\'h10)
begin
error = 1;
\t$display ("FAILED - 1 << 4 is %h",value);
end
#1 ;
var1 = 8\'h1;
var2 = 8\'h5;
#2;
if(value !== 8\'h20)
begin
error = 1;
\t$display ("FAILED - 1 << 5 is %h",value);
end
#1 ;
var1 = 8\'h1;
var2 = 8\'h6;
#2;
if(value !== 8\'h40)
begin
error = 1;
\t$display ("FAILED - 1 << 6 is %h",value);
end
#1 ;
var1 = 8\'h1;
var2 = 8\'h7;
#2;
if(value !== 8\'h80)
begin
error = 1;
\t$display ("FAILED - 1 << 6 is %h",value);
end
#1 ;
var1 = 8\'ha5;
var2 = 8\'h7;
#2;
if(value !== 8\'h80)
begin
error = 1;
\t$display ("FAILED - a5 << 7 is %h",value);
end
#1 ;
var1 = 8\'ha5;
var2 = 8\'h1;
#2;
if(value !== 8\'h4a)
begin
error = 1;
\t$display ("FAILED - aa << 1 is %h",value);
end
if(error === 0)
$display("PASSED");
end
endmodule // main
|
/*
* Copyright (c) 2000 Steven Wilson ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This test looks for >= operation in a continuous assignment.
*/
module test;
integer a;
integer b;
wire result;
integer error;
assign result = (a >= b);
initial
begin
a = 0;
b = 0;
error = 0;
#5 ;
if( result !== 1\'b1)
error =1;
a = 1;
#5;
if( result !== 1\'b1)
error =1;
b = 1;
#5 ;
if( result !== 1\'b1)
error =1;
a = 1001;
b = 1002;
#5 ;
if( result !== 1\'b0)
error =1;
a = 1003;
#5 ;
if( result !== 1\'b1)
error =1;
if(error === 0)
\t $display("PASSED");
else
\t $display("FAILED");
end
endmodule
|
// Adapted from test case submitted by Geoff Blackman
module pr2276163();
function automatic integer f1;
input integer in;
f1 = in + 1;
endfunction
function integer f2;
input integer in;
f2 = in * 2;
endfunction
integer ret;
initial begin
ret = f1 ( f1 (1) );
if (ret !== 3) begin
$display("FAILED: expected 3, got %0d", ret);
$finish;
end
ret = f1 ( f2 (2) );
if (ret !== 5) begin
$display("FAILED: expected 5, got %0d", ret);
$finish;
end
ret = f2 ( f1 (3) );
if (ret !== 8) begin
$display("FAILED: expected 8, got %0d", ret);
$finish;
end
ret = f2 ( f2 (4) );
if (ret !== 16) begin
$display("FAILED: expected 16, got %0d", ret);
$finish;
end
$display("PASSED");
end
endmodule
|
module main;
localparam AMAX = 7;
localparam SHIFT = 4;
byte foo [AMAX:0];
byte unsigned foo_u [AMAX:0];
int idx;
initial begin
for (idx = 0 ; idx <= AMAX ; idx = idx+1) begin
\t foo[idx] = idx - SHIFT;
\t foo_u[idx] = idx;
end
for (idx = 0 ; idx <= AMAX ; idx = idx+1) begin
\t if (idx < SHIFT && foo[idx] > 0) begin
\t $display("FAIL -- foo[%0d] = %0d (not signed?)", idx, foo[idx]);
\t $finish;
\t end
\t if (foo[idx] != (idx-SHIFT)) begin
\t $display("FAIL -- foo[%0d] = %0d", idx, foo[idx]);
\t $finish;
\t end
\t if (foo_u[idx] != idx) begin
\t $display("FAIL -- foo_u[%0d] = %0d", idx, foo[idx]);
\t $finish;
\t end
end
$display("PASSED");
$finish;
end // initial begin
endmodule // main
|
// Copyright (c) 2016 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Unary minus operator test
module vhdl_unary_minus_test;
logic signed [7:0] data_in;
logic signed [7:0] data_out;
logic clk = 1\'b0;
vhdl_unary_minus dut(data_in, clk, data_out);
always #10 clk = ~clk;
initial begin
#5;
data_in = -12;
#20;
if(data_out !== 12) begin
$display("FAILED 1");
$finish();
end
data_in = 33;
#20;
if(data_out !== -33) begin
$display("FAILED 2");
$finish();
end
$display("PASSED");
$finish();
end
endmodule
|
module top();
reg [3:0] a;
reg [4:0] b;
wire [8:0] y;
functest uut(a, b, y);
initial begin
a = 3\'b101;
b = 4\'b0101;
#1;
if (y == 8\'b10100101)
$display("PASSED");
else
$display("FAILED y = %b", y);
end
endmodule // top
module functest (
operand_a,
operand_b,
result_y
);
input [3:0] operand_a;
input [4:0] operand_b;
output [8:0] result_y;
function [8:0] concat_this;
input [3:0] op_s;
input [4:0] op_l;
concat_this = {op_s, op_l};
endfunction
reg [8:0] result_y_wire;
always @ (operand_a or operand_b) begin
result_y_wire = concat_this(operand_a, operand_b);
end
assign result_y = result_y_wire;
endmodule
|
module top;
reg [24*8-1:0] str;
real rval;
reg [7:0] array [0:7];
reg [7:0] array2 [8:15];
reg [7:0] array3 [-1:7];
integer idx, istr;
task clear_array;
for (idx = 0; idx < 8; idx = idx + 1) begin
array[idx] = 0;
array2[idx+8] = 0;
end
endtask
initial begin
// An invalid string.
$readmemb(str, array);
$readmemb(istr, array);
// Check a valid string.
str = "ivltests/readmemb.txt";
$readmemb(str, array);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== idx + 1) begin
$display("Failed: for index %0d of readmemb 1, expected %0d, got %0d",
idx, idx+1, array[idx]);
end
end
// Check a string with a non-printing character.
str[7:0] = \'d2;
$readmemb(str, array);
// This should load, but will print a warning about the real.
rval = 0.0;
clear_array;
$readmemb("ivltests/readmemb.txt", array, rval);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== idx + 1) begin
$display("Failed: for index %0d of readmemb 2, expected %0d, got %0d",
idx, idx+1, array[idx]);
end
end
// This should load, but will print a warning about the real.
rval = 7.0;
clear_array;
$readmemb("ivltests/readmemb.txt", array, 0, rval);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== idx + 1) begin
$display("Failed: for index %0d of readmemb 3, expected %0d, got %0d",
idx, idx+1, array[idx]);
end
end
// These should not load the array.
clear_array;
$readmemb("ivltests/readmemb.txt", array, -1, 7);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== 0) begin
$display("Failed: for index %0d of readmemb 4, expected 0, got %0d",
idx, array[idx]);
end
end
$readmemb("ivltests/readmemb.txt", array2, 7, 15);
for (idx = 8; idx < 16; idx = idx + 1) begin
if (array2[idx] !== 0) begin
$display("Failed: for index %0d of readmemb 5, expected 0, got %0d",
idx, array2[idx]);
end
end
$readmemb("ivltests/readmemb.txt", array, 0, 8);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== 0) begin
$display("Failed: for index %0d of readmemb 6, expected 0, got %0d",
idx, array[idx]);
end
end
$readmemb("ivltests/readmemb.txt", array2, 8, 16);
for (idx = 8; idx < 16; idx = idx + 1) begin
if (array2[idx] !== 0) begin
$display("Failed: for index %0d of readmemb 7, expected 0, got %0d",
idx, array2[idx]);
end
end
// Check that a warning is printed if we have the wrong number of values.
clear_array;
$readmemb("ivltests/readmemb.txt", array, 0, 6);
for (idx = 0; idx < 7; idx = idx + 1) begin
if (array[idx] !== idx + 1) begin
$display("Failed: for index %0d of readmemb 8, expected %0d, got %0d",
idx, idx+1, array[idx]);
end
end
if (array[7] !== 0) begin
$display("Failed: for index 7 of readmemb 8, expected 0, got %0d",
array[7]);
end
$readmemb("ivltests/readmemb.txt", array3, -1, 7);
for (idx = -1; idx < 7; idx = idx + 1) begin
if ($signed(array3[idx]) !== idx + 2) begin
$display("Failed: for index %0d of readmemb 9, expected %0d, got %0d",
idx, idx+2, array3[idx]);
end
end
if (array3[7] !== 8\'bx) begin
$display("Failed: for index 7 of readmemb 9, expected \'dx, got %0d",
array3[7]);
end
// Check what an invalid token returns.
$readmemb("ivltests/readmem-error.txt", array);
// An invalid string.
str = \'bx;
$readmemh(str, array);
$readmemh(istr, array);
// Check a valid string.
str = "ivltests/readmemh.txt";
$readmemh(str, array);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== idx + 1) begin
$display("Failed: for index %0d of readmemh 1, expected %0d, got %0d",
idx, idx+1, array[idx]);
end
end
// Check a string with a non-printing character.
str[7:0] = \'d2;
$readmemh(str, array);
// This should load, but will print a warning about the real.
rval = 0.0;
clear_array;
$readmemh("ivltests/readmemh.txt", array, rval);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== idx + 1) begin
$display("Failed: for index %0d of readmemh 2, expected %0d, got %0d",
idx, idx+1, array[idx]);
end
end
// This should load, but will print a warning about the real.
rval = 7.0;
clear_array;
$readmemh("ivltests/readmemh.txt", array, 0, rval);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== idx + 1) begin
$display("Failed: for index %0d of readmemh 3, expected %0d, got %0d",
idx, idx+1, array[idx]);
end
end
// These should not load the array.
clear_array;
$readmemh("ivltests/readmemh.txt", array, -1, 7);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== 0) begin
$display("Failed: for index %0d of readmemh 4, expected 0, got %0d",
idx, array[idx]);
end
end
$readmemh("ivltests/readmemh.txt", array2, 7, 15);
for (idx = 8; idx < 16; idx = idx + 1) begin
if (array2[idx] !== 0) begin
$display("Failed: for index %0d of readmemh 5, expected 0, got %0d",
idx, array2[idx]);
end
end
$readmemh("ivltests/readmemh.txt", array, 0, 8);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== 0) begin
$display("Failed: for index %0d of readmemh 6, expected 0, got %0d",
idx, array[idx]);
end
end
$readmemh("ivltests/readmemh.txt", array2, 8, 16);
for (idx = 8; idx < 16; idx = idx + 1) begin
if (array2[idx] !== 0) begin
$display("Failed: for index %0d of readmemh 7, expected 0, got %0d",
idx, array2[idx]);
end
end
// Check that a warning is printed if we have the wrong number of values.
clear_array;
$readmemh("ivltests/readmemh.txt", array, 0, 6);
for (idx = 0; idx < 7; idx = idx + 1) begin
if (array[idx] !== idx + 1) begin
$display("Failed: for index %0d of readmemh 8, expected %0d, got %0d",
idx, idx+1, array[idx]);
end
end
if (array[7] !== 0) begin
$display("Failed: for index 7 of readmemh 8, expected 0, got %0d",
array[7]);
end
$readmemh("ivltests/readmemh.txt", array3, -1, 7);
for (idx = -1; idx < 7; idx = idx + 1) begin
if ($signed(array3[idx]) !== idx + 2) begin
$display("Failed: for index %0d of readmemh 9, expected %0d, got %0d",
idx, idx+2, array3[idx]);
end
end
if (array3[7] !== 8\'bx) begin
$display("Failed: for index 7 of readmemh 9, expected \'dx, got %0d",
array3[7]);
end
// Check what an invalid token returns.
$readmemh("ivltests/readmem-error.txt", array);
end
endmodule
|
module top;
reg pass = 1\'b1;
wire real rval;
real in;
assign rval = in + 2;
initial begin
// $monitor(rval,, in);
in = 0;
#1 in = 1;
#1 in = 2;
#1 if (pass) $display("PASSED");
end
always @(rval) begin
if (rval != in + 2.0) begin
$display("FAILED: expected %f, got %f", in + 2.0, rval);
pass = 1\'b0;
end
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
//
// SDW: Instantiation of Modules:
//
// D: Instantiate two versions of a module containing a single
// D: resetable f/f. Reset both - then feed 1 module with a clock
// D: and validate that the output toggles. Feed the 2nd module
// D: with a clock and validate that the 2nd output toggles.
//
//
module test_mod (reset,clka,out);
input reset;
input clka;
output out;
reg out;
always @(posedge clka or posedge reset)
if(reset)
out = 0;
else
begin
out = ~out;
$display("saw a clk at %d, out is %b\
",$time,out);
end
endmodule
module main();
reg reset,clk_0,clk_1;
wire out_0,out_1;
test_mod module_1 (reset,clk_0,out_0);
test_mod module_2 (reset,clk_1,out_1);
initial
begin
clk_0 = 0;
clk_1 = 0;
#1 reset = 1;
# 2;
$display("time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\
",$time,reset,clk_0,
clk_1,out_0,out_1);
// Validate that both out_0 and out_1 are reset
if(out_0)
begin
$display("FAILED - out_0 not reset\
");
$finish ;
end
if(out_1)
begin
$display("FAILED - out_1 not reset\
");
$finish ;
end
reset = 0;
$display("time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\
",$time,reset,clk_0,
clk_1,out_0,out_1);
# 2;
clk_0 = 1;
# 2; // Wait so we don\'t worry about races.
$display("time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\
",$time,reset,clk_0,
clk_1,out_0,out_1);
if(!out_0)
begin
$display("FAILED - out_0 didn\'t set on clk_0\
");
$finish ;
end
if(out_1)
begin
$display("FAILED - out_1 set on wrong clk!\
");
$finish ;
end
clk_1 = 1;
# 2; // Wait so we don\'t worry about races.
$display("time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\
",$time,reset,clk_0,
clk_1,out_0,out_1);
if(!out_1)
begin
$display("FAILED - out_1 didn\'t set on clk_1\
");
$finish ;
end
if(!out_0)
begin
$display("FAILED - out_0 changed due to clk_0\
");
$finish ;
end
$display("PASSED\
");
$finish ;
end
endmodule
|
task start;
top.dut.signal = 1;
endtask
module dut();
logic signal = 0;
initial begin
$display(signal);
@(signal);
$display(signal);
if (signal === 1)
$display("PASSED");
else
$display("FAILED");
$finish;
end
endmodule
module top();
initial begin
#1 start();
end
dut dut();
endmodule
|
module check (input unsigned [103:0] a, b, c);
wire [103:0] int_AB;
assign int_AB = ~(a | b);
always @(a, b, int_AB, c) begin
#1;
if (int_AB !== c) begin
$display("ERROR");
$finish;
end
end
endmodule
module stimulus (output reg unsigned [103:0] A, B);
parameter S = 2000;
int unsigned i;
initial begin
A = 0; B= 0;
// values with 0, 1
for (i=0; i<S; i=i+1) begin
#1 A[103:8] = {$random, $random, $random};
\t\t A[7:0] = $random % 256;
B[103:8] = {$random, $random, $random};
\t B[7:0] = $random % 256;
end
// values with x, z
for (i=0; i<S; i=i+1) begin
#1;
A[103:8] = {$random, $random, $random};
\t A[7:0] = $random % 256;
B[103:8] = {$random, $random, $random};
\t B[7:0] = $random % 256;
A[103:72] = xz_inject (A[103:72]);
A[71:40] = xz_inject (A[71:40]);
B[71:40] = xz_inject (B[71:40]);
B[39:8] = xz_inject (B[39:8]);
end
end
// injects some x, z values on 32 bits arguments
function [31:0] xz_inject (input unsigned [31:0] value);
integer i, temp;
begin
temp = {$random};
for (i=0; i<32; i=i+1)
begin
if (temp[i] == 1\'b1)
begin
temp = $random;
if (temp <= 0)
value[i] = 1\'bx; // \'x noise
else
value[i] = 1\'bz; // \'z noise
end
end
xz_inject = value;
end
endfunction
endmodule
module test;
wire unsigned [103:0] a, b;
wire unsigned [103:0] r;
stimulus stim (.A(a), .B(b));
nor104 duv (.a_i(a), .b_i(b), .c_o(r) );
check check (.a(a), .b(b), .c(r) );
initial begin
#120000;
$display("PASSED");
$finish;
end
endmodule
|
`timescale 1ns/1ns
module sum_test;
reg clk;
wire [10:0] s;
initial begin
clk = 0;
forever #10 clk = ~clk;
end
sum #(5, 8) sum (clk, {8\'d10,8\'d20,8\'d30,8\'d40,8\'d50}, s);
initial begin
$display("Starting...");
repeat (50) @(posedge clk);
$display("sum = %d",s);
if (s !== 150)
$display("FAILED: expected 150, received %0d",s);
else
$display("PASSED");
$finish;
end
endmodule
module sum
#(
parameter n = 4,
parameter width = 8,
parameter log_n = $clog2(n)
)
(
input clk,
input [n*width-1:0]addends,
output reg [log_n+width-1:0] s
);
generate
if (n==1)
always @(*) s = addends;
else begin
wire [$clog2(n/2)+width-1:0] a1;
wire [$clog2(n-n/2)+width-1:0] a2;
sum #(n/2, width) s0 (clk, addends[(n/2)*width-1:0], a1);
sum #(n-n/2, width) s1 (clk, addends[n*width-1:(n/2)*width], a2);
always @(posedge clk) s <= a1 + a2;
end
endgenerate
endmodule // sum
|
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