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/*
* Copyright (c) 2000 Stephan I. Boettcher <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// compile time test for nested task scope elaboration
`define TEST
module nest(r);
output [7:0] r;
reg [7:0] r;
task incr;
input [7:0] a;
begin
\t r <= r+a;
\t #1 $display("R=%b",r);
end
endtask
endmodule
module test;
wire [7:0] acc;
nest n(acc);
initial n.r <= 0;
`ifdef TEST
task increment;
begin
\t n.incr(1);
end
endtask
`endif
initial
begin
`ifdef TEST
\t#10 increment;
\t#10 increment;
\t#10 increment;
`else
\t#10 n.incr(3);
`endif
\t#10;
\tif (acc==3)
\t $display("PASSED");
\telse
\t $display("FAILED");
end
endmodule
|
module stimulus (output reg A, B);
reg unsigned [1:0] stimulus_count = 2\'b0;
initial begin
{A, B} = 2\'b00;
#10 {A, B} = 2\'b01;
#10 {A, B} = 2\'b10;
#10 {A, B} = 2\'b11;
end
endmodule
module scoreboard (input Y, A, B);
reg [3:0] truth_table;
reg Y_s;
initial begin
truth_table[\'b00] = 0;
truth_table[\'b01] = 0;
truth_table[\'b10] = 0;
truth_table[\'b11] = 1;
end
always @(A or B) begin
Y_s = truth_table[{A,B}];
#1;
//$display ("a = %b, b = %b, Y_s = %b, Y = %b", A, B, Y_s, Y);
if (Y_s !== Y) begin
$display("FAILED! - mismatch found for inputs %b and %b", A, B);
$finish;
end
end
endmodule
module test;
stimulus stim (A, B);
and_gate duv (.a_i(A), .b_i(B), .c_o(Y) );
scoreboard mon (Y, A, B);
initial begin
#100 $display("PASSED");
$finish;
end
endmodule
|
// Tests that the signedness for struct members is handled correctly
module test;
struct packed {
logic [15:0] x;
logic signed [15:0] y;
} s;
bit failed = 1\'b0;
`define check(x) \\
if (!(x)) begin \\
$display("FAILED: ", `"x`"); \\
failed = 1\'b1; \\
end
initial begin
s.x = -1;
s.y = -1;
`check(!$is_signed(s.x));
`check($is_signed(s.y));
// These evaluate as signed
`check($signed(s.x) < 0);
`check(s.y < 0);
// These all evaluate as unsigned
`check(s.x > 0);
`check(s.y[15:0] > 0)
`check({s.y} > 0)
`check($unsigned(s.y) > 0)
`check(s.y > 16\'h0)
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
/*
* This is derived from PR#938 in the test suite.
*/
`timescale 1ns/100ps
module test;
wire out;
reg A, B, select;
prim_mux2 mux (out, B, A, select);
reg [3:0] cnt;
initial begin
$display("A B S out");
for (cnt = 0 ; cnt <= \'b0111 ; cnt = cnt + 1) begin
\t A <= cnt[0];
\t B <= cnt[1];
\t select <= cnt[2];
\t #1 $display("%b %b %b --> %b", A, B, select, out);
end
end
endmodule
primitive prim_mux2( output out, input in1, input in0, input select);
table
//in1 in0 select : out
0 0 1 : 0;
1 1 ? : 1;
0 ? 1 : 0;
1 ? 1 : 1;
? 0 0 : 0;
? 1 0 : 1;
endtable
endprimitive
|
module dff();
reg clk;
reg rst;
reg ce;
reg [3:0] d;
reg [3:0] q;
always @(negedge clk or posedge rst) begin
if (rst)
q <= 4\'b1001;
else if (ce)
q <= d;
end
(* ivl_synthesis_off *)
reg failed = 0;
initial begin
$monitor("%b %b %b %b", rst, clk, d, q);
clk = 1\'b0;
ce = 1\'b0;
rst = 1\'b0;
d = 4\'b0110;
#1;
if (q !== 4\'bxxxx) failed = 1;
rst = 1\'b1;
#1;
if (q !== 4\'b1001) failed = 1;
clk = 1\'b1;
#1;
if (q !== 4\'b1001) failed = 1;
clk = 1\'b0;
#1;
if (q !== 4\'b1001) failed = 1;
rst = 1\'b0;
#1;
if (q !== 4\'b1001) failed = 1;
clk = 1\'b1;
#1;
if (q !== 4\'b1001) failed = 1;
clk = 1\'b0;
#1;
if (q !== 4\'b1001) failed = 1;
ce = 1\'b1;
#1;
if (q !== 4\'b1001) failed = 1;
clk = 1\'b1;
#1;
if (q !== 4\'b1001) failed = 1;
clk = 1\'b0;
#1;
if (q !== 4\'b0110) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule // dff
|
module top;
reg [63:0] str;
reg [31:0] in, ck, out;
integer res;
initial begin
// To avoid embedded NULL bytes each byte must have a 1.
in = 32\'b000x100z_001z000x_101xxxzz_100z111x;
ck = 32\'b00001000_00100000_10100000_10001110;
$sformat(str, "%u", in);
res = $sscanf(str, "%u", out);
if (res !== 1) $display("FAILED: $sscanf() returned %d", res);
else if (ck !== out) $display("FAILED: %b !== %b", in, out);
else $display("PASSED");
end
endmodule
|
// Check that passing a data type to $bits works as expected
module test;
bit failed = 1\'b0;
`define check(type, value) \\
if ($bits(type) !== value) begin \\
$display("FAILED: $bits(", `"type`", ") is %0d", $bits(type), " expected %0d", value); \\
failed = 1\'b1; \\
end
typedef int T1;
typedef int T2[3:0];
initial begin
`check(reg, 1);
`check(logic, 1);
`check(bit, 1);
`check(logic [3:0], 4);
`check(byte, 8);
`check(shortint, 16);
`check(int, 32);
`check(longint, 64);
`check(struct packed { int x; shortint y; }, 32 + 16);
`check(T1, 32);
`check(T2, 4 * 32);
if (failed == 1\'b0) begin
$display("PASSED");
end
end
endmodule
|
// Check that shortreal module ports are supported
module M (
input shortreal in,
output shortreal out
);
assign out = in * 10.1;
endmodule
module test;
shortreal r;
M m (
.in (1.23),
.out (r)
);
initial begin
#1
if (r == 12.423) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
|
module test();
wire [7:0] value1;
wire [7:0] value2;
assign value1[3:0] = 4\'d2;
cmos buffer[7:0](value2, value1, 1\'b1, 1\'b0);
initial begin
#2 $display("%b %b", value1, value2);
if (value2 === 8\'bzzzz0010)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
// Regression test for GitHub issue 9 : Efficiency of verinum and vpp_net
// pow() functions.
module bug();
reg [5:0] ra;
reg [5:0] ry;
wire [5:0] wa = 3;
wire [5:0] wy = wa ** 123456789;
localparam [5:0] pa = 3;
localparam [5:0] py = pa ** 123456789;
reg failed = 0;
initial begin
#0;
ra = 3;
ry = ra ** 123456789;
$display("%b", ry);
if (ry !== 6\'b110011) failed = 1;
$display("%b", wy);
if (wy !== 6\'b110011) failed = 1;
$display("%b", py);
if (py !== 6\'b110011) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module test(input wire load, in,
\t output reg out1, out2);
(* ivl_combinational *)
always @* begin
out1 = 0;
if (load) begin
\t out1 = in;
\t out2 = in;
end else begin
\t out2 = ~in;
end
end
endmodule // test
module test_bench;
reg load;
reg val;
wire out1, out2;
test DUT(.load(load), .in(val), .out1(out1), .out2(out2));
(* ivl_synthesis_off *)
initial begin
val = 0;
load = 1;
#1 ;
if (out1 !== 0 || out2 !== 0) begin
\t $display("FAILED -- load=%b, val=%b, out1=%b, out2=%b", load, val, out1, out2);
\t $finish;
end
val = 1;
#1 ;
if (out1 !== 1 || out2 !== 1) begin
\t $display("FAILED -- load=%b, val=%b, out1=%b, out2=%b", load, val, out1, out2);
\t $finish;
end
load = 0;
#1 ;
if (out1 !== 0 || out2 !== 0) begin
\t $display("FAILED -- load=%b, val=%b, out1=%b, out2=%b", load, val, out1, out2);
\t $finish;
end
val = 0;
#1 ;
if (out1 !== 0 || out2 !== 1) begin
\t $display("FAILED -- load=%b, val=%b, out1=%b, out2=%b", load, val, out1, out2);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule // test_bench
|
module top;
reg pass = 1\'b0;
integer lp;
reg [7:0] ival = 8\'b0;
initial begin
/* If `ival\' is replaced by a literal `0\' this works... */
for(lp = ival; lp < 5; lp = lp + 1) begin
pass = 1\'b1;
end
if(pass) $display("PASSED");
else $display("FAILED");
end
endmodule
|
module top;
reg result;
initial begin
result = $onehot(top);
result = $onehot("a string");
result = $onehot(4\'b001, 1\'b0);
end
endmodule
|
module sub_module();
parameter Value1 = 0;
endmodule
module top_module();
integer Value2;
sub_module sub_module();
defparam sub_module.Value1 = Value2;
endmodule
|
module test;
parameter bar = 8;
localparam foo = 2**bar;
initial begin
if (foo != \'h100) begin
\t $display("FAILED -- foo = %h", foo);
\t $finish;
end
$display("PASSED");
end
endmodule
|
// Check that it is possible to reference a package scoped type identifier in an
// expression, even if there is a non type identifier of the same name in the
// current scope.
bit failed = 1\'b0;
`define check(expr, val) \\
if (expr !== val) begin \\
$display("FAILED: %s, expected %0d, got %0d", `"expr`", val, expr); \\
failed = 1\'b1; \\
end
package P;
typedef integer T;
endpackage
module test;
integer T;
initial begin
`check($bits(P::T), $bits(integer))
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
// Check that declarations for unpacked arrays of queues are supported.
module test;
// Unpacked array of queues
int q[$][10];
endmodule
|
module m;
reg [15:0] x,y;
initial
begin
y = 0;
x <= 0;
x <= 1;
x <= 2;
x <= 3;
x <= 4;
x <= 5;
x <= 6; // Only this should cause an event, so y should become 1.
#10
$display("x = %d (expect 6)", x);
$display("y = %d (expect 1)", y);
if (x !== 16\'d6) begin
$display("FAILED");
$finish;
end
if (y !== 16\'d1) begin
$display("FAILED");
$finish;
end
$display("PASSED");
$finish;
end
always @(x[0])
y <= y + 1;
endmodule
|
//
// Copyright (c) 1999 Peter Monta ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module main;
wire a;
assign a = 1;
initial begin
#1;
if (a===1\'b1)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
module test;
reg [63:0] i, j;
initial
main;
task main;
integer k, l, m, n;
begin
i = 64\'hffff_ffff_ffff_ffff;
j = 64\'hffff_ffff_ffff_fffe;
k = $signed(i) < $signed(j);
l = $signed(i) <= $signed(j);
m = $signed(i) > $signed(j);
n = $signed(i) >= $signed(j);
$display("< : %s", k? "Y":"N");
$display("<=: %s", l? "Y":"N");
$display("> : %s", m? "Y":"N");
$display(">=: %s", n? "Y":"N");
end
endtask
endmodule
|
// Test constant functions.
module main;
localparam BYTESIZE = 8;
localparam STRLEN = 4;
function [STRLEN*BYTESIZE - 1 : 0] bits2text;
input [STRLEN-1:0] use_map;
integer\t\t idx;
begin
\t bits2text = 0;
\t for (idx = 0 ; idx < STRLEN ; idx = idx+1) begin
\t bits2text[(idx*BYTESIZE) +: BYTESIZE] = (use_map[idx] == 1\'b0)? "1" : "0";
\t end
end
endfunction
localparam [STRLEN*BYTESIZE - 1 : 0] str0010 = bits2text(4\'b0010);
localparam [STRLEN*BYTESIZE - 1 : 0] str0100 = bits2text(4\'b0100);
localparam [STRLEN*BYTESIZE - 1 : 0] str0011 = bits2text(4\'b0011);
localparam [STRLEN*BYTESIZE - 1 : 0] str1100 = bits2text(4\'b1100);
reg [STRLEN*BYTESIZE - 1 : 0] tmp;
initial begin
tmp = bits2text(4\'b0010);
if (tmp !== str0010) begin
\t $display("FAILED -- str0010=%h, expect %h", str0010, tmp);
\t $finish;
end
tmp = bits2text(4\'b0100);
if (tmp !== str0100) begin
\t $display("FAILED -- str0100=%h, expect %h", str0100, tmp);
\t $finish;
end
tmp = bits2text(4\'b0011);
if (tmp !== str0011) begin
\t $display("FAILED -- str0011=%h, expect %h", str0011, tmp);
\t $finish;
end
tmp = bits2text(4\'b1100);
if (tmp !== str1100) begin
\t $display("FAILED -- str1100=%h, expect %h", str1100, tmp);
\t $finish;
end
$display("PASSED");
$finish;
end
endmodule // main
|
/* Copyright (C) 2000 Stephen G. Tell
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this software; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
* Boston, MA 02111-1307 USA
*/
/* fdisplay2 - test $fopen and $fdisplay system tasks */
module fdisplay2;
integer fp, dfp;
reg [7:0] a;
initial begin
fp = $fopen("work/fdisplay2.out");
if(fp != 2 && fp != 4 && fp != 8 && fp != 16 && fp != 32 && fp != 64)
begin
\t $display("FAILED fopen fp=%d", fp);
\t $finish;
end
$fwrite(fp, "hello, world\
");
a = 8\'hac;
//$fdisplay(1|fp, "a = %h; x: %b\
", a, a^8\'h0f);
dfp = 1|fp;
$fdisplay(dfp, "a = \'h%h = \'b%b", a, a);
$finish;
end // initial begin
endmodule
|
/*
* Verify that the continuous assignments support a delay that is
* greater than 32 bits. The top delays are in seconds and the other
* delays are in ps. The second delays all require more than 32 bits
* to work correctly. They will use the /d version.
*/
`timescale 1s/1s
module gt32b;
wire real rlval;
wire rval;
wire aval[1:0];
wire [7:0] psval;
assign #1 rlval = 1.0;
assign #2 rval = 1\'b1;
assign #3 aval[0] = 1\'b0;
assign #4 psval[1] = 1\'b1;
initial begin
$timeformat(-12, 0, " ps", 16);
#1;
$display("dl:gt32b- %t", $realtime);
end
always @(rlval) begin
$display("rl:gt32b- %t", $realtime);
end
always @(rval) begin
$display("rg:gt32b- %t", $realtime);
end
always @(aval[0]) begin
$display("ar:gt32b- %t", $realtime);
end
always @(psval) begin
$display("ps:gt32b- %t", $realtime);
end
endmodule
`timescale 1ps/1ps
module ls32b;
wire real rlval;
wire rval;
wire aval[1:0];
wire [7:0] psval;
assign #1 rlval = 1.0;
assign #2 rval = 1\'b1;
assign #3 aval[0] = 1\'b0;
assign #4 psval[1] = 1\'b1;
initial begin
#1;
$display("dl:ls32b- %t", $realtime);
end
always @(rlval) begin
$display("rl:ls32b- %t", $realtime);
end
always @(rval) begin
$display("rg:ls32b- %t", $realtime);
end
always @(aval[0]) begin
$display("ar:ls32b- %t", $realtime);
end
always @(psval) begin
$display("ps:ls32b- %t", $realtime);
end
endmodule
|
module test;
localparam NOM_COUNT = 1000;
localparam MIN_COUNT = NOM_COUNT - 200;
localparam MAX_COUNT = NOM_COUNT + 200;
integer histogram[255:0];
integer i;
reg [7:0] value;
reg failed;
initial begin
failed = 0;
for (i = 0; i < 256; i++) begin
histogram[i] = 0;
end
for (i = 0; i < 256*NOM_COUNT; i = i + 1) begin
value = $urandom_range(32\'hffffffff, 32\'h0) >> 24;
histogram[value] += 1;
end
for (i = 0; i < 256; i++) begin
if (histogram[i] < MIN_COUNT) begin
$display("Bin %3d count %0d", i, histogram[i]);
failed = 1;
end
if (histogram[i] > MAX_COUNT) begin
$display("Bin %3d count %0d", i, histogram[i]);
failed = 1;
end
end
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module top;
string q_tst [$];
string q_tmp [$];
string elem;
integer idx;
bit passed;
task automatic check_size(integer size,
string fname,
integer lineno);
if (q_tst.size !== size) begin
$display("%s:%0d: Failed: queue initial size != %0d (%0d)",
fname, lineno, size, q_tst.size);
passed = 1\'b0;
end
endtask
task automatic check_idx_value(integer idx,
string expected,
string fname,
integer lineno);
if (q_tst[idx] != expected) begin
$display("%s:%0d: Failed: element [%0d] != \'%s\' (\'%s\')",
fname, lineno, idx, expected, q_tst[idx]);
passed = 1\'b0;
end
endtask
initial begin
passed = 1\'b1;
q_tst.delete(0); // Warning: skip delete on an empty queue
check_size(0, `__FILE__, `__LINE__);
check_idx_value(0, "", `__FILE__, `__LINE__);
elem = q_tst.pop_front(); // Warning: cannot pop_front() an empty queue
if (elem != "") begin
$display("Failed: pop_front() != \'\' (\'%s\')", elem);
passed = 1\'b0;
end
elem = q_tst.pop_back(); // Warning: cannot pop_back() an empty queue
if (elem != "") begin
$display("Failed: pop_back() != \'\' (\'%s\')", elem);
passed = 1\'b0;
end
q_tst.push_back("World");
q_tst.push_front("Hello");
q_tst.push_back("!");
q_tst.push_back("This should get deleted");
q_tst.delete(3);
q_tst.delete(3); // Warning: skip an out of range delete()
q_tst.delete(-1); // Warning: skip delete with negative index
q_tst.delete(\'X); // Warning: skip delete with undefined index
check_size(3, `__FILE__, `__LINE__);
if (q_tst[0] != "Hello") begin
$display("Failed: element [0] != \'Hello\' (\'%s\')", q_tst[0]);
passed = 1\'b0;
end
if (q_tst[1] != "World") begin
$display("Failed: element [1] != \'World\' (\'%s\')", q_tst[1]);
passed = 1\'b0;
end
if (q_tst[2] != "!") begin
$display("Failed: element [2] != \'!\' (\'%s\')", q_tst[2]);
passed = 1\'b0;
end
if (q_tst[3] != "") begin
$display("Failed: element [3] != \'\' (\'%s\')", q_tst[3]);
passed = 1\'b0;
end
if (q_tst[-1] != "") begin
$display("Failed: element [-1] != \'\' (\'%s\')", q_tst[-1]);
passed = 1\'b0;
end
if (q_tst[\'X] != "") begin
$display("Failed: element [\'X] != \'\' (\'%s\')", q_tst[\'X]);
passed = 1\'b0;
end
check_idx_value(-1, "", `__FILE__, `__LINE__);
check_idx_value(\'X, "", `__FILE__, `__LINE__);
elem = q_tst.pop_front();
if (elem != "Hello") begin
$display("Failed: element pop_front() != \'Hello\' (\'%s\')", elem);
passed = 1\'b0;
end
elem = q_tst.pop_back();
if (elem != "!") begin
$display("Failed: element pop_back() != \'!\' (\'%s\')", elem);
passed = 1\'b0;
end
check_size(1, `__FILE__, `__LINE__);
if ((q_tst[0] != q_tst[$]) || (q_tst[0] != "World")) begin
$display("Failed: q_tst[0](\'%s\') != q_tst[$](\'%s\') != \'World\'",
q_tst[0], q_tst[$]);
passed = 1\'b0;
end
q_tst.delete();
check_size(0, `__FILE__, `__LINE__);
q_tst.push_front("hello");
q_tst.push_front("Will be removed");
q_tst.push_back("Will also be removed");
elem = q_tst.pop_back;
elem = q_tst.pop_front;
check_size(1, `__FILE__, `__LINE__);
check_idx_value(0, "hello", `__FILE__, `__LINE__);
q_tst[0] = "Hello";
q_tst[1] = "world";
q_tst[1] = "World";
q_tst[2] = "!";
q_tst[-1] = "Will not write"; // Warning: will not be added (negative index)
q_tst[\'X] = "Will not write"; // Warning: will not be added (undefined index)
q_tst[4] = "Will not write"; // Warning: will not be added (out of range index)
idx = -1;
q_tst[idx] = "Will not write"; // Warning: will not be added (negative index)
idx = 3\'b0x1;
q_tst[idx] = "Will not write"; // Warning: will not be added (undefined index)
idx = 4;
q_tst[idx] = "Will not write"; // Warning: will not be added (out of range index)
check_size(3, `__FILE__, `__LINE__);
check_idx_value(0, "Hello", `__FILE__, `__LINE__);
check_idx_value(1, "World", `__FILE__, `__LINE__);
check_idx_value(2, "!", `__FILE__, `__LINE__);
q_tst.delete();
q_tst[0] = "World";
q_tst.insert(1, "Again");
q_tst.insert(0, "Hello");
q_tst.insert(2, "!");
q_tst.insert(-1, "Will not be added"); // Warning: will not be added (negative index)
q_tst.insert(\'X, "Will not be added"); // Warning: will not be added (undefined index)
q_tst.insert(5, "Will not be added"); // Warning: will not be added (out of range index)
check_size(4, `__FILE__, `__LINE__);
check_idx_value(0, "Hello", `__FILE__, `__LINE__);
check_idx_value(1, "World", `__FILE__, `__LINE__);
check_idx_value(2, "!", `__FILE__, `__LINE__);
check_idx_value(3, "Again", `__FILE__, `__LINE__);
q_tst = \'{"!", "World", "Hello"};
check_size(3, `__FILE__, `__LINE__);
check_idx_value(0, "!", `__FILE__, `__LINE__);
check_idx_value(1, "World", `__FILE__, `__LINE__);
check_idx_value(2, "Hello", `__FILE__, `__LINE__);
q_tmp = \'{"Hello", "World"};
q_tst = q_tmp;
q_tmp[0] = "Goodbye";
q_tmp[2] = "Not seen";
check_size(2, `__FILE__, `__LINE__);
check_idx_value(0, "Hello", `__FILE__, `__LINE__);
check_idx_value(1, "World", `__FILE__, `__LINE__);
q_tst[2] = "Added, but removed";
check_size(3, `__FILE__, `__LINE__);
check_idx_value(2, "Added, but removed", `__FILE__, `__LINE__);
q_tst = {"Hello", "World"};
check_size(2, `__FILE__, `__LINE__);
check_idx_value(0, "Hello", `__FILE__, `__LINE__);
check_idx_value(1, "World", `__FILE__, `__LINE__);
q_tst = \'{};
check_size(0, `__FILE__, `__LINE__);
if (passed) $display("PASSED");
end
endmodule : top
|
module testbench();
reg [3:0] a, b;
initial begin
a = 1;
b = 2;
#1;
a = a + b;
b = a + b;
if (a !== 3)
begin
$display("FAILED -- a !== 3");
$finish;
end
if (b !== 5)
begin
$display("FAILED -- b !== 5");
$finish;
end
#2;
$display("PASSED");
end // initial begin
initial begin
#2;
if (a !== 3)
begin
$display("FAILED -- a (signal) !== 3");
$finish;
end
if (b !== 5)
begin
$display("FAILED -- b (signal) !== 5");
$finish;
end
end
endmodule // testbench
|
// Check that it is possible to call a class task without parenthesis after the
// task name when using the implicit `this` class handle.
module test;
class C;
task a;
$display("PASSED");
endtask
task b;
this.a;
endtask
endclass
C c = new;
initial begin
c.b;
end
endmodule
|
module top;
wire res, ler0, ler1, ler2, ler3;
wire [1:0] lew, lews;
real rval1, rval2;
reg val1, val2;
reg [3:0] wval1, wval2;
reg pass;
assign res = val1 <-> val2;
assign lew = wval1 <-> wval2;
assign lews = $signed(wval1 <-> wval2);
assign ler0 = rval1 <-> val2;
assign ler1 = val1 <-> rval2;
assign ler2 = rval1 <-> val2;
assign ler3 = rval1 <-> rval2;
initial begin
pass = 1\'b1;
val1 = 1\'b0;
val2 = 1\'b0;
#1;
if (res !== 1\'b1) begin
$display("FAILED: 1\'b0 <-> 1\'b0 returned %b not 1\'b1", res);
pass = 1\'b0;
end
val2 = 1\'b1;
#1;
if (res !== 1\'b0) begin
$display("FAILED: 1\'b0 <-> 1\'b1 returned %b not 1\'b0", res);
pass = 1\'b0;
end
val2 = 1\'bx;
#1;
if (res !== 1\'bx) begin
$display("FAILED: 1\'b0 <-> 1\'bx returned %b not 1\'bx", res);
pass = 1\'b0;
end
val2 = 1\'bz;
#1;
if (res !== 1\'bx) begin
$display("FAILED: 1\'b0 <-> 1\'bz returned %b not 1\'bx", res);
pass = 1\'b0;
end
val1 = 1\'b1;
val2 = 1\'b0;
#1;
if (res !== 1\'b0) begin
$display("FAILED: 1\'b1 <-> 1\'b0 returned %b not 1\'b0", res);
pass = 1\'b0;
end
val2 = 1\'b1;
#1;
if (res !== 1\'b1) begin
$display("FAILED: 1\'b1 <-> 1\'b1 returned %b not 1\'b1", res);
pass = 1\'b0;
end
val2 = 1\'bx;
#1;
if (res !== 1\'bx) begin
$display("FAILED: 1\'b1 <-> 1\'bx returned %b not 1\'bx", res);
pass = 1\'b0;
end
val2 = 1\'bz;
#1;
if (res !== 1\'bx) begin
$display("FAILED: 1\'b1 <-> 1\'bz returned %b not 1\'bx", res);
pass = 1\'b0;
end
val1 = 1\'bx;
val2 = 1\'b0;
#1;
if (res !== 1\'bx) begin
$display("FAILED: 1\'bx <-> 1\'b0 returned %b not 1\'bx", res);
pass = 1\'b0;
end
val2 = 1\'b1;
#1;
if (res !== 1\'bx) begin
$display("FAILED: 1\'bx <-> 1\'b1 returned %b not 1\'bx", res);
pass = 1\'b0;
end
val2 = 1\'bx;
#1;
if (res !== 1\'bx) begin
$display("FAILED: 1\'bx <-> 1\'bx returned %b not 1\'bx", res);
pass = 1\'b0;
end
val2 = 1\'bz;
#1;
if (res !== 1\'bx) begin
$display("FAILED: 1\'bx <-> 1\'bz returned %b not 1\'bx", res);
pass = 1\'b0;
end
val1 = 1\'bz;
val2 = 1\'b0;
#1;
if (res !== 1\'bx) begin
$display("FAILED: 1\'bz <-> 1\'b0 returned %b not 1\'bx", res);
pass = 1\'b0;
end
val2 = 1\'b1;
#1;
if (res !== 1\'bx) begin
$display("FAILED: 1\'bz <-> 1\'b1 returned %b not 1\'bx", res);
pass = 1\'b0;
end
val2 = 1\'bx;
#1;
if (res !== 1\'bx) begin
$display("FAILED: 1\'bz <-> 1\'bx returned %b not 1\'bx", res);
pass = 1\'b0;
end
val2 = 1\'bz;
#1;
if (res !== 1\'bx) begin
$display("FAILED: 1\'bz <-> 1\'bz returned %b not 1\'bx", res);
pass = 1\'b0;
end
rval1 = 0.0;
val2 = 1\'b0;
#1;
if (ler0 !== 1\'b1) begin
$display("FAILED: 0.0 <-> 1\'b0 returned %b not 1\'b1", ler0);
pass = 1\'b0;
end
val1 = 1\'b0;
rval2 = 2.0;
#1;
if (ler1 !== 1\'b0) begin
$display("FAILED: 1\'b0 <-> 2.0 returned %b not 1\'b0", ler1);
pass = 1\'b0;
end
rval1 = 2.0;
val2 = 1\'bx;
#1;
if (ler2 !== 1\'bx) begin
$display("FAILED: 2.0 <-> 1\'bx returned %b not 1\'bx", ler2);
pass = 1\'b0;
end
rval1 = -5.0;
rval2 = 2.0;
#1;
if (ler3 !== 1\'b1) begin
$display("FAILED: -5.0 <-> -2.0 returned %b not 1\'b1", ler3);
pass = 1\'b0;
end
wval1 = 4\'b0110;
wval2 = 4\'b1001;
#1;
if (lew !== 2\'b01) begin
$display("FAILED: 4\'b0110 <-> 4\'b1001 returned %b not 2\'b01", lew);
pass = 1\'b0;
end
if (lews !== 2\'b11) begin
$display("FAILED: 4\'b0110 <-> 4\'b1001 returned %b not 2\'b11", lews);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
/*
* Basics tests of continuous assignment.
*/
module testbench();
reg [3:0] a, b;
integer c, d;
wire [3:0] x, y, z;
assign x = a + b + b;
assign y = b - a;
assign z = a + (a * b);
initial begin
a <= 4\'h2;
b <= 4\'h3;
#1;
if (x !== 4\'h8)
begin
$display("FAILED -- 2 + 3 + 3 !== 8");
$finish;
end
if (y !== 4\'h1)
begin
$display("FAILED -- 3 - 2 !== 1");
$finish;
end
if (z !== 4\'h8)
begin
$display("FAILED -- 2 + (2 * 3) !== 8");
$finish;
end
$display("PASSED");
end
endmodule // testbench
|
// Check assignment operations in constant functions.
module constfunc7();
function real i_to_r(input signed [3:0] value);
i_to_r = value + 0.5;
endfunction
function signed [3:0] r_to_i(input real value);
r_to_i = value;
endfunction
function real u_to_r(input [3:0] value);
u_to_r = value + 0.5;
endfunction
function [3:0] r_to_u(input real value);
r_to_u = value;
endfunction
function [3:0] i_to_u(input signed [3:0] value);
i_to_u = value;
endfunction
function signed [3:0] u_to_i(input [3:0] value);
u_to_i = value;
endfunction
function [5:0] si_to_lu(input signed [3:0] value);
si_to_lu = value;
endfunction
function signed [5:0] su_to_li(input [3:0] value);
su_to_li = value;
endfunction
function [3:0] li_to_su(input signed [5:0] value);
li_to_su = value;
endfunction
function signed [3:0] lu_to_si(input [5:0] value);
lu_to_si = value;
endfunction
localparam i_to_r_res1 = i_to_r(-9);
localparam i_to_r_res2 = i_to_r(-8);
localparam i_to_r_res3 = i_to_r( 7);
localparam i_to_r_res4 = i_to_r( 8);
localparam r_to_i_res1 = r_to_i(-8.5);
localparam r_to_i_res2 = r_to_i(-7.5);
localparam r_to_i_res3 = r_to_i( 6.5);
localparam r_to_i_res4 = r_to_i( 7.5);
localparam u_to_r_res1 = u_to_r(-1);
localparam u_to_r_res2 = u_to_r( 1);
localparam u_to_r_res3 = u_to_r(15);
localparam u_to_r_res4 = u_to_r(17);
localparam r_to_u_res1 = r_to_u(-0.5);
localparam r_to_u_res2 = r_to_u( 0.5);
localparam r_to_u_res3 = r_to_u(14.5);
localparam r_to_u_res4 = r_to_u(16.5);
localparam i_to_u_res1 = i_to_u(-9);
localparam i_to_u_res2 = i_to_u(-8);
localparam i_to_u_res3 = i_to_u( 7);
localparam i_to_u_res4 = i_to_u( 8);
localparam u_to_i_res1 = u_to_i(-1);
localparam u_to_i_res2 = u_to_i( 1);
localparam u_to_i_res3 = u_to_i(15);
localparam u_to_i_res4 = u_to_i(17);
localparam si_to_lu_res1 = si_to_lu(-9);
localparam si_to_lu_res2 = si_to_lu(-8);
localparam si_to_lu_res3 = si_to_lu( 7);
localparam si_to_lu_res4 = si_to_lu( 8);
localparam su_to_li_res1 = su_to_li(-1);
localparam su_to_li_res2 = su_to_li( 1);
localparam su_to_li_res3 = su_to_li(15);
localparam su_to_li_res4 = su_to_li(17);
localparam li_to_su_res1 = li_to_su(-9);
localparam li_to_su_res2 = li_to_su(-8);
localparam li_to_su_res3 = li_to_su( 7);
localparam li_to_su_res4 = li_to_su( 8);
localparam lu_to_si_res1 = lu_to_si(-1);
localparam lu_to_si_res2 = lu_to_si( 1);
localparam lu_to_si_res3 = lu_to_si(15);
localparam lu_to_si_res4 = lu_to_si(17);
reg failed;
initial begin
failed = 0;
$display("%0g", i_to_r_res1); if (i_to_r_res1 != 7.5) failed = 1;
$display("%0g", i_to_r_res2); if (i_to_r_res2 != -7.5) failed = 1;
$display("%0g", i_to_r_res3); if (i_to_r_res3 != 7.5) failed = 1;
$display("%0g", i_to_r_res4); if (i_to_r_res4 != -7.5) failed = 1;
$display("");
$display("%0d", r_to_i_res1); if (r_to_i_res1 !== 7) failed = 1;
$display("%0d", r_to_i_res2); if (r_to_i_res2 !== -8) failed = 1;
$display("%0d", r_to_i_res3); if (r_to_i_res3 !== 7) failed = 1;
$display("%0d", r_to_i_res4); if (r_to_i_res4 !== -8) failed = 1;
$display("");
$display("%0g", u_to_r_res1); if (u_to_r_res1 != 15.5) failed = 1;
$display("%0g", u_to_r_res2); if (u_to_r_res2 != 1.5) failed = 1;
$display("%0g", u_to_r_res3); if (u_to_r_res3 != 15.5) failed = 1;
$display("%0g", u_to_r_res4); if (u_to_r_res4 != 1.5) failed = 1;
$display("");
$display("%0d", r_to_u_res1); if (r_to_u_res1 !== 15) failed = 1;
$display("%0d", r_to_u_res2); if (r_to_u_res2 !== 1) failed = 1;
$display("%0d", r_to_u_res3); if (r_to_u_res3 !== 15) failed = 1;
$display("%0d", r_to_u_res4); if (r_to_u_res4 !== 1) failed = 1;
$display("");
$display("%0d", i_to_u_res1); if (i_to_u_res1 !== 7) failed = 1;
$display("%0d", i_to_u_res2); if (i_to_u_res2 !== 8) failed = 1;
$display("%0d", i_to_u_res3); if (i_to_u_res3 !== 7) failed = 1;
$display("%0d", i_to_u_res4); if (i_to_u_res4 !== 8) failed = 1;
$display("");
$display("%0d", u_to_i_res1); if (u_to_i_res1 !== -1) failed = 1;
$display("%0d", u_to_i_res2); if (u_to_i_res2 !== 1) failed = 1;
$display("%0d", u_to_i_res3); if (u_to_i_res3 !== -1) failed = 1;
$display("%0d", u_to_i_res4); if (u_to_i_res4 !== 1) failed = 1;
$display("");
$display("%0d", si_to_lu_res1); if (si_to_lu_res1 !== 7) failed = 1;
$display("%0d", si_to_lu_res2); if (si_to_lu_res2 !== 56) failed = 1;
$display("%0d", si_to_lu_res3); if (si_to_lu_res3 !== 7) failed = 1;
$display("%0d", si_to_lu_res4); if (si_to_lu_res4 !== 56) failed = 1;
$display("");
$display("%0d", su_to_li_res1); if (su_to_li_res1 !== 15) failed = 1;
$display("%0d", su_to_li_res2); if (su_to_li_res2 !== 1) failed = 1;
$display("%0d", su_to_li_res3); if (su_to_li_res3 !== 15) failed = 1;
$display("%0d", su_to_li_res4); if (su_to_li_res4 !== 1) failed = 1;
$display("");
$display("%0d", li_to_su_res1); if (li_to_su_res1 !== 7) failed = 1;
$display("%0d", li_to_su_res2); if (li_to_su_res2 !== 8) failed = 1;
$display("%0d", li_to_su_res3); if (li_to_su_res3 !== 7) failed = 1;
$display("%0d", li_to_su_res4); if (li_to_su_res4 !== 8) failed = 1;
$display("");
$display("%0d", lu_to_si_res1); if (lu_to_si_res1 !== -1) failed = 1;
$display("%0d", lu_to_si_res2); if (lu_to_si_res2 !== 1) failed = 1;
$display("%0d", lu_to_si_res3); if (lu_to_si_res3 !== -1) failed = 1;
$display("%0d", lu_to_si_res4); if (lu_to_si_res4 !== 1) failed = 1;
$display("");
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
package p_defs;
class a_class;
int id_;
function new(int id);
id_ = id;
endfunction
task display();
$display("This is class %0d.", id_);
endtask
endclass
endpackage
// This should print the following:
// This is class 2.
// This is class 1.
module top;
import p_defs::a_class;
a_class ac1;
a_class ac2;
initial begin
ac1 = new(1);
ac2 = new(2);
ac2.display();
ac1.display();
end
endmodule
|
// Check that declaring a net of a class type results in an error
module test;
class C;
endclass
wire C x;
initial begin
$display("FAILED");
end
endmodule
|
// Copyright 2008, Martin Whitaker.
// This file may be freely copied for any purpose.
module localparam_sign();
localparam\tP1\t= 16;
localparam\tP2\t= P1 * 2;
submodule #(P2) submodule();
endmodule
module submodule();
parameter\tP3\t= 1;
initial begin
$display("P3 = %0d", P3);
end
endmodule
|
// Check that non-blocking partial writes to a 2-state vector array element are
// correctly handlded.
module test;
reg failed = 1\'b0;
`define check(val, exp) \\
if (exp !== val) begin \\
$display("FAILED. Got %b, expected %b.", val, exp); \\
failed = 1\'b1; \\
end
bit [3:0] x[1:0];
integer i;
initial begin
// Immediate index
// Within bounds
x[0] = \'h0;
x[0][2:1] <= 2\'b10;
#1
`check(x[0], 4\'b0100)
// Partially oob at high and low side
x[0] = \'h0;
x[0][4:-1] <= 6\'b101010;
#1
`check(x[0], 4\'b0101)
// Partially oob at low side
x[0] = \'h0;
x[0][0:-1] <= 2\'b10;
#1
`check(x[0], 4\'b0001)
// Partially oob at high side
x[0] = \'h0;
x[0][4:3] <= 2\'b01;
#1
`check(x[0], 4\'b1000)
// Fully oob at low side
x[0] = \'h0;
x[0][-1:-2] <= 2\'b11;
#1
`check(x[0], 4\'b0000)
// Fully oob at high side
x[0] = \'h0;
x[0][6:5] <= 2\'b11;
#1
`check(x[0], 4\'b0000)
// Variable index
// Within bounds
i = 1;
x[0] = \'h0;
x[0][i+:2] = 2\'b10;
#1
`check(x[0], 4\'b0100)
// Partially oob at high and low side
i = -1;
x[0] = \'h0;
x[0][i+:6] <= 6\'b101010;
#1
`check(x[0], 4\'b0101)
// Partially oob at low side
i = -1;
x[0] = \'h0;
x[0][i+:2] <= 2\'b10;
#1
`check(x[0], 4\'b0001)
// Partially oob at high side
i = 3;
x[0] = \'h0;
x[0][i+:2] <= 2\'b01;
#1
`check(x[0], 4\'b1000)
// Fully oob at low side
i = -2;
x[0] = \'h0;
x[0][i+:2] <= 2\'b11;
#1
`check(x[0], 4\'b0000)
// Fully oob at high side
i = 5;
x[0] = \'h0;
x[0][i+:2] <= 2\'b11;
#1
`check(x[0], 4\'b0000)
// Undefined index
i = \'hx;
x[0] = \'h0;
x[0][i+:2] <= 2\'b11;
#1
`check(x[0], 4\'b0000)
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
/*
* This test is derived from bug report PR#511. Mostly what it is
* doing is checking the behavior of === and wait.
*/
`timescale 1 ps / 1 ps
module I54;
initial begin
#500000
$display( "FAILED." );
$finish;
end
parameter I148 = 4096;
integer I20;
integer I57;
integer I58;
integer I137;
time I106;
time I95;
time I97;
time I122;
time I142;
time I67;
time I25;
time I83;
time I128;
time I10;
time I12;
time I73;
time I159;
reg I77;
reg I108;
reg I2;
reg I81;
reg I60;
reg I114;
reg I124;
reg I41;
reg I151;
reg I43;
reg [1:0] I68;
reg [4*8-1:0] I138;
reg [3:0] I71;
reg [3:0] I149;
reg [3:0] I6;
reg [3:0] I76;
reg I48;
reg I61;
reg I62;
reg I49;
reg I158;
reg I85;
reg [2:0] I84;
reg [2:0] I30;
reg I94;
wire I69;
wire I98;
reg I115;
reg I101;
reg I14;
reg I78;
reg I131;
reg I24;
reg I52;
reg I13;
reg I132;
reg I139;
reg I107;
wire I93;
wire [3:0] I120;
wire [3:0] I82;
wire I38;
wire I22;
wire [1:0] I46;
wire [2:0] I1;
wire [4*8-1:0] I4;
wire [3:0] I125;
wire [3:0] I36;
wire [3:0] I91;
wire [3:0] I3;
wire [3:0] I143;
wire [1:0] I72;
wire I34;
wire I150;
wire I40;
wire [1:0] I51;
reg [1:0] I39;
reg [4-1:0] I70;
wire I103;
wire I29;
wire I74;
wire I144;
reg I63;
reg I15;
reg I146;
reg I110;
reg I152;
reg I129;
reg I19;
reg I112;
reg I102;
reg I156;
reg I121;
wire I23;
wire [3:0] I118;
wire [3:0] I86;
wire I28;
wire I65;
wire [1:0] I79;
wire [2:0] I17;
wire [4*8-1:0] I133;
wire [3:0] I27;
wire [3:0] I99;
wire [3:0] I135;
wire [3:0] I90;
wire [3:0] I35;
wire [1:0] I55;
wire I8;
wire I126;
wire I5;
wire [1:0] I140;
reg [1:0] I116;
reg [4-1:0] I45;
wire I105;
wire I33;
wire I75;
wire I145;
reg I64;
reg I16;
reg I147;
reg I111;
reg I153;
reg I130;
reg I21;
reg I113;
reg I104;
reg I157;
reg I123;
wire I26;
wire [3:0] I119;
wire [3:0] I87;
wire I32;
wire I66;
wire [1:0] I80;
wire [2:0] I18;
wire [4*8-1:0] I134;
wire [3:0] I31;
wire [3:0] I100;
wire [3:0] I136;
wire [3:0] I92;
wire [3:0] I37;
wire [1:0] I56;
wire I9;
wire I127;
wire I7;
wire [1:0] I141;
reg [1:0] I117;
reg [4-1:0] I47;
wire [256:0] I59;
wire [256:0] I50;
wire [256:0] I88;
wire [256:0] I154;
wire [256:0] I89;
wire [256:0] I155;
assign I69 = I59[I20];
assign I98 = I50[I20];
assign I103 = I88[I57];
assign I29 = I154[I57];
assign I105 = I89[I58];
assign I33 = I155[I58];
wire I109 = ( ~ I94 ) & ( ~ I151 );
wire I96 = ( ~ I94 ) & ( I151 );
wire I42 = ( I94 ) & ( ~ I151 );
wire I44 = ( I94 ) & ( I151 );
always @( I114 ) begin
I132 <= #I106 I114;
I102 <= #I95 I114;
I104 <= #I97 I114;
end
always @( I124 ) begin
I139 <= #I106 I124;
I156 <= #I95 I124;
I157 <= #I97 I124;
end
initial begin
I77 = 1\'b0;
#0 ;
#(I142) I77 = 1\'b1;
forever #(I122/2) I77 = ~ I77;
end
initial begin
I108 = 1\'b0;
#0 ;
#(I25) I108 = 1\'b1;
forever #(I67/2) I108 = ~ I108;
end
initial begin
I2 = 1\'b0;
#0 ;
#(I128) I2 = 1\'b1;
forever #(I83/2) I2 = ~ I2;
end
initial begin
I81 = 1\'b0;
#0 ;
#(I12) I81 = 1\'b1;
forever #(I10/2) I81 = ~ I81;
end
initial begin
I60 = 1\'b0;
#0 ;
#(I159) I60 = 1\'b1;
forever #(I73/2) I60 = ~ I60;
end
initial begin
I114 = 1\'b1;
#300000 ;
@( posedge I81 ) ;
@( posedge I81 ) ;
#50 I114 = 1\'b0;
end
initial begin
I124 = 1\'b1;
#300000 ;
@( posedge I60 ) ;
@( posedge I60 ) ;
#50 I124 = 1\'b0;
end
initial begin : I53
I137 = 1600;
I20 = 40;
I57 = 0;
I58 = 80;
I106 = 150;
I95 = 300;
I97 = 0;
I151 = 1\'b0;
I94 = 1\'b0;
I122 = 6400;
I142 = 0;
I67 = 6270;
I25 = 0;
I83 = 6400;
I128 = 1000;
I10 = 6270;
I12 = 0;
I73 = 6400;
I159 = 1000;
wait ( I114 === 1\'b1 );
wait ( I114 === 1\'b0 );
wait ( I124 === 1\'b0 );
$display( "PASSED" );
$finish;
end
endmodule
|
module top;
reg [3:0][3:0] array;
reg failed = 0;
initial begin
array = 16\'h4321;
$display("%h", array[ 0+:2]); if (array[ 0+:2] !== 8\'h21) failed = 1;
$display("%h", array[ 1+:2]); if (array[ 1+:2] !== 8\'h32) failed = 1;
$display("%h", array[ 2+:2]); if (array[ 2+:2] !== 8\'h43) failed = 1;
$display("%h", array[ 1-:2]); if (array[ 1-:2] !== 8\'h21) failed = 1;
$display("%h", array[ 2-:2]); if (array[ 2-:2] !== 8\'h32) failed = 1;
$display("%h", array[ 3-:2]); if (array[ 3-:2] !== 8\'h43) failed = 1;
$display("%h", array[ 1:0 ]); if (array[ 1:0 ] !== 8\'h21) failed = 1;
$display("%h", array[ 2:1 ]); if (array[ 2:1 ] !== 8\'h32) failed = 1;
$display("%h", array[ 3:2 ]); if (array[ 3:2 ] !== 8\'h43) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module main;
genvar i;
parameter MSB = 7;
wire [MSB:0] Z;
reg [MSB:0]\tA, B;
generate
for (i = 0; i <= MSB; i = i+1)
\tbegin: or2
\t OR2 uor2 (.A(A[i]), .B(B[i]), .Z(Z[i]));
\tend
endgenerate
initial begin
for (A = 0 ; A < \'hff ; A = A+1)
\tfor (B = 0 ; B < \'hff ; B = B+1)
\t #1 if (Z !== (A|B)) begin
\t $display("FAILED -- A=%h, B=%h, Z=%h", A, B, Z);
\t $finish;
\t end
$display("PASSED");
end
endmodule
module OR2 (Z, A, B);
output Z;
input A;
input B;
or (Z, A, B);
endmodule
|
// Copyright (c) 2015 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test string escaping in VHDL.
module vhdl_string_test;
logic start;
vhdl_string dut(start);
// nothing else is needed here
endmodule
|
//
// Copyright (c) 2002 Stephen Williams
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// Binary ~& (nand) operator.
module main;
reg A, B;
reg result1;
wire result2 = A ~& B;
initial
begin
\tA = 0;
\tB = 0;
\t#1 result1 = A ~& B;
\tif (result1 !== 1\'b1) begin
\t $display("FAILED");
\t $finish;
\tend
\tif (result2 !== 1\'b1) begin
\t $display("FAILED");
\t $finish;
\tend
\tA = 1;
\t#1 result1 = A ~& B;
\tif (result1 !== 1\'b1) begin
\t $display("FAILED");
\t $finish;
\tend
\tif (result2 !== 1\'b1) begin
\t $display("FAILED");
\t $finish;
\tend
\tB = 1;
\t#1 result1 = A ~& B;
\tif (result1 !== 1\'b0) begin
\t $display("FAILED");
\t $finish;
\tend
\tif (result2 !== 1\'b0) begin
\t $display("FAILED");
\t $finish;
\tend
\tA = 0;
\t#1 result1 = A ~& B;
\tif (result1 !== 1\'b1) begin
\t $display("FAILED");
\t $finish;
\tend
\tif (result2 !== 1\'b1) begin
\t $display("FAILED");
\t $finish;
\tend
\t$display("PASSED");
end
endmodule // main
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Force stmt validation
//
// D: This code verifies the force statement
// D: It is intended to be self checking.
//
module main ();
reg working;
reg timer;
initial
begin
timer = 1;
# 5;
timer = 0;
# 5 ;
timer = 1;
# 5 ;
end
initial
begin
working = 1;
#2 ; // Validate that force occurs
force timer = 0;
if( timer == 1) working = 0;
#10 ; // Validate that force stays in effect
if( timer == 1) working = 0;
end
initial
begin
#20;
if(!working)
$display("FAILED\
");
else
$display("PASSED\
");
end
endmodule
|
// Check that declarations for queues of queues are supported.
module test;
// Queue of queues
int q[$][$];
endmodule
|
module main;
localparam AMAX = 7;
localparam SHIFT = 4;
longint foo [AMAX:0];
longint unsigned foo_u [AMAX:0];
int idx;
initial begin
for (idx = 0 ; idx <= AMAX ; idx = idx+1) begin
\t foo[idx] = idx - SHIFT;
\t foo_u[idx] = idx;
end
for (idx = 0 ; idx <= AMAX ; idx = idx+1) begin
\t if (idx < SHIFT && foo[idx] > 0) begin
\t $display("FAIL -- foo[%0d] = %0d (not signed?)", idx, foo[idx]);
\t $finish;
\t end
\t if (foo[idx] != (idx-SHIFT)) begin
\t $display("FAIL -- foo[%0d] = %0d", idx, foo[idx]);
\t $finish;
\t end
\t if (foo_u[idx] != idx) begin
\t $display("FAIL -- foo_u[%0d] = %0d", idx, foo[idx]);
\t $finish;
\t end
end
$display("PASSED");
$finish;
end // initial begin
endmodule // main
|
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
module bug();
reg [1:2][1:16][1:8] array;
reg failed = 0;
integer i;
reg [3:0] index;
initial begin
i = $bits(array);
$display("width 0 = %0d", i);
if (i !== 256) failed = 1;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
i = $bits(array[0]);
`else
i = $bits(array[1]);
`endif
$display("width 1 = %0d", i);
if (i !== 128) failed = 1;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
i = $bits(array[0][0]);
`else
i = $bits(array[1][1]);
`endif
$display("width 2 = %0d", i);
if (i !== 8) failed = 1;
for (i = 0; i < 16; i++) begin
index = i[3:0];
array[1][5\'d1+index] = {4\'d0, index};
array[2][5\'d1+index] = {4\'d1, index};
end
$display("%h", array);
if (array !== 256\'h000102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f)
failed = 1;
for (i = 0; i < 16; i++) begin
index = i[3:0];
$display("%h : %h %h", index, array[1][5\'d1+index], array[2][5\'d1+index]);
if (array[1][5\'d1+index] !== {4\'d0, index}) failed = 1;
if (array[2][5\'d1+index] !== {4\'d1, index}) failed = 1;
end
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
// Check that when a enum type is declared inside a class that the enum is
// properly installed in the scope and the enum items are available.
//
// Also check that when using a typedef of a enum inside a class that the enum
// is not elaborated inside the class and it is possible to have a enum with the
// same names inside the class scope.
module test;
typedef enum integer {
A = 1
} e1_t;
class C;
typedef enum integer {
A = 10
} e2_t;
e1_t e1;
e2_t e2;
function new();
e1 = test.A;
e2 = A;
endfunction
function void set(e2_t new_e2);
e2 = new_e2;
endfunction
endclass
C c;
initial begin
c = new;
c.e1 = A;
c.set(c.e2);
// Not yet supported
// c.e2 = C::A;
c.e2 = c.A;
// Check that they have the numerical value from the right scope
if (c.e1 == 1 && c.e2 == 10) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
|
module top(
pi_wi, // port implicit, wire implicit
pi_ws, // port implicit, wire signed
pi_wu, // port implicit, wire unsigned
ps_wi, // port signed, wire implicit
ps_ws, // port signed, wire signed
ps_wu, // port signed, wire unsigned
pu_wi, // port unsigned, wire implicit
pu_ws, // port unsigned, wire signed
pu_wu // port unsigned, wire unsigned
);
output pi_wi;
output pi_ws;
output pi_wu;
output signed ps_wi;
output signed ps_ws;
output signed ps_wu;
output unsigned pu_wi;
output unsigned pu_ws;
output unsigned pu_wu;
wire pi_wi = 1\'b1;
wire ps_wi = 1\'b1;
wire pu_wi = 1\'b1;
wire signed pi_ws = 1\'b1;
wire signed ps_ws = 1\'b1;
wire signed pu_ws = 1\'b1;
wire unsigned pi_wu = 1\'b1;
wire unsigned ps_wu = 1\'b1;
wire unsigned pu_wu = 1\'b1;
reg [1:0] value;
reg failed = 0;
initial begin
#1;
value = pi_wi; $display("%b", value); if (value !== 2\'b01) failed = 1;
value = pi_ws; $display("%b", value); if (value !== 2\'b11) failed = 1;
value = pi_wu; $display("%b", value); if (value !== 2\'b01) failed = 1;
value = ps_wi; $display("%b", value); if (value !== 2\'b11) failed = 1;
value = ps_ws; $display("%b", value); if (value !== 2\'b11) failed = 1;
value = ps_wu; $display("%b", value); if (value !== 2\'b11) failed = 1;
value = pu_wi; $display("%b", value); if (value !== 2\'b01) failed = 1;
value = pu_ws; $display("%b", value); if (value !== 2\'b11) failed = 1;
value = pu_wu; $display("%b", value); if (value !== 2\'b01) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module top;
reg pass;
reg [7:0] in;
reg [1:0] res;
integer lp;
initial begin
pass = 1\'b1;
in = 8\'b11100100;
lp = 3;
// lp[1:0] is being sign extended and that fails when the value mod 4
// is either 2 or 3! A bit/part select is always unsigned unless we use
// The $signed function to cast it to signed!
res = in[lp[1:0]*2 +: 2];
if (res !== 2\'b11) begin
$display("Failed expected 2\'b11, got %b (%b:%d)", res, in, lp[1:0]*2);
pass = 1\'b0;
end
// This should give -2 for the index.
res = in[$signed(lp[1:0])*2 +: 2];
if (res !== 2\'bxx) begin
$display("Failed expected 2\'bxx, got %b (%b:%d)", res, in,
$signed(lp[1:0])*2);
pass = 1\'b0;
end
lp = 6;
// The same as above, but not at the start of the signal.
res = in[lp[2:1]*2 +: 2];
if (res !== 2\'b11) begin
$display("Failed expected 2\'b11, got %b (%b:%d)", res, in, lp[2:1]*2);
pass = 1\'b0;
end
res = in[$signed(lp[2:1])*2 +: 2];
if (res !== 2\'bxx) begin
$display("Failed expected 2\'bxx, got %b (%b:%d)", res, in,
$signed(lp[2:1])*2);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
module vvp_scalar_value();
reg [2:0] v1;
reg [2:0] v2;
wire [2:0] w1;
wire [2:0] w2;
wire [2:0] w3;
assign ( highz1, strong0) w1 = v1;
assign (strong1, highz0) w2 = v1;
assign ( highz1, strong0) w3 = v1;
assign (strong1, highz0) w3 = v2;
reg failed;
initial begin
failed = 0;
v1 = 3\'bz10; #1;
$display("%b %v %v %v", w1, w1[2], w1[1], w1[0]);
if (w1 !== 3\'bzz0) failed = 1;
$display("%b %v %v %v", w2, w2[2], w2[1], w2[0]);
if (w2 !== 3\'bz1z) failed = 1;
v2 = 3\'b000; #1;
$display("%b %v %v %v", w3, w3[2], w3[1], w3[0]);
if (w3 !== 3\'bzz0) failed = 1;
v2 = 3\'b111; #1;
$display("%b %v %v %v", w3, w3[2], w3[1], w3[0]);
if (w3 !== 3\'b11x) failed = 1;
v2 = 3\'bzzz; #1;
$display("%b %v %v %v", w3, w3[2], w3[1], w3[0]);
if (w3 !== 3\'bzz0) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module dut(a,);
input wire a;
endmodule
module top;
wire a;
dut i(.*);
endmodule
|
/*
* This is a post-wynthesis test for the blif01a.v test. Run this
* simulation in these steps:
*
* $ iverilog -tblif -o foo.blif blif01a.v
* $ abc
* abc 01> read_blif foo.blif
* abc 02> write_verilog foo.v
* abc 03> quit
* $ iverilog -g2009 -o foo.vvp blif02a_tb.v foo.v
* $ vvp foo.vvp
*/
module main;
parameter WID = 4;
reg [WID-1:0] A, B;
wire [WID:0] Q;
addN usum(.\\A[3] (A[3]), .\\A[2] (A[2]), .\\A[1] (A[1]), .\\A[0] (A[0]),
\t .\\B[3] (B[3]), .\\B[2] (B[2]), .\\B[1] (B[1]), .\\B[0] (B[0]),
\t .\\Q[4] (Q[4]), .\\Q[3] (Q[3]), .\\Q[2] (Q[2]), .\\Q[1] (Q[1]), .\\Q[0] (Q[0]));
int\t\t adx;
int\t\t bdx;
initial begin
for (bdx = 0 ; bdx[WID]==0 ; bdx = bdx+1) begin
\t for (adx = 0 ; adx[WID]==0 ; adx = adx+1) begin
\t A <= adx[WID-1:0];
\t B <= bdx[WID-1:0];
\t #1 if (Q !== (adx+bdx)) begin
\t $display("FAILED -- A=%b, B=%b, Q=%b", A, B, Q);
\t $finish;
\t end
\t end
end
$display("PASSED");
end
endmodule // main
|
`timescale 1ns/10ps
module top;
reg pass;
reg [80*8:1] str;
reg [63:0] a, b, c;
real r;
integer code;
initial begin
pass = 1\'b1;
// Check that a failing match stops the matching process.
str = "2 3";
code = $sscanf(str, "%b%d", a, b);
if (code !== 0) begin
$display("FAILED(mb) to stop matching found %d", code);
pass = 1\'b0;
end
str = "8 3";
code = $sscanf(str, "%o%d", a, b);
if (code !== 0) begin
$display("FAILED(mo) to stop matching found %d", code);
pass = 1\'b0;
end
str = "g 3";
code = $sscanf(str, "%h%d", a, b);
if (code !== 0) begin
$display("FAILED(mh) to stop matching found %d", code);
pass = 1\'b0;
end
str = "g 3";
code = $sscanf(str, "%x%d", a, b);
if (code !== 0) begin
$display("FAILED(mx) to stop matching found %d", code);
pass = 1\'b0;
end
str = "a 3";
code = $sscanf(str, "%d%d", a, b);
if (code !== 0) begin
$display("FAILED(md) to stop matching found %d", code);
pass = 1\'b0;
end
// Check parsing all the binary values (%b).
str = "01_?xzXZ";
code = $sscanf(str, "%b", a);
if (code !== 1) begin
$display("FAILED(b) to parse one argument found %d", code);
pass = 1\'b0;
end
if (a !== \'b01xxzxz) begin
$display("FAILED(b) argument value, expected 01xxzxz, got %b", a);
pass = 1\'b0;
end
// Check that a leaading underscore is invalid.
a = \'bx;
str = "_01_?xzXZ";
code = $sscanf(str, "%b", a);
if (code !== 0) begin
$display("FAILED(bi) to parse zero argument found %d", code);
pass = 1\'b0;
end
if (a !== \'bx) begin
$display("FAILED(bi) argument value, expected x, got %b", a);
pass = 1\'b0;
end
// Check parsing all the octal values (%o).
str = "01234567_xzXZ?";
code = $sscanf(str, "%o", a);
if (code !== 1) begin
$display("FAILED(o) to parse one argument found %d", code);
pass = 1\'b0;
end
if (a !== 64\'o01234567xzxzx) begin
$display("FAILED(o) argument value, expected 01234567xzxzx, got %o", a);
pass = 1\'b0;
end
// Check that a leaading underscore is invalid.
a = \'bx;
str = "_01234567_xzXZ?";
code = $sscanf(str, "%o", a);
if (code !== 0) begin
$display("FAILED(oi) to parse zero argument found %d", code);
pass = 1\'b0;
end
if (a !== \'ox) begin
$display("FAILED(oi) argument value, expected x, got %o", a);
pass = 1\'b0;
end
// Check parsing all the decimal values (%d).
str = "+01234_56789";
code = $sscanf(str, "%d", a);
if (code !== 1) begin
$display("FAILED(d1) to parse one argument found %d", code);
pass = 1\'b0;
end
if (a !== \'d0123456789) begin
$display("FAILED(d1) argument value, expected 0123456789, got %d", a);
pass = 1\'b0;
end
str = "01234_56789";
code = $sscanf(str, "%d", a);
if (code !== 1) begin
$display("FAILED(d2) to parse one argument found %d", code);
pass = 1\'b0;
end
if (a !== \'d0123456789) begin
$display("FAILED(d2) argument value, expected 0123456789, got %d", a);
pass = 1\'b0;
end
str = "-01234_56789";
code = $sscanf(str, "%d", a);
if (code !== 1) begin
$display("FAILED(d3) to parse one argument found %d", code);
pass = 1\'b0;
end
if (a !== -\'d0123456789) begin
$display("FAILED(d3) argument value, expected -0123456789, got %d", a);
pass = 1\'b0;
end
str = "x";
code = $sscanf(str, "%d", a);
if (code !== 1) begin
$display("FAILED(d4) to parse one argument found %d", code);
pass = 1\'b0;
end
if (a !== \'dx) begin
$display("FAILED(d4) argument value, expected x, got %d", a);
pass = 1\'b0;
end
str = "X";
code = $sscanf(str, "%d", a);
if (code !== 1) begin
$display("FAILED(d5) to parse one argument found %d", code);
pass = 1\'b0;
end
if (a !== \'dx) begin
$display("FAILED(d5) argument value, expected x, got %d", a);
pass = 1\'b0;
end
str = "z";
code = $sscanf(str, "%d", a);
if (code !== 1) begin
$display("FAILED(d6) to parse one argument found %d", code);
pass = 1\'b0;
end
if (a !== \'dz) begin
$display("FAILED(d6) argument value, expected z, got %d", a);
pass = 1\'b0;
end
str = "Z";
code = $sscanf(str, "%d", a);
if (code !== 1) begin
$display("FAILED(d7) to parse one argument found %d", code);
pass = 1\'b0;
end
if (a !== \'dz) begin
$display("FAILED(d7) argument value, expected z, got %d", a);
pass = 1\'b0;
end
str = "?";
code = $sscanf(str, "%d", a);
if (code !== 1) begin
$display("FAILED(d8) to parse one argument found %d", code);
pass = 1\'b0;
end
if (a !== \'dx) begin
$display("FAILED(d8) argument value, expected x, got %d", a);
pass = 1\'b0;
end
// A plus or minus must have a digit after to match.
a = \'bx;
str = "-q";
code = $sscanf(str, "%d", a);
if (code !== 0) begin
$display("FAILED(d9) to parse zero arguments found %d", code);
pass = 1\'b0;
end
if (a !== \'dx) begin
$display("FAILED(d9) argument value, expected x, got %d", a);
pass = 1\'b0;
end
a = \'bx;
str = "+q";
code = $sscanf(str, "%d", a);
if (code !== 0) begin
$display("FAILED(d0) to parse zero arguments found %d", code);
pass = 1\'b0;
end
if (a !== \'dx) begin
$display("FAILED(d0) argument value, expected x, got %d", a);
pass = 1\'b0;
end
// Check that a leaading underscore is invalid.
a = \'dx;
str = "_01234_56789";
code = $sscanf(str, "%d", a);
if (code !== 0) begin
$display("FAILED(di) to parse zero argument found %d", code);
pass = 1\'b0;
end
if (a !== \'dx) begin
$display("FAILED(di) argument value, expected x, got %d", a);
pass = 1\'b0;
end
// Check parsing all the hex values (both %h and %x).
str = "0123456789_xzXZ?";
code = $sscanf(str, "%h", a);
if (code !== 1) begin
$display("FAILED(h1) to parse one argument found %d", code);
pass = 1\'b0;
end
if (a !== 64\'h0123456789xzxzx) begin
$display("FAILED(h1) argument value, expected 0123456789xzxzx, got %h", a);
pass = 1\'b0;
end
str = "aA_bB_cC_dD_eE_fF";
code = $sscanf(str, "%h", a);
if (code !== 1) begin
$display("FAILED(h2) to parse one argument found %d", code);
pass = 1\'b0;
end
if (a !== 64\'haabbccddeeff) begin
$display("FAILED(h2) argument value, expected aabbccddeeff, got %h", a);
pass = 1\'b0;
end
str = "0123456789_xzXZ?";
code = $sscanf(str, "%x", a);
if (code !== 1) begin
$display("FAILED(h3) to parse one argument found %d", code);
pass = 1\'b0;
end
if (a !== 64\'h0123456789xzxzx) begin
$display("FAILED(h3) argument value, expected 0123456789xzxzx, got %h", a);
pass = 1\'b0;
end
str = "aA_bB_cC_dD_eE_fF";
code = $sscanf(str, "%x", a);
if (code !== 1) begin
$display("FAILED(h4) to parse one argument found %d", code);
pass = 1\'b0;
end
if (a !== 64\'haabbccddeeff) begin
$display("FAILED(h4) argument value, expected aabbccddeeff, got %h", a);
pass = 1\'b0;
end
// Check that a leaading underscore is invalid.
a = \'dx;
str = "_0123456789_xzXZ?";
code = $sscanf(str, "%h", a);
if (code !== 0) begin
$display("FAILED(hi) to parse zero argument found %d", code);
pass = 1\'b0;
end
if (a !== \'hx) begin
$display("FAILED(hi) argument value, expected x, got %h", a);
pass = 1\'b0;
end
// Check parsing real values %f.
str = "+0123456789";
code = $sscanf(str, "%f", r);
if (code !== 1) begin
$display("FAILED(f1) to parse one argument found %d", code);
pass = 1\'b0;
end
if (r != 123456789.0) begin
$display("FAILED(f1) argument value, expected 123456789.0, got %f", r);
pass = 1\'b0;
end
str = "0123456789";
code = $sscanf(str, "%f", r);
if (code !== 1) begin
$display("FAILED(f2) to parse one argument found %d", code);
pass = 1\'b0;
end
if (r != 123456789.0) begin
$display("FAILED(f2) argument value, expected 123456789.0, got %f", r);
pass = 1\'b0;
end
str = "-0123456789";
code = $sscanf(str, "%f", r);
if (code !== 1) begin
$display("FAILED(f3) to parse one argument found %d", code);
pass = 1\'b0;
end
if (r != -123456789.0) begin
$display("FAILED(f3) argument value, expected -123456789.0, got %f", r);
pass = 1\'b0;
end
// A plus or minus must have a digit after to match.
r = 1.0;
str = "-q";
code = $sscanf(str, "%f", r);
if (code !== 0) begin
$display("FAILED(f4) to parse zero arguments found %d", code);
pass = 1\'b0;
end
if (r != 1.0) begin
$display("FAILED(f4) argument value, expected 1.0, got %f", r);
pass = 1\'b0;
end
r = 1.0;
str = "+q";
code = $sscanf(str, "%f", r);
if (code !== 0) begin
$display("FAILED(f5) to parse zero arguments found %d", code);
pass = 1\'b0;
end
if (r != 1.0) begin
$display("FAILED(f5) argument value, expected 1.0, got %f", r);
pass = 1\'b0;
end
r = 1.0;
str = "q";
code = $sscanf(str, "%f", r);
if (code !== 0) begin
$display("FAILED(f6) to parse zero arguments found %d", code);
pass = 1\'b0;
end
if (r != 1.0) begin
$display("FAILED(f6) argument value, expected 1.0, got %f", r);
pass = 1\'b0;
end
// Check starting/trailing decimal point.
str = "2.";
code = $sscanf(str, "%f", r);
if (code !== 1) begin
$display("FAILED(f7) to parse one arguments found %d", code);
pass = 1\'b0;
end
if (r != 2.0) begin
$display("FAILED(f7) argument value, expected 2.0, got %f", r);
pass = 1\'b0;
end
str = ".2";
code = $sscanf(str, "%f", r);
if (code !== 1) begin
$display("FAILED(f8) to parse one arguments found %d", code);
pass = 1\'b0;
end
if (r != 0.2) begin
$display("FAILED(f8) argument value, expected 0.2, got %f", r);
pass = 1\'b0;
end
// Check with an exponent.
str = "2.e1";
code = $sscanf(str, "%f", r);
if (code !== 1) begin
$display("FAILED(f9) to parse one arguments found %d", code);
pass = 1\'b0;
end
if (r != 20.0) begin
$display("FAILED(f9) argument value, expected 20.0, got %f", r);
pass = 1\'b0;
end
str = "2.e-1";
code = $sscanf(str, "%f", r);
if (code !== 1) begin
$display("FAILED(f10) to parse one arguments found %d", code);
pass = 1\'b0;
end
if (r != 0.2) begin
$display("FAILED(f10) argument value, expected 0.2, got %f", r);
pass = 1\'b0;
end
// Check failing exponent cases.
r = 1.0;
str = "2.ea";
code = $sscanf(str, "%f", r);
if (code !== 0) begin
$display("FAILED(f11) to parse zero arguments found %d", code);
pass = 1\'b0;
end
if (r != 1.0) begin
$display("FAILED(f11) argument value, expected 1.0, got %f", r);
pass = 1\'b0;
end
r = 1.0;
str = "2.e+a";
code = $sscanf(str, "%f", r);
if (code !== 0) begin
$display("FAILED(f12) to parse zero arguments found %d", code);
pass = 1\'b0;
end
if (r != 1.0) begin
$display("FAILED(f12) argument value, expected 1.0, got %f", r);
pass = 1\'b0;
end
r = 1.0;
str = "2.e-a";
code = $sscanf(str, "%f", r);
if (code !== 0) begin
$display("FAILED(f13) to parse zero arguments found %d", code);
pass = 1\'b0;
end
if (r != 1.0) begin
$display("FAILED(f13) argument value, expected 1.0, got %f", r);
pass = 1\'b0;
end
str = "1e5000";
code = $sscanf(str, "%f", r);
if (code !== 1) begin
$display("FAILED(f14) to parse one arguments found %d", code);
pass = 1\'b0;
end
if (r != 1.0/0.0) begin
$display("FAILED(f14) argument value, expected inf, got %f", r);
pass = 1\'b0;
end
str = "-1e5000";
code = $sscanf(str, "%f", r);
if (code !== 1) begin
$display("FAILED(f14) to parse one arguments found %d", code);
pass = 1\'b0;
end
if (r != -1.0/0.0) begin
$display("FAILED(f14) argument value, expected -inf, got %f", r);
pass = 1\'b0;
end
// Check parsing real values %e.
str = "+0123456789";
code = $sscanf(str, "%e", r);
if (code !== 1) begin
$display("FAILED(e1) to parse one argument found %d", code);
pass = 1\'b0;
end
if (r != 123456789.0) begin
$display("FAILED(e1) argument value, expected 123456789.0, got %f", r);
pass = 1\'b0;
end
str = "0123456789";
code = $sscanf(str, "%e", r);
if (code !== 1) begin
$display("FAILED(e2) to parse one argument found %d", code);
pass = 1\'b0;
end
if (r != 123456789.0) begin
$display("FAILED(e2) argument value, expected 123456789.0, got %f", r);
pass = 1\'b0;
end
str = "-0123456789";
code = $sscanf(str, "%e", r);
if (code !== 1) begin
$display("FAILED(e3) to parse one argument found %d", code);
pass = 1\'b0;
end
if (r != -123456789.0) begin
$display("FAILED(e3) argument value, expected -123456789.0, got %f", r);
pass = 1\'b0;
end
// A plus or minus must have a digit after to match.
r = 1.0;
str = "-q";
code = $sscanf(str, "%e", r);
if (code !== 0) begin
$display("FAILED(e4) to parse zero arguments found %d", code);
pass = 1\'b0;
end
if (r != 1.0) begin
$display("FAILED(e4) argument value, expected 1.0, got %f", r);
pass = 1\'b0;
end
r = 1.0;
str = "+q";
code = $sscanf(str, "%e", r);
if (code !== 0) begin
$display("FAILED(e5) to parse zero arguments found %d", code);
pass = 1\'b0;
end
if (r != 1.0) begin
$display("FAILED(e5) argument value, expected 1.0, got %f", r);
pass = 1\'b0;
end
r = 1.0;
str = "q";
code = $sscanf(str, "%e", r);
if (code !== 0) begin
$display("FAILED(e6) to parse zero arguments found %d", code);
pass = 1\'b0;
end
if (r != 1.0) begin
$display("FAILED(e6) argument value, expected 1.0, got %f", r);
pass = 1\'b0;
end
// Check starting/trailing decimal point.
str = "2.";
code = $sscanf(str, "%e", r);
if (code !== 1) begin
$display("FAILED(e7) to parse one arguments found %d", code);
pass = 1\'b0;
end
if (r != 2.0) begin
$display("FAILED(e7) argument value, expected 2.0, got %f", r);
pass = 1\'b0;
end
str = ".2";
code = $sscanf(str, "%e", r);
if (code !== 1) begin
$display("FAILED(e8) to parse one arguments found %d", code);
pass = 1\'b0;
end
if (r != 0.2) begin
$display("FAILED(e8) argument value, expected 0.2, got %f", r);
pass = 1\'b0;
end
// Check with an exponent.
str = "2.e1";
code = $sscanf(str, "%e", r);
if (code !== 1) begin
$display("FAILED(e9) to parse one arguments found %d", code);
pass = 1\'b0;
end
if (r != 20.0) begin
$display("FAILED(e9) argument value, expected 20.0, got %f", r);
pass = 1\'b0;
end
str = "2.e-1";
code = $sscanf(str, "%e", r);
if (code !== 1) begin
$display("FAILED(e10) to parse one arguments found %d", code);
pass = 1\'b0;
end
if (r != 0.2) begin
$display("FAILED(e10) argument value, expected 0.2, got %f", r);
pass = 1\'b0;
end
// Check failing exponent cases.
r = 1.0;
str = "2.ea";
code = $sscanf(str, "%e", r);
if (code !== 0) begin
$display("FAILED(e11) to parse zero arguments found %d", code);
pass = 1\'b0;
end
if (r != 1.0) begin
$display("FAILED(e11) argument value, expected 1.0, got %f", r);
pass = 1\'b0;
end
r = 1.0;
str = "2.e+a";
code = $sscanf(str, "%e", r);
if (code !== 0) begin
$display("FAILED(e12) to parse zero arguments found %d", code);
pass = 1\'b0;
end
if (r != 1.0) begin
$display("FAILED(e12) argument value, expected 1.0, got %f", r);
pass = 1\'b0;
end
r = 1.0;
str = "2.e-a";
code = $sscanf(str, "%e", r);
if (code !== 0) begin
$display("FAILED(e13) to parse zero arguments found %d", code);
pass = 1\'b0;
end
if (r != 1.0) begin
$display("FAILED(e13) argument value, expected 1.0, got %f", r);
pass = 1\'b0;
end
str = "1e5000";
code = $sscanf(str, "%e", r);
if (code !== 1) begin
$display("FAILED(e14) to parse one arguments found %d", code);
pass = 1\'b0;
end
if (r != 1.0/0.0) begin
$display("FAILED(e14) argument value, expected inf, got %f", r);
pass = 1\'b0;
end
str = "-1e5000";
code = $sscanf(str, "%e", r);
if (code !== 1) begin
$display("FAILED(e14) to parse one arguments found %d", code);
pass = 1\'b0;
end
if (r != -1.0/0.0) begin
$display("FAILED(e14) argument value, expected -inf, got %f", r);
pass = 1\'b0;
end
// Check parsing real values %g.
str = "+0123456789";
code = $sscanf(str, "%g", r);
if (code !== 1) begin
$display("FAILED(g1) to parse one argument found %d", code);
pass = 1\'b0;
end
if (r != 123456789.0) begin
$display("FAILED(g1) argument value, expected 123456789.0, got %f", r);
pass = 1\'b0;
end
str = "0123456789";
code = $sscanf(str, "%g", r);
if (code !== 1) begin
$display("FAILED(g2) to parse one argument found %d", code);
pass = 1\'b0;
end
if (r != 123456789.0) begin
$display("FAILED(g2) argument value, expected 123456789.0, got %f", r);
pass = 1\'b0;
end
str = "-0123456789";
code = $sscanf(str, "%g", r);
if (code !== 1) begin
$display("FAILED(g3) to parse one argument found %d", code);
pass = 1\'b0;
end
if (r != -123456789.0) begin
$display("FAILED(g3) argument value, expected -123456789.0, got %f", r);
pass = 1\'b0;
end
// A plus or minus must have a digit after to match.
r = 1.0;
str = "-q";
code = $sscanf(str, "%g", r);
if (code !== 0) begin
$display("FAILED(g4) to parse zero arguments found %d", code);
pass = 1\'b0;
end
if (r != 1.0) begin
$display("FAILED(g4) argument value, expected 1.0, got %f", r);
pass = 1\'b0;
end
r = 1.0;
str = "+q";
code = $sscanf(str, "%g", r);
if (code !== 0) begin
$display("FAILED(g5) to parse zero arguments found %d", code);
pass = 1\'b0;
end
if (r != 1.0) begin
$display("FAILED(g5) argument value, expected 1.0, got %f", r);
pass = 1\'b0;
end
r = 1.0;
str = "q";
code = $sscanf(str, "%g", r);
if (code !== 0) begin
$display("FAILED(g6) to parse zero arguments found %d", code);
pass = 1\'b0;
end
if (r != 1.0) begin
$display("FAILED(g6) argument value, expected 1.0, got %f", r);
pass = 1\'b0;
end
// Check starting/trailing decimal point.
str = "2.";
code = $sscanf(str, "%g", r);
if (code !== 1) begin
$display("FAILED(g7) to parse one arguments found %d", code);
pass = 1\'b0;
end
if (r != 2.0) begin
$display("FAILED(g7) argument value, expected 2.0, got %f", r);
pass = 1\'b0;
end
str = ".2";
code = $sscanf(str, "%g", r);
if (code !== 1) begin
$display("FAILED(g8) to parse one arguments found %d", code);
pass = 1\'b0;
end
if (r != 0.2) begin
$display("FAILED(g8) argument value, expected 0.2, got %f", r);
pass = 1\'b0;
end
// Check with an exponent.
str = "2.e1";
code = $sscanf(str, "%g", r);
if (code !== 1) begin
$display("FAILED(g9) to parse one arguments found %d", code);
pass = 1\'b0;
end
if (r != 20.0) begin
$display("FAILED(g9) argument value, expected 20.0, got %f", r);
pass = 1\'b0;
end
str = "2.e-1";
code = $sscanf(str, "%g", r);
if (code !== 1) begin
$display("FAILED(g10) to parse one arguments found %d", code);
pass = 1\'b0;
end
if (r != 0.2) begin
$display("FAILED(g10) argument value, expected 0.2, got %f", r);
pass = 1\'b0;
end
// Check failing exponent cases.
r = 1.0;
str = "2.ea";
code = $sscanf(str, "%g", r);
if (code !== 0) begin
$display("FAILED(g11) to parse zero arguments found %d", code);
pass = 1\'b0;
end
if (r != 1.0) begin
$display("FAILED(g11) argument value, expected 1.0, got %f", r);
pass = 1\'b0;
end
r = 1.0;
str = "2.e+a";
code = $sscanf(str, "%g", r);
if (code !== 0) begin
$display("FAILED(g12) to parse zero arguments found %d", code);
pass = 1\'b0;
end
if (r != 1.0) begin
$display("FAILED(g12) argument value, expected 1.0, got %f", r);
pass = 1\'b0;
end
r = 1.0;
str = "2.e-a";
code = $sscanf(str, "%g", r);
if (code !== 0) begin
$display("FAILED(g13) to parse zero arguments found %d", code);
pass = 1\'b0;
end
if (r != 1.0) begin
$display("FAILED(g13) argument value, expected 1.0, got %f", r);
pass = 1\'b0;
end
str = "1e5000";
code = $sscanf(str, "%g", r);
if (code !== 1) begin
$display("FAILED(g14) to parse one arguments found %d", code);
pass = 1\'b0;
end
if (r != 1.0/0.0) begin
$display("FAILED(g14) argument value, expected inf, got %f", r);
pass = 1\'b0;
end
str = "-1e5000";
code = $sscanf(str, "%g", r);
if (code !== 1) begin
$display("FAILED(g14) to parse one arguments found %d", code);
pass = 1\'b0;
end
if (r != -1.0/0.0) begin
$display("FAILED(g14) argument value, expected -inf, got %f", r);
pass = 1\'b0;
end
// Check parsing time values (%t).
// The %t format uses the real code to parse the number so all the
// corner cases are tested above.
str = "+012345678925";
code = $sscanf(str, "%t", r);
if (code !== 1) begin
$display("FAILED(t1) to parse one argument found %d", code);
pass = 1\'b0;
end
if (r != 123456789.25) begin
$display("FAILED(t1) argument value, expected 123456789.25, got %f", r);
pass = 1\'b0;
end
str = "012345678925";
code = $sscanf(str, "%t", r);
if (code !== 1) begin
$display("FAILED(t2) to parse one argument found %d", code);
pass = 1\'b0;
end
if (r != 123456789.25) begin
$display("FAILED(t2) argument value, expected 123456789.25, got %f", r);
pass = 1\'b0;
end
str = "-012345678925";
code = $sscanf(str, "%t", r);
if (code !== 1) begin
$display("FAILED(t3) to parse one argument found %d", code);
pass = 1\'b0;
end
if (r != -123456789.25) begin
$display("FAILED(t3) argument value, expected -123456789.25, got %f", r);
pass = 1\'b0;
end
// Check using different scaling and rounding.
$timeformat(-9, 3, "ns", 20);
str = "10.125";
code = $sscanf(str, "%t", r);
if (code !== 1) begin
$display("FAILED(t4) to parse one argument found %d", code);
pass = 1\'b0;
end
if (r != 10.125) begin
$display("FAILED(t4) argument value, expected 10.125, got %f", r);
pass = 1\'b0;
end
str = "10.0625";
code = $sscanf(str, "%t", r);
if (code !== 1) begin
$display("FAILED(t5) to parse one argument found %d", code);
pass = 1\'b0;
end
if (r != 10.063) begin
$display("FAILED(t5) argument value, expected 10.063, got %f", r);
pass = 1\'b0;
end
str = "10.03125";
code = $sscanf(str, "%t", r);
if (code !== 1) begin
$display("FAILED(t6) to parse one argument found %d", code);
pass = 1\'b0;
end
if (r != 10.031) begin
$display("FAILED(t6) argument value, expected 10.031, got %f", r);
pass = 1\'b0;
end
$timeformat(-9, 1, "ns", 20);
str = "10.543";
code = $sscanf(str, "%t", r);
if (code !== 1) begin
$display("FAILED(t7) to parse one argument found %d", code);
pass = 1\'b0;
end
if (r != 10.5) begin
$display("FAILED(t7) argument value, expected 10.5, got %f", r);
pass = 1\'b0;
end
// Check parsing a single character (%c).
str = "t";
code = $sscanf(str, "%c", a);
if (code !== 1) begin
$display("FAILED(c) to parse one argument found %d", code);
pass = 1\'b0;
end
if (a !== 116) begin // t has an ASCII code of 116
$display("FAILED(c) argument value, expected t, got %c", a);
pass = 1\'b0;
end
// Check parsing a string value (%s).
str = "hi ho";
code = $sscanf(str, "%s %s", a, b);
if (code !== 2) begin
$display("FAILED(s) to parse two arguments found %d", code);
pass = 1\'b0;
end
if (a !== "hi") begin
$display("FAILED(s) first argument value, expected hi, got %s", a);
pass = 1\'b0;
end
if (b !== "ho") begin
$display("FAILED(s) second argument value, expected ho, got %s", b);
pass = 1\'b0;
end
// Check an empty %s match.
a = "skip";
str = " ";
code = $sscanf(str, "%s", a);
if (code !== 0) begin
$display("FAILED(ep) to parse zero arguments found %d", code);
pass = 1\'b0;
end
if (a !== "skip") begin
$display("FAILED(ep) first argument value, expected skip, got %s", a);
pass = 1\'b0;
end
// Check an empty %s second match.
b = "skip";
str = "one ";
code = $sscanf(str, "%s %s", a, b);
if (code !== 1) begin
$display("FAILED(es) to parse one arguments found %d", code);
pass = 1\'b0;
end
if (a !== "one") begin
$display("FAILED(es) first argument value, expected one, got %s", a);
pass = 1\'b0;
end
if (b !== "skip") begin
$display("FAILED(es) second argument value, expected skip, got %s", a);
pass = 1\'b0;
end
// Check parsing 2 state unformatted binary values (%u).
// Check parsing 4 state unformatted binary values (%z).
// Check geting the current module (%m).
code = $sscanf(" ", "%m", a);
if (code !== 1) begin
$display("FAILED(m) to parse two argument found %d", code);
pass = 1\'b0;
end
if (a !== "top") begin
$display("FAILED(m) first argument value, expected top, got %s", a);
pass = 1\'b0;
end
// Check a string using a width.
str = "helloworld";
code = $sscanf(str, "%5s %s", a, b);
if (code !== 2) begin
$display("FAILED(sw) to parse two argument found %d", code);
pass = 1\'b0;
end
if (a !== "hello") begin
$display("FAILED(sw) first argument value, expected hello, got %s", a);
pass = 1\'b0;
end
if (b !== "world") begin
$display("FAILED(sw) second argument value, expected world, got %s", b);
pass = 1\'b0;
end
// Check a binary using a width.
str = "01101001";
code = $sscanf(str, "%4b %b", a, b);
if (code !== 2) begin
$display("FAILED(bw) to parse two argument found %d", code);
pass = 1\'b0;
end
if (a !== \'b0110) begin
$display("FAILED(bw) first argument value, expected \'b0110, got %b", a);
pass = 1\'b0;
end
if (b !== \'b1001) begin
$display("FAILED(bw) second argument value, expected \'b1001, got %b", b);
pass = 1\'b0;
end
// Check an octal using a width.
str = "234567";
code = $sscanf(str, "%3o %o", a, b);
if (code !== 2) begin
$display("FAILED(ow) to parse two argument found %d", code);
pass = 1\'b0;
end
if (a !== \'o234) begin
$display("FAILED(ow) first argument value, expected \'o234, got %o", a);
pass = 1\'b0;
end
if (b !== \'o567) begin
$display("FAILED(ow) second argument value, expected \'o567, got %o", b);
pass = 1\'b0;
end
// Check a hex using a width.
str = "89abcdef";
code = $sscanf(str, "%4h %h", a, b);
if (code !== 2) begin
$display("FAILED(hw) to parse two argument found %d", code);
pass = 1\'b0;
end
if (a !== \'h89ab) begin
$display("FAILED(hw) first argument value, expected \'h89ab, got %h", a);
pass = 1\'b0;
end
if (b !== \'hcdef) begin
$display("FAILED(hw) second argument value, expected \'hcdef, got %h", b);
pass = 1\'b0;
end
// Check a decimal using a width.
str = "23456789";
code = $sscanf(str, "%4d %d", a, b);
if (code !== 2) begin
$display("FAILED(dw) to parse two argument found %d", code);
pass = 1\'b0;
end
if (a !== \'d2345) begin
$display("FAILED(dw) first argument value, expected \'d2345, got %d", a);
pass = 1\'b0;
end
if (b !== \'d6789) begin
$display("FAILED(dw) second argument value, expected \'d6789, got %d", b);
pass = 1\'b0;
end
// Check a real using a width.
str = "-2.2566789";
code = $sscanf(str, "%6f %d", r, a);
if (code !== 2) begin
$display("FAILED(fw1) to parse two argument found %d", code);
pass = 1\'b0;
end
if (r != -2.256) begin
$display("FAILED(fw1) first argument value, expected 2.256, got %f", r);
pass = 1\'b0;
end
if (a !== \'d6789) begin
$display("FAILED(fw1) second argument value, expected \'d6789, got %d", a);
pass = 1\'b0;
end
str = "+2.e+16789";
code = $sscanf(str, "%6f %d", r, a);
if (code !== 2) begin
$display("FAILED(fw2) to parse two argument found %d", code);
pass = 1\'b0;
end
if (r != 20.0) begin
$display("FAILED(fw2) first argument value, expected 20.0, got %f", r);
pass = 1\'b0;
end
if (a !== \'d6789) begin
$display("FAILED(fw2) second argument value, expected \'d6789, got %d", a);
pass = 1\'b0;
end
str = "-2.2566789";
code = $sscanf(str, "%6e %d", r, a);
if (code !== 2) begin
$display("FAILED(ew1) to parse two argument found %d", code);
pass = 1\'b0;
end
if (r != -2.256) begin
$display("FAILED(ew1) first argument value, expected 2.256, got %f", r);
pass = 1\'b0;
end
if (a !== \'d6789) begin
$display("FAILED(ew1) second argument value, expected \'d6789, got %d", a);
pass = 1\'b0;
end
str = "+2.e+16789";
code = $sscanf(str, "%6e %d", r, a);
if (code !== 2) begin
$display("FAILED(ew2) to parse two argument found %d", code);
pass = 1\'b0;
end
if (r != 20.0) begin
$display("FAILED(ew2) first argument value, expected 20.0, got %f", r);
pass = 1\'b0;
end
if (a !== \'d6789) begin
$display("FAILED(ew2) second argument value, expected \'d6789, got %d", a);
pass = 1\'b0;
end
str = "-2.2566789";
code = $sscanf(str, "%6g %d", r, a);
if (code !== 2) begin
$display("FAILED(gw1) to parse two argument found %d", code);
pass = 1\'b0;
end
if (r != -2.256) begin
$display("FAILED(gw1) first argument value, expected 2.256, got %f", r);
pass = 1\'b0;
end
if (a !== \'d6789) begin
$display("FAILED(gw1) second argument value, expected \'d6789, got %d", a);
pass = 1\'b0;
end
str = "+2.e+16789";
code = $sscanf(str, "%6g %d", r, a);
if (code !== 2) begin
$display("FAILED(gw2) to parse two argument found %d", code);
pass = 1\'b0;
end
if (r != 20.0) begin
$display("FAILED(gw2) first argument value, expected 20.0, got %f", r);
pass = 1\'b0;
end
if (a !== \'d6789) begin
$display("FAILED(gw2) second argument value, expected \'d6789, got %d", a);
pass = 1\'b0;
end
// Check a time using a width.
$timeformat(-9, 3, "ns", 20);
str = "-2.2566789";
code = $sscanf(str, "%6t %d", r, a);
if (code !== 2) begin
$display("FAILED(tw1) to parse two argument found %d", code);
pass = 1\'b0;
end
if (r != -2.256) begin
$display("FAILED(tw1) first argument value, expected 2.256, got %f", r);
pass = 1\'b0;
end
if (a !== \'d6789) begin
$display("FAILED(tw1) second argument value, expected \'d6789, got %d", a);
pass = 1\'b0;
end
str = "+2.e+16789";
code = $sscanf(str, "%6t %d", r, a);
if (code !== 2) begin
$display("FAILED(tw2) to parse two argument found %d", code);
pass = 1\'b0;
end
if (r != 20.0) begin
$display("FAILED(tw2) first argument value, expected 20.0, got %f", r);
pass = 1\'b0;
end
if (a !== \'d6789) begin
$display("FAILED(tw2) second argument value, expected \'d6789, got %d", a);
pass = 1\'b0;
end
// Check a suppressed string.
str = "hello bad world";
code = $sscanf(str, "%s %*s %s", a, b);
if (code !== 2) begin
$display("FAILED(ss) to parse two argument found %d", code);
pass = 1\'b0;
end
if (a !== "hello") begin
$display("FAILED(sw) first argument value, expected hello, got %s", a);
pass = 1\'b0;
end
if (b !== "world") begin
$display("FAILED(sw) second argument value, expected world, got %s", b);
pass = 1\'b0;
end
// Check a suppressed binary.
str = "0110 xxz 1001";
code = $sscanf(str, "%b %*b %b", a, b);
if (code !== 2) begin
$display("FAILED(bs) to parse two argument found %d", code);
pass = 1\'b0;
end
if (a !== \'b0110) begin
$display("FAILED(bs) first argument value, expected \'b0110, got %b", a);
pass = 1\'b0;
end
if (b !== \'b1001) begin
$display("FAILED(bs) second argument value, expected \'b1001, got %b", b);
pass = 1\'b0;
end
// Check a suppressed octal.
str = "234 xxz 567";
code = $sscanf(str, "%o %*o %o", a, b);
if (code !== 2) begin
$display("FAILED(os) to parse two argument found %d", code);
pass = 1\'b0;
end
if (a !== \'o234) begin
$display("FAILED(os) first argument value, expected \'o234, got %o", a);
pass = 1\'b0;
end
if (b !== \'o567) begin
$display("FAILED(os) second argument value, expected \'o567, got %o", b);
pass = 1\'b0;
end
// Check a suppressed hex.
str = "89ab xz CDEF";
code = $sscanf(str, "%h %*h %h", a, b);
if (code !== 2) begin
$display("FAILED(hs) to parse two argument found %d", code);
pass = 1\'b0;
end
if (a !== \'h89ab) begin
$display("FAILED(hs) first argument value, expected \'h89ab, got %h", a);
pass = 1\'b0;
end
if (b !== \'hcdef) begin
$display("FAILED(hs) second argument value, expected \'hcdef, got %h", b);
pass = 1\'b0;
end
// Check a suppressed decimal.
str = "2345 x 6789";
code = $sscanf(str, "%d %*d %d", a, b);
if (code !== 2) begin
$display("FAILED(ds) to parse two argument found %d", code);
pass = 1\'b0;
end
if (a !== \'d2345) begin
$display("FAILED(ds) first argument value, expected \'d2345, got %d", a);
pass = 1\'b0;
end
if (b !== \'d6789) begin
$display("FAILED(ds) second argument value, expected \'d6789, got %d", b);
pass = 1\'b0;
end
// Check a suppressed real.
str = "2345 1.0 2.0";
code = $sscanf(str, "%d %*f %f", a, r);
if (code !== 2) begin
$display("FAILED(fs) to parse two argument found %d", code);
pass = 1\'b0;
end
if (a !== \'d2345) begin
$display("FAILED(fs) first argument value, expected \'d2345, got %d", a);
pass = 1\'b0;
end
if (r != 2.0) begin
$display("FAILED(fs) second argument value, expected 2.0, got %f", r);
pass = 1\'b0;
end
str = "2345 1.0 2.0";
code = $sscanf(str, "%d %*e %e", a, r);
if (code !== 2) begin
$display("FAILED(es) to parse two argument found %d", code);
pass = 1\'b0;
end
if (a !== \'d2345) begin
$display("FAILED(es) first argument value, expected \'d2345, got %d", a);
pass = 1\'b0;
end
if (r != 2.0) begin
$display("FAILED(es) second argument value, expected 2.0, got %f", r);
pass = 1\'b0;
end
str = "2345 1.0 2.0";
code = $sscanf(str, "%d %*g %g", a, r);
if (code !== 2) begin
$display("FAILED(gs) to parse two argument found %d", code);
pass = 1\'b0;
end
if (a !== \'d2345) begin
$display("FAILED(gs) first argument value, expected \'d2345, got %d", a);
pass = 1\'b0;
end
if (r != 2.0) begin
$display("FAILED(gs) second argument value, expected 2.0, got %f", r);
pass = 1\'b0;
end
// Check a suppressed time.
str = "2345 1.0 2.0";
code = $sscanf(str, "%d %*t %t", a, r);
if (code !== 2) begin
$display("FAILED(ts) to parse two argument found %d", code);
pass = 1\'b0;
end
if (a !== \'d2345) begin
$display("FAILED(ts) first argument value, expected \'d2345, got %d", a);
pass = 1\'b0;
end
if (r != 2.0) begin
$display("FAILED(ts) second argument value, expected 2.0, got %f", r);
pass = 1\'b0;
end
// Check matching normal characters. Also check %%.
str = "test% str";
code = $sscanf(str, "test%% %s", a);
if (code !== 1) begin
$display("FAILED(nc) to parse one argument found %d", code);
pass = 1\'b0;
end
if (a !== "str") begin
$display("FAILED(nc) first argument value, expected str, got %s", a);
pass = 1\'b0;
end
// Check different spacing issues, tab, leading space, extra space, etc.
str = " one \\t\
\ttwo ";
code = $sscanf(str, "%s %s", a, b);
if (code !== 2) begin
$display("FAILED(sp) to parse two arguments found %d", code);
pass = 1\'b0;
end
if (a !== "one") begin
$display("FAILED(sp) first argument value, expected one, got %s", a);
pass = 1\'b0;
end
if (b !== "two") begin
$display("FAILED(sp) second argument value, expected two, got %s", b);
pass = 1\'b0;
end
// Check for a failing match.
a = \'bx;
b = \'bx;
str = "BAD";
code = $sscanf(str, "GOOD %s %s", a, b);
if (code !== 0) begin
$display("FAILED(fl) to parse bad match arguments found %d", code);
pass = 1\'b0;
end
if (a !== \'bx) begin
$display("FAILED(fl) first argument value, expected \'bx, got %b", a);
pass = 1\'b0;
end
if (b !== \'bx) begin
$display("FAILED(fl) second argument value, expected \'bx, got %b", b);
pass = 1\'b0;
end
b = \'bx;
str = "a ";
// Check a failing character match at EOF.
code = $sscanf(str, "%s %c", a, b);
if (code !== 1) begin
$display("FAILED(fle) character at end, expected one found %d", code);
pass = 1\'b0;
end
if (a !== "a") begin
$display("FAILED(fle) first argument value, expected a, got %s", a);
pass = 1\'b0;
end
if (b !== \'bx) begin
$display("FAILED(fle) second argument value, expected \'bx, got %b", b);
pass = 1\'b0;
end
// Check for no match.
a = \'bx;
b = \'bx;
str = "";
code = $sscanf(str, "GOOD %s %s", a, b);
if (code !== -1) begin
$display("FAILED(no) to parse no match arguments found %d", code);
pass = 1\'b0;
end
if (a !== \'bx) begin
$display("FAILED(no) first argument value, expected \'bx, got %s", a);
pass = 1\'b0;
end
if (b !== \'bx) begin
$display("FAILED(no) second argument value, expected \'bx, got %s", b);
pass = 1\'b0;
end
// Check for an undefined conversion string.
a = \'bx;
str = "foo";
code = $sscanf(str, \'bx, a);
if (code !== -1) begin
$display("FAILED(udef) to parse undefined string returned %d", code);
pass = 1\'b0;
end
if (a !== \'bx) begin
$display("FAILED(udef) first argument value, expected \'bx, got %s", a);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
/*
* Copyright (c) 2002 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
initial begin
fork :fork_label
\t#100 disable fork_label;
\t#200 begin
\t $display("FAILED -- shouldn\'t get here");
\t $finish;
\tend
join
$display("PASSED");
end
endmodule // main
|
/*
* Copyright (c) 1998-2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
parameter PARM08 = 8;
parameter PARM04 = PARM08 >> 1;
parameter PARM16 = PARM08 << 1;
parameter PARM10 = ((PARM08 <=2) ? 1:
((PARM08 <=4) ? 2:
((PARM08 <=8) ? 3:4)));
// this parameterized input compiles ok
wire [PARM04 : 0] in04;
wire [PARM16 : 0] in05;
reg [PARM08 : 0] out00;
reg [PARM04 : 0] out04;
reg [PARM16 : 0] out05;
// this parameterized doesn\'t compile, stack dump
wire [PARM10:0] in99;
initial begin
if (PARM08 !== 8) begin
\t $display("FAILED -- PARM08 == %b", PARM08);
\t $finish;
end
if (PARM04 !== 4) begin
\t $display("FAILED -- PARM04 == %b", PARM04);
\t $finish;
end
if (PARM16 !== 16) begin
\t $display("FAILED -- PARM16 == %b", PARM16);
\t $finish;
end
if (PARM10 !== 3) begin
\t $display("FAILED -- PARM10 == %b", PARM10);
\t $finish;
end
$display("PASSED");
end
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.will need a Picture Elements Binary Software
* License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program demonstrates the mixing of reg and memories in l-value
* contatenations.
*/
module main;
reg [3:0] mem [2:0];
reg\t a, b;
initial begin
mem[0] = 0;
mem[1] = 0;
mem[2] = 0;
{b, mem[1], a} <= 6\'b0_0000_1;
#1
if (a !== 1\'b1) begin
\t $display("FAILED -- a = %b", a);
\t $finish;
end
if (mem[1] !== 4\'b0000) begin
\t $display("FAILED -- mem[1] = %b", mem[1]);
\t $finish;
end
if (b !== 1\'b0) begin
\t $display("FAILED -- b = %b", b);
\t $finish;
end
{b, mem[1], a} <= 6\'b0_1111_0;
#1
if (a !== 1\'b0) begin
\t $display("FAILED -- a = %b", a);
\t $finish;
end
if (mem[0] !== 4\'b0000) begin
\t $display("FAILED -- mem[0] - %b", mem[0]);
\t $finish;
end
if (mem[1] !== 4\'b1111) begin
\t $display("FAILED -- mem[1] = %b", mem[1]);
\t $finish;
end
if (b !== 1\'b0) begin
\t $display("FAILED -- b = %b", b);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
// Check that blocking partial writes to a 2-state vector array element are
// correctly handlded.
module test;
reg failed = 1\'b0;
`define check(val, exp) \\
if (exp !== val) begin \\
$display("FAILED. Got %b, expected %b.", val, exp); \\
failed = 1\'b1; \\
end
bit [3:0] x[1:0];
integer i;
initial begin
// Immediate index
// Within bounds
x[0] = \'h0;
x[0][2:1] = 2\'b10;
`check(x[0], 4\'b0100)
// Partially oob at high and low side
x[0] = \'h0;
x[0][4:-1] = 6\'b101010;
`check(x[0], 4\'b0101)
// Partially oob at low side
x[0] = \'h0;
x[0][0:-1] = 2\'b10;
`check(x[0], 4\'b0001)
// Partially oob at high side
x[0] = \'h0;
x[0][4:3] = 2\'b01;
`check(x[0], 4\'b1000)
// Fully oob at low side
x[0] = \'h0;
x[0][-1:-2] = 2\'b11;
`check(x[0], 4\'b0000)
// Fully oob at high side
x[0] = \'h0;
x[0][6:5] = 2\'b11;
`check(x[0], 4\'b0000)
// Variable index
// Within bounds
i = 1;
x[0] = \'h0;
x[0][i+:2] = 2\'b10;
`check(x[0], 4\'b0100)
// Partially oob at high and low side
i = -1;
x[0] = \'h0;
x[0][i+:6] = 6\'b101010;
`check(x[0], 4\'b0101)
// Partially oob at low side
i = -1;
x[0] = \'h0;
x[0][i+:2] = 2\'b10;
`check(x[0], 4\'b0001)
// Partially oob at high side
i = 3;
x[0] = \'h0;
x[0][i+:2] = 2\'b01;
`check(x[0], 4\'b1000)
// Fully oob at low side
i = -2;
x[0] = \'h0;
x[0][i+:2] = 2\'b11;
`check(x[0], 4\'b0000)
// Fully oob at high side
i = 5;
x[0] = \'h0;
x[0][i+:2] = 2\'b11;
`check(x[0], 4\'b0000)
// Undefined index
i = \'hx;
x[0] = \'h0;
x[0][i+:2] = 2\'b11;
`check(x[0], 4\'b0000)
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
module test (a, b);
output [31 : 0] a;
input b;
buf bufd[31:0] (a, b);
initial#1 $display("PASSED");
specify
specparam
th = 0.9;
// This incomplete set of specify cases needs to be handled.
if (!b)
(b *> a[0]) = (0);
endspecify
endmodule
|
module test;
reg pass;
reg [8*40:1] str;
integer s;
reg [31:0] su;
integer res;
initial begin
pass = 1\'b1;
s = 2000;
su = 2000;
res = s + (1 << 3) - 1;
if (res !== 2007) begin
$display("FAILED first term << (s), expected 2007, got %d", res);
pass = 1\'b0;
end
res = su + (1 << 3) - 1;
if (res !== 2007) begin
$display("FAILED first term << (su), expected 2007, got %d", res);
pass = 1\'b0;
end
res = s + (16 >> 1) - 1;
if (res !== 2007) begin
$display("FAILED first term >> (s), expected 2007, got %d", res);
pass = 1\'b0;
end
res = su + (16 >> 1) - 1;
if (res !== 2007) begin
$display("FAILED first term >> (su), expected 2007, got %d", res);
pass = 1\'b0;
end
res = (s + (1 << 3) - 1) * 16000;
if (res !== 32112000) begin
$display("FAILED second term << (s), expected 32112000, got %d", res);
pass = 1\'b0;
end
res = (su + (1 << 3) - 1) * 16000;
if (res !== 32112000) begin
$display("FAILED second term << (su), expected 32112000, got %d", res);
pass = 1\'b0;
end
res = (s + (16 >> 1) - 1) * 16000;
if (res !== 32112000) begin
$display("FAILED second term >> (s), expected 32112000, got %d", res);
pass = 1\'b0;
end
res = (su + (16 >> 1) - 1) * 16000;
if (res !== 32112000) begin
$display("FAILED second term >> (su), expected 32112000, got %d", res);
pass = 1\'b0;
end
$sformat(str, "%0d", s + (1 << 3) - 1);
if (str[8*4:1] !== "2007" || str[8*40:8*4+1] !== 0) begin
$display("FAILED first string << (s), expected \\"2007\\", got %s", str);
pass = 1\'b0;
end
$sformat(str, "%0d", su + (1 << 3) - 1);
if (str[8*4:1] !== "2007" || str[8*40:8*4+1] !== 0) begin
$display("FAILED first string << (su), expected \\"2007\\", got %s", str);
pass = 1\'b0;
end
$sformat(str, "%0d", s + (16 >> 1) - 1);
if (str[8*4:1] !== "2007" || str[8*40:8*4+1] !== 0) begin
$display("FAILED first string >> (s), expected \\"2007\\", got %s", str);
pass = 1\'b0;
end
$sformat(str, "%0d", su + (16 >> 1) - 1);
if (str[8*4:1] !== "2007" || str[8*40:8*4+1] !== 0) begin
$display("FAILED first string >> (su), expected \\"2007\\", got %s", str);
pass = 1\'b0;
end
$sformat(str, "%0d", (s + (1 << 3) - 1) * 16000);
if (str[8*8:1] !== "32112000" || str[8*40:8*8+1] !== 0) begin
$display("FAILED second string << (s), expected \\"32112000\\", got %s",
str);
pass = 1\'b0;
end
$sformat(str, "%0d", (su + (1 << 3) - 1) * 16000);
if (str[8*8:1] !== "32112000" || str[8*40:8*8+1] !== 0) begin
$display("FAILED second string << (su), expected \\"32112000\\", got %s",
str);
pass = 1\'b0;
end
$sformat(str, "%0d", (s + (16 >> 1) - 1) * 16000);
if (str[8*8:1] !== "32112000" || str[8*40:8*8+1] !== 0) begin
$display("FAILED second string >> (s), expected \\"32112000\\", got %s",
str);
pass = 1\'b0;
end
$sformat(str, "%0d", (su + (16 >> 1) -1) * 16000);
if (str[8*8:1] !== "32112000" || str[8*40:8*8+1] !== 0) begin
$display("FAILED second string >> (su), expected \\"32112000\\", got %s",
str);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
`timescale 1ns/10ps
module top;
reg a, pass;
wire z;
time edge_time;
always @(z) begin
if ((z === 0) && (($time - edge_time) != 3)) begin
$display("Falling took %d, expected 3", $time - edge_time);
pass = 1\'b0;
end
if ((z === 1) && (($time - edge_time) != 2)) begin
$display("Rising took %d, expected 2", $time - edge_time);
pass = 1\'b0;
end
end
initial begin
pass = 1\'b1;
$sdf_annotate("ivltests/sdf_del.sdf", top);
#10;
edge_time = $time;
a = 1\'b0;
#10;
edge_time = $time;
a = 1\'b1;
#10 if (pass) $display("PASSED");
end
my_buf dut(z, a);
endmodule
module my_buf (output z, input a);
buf (z, a);
specify
(a => z) = (0, 0);
endspecify
endmodule
|
module top;
reg [1:0] q;
reg [4:0] icim[1:0];
integer j;
always @(q) begin
/*
* The following line had the muli problem, the other line has a
* different problem.
*/
icim[0] <= #1 0 + 8 * (0 >> q);
icim[1] <= #1 1 + 8 * (1 >> q);
end
initial begin
q = 2\'d1;
#2;
if (icim[0] !== 0) begin
\t $display("FAILED");
\t $finish;
end
if (icim[1] !== 1) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
end
endmodule
|
// Check that all parameters in a parameter port list after a `localparam` get
// elaborated as localparams, until the next `parameter`.
module a #(
parameter A = 1, B = 2,
localparam C = 3, D = 4,
parameter E = 5
);
initial begin
if (A == 10 && B == 20 && C == 3 && D == 4 && E == 50) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
module b;
a #(
.A(10),
.B(20),
// Cannot override localparam .C(30),
// Cannot override localparam .D(40),
.E(50)
) i_a();
endmodule
|
// This is the most trivial example of a program block.
// It contains only an initial statement and final statement,
// and prints "PASSED" so the test bench knows that it works.
program main ();
initial $display("Hello, World.");
final $display("PASSED");
endprogram : main
|
module foo ();
parameter CLOCK_FREQUENCY = 90e6;
// CLOCK_PERIOD_BIT_WIDTH <= log2(90e6)
// log2(90e6) = 26.423
parameter CLOCK_PERIOD_BIT_WIDTH = 26;
// build something big enaugh to hold CLOCK_FREQUENCY x CLOCK_PERIOD_BIT_WIDTH sums.
parameter CP_SUM_BIT_WIDTH = 2 * CLOCK_PERIOD_BIT_WIDTH;
//
// calculate a sane reset value.
//
wire [CLOCK_PERIOD_BIT_WIDTH-1:0] rst, rst2;
assign rst = {1\'d1, {CP_SUM_BIT_WIDTH-1 {1\'d0}}} / CLOCK_FREQUENCY;
assign rst2 = (52\'d2**(CP_SUM_BIT_WIDTH-1)) / CLOCK_FREQUENCY;
initial
#1 if (rst == rst2) $display("PASSED");
else $display("FAILED");
endmodule // foo
|
// This tests unalligned write/read access to packed structures
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module test;
typedef struct packed {
logic [7:0] high;
logic [7:0] low;
} word_t;
// Declare word* as a VARIABLE
wire word_t word_se0, word_se1, word_se2, word_se3;
wire word_t word_sw0, word_sw1, word_sw2, word_sw3;
wire word_t word_sp0, word_sp1, word_sp2, word_sp3;
wire word_t word_ep0, word_ep1, word_ep2, word_ep3;
// error counter
bit err = 0;
// access to structure elements
assign word_se1.high = {8+0{1\'b1}};
assign word_se1.low = {8+0{1\'b0}};
assign word_se2.high = {8+1{1\'b1}};
assign word_se2.low = {8+1{1\'b0}};
assign word_se3.high = {8-1{1\'b1}};
assign word_se3.low = {8-1{1\'b0}};
// access to whole structure
assign word_sw1 = {16+0{1\'b1}};
assign word_sw2 = {16+1{1\'b1}};
assign word_sw3 = {16-1{1\'b1}};
// access to parts of structure elements
assign word_ep1.high [3:0] = {4+0{1\'b1}};
assign word_ep1.low [3:0] = {4+0{1\'b0}};
assign word_ep2.high [3:0] = {4+1{1\'b1}};
assign word_ep2.low [3:0] = {4+1{1\'b0}};
assign word_ep3.high [3:0] = {4-1{1\'b1}};
assign word_ep3.low [3:0] = {4-1{1\'b0}};
// access to parts of the whole structure
assign word_sp1 [11:4] = {8+0{1\'b1}};
assign word_sp2 [11:4] = {8+1{1\'b1}};
assign word_sp3 [11:4] = {8-1{1\'b1}};
initial begin
#1;
// access to structure elements
if (word_se0 !== 16\'bzzzzzzzz_zzzzzzzz) begin $display("FAILED -- word_se0 = \'b%b", word_se0 ); err=1; end
if (word_se1 !== 16\'b11111111_00000000) begin $display("FAILED -- word_se1 = \'b%b", word_se1 ); err=1; end
if (word_se1.high !== 8\'b11111111 ) begin $display("FAILED -- word_se1.high = \'b%b", word_se1.high); err=1; end
if (word_se1.low !== 8\'b00000000 ) begin $display("FAILED -- word_se1.low = \'b%b", word_se1.low ); err=1; end
if (word_se2 !== 16\'b11111111_00000000) begin $display("FAILED -- word_se2 = \'b%b", word_se2 ); err=1; end
if (word_se2.high !== 8\'b11111111 ) begin $display("FAILED -- word_se2.high = \'b%b", word_se2.high); err=1; end
if (word_se2.low !== 8\'b00000000 ) begin $display("FAILED -- word_se2.low = \'b%b", word_se2.low ); err=1; end
if (word_se3 !== 16\'b01111111_00000000) begin $display("FAILED -- word_se3 = \'b%b", word_se3 ); err=1; end
if (word_se3.high !== 8\'b01111111 ) begin $display("FAILED -- word_se3.high = \'b%b", word_se3.high); err=1; end
if (word_se3.low !== 8\'b00000000 ) begin $display("FAILED -- word_se3.low = \'b%b", word_se3.low ); err=1; end
// access to whole structure
if (word_sw0 !== 16\'bzzzzzzzz_zzzzzzzz) begin $display("FAILED -- word_sw0 = \'b%b", word_sw0 ); err=1; end
if (word_sw1 !== 16\'b11111111_11111111) begin $display("FAILED -- word_sw1 = \'b%b", word_sw1 ); err=1; end
if (word_sw2 !== 16\'b11111111_11111111) begin $display("FAILED -- word_sw2 = \'b%b", word_sw2 ); err=1; end
if (word_sw3 !== 16\'b01111111_11111111) begin $display("FAILED -- word_sw3 = \'b%b", word_sw3 ); err=1; end
// access to parts of structure elements
if (word_ep0 !== 16\'bzzzzzzzz_zzzzzzzz) begin $display("FAILED -- word_ep0 = \'b%b", word_ep0 ); err=1; end
if (word_ep1 !== 16\'bzzzz1111_zzzz0000) begin $display("FAILED -- word_ep1 = \'b%b", word_ep1 ); err=1; end
if (word_ep1.high !== 8\'bzzzz1111 ) begin $display("FAILED -- word_ep1.high = \'b%b", word_ep1.high); err=1; end
if (word_ep1.low !== 8\'bzzzz0000 ) begin $display("FAILED -- word_ep1.low = \'b%b", word_ep1.low ); err=1; end
if (word_ep2 !== 16\'bzzzz1111_zzzz0000) begin $display("FAILED -- word_ep2 = \'b%b", word_ep2 ); err=1; end
if (word_ep2.high !== 8\'bzzzz1111 ) begin $display("FAILED -- word_ep2.high = \'b%b", word_ep2.high); err=1; end
if (word_ep2.low !== 8\'bzzzz0000 ) begin $display("FAILED -- word_ep2.low = \'b%b", word_ep2.low ); err=1; end
if (word_ep3 !== 16\'bzzzz0111_zzzz0000) begin $display("FAILED -- word_ep3 = \'b%b", word_ep3 ); err=1; end
if (word_ep3.high !== 8\'bzzzz0111 ) begin $display("FAILED -- word_ep3.high = \'b%b", word_ep3.high); err=1; end
if (word_ep3.low !== 8\'bzzzz0000 ) begin $display("FAILED -- word_ep3.low = \'b%b", word_ep3.low ); err=1; end
// access to parts of the whole structure
if (word_sp0 !== 16\'bzzzzzzzz_zzzzzzzz) begin $display("FAILED -- word_sp0 = \'b%b", word_sp0 ); err=1; end
if (word_sp1 !== 16\'bzzzz1111_1111zzzz) begin $display("FAILED -- word_sp1 = \'b%b", word_sp1 ); err=1; end
if (word_sp2 !== 16\'bzzzz1111_1111zzzz) begin $display("FAILED -- word_sp2 = \'b%b", word_sp2 ); err=1; end
if (word_sp3 !== 16\'bzzzz0111_1111zzzz) begin $display("FAILED -- word_sp3 = \'b%b", word_sp3 ); err=1; end
if (!err) $display("PASSED");
end
endmodule // test
|
// Check that declaring a real typed non-ANSI module port for a signal that was
// previously declared as a variable is an error. Even if the types for both
// declarations are the same.
module test(x);
real x;
output real x;
endmodule
|
// Test concatenation inside a constant function
module constfunc14();
function [7:0] concat1(input [7:0] value);
reg [3:0] tmp1;
reg [3:0] tmp2;
begin
{tmp1, tmp2} = {value[3:0], value[7:4]};
{concat1[3:0], concat1[7:4]} = {tmp2, tmp1};
end
endfunction
function [7:0] concat2(input [7:0] value);
reg [2:0] tmp1;
reg [3:0] tmp2;
begin
{tmp1, tmp2} = {value[3:0], value[7:4]};
{concat2[3:0], concat2[7:4]} = {tmp2, tmp1};
end
endfunction
function [7:0] concat3(input [7:0] value);
reg signed [2:0] tmp1;
reg signed [2:0] tmp2;
begin
{tmp1, tmp2} = {value[2:0], value[6:4]};
concat3[7:4] = tmp1;
concat3[3:0] = tmp2;
end
endfunction
localparam res1 = concat1(8\'h5a);
localparam res2 = concat2(8\'h5a);
localparam res3 = concat3(8\'h5a);
reg failed = 0;
initial begin
$display("%h", res1); if (res1 !== 8\'ha5) failed = 1;
$display("%h", res2); if (res2 !== 8\'ha2) failed = 1;
$display("%h", res3); if (res3 !== 8\'h2d) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
`timescale 1us/100ns
module top;
reg pass = 1\'b1;
real ra = 1.0;
wire real rufunc;
assign #10 rufunc = rl_func(ra);
initial begin
#1 if (rufunc == 2.0) begin
pass = 1\'b0;
$display("Real: user function value (%f) not delayed.", rufunc);
end
#8 if (rufunc == 2.0) begin
pass = 1\'b0;
$display("Real: user function value (%f) not delayed.", rufunc);
end
#2;
if (rufunc != 2.0) begin
pass = 1\'b0;
$display("Real: user function value not delayed correctly.");
end
if (pass) $display("PASSED");
end
function real rl_func;
input real in;
rl_func = in * 2.0;
endfunction
endmodule
|
// Check that the signedness of the element type of a queue is correctly handled
// whenn calling one of the pop methods with parenthesis.
module test;
bit failed = 1\'b0;
`define check(x) \\
if (!(x)) begin \\
$display("FAILED(%0d): ", `__LINE__, `"x`"); \\
failed = 1\'b1; \\
end
int unsigned x = 10;
int y = 10;
int z;
longint w;
shortint qs[$];
bit [15:0] qu[$];
initial begin
for (int i = 0; i < 16; i++) begin
qu.push_back(-1);
qs.push_back(-1);
end
// These all evaluate as signed
`check($signed(qu.pop_back) < 0)
`check(qs.pop_back < 0)
`check($signed(qu.pop_front) < 0)
`check(qs.pop_front < 0)
// These all evaluate as unsigned
`check(qu.pop_back > 0)
`check({qs.pop_back} > 0)
`check($unsigned(qs.pop_back) > 0)
`check(qs.pop_back > 16\'h0)
`check(qu.pop_front > 0)
`check({qs.pop_front} > 0)
`check($unsigned(qs.pop_front) > 0)
`check(qs.pop_front > 16\'h0)
// In arithmetic expressions if one operand is unsigned all operands are
// considered unsigned
z = qu.pop_back + x;
`check(z === 65545)
z = qu.pop_back + y;
`check(z === 65545)
z = qu.pop_front + x;
`check(z === 65545)
z = qu.pop_front + y;
`check(z === 65545)
z = qs.pop_back + x;
`check(z === 65545)
z = qs.pop_back + y;
`check(z === 9)
z = qs.pop_front + x;
`check(z === 65545)
z = qs.pop_front + y;
`check(z === 9)
// For ternary operators if one operand is unsigned the result is unsigend
z = x ? qu.pop_back : x;
`check(z === 65535)
z = x ? qu.pop_back : y;
`check(z === 65535)
z = x ? qu.pop_front : x;
`check(z === 65535)
z = x ? qu.pop_front : y;
`check(z === 65535)
z = x ? qs.pop_back : x;
`check(z === 65535)
z = x ? qs.pop_back : y;
`check(z === -1)
z = x ? qs.pop_front : x;
`check(z === 65535)
z = x ? qs.pop_front : y;
`check(z === -1)
// Size return value is always positive, but check that it gets padded
// properly
w = x ? qu.size : 64\'h123;
`check(w === 64\'h4)
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
package my_package;
parameter p1 = 1;
localparam p2 = 2;
typedef logic [1:0] word;
word v;
event e;
endpackage
module test();
import my_package::*;
word my_v;
initial begin
@(e) v = p1 + p2;
end
parameter p1 = 3;
localparam p2 = 4;
typedef logic [7:0] word;
word v;
event e;
endmodule
|
module test;
wire [7:0] val[3:0];
genvar i;
for (i = 3; i >= 0; i--) begin
assign val[i] = i;
end
integer j;
reg failed = 0;
initial begin
for (j = 3; j >= 0; j = j - 1) begin
$display(val[j]);
if (val[j] != j) failed = 1;
end
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module test();
wire [7:0] value1;
wire [7:0] value2;
assign value1[3:0] = 4\'d2;
bufif1 buffer[7:0](value2, value1, 1\'b1);
initial begin
#2 $display("%b %b", value1, value2);
if (value2 === 8\'bxxxx0010)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: function calling function validated
//
// D: Instantiate a 2 functions, with the 2nd calling
// D: the first. Validate the results are correct.
//
module main ();
reg [3:0] global_reg;
reg [3:0] result;
// Instantiate the function to be called
function [3:0] my_func_2;
input [3:0] a;
begin
my_func_2 = a;
end
endfunction
// This is the calling function
function [3:0] my_func_1 ;
input [3:0] a;
begin
my_func_1 = my_func_2(a) + my_func_2(a); // So call it twice!
end
endfunction
initial
begin
global_reg = 2;
result = my_func_1(global_reg);
if(result != 4)
begin
$display("FAILED - function didn\'t function!\
");
$finish ;
end
$display("PASSED\
");
$finish ;
end
endmodule
|
`begin_keywords "1364-2005"
module top;
reg [20*8-1:0] var;
integer fp, code;
initial begin
fp = $fopenr("read");
if (fp != 0) $display("Read of empty file failed.");
fp = $fopenw("work/test.txt");
$fdisplay(fp, "From the write.");
$fclose(fp);
fp = $fopena("work/test.txt");
$fdisplay(fp, "From the append.");
$fclose(fp);
fp = $fopenr("work/test.txt");
code = $fgets(var, fp);
$display("%0s", var[20*8-1:8]);
code = $fgets(var, fp);
$display("%0s", var[20*8-1:8]);
$fclose(fp);
end
endmodule
`end_keywords
|
module forBug();
integer i;
integer j;
initial
begin
\t// This loop sets i=4 .. -1 which is an error
\tfor (i=4; i>-1; i=i-1)
\t $display("i=%d",i);
\t// This loop sets j=4 .. 0 which is correct.
\tfor (j=4; j>=0; j=j-1)
\t $display("j=%d",j);
end
endmodule // forBug
|
/* I expected that p1=p2. But the generated output looks like:
Icarus Verilog version 0.7
Copyright 1998-2003 Stephen Williams
$Name: $
0 p1=x p2=StX
5 p1=1 p2=StX
10 p1=0 p2=St0
15 p1=1 p2=St0
20 p1=0 p2=St0
25 p1=1 p2=St0
30 p1=0 p2=St0
35 p1=1 p2=St0
40 p1=0 p2=St0
45 p1=1 p2=St0
50 p1=0 p2=St0
55 p1=1 p2=St0
60 p1=0 p2=St0
65 p1=1 p2=St0
70 p1=0 p2=St0
75 p1=1 p2=St0
80 p1=0 p2=St0
85 p1=1 p2=St0
90 p1=0 p2=St0
95 p1=1 p2=St0
Model Technology ModelSim SE vsim 5.7c Simulator 2003.03 Mar 13 2003
# 0 p1=x p2=StX
# 5 p1=1 p2=StX
# 10 p1=0 p2=St0
# 15 p1=1 p2=St0
# 20 p1=0 p2=St0
# 25 p1=1 p2=St0
# 30 p1=0 p2=St0
# 35 p1=1 p2=St0
# 40 p1=0 p2=St0
# 45 p1=1 p2=St0
# 50 p1=0 p2=St0
# 55 p1=1 p2=St0
# 60 p1=0 p2=St0
# 65 p1=1 p2=St0
# 70 p1=0 p2=St0
# 75 p1=1 p2=St0
# 80 p1=0 p2=St0
# 85 p1=1 p2=St0
# 90 p1=0 p2=St0
# 95 p1=1 p2=St0
#
*/
`timescale 1 ns / 1 ns
module pulse;
reg p1,p2;
initial
begin
$monitor("%t p1=%b p2=%v",$time,p1,p2);
#101 $finish(0);
end
initial
repeat(10)
begin
#5 p1=1\'b1;
#5 p1=1\'b0;
end
initial
repeat(10) single_pulse(p2);
task single_pulse;
output p;
begin
#5 p=1\'b1;
#5 p=1\'b0;
end
endtask
endmodule
|
module ornor4(output wire O_OR, output wire O_NOR,
\t input wire I0, I1, I2, I3);
assign O_OR = | {I0, I1, I2, I3};
assign O_NOR = ~| {I0, I1, I2, I3};
endmodule // ornor4
|
// Copyright (c) 2016 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test special character enums (LF, CR).
module vhdl_lfcr_test;
vhdl_lfcr dut();
// we do not need anything more
endmodule
|
/*
* Copyright (c) 1998-2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* SDW: This verifies the bit equivalence expr in a parameter
*/
module test;
parameter A0 = (3\'b1zx === 3\'b1zx);
initial
begin
if(A0 !== 1\'b1)
$display("FAILED - Expression equivalence fails in a parameter.");
else
$display("PASSED");
end
endmodule
|
// Check the power operator (run time).
module top;
reg pass;
integer res;
reg signed [31:0] l, r;
initial begin
pass = 1\'b1;
// Check the constant ** with various arguments (table 5-6 1364-2005).
l = -3;
r = \'bx;
res = l**r;
if (res !== \'bx) begin
$display("Failed: constant -3**\'bx, expected \'bx, got %0d", res);
pass = 1\'b0;
end
l = -1;
res = l**r;
if (res !== \'bx) begin
$display("Failed: constant -1**\'bx, expected \'bx, got %0d", res);
pass = 1\'b0;
end
l = 0;
res = l**r;
if (res !== \'bx) begin
$display("Failed: constant 0**\'bx, expected \'bx, got %0d", res);
pass = 1\'b0;
end
l = 1;
res = l**r;
if (res !== \'bx) begin
$display("Failed: constant 1**\'bx, expected \'bx, got %0d", res);
pass = 1\'b0;
end
l = 3;
res = l**r;
if (res !== \'bx) begin
$display("Failed: constant 3**\'bx, expected \'bx, got %0d", res);
pass = 1\'b0;
end
l = \'bx;
r=-3;
res = l**r;
if (res !== \'bx) begin
$display("Failed: constant \'bx**-3, expected \'bx, got %0d", res);
pass = 1\'b0;
end
r=-2;
res = l**r;
if (res !== \'bx) begin
$display("Failed: constant \'bx**-2, expected \'bx, got %0d", res);
pass = 1\'b0;
end
r=-1;
res = l**r;
if (res !== \'bx) begin
$display("Failed: constant \'bx**-1, expected \'bx, got %0d", res);
pass = 1\'b0;
end
r=0;
res = l**r;
if (res !== \'bx) begin
$display("Failed: constant \'bx**0, expected \'bx, got %0d", res);
pass = 1\'b0;
end
r=1;
res = l**r;
if (res !== \'bx) begin
$display("Failed: constant \'bx**1, expected \'bx, got %0d", res);
pass = 1\'b0;
end
r=2;
res = l**r;
if (res !== \'bx) begin
$display("Failed: constant \'bx**2, expected \'bx, got %0d", res);
pass = 1\'b0;
end
r=3;
res = l**r;
if (res !== \'bx) begin
$display("Failed: constant \'bx**3, expected \'bx, got %0d", res);
pass = 1\'b0;
end
// Check the 1st line (rvalue is positive).
l=-3;
r=3;
res = l**r;
if (res !== -27) begin
$display("Failed: constant -3**3, expected -27, got %0d", res);
pass = 1\'b0;
end
l=-3;
r=2;
res = l**r;
if (res !== 9) begin
$display("Failed: constant -3**2, expected 9, got %0d", res);
pass = 1\'b0;
end
l=-1;
r=3;
res = l**r;
if (res !== -1) begin
$display("Failed: constant -1**3, expected -1, got %0d", res);
pass = 1\'b0;
end
l=-1;
r=2;
res = l**r;
if (res !== 1) begin
$display("Failed: constant -1**2, expected 1, got %0d", res);
pass = 1\'b0;
end
l=0;
r=3;
res = l**r;
if (res !== 0) begin
$display("Failed: constant 0**3, expected 0, got %0d", res);
pass = 1\'b0;
end
l=0;
r=2;
res = l**r;
if (res !== 0) begin
$display("Failed: constant 0**2, expected 0, got %0d", res);
pass = 1\'b0;
end
l=1;
r=3;
res = l**r;
if (res !== 1) begin
$display("Failed: constant 1**3, expected 1, got %0d", res);
pass = 1\'b0;
end
l=1;
r=2;
res = l**r;
if (res !== 1) begin
$display("Failed: constant 1**2, expected 1, got %0d", res);
pass = 1\'b0;
end
l=3;
r=3;
res = l**r;
if (res !== 27) begin
$display("Failed: constant 3**3, expected 27, got %0d", res);
pass = 1\'b0;
end
l=3;
r=2;
res = l**r;
if (res !== 9) begin
$display("Failed: constant 3**2, expected 9, got %0d", res);
pass = 1\'b0;
end
// Check the 2nd line (rvalue is zero).
l=-3;
r=0;
res = l**r;
if (res !== 1) begin
$display("Failed: constant -3**0, expected 1, got %0d", res);
pass = 1\'b0;
end
l=-2;
r=0;
res = l**r;
if (res !== 1) begin
$display("Failed: constant -2**0, expected 1, got %0d", res);
pass = 1\'b0;
end
l=-1;
r=0;
res = l**r;
if (res !== 1) begin
$display("Failed: constant -1**0, expected 1, got %0d", res);
pass = 1\'b0;
end
l=0;
r=0;
res = l**r;
if (res !== 1) begin
$display("Failed: constant 0**0, expected 1, got %0d", res);
pass = 1\'b0;
end
l=1;
r=0;
res = l**r;
if (res !== 1) begin
$display("Failed: constant 1**0, expected 1, got %0d", res);
pass = 1\'b0;
end
l=2;
r=0;
res = l**r;
if (res !== 1) begin
$display("Failed: constant 2**0, expected 1, got %0d", res);
pass = 1\'b0;
end
l=3;
r=0;
res = l**r;
if (res !== 1) begin
$display("Failed: constant 3**0, expected 1, got %0d", res);
pass = 1\'b0;
end
// Check the 3rd line (rvalue is negative).
l=-2;
r=-3;
res = l**r;
if (res !== 0) begin
$display("Failed: constant -2**-3, expected 0, got %0d", res);
pass = 1\'b0;
end
l=-2;
r=-2;
res = l**r;
if (res !== 0) begin
$display("Failed: constant -2**-2, expected 0, got %0d", res);
pass = 1\'b0;
end
l=-1;
r=-3;
res = l**r;
if (res !== -1) begin
$display("Failed: constant -1**-3, expected -1, got %0d", res);
pass = 1\'b0;
end
l=-1;
r=-2;
res = l**r;
if (res !== 1) begin
$display("Failed: constant -1**-2, expected 1, got %0d", res);
pass = 1\'b0;
end
l=0;
r=-3;
res = l**r;
if (res !== \'bx) begin
$display("Failed: constant 0**-3, expected \'bx, got %0d", res);
pass = 1\'b0;
end
l=0;
r=-2;
res = l**r;
if (res !== \'bx) begin
$display("Failed: constant 0**-2, expected \'bx, got %0d", res);
pass = 1\'b0;
end
l=1;
r=-3;
res = l**r;
if (res !== 1) begin
$display("Failed: constant 1**-3, expected 1, got %0d", res);
pass = 1\'b0;
end
l=1;
r=-2;
res = l**r;
if (res !== 1) begin
$display("Failed: constant 1**-2, expected 1, got %0d", res);
pass = 1\'b0;
end
l=2;
r=-3;
res = l**r;
if (res !== 0) begin
$display("Failed: constant 2**-3, expected 0, got %0d", res);
pass = 1\'b0;
end
l=2;
r=-2;
res = l**r;
if (res !== 0) begin
$display("Failed: constant 2**-2, expected 0, got %0d", res);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
module t();
reg passed;
parameter ch = 14;
parameter csek2 = 1;
parameter offset = 10/0;
localparam csek = 1 << csek2;
wire [ch + csek2 - 1:0] cim_k;
wire [csek - 1:0] up1, up2, up3, up4, up5, dwn1, dwn2, dwn3;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
// This checks the always above code.
assign up1 = cim_k[(csek2 + ch)+:csek2];
// This checks the always above code.
assign up2 = cim_k[(csek2 + ch + 2)+:csek2];
// This checks the always below code.
assign up3 = cim_k[(csek2 + ch - 17)+:csek2];
// This checks that -4 goes into three bits not two.
assign up4 = cim_k[(csek2 + ch - 18)+:csek2];
// This checks that an undef base gives \'bx out.
assign up5 = cim_k[(csek2 + ch - offset)+:csek2];
// This checks the always above code.
assign dwn1 = cim_k[(csek2 + ch + 2)-:csek2];
// This checks the always below code.
assign dwn2 = cim_k[(csek2 + ch - 17)-:csek2];
// This checks that an undef base gives \'bx out.
assign dwn3 = cim_k[(csek2 + ch - offset)-:csek2];
`else
assign up1 = 2\'b0x;
assign up2 = 2\'b0x;
assign up3 = 2\'b0x;
assign up4 = 2\'b0x;
assign up5 = 2\'b0x;
assign dwn1 = 2\'b0x;
assign dwn2 = 2\'b0x;
assign dwn3 = 2\'b0x;
`endif
initial begin
#1;
passed = 1\'b1;
if (cim_k !== 15\'bz) begin
$display("FAILED: cim_k should be 15\'bz, got %b", cim_k);
passed = 1\'b0;
end
if (up1 !== 2\'b0x) begin
$display("FAILED: up1 should be 2\'b0x, got %b", up1);
passed = 1\'b0;
end
if (up2 !== 2\'b0x) begin
$display("FAILED: up2 should be 2\'b0x, got %b", up2);
passed = 1\'b0;
end
if (up3 !== 2\'b0x) begin
$display("FAILED: up3 should be 2\'b0x, got %b", up3);
passed = 1\'b0;
end
if (up4 !== 2\'b0x) begin
$display("FAILED: up4 should be 2\'b0x, got %b", up4);
passed = 1\'b0;
end
if (up5 !== 2\'b0x) begin
$display("FAILED: up5 should be 2\'b0x, got %b", up5);
passed = 1\'b0;
end
if (dwn1 !== 2\'b0x) begin
$display("FAILED: dwn1 should be 2\'b0x, got %b", dwn1);
passed = 1\'b0;
end
if (dwn2 !== 2\'b0x) begin
$display("FAILED: dwn2 should be 2\'b0x, got %b", dwn2);
passed = 1\'b0;
end
if (dwn3 !== 2\'b0x) begin
$display("FAILED: dwn3 should be 2\'b0x, got %b", dwn3);
passed = 1\'b0;
end
if (passed) $display("PASSED");
end
endmodule
|
module test;
reg fail = 0;
reg [3:0] in = 4\'b0;
wire [3:0] bus = in;
initial begin
#1; // Need some delay for the calculations to run.
if (bus !== 4\'b0) begin
$display("FAILED: initial value, got %b, expected 0000.", bus);
fail = 1;
end
#1 force bus[0] = 1\'b1;
#1 in[0] = 1\'bz;
if (bus !== 4\'b0001) begin
$display("FAILED: force of bus[0], got %b, expected 0001.", bus);
fail = 1;
end
#1 force bus[3:2] = 2\'b11;
if (bus !== 4\'b1101) begin
$display("FAILED: force of bus[3:2], got %b, expected 1101.", bus);
fail = 1;
end
#1 release bus[0];
if (bus !== 4\'b110z) begin
$display("FAILED: release of bus[0], got %b, expected 110z.", bus);
fail = 1;
end
#1 release bus[3:2];
if (bus !== 4\'b000z) begin
$display("FAILED: release of bus[3:2], got %b, expected 000z.", bus);
fail = 1;
end
if (!fail) $display("PASSED");
end
endmodule
|
`begin_keywords "1364-2005"
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
module top;
reg pass = 1\'b1;
reg [3:0] var = 4\'b1001;
// wire [3:0] var = 4\'b1001;
// parameter [3:0] var = 4\'b1001;
reg [3:0] part;
reg [5:0] big;
initial begin
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
part = var[1:-2]; // should be 01xx.
if (part !== 4\'b01xx) begin
$display("part select [1:-2] failed, expected 4\'b01xx, got %b", part);
pass = 1\'b0;
end
part = var[5:2]; // should be xx10.
if (part !== 4\'bxx10) begin
$display("part select [5:2] failed, expected 4\'bxx10, got %b", part);
pass = 1\'b0;
end
big = var[4:-1]; // should be x10100101x.
if (big !== 6\'bx1001x) begin
$display("part select [4:-1] failed, expected 6\'bx1001x, got %b", big);
pass = 1\'b0;
end
`endif
if (pass) $display("PASSED");
end
endmodule
`end_keywords
|
package t_pkg;
virtual class uvm_component;
function new (string name = "uvm_component", uvm_component parent = null);
endfunction : new
endclass
endpackage : t_pkg
module m;
import t_pkg::*;
initial begin
$display ("PASSED");
end
endmodule
|
`timescale 1ns/10ps
module top;
reg pass;
real rise, fall, delay, base, diff;
reg in, ctl;
wire out, outif0;
buf #(rise, fall) dut(out, in);
bufif0 #(rise, fall) dutif0(outif0, in, ctl);
// Check that the buffer output has the correct value and changed at the
// correct time.
always @(out) begin
if ((in === 1\'bz && out !== 1\'bx) ||
(in !== 1\'bz && out !== in)) begin
$display("in (%b) !== out (%b) at %.1f", in, out, $realtime);
pass = 1\'b0;
end
diff = $realtime - (base + delay);
if (diff < 0.0) diff = -diff;
if (diff >= 0.01) begin
$display("Incorrect buf delay at %.1f, got %.1f, expected %.1f",
base, $realtime-base, delay);
pass = 1\'b0;
end
end
// Check that the bufif0 output has the correct value and changed at the
// correct time.
always @(outif0) begin
if (ctl) begin
if (outif0 !== 1\'bz) begin
$display("outif0 (%b) !== 1\'bz at %.1f", out, $realtime);
pass = 1\'b0;
end
end else if ((in === 1\'bz && outif0 !== 1\'bx) ||
(in !== 1\'bz && outif0 !== in)) begin
$display("in (%b) !== outif0 (%b) at %.1f", in, outif0, $realtime);
pass = 1\'b0;
end
diff = $realtime - (base + delay);
if (diff < 0.0) diff = -diff;
if (diff >= 0.01) begin
$display("Incorrect bufif0 delay at %.1f, got %.1f, expected %.1f",
base, $realtime-base, delay);
pass = 1\'b0;
end
end
function real min(input real a, input real b);
if (a < b) min = a;
else min = b;
endfunction
initial begin
// $monitor($realtime,,out,outif0,, in,, ctl);
pass = 1\'b1;
rise = 1.1;
fall = 1.2;
ctl = 1\'b0;
// x -> 0 (fall)
in = 1\'b0;
delay = fall;
base = $realtime;
#2;
// 0 -> 1 (rise)
in = 1\'b1;
delay = rise;
base = $realtime;
#2;
// 1 -> x (min(rise, fall))
delay = min(rise, fall);
in = 1\'bz;
base = $realtime;
#2;
// x -> 1 (rise)
in = 1\'b1;
delay = rise;
base = $realtime;
#2;
// 1 -> 0 (fall)
in = 1\'b0;
delay = fall;
base = $realtime;
#2;
fall = 1.0;
// 0 -> x (min(rise, fall))
in = 1\'bx;
delay = min(rise, fall);
base = $realtime;
#2;
// x -> z (min(rise, fall))
ctl = 1\'b1;
delay = min(rise, fall);
base = $realtime;
#2;
// z -> x (min(rise, fall))
ctl = 1\'b0;
delay = min(rise, fall);
base = $realtime;
#2;
fall = 1.2;
// x -> z (min(rise, fall))
ctl = 1\'b1;
delay = min(rise, fall);
base = $realtime;
#2;
if (pass) $display("PASSED");
end
endmodule
|
// Check that the var keyword is supported for variable declarations in blocks
`define check(val, exp) \\
if (val !== exp) begin \\
$display("FAILED(%0d). \'%s\' expected %b, got %b", `__LINE__, `"val`", val, exp); \\
failed = 1\'b1; \\
end
module test;
bit failed = 1\'b0;
initial begin
var x;
var [7:0] y;
var signed [8:0] z;
var logic [9:0] w;
x = 1\'b1;
y = 8\'d10;
z = -8\'sd1;
w = 8\'d20;
`check(x, 1\'b1)
`check(y, 10)
`check(z, -1)
`check(w, 20)
// var should default to logic and allow x state
x = 1\'bx;
y = 8\'hxx;
z = 8\'hxx;
w = 8\'hxx;
`check(x, 1\'bx)
`check(y, 8\'hxx)
`check(z, 8\'hxx)
`check(w, 8\'hxx)
`check($bits(x), 1)
`check($bits(y), 8)
`check($bits(z), 9)
`check($bits(w), 10)
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
module top;
reg pass = 1\'b1;
reg [2:0] in;
real rin;
wire out, rout;
assign out = (\'d4 == in**2\'d2);
assign rout = (4.0 == rin**2);
initial begin
in = \'d0; rin = 0.0;
#1 if (out != 1\'b0 && rout != 1\'b0) begin
$display("FAILED 0/0.0 check");
pass = 1\'b0;
end
#1 in = \'d1; rin = 1.0;
#1 if (out != 1\'b0 && rout != 1\'b0) begin
$display("FAILED 1/1.0 check");
pass = 1\'b0;
end
#1 in = \'d2; rin = 2.0;
#1 if (out != 1\'b1 && rout != 1\'b1) begin
$display("FAILED 2/2.0 check");
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
module top;
reg pass;
wire [2:-1] vec1;
wire [2:-1] vec2;
wire [2:-1] vec3;
wire [2:-1] vec4;
wire [2:-1] vec5;
wire [2:-1] vec6;
assign vec1 = 4\'bxxxx;
assign vec2 = 4\'bxxxx;
assign vec3 = 4\'bxxxx;
assign vec4 = 4\'bxxxx;
assign vec5 = 4\'bxxxx;
assign vec6 = 4\'bxxxx;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
assign vec1[1\'bx] = 1\'b1;
assign vec2[1\'bx:0] = 1\'b1;
assign vec3[0:1\'bx] = 1\'b1;
assign vec4[1\'bx:1\'bx] = 1\'b1;
assign vec5[1\'bx+:1] = 1\'b1;
assign vec6[1\'bx-:1] = 1\'b1;
`endif
initial begin
pass = 1\'b1;
if (vec1 !== 4\'bxxx) begin
$display("Failed vec1, expected 4\'bxxxx, got %b", vec1);
pass = 1\'b0;
end
if (vec2 !== 4\'bxxx) begin
$display("Failed vec2, expected 4\'bxxxx, got %b", vec2);
pass = 1\'b0;
end
if (vec3 !== 4\'bxxx) begin
$display("Failed vec3, expected 4\'bxxxx, got %b", vec3);
pass = 1\'b0;
end
if (vec4 !== 4\'bxxx) begin
$display("Failed vec4, expected 4\'bxxxx, got %b", vec4);
pass = 1\'b0;
end
if (vec5 !== 4\'bxxx) begin
$display("Failed vec5, expected 4\'bxxxx, got %b", vec5);
pass = 1\'b0;
end
if (vec6 !== 4\'bxxx) begin
$display("Failed vec6, expected 4\'bxxxx, got %b", vec6);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This module tests the basic behavior of a tri0 register. We use a ?:
* to turn on/off the driver to the tri0 net and watch its value.
* A tri0 net should pull to 0 when undriven, and follow the driver
* otherwise.
*/
module main;
reg enable, val;
tri0 t0 = enable ? val : 1\'bz;
initial begin
enable = 0;
val = 0;
#1 if (t0 !== 1\'b0) begin
\t $display("FAILED -- undriven t0 == %b", t0);
\t $finish;
end
enable = 1;
#1 if (t0 !== 1\'b0) begin
\t $display("FAILED -- driven-0 t0 == %b", t0);
\t $finish;
end
val = 1;
#1 if (t0 !== 1\'b1) begin
\t $display("FAILED -- driven-1 t0 == %b", t0);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
module top;
reg real [1:0] a;
initial begin
a[0] = 0.3;
a[1] = 0.4;
$display("FAILED");
end
endmodule
|
// Check that it is possible to declare the data type for a packed array type
// task port before the direction for non-ANSI style port declarations.
module test;
typedef logic [7:0] T1;
typedef T1 [3:0] T2;
task t;
T2 x;
input x;
if (x[0] == 1 && x[1] == 2 && x[2] == 3 && x[3] == 4 &&
$bits(x) == $bits(T2)) begin
$display("PASSED");
end else begin
$display("FAILED");
end
endtask
initial begin
static T2 val;
val[0] = 8\'h1;
val[1] = 8\'h2;
val[2] = 8\'h3;
val[3] = 8\'h4;
t(val);
end
endmodule
|
// This is a compile time test,
// for various port declaration syntax options
`define TEST3
// `define TEST3_X
// unconnected ports
`ifdef TEST3
module port_3
(
dummy_1,
/* unconnected */,
in[7:0],
dummy_2,
out[7:0],
/* unconnected */
);
input [7:0] in;
output [7:0] out;
output\tdummy_1;
output\tdummy_2;
assign\tout = in;
endmodule
`endif // ifdef TEST_3
module port_test;
reg [7:0] data;
`ifdef TEST3
wire [7:0] out_3;
reg\t pass_3;
initial pass_3 = 1;
port_3 dut_3
(, // unconnected dummy_1
`ifdef TEST3_X
// This fails in verilog-XL with:
// Error! Expression given for a null module port [Verilog-EXPNMP]
// "port-test.v", 115: dut_3(, pass_3, data[7:0], ,
// out_3[7:0], )
pass_3, // dummy unconnected
`else
, // unconnected unconnected
`endif
data[7:0],
, // unconnected dummy_2
out_3[7:0],
// unconnected unconnected
);
`endif
initial
begin
\tdata <= 1;
\t#1;
\twhile (data != 0)
\t begin
\t $display ("%b", data);
`ifdef TEST3
\t if (out_3 != data)
\t begin
\t\t $display("data=%b, out_2=%b, FAILED", data, out_3);
\t\t pass_3 = 0;
\t end
`endif
\t data <= data << 1;
\t #1;
\t end
`ifdef TEST3
\tif (pass_3)
\t $display("PASSED");
`endif
\t$finish;
end
endmodule // port_test
|
// Note: The for is translated to a begin/while is it tests the while.
module main;
reg val = 1'b0;
reg cond = 1'b1;
reg [1:0] cval;
integer idx;
integer dly = 1;
// Simple assign (error).
always val = 1'b1;
// A zero delay assign (error).
always #0 val = 1'b1;
// A variable delay assign (warning).
always #dly val = 1'b1;
// Non-blocking assign (error).
always val <= #1 1'b1;
// No delay if (error).
always if (cond) val = 1'b1;
// No delay if/else (error).
always if (cond) val = 1'b1; else val = 1'b0;
// Delay if/no delay else (warning).
always if (cond) #1 val = 1'b1; else val = 1'b0;
// Delay if/no delay else (warning).
always #0 if (cond) #1 val = 1'b1; else val = 1'b0;
// No delay if/delay else (warning).
always if (cond) val = 1'b1; else #1 val = 1'b0;
// No delay forever (error).
always forever val = 1'b1;
// Zero delay forever (error).
always forever #0 val = 1'b1;
// Possible delay forever (warning).
always forever if (cond) #1 val = 1'b1; else val = 1'b0;
// No delay for (error).
always for(idx=0; idx<1; idx=idx+1) val = 1'b1;
// Zero delay for (error).
always for(idx=0; idx<1; idx=idx+1) #0 val = 1'b1;
// Possible delay for (warning).
always for(idx=0; idx<1; idx=idx+1) if (cond) #1 val = 1'b1; else val = 1'b0;
// Never run for (error).
always for(idx=0; 0; idx=idx+1) #1 val = 1'b1;
// Always run for (error).
always for(idx=0; 1; idx=idx+1) #0 val = 1'b1;
// An empty bock (error).
always begin end
// Block with no delay (error).
always begin val = 1'b1; end
// Block with zero delay (error).
always begin #0 val = 1'b1; end
// Block with zero delay (warning).
always begin #0; if (cond) #1 val = 1'b1; else val = 1'b0; end
// Never run repeat (error).
always repeat(0) #1 val = 1'b1;
// Always run repeat (error).
always repeat(1) #0 val = 1'b1;
// Possibly run repeat (warning).
always repeat(cond) #1 val = 1'b1;
// No wait (error).
always wait(1) val = 1'b1;
// May wait (warning).
always wait(cond) val = 1'b1;
// Not all paths covered (warning).
always case(cval)
2'b00: #1 val = 1'b1;
2'b10: #1 val = 1'b1;
endcase
// Not all paths have delay (warning).
always case(cval)
2'b00: #1 val = 1'b1;
2'b10: #1 val = 1'b1;
default: #0 val = 1'b1;
endcase
// Check task calls (error, error, warning).
always no_delay;
always zero_delay;
always possible_delay;
task no_delay;
val = 1'b1;
endtask
task zero_delay;
#0 val = 1'b1;
endtask
task possible_delay;
#dly val = 1'b1;
endtask
// Check a function call (error).
always val = func(1'b1);
function func;
input in;
func = in;
endfunction
endmodule
|
// Check the various variable indexed down selects (LSB > MSB).
module top;
parameter [-4:-1] ap = 4\'he;
parameter [-4:-1] bp = 4\'h1;
parameter [1:4] cp = 4\'he;
parameter [1:4] dp = 4\'h1;
reg passed;
wire [-4:-1] a = 4\'he;
wire [-4:-1] b = 4\'h1;
wire [0:0] s0 = 0;
wire [1:0] s1 = 0;
wire [2:0] s2 = 0;
reg [-4:-1] ar = 4\'he;
reg [-4:-1] br = 4\'h1;
wire [1:4] c = 4\'he;
wire [1:4] d = 4\'h1;
wire [0:0] s3 = 1;
wire [1:0] s4 = 1;
reg [1:4] cr = 4\'he;
reg [1:4] dr = 4\'h1;
wire [1:0] res_a0 = a[s0-:2];
wire [1:0] res_b0 = b[s0-:2];
wire [1:0] res_a1 = a[s1-:2];
wire [1:0] res_b1 = b[s1-:2];
wire [1:0] res_a2 = a[s2-:2];
wire [1:0] res_b2 = b[s2-:2];
wire [1:0] res_c3 = c[s3-:2];
wire [1:0] res_d3 = d[s3-:2];
wire [1:0] res_c4 = c[s4-:2];
wire [1:0] res_d4 = d[s4-:2];
reg [-4:-1] res_ab;
reg [1:4] res_cd;
initial begin
#1;
passed = 1\'b1;
// Check procedural R-value variable index down selects of a net.
$display("a[s0-:2]: %b", a[s1-:2]);
if (a[s0-:2] !== 2\'b0x) begin
$display("Failed a[s0-:2], expected 2\'b0x, got %b", a[s0-:2]);
passed = 1\'b0;
end
$display("b[s0-:2]: %b", b[s1-:2]);
if (b[s0-:2] !== 2\'b1x) begin
$display("Failed b[s0-:2], expected 2\'b1x, got %b", b[s0-:2]);
passed = 1\'b0;
end
$display("a[s1-:2]: %b", a[s1-:2]);
if (a[s1-:2] !== 2\'b0x) begin
$display("Failed a[s1-:2], expected 2\'b0x, got %b", a[s1-:2]);
passed = 1\'b0;
end
$display("b[s1-:2]: %b", b[s1-:2]);
if (b[s1-:2] !== 2\'b1x) begin
$display("Failed b[s1-:2], expected 2\'b1x, got %b", b[s1-:2]);
passed = 1\'b0;
end
$display("a[s2-:2]: %b", a[s2-:2]);
if (a[s2-:2] !== 2\'b0x) begin
$display("Failed a[s2-:2], expected 2\'b0x, got %b", a[s2-:2]);
passed = 1\'b0;
end
$display("b[s2-:2]: %b", b[s2-:2]);
if (b[s2-:2] !== 2\'b1x) begin
$display("Failed b[s2-:2], expected 2\'b1x, got %b", b[s2-:2]);
passed = 1\'b0;
end
$display("c[s3-:2]: %b", c[s3-:2]);
if (c[s3-:2] !== 2\'bx1) begin
$display("Failed c[s3-:2], expected 2\'bx1, got %b", c[s3-:2]);
passed = 1\'b0;
end
$display("d[s3-:2]: %b", d[s3-:2]);
if (d[s3-:2] !== 2\'bx0) begin
$display("Failed d[s3-:2], expected 2\'bx0, got %b", d[s3-:2]);
passed = 1\'b0;
end
$display("c[s4-:2]: %b", c[s4-:2]);
if (c[s4-:2] !== 2\'bx1) begin
$display("Failed c[s4-:2], expected 2\'bx1, got %b", c[s4-:2]);
passed = 1\'b0;
end
$display("d[s4-:2]: %b", d[s4-:2]);
if (d[s4-:2] !== 2\'bx0) begin
$display("Failed d[s4-:2], expected 2\'bx0, got %b", d[s4-:2]);
passed = 1\'b0;
end
// Check procedural R-value variable index down selects of a parameter.
$display("ap[s0-:2]: %b", ap[s0-:2]);
if (ap[s0-:2] !== 2\'b0x) begin
$display("Failed ap[s0-:2], expected 2\'b0x, got %b", ap[s0-:2]);
passed = 1\'b0;
end
$display("bp[s0-:2]: %b", bp[s0-:2]);
if (bp[s0-:2] !== 2\'b1x) begin
$display("Failed bp[s0-:2], expected 2\'b1x, got %b", bp[s0-:2]);
passed = 1\'b0;
end
$display("ap[s1-:2]: %b", ap[s1-:2]);
if (ap[s1-:2] !== 2\'b0x) begin
$display("Failed ap[s1-:2], expected 2\'b0x, got %b", ap[s1-:2]);
passed = 1\'b0;
end
$display("bp[s1-:2]: %b", bp[s1-:2]);
if (bp[s1-:2] !== 2\'b1x) begin
$display("Failed bp[s1-:2], expected 2\'b1x, got %b", bp[s1-:2]);
passed = 1\'b0;
end
$display("ap[s2-:2]: %b", ap[s2-:2]);
if (ap[s2-:2] !== 2\'b0x) begin
$display("Failed ap[s2-:2], expected 2\'b0x, got %b", ap[s2-:2]);
passed = 1\'b0;
end
$display("bp[s2-:2]: %b", bp[s2-:2]);
if (bp[s2-:2] !== 2\'b1x) begin
$display("Failed bp[s2-:2], expected 2\'b1x, got %b", bp[s2-:2]);
passed = 1\'b0;
end
$display("cp[s3-:2]: %b", cp[s3-:2]);
if (cp[s3-:2] !== 2\'bx1) begin
$display("Failed cp[s3-:2], expected 2\'bx1, got %b", cp[s3-:2]);
passed = 1\'b0;
end
$display("dp[s3-:2]: %b", dp[s3-:2]);
if (dp[s3-:2] !== 2\'bx0) begin
$display("Failed dp[s3-:2], expected 2\'bx0, got %b", dp[s3-:2]);
passed = 1\'b0;
end
$display("cp[s4-:2]: %b", cp[s4-:2]);
if (cp[s4-:2] !== 2\'bx1) begin
$display("Failed cp[s4-:2], expected 2\'bx1, got %b", cp[s4-:2]);
passed = 1\'b0;
end
$display("dp[s4-:2]: %b", dp[s4-:2]);
if (dp[s4-:2] !== 2\'bx0) begin
$display("Failed dp[s4-:2], expected 2\'bx0, got %b", dp[s4-:2]);
passed = 1\'b0;
end
// Check procedural R-value variable index down selects of a reg.
$display("ar[s0-:2]: %b", ar[s0-:2]);
if (ar[s0-:2] !== 2\'b0x) begin
$display("Failed ar[s0-:2], expected 2\'b0x, got %b", ar[s0-:2]);
passed = 1\'b0;
end
$display("br[s0-:2]: %b", br[s0-:2]);
if (br[s0-:2] !== 2\'b1x) begin
$display("Failed br[s0-:2], expected 2\'b1x, got %b", br[s0-:2]);
passed = 1\'b0;
end
$display("ar[s1-:2]: %b", ar[s1-:2]);
if (ar[s1-:2] !== 2\'b0x) begin
$display("Failed ar[s1-:2], expected 2\'b0x, got %b", ar[s1-:2]);
passed = 1\'b0;
end
$display("br[s1-:2]: %b", br[s1-:2]);
if (br[s1-:2] !== 2\'b1x) begin
$display("Failed br[s1-:2], expected 2\'b1x, got %b", br[s1-:2]);
passed = 1\'b0;
end
$display("ar[s2-:2]: %b", ar[s2-:2]);
if (ar[s2-:2] !== 2\'b0x) begin
$display("Failed ar[s2-:2], expected 2\'b0x, got %b", ar[s2-:2]);
passed = 1\'b0;
end
$display("br[s2-:2]: %b", br[s2-:2]);
if (br[s2-:2] !== 2\'b1x) begin
$display("Failed br[s2-:2], expected 2\'b1x, got %b", br[s2-:2]);
passed = 1\'b0;
end
$display("cr[s3-:2]: %b", cr[s3-:2]);
if (cr[s3-:2] !== 2\'bx1) begin
$display("Failed cr[s3-:2], expected 2\'bx1, got %b", cr[s3-:2]);
passed = 1\'b0;
end
$display("dr[s3-:2]: %b", dr[s3-:2]);
if (dr[s3-:2] !== 2\'bx0) begin
$display("Failed dr[s3-:2], expected 2\'bx0, got %b", dr[s3-:2]);
passed = 1\'b0;
end
$display("cr[s4-:2]: %b", cr[s4-:2]);
if (cr[s4-:2] !== 2\'bx1) begin
$display("Failed cr[s4-:2], expected 2\'bx1, got %b", cr[s4-:2]);
passed = 1\'b0;
end
$display("dr[s4-:2]: %b", dr[s4-:2]);
if (dr[s4-:2] !== 2\'bx0) begin
$display("Failed dr[s4-:2], expected 2\'bx0, got %b", dr[s4-:2]);
passed = 1\'b0;
end
// Check continuous assignment R-value variable index down selects.
if (res_a0 !== 2\'b0x) begin
$display("Failed res_a0, expected 2\'b0x, got %b", res_a0);
passed = 1\'b0;
end
if (res_b0 !== 2\'b1x) begin
$display("Failed res_b0, expected 2\'b1x, got %b", res_b0);
passed = 1\'b0;
end
if (res_a1 !== 2\'b0x) begin
$display("Failed res_a1, expected 2\'b0x, got %b", res_a1);
passed = 1\'b0;
end
if (res_b1 !== 2\'b1x) begin
$display("Failed res_b1, expected 2\'b1x, got %b", res_b1);
passed = 1\'b0;
end
if (res_a2 !== 2\'b0x) begin
$display("Failed res_a2, expected 2\'b0x, got %b", res_a2);
passed = 1\'b0;
end
if (res_b2 !== 2\'b1x) begin
$display("Failed res_b2, expected 2\'b1x, got %b", res_b2);
passed = 1\'b0;
end
if (res_c3 !== 2\'bx1) begin
$display("Failed res_c3, expected 2\'bx1, got %b", res_c3);
passed = 1\'b0;
end
if (res_d3 !== 2\'bx0) begin
$display("Failed res_d3, expected 2\'bx0, got %b", res_d3);
passed = 1\'b0;
end
if (res_c4 !== 2\'bx1) begin
$display("Failed res_c4, expected 2\'bx1, got %b", res_c4);
passed = 1\'b0;
end
if (res_d4 !== 2\'bx0) begin
$display("Failed res_d4, expected 2\'bx0, got %b", res_d4);
passed = 1\'b0;
end
// Check procedural L-value variable index down selects.
res_ab = 4\'bxxxx;
res_ab[s0-:2] = 2\'b00;
if (res_ab !== 4\'bxxx0) begin
$display("Failed res_ab[s0], expected 4\'bxxx0, got %b", res_ab);
passed = 1\'b0;
end
res_ab = 4\'bxxxx;
res_ab[s1-:2] = 2\'b00;
if (res_ab !== 4\'bxxx0) begin
$display("Failed res_ab[s1], expected 4\'bxxx0, got %b", res_ab);
passed = 1\'b0;
end
res_ab = 4\'bxxxx;
res_ab[s2-:2] = 2\'b00;
if (res_ab !== 4\'bxxx0) begin
$display("Failed res_ab[s2], expected 4\'bxxx0, got %b", res_ab);
passed = 1\'b0;
end
res_cd = 4\'bxxxx;
res_cd[s3-:2] = 2\'b00;
if (res_cd !== 4\'b0xxx) begin
$display("Failed res_cd[s3], expected 4\'b0xxx, got %b", res_cd);
passed = 1\'b0;
end
res_cd = 4\'bxxxx;
res_cd[s4-:2] = 2\'b00;
if (res_cd !== 4\'b0xxx) begin
$display("Failed res_cd[s4], expected 4\'b0xxx, got %b", res_cd);
passed = 1\'b0;
end
if (passed) $display("Compare tests passed");
end
endmodule
|
// deliberately empty
|
// Check that it is possible to declare the data type for a time type task port
// before the direction for non-ANSI style port declarations.
module test;
task t;
time x;
input x;
if (x == 10 && $bits(x) == $bits(time)) begin
$display("PASSED");
end else begin
$display("FAILED");
end
endtask
initial t(10);
endmodule
|
module top;
reg y, a, b, flip, hidden, en;
reg pass;
function f_and (input i1, i2);
reg partial;
begin
partial = i1 & i2;
f_and = partial | hidden;
end
endfunction
reg intr;
always_latch begin
if (en) begin
intr = flip;
y <= f_and(a, b) ^ intr;
end
end
initial begin
pass = 1\'b1;
en = 1\'b1;
flip = 1\'b0;
hidden = 1\'b0;
a = 1\'b0;
b = 1\'b0;
#1;
if (y !== 1\'b0) begin
$display("FAILED: a=1\'b0, b=1\'b0, hidden=1\'b0, expected 1\'b0, got %b", y);
pass = 1\'b0;
end
a = 1\'b0;
b = 1\'b1;
#1;
if (y !== 1\'b0) begin
$display("FAILED: a=1\'b0, b=1\'b1, hidden=1\'b0, expected 1\'b0, got %b", y);
pass = 1\'b0;
end
a = 1\'b1;
b = 1\'b0;
#1;
if (y !== 1\'b0) begin
$display("FAILED: a=1\'b1, b=1\'b0, hidden=1\'b0, expected 1\'b0, got %b", y);
pass = 1\'b0;
end
a = 1\'b1;
b = 1\'b1;
#1;
if (y !== 1\'b1) begin
$display("FAILED: a=1\'b1, b=1\'b1, hidden=1\'b0, expected 1\'b1, got %b", y);
pass = 1\'b0;
end
hidden = 1\'b0;
a = 1\'b0;
b = 1\'b0;
#1;
if (y !== 1\'b0) begin
$display("FAILED: a=1\'b0, b=1\'b0, hidden=1\'b0, expected 1\'b0, got %b", y);
pass = 1\'b0;
end
hidden = 1\'b1;
a = 1\'b0;
b = 1\'b0;
#1;
if (y !== 1\'b1) begin
$display("FAILED: a=1\'b0, b=1\'b0, hidden=1\'b1, expected 1\'b1, got %b", y);
pass = 1\'b0;
end
en = 1\'b0;
hidden = 1\'b0;
#1;
if (y !== 1\'b1) begin
$display("FAILED: en=1\'b0, expected 1\'b1, got %b", y);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
// Regression test for bug reported by Orson on 24-Apr-15 via iverilog_devel.
module test();
localparam value = $ivlh_to_unsigned((1000 / ($signed(13\'d50))), 12);
initial begin
$display("%d", value);
if (value === 20)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
// Check that a vector base type of an array type gets evaluated in the right
// scope if the base type is defined in a different scope than the array type.
localparam A = 8;
typedef logic [A-1:0] Base;
module test;
localparam A = 4;
typedef Base T[1:0];
T x;
initial begin
x[0] = 8\'hff;
if (x[0] === 8\'hff) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
|
/*
* This tests the case that a delay value is a calculated real value.
*/
module main;
real test;
wire [3:0] Q;
reg [3:0] D;
assign #(test/2.0) Q = D;
initial begin
test = 4.0;
D = 1;
#(test) if (Q !== 1) begin
\t $display("FAILED -- %0t: Q=%d, D=%d", $time, Q, D);
\t $finish;
end
D = 2;
#(test/4) if (Q !== 1) begin
\t $display("FAILED -- %0t: Q=%d, D=%d", $time, Q, D);
\t $finish;
end
#(test/2) if (Q !== 2) begin
\t $display("FAILED -- %0t: Q=%d, D=%d", $time, Q, D);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - include a single file
//
`include "ivltests/else3.v"
|
`begin_keywords "1364-2005"
/*
* Copyright (c) 2005 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/* andnot1.v
* This tests types.
*/
module main;
reg a, b, c;
wire d = a & !b; // change from !b to ~b and everything is fine
reg [2:0] tmp;
reg\t ref;
initial begin
// Do an exaustive scan of the possible values.
for (tmp = 0 ; tmp < 4 ; tmp = tmp + 1) begin
\t a = tmp[0];
\t b = tmp[1];
\t c = a & ~b;
\t #1 if (c != d) begin
\t $display("FAILED -- a=%b, b=%b, c=%b, d=%b",
\t\t a, b, c, d);
\t $finish;
\t end
end // for (tmp = 0 ; tmp < 4 ; tmp = tmp + 1)
$display("PASSED");
end
endmodule // main
`end_keywords
|
/*
* This is a reduced example from comp1001 to demonstrate a problem
* in the Icarus Verilog code generator. If one addition argument is
* replaced with a 1-bit register (instead of the constant 1\'b1),
* evaluation is postponed to vvp, which works correctly. It appears
* that the width of the adder is calculated incorrectly when part
* of a comparison, but only in constant-propagation mode.
*/
module top;
reg [30:0] r2;
reg r1=1;
initial begin
r2 = (1\'b1+1\'b1) != 1\'bx;
// r2 = (1\'b1+r1) != 1\'bx;
$displayb("r2 = ",r2);
if (r2 !== 31\'b0x) $display("FAILED");
else $display("PASSED");
end
endmodule
|
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