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/*
* Copyright (c) 2001 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
wire no, po;
reg\td, c;
rnmos n (no, d, c);
rpmos p (po, d, c);
initial begin
c = 0;
d = 0;
#1 if (no !== 1\'bz) begin
\t $display("FAILED -- n (%b, %b, %b)", no, d, c);
\t $finish;
end
if (po !== 1\'b0) begin
\t $display("FAILED -- p (%b, %b, %b)", po, d, c);
\t $finish;
end
d = 1;
#1 if (no !== 1\'bz) begin
\t $display("FAILED -- n (%b, %b, %b)", no, d, c);
\t $finish;
end
if (po !== 1\'b1) begin
\t $display("FAILED -- p (%b, %b, %b)", po, d, c);
\t $finish;
end
c = 1;
#1 if (no !== 1\'b1) begin
\t $display("FAILED -- n (%b, %b, %b)", no, d, c);
\t $finish;
end
if (po !== 1\'bz) begin
\t $display("FAILED -- p (%b, %b, %b)", po, d, c);
\t $finish;
end
d = 0;
#1 if (no !== 1\'b0) begin
\t $display("FAILED -- n (%b, %b, %b)", no, d, c);
\t $finish;
end
if (po !== 1\'bz) begin
\t $display("FAILED -- p (%b, %b, %b)", po, d, c);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
// This tests the basic support for default arguments to task/function
// ports. The default port syntax gives SystemVerilog a limited form
// of variable argument lists.
program main;
class foo_t;
int int_val;
logic[3:0]log_val;
function new (int int_init, logic[3:0] log_init = 4\'bzzzz);
\t int_val = int_init;
\t log_val = log_init;
endfunction : new
endclass : foo_t
foo_t obj1;
initial begin
obj1 = new (5, 4\'b1010);
if (obj1.int_val != 5 || obj1.log_val !== 4\'b1010) begin
\t $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%0s", obj1.int_val, obj1.log_val);
\t $finish;
end
obj1 = new (7);
if (obj1.int_val != 7 || obj1.log_val !== 4\'bzzzz) begin
\t $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%0s", obj1.int_val, obj1.log_val);
\t $finish;
end
$display("PASSED");
end
endprogram // main
|
`ifndef MACRO1
`define MACRO1 21
`endif
`ifndef MACRO2
`define MACRO2 22
`endif
`ifndef MACRO3
`define MACRO3 23
`endif
module test2(input w);
buf(a,b);
initial #2 begin
$display("test2 macro1 = %0d", `MACRO1 );
$display("test2 macro2 = %0d", `MACRO2 );
$display("test2 macro3 = %0d", `MACRO3 );
$display("test2 wire = %b", a);
end
endmodule
|
// Check that VAMS `abs()` functions works if its argument is a function call
module main;
function reg signed [7:0] fv(input reg signed [7:0] x);
fv = x;
endfunction
function real fr(input real x);
fr = x;
endfunction
reg signed [7:0] a;
wire signed [7:0] vala = abs(fv(a));
reg\t real b;
wire real valb = abs(fr(b));
initial begin
a = 0;
b = 0;
#1 if (vala !== 0) begin
\t $display("FAILED -- a=%b, vala=%b", a, vala);
\t $finish;
end
#1 if (valb != 0) begin
\t $display("FAILED -- b=%g valb=%g", b, valb);
\t $finish;
end
a = 1;
b = 1;
#1 if (vala !== 1) begin
\t $display("FAILED -- a=%b, vala=%b", a, vala);
\t $finish;
end
#1 if (valb != 1) begin
\t $display("FAILED -- b=%g valb=%g", b, valb);
\t $finish;
end
a = -1;
b = -1;
#1 if (vala !== 1) begin
\t $display("FAILED -- a=%b, vala=%b", a, vala);
\t $finish;
end
#1 if (valb != 1) begin
\t $display("FAILED -- b=%g valb=%g", b, valb);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
/*
Verilog-XL error message:
Error! Recursive instantiation of module (a) [Verilog-RINOM]
"murec.v", 13: a a0(z, x);
1 error
*/
module test;
reg x ;
wire z ;
a a0( z, x );
endmodule
module a( z, x );
output z ;
input x ;
b b0( z, x );
endmodule
module b( z, x );
output z ;
input x ;
a a0( z, x ); // Error should be caught here
endmodule
|
module top;
reg [15:0] out_16;
reg [31:0] in_32, in_32x, ck_32, ck_32x, out_32, out_32x;
reg [63:0] out_64;
integer res, fd;
reg passed;
initial begin
passed = 1\'b1;
// Check that a normal 32 bit %u works as expected.
fd = $fopen("work/test_fscanf.bin", "wb");
in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x;
ck_32 = 32\'b00001000_00100000_10100000_10001110;
$fwrite(fd, "%u", in_32);
$fclose(fd);
fd = $fopen("work/test_fscanf.bin", "rb");
res = $fscanf(fd, "%u", out_32);
if (res !== 1) begin
$display("FAILED: $fscanf() #1 returned %d", res);
passed = 1\'b0;
end else if (ck_32 !== out_32) begin
$display("FAILED: #1 %b !== %b", ck_32, out_32);
passed = 1\'b0;
end
res = $fscanf(fd, "%u", out_32);
if (res !== -1) begin
$display("FAILED: $fscanf() #1 EOF returned %d (%b)", res, out_32);
passed = 1\'b0;
end
$fclose(fd);
// Check that a normal 32/64 bit %u works as expected. Do the write as
// two 32 bit values to make sure the word order is correct.
fd = $fopen("work/test_fscanf.bin", "wb");
in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x;
ck_32 = 32\'b00001000_00100000_10100000_10001110;
$fwrite(fd, "%u", in_32);
in_32x = 32\'b0001000x_0010000x_0011000x_0100000x;
ck_32x = 32\'b00010000_00100000_00110000_01000000;
$fwrite(fd, "%u", in_32x);
$fclose(fd);
fd = $fopen("work/test_fscanf.bin", "rb");
res = $fscanf(fd, "%u", out_64);
if (res !== 1) $display("FAILED: $fscanf() #2a returned %d", res);
else if ({ck_32x,ck_32} !== out_64) begin
$display("FAILED: #2a %b !== %b", {ck_32x,ck_32}, out_64);
passed = 1\'b0;
end
res = $fscanf(fd, "%u", out_32);
if (res !== -1) begin
$display("FAILED: $fscanf() #2a EOF returned %d (%b)", res, out_32);
passed = 1\'b0;
end
$fclose(fd);
// Check that a normal 64/64 bit %u works as expected.
fd = $fopen("work/test_fscanf.bin", "wb");
in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x;
ck_32 = 32\'b00001000_00100000_10100000_10001110;
in_32x = 32\'b0001000x_0010000x_0011000x_0100000x;
ck_32x = 32\'b00010000_00100000_00110000_01000000;
$fwrite(fd, "%u", {in_32x,in_32});
$fclose(fd);
fd = $fopen("work/test_fscanf.bin", "rb");
res = $fscanf(fd, "%u", out_64);
if (res !== 1) $display("FAILED: $fscanf() #2b returned %d", res);
else if ({ck_32x,ck_32} !== out_64) begin
$display("FAILED: #2b %b !== %b", {ck_32x,ck_32}, out_64);
passed = 1\'b0;
end
res = $fscanf(fd, "%u", out_32);
if (res !== -1) begin
$display("FAILED: $fscanf() #2b EOF returned %d (%b)", res, out_32);
passed = 1\'b0;
end
$fclose(fd);
// Check that a normal 64/32 bit %u works as expected.
fd = $fopen("work/test_fscanf.bin", "wb");
in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x;
ck_32 = 32\'b00001000_00100000_10100000_10001110;
in_32x = 32\'b0001000x_0010000x_0011000x_0100000x;
ck_32x = 32\'b00010000_00100000_00110000_01000000;
$fwrite(fd, "%u", {in_32x,in_32});
$fclose(fd);
fd = $fopen("work/test_fscanf.bin", "rb");
res = $fscanf(fd, "%u%u", out_32,out_32x);
if (res !== 2) $display("FAILED: $fscanf() #2c returned %d", res);
else if ({ck_32x,ck_32} !== {out_32x, out_32}) begin
$display("FAILED: #2c %b !== %b", {ck_32x,ck_32}, {out_32x,out_32});
passed = 1\'b0;
end
res = $fscanf(fd, "%u", out_32);
if (res !== -1) begin
$display("FAILED: $fscanf() #2c EOF returned %d (%b)", res, out_32);
passed = 1\'b0;
end
$fclose(fd);
// Check that a 16 bit %u works as expected.
fd = $fopen("work/test_fscanf.bin", "wb");
in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x;
ck_32 = 32\'b00001000_00100000_10100000_10001110;
$fwrite(fd, "%u", in_32);
$fclose(fd);
fd = $fopen("work/test_fscanf.bin", "rb");
res = $fscanf(fd, "%u", out_16);
if (res !== 1) begin
$display("FAILED: $fscanf() #3 returned %d", res);
passed = 1\'b0;
end else if (ck_32[15:0] !== out_16) begin
$display("FAILED: #3 %b !== %b", ck_32[15:0], out_16);
passed = 1\'b0;
end
res = $fscanf(fd, "%u", out_32);
if (res !== -1) begin
$display("FAILED: $fscanf() #3 EOF returned %d (%b)", res, out_32);
passed = 1\'b0;
end
$fclose(fd);
// Check that a 16 bit %u works as expected even with a 32 bit variable.
// All 32 bits are read but we truncate and zero fill the result.
fd = $fopen("work/test_fscanf.bin", "wb");
in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x;
ck_32 = 32\'b00001000_00100000_10100000_10001110;
$fwrite(fd, "%u", in_32);
$fclose(fd);
fd = $fopen("work/test_fscanf.bin", "rb");
res = $fscanf(fd, "%16u", out_32);
if (res !== 1) begin
$display("FAILED: $fscanf() #4 returned %d", res);
passed = 1\'b0;
end else if (ck_32[15:0] !== out_32) begin
$display("FAILED: #4 %b !== %b", ck_32[15:0], out_32);
passed = 1\'b0;
end
res = $fscanf(fd, "%u", out_32);
if (res !== -1) begin
$display("FAILED: $fscanf() #4 EOF returned %d (%b)", res, out_32);
passed = 1\'b0;
end
$fclose(fd);
// Check that a 32 bit %u works with a 64 bit variable when sized.
fd = $fopen("work/test_fscanf.bin", "wb");
in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x;
ck_32 = 32\'b00001000_00100000_10100000_10001110;
$fwrite(fd, "%u", in_32);
$fclose(fd);
fd = $fopen("work/test_fscanf.bin", "rb");
res = $fscanf(fd, "%32u", out_64);
if (res !== 1) begin
$display("FAILED: $fscanf() #5 returned %d", res);
passed = 1\'b0;
end else if (ck_32 !== out_64) begin
$display("FAILED: #5 %b !== %b", ck_32, out_64);
passed = 1\'b0;
end
res = $fscanf(fd, "%u", out_32);
if (res !== -1) begin
$display("FAILED: $fscanf() #5 EOF returned %d (%b)", res, out_32);
passed = 1\'b0;
end
$fclose(fd);
// Check that by default one element is suppressed.
fd = $fopen("work/test_fscanf.bin", "wb");
in_32x = 32\'b0001000x_0010000x_0011000x_0100000x;
$fwrite(fd, "%u", in_32x);
in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x;
ck_32 = 32\'b00001000_00100000_10100000_10001110;
$fwrite(fd, "%u", in_32);
$fclose(fd);
fd = $fopen("work/test_fscanf.bin", "rb");
res = $fscanf(fd, "%*u%u", out_32);
if (res !== 1) begin
$display("FAILED: $fscanf() #6 returned %d", res);
passed = 1\'b0;
end else if (ck_32 !== out_32) begin
$display("FAILED: #6 %b !== %b", ck_32, out_32);
passed = 1\'b0;
end
res = $fscanf(fd, "%u", out_32);
if (res !== -1) begin
$display("FAILED: $fscanf() #6 EOF returned %d (%b)", res, out_32);
passed = 1\'b0;
end
$fclose(fd);
// Check that multiple elements can be suppressed (exact count).
fd = $fopen("work/test_fscanf.bin", "wb");
in_32x = 32\'b0001000x_0010000x_0011000x_0100000x;
$fwrite(fd, "%u%u", in_32x, in_32x);
in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x;
ck_32 = 32\'b00001000_00100000_10100000_10001110;
$fwrite(fd, "%u", in_32);
$fclose(fd);
fd = $fopen("work/test_fscanf.bin", "rb");
res = $fscanf(fd, "%*64u%u", out_32);
if (res !== 1) begin
$display("FAILED: $fscanf() #7 returned %d", res);
passed = 1\'b0;
end else if (ck_32 !== out_32) begin
$display("FAILED: #7 %b !== %b", ck_32, out_32);
passed = 1\'b0;
end
res = $fscanf(fd, "%u", out_32);
if (res !== -1) begin
$display("FAILED: $fscanf() #7 EOF returned %d (%b)", res, out_32);
passed = 1\'b0;
end
$fclose(fd);
// Check that multiple elements can be suppressed (minimum count).
fd = $fopen("work/test_fscanf.bin", "wb");
in_32x = 32\'b0001000x_0010000x_0011000x_0100000x;
$fwrite(fd, "%u%u", in_32x, in_32x);
in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x;
ck_32 = 32\'b00001000_00100000_10100000_10001110;
$fwrite(fd, "%u", in_32);
$fclose(fd);
fd = $fopen("work/test_fscanf.bin", "rb");
res = $fscanf(fd, "%*33u%u", out_32);
if (res !== 1) begin
$display("FAILED: $fscanf() #8 returned %d", res);
passed = 1\'b0;
end else if (ck_32 !== out_32) begin
$display("FAILED: #8 %b !== %b", ck_32, out_32);
passed = 1\'b0;
end
res = $fscanf(fd, "%u", out_32);
if (res !== -1) begin
$display("FAILED: $fscanf() #8 EOF returned %d (%b)", res, out_32);
passed = 1\'b0;
end
$fclose(fd);
if (passed) $display("PASSED");
end
endmodule
|
// Copyright (c) 2002 Michael Ruff (mruff at chiaro.com)
// Michael Runyan (mrunyan at chiaro.com)
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module test;
reg [0:32]\tbig_reg;
reg [0:32]\tmy_mem[0:16];
reg\t\tevent_trigger;
initial begin
#10 $display("!!!VERILOG: big_reg=%h",big_reg);
$display(" my_mem[1]=%h",my_mem[1]);
event_trigger=1;
#10 big_reg=33\'h1_2345_6789;
my_mem[1]=33\'h1_5432_9876;
#10 $display("!!!VERILOG: big_reg=%h",big_reg);
$display(" my_mem[1]=%h",my_mem[1]);
event_trigger=!event_trigger;
#10 $finish(0);
end
endmodule
|
// pr1755593
module main;
wire out;
reg [4:0] data;
reg [2:0] sel;
test U1(out, data[0], data[1], data[2], data[3], sel[0], sel[1]);
initial begin
for (sel=0 ; sel<4 ; sel=sel+1)
\t for (data=0 ; data<16 ; data=data+1) begin
\t #1 if (out !== data[sel]) begin
\t $display("FAILED -- data=%b, sel=%d", data, sel);
\t $finish;
\t end
\t end
$display("PASSED");
end
endmodule // main
module test (Z, D0, D1, D2, D3, E0, E1);
output Z;
input D0;
input D1;
input D2;
input D3;
input E0;
input E1;
u_test I48 (Z, D0, D1, D2, D3, E0, E1);
endmodule
primitive u_test (Z, D0, D1, D2, D3, E0, E1);
output Z;
input D0, D1, D2, D3, E0, E1;
table
0 ? ? ? 0 0 : 0 ;
1 ? ? ? 0 0 : 1 ;
? 0 ? ? 1 0 : 0 ;
? 1 ? ? 1 0 : 1 ;
? ? 0 ? 0 1 : 0 ;
? ? 1 ? 0 1 : 1 ;
? ? ? 0 1 1 : 0 ;
? ? ? 1 1 1 : 1 ;
0 0 ? ? x 0 : 0 ;
1 1 ? ? x 0 : 1 ;
? ? 0 0 x 1 : 0 ;
? ? 1 1 x 1 : 1 ;
0 ? 0 ? 0 x : 0 ;
1 ? 1 ? 0 x : 1 ;
? 0 ? 0 1 x : 0 ;
? 1 ? 1 1 x : 1 ;
0 0 0 0 x x : 0 ;
1 1 1 1 x x : 1 ;
endtable
endprimitive
|
/*
* This program handles the case of a system task within a user
* defined function.
*/
module main;
reg [31:0] tmp1;
reg [31:0] tmp2;
function [31:0] test;
input [31:0] op1;
$write("op1 = %h\
", op1);
endfunction
initial
begin
tmp1 = \'hdeadbeef;
tmp2 = test(tmp1);
$display("PASSED");
end
endmodule
|
module top;
reg [6:0] dx, dz, dz2;
initial begin
// Check the unsigned version.
dx = 7\'dx;
dz = 7\'dz;
dz2 = 7\'d?;
$display(" 7\'dx: %b", dx, ", 7\'dz: %b", dz, ", 7\'d?: %b", dz2);
dx = \'dx;
dz = \'dz;
dz2 = \'d?;
$display(" \'dx: %b", dx, ", \'dz: %b", dz, ", \'d?: %b", dz2);
dx = 2\'dx;
dz = 2\'dz;
dz2 = 2\'d?;
$display(" 2\'dx: %b", dx, ", 2\'dz: %b", dz, ", 2\'d?: %b", dz2);
// Check the signed version.
dx = 7\'sdx;
dz = 7\'sdz;
dz2 = 7\'sd?;
$display("7\'sdx: %b", dx, ", 7\'sdz: %b", dz, ", 7\'sd?: %b", dz2);
dx = \'sdx;
dz = \'sdz;
dz2 = \'sd?;
$display(" \'sdx: %b", dx, ", \'sdz: %b", dz, ", \'sd?: %b", dz2);
dx = 2\'sdx;
dz = 2\'sdz;
dz2 = 2\'sd?;
$display("2\'sdx: %b", dx, ", 2\'sdz: %b", dz, ", 2\'sd?: %b", dz2);
// Check the trailing underscore.
dx = 7\'dx_;
dz = 7\'dz__;
dz2 = 7\'d?___;
$display("7\'dx_: %b", dx, ", 7\'dz_: %b", dz, ", 7\'d?_: %b", dz2);
end
endmodule
|
module example;
reg [7:0] vec;
reg [3:0] ix;
wire vix = vec[ix];
initial begin
$display( " time ix vix vec" );
$display( " ---- ---- --- --------" );
$monitor( "%T %b %b %b", $time, ix, vix, vec );
vec = 8\'b00000000;
ix = 0; // 0
#100 ix = 1; // 100
#100 ix = 2; // 200
#100 ix = 3; // 300
#100 ix = 4; // 400
#100 ix = 5; // 500
#100 ix = 6; // 600
#100 ix = 7; // 700
#100 ix = 8; // 800
#100 ix = 4\'b001x; // 900
#100 ix = 4\'b01x0; // 1000
#100 ix = 4\'b0x01; // 1100
#100 ix = 0; // 1200
#100 vec[ix] = 1\'b1; // 1300
#100 vec[ix] = 1\'b0; // 1400
#100 ix = 3; // 1500
#100 vec[ix] = 1\'b1; // 1600
#100 vec[ix] = 1\'b0; // 1700
#100 ix = 6; // 1800
#100 vec[ix] = 1\'b1; // 1900
#100 vec[ix] = 1\'b0; // 2000
#100 ix = 8; // 2100
#100 vec[ix] = 1\'b1; // 2200
#100 vec[ix] = 1\'b0; // 2300
#100 ix = 4\'b010x; // 2400
#100 vec[ix] = 1\'b1; // 2500
#100 vec[ix] = 1\'b0; // 2600
#100 ix = 4\'b00x1; // 2700
#100 vec[ix] = 1\'b1; // 2800
#100 vec[ix] = 1\'b0; // 2900
#100 ix = 4\'b0x10; // 3000
#100 vec[ix] = 1\'b1; // 3100
#100 vec[ix] = 1\'b0; // 3200
#100 ix = 4\'bxxxx; // 3300
#100 vec[ix] = 1\'b1; // 3400
#100 vec[ix] = 1\'b0; // 3500
#100 $display( "Finish at time %T", $time );
end
endmodule
|
// Check that it is possible to reference a package scoped type identifier as
// the type in a type cast expression.
bit failed = 1\'b0;
`define check(expr, val) \\
if (expr !== val) begin \\
$display("FAILED: %s, expected %0d, got %0d", `"expr`", val, expr); \\
failed = 1\'b1; \\
end
package P;
typedef integer T;
endpackage
module test;
integer x;
initial begin
x = P::T\'(-1024.123);
`check(x, -1024)
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
//
// Copyright (c) 1999 Stephen Williams ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// Test the divide (/) operator
module top () ;
reg [7:0] a, b, result;
wire [7:0] wa, wb, wresult;
assign wa = a;
assign wb = b;
assign wresult = wa / wb;
always @(a or b)
result = a / b;
initial begin
#1 a = 0; b = 1;
# 1;
if( result !== 8\'b0)
begin
$display("FAILED - Divide 0/1 reg assign failed - is %b",result);
$finish;
end
if( wresult !== 8\'b0)
begin
$display("FAILED - Divide 0/1 wire assign failed - is %b",wresult);
$finish;
end
#1 a = 1;
#1 if( result !== 8\'b1)
begin
$display("FAILED - Divide 1/1 reg assign failed - is %b",result);
\t$finish;
end
if( wresult !== 8\'b1)
begin
$display("FAILED - Divide 1/1 wire assign failed - is %b",wresult);
$finish;
end
#1 a = 5; b = 2;
#1 if( result !== 8\'d2)
begin
$display("FAILED - Divide 5/2 reg assign failed - is %b",result);
$finish;
end
if( wresult !== 8\'d2)
begin
$display("FAILED - Divide 5/2 wire assign failed - is %b",wresult);
$finish;
end
#1 a = 8\'d255; b = 5;
#1 if( result !== 51)
begin
$display("FAILED - Divide 255/5 reg assign failed - is %b",result);
$finish;
end
if( wresult !== 51)
begin
$display("FAILED - Divide 255/5 wire assign failed - is %b",wresult);
$finish;
end
#1 a = 1\'bx; b = 3;
#1 if( result !== 8\'bxxxx_xxxx)
begin
$display("FAILED - Divide x/3 reg assign failed - is %b",result);
$finish;
end
if( wresult !== 8\'bxxxx_xxxx)
begin
$display("FAILED - Divide x/3 wire assign failed - is %b",wresult);
$finish;
end
$display("PASSED");
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate parameter passing override in module declaration.
//
// Build a single line of storage - Note it\'s
//
module reg32 (clk,we, din, dout);
parameter WIDTH=32;
input\t\t\twe;
input\t\t\tclk;
input [WIDTH-1:0]\tdin;
output [WIDTH-1:0]\tdout;
reg [WIDTH-1:0] store;
always @(posedge clk)
if(we)
store <= din;
assign dout = store ;
endmodule
module memory(clk, we, addr, din, dout);
parameter WIDTH=8;
input\t\t\tclk;
input\t\t\twe;
input [1:0]\t\taddr;
input [WIDTH-1:0]\tdin;
output [WIDTH-1:0]\tdout;
reg [WIDTH-1:0]\tdout;
wire [WIDTH-1:0]\tdout0,dout1,dout2,dout3;
reg\t\t\twe0,we1,we2,we3;
reg32 #(WIDTH) reg0 (.clk(clk),.we(we0),.din(din[WIDTH-1:0]),
.dout(dout0[WIDTH-1:0]));
reg32 #(WIDTH) reg1 (.clk(clk),.we(we1),.din(din[WIDTH-1:0]),
.dout(dout1[WIDTH-1:0]));
reg32 #(WIDTH) reg2 (.clk(clk),.we(we2),.din(din[WIDTH-1:0]),
.dout(dout2[WIDTH-1:0]));
reg32 #(WIDTH) reg3 (.clk(clk),.we(we3),.din(din[WIDTH-1:0]),
.dout(dout3[WIDTH-1:0]));
//
// Build we decode
//
always @(addr or we)
case (addr)
2\'b00: begin
we0 = we;
we1 = 0;
we2 = 0;
we3 = 0;
end
2\'b01: begin
we0 = 0;
we1 = we;
we2 = 0;
we3 = 0;
end
2\'b10: begin
we0 = 0;
we1 = 0;
we2 = we;
we3 = 0;
end
2\'b11: begin
we0 = 0;
we1 = 0;
we2 = 0;
we3 = we;
end
endcase
//
// Connect dout to register output
//
always @(addr or dout0 or dout1 or dout2 or dout3)
case (addr)
2\'b00: dout = dout0;
2\'b01: dout = dout1;
2\'b10: dout = dout2;
2\'b11: dout = dout3;
endcase
endmodule
module top;
parameter WIDTH=8;
reg\t\t\tclk;
reg\t\t\twe;
reg [1:0]\t\taddr;
reg [WIDTH-1:0]\t\tdin;
reg\t\t\terror;
wire [WIDTH-1:0]\t\tdout;
memory mem (clk, we, addr, din, dout);
initial
begin
// $dumpfile("test.vcd");
// $dumpvars(0,top.mem.reg0);
clk = 0;
error =0;
#3;
we = 1;
addr = 0;
din = 32\'b0_00;
#10;
addr = 1;
din = 32\'h1;
#10;
addr = 2;
din = 32\'h2;
#10;
addr = 3;
din = 32\'h3;
#10;
we = 0;
addr = 0;
#1;
if(dout[7:0] !== 8\'h00)
begin
$display("FAILED - Ram[0] not 0, is %h",dout[7:0]);
error = 1;
end
if(error == 0)
$display("PASSED");
$finish ;
end
always #(5) clk = ~clk;
endmodule
|
//
// Copyright (c) 1999 Thomas Coonan ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
//
// Just a little demo of some FSM techniques, including One-Hot and
// using \'default\' settings and the case statements to selectively
// update registers (sort of like J-K flip-flops).
//
// tom coonan, 12/98.
//
// SDW - modified test to check final X and Y value... and print out
// PASSED if it\'s okay.
//
module onehot (clk, resetb, a, b, x, y);
input clk;
input resetb;
input [7:0] a;
input [7:0] b;
output [7:0] x;
output [7:0] y;
// Use One-Hot encoding. There will be 16 states.
//
reg [15:0] state, next_state;
// These are working registers. Declare the register itself (e.g. \'x\') and then
// the input bus used to load in a new value (e.g. \'x_in\'). The \'x_in\' bus will
// physically be a wire bus and \'x\' will be the flip-flop register (\'x_in\' must
// be declared \'reg\' because it\'s used in an always block.
//
reg [7:0] x, x_in;
reg [7:0] y, y_in;
// Update state. \'state\' is the actual flip-flop register and next_state is the combinatorial
// bus used to update \'state\'\'s value. Check for the ZERO state which means an unexpected
// next state was computed. If this occurs, jump to our initialization state; state[0].
//
// It is considered good practice by many designers to seperate the combinatorial
// and sequential aspects of state registers, and often registers in general.
//
always @(posedge clk or negedge resetb) begin
if (~resetb) state = 0;
else begin
if (next_state == 0) begin
state = 16\'h0001;
end
else begin
state = next_state;
end
end
end
// Implement the X flip-flop register. Always load the input bus into the register.
// Reset to zero.
//
always @(posedge clk or negedge resetb) begin
if (~resetb) x = 0;
else x = x_in;
end
// Implement the Y flip-flop register. Always load the input bus into the register.
// Reset to zero.
//
always @(posedge clk or negedge resetb) begin
if (~resetb) y = 0;
else y = y_in;
end
// Generate the next_state function. Also, based on the current state, generate
// any new values for X and Y.
//
always @(state or a or b or x or y) begin
// *** Establish defaults.
// Working registers by default retain their current value. If any particular
// state does NOT need to change a register, then it doesn\'t have to reference
// the register at all. In these cases, the default below takes affect. This
// turns out to be a pretty succinct way to control stuff from the FSM.
//
x_in = x;
y_in = y;
// State by default will be cleared. If we somehow ever got into an unknown
// state, then the default would throw state machine back to zero. Look
// at the sequential \'always\' block for state to see how this is handled.
//
next_state = 0;
// One-Hot State Machine Encoding.
//
// *** Using a 1\'b1 in the case statement is the trick to doing One-Hot...
// DON\'T include a \'default\' clause within the case because we want to
// establish the defaults above. ***
//
case (1\'b1) // synopsys parallel_case
// Initialization state. Set X and Y register to some interesting starting values.
//
state[0]:
begin
x_in = 8\'d20;
y_in = 8\'d100;
next_state[1] = 1\'b1;
end
// Just for fun.. Jump through states..
state[1]: next_state[2] = 1\'b1;
state[2]: next_state[3] = 1\'b1;
state[3]: next_state[4] = 1\'b1;
state[4]: next_state[5] = 1\'b1;
state[5]: next_state[6] = 1\'b1;
state[6]: next_state[7] = 1\'b1;
// Conditionally decrement Y register.
state[7]:
begin
if (a == 1) begin
y_in = y - 1;
next_state[1] = 1\'b1;
end
else begin
next_state[8] = 1\'b1;
end
end
// Just for fun.. Jump through states..
state[8]: next_state[9] = 1\'b1;
state[9]: next_state[10] = 1\'b1;
state[10]: next_state[11] = 1\'b1;
// Conditionally increment X register.
state[11]:
begin
if (b == 1) begin
x_in = x + 1;
next_state[1] = 1\'b1;
end
else begin
next_state[12] = 1\'b1;
end
end
// Just for fun.. Jump through states..
state[12]: next_state[13] = 1\'b1;
state[13]: next_state[14] = 1\'b1;
state[14]: next_state[15] = 1\'b1;
state[15]: next_state[1] = 1\'b1; // Don\'t go back to our
// initialization state, but state
// following that one.
endcase
end
endmodule
// synopsys translate_off
module test_onehot;
reg clk, resetb;
reg [7:0] a;
reg [7:0] b;
wire [7:0] x;
wire [7:0] y;
reg error;
// Instantiate module.
//
onehot onehot (
.clk(clk),
.resetb(resetb),
.a(a),
.b(b),
.x(x),
.y(y)
);
// Generate clock.
//
initial
begin
clk = 0;
forever begin
#10 clk = ~clk;
end
end
// Reset..
//
initial begin
resetb = 0;
#33 resetb = 1;
end
// Here\'s the test.
//
// Should see X and Y get initially loaded with their starting values.
// As long as a and b are zero, nothing should change.
// When a is asserted, Y should slowly decrement. When b is asserted, X should
// slowly increment. That\'s it.
//
initial begin
`ifdef DEBUG
$dumpfile("test.vcd");
$dumpvars(0,test_onehot);
`endif // DEBUG
error = 0;
a = 0;
b = 0;
repeat (64) @(posedge clk);
#1
// Y should be decremented..
a = 1;
b = 0;
repeat (256) @(posedge clk);
#1
// X should be incremented..
a = 0;
b = 1;
repeat (256) @(posedge clk);
if (x !== 8\'d43)
begin
error = 1;
$display("FAILED - X Expected value 43, is %d",x);
end
if (y !== 8\'d64)
begin
error = 1;
$display("FAILED - Y Expected value 63, is %d",y);
end
if(error == 0)
$display("PASSED");
$finish;
end
// Monitor the module.
//
endmodule
|
program main;
int foo;
int bar;
initial begin
bar = 1;
for (foo = 1 ; foo < 10 ; ++foo) begin
\t bar <= bar * foo;
\t #1 $display("foo = %d, bar=%d", foo, bar);
end
end
final begin
if (foo !== 10 || bar !== 362_880) begin
\t $display("FAILED -- foo=%d", foo);
end else $display("PASSED");
end
endprogram // main
|
/*
* This tests a trivial class. In SystemVerilong, classes are garbage
* collected dynamic objects, so this tests the creation of class objects,
* some simple manipulations, copying (by reference) and cleanup.
*/
program main;
// Trivial example of a class
class foo_t ;
int a;
int b;
endclass : foo_t // foo_t
foo_t obj, copy;
initial begin
if (obj != null) begin
\t $display("FAILED -- objects must start out null.");
\t $finish;
end
obj = new;
if (obj == null) begin
\t $display("FAILED -- After allocation, object is NOT null.");
\t $finish;
end
// This is the most trivial assignment of class properties.
obj.a = 10;
obj.b = 11;
if (obj.a != 10 || obj.b != 11) begin
\t $display("FAILED -- assign to object: obj.a=%0d, obj.b=%0d", obj.a, obj.b);
\t $finish;
end
// This actually makes a shared link to the same object. This
// will make a link to the object.
copy = obj;
if (copy.a != 10 || copy.b != 11) begin
\t $display("FAILED -- copy object: copy.a=%0d, copy.b=%0d", copy.a, copy.b);
\t $finish;
end
copy.a = 7;
copy.b = 8;
if (obj.a != 7 || obj.b != 8) begin
\t $display("FAILED -- check shared-ness: obj.a=%0d, obj.b=%0d", obj.a, obj.b);
\t $finish;
end
// Clear the copy pointer. obj still exists, though.
copy = null;
if (obj.a != 7 || obj.b != 8) begin
\t $display("FAILED -- clear copy preserved link: obj.a=%0d, obj.b=%0d", obj.a, obj.b);
\t $finish;
end
// This is the last reference to the class, so it should cause
// the object to be destroyed. How to test that?
obj = null;
$display("PASSED");
$finish;
end
endprogram // main
|
// Copyright (c) 2016 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for 'image attribute in VHDL.
module image_attr_test;
logic start_test;
image_attr_entity dut(start_test);
initial begin
start_test = 1'b0;
#1 start_test = 1'b1;
end
endmodule
|
/*
* Copyright (c) 2001 Stephan Boettcher <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: many_drivers.v,v 1.2 2001/07/21 02:30:44 stevewilliams Exp $
// $Log: many_drivers.v,v $
// Revision 1.2 2001/07/21 02:30:44 stevewilliams
// Get the expected blended values right.
//
// Revision 1.1 2001/07/18 01:22:26 sib4
// test for nets with many drivers
//
module test;
reg [66:0] in;
wire out;
buf (out, in[ 0]);
buf (out, in[ 1]);
buf (out, in[ 2]);
buf (out, in[ 3]);
buf (out, in[ 4]);
buf (out, in[ 5]);
buf (out, in[ 6]);
buf (out, in[ 7]);
buf (out, in[ 8]);
buf (out, in[ 9]);
buf (out, in[10]);
buf (out, in[11]);
buf (out, in[12]);
buf (out, in[13]);
buf (out, in[14]);
buf (out, in[15]);
buf (out, in[16]);
buf (out, in[17]);
buf (out, in[18]);
buf (out, in[19]);
buf (out, in[20]);
buf (out, in[21]);
buf (out, in[22]);
buf (out, in[23]);
buf (out, in[24]);
buf (out, in[25]);
buf (out, in[26]);
buf (out, in[27]);
buf (out, in[28]);
buf (out, in[29]);
buf (out, in[30]);
buf (out, in[31]);
buf (out, in[32]);
buf (out, in[33]);
buf (out, in[34]);
buf (out, in[35]);
buf (out, in[36]);
buf (out, in[37]);
buf (out, in[38]);
buf (out, in[39]);
buf (out, in[40]);
buf (out, in[41]);
buf (out, in[42]);
buf (out, in[43]);
buf (out, in[44]);
buf (out, in[45]);
buf (out, in[46]);
buf (out, in[47]);
buf (out, in[48]);
buf (out, in[49]);
buf (out, in[50]);
buf (out, in[51]);
buf (out, in[52]);
buf (out, in[53]);
buf (out, in[54]);
buf (out, in[55]);
buf (out, in[56]);
buf (out, in[57]);
buf (out, in[58]);
buf (out, in[59]);
buf (out, in[60]);
buf (out, in[61]);
buf (out, in[62]);
buf (out, in[63]);
buf (out, in[64]);
buf (out, in[65]);
buf (out, in[66]);
reg\t err;
// Verilog-XL yields out=x for all but the first two
initial
begin
\terr = 0;
\tin = 67\'b0;
\t#1 $display("in=%b out=%b", in, out);
\tif (out!==1\'b0) err = 1;
\tin = ~67\'b0;
\t#1 $display("in=%b out=%b", in, out);
\tif (out!==1\'b1) err = 1;
\tin = 67\'bz;
\t#1 $display("in=%b out=%b", in, out);
\tif (out!==1\'bx) err = 1;
\tin = 67\'bx;
\t#1 $display("in=%b out=%b", in, out);
\tif (out!==1\'bx) err = 1;
\tin = 67\'h 5_55555555_55555555;
\t#1 $display("in=%b out=%b", in, out);
\tif (out!==1\'bx) err = 1;
\tin = ~67\'h 5_55555555_55555555;
\t#1 $display("in=%b out=%b", in, out);
\tif (out!==1\'bx) err = 1;
\tin = 67\'h 0_xxxxxxxx_00000000;
\t#1 $display("in=%b out=%b", in, out);
\tif (out!==1\'bx) err = 1;
\tin = ~67\'h 0_xxxxxxxx_00000000;
\t#1 $display("in=%b out=%b", in, out);
\tif (out!==1\'bx) err = 1;
\tin = 67\'h x_xxxxxxxx_00000000;
\t#1 $display("in=%b out=%b", in, out);
\tif (out!==1\'bx) err = 1;
\tin = ~67\'h x_xxxxxxxx_00000000;
\t#1 $display("in=%b out=%b", in, out);
\tif (out!==1\'bx) err = 1;
\tin = 67\'h x_55555555_55555555;
\t#1 $display("in=%b out=%b", in, out);
\tif (out!==1\'bx) err = 1;
\tin = ~67\'h x_55555555_55555555;
\t#1 $display("in=%b out=%b", in, out);
\tif (out!==1\'bx) err = 1;
\tin = 67\'h 1_ffffxxxx_00000000;
\t#1 $display("in=%b out=%b", in, out);
\tif (out!==1\'bx) err = 1;
\tin = ~67\'h 1_ffffxxxx_00000000;
\t#1 $display("in=%b out=%b", in, out);
\tif (out!==1\'bx) err = 1;
\tif (err)
\t $display("FAILED");
\telse
\t $display("PASSED");
\t$finish;
end
endmodule
|
//
// Verifies disable terminates a forked forever.
//
module test;
initial begin
fork: F
forever #10;
disable F;
join
$display("PASSED");
$finish;
end
initial begin
#20;
$display("FAILED");
$finish;
end
endmodule
|
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
module top;
reg pass;
reg [5:0] cond;
reg [2:1] expr;
integer result;
always @(cond or expr) begin
casex (cond)
6\'b01_??10 : result = 1;
{2\'b10, 4\'b??10} : result = 2;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
{expr[1:0], 4\'b??01} : result = 3;
expr[11:6] : result = 4;
`else
{expr[1], 1\'bx, 4\'b??01} : result = 3;
6\'bxxxxxx : result = 4;
`endif
default : result = 0;
endcase
end
initial begin
pass = 1\'b1;
expr = 2\'b10;
cond = 6\'b01_xx10;
#1 if (result != 1) begin
$display("Failed case expr 1 test, got expr %0d", result);
pass = 1\'b0;
end
cond = 6\'bxx_xxxx;
#1 if (result != 1) begin
$display("Failed case expr 1a test, got expr %0d", result);
pass = 1\'b0;
end
cond = 6\'b10_zz10;
#1 if (result != 2) begin
$display("Failed case expr 2 test, got expr %0d", result);
pass = 1\'b0;
end
cond = 6\'b0x_zz01;
#1 if (result != 3) begin
$display("Failed case expr 3 test, got expr %0d", result);
pass = 1\'b0;
end
cond = 6\'b11_1111;
#1 if (result != 4) begin
$display("Failed case expr 1a test, got expr %0d", result);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
module check (input signed [22:0] a, b, c);
wire signed [22:0] int_AB;
assign int_AB = a + b;
always @(a, b, int_AB, c) begin
#1;
if (int_AB !== c) begin
$display("ERROR");
$finish;
end
end
endmodule
module stimulus (output reg signed [22:0] A, B);
parameter MAX = 1 << 23;
parameter S = 10000;
int unsigned i;
initial begin
A = 0; B= 0;
for (i=0; i<S; i=i+1) begin
#1 A = $random % MAX;
B = $random % MAX;
end
#1 A = 1;
B = -1;
#1 A = 23\'h7fffff;
#1 B = 23\'h7fffff;
#1 B = 0;
// x and z injected on A
for (i=0; i<S/2; i=i+1) begin
#1 A = $random % MAX;
A = xz_inject (A);
end
// x and z injected on B
#1 A = 1;
for (i=0; i<S/2; i=i+1) begin
#1 B = $random % MAX;
B = xz_inject (B);
end
// x and z injected on A, B
for (i=0; i<S; i=i+1) begin
#1 A = $random % MAX;
B = $random % MAX;
A = xz_inject (A);
B = xz_inject (B);
end
end
// injects some x, z values on 23 bits arguments
function [22:0] xz_inject (input signed [22:0] value);
integer i, temp;
begin
temp = {$random};
for (i=0; i<23; i=i+1)
begin
if (temp[i] == 1\'b1)
begin
temp = $random;
if (temp <= 0)
value[i] = 1\'bx; // \'x noise
else
value[i] = 1\'bz; // \'z noise
end
end
xz_inject = value;
end
endfunction
endmodule
module test;
wire signed [22:0] a, b;
wire signed [22:0] r;
stimulus stim (.A(a), .B(b));
sadd23 duv (.a_i(a), .b_i(b), .c_o(r) );
check check (.a(a), .b(b), .c(r) );
initial begin
#40000;
$display("PASSED");
$finish;
end
endmodule
|
module test;
bit [7:0] mema[];
bit [7:0] memb[];
reg failed = 0;
initial begin
mema = new[4] (\'{8\'d1,8\'d2,8\'d3,8\'d4});
$display("%x %x %x %x", mema[0], mema[1], mema[2], mema[3]);
memb = new[4] (mema);
$display("%x %x %x %x", memb[0], memb[1], memb[2], memb[3]);
if (memb[0] !== 8\'d1 || memb[1] !== 8\'d2 || memb[2] !== 8\'d3 || memb[3] !== 8\'d4) failed = 1;
memb = new[5] (memb);
$display("%x %x %x %x %x", memb[0], memb[1], memb[2], memb[3], memb[4]);
if (memb[0] !== 8\'d1 || memb[1] !== 8\'d2 || memb[2] !== 8\'d3 || memb[3] !== 8\'d4 || memb[4] !== 8\'b0) failed = 1;
memb = new[3] (memb);
$display("%x %x %x", memb[0], memb[1], memb[2]);
if (memb[0] !== 8\'d1 || memb[1] !== 8\'d2 || memb[2] !== 8\'d3) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program tests some tricky-to-compile strength syntax. Show that
* gates can drive a wire with various strengths and be properly resolved.
*/
module main();
reg pullval;
wire (weak0, weak1) value = pullval;
reg\ten0, en1;
/* This buffer will drive a strong 1 to value if en0 is 1, otherwise
it will go HiZ. */
buf (highz0, strong1) drive0(value, en0);
/* This inverter will drive a strong 0 to value if en1 is 1, otherwise
is will go HiZ. */
not (strong0, highz1) drive1(value, en1);
initial begin
en0 = 0;
en1 = 0;
/* Make sure when the other drivers are disabled, the pullval
can pull the value up or down. The gates should be HiZ. */
pullval = 1;
#1 if (value !== 1\'b1) begin
\t $display("FAILED -- value is %b", value);
\t $finish;
end
pullval = 0;
#1 if (value !== 1\'b0) begin
\t $display("FAILED -- value is %b", value);
\t $finish;
end
/* When en0 is 1, drive0 puts a strong 1 onto value so the
pullval should not matter. */
en0 = 1;
pullval = 1;
#1 if (value !== 1\'b1) begin
\t $display("FAILED -- en0==%b en1==%b pull==%b value==%b",
\t\t en0, en1, pullval, value);
\t $finish;
end
pullval = 0;
#1 if (value !== 1\'b1) begin
\t $display("FAILED -- en0==%b en1==%b pull=0%b value==%b",
\t\t en0, en1, pullval, value);
\t $finish;
end
/* When en1 is 1, drive1 puts a strong 0 onto value so the
pullval should not matter. */
en0 = 0;
en1 = 1;
pullval = 1;
#1 if (value !== 1\'b0) begin
\t $display("FAILED -- en0==%b en1==%b pull=0%b value==%b",
\t\t en0, en1, pullval, value);
\t $finish;
end
pullval = 0;
#1 if (value !== 1\'b0) begin
\t $display("FAILED -- en0==%b en1==%b pull=0%b value==%b",
\t\t en0, en1, pullval, value);
\t $finish;
end
/* When both enables are 1, we have a double driven signal
and the value should be x. */
en0 = 1;
en1 = 1;
pullval = 1;
#1 if (value !== 1\'bx) begin
\t $display("FAILED -- en0==%b en1==%b pull=0%b value==%b",
\t\t en0, en1, pullval, value);
\t $finish;
end
pullval = 0;
#1 if (value !== 1\'bx) begin
\t $display("FAILED -- en0==%b en1==%b pull=0%b value==%b",
\t\t en0, en1, pullval, value);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
`timescale 1ns/1ps
module top;
realtime rtime;
time itime;
initial begin
repeat (5) begin
rtime = $realtime;
itime = $time;
$display("%t %.2f %2d, %t %0.2f %2d, %t %.2f, %t %0.2f, %t %.2f,",
$time, $time, $time, itime, itime, itime,
$realtime, $realtime, rtime, rtime, rtm($realtime),
rtm($realtime),, $time,, $realtime);
#0.6;
end
end
function real rtm;
input real rin;
rtm = rin;
endfunction
endmodule
|
module top;
reg pass = 1\'b1;
parameter one = 1\'b1;
parameter zero = 1\'b0;
wire [3:0] ca_tru = one ? 4\'b0001 : 4\'b0000;
wire [3:0] ca_fal = zero ? 4\'b0000 : 4\'b0010;
initial begin
#1;
if (ca_tru != 4\'b0001) begin
$display("FAILED: CA true expression (%b != 4\'b0001)", ca_tru);
pass = 1\'b0;
end
if (ca_fal != 4\'b0010) begin
$display("FAILED: CA false expression (%b != 4\'b0010)", ca_fal);
pass = 1\'b0;
end
if(pass) $display("PASSED");
end
endmodule
|
module top;
reg pass;
reg [1:0] in, shift, result;
reg signed [1:0] ins;
wire [1:0] ls = in << shift;
wire [1:0] als = in <<< shift;
wire [1:0] rs = in >> shift;
wire [1:0] rs2 = in >>> shift;
wire [1:0] ars = ins >> shift;
initial begin
pass = 1\'b1;
in = 2\'b01;
ins = 2\'b10;
shift = 2\'bx1;
#1
if (ls !== 2\'bxx) begin
$display("Failed << (CA), expected 2\'bxx, got %b", ls);
pass = 1\'b0;
end
if (als !== 2\'bxx) begin
$display("Failed <<< (CA), expected 2\'bxx, got %b", als);
pass = 1\'b0;
end
if (rs !== 2\'bxx) begin
$display("Failed >> (CA), expected 2\'bxx, got %b", rs);
pass = 1\'b0;
end
if (rs2 !== 2\'bxx) begin
$display("Failed >>> (CA), expected 2\'bxx, got %b", rs2);
pass = 1\'b0;
end
if (ars !== 2\'bxx) begin
$display("Failed >>> (signed, CA), expected 2\'bxx, got %b", ars);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
module test(input wire load, drain,
\t input wire clk, data,
\t output reg foo_nxt, bar_nxt);
reg\t\t foo, bar;
(* ivl_combinational *)
always @* begin
foo_nxt = foo;
bar_nxt = bar;
if (load) begin
\t foo_nxt = data;
\t bar_nxt = 1;
end else if (drain) begin
\t bar_nxt = 0;
end
end
always @(posedge clk) begin
foo <= foo_nxt;
bar <= bar_nxt;
end
endmodule // test
module main;
reg clk, load, drain, data;
wire foo, bar;
test dut (.clk(clk), .load(load), .drain(drain), .data(data),
\t .foo_nxt(foo), .bar_nxt(bar));
(* ivl_synthesis_off *)
initial begin
clk = 0;
load = 1;
drain = 0;
data = 1;
#1 clk = 1;
#1 clk = 0;
$display("%0t: load=%b, drain=%b, data=%b: foo=%b, bar=%b",
\t $time, load, drain, data, foo, bar);
if (foo !== 1 || bar !== 1) begin
\t $display("FAILED -- foo=%b, bar=%b (1)", foo, bar);
\t $finish;
end
data = 0;
#1 clk = 1;
#1 clk = 0;
$display("%0t: load=%b, drain=%b, data=%b: foo=%b, bar=%b",
\t $time, load, drain, data, foo, bar);
if (foo !== 0 || bar !== 1) begin
\t $display("FAILED -- foo=%b, bar=%b (2)", foo, bar);
\t $finish;
end
load = 0;
drain = 1;
#1 ;
if (foo !== 0 || bar !== 0) begin
\t $display("FAILED -- foo=%b, bar=%b (3)", foo, bar);
\t $finish;
end
#1 clk = 1;
#1 clk = 0;
$display("%0t: load=%b, drain=%b, data=%b: foo=%b, bar=%b",
\t $time, load, drain, data, foo, bar);
$display("PASSED");
end
endmodule // main
|
module example;
reg [7:0] vec;
reg [3:0] ix;
wire vix = vec[ix];
initial begin
$display( " time ix vix vec" );
$display( " ---- ---- --- --------" );
$monitor( "%T %b %b %b", $time, ix, vix, vec );
vec = 8\'b00000000;
ix = 0; // 0
#100 ix = 1; // 100
#100 ix = 2; // 200
#100 ix = 3; // 300
#100 ix = 4; // 400
#100 ix = 5; // 500
#100 ix = 6; // 600
#100 ix = 7; // 700
#100 ix = 8; // 800
#100 ix = 4\'b001x; // 900
#100 ix = 4\'b01x0; // 1000
#100 ix = 4\'b0x01; // 1100
#100 ix = 0; // 1200
#100 vec[ix] <= 1\'b1; // 1300
#100 vec[ix] <= 1\'b0; // 1400
#100 ix = 3; // 1500
#100 vec[ix] <= 1\'b1; // 1600
#100 vec[ix] <= 1\'b0; // 1700
#100 ix = 6; // 1800
#100 vec[ix] <= 1\'b1; // 1900
#100 vec[ix] <= 1\'b0; // 2000
#100 ix = 8; // 2100
#100 vec[ix] <= 1\'b1; // 2200
#100 vec[ix] <= 1\'b0; // 2300
#100 ix = 4\'b010x; // 2400
#100 vec[ix] <= 1\'b1; // 2500
#100 vec[ix] <= 1\'b0; // 2600
#100 ix = 4\'b00x1; // 2700
#100 vec[ix] <= 1\'b1; // 2800
#100 vec[ix] <= 1\'b0; // 2900
#100 ix = 4\'b0x10; // 3000
#100 vec[ix] <= 1\'b1; // 3100
#100 vec[ix] <= 1\'b0; // 3200
#100 ix = 4\'bxxxx; // 3300
#100 vec[ix] <= 1\'b1; // 3400
#100 vec[ix] <= 1\'b0; // 3500
#100 $display( "Finish at time %T", $time );
end
endmodule
|
/* The original test case submitted for pr2715558 should not have
given the the results the bug reporter expected (see pr2986806).
This is a reworked version that does give those results.
*/
module pr2715558b();
wire sup1_sup0;
wire sup1_str0;
wire sup1_pl0;
wire sup1_we0;
assign (supply0, supply1) sup1_sup0 = 1\'b1;
assign (supply0, supply1) sup1_sup0 = 1\'b0;
assign (supply0, supply1) sup1_str0 = 1\'b1;
assign (strong0, strong1) sup1_str0 = 1\'b0;
assign (supply0, supply1) sup1_pl0 = 1\'b1;
assign (pull0, pull1) sup1_pl0 = 1\'b0;
assign (supply0, supply1) sup1_we0 = 1\'b1;
assign (weak0, weak1) sup1_we0 = 1\'b0;
initial begin
#1;
$display("sup1_sup0 resulted in: %b", sup1_sup0);
$display("sup1_str0 resulted in: %b", sup1_str0);
$display("sup1_pl0 resulted in: %b", sup1_pl0);
$display("sup1_we0 resulted in: %b", sup1_we0);
end
wire str1_sup0;
wire str1_str0;
wire str1_pl0;
wire str1_we0;
assign (strong0, strong1) str1_sup0 = 1\'b1;
assign (supply0, supply1) str1_sup0 = 1\'b0;
assign (strong0, strong1) str1_str0 = 1\'b1;
assign (strong0, strong1) str1_str0 = 1\'b0;
assign (strong0, strong1) str1_pl0 = 1\'b1;
assign (pull0, pull1) str1_pl0 = 1\'b0;
assign (strong0, strong1) str1_we0 = 1\'b1;
assign (weak0, weak1) str1_we0 = 1\'b0;
initial begin
#1;
$display("str1_sup0 resulted in: %b", str1_sup0);
$display("str1_str0 resulted in: %b", str1_str0);
$display("str1_pl0 resulted in: %b", str1_pl0);
$display("str1_we0 resulted in: %b", str1_we0);
end
wire pl1_sup0;
wire pl1_str0;
wire pl1_pl0;
wire pl1_we0;
assign (pull0, pull1) pl1_sup0 = 1\'b1;
assign (supply0, supply1) pl1_sup0 = 1\'b0;
assign (pull0, pull1) pl1_str0 = 1\'b1;
assign (strong0, strong1) pl1_str0 = 1\'b0;
assign (pull0, pull1) pl1_pl0 = 1\'b1;
assign (pull0, pull1) pl1_pl0 = 1\'b0;
assign (pull0, pull1) pl1_we0 = 1\'b1;
assign (weak0, weak1) pl1_we0 = 1\'b0;
initial begin
#1;
$display("pl1_sup0 resulted in: %b", pl1_sup0);
$display("pl1_str0 resulted in: %b", pl1_str0);
$display("pl1_pl0 resulted in: %b", pl1_pl0);
$display("pl1_we0 resulted in: %b", pl1_we0);
end
wire we1_sup0;
wire we1_str0;
wire we1_pl0;
wire we1_we0;
assign (weak0, weak1) we1_sup0 = 1\'b1;
assign (supply0, supply1) we1_sup0 = 1\'b0;
assign (weak0, weak1) we1_str0 = 1\'b1;
assign (strong0, strong1) we1_str0 = 1\'b0;
assign (weak0, weak1) we1_pl0 = 1\'b1;
assign (pull0, pull1) we1_pl0 = 1\'b0;
assign (weak0, weak1) we1_we0 = 1\'b1;
assign (weak0, weak1) we1_we0 = 1\'b0;
initial begin
#1;
$display("we1_sup0 resulted in: %b", we1_sup0);
$display("we1_str0 resulted in: %b", we1_str0);
$display("we1_pl0 resulted in: %b", we1_pl0);
$display("we1_we0 resulted in: %b", we1_we0);
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate casez/endcase w/ default
module main ();
reg error;
reg [2:0] val1,val2;
reg [2:0] result ;
always @( val1 )
casez (val1)
5\'b0000z: result = 0;
5\'b001z0: result = 1 ;
5\'b01zz0: result = 2;
default: result = 4;
endcase
initial
begin
error = 0;
val1 = 5\'b0000z ;
if(result !=0)
begin
$display("FAILED casez 3.10D - case (expr) lab1: ");
error = 1;
end
val1 = 5\'b001z0;
if(result !=1)
begin
$display("FAILED casez 3.10D - case (expr) lab2: ");
error = 1;
end
val1 = 5\'b1zzzz;\t// Should get no-action - expr = 3\'b011
if(result !=4)
begin
$display("FAILED casez 3.10D - case (expr) lab1: ");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
module test();
typedef enum { a, b, c } enum_type;
enum_type enum_value;
assign enum_value = 1;
endmodule
|
/* Copyright (C) 2000 Stephen G. Tell
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this software; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
* Boston, MA 02111-1307 USA
*/
/* fdisplay1 - test $fwrite and $fdisplay system tasks without using $fopen
*
* NB: this may need a little tweaking, as I\'m not sure that all verilogs
* have the predefined $fdisplay descriptors 2 and 3 matching what
* vpi_mcd_printf provides.
*/
module fdisplay1;
integer fp;
reg [7:0] a;
initial begin
$display("message to stdout (from $display)\
");
$fwrite(1, "another message (via fwrite) ");
$fdisplay(1,"to stdout\
(via fdisplay)");
#5
a = 8\'h5a;
$fwrite(1, "a = %b at %0t\
", a, $time);
$finish(0);
end // initial begin
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This test checks that the upwards search for a name stops at a
* module boundary. In this example, the q variable in the instance
* "inst" of the test module should be an implicit wire, even though
* it is placed into the containing main scope that has a wire q in it.
*/
module test(p);
output p;
wire q = 1;
assign p = q;
endmodule // test
module main;
wire q = 0;
wire sig;
test inst(sig);
initial begin
#1 if (q !== 1\'b0) begin
\t $display("FAILED -- main.q == %b", q);
\t $finish;
end
if (sig !== 1\'b1) begin
\t $display("FAILED -- main.test.q == %b", sig);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
module main ();
reg [31:0] tdelay;
reg [3:0] var1,var2;
reg error;
always @(var1)
#tdelay var2 = var1;
initial
begin
error = 0;
tdelay = 5;
# 1;\t\t\t// This removes race between tdelay5 and var2.
var2 = 0;
#1 ;
var1 = 1;\t\t// Now twiddle var1 to cause var2 change 5ns later.
#1 ;
if(var2 != 0)
begin
$display("FAILED at %t",$time);
error = 1;
end
#1;
if(var2 != 0)
begin
$display("FAILED at %t",$time);
error = 1;
end
#1;
if(var2 != 0)
begin
$display("FAILED at %t",$time);
error = 1;
end
#1;
if(var2 != 0)
begin
$display("FAILED at %t",$time);
error = 1;
end
#1;
if(var2 != 1)
begin
$display("FAILED at %t",$time);
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule
|
module main;
reg [2:0] Q;
reg\t clk, clr, up, down;
(*ivl_synthesis_off *)
initial begin
clk = 0;
up = 0;
down = 0;
clr = 1;
#1 clk = 1;
#1 clk = 0;
if (Q !== 0) begin
\t $display("FAILED");
\t $finish;
end
up = 1;
clr = 0;
#1 clk = 1;
#1 clk = 0;
#1 clk = 1;
#1 clk = 0;
if (Q !== 3\'b010) begin
\t $display("FAILED");
\t $finish;
end
up = 0;
down = 1;
#1 clk = 1;
#1 clk = 0;
if (Q !== 3\'b001) begin
\t $display("FAILED");
\t $finish;
end
down = 0;
#1 clk = 1;
#1 clk = 0;
if (Q !== 3\'b001) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
$finish;
end
/*
* This statement models a snythesizable UP/DOWN counter. The up
* and down cases are enabled by up and down signals. If both
* signals are absent, the synthesizer should take the implicit
* case that Q <= Q;
*/
(* ivl_synthesis_on *)
always @(posedge clk, posedge clr)
if (clr) begin
Q <= 0;
end else begin
\tif (up)
\t Q <= Q + 1;
\telse if (down)
\t Q <= Q - 1;
end
endmodule // main
|
module main;
reg [7:0] foo;
reg [7:0] bar;
initial begin
foo = \'hff;
if ($bits(foo) !== 8) begin
\t $display("FAILED -- $bits(foo) = %d", $bits(foo));
\t $finish;
end
if ($bits( 4\'(foo) ) !== 4) begin
\t $display("FAILED -- $bits( 4\'(foo) ) = %d", $bits( 4\'(foo) ));
\t $finish;
end
bar = {4\'d0, 4\'(foo)};
if (bar !== 8\'h0f) begin
\t $display("FAILED -- foo=%b, bar=%b", foo, bar);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
/*
* Copyright (c) 1998 Philips Semiconductors ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// 9/7/99 - SDW - Added a PASSED message - no functional checking needed
module test();
wire [1:0] a;
wire [9:0] b;
wire [0:9] d;
a a1(.a(c));
b b1(.a(a[0]));
c ci(.a({a, b}));
d d1(.a({d[0:9], a[1:0]}), .d(c));
f f(a);
a a3(a[1]);
a a4({a[1]});
g g({a,b});
e e();
initial
$display("PASSED");
endmodule
module a(a);
input a;
endmodule
module b(.a(b));
input b;
endmodule
module c(.a({b, c}), );
input [10:0] b;
input c;
endmodule
module d(.a({b, c}), d);
input [10:0] b;
input c, d;
endmodule
module e();
endmodule
module f({a, b});
input a, b;
endmodule
module g(a);
input [11:0] a;
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate NAND gate vector
//
module main;
reg globvar;
wire [15:0] out;
reg [15:0] a,b, rslt;
reg error;
// The test gate goes HERE!
nand foo [15:0] (out,a,b);
always @(a or b)
rslt = ~(a & b);
initial
begin // {
error = 0;
# 1;
for(a = 16\'h1; a != 16\'hffff; a = (a << 1) | 1)
begin // {
for(b = 16\'hffff; b !== 16\'h0; b = b >> 1)
begin // {
#1 ;
if(out !== rslt)
begin // {
$display("FAILED - GA NAND a=%h,b=%h,expct=%h - rcvd=%h",
a,b,rslt,out);
error = 1;
end // }
end // }
end // }
if( error == 0)
$display("PASSED");
end // }
endmodule // main
|
//
// Copyright (c) 2002 Stephen Williams ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
/*
* This function captures the correctness of a non-constant delay
* that is internal to a non-blocking assignment.
*/
module main;
reg [7:0] delay = 0;
reg\t step;
initial begin
delay = 2;
step = 0;
step <= #(delay) 1;
#1 if (step !== 0) begin
\t $display("FAILED -- step=%b at time=1", step);
\t $finish;
end
#2 if (step !== 1) begin
\t $display("FAILED == step=%b at time=3", step);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
/*
* This demonstrates that strings can be used as
* constructed formats in $display et al.
*/
module main;
string foo;
initial begin
foo = "PAXXED";
$display("foo.len()=%0d (s.b. 6)", foo.len());
if (foo.len() != 6) begin
\t $display("FAILED -- foo.len() = %0d", foo.len());
\t $finish;
end
$display("foo[-1]=%b (s.b. 00000000)", foo[-1]);
if (foo[-1] != \'h00) begin
\t $display("FAILED -- foo[-1]=%h", foo[-1]);
\t $finish;
end
$display("foo[7]=%b (s.b. 00000000)", foo[7]);
if (foo[7] != \'h00) begin
\t $display("FAILED -- foo[7]=%h", foo[7]);
\t $finish;
end
$display("foo[4]=%b (s.b. 01000101)", foo[4]);
if (foo[4] != \'h45) begin
\t $display("FAILED -- foo[4]=%h", foo[4]);
\t $finish;
end
foo[2] = \'h00;
if (foo != "PAXXED") begin
\t $display("FAILED -- foo=%0s (1)", foo);
\t $finish;
end
foo[2]=\'h53;
foo[3]=\'h53;
$display(foo);
end
endmodule // main
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always disable task_identifier ;
module main ;
reg [3:0] value1 ;
task foo ;
value1 = #1 1;
endtask
initial
begin
value1 = 0;
#2 ;
$display("value = %d",value1);
#1 ;
$finish ;
end
always disable foo ;
endmodule
|
/*
* Copyright (c) 1998 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This demonstrates proper handling of unknown values in decimal output.
*/
module main();
initial
begin
$display("4\'bxxxx = %d", 4\'bxxxx);
$display("4\'bzzxx = %d", 4\'bzzxx);
$display("4\'bzzzz = %d", 4\'bzzzz);
$display("4\'b00zz = %d", 4\'b00zz);
$display("4\'b0000 = %d", 4\'b0000);
$display("4\'b0011 = %d", 4\'b0011);
$finish(0);
end
endmodule
|
`timescale 1ns/10ps
module top;
reg a, pass;
wire z;
time edge_time;
always @(z) begin
if ((z === 0) && (($time - edge_time) != 2)) begin
$display("Falling took %d, expected 2", $time - edge_time);
pass = 1\'b0;
end
if ((z === 1) && (($time - edge_time) != 1)) begin
$display("Rising took %d, expected 1", $time - edge_time);
pass = 1\'b0;
end
end
initial begin
pass = 1\'b1;
$sdf_annotate("ivltests/sdf_del.sdf", top);
#10;
edge_time = $time;
a = 1\'b0;
#10;
edge_time = $time;
a = 1\'b1;
#10 if (pass) $display("PASSED");
end
my_buf dut(z, a);
endmodule
module my_buf (output z, input a);
buf (z, a);
specify
(a => z) = (0, 0);
endspecify
endmodule
|
module test;
reg fail = 1\'b0;
reg [3:0] bus = 4\'b0;
wire [3:0] val = bus; // to check the propagated value is correct
initial begin
// Check the initial value.
#1 if (val !== 4\'b0) begin
$display("FAILED: initial value, got %b, expected 0000.", val);
fail = 1;
end
// Check a bit force and verify a normal bit assign does nothing.
#1 force bus[0] = 1\'b1;
bus[0] = 1\'bz;
#1 if (val !== 4\'b0001) begin
$display("FAILED: force of bus[0], got %b, expected 0001.", val);
fail = 1\'b1;
end
// Check a part force
#1 force bus[3:2] = 2\'b11;
#1 if (val !== 4\'b1101) begin
$display("FAILED: force of bus[3:2], got %b, expected 1101.", val);
fail = 1\'b1;
end
// Check that we can change an unforced bit.
#1 bus[1] = 1\'bz;
#1 if (val !== 4\'b11z1) begin
$display("FAILED: assignment of bus[1], got %b, expected 11z1.", val);
fail = 1\'b1;
end
#1 bus[1] = 1\'b0;
// Check a bit release.
#1 release bus[0];
bus = 4\'b000z;
#1 if (val !== 4\'b110z) begin
$display("FAILED: release of bus[0], got %b, expected 110z.", val);
fail = 1\'b1;
end
// Check a part release.
#1 release bus[3:2];
bus[3] = 1\'b0;
#1 if (val !== 4\'b010z) begin
$display("FAILED: release of bus[3:2], got %b, expected 010z.", val);
fail = 1\'b1;
end
// Check a force from the upper thread bits (>=8).
#1 force bus[2:1] = 2\'bx1;
#1 if (val !== 4\'b0x1z) begin
$display("FAILED: force of bus[2:1], got %b, expected 0x1z.", val);
fail = 1\'b1;
end
if (!fail) $display("PASSED");
end
endmodule
|
module test();
wire [1:0] b;
assign b[0] = 0;
a a(~b[0]);
endmodule
module a(b);
input b;
initial #1 if (b) $display("PASSED"); else $display("FAILED");
endmodule
|
module main;
wire [31:0] DB;
reg\t E;
X2 U (.DB(DB[31:8]), .E(E));
Y1 V (.DB(DB[7:0]), .E(E));
initial begin
E = 0;
#1 if (DB !== 32\'hzzzzzzzz) begin
\t $display("FAILED -- DB=%b", DB);
\t $finish;
end
E = 1;
#1 if (DB !== 32\'h9zzzzz87) begin
\t $display("FAILED -- DB=%b", DB);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule // main
module X2(inout wire [31:8] DB, input wire E);
X1 uu (.DB(DB[31:28]), .E(E));
endmodule // X2
module X1(inout wire [31:28] DB, input wire E);
wire foo = DB[31:28];
assign DB[31:28] = E? 4\'b1001 : 4\'bzzzz;
endmodule // sub
module Y1(inout wire [7:0] DB, input wire E);
wire foo = DB[7:0];
assign DB[7:0] = E? 8\'h87 : 8\'hzz;
endmodule // sub
|
module test();
reg [7:0] array[3:0][3:0];
initial begin
$dumpvars(0, array[0][0][0]);
end
endmodule
|
// Invalid packed dimensions
// This should generate a error message and not crash during elaboration
typedef logic [] T1;
typedef logic [0] T2;
typedef logic [-1] T3;
typedef logic [$] T4;
module test (
input [] port_a,
input [0] port_b,
output [-1] port_c,
output [$] port_d
);
\tlogic [$] a;
\tT1 b;
\tT1 [$] c;
\tlogic [0] d;
\tT2 e;
\tT2 [0] f;
\tlogic [-1] g;
\tT3 h;
\tT3 [-1] i;
\tlogic [$] j;
\tT4 k;
\tT4 [$] l;
endmodule
|
// Check that signed arguments to a sign cast are evaluated as self-determined.
module test;
reg signed [3:0] op1;
reg signed [2:0] op2;
reg [7:0] result;
bit failed = 1\'b0;
`define check(val, exp) \\
if (exp !== val) begin \\
$display("FAILED(%0d). Got %b, expected %b.", `__LINE__, val, exp); \\
failed = 1\'b1; \\
end
initial begin
// Addition tests
op1 = 4\'b1111; op2 = 3\'b111;
result = 8\'sd0 + signed\'(op1 + op2);
`check(result, 8\'b11111110);
result = 8\'sd0 + unsigned\'(op1 + op2);
`check(result, 8\'b00001110);
op1 = 4\'b1000; op2 = 3\'b011;
result = 8\'sd0 + signed\'(op1 + op2);
`check(result, 8\'b11111011);
result = 8\'sd0 + unsigned\'(op1 + op2);
`check(result, 8\'b00001011);
// Multiply tests
op1 = 4\'b0101; op2 = 3\'b100;
result = 8\'sd0 + signed\'(op1 * op2);
`check(result, 8\'b11111100);
result = 8\'sd0 + unsigned\'(op1 * op2);
`check(result, 8\'b00001100);
op1 = 4\'b0010; op2 = 3\'b100;
result = 8\'sd0 + signed\'(op1 * op2);
`check(result, 8\'b11111000);
result = 8\'sd0 + unsigned\'(op1 * op2);
`check(result, 8\'b00001000);
// Left ASR tests
op1 = 4\'b1010;
result = 8\'sd0 + signed\'(op1 <<< 1);
`check(result, 8\'b00000100);
result = 8\'sd0 + unsigned\'(op1 <<< 1);
`check(result, 8\'b00000100);
op1 = 4\'b0101;
result = 8\'sd0 + signed\'(op1 <<< 1);
`check(result, 8\'b11111010);
result = 8\'sd0 + unsigned\'(op1 <<< 1);
`check(result, 8\'b00001010);
// Right ASR tests
op1 = 4\'b0101;
result = 8\'sd0 + signed\'(op1 >>> 1);
`check(result, 8\'b00000010);
result = 8\'sd0 + unsigned\'(op1 >>> 1);
`check(result, 8\'b00000010);
op1 = 4\'b1010;
result = 8\'sd0 + signed\'(op1 >>> 1);
`check(result, 8\'b11111101);
result = 8\'sd0 + unsigned\'(op1 >>> 1);
`check(result, 8\'b00001101);
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
/*
* Copyright (c) 2000 Guy Hutchison ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module pullupdown;
// declare several bussed wires
wire pull_up_1, pull_down_1;
wire [7:0] pull_up_8, pull_down_8;
reg\t error;
// assign pullups to each wire
pullup (pull_up_1);
pulldown (pull_down_1);
pullup u8 [7:0] (pull_up_8);
pulldown d8 [7:0] (pull_down_8);
// create tristate drivers for each wire
reg\t driver_1;
reg [7:0] driver_8;
assign pull_up_1 = driver_1;
assign pull_down_1 = driver_1;
assign pull_up_8 = driver_8;
assign pull_down_8 = driver_8;
initial
begin : test_block
integer i;
// turn off all drivers
driver_1 = 1\'bz;
driver_8 = 8\'bz;
error = 0;
#1;
// check default values
if ((pull_up_1 !== 1\'b1) || (pull_down_1 !== 1\'b0) ||
\t (pull_up_8 !== 8\'hFF) || (pull_down_8 !== 8\'h00)) begin
\t $display("driver_8=%b, pull_up_8=%b, pull_down_8=%b",
\t\t driver_8, pull_up_8, pull_down_8);
\t $display("driver_1=%b, pull_up_1=%b, pull_down_1=%b",
\t\t driver_1, pull_up_1, pull_down_1);
\t error = 1;
end
for (i=0; i<256; i=i+1)
\tbegin
\t driver_1 = ~driver_1;
\t driver_8 = i;
\t $display ("Testing drivers with value %h", driver_8);
\t #1;
\t check_drivers;
\t #10;
\tend
if (error)
\t$display ("FAILED - pullupdown ");
else $display ("PASSED");
end // block: test_block
task check_drivers;
begin
if ((pull_up_1 !== driver_1) || (pull_down_1 !== driver_1) ||
\t (pull_up_8 !== driver_8) || (pull_down_8 !== driver_8)) begin
\t $display("driver_8=%b, pull_up_8=%b, pull_down_8=%b",
\t\t driver_8, pull_up_8, pull_down_8);
\t $display("driver_1=%b, pull_up_1=%b, pull_down_1=%b",
\t\t driver_1, pull_up_1, pull_down_1);
\t error = 1;
end
end
endtask // check_drivers
endmodule // pullupdown
|
// Check that using a type identifier that resolves to a type with a packed
// dimensions together with another packed dimensions as the base type for an
// enum results in an error.
module test;
typedef int T;
enum T [1:0] {
A
} e;
initial begin
$display("FAILED");
end
endmodule
|
/*
* Copyright (c) 2002 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
reg a;
reg b;
wire q = a & b;
initial begin
a = 1;
b = 0;
#1;
if (q !== 0) begin
\t $display("FAILED -- q did not start out right: %b", q);
\t $finish;
end
b = 1;
if (q !== 0) begin
\t // Since b takes the new value with a blocking assignment,
\t // it is up to the & gate to schedule the q change, and not
\t // actually push the change through.
\t $display("FAILED -- q changed too soon? %b", q);
\t $finish;
end
if (b !== 1) begin
\t $display("FAILED -- b value did not stick: %b", b);
\t $finish;
end
// The #0 delay lets the scheduler execute the change to the
// q value, so that we can read the correct value out.
#0 if (q !== 1) begin
\t $display("FAILED -- q did not change when it should: %b", q);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
`timescale 1us / 1ns
module usns;
initial begin
\t#123;
\t$mytest;
end
endmodule
`timescale 1ns / 1ns
module nsns;
initial begin
\t#456;
\t$mytest;
end
endmodule
|
// Test disable statements inside a constant function
module constfunc10();
function [31:0] pow2(input [5:0] x);
begin:body
pow2 = 1;
while (1) begin:loop
if (x == 0) disable body;
pow2 = 2 * pow2;
x = x - 1;
disable loop;
pow2 = 0;
end
end
endfunction
localparam val = pow2(8);
initial begin
$display("%0d", val);
if (val === 256)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
module test;
real x[], y[], z[];
real src[0:7];
int\t i;
initial begin
src[0] = 1.0;
src[1] = 2.0;
src[2] = 3.0;
src[3] = 4.0;
src[4] = 5.0;
src[5] = 6.0;
src[6] = 7.0;
src[7] = 8.0;
x = new [4];
for (i = 0; i < 4; i = i + 1) x[i] = src[i];
y = x;
z = new [4](x);
for (i = 0; i < 4; i = i + 1) y[i] = src[3 - i];
for (i = 0; i < 4; i = i + 1) z[i] = src[7 - i];
// Expected output:
// 1.00000 2.00000 3.00000 4.00000
// 4.00000 3.00000 2.00000 1.00000
// 8.00000 7.00000 6.00000 5.00000
$display(x[0],,x[1],,x[2],,x[3]);
$display(y[0],,y[1],,y[2],,y[3]);
$display(z[0],,z[1],,z[2],,z[3]);
end
endmodule
|
module automatic_error();
reg global;
task automatic auto_task;
reg local;
begin:block
force global = local;
end
endtask
endmodule
|
module top;
wire [1:0] out;
reg [1:0] in1, in2;
initial begin
$monitor($time,,"out=%d", out);
in1 = 2\'d1;
in2 = 2\'d2;
#1 force out = in1;
#1 force out = in2;
#1 release out;
end
endmodule
|
module top;
reg pass = 1\'b1;
integer count;
reg [2:0] icount;
reg clk = 0;
reg [3:0] in = 4\'h0;
reg [3:0] result;
always #10 clk = ~clk;
always #20 in = in + 4\'h1;
initial begin
count = 3;
result <= repeat(count) @(posedge clk) in;
if ($simtime != 0 || result !== 4\'bx) begin
$display("Failed repeat(3) blocked at %0t, expected 4\'hx, got %h",
$simtime, result);
pass = 1\'b0;
end
@(result);
if ($simtime != 50 || result !== 4\'h0) begin
$display("Failed repeat(3) at %0t, expected 4\'h0, got %h",
$simtime, result);
pass = 1\'b0;
end
#15;
count = 0;
result <= repeat(count) @(posedge clk) in;
@(result); // Reals happen faster so they can use an #0, vectors are slower.
if ($simtime != 65 || result !== 4\'h3) begin
$display("Failed repeat(0) at %0t, expected 4\'h3, got %h",
$simtime, result);
pass = 1\'b0;
end
#20;
count = -1;
result <= repeat(count) @(posedge clk) in;
@(result); // Reals happen faster so they can use an #0, vectors are slower.
if ($simtime != 85 || result !== 4\'h4) begin
$display("Failed repeat(-1) at %0t, expected 4\'h4, got %h",
$simtime, result);
pass = 1\'b0;
end
#20;
result <= @(posedge clk) 4\'h0;
result <= @(posedge clk) in; // This one sets the final value.
@(result);
if ($simtime != 110 || result !== 4\'h5) begin
$display("Failed @ at %0t, expected 4\'h5, got %h",
$simtime, result);
pass = 1\'b0;
end
icount = 3\'d2;
result <= @(posedge clk) 4\'h1;
result <= repeat(icount) @(posedge clk) 4\'h2;
result <= repeat(3) @(posedge clk) 4\'h3;
@(result);
if ($simtime != 130 || result !== 4\'h1) begin
$display("Failed first @ at %0t, expected 4\'h1, got %h",
$simtime, result);
pass = 1\'b0;
end
@(result);
if ($simtime != 150 || result !== 4\'h2) begin
$display("Failed second @ at %0t, expected 4\'h2, got %h",
$simtime, result);
pass = 1\'b0;
end
@(result);
if ($simtime != 170 || result !== 4\'h3) begin
$display("Failed third @ at %0t, expected 4\'h3, got %h",
$simtime, result);
pass = 1\'b0;
end
if (pass) $display("PASSED");
$finish;
end
endmodule
|
/*
* Copyright (c) 2001 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This test was inspired by PR#539. We check that the calculated bit
* select of a net in a continuous assignment gets bits in the right
* order and position. The trick here is that the bits are numbered
* from MSB to LSB.
*/
module main;
reg [0:63] target0 = 64\'h0040200000000000;
reg [1:64] target1 = 64\'h0040200000000000;
reg [6:0] idx;
wire mux0 = target0[idx];
wire mux1 = target1[idx+1];
initial begin
$display( "Using constant indices:" );
$display( " %b=v[ 9]", target0[ 9] );
if (target0[9] !== 1\'b1) begin
\t $display("FAILED -- target0[9] != 1");
\t $finish;
end
$display( " %b=v[18]", target0[18] );
if (target0[18] !== 1\'b1) begin
\t $display("FAILED -- target0[18] != 1");
\t $finish;
end
$display( " %b=v[45]", target0[45] );
if (target0[45] !== 1\'b0) begin
\t $display("FAILED -- target0[45] != 0");
\t $finish;
end
$display( " %b=v[54]", target0[54] );
if (target0[54] !== 1\'b0) begin
\t $display("FAILED -- target0[54] != 0");
\t $finish;
end
$display( "Using calcuated indices:" );
for (idx = 0 ; idx < 64 ; idx = idx + 1) begin
\t #1 $display("target0[%2d]=%b, mux0=%b", idx, target0[idx], mux0);
\t $display("target1[%2d]=%b, mux1=%b", idx+1, target1[idx+1], mux1);
\t if (target0[idx] !== mux0) begin
\t $display("FAILED -- target0[idx] != mux0");
\t $finish;
\t end
\t if (target1[idx+1] !== mux1) begin
\t $display("FAILED -- target1[idx+1] != mux1");
\t $finish;
\t end
end
$display("PASSED");
end
endmodule // main
|
// Check a missing local time precision.
`resetall
module no_ltp;
timeunit 1ns;
endmodule
|
module bug();
localparam Size = 24;
reg [2:0] Value;
integer n;
initial begin
for (n = 0; n < (Size/4); n = n + 1) begin
Value = (Size/4) - n - 1;
$display(Value);
end
end
endmodule
|
/*
* Copyright (c) 2004 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main();
reg [4:0] sum;
initial begin
// Self-determined expressions take their size from the
// operands. The compiler should thus make the constant
// expression below exactly 4 bits wide.
$display("Should be 0001: %b", 4\'d7 + 4\'d10);
if ($bits(4\'d7 + 4\'d10) != 4) begin
\t $display("FAILED -- bit width should be 4: %d",
\t\t $bits(4\'d7 + 4\'d10));
\t $finish;
end
// When assigning to an l-value, the expression, and
// by extension the operands, take on the width of the
// left side. This expansion should be passed all the
// way down the expression.
sum = 4\'d7 + 4\'d10;
$display("Should be 10001: %b", sum);
if (sum !== 5\'b1_0001) begin
\t $display("FAILED -- expression truncated?");
\t $finish;
end
$display("PASSED");
end
endmodule
|
// This module generates M pairs of N-1 bits unsigned numbers A, B
// and also serialises them starting from LSB bits between
// activation of active-high reset signal
module stimulus #(parameter N = 4, M = 10) (input clk,
output reg reset,
output reg sa, sb,
output reg unsigned [N-1:0] A, B );
parameter D = 5;
int unsigned i;
reg unsigned [N-1:0] r1, r2;
initial begin
repeat(M) begin
r1 = {$random} % N;
r2 = {$random} % N;
do_items(r1, r2);
end
end
task do_items (input unsigned [N-1:0] v1, v2);
begin
A = 0; B = 0; reset = 0;
do_reset();
A = v1; B = v2;
for (i=0; i<N; i=i+1) begin
#2 sa = A[i];
sb = B[i];
@(posedge clk);
end
#2 sa = 1\'b0;
sb = 1\'b0;
@(posedge clk);
end
endtask
task do_reset;
begin
@(posedge clk);
@(negedge clk) reset = 1\'b1;
repeat(D) @(negedge clk);
reset = 1\'b0;
end
endtask
endmodule
// This module takes M pairs of N-1 bits unsigned numbers A, B and a serial stream ss
// then it checks that following a negedge of a reset, after N positive clock cycles
// the reconstuction of N ss bits is equal to A+B.
module check #(parameter N = 4, M = 10)(input clk, reset, input unsigned [N-1:0] A, B, input ss);
reg unsigned [N:0] psum;
reg unsigned [N:0] ssum;
int unsigned i;
initial begin
repeat(M)
check_item();
end
task check_item;
begin
@(posedge reset);
@(negedge reset);
#2;
psum = A + B;
for (i=0; i<=N; i=i+1) begin
@(posedge clk);
#1;
ssum[i] = ss;
end
if (psum != ssum) begin
$display("ERROR");
$finish;
end
end
endtask
endmodule
module test;
parameter N = 8, M = 25;
parameter T = 10;
parameter S = (N+1+6)*M*T + 100; // 6 is duration of a reset
reg reset, clk;
wire sa, sb, ss;
wire [N-1:0] A, B;
initial begin
clk = 0;
forever #(T/2) clk = ~clk;
end
stimulus #(N, M) stim (.clk(clk), .reset(reset), .sa(sa), .sb(sb), .A(A), .B(B));
sa1 duv (.clk(clk), .reset(reset), .a_i(sa), .b_i(sb), .s_o(ss) );
check #(N, M) check (.clk(clk), .reset(reset), .A(A), .B(B), .ss(ss));
initial begin
#S;
$display("PASSED");
$finish;
end
endmodule
|
//
// Author: Pawel Szostek ([email protected])
// Date: 01.08.2011
`timescale 1ns/1ps
module match_bits_v(input [7:0] a,b, output reg [7:0] match);
integer i;
wire ab_xor;
always @(a or b) begin
for (i=7; i>=0; i=i-1) begin
match[i] = ~(a[i]^b[i]);
end
end
endmodule
module check(input [7:0] a,b,o_vhdl, o_verilog);
always @(a or b) begin
#1 if (o_vhdl !== o_verilog) begin
$display("ERROR!");
$display("VERILOG: ", o_verilog);
$display("VHDL: ", o_vhdl);
$finish;
end
end
endmodule
module stimulus (output reg [7:0] a,b);
parameter S = 20000;
int unsigned i,j,k,l;
initial begin //stimulate data
for (i=0; i<S; i=i+1) begin
#5;
for(k=0; k<8; k=k+1) begin
a[k] <= inject();
end
end
end
initial begin //stimulate data
for (i=0; i<S; i=i+1) begin
#4;
for(l=0; l<8; l=l+1) begin
b[l] <= inject();
end
end
#100 $display("PASSED");
$finish;
end
function inject();
reg [3:0] temp;
begin
temp = $random % 16;
if(temp >= 10)
inject = 1\'b1;
else
inject = 1\'b0;
end
endfunction
endmodule
module main;
wire [7:0] a,b,o_vhdl, o_verilog;
match_bits match_vhdl(a,b,o_vhdl);
match_bits_v match_verilog(a,b,o_verilog);
stimulus stim(a,b);
check c(a,b,o_vhdl, o_verilog);
endmodule
|
module test;
parameter SIZE = 3;
parameter PVALUE = 12;
localparam LVALUE = 88;
enum byte unsigned { UVAL[256] } unsignedbyte_enum;
enum byte { SVAL[100] } signedbyte_enum;
enum { ADD = 10, SUB[5], JMP[6:8]} E1; // page 28 LRM
enum { REGISTER[2] = 1, REGISTER[2:4] = 10 } vr; // page 28 LRM
enum { P[5] = 12 /*PVALUE*/, Q, S[3] = 88/*LVALUE*/} par_enum;
initial begin
// 1. Default anonymous enum data type should be int
// don\'t know yet how to quickly check this
//
// 1. Checking initialisations
//
// a. If the first name is not assigned it should be zero
if (UVAL0 !== 8\'h0 || SVAL0 !== 8\'h0)
begin
$display ("FAILED - First un-assigned element of enum type was not zero");
$finish;
end
// b. Checking initials E1 and vr
if (ADD != 10 || REGISTER0 != 1)
begin
$display ("FAILED - First initialised elements of enums E1 and vr were not elaborated properly");
$finish;
end
// A name without a value is automatically assigned and increment of the value of the
// previous name (Section 4.10 LRM)
// c. checking initial values for SUB (0-4) in E1
if (SUB0 != 11 || SUB1 != 12 || SUB2 != 13 || SUB3 != 14 || SUB4 != 15)
begin
$display ("FAILED - Initialised elements SUB (0-4) in enum E1 were not elaborated properly");
$finish;
end
// c. checking initial values for JMP (6-8) in E1
if (JMP6 != 16 || JMP7 != 17 || JMP8 != 18)
begin
$display ("FAILED - Initialised elements (6-8) JMP in enum E1 were not elaborated properly");
$finish;
end
// c. checking initial values in vr
if (REGISTER1 != 2 || REGISTER2 != 10 || REGISTER3 != 11 || REGISTER4 != 12)
begin
$display ("FAILED - Initialised elements REGISTER (1-4) in enum vr were not elaborated properly");
$finish;
end
// c. checking hand-picked values in unsignedbyte_enum
if (UVAL23 != 23 || UVAL91 != 91 || UVAL138 != 138 || UVAL207 != 207)
begin
$display ("FAILED - Initialised some UVAL in enum unsignedbyte_enum were not elaborated properly");
$display ("UVAL23 = %0d, UVAL91 = %0d, UVAL138 = %0d, UVAL207 = %0d", UVAL23, UVAL91, UVAL138, UVAL207);
$finish;
end
// c. checking hand-picked values in signedbyte_enum
if (SVAL7 != 7 || SVAL19 != 19 || SVAL87 != 87)
begin
$display ("FAILED - Initialised some SVAL in enum signedbyte_enum were not elaborated properly");
$display ("SVAL7 = %0d, SVAL19 = %0d, SVAL87 = %0d", SVAL7, UVAL91, SVAL19, SVAL87);
$finish;
end
// c. checking final values in unsignedbyte_enum and signedbyte_enum
if (UVAL255 != 255 || SVAL99 != 99)
begin
$display ("FAILED - Initialised final values UVAL and SVAL did not elaborate properly");
$display ("UVAL255 = %0d, SVAL99 = %0d", UVAL255, SVAL99);
$finish;
end
// constants elaborated from parameter
if (P0 != PVALUE+0 || P1 != PVALUE+1 || P2 != PVALUE+2 || P3 != PVALUE+3 || P4 != PVALUE + 4 || Q != PVALUE+5)
begin
$display ("FAILED - Initialised values P in par_enum were not elaborated properly");
$finish;
end
// constants elaborated from localparam
if (S0 != LVALUE+0 || S1 != LVALUE+1 || S2 != LVALUE+2)
begin
$display ("FAILED - Initialised values S in par_enum were not elaborated properly");
$finish;
end
#1;
// checking num method
if (unsignedbyte_enum.num != 256 || signedbyte_enum.num != 100 ||
E1.num != 9 || vr.num != 5 || par_enum.num != 9)
begin
$display ("FAILED - The num method does not report as expected");
$finish;
end
$display ("PASSED");
end
endmodule
|
// Check that it is possible to do a part select on a vector declared in
// package
package P;
reg [7:0] x = 8\'h5a;
reg [1:0][7:0] y = 16\'h5af0;
endpackage
module test;
initial begin
if (P::x[3:0] == 4\'ha && P::x[7:4] == 4\'h5 &&
P::y[0] == 8\'hf0 && P::y[1] == 8\'h5a) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
|
/*
* Copyright (c) 2001 Steve Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/* Check that display prints the right signed value. */
module signed1();
reg [7:0] x;
reg signed [7:0] y;
initial
begin
\tx = 8\'b0000_0011;
\ty = 8\'b1111_1101;
\t$display("x = %0d (should be 3)",x);
\t$display("y = %0d (should be -3)",y);
\tx = y;
\t$display("x = %0d (should be 253)",x);
end
endmodule
|
module main;
reg [7:0] a;
reg [2:0] adr, w_adr;
reg\t rst, clk, ae, wr;
(* ivl_synthesis_on *)
always @(posedge clk)
if (rst) begin
\ta <= 8\'b00000000;
\tadr <= 3\'b000;
end else if (ae) begin
\tadr <= w_adr;
end else if (wr) begin
\tadr <= adr + 1;
\ta[adr] <= 1;
end
(* ivl_synthesis_off *)
initial begin
clk = 0;
wr = 0;
ae = 0;
rst = 1;
#1 clk = 1;
#1 clk = 0;
if (a !== 8\'b0000_0000 || adr !== 3\'b000) begin
\t $display("FAILED - reset - a=%b, adr=%b", a, adr);
\t $finish;
end
rst = 0;
#1 clk = 1;
#1 clk = 0;
if (a !== 8\'b0000_0000 || adr !== 3\'b000) begin
\t $display("FAILED - pause - a=%b, adr=%b", a, adr);
\t $finish;
end
wr = 1;
#1 clk = 1;
#1 clk = 0;
if (a !== 8\'b0000_0001 || adr !== 3\'b001) begin
\t $display("FAILED - wr 1 - a=%b, adr=%b", a, adr);
\t $finish;
end
#1 clk = 1;
#1 clk = 0;
if (a !== 8\'b0000_0011 || adr !== 3\'b010) begin
\t $display("FAILED - wr 2 - a=%b, adr=%b", a, adr);
\t $finish;
end
ae = 1;
w_adr = 4;
#1 clk = 1;
#1 clk = 0;
if (a !== 8\'b0000_0011 || adr !== 3\'b100) begin
\t $display("FAILED - ae - a=%b, adr=%b", a, adr);
\t $finish;
end
ae = 0;
#1 clk = 1;
#1 clk = 0;
if (a !== 8\'b0001_0011 || adr !== 3\'b101) begin
\t $display("FAILED - ae - a=%b, adr=%b", a, adr);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
module top;
int bound = 2;
int q_vec [$];
int q_vec1 [$:-1];
int q_vec2 [$:\'X];
int q_vec3 [$:bound];
initial begin
$display(q_vec.size(1));
$display(q_vec.pop_front(1));
$display(q_vec.pop_back(1));
q_vec.push_front(1, 2);
q_vec.push_back(1, 2);
$display("FAILED");
end
endmodule : top
|
// Test system function calls in constant functions
module constfunc6();
function [7:0] clog2(input [7:0] a);
clog2 = $clog2(a);
endfunction
function real log10(input [7:0] a);
log10 = $log10(a);
endfunction
function real sqrt(input real a);
sqrt = $sqrt(a);
endfunction
function real pow_i(input [7:0] a, input [7:0] b);
pow_i = $pow(a, b);
endfunction
function real pow_r(input real a, input real b);
pow_r = $pow(a, b);
endfunction
localparam [7:0] clog2Result = clog2(25);
localparam real log10Result = log10(100);
localparam real sqrtResult = sqrt(25.0);
localparam [7:0] powIResult = pow_i(4, 3);
localparam real powRResult = pow_r(4.0, 3.0);
reg failed;
initial begin
failed = 0;
$display("%0d", clog2Result);
$display("%0g", log10Result);
$display("%0g", sqrtResult);
$display("%0d", powIResult);
$display("%0g", powRResult);
if (clog2Result !== 8\'d5) failed = 1;
if (log10Result != 2.0) failed = 1;
if ( sqrtResult != 5.0) failed = 1;
if ( powIResult !== 8\'d64) failed = 1;
if ( powRResult != 64.0) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module test();
function integer pre_inc(input integer x);
begin
++x;
pre_inc = x;
end
endfunction
function integer pre_dec(input integer x);
begin
--x;
pre_dec = x;
end
endfunction
function integer post_inc(input integer x);
begin
x++;
post_inc = x;
end
endfunction
function integer post_dec(input integer x);
begin
x--;
post_dec = x;
end
endfunction
localparam pre_inc_5 = pre_inc(5);
localparam pre_dec_5 = pre_dec(5);
localparam post_inc_5 = post_inc(5);
localparam post_dec_5 = post_dec(5);
function integer add2(input integer x);
begin
x += 2;
add2 = x;
end
endfunction
function integer sub2(input integer x);
begin
x -= 2;
sub2 = x;
end
endfunction
function integer mul2(input integer x);
begin
x *= 2;
mul2 = x;
end
endfunction
function integer div2(input integer x);
begin
x /= 2;
div2 = x;
end
endfunction
function integer mod2(input integer x);
begin
x %= 2;
mod2 = x;
end
endfunction
function [3:0] and6(input [3:0] x);
begin
x &= 4\'h6;
and6 = x;
end
endfunction
function [3:0] or6(input [3:0] x);
begin
x |= 4\'h6;
or6 = x;
end
endfunction
function [3:0] xor6(input [3:0] x);
begin
x ^= 4\'h6;
xor6 = x;
end
endfunction
function integer lsl2(input integer x);
begin
x <<= 2;
lsl2 = x;
end
endfunction
function integer lsr2(input integer x);
begin
x >>= 2;
lsr2 = x;
end
endfunction
function integer asl2(input integer x);
begin
x <<<= 2;
asl2 = x;
end
endfunction
function integer asr2(input integer x);
begin
x >>>= 2;
asr2 = x;
end
endfunction
localparam add2_5 = add2(5);
localparam sub2_5 = sub2(5);
localparam mul2_5 = mul2(5);
localparam div2_5 = div2(5);
localparam mod2_5 = mod2(5);
localparam and6_f = and6(4\'hf);
localparam or6_0 = or6(4\'h0);
localparam xor6_f = xor6(4\'hf);
localparam lsl2_p25 = lsl2( 25);
localparam lsr2_m25 = lsr2(-25);
localparam asl2_m25 = asl2(-25);
localparam asr2_m25 = asr2(-25);
function integer add3(input integer x);
begin
add3 = x;
add3 += 3;
end
endfunction
function integer sub3(input integer x);
begin
sub3 = x;
sub3 -= 3;
end
endfunction
function integer mul3(input integer x);
begin
mul3 = x;
mul3 *= 3;
end
endfunction
function integer div3(input integer x);
begin
div3 = x;
div3 /= 3;
end
endfunction
function integer mod3(input integer x);
begin
mod3 = x;
mod3 %= 3;
end
endfunction
function [3:0] and9(input [3:0] x);
begin
and9 = x;
and9 &= 4\'h9;
end
endfunction
function [3:0] or9(input [3:0] x);
begin
or9 = x;
or9 |= 4\'h9;
end
endfunction
function [3:0] xor9(input [3:0] x);
begin
xor9 = x;
xor9 ^= 4\'h9;
end
endfunction
function integer lsl3(input integer x);
begin
lsl3 = x;
lsl3 <<= 3;
end
endfunction
function integer lsr3(input integer x);
begin
lsr3 = x;
lsr3 >>= 3;
end
endfunction
function integer asl3(input integer x);
begin
asl3 = x;
asl3 <<<= 3;
end
endfunction
function integer asr3(input integer x);
begin
asr3 = x;
asr3 >>>= 3;
end
endfunction
localparam add3_5 = add3(5);
localparam sub3_5 = sub3(5);
localparam mul3_5 = mul3(5);
localparam div3_5 = div3(5);
localparam mod3_5 = mod3(5);
localparam and9_f = and9(4\'hf);
localparam or9_0 = or9(4\'h0);
localparam xor9_f = xor9(4\'hf);
localparam lsl3_p25 = lsl3( 25);
localparam lsr3_m25 = lsr3(-25);
localparam asl3_m25 = asl3(-25);
localparam asr3_m25 = asr3(-25);
reg failed = 0;
initial begin
$display("pre_inc_5 = %0d", pre_inc_5);
if (pre_inc_5 !== pre_inc(5)) failed = 1;
if (pre_inc_5 !== 6) failed = 1;
$display("pre_dec_5 = %0d", pre_dec_5);
if (pre_dec_5 !== pre_dec(5)) failed = 1;
if (pre_dec_5 !== 4) failed = 1;
$display("post_inc_5 = %0d", post_inc_5);
if (post_inc_5 !== post_inc(5)) failed = 1;
if (post_inc_5 !== 6) failed = 1;
$display("post_dec_5 = %0d", post_dec_5);
if (post_dec_5 !== post_dec(5)) failed = 1;
if (post_dec_5 !== 4) failed = 1;
$display("add2_5 = %0d", add2_5);
if (add2_5 !== add2(5)) failed = 1;
if (add2_5 !== 7) failed = 1;
$display("sub2_5 = %0d", sub2_5);
if (sub2_5 !== sub2(5)) failed = 1;
if (sub2_5 !== 3) failed = 1;
$display("mul2_5 = %0d", mul2_5);
if (mul2_5 !== mul2(5)) failed = 1;
if (mul2_5 !== 10) failed = 1;
$display("div2_5 = %0d", div2_5);
if (div2_5 !== div2(5)) failed = 1;
if (div2_5 !== 2) failed = 1;
$display("mod2_5 = %0d", mod2_5);
if (mod2_5 !== mod2(5)) failed = 1;
if (mod2_5 !== 1) failed = 1;
$display("and6_f = %h", and6_f);
if (and6_f !== and6(4\'hf)) failed = 1;
if (and6_f !== 4\'h6) failed = 1;
$display("or6_0 = %h", or6_0);
if (or6_0 !== or6(4\'h0)) failed = 1;
if (or6_0 !== 4\'h6) failed = 1;
$display("xor6_f = %h", xor6_f);
if (xor6_f !== xor6(4\'hf)) failed = 1;
if (xor6_f !== 4\'h9) failed = 1;
$display("lsl2_p25 = %0d", lsl2_p25);
if (lsl2_p25 !== lsl2( 25)) failed = 1;
if (lsl2_p25 !== 100) failed = 1;
$display("lsr2_m25 = %0h", lsr2_m25);
if (lsr2_m25 !== lsr2(-25)) failed = 1;
if (lsr2_m25 !== 32\'h3ffffff9) failed = 1;
$display("asl2_m25 = %0d", asl2_m25);
if (asl2_m25 !== asl2(-25)) failed = 1;
if (asl2_m25 !== -100) failed = 1;
$display("asr2_m25 = %0d", asr2_m25);
if (asr2_m25 !== asr2(-25)) failed = 1;
if (asr2_m25 !== -7) failed = 1;
$display("add3_5 = %0d", add3_5);
if (add3_5 !== add3(5)) failed = 1;
if (add3_5 !== 8) failed = 1;
$display("sub3_5 = %0d", sub3_5);
if (sub3_5 !== sub3(5)) failed = 1;
if (sub3_5 !== 2) failed = 1;
$display("mul3_5 = %0d", mul3_5);
if (mul3_5 !== mul3(5)) failed = 1;
if (mul3_5 !== 15) failed = 1;
$display("div3_5 = %0d", div3_5);
if (div3_5 !== div3(5)) failed = 1;
if (div3_5 !== 1) failed = 1;
$display("mod3_5 = %0d", mod3_5);
if (mod3_5 !== mod3(5)) failed = 1;
if (mod3_5 !== 2) failed = 1;
$display("and9_f = %h", and9_f);
if (and9_f !== and9(4\'hf)) failed = 1;
if (and9_f !== 4\'h9) failed = 1;
$display("or9_0 = %h", or9_0);
if (or9_0 !== or9(4\'h0)) failed = 1;
if (or9_0 !== 4\'h9) failed = 1;
$display("xor9_f = %h", xor9_f);
if (xor9_f !== xor9(4\'hf)) failed = 1;
if (xor9_f !== 4\'h6) failed = 1;
$display("lsl3_p25 = %0d", lsl3_p25);
if (lsl3_p25 !== lsl3( 25)) failed = 1;
if (lsl3_p25 !== 200) failed = 1;
$display("lsr3_m25 = %0h", lsr3_m25);
if (lsr3_m25 !== lsr3(-25)) failed = 1;
if (lsr3_m25 !== 32\'h1ffffffc) failed = 1;
$display("asl3_m25 = %0d", asl3_m25);
if (asl3_m25 !== asl3(-25)) failed = 1;
if (asl3_m25 !== -200) failed = 1;
$display("asr3_m25 = %0d", asr3_m25);
if (asr3_m25 !== asr3(-25)) failed = 1;
if (asr3_m25 !== -4) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
`timescale 1 ms / 1 ps
module test;
initial begin
\t#12345.6789;
\t$display("time = %0f", $realtime);
\t$test(test);
\t#2345.67891;
\t$display("time = %0f", $realtime);
\t$test(test);
end
endmodule
`timescale 1 ps / 1 ps
module test2;
initial begin
\t#12345.6789;
\t$display("time = %0f", $realtime);
\t$test(test2);
\t#2345.67891;
\t$display("time = %0f", $realtime);
\t$test(test2);
end
endmodule
|
module test();
function integer accumulate1(input integer value);
static int acc = 1;
acc = acc + value;
return acc;
endfunction
function automatic integer accumulate2(input integer value);
int acc = 1;
acc = acc + value;
return acc;
endfunction
localparam value1 = accumulate1(2);
localparam value2 = accumulate1(3);
localparam value3 = accumulate2(2);
localparam value4 = accumulate2(3);
integer value;
reg failed = 0;
initial begin
$display("%d", value1);
if (value1 !== 3) failed = 1;
$display("%d", value2);
if (value2 !== 4) failed = 1;
$display("%d", value3);
if (value3 !== 3) failed = 1;
$display("%d", value4);
if (value4 !== 4) failed = 1;
value = accumulate1(2);
$display("%d", value);
if (value !== 3) failed = 1;
value = accumulate1(3);
$display("%d", value);
if (value !== 6) failed = 1;
value = accumulate2(2);
$display("%d", value);
if (value !== 3) failed = 1;
value = accumulate2(3);
$display("%d", value);
if (value !== 4) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module p #(parameter a = 1, b = 2) ();
typedef logic [b:a] vector_t;
vector_t v;
initial begin
v = ~0;
#b $display("%m %0d %0d %b", a, b, v);
end
endmodule
module m;
p #(1,2) p1();
p #(1,4) p2();
endmodule
|
// Regression test for br962 - based on test case provided in bug report
module qtest;
parameter width = 32;
parameter depth = 32;
reg [width-1:0] values[$];
reg [$clog2(depth)+width-1:0] sum1;
reg [$clog2(depth)+width-1:0] sum2;
task new_sample;
input [width-1:0] data;
int i;
begin
reg [width-1:0] popped;
if (values.size >= depth)
\tbegin : foo
\t popped = values.pop_back();
\t sum1 = sum1 - popped;
\tend
sum1 = sum1 + data;
values.push_front(data);
sum2 = 0;
for (i = 0; i < values.size; i++) begin
sum2 = sum2 + values[i];
end
$display("sum1 = %d sum2 = %d", sum1, sum2);
if (sum1 !== sum2) begin
$display("FAILED");
$finish;
end
end
endtask
initial begin
sum1 = 0;
repeat (2*depth) new_sample({$random});
$display("PASSED");
end
endmodule
|
module main;
wire struct packed {
logic m1;
logic [7:0] m8;
} foo;
assign foo = {1\'b1, 8\'ha5};
struct packed {
logic [3:0] m4;
logic [7:0] m8;
} bar;
initial begin
#1 /* wait for logic to settle. */;
bar.m8 <= foo.m8[7:0];
bar.m4 <= foo.m8[7:4];
#1 $display("bar8=%h, bar4=%h", bar.m8, bar.m4);
if (bar.m8 !== 8\'ha5) begin
\t $display("FAILED");
\t $finish;
end
if (bar.m4 !== 4\'ha) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
module top_module(
input wire [2:0] N,
input wire [7:0] In,
output reg [7:0] Out
);
wire [7:0] Array[7:0];
assign Array[N][0] = In[0];
assign Array[0][7:1] = In[7:1];
initial begin
Out[0] = Array[0][0];
Out[7:1] = Array[0][7:N];
end
endmodule
|
// Regression test for GitHub issue #28 : Insufficient string escaping
// when writing vvp script.
module tb;
wire [63:0] y;
\\test_str="hello" uut (y);
initial begin
#1 $display("%s", y);
if (y === "hello")
$display("PASSED");
else
$display("FAILED");
end
endmodule
module \\test_str="hello" (output [63:0] \\port="y" );
assign \\port="y" = "hello";
endmodule
|
module top;
parameter in = "First Second Third 15";
reg pass;
integer res, arg4;
reg [32*8:1] arg1, arg2, arg3;
initial begin
pass = 1\'b1;
res = $sscanf(in, "%s%s%s%d", arg1, arg2, arg3, arg4);
if (res != 4) begin
$display("FAILED: wrong number of arguments, expected 4, got %0d", res);
pass = 1\'b0;
end
if (arg1[5*8:1] !== "First") begin
$display("FAILED: arg1, expected \\"First\\", got \\"%0s\\"", arg1);
pass = 1\'b0;
end
if (arg2[6*8:1] !== "Second") begin
$display("FAILED: arg2, expected \\"Second\\", got \\"%0s\\"", arg2);
pass = 1\'b0;
end
if (arg3[5*8:1] !== "Third") begin
$display("FAILED: arg3, expected \\"Third\\", got \\"%0s\\"", arg3);
pass = 1\'b0;
end
if (arg4 != 15) begin
$display("FAILED: arg4, expected 15, got %0d", arg4);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* The assignment to the input of a task port should pad with
* zeros. It seems that certain Verilog bugs can cause this test to
* fail.
*/
module test;
task writeInto;
input [31:0] x;
begin
\t $display("x=%h", x);
\t if (x[31:10] !== 22\'d0) begin
\t $display("FAILED -- x is %b", x);
\t $finish;
\t end
end
endtask
reg [7:0] y;
reg [31:0] y1;
initial begin
y1 = 512;
y = 4;
writeInto(y1);
writeInto(y);
$display("PASSED");
end
endmodule
|
//
// Copyright (c) 2000 Stephen Williams ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// Check support for event lists with named events.
//
module main ();
reg flag1, flag2, flag12;
event event_1, event_2;
always @ event_1 flag1 = ~flag1;
always @ event_2 flag2 = ~flag2;
always @(event_1 or event_2) flag12 = ~flag12;
initial begin
flag1 = 0;
flag2 = 0;
flag12 = 0;
#1 -> event_1;
#1
\tif (flag1 !== 1) begin
\t $display("FAILED -- event_1 didn\'t trigger flag1");
\t $finish;
\tend
if (flag2 !== 0) begin
\t $display("FAILED -- event_1 DID trigger flag2");
\t $finish;
\tend
if (flag12 !== 1) begin
\t $display("FAILED -- event_1 didn\'t trigger flag12");
\t $finish;
\tend
flag1 = 0;
flag2 = 0;
flag12 = 0;
#1 -> event_2;
#1
\tif (flag1 !== 0) begin
\t $display("FAILED -- event_2 DID trigger flag1");
\t $finish;
\tend
if (flag2 !== 1) begin
\t $display("FAILED -- event_2 didn\'t trigger flag2");
\t $finish;
\tend
if (flag12 !== 1) begin
\t $display("FAILED -- event_1 didn\'t trigger flag12");
\t $finish;
\tend
$display("PASSED");
end
endmodule
|
// This slightly convoluted module used to cause an argument-size
// mismatch in the call to the function extend_data
module test (c);
parameter MAX_SIZE = 32;
input\t\t\tc;
reg\t[MAX_SIZE-1:0]\td,
\t\t\te,
\t\t\tf;
reg\t[7:0]\t\tg;
wire\t\t\th;
always @(posedge h or negedge c)
if (~c)
f <= #2 {MAX_SIZE{1'b0}};
else
case (g)
8'h18 :
f <= #2 hw(d, e);
default :
f <= #2 {MAX_SIZE{1'b0}};
endcase
parameter FALSE_RESULT = {MAX_SIZE{1'b0}},
\t TRUE_RESULT = FALSE_RESULT | 1'b1;
function integer sign_of;
input\t[2*MAX_SIZE-1:0]\tdata;
input\t\t\t\tsize;
reg\t[2*MAX_SIZE-1:0]\tdata;
integer\t\t\tsize;
if (data[size-1]===1'b1)
sign_of = -1;
else
sign_of = 1;
endfunction
function [2*MAX_SIZE-1:0] extend_data;
input\t[2*MAX_SIZE-1:0]\tdata;
input\t\t\t\tsize;
input\t\t\t\tnew_size;
input\t\t\t\textend;
reg\t[2*MAX_SIZE-1:0]\tdata;
integer\t\t\tsize,
\t\t\t\tnew_size;
reg\t\t\t\textend;
for (extend_data = data ; new_size-size>0 ; new_size=new_size-1)
extend_data[new_size-1] = extend & data[size-1];
endfunction
function [MAX_SIZE-1:0] hw;
input\t[MAX_SIZE-1:0]\t\ta;
input\t[MAX_SIZE-1:0]\t\tb;
reg\t[MAX_SIZE-1:0]\t\ta,
\t\t\t\tb;
reg\t[MAX_SIZE:0]\t\tdiff;
begin
diff = extend_data(b, MAX_SIZE, MAX_SIZE+1, 1'b1) -
extend_data(a, MAX_SIZE, MAX_SIZE+1, 1'b1);
if (sign_of(diff, MAX_SIZE+1)==-1)
hw = TRUE_RESULT;
else
hw = FALSE_RESULT;
end
endfunction
endmodule
|
// Check that it is possible to explicitly call the base class constructor, even
// if it does not take any parameters. Check that it is possible to call it
// without parenthesis after the `new`.
module test;
class B;
function new();
$display("PASSED");
endfunction
endclass
class C extends B;
function new();
super.new;
endfunction
endclass
C c = new;
endmodule
|
module main;
reg clk;
reg mem[1:0];
reg clr;
(* ivl_synthesis_on *)
always @(posedge clk)
if (clr) begin
\tmem[1] <= 1;
\tmem[0] <= 0;
end else begin
\tmem[1] <= ~mem[1];
\tmem[0] <= ~mem[0];
end
(* ivl_synthesis_off *)
initial begin
clk = 0;
clr = 1;
#1 clk = 1;
#1 clk = 0;
if (mem[0] !== 0 || mem[1] !== 1) begin
\t $display("FAILED -- clr");
\t $finish;
end
clr = 0;
#1 clk = 1;
#1 clk = 0;
if (mem[0] !== 1 || mem[1] !== 0) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
module test;
reg fail = 0;
reg [3:0] bus = 4\'b0;
initial begin
if (bus !== 4\'b0) begin
$display("FAILED: initial value, got %b, expected 0000.", bus);
fail = 1;
end
#1 force bus[0] = 1;
bus[0] = 1\'bz;
if (bus !== 4\'b0001) begin
$display("FAILED: force of bus[0], got %b, expected 0001.", bus);
fail = 1;
end
#1 force bus[3:2] = 2\'b11;
if (bus !== 4\'b1101) begin
$display("FAILED: force of bus[3:2], got %b, expected 1101.", bus);
fail = 1;
end
#1 release bus[0];
bus = 4\'b000z;
#0;
if (bus !== 4\'b110z) begin
$display("FAILED: release of bus[0], got %b, expected 110z.", bus);
fail = 1;
end
#1 release bus[3:2];
bus[3] = 1\'b0;
if (bus !== 4\'b010z) begin
$display("FAILED: release of bus[3:2], got %b, expected 010z.", bus);
fail = 1;
end
if (!fail) $display("PASSED");
end
endmodule
|
module top;
reg [1:0] in;
subm sm [1:0](in);
initial begin
// This should trigger instance 0.
in[0] = 0;
#1 in[0] = 1;
// This should trigger instance 1.
in[1] = 0;
#1 in[1] = 1;
end
endmodule
module subm(input wire in);
always @(posedge in) $display("In %m at %0t", $time);
endmodule
|
/*
* integer3gt - a verilog test for integer greater-than conditional >
*
* Copyright (C) 1999 Stephen G. Tell
* Portions inspired by qmark.v by Steven Wilson ([email protected])
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this software; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
* Boston, MA 02111-1307 USA
*/
module integer3gt;
integer a;
integer b;
reg\t error;
initial begin
error = 0;
a = 1;
if(a > 2) begin
\t $display("FAILED 1 > 2");
\t error = 1;
end // if (a < 2)
a = 2;
if(a > 2) begin
\t $display("FAILED 2 > 2");
\t error = 1;
end
a = 3;
if(a > 2) begin
\t b = 1;
end else begin
\t $display("FAILED 3 > 2");
\t error = 1;
end
b = 0;
for(a = 10; a > 5; a = a - 1) begin
\t b = b + a;
end
if(b != 40) begin
\t $display("FAILED forloop b=%d expected 40", b);
\t error = 1;
end
if(error == 0)
\t $display("PASSED");
$finish;
end // initial begin
endmodule
|
/*
* Copyright (c) 1998-2000 Andrei Purdea ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// This test checks that returning from a void function works correctly.
module main;
int res = 123;
function void bla();
int i;
for (i=0;i<10;i=i+1) begin
res = i;
$display("loop %d", i);
if (i == 5)
begin
return;
end
end
endfunction
initial begin
bla();
if (res == 5) begin
$display("PASS");
end else begin
$display("FAIL");
end
end
endmodule
|
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
/*
* Copyright (c) 2001 Stephan Boettcher <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: memidxrng.v,v 1.1 2001/09/29 05:03:41 sib4 Exp $
// $Log: memidxrng.v,v $
// Revision 1.1 2001/09/29 05:03:41 sib4
// add memidxrng.v: memory address range check
//
module memidxrng;
reg mem[12:2];
reg [7:0] i;
integer errs = 0;
initial
begin
\tfor (i=0; i<255; i=i+1) mem[i] <= ^i;
\t#1;
\tfor (i=0; i<17; i=i+1)
\t $display("mem[%d] = %b \\%b", i, mem[i], ^i);
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
\tif (mem[13] !== 1\'bx)
\t begin
\t $display("FAILED: mem[13] = %b, expect x", mem[14]);
\t errs = errs + 1;
\t end
\tif (mem[1] !== 1\'bx)
\t begin
\t $display("FAILED: mem[1] = %b, expect x", mem[1]);
\t errs = errs + 1;
\t end
`endif
\tif (errs===0)
\t $display("PASSED");
\t$finish;
end
endmodule
|
/*
* Copyright (c) 1999-2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This is derived from pr602.
*/
module main;
reg [1:0] a [3:0], x;
integer i;
initial begin
a[0] = 0;
a[1] = 1;
a[2] = 2;
a[3] = 3;
// The index expressions of this parameter expression
// should be evaluated to constants.
$display("a[(1-1)+0] = %b", a[(1-1)+0]);
$display("a[(2-1)+0] = %b", a[(2-1)+0]);
x = a[(1-1)+0];
if (x !== 2\'b00) begin
\t $display("FAILED -- x == %b", x);
\t $finish;
end
x = a[(2-1)+0];
if (x !== 2\'b01) begin
\t $display("FAILED -- x == %b", x);
\t $finish;
end
x <= a[(1-1)+0];
#1 if (x !== 2\'b00) begin
\t $display("FAILED -- x == %b", x);
\t $finish;
end
x <= a[(2-1)+0];
#1 if (x !== 2\'b01) begin
\t $display("FAILED -- x == %b", x);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
/*
* Copyright (c) 2003 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
* $Id: onehot16_tb.v,v 1.1 2003/03/31 01:35:05 stevewilliams Exp $
*/
/*
* Exhaustive check of all the subtract results.
*/
module main;
wire [15:0] out;
reg [3:0] A;
onehot16 dut(.out(out), .A(A));
reg\t error = 0;
integer adx;
initial begin
A = 0;
for (adx = 0 ; adx < 16 ; adx = adx + 1) begin
\t A = adx;
\t #1 $write("onehot(%b): %b", A, out);
\t if (out !== (1 << adx)) begin
\t $display(" ERROR");
\t error = 1;
\t end else begin
\t $display(" OK");
\t end
end // for (adx = 0 ; adx < 256 ; adx = adx + 1)
if (error == 0)
\t$display("PASSED");
else
\t$display("FAILED");
end // initial begin
endmodule // main
|
// Check that it is possible to declare parameters and localparams inside a
// class. Both declared parameters that can not be overridden.
module test;
class C;
// `parameter` is also declaring a local parameter inside a class
parameter A = 1;
localparam B = 2;
function bit test();
return A == 1 && B == 2;
endfunction
endclass
initial begin
C c;
c = new;
if (c.test() && c.A == 1 && c.B == 2) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - always force net_lvalue = boolean_expr ;
// D: No dependancy
module main ;
wire [3:0] value1 ;
initial
begin
#15;
if(value1 != 4\'h5)
$display("FAILED - 3.1.3G always force net_lvalue = boolean_expr;\
");
else
\tbegin
$display("PASSED\
");
\t $finish;
end
end
always force value1 = 1\'b1 && 1\'b1;
endmodule
|
`timescale 1ns/1ns
module top;
reg itrig = 1'b0;
wire [31:0] tm, stm;
assign tm = itrig * $time;
assign stm = itrig * $stime;
initial begin
$monitor(tm,, stm);
#1 itrig = 1'b1;
#1 itrig = 1'b0;
#1 itrig = 1'b1;
#1 itrig = 1'b0;
end
endmodule
|
package pkg;
typedef enum logic [3:0] {
ABC = 4\'h1
} enum_t;
typedef struct packed {
enum_t item;
} w_enum;
typedef struct packed {
logic [3:0] item;
} w_logic;
typedef union packed {
w_enum el1;
w_logic el2;
} foo_t;
endpackage
module main();
import pkg::*;
foo_t val;
initial begin
val.el1.item = ABC;
if (val.el2.item === 4\'h1)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate unary or |(value)
//
module main;
reg [3:0] vect;
reg\terror;
wire\tresult;
assign result = ^(vect);
initial
begin
error = 0;
for(vect=4\'b0001;vect<4\'b0000;vect = vect << 1)
begin
#1;
if(result !== 1\'b1)
begin
$display("FAILED - Unary xor ^(%b)=%b",vect,result);
error = 1\'b1;
end
end
#1;
for(vect=4\'b0011;vect<4\'b0000;vect = vect << 1)
begin
#1;
if(result !== 1\'b0)
begin
$display("FAILED - Unary xor ^(%b)=%b",vect,result);
error = 1\'b1;
end
end
#1;
vect = 4\'b0000;
#1;
if(result !== 1\'b0)
begin
$display("FAILED - Unary xor ^(%b)=%b",vect,result);
error = 1\'b1;
end
if(error === 0 )
$display("PASSED");
end
endmodule // main
|
module top;
time ioffset, ifuture;
realtime offset, future;
initial begin
offset = 1.0;
ioffset = 1;
future = 20.0;
ifuture = 120;
#1;
$display("----- Using real times -----");
$display("The time one unit ago was : %t", $realtime - 1.0);
$display("The time one unit ago was : %t", $realtime - offset);
$display("The time now is : %t", $realtime);
$display("One time unit from now it will be: %t", $realtime + 1.0);
$display("The time at 20 will be : %t", future);
$display("The time at 40 will be : %t", 40.0);
#100;
$display("\
----- Using integer times -----");
$display("The time one unit ago was : %t", $time - 1);
$display("The time one unit ago was : %t", $time - ioffset);
$display("The time now is : %t", $time);
$display("One time unit from now it will be: %t", $time + 1);
$display("The time at 120 will be : %t", ifuture);
$display("The time at 140 will be : %t", 140);
end
endmodule
|
module test;
reg pass;
reg [8*40:1] str;
reg [15:0] v;
initial begin
pass = 1\'b1;
v = 2;
$sformat(str, "%0d", (v + 2 - 1) * 1);
if (str[8*1:1] !== "3" || str[8*40:8*1+1] !== 0) begin
$display("FAILED 1st test, expected \\"3\\", got %s", str);
pass = 1\'b0;
end
$sformat(str, "%0d", \'d1 - \'d2 + v);
if (str[8*1:1] !== "1" || str[8*40:8*1+1] !== 0) begin
$display("FAILED 2nd test, expected \\"1\\", got %s", str);
pass = 1\'b0;
end
$sformat(str, "%0d", v + (-1));
if (str[8*1:1] !== "1" || str[8*40:8*1+1] !== 0) begin
$display("FAILED 3rd test, expected \\"1\\", got %s", str);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
module test();
reg [1:0] src;
reg [2:0] dst;
initial begin
assign dst = src;
src = 2\'b01;
#1 $display("%b", dst);
if (dst === 3\'b001)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
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