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2.1M
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module top();
localparam signed [31:0] SizedValue = -1;
localparam UnsizedValue = -1;
reg [35:0] Result;
reg Failed;
initial begin
Failed = 0;
// check for sign extension
Result = SizedValue;
$display("%h", Result);
if (Result !== 36\'hfffffffff) Failed = 1;
Result = UnsizedValue;
$display("%h", Result);
if (Result !== 36\'hfffffffff) Failed = 1;
// check for zero extension
Result = \'d0 + SizedValue;
$display("%h", Result);
if (Result !== 36\'h0ffffffff) Failed = 1;
Result = \'d0 + UnsizedValue;
$display("%h", Result);
`ifdef OLD_UNSIZED
if (Result !== 36\'hfffffffff) Failed = 1;
`else
if (Result !== 36\'h0ffffffff) Failed = 1;
`endif
if (Failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module top;
initial begin: b_label
$display("FAILED");
end: b_label_f
initial fork:fj_label
join:fj_label_f
initial fork:fja_label
join_any:fja_label_f
initial fork:fjn_label
join_none:fjn_label_f
task t_label;
endtask: t_label_f
task twa_label(input arg);
endtask: twa_label_f
function fn_label;
input arg;
endfunction: fn_label_f
function fa_label(input in);
endfunction: fa_label_f
endmodule:top_f
macromodule extra;
parameter add_inv = 1;
reg a;
wire y, yb;
pbuf dut(y, a);
if (add_inv) begin: g_label
pinv dut2(yb, y);
end: g_label_f
endmodule: extra_f
package pkg;
endpackage: pkg_f
program pgm;
class foo;
endclass: foo_f
endprogram: pgm_f
primitive pbuf (out, in);
output out;
input in;
table
0 : 0;
1 : 1;
endtable
endprimitive: pbuf
primitive pinv (output out, input in);
table
0 : 1;
1 : 0;
endtable
endprimitive: pinv_f
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This is a check of the implementation of division and multiplication
* within more complex expressions.
*/
module test;
task mod;
input [31:0] a;
input [15:0] b;
output [31:0] out;
begin
\t out = a-(a/b)*b;
end
endtask
reg [31:0] result,c, nl;
initial begin
c = 13; nl = 3;
mod(c, nl, result);
$display("13 %% 3 = %d", result);
if (result !== 32\'h00_00_00_01) begin
\t $display("FAILED -- result is %b", result);
\t $finish;
end
$display("PASSED");
end
endmodule
|
// This module generate M single 2*HW-1 bit vector each T time steps
module stimulus #(parameter W = 8, M = 200, MAX = 256) (
input bit clk, reset,
output reg [W-1:0] x
);
int i;
initial begin
@(negedge reset);
for (i = 0; i < M; i=i+1) begin
@(negedge clk);
x = {$random} % MAX;
end
end
endmodule
module test;
parameter M = 200; // number of test vectors
parameter W = 8; // bit width of input vecotrs
parameter T = 10; // for timing
parameter D = 8; // depth of pipeline, MAX of 8
parameter K = 10; // distance between boundaries of pipeline
parameter S = 2*M*T + 12*D;
parameter MAX = D*K;
bit clk =0, reset = 0;
wire [W-1:0] xin;
wire [W-1:0] din = K;
wire [W-1:0] dout, bout, xout;
wire [2:0] lin = 3\'b111; // -1 in fact
wire [2:0] lout;
int x_gold; // for computing expected result
initial forever #T clk = ~clk;
stimulus #(W, M, MAX) stim (.clk(clk), .reset(reset), .x(xin));
diq_array #(W, D) duv (.clk(clk), .reset(reset),
.din(din), .bin(8\'d0), .xin(xin), .lin(lin),
.dout(dout), .bout(bout), .xout(xout),
.lout(lout) );
initial begin: checking
@(negedge reset);
@(posedge clk);
repeat (D) @(negedge clk);
forever begin
@(posedge clk);
#1;
// checking dout
if (dout !== din) begin
$display("ERROR");
$finish;
end
// checking bout
if (bout !== MAX) begin
$display("ERROR");
$finish;
end
// checking lout
x_gold = xout-1; // dirty fix, for example xin = 30 muste be reported as 2
if (lout !== x_gold/K) begin
$display("ERROR");
$finish;
end
end
end
initial begin
doreset();
#S;
$display("PASSED");
$finish;
end
task doreset;
begin
\t@(negedge clk);
\treset = 1;
\trepeat (5) @(negedge clk);
\treset = 0;
end
endtask
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Basic ifdef test with define
//
`define NOCODE
module ifdef2;
reg error ;
`ifdef NOCODE
initial
begin
#20;
error = 0;
#20;
end
`endif
initial
begin
#1;
error = 1;
#40;
if(error == 0)
$display("PASSED");
else
$display("FAILED");
end
endmodule // main
|
// Check that queues with compatible packed base types can be assigned to each
// other. Even if the element types are not identical.
module test;
typedef bit [31:0] T1;
typedef bit [31:0] T2[$];
// For two packed types to be compatible they need to have the same packed
// width, both be 2-state or 4-state and both be either signed or unsigned.
bit [32:1] q1[$];
bit [7:0][3:0] q2[$];
int unsigned q3[$];
T1 q4[$];
T2 q5;
initial begin
q2 = q1;
q3 = q2;
q4 = q3;
q5 = q4;
q1 = q5;
$display("PASSED");
end
endmodule
|
module check (input unsigned [22:0] a, b, c);
wire unsigned [22:0] int_AB;
assign int_AB = a - b;
always @(a, b, int_AB, c) begin
#1;
if (int_AB !== c) begin
$display("ERROR");
$finish;
end
end
endmodule
module stimulus (output reg unsigned [22:0] A, B);
parameter MAX = 1 << 23;
parameter S = 10000;
int unsigned i;
initial begin
A = 0; B= 0;
for (i=0; i<S; i=i+1) begin
#1 A = {$random} % MAX;
B = {$random} % MAX;
end
#1 A = 0;
B = 0;
#1 A = 23\'h7fffff;
#1 B = 23\'h7fffff;
#1 B = 0;
// x and z injected on A
for (i=0; i<S/2; i=i+1) begin
#1 A = {$random} % MAX;
A = xz_inject (A);
end
// x and z injected on B
#1 A = 1;
for (i=0; i<S/2; i=i+1) begin
#1 B = {$random} % MAX;
B = xz_inject (B);
end
// x and z injected on A, B
for (i=0; i<S; i=i+1) begin
#1 A = {$random} % MAX;
B = {$random} % MAX;
A = xz_inject (A);
B = xz_inject (B);
end
end
// injects some x, z values on 23 bits arguments
function [22:0] xz_inject (input unsigned [22:0] value);
integer i, temp;
begin
temp = {$random};
for (i=0; i<23; i=i+1)
begin
if (temp[i] == 1\'b1)
begin
temp = $random;
if (temp <= 0)
value[i] = 1\'bx; // \'x noise
else
value[i] = 1\'bz; // \'z noise
end
end
xz_inject = value;
end
endfunction
endmodule
module test;
wire unsigned [22:0] a, b;
wire unsigned [22:0] r;
stimulus stim (.A(a), .B(b));
usub23 duv (.a_i(a), .b_i(b), .c_o(r) );
check check (.a(a), .b(b), .c(r) );
initial begin
#40000;
$display("PASSED");
$finish;
end
endmodule
|
module main;
typedef struct packed {
logic [3:0] adr;
logic [3:0] val;
} foo_s;
foo_s [1:0][3:0] ival;
foo_s [1:0][3:0] oval;
genvar\t g;
for (g = 0 ; g < 4 ; g = g+1) begin:loop
TEST dut(.in(ival[0][g]),
\t .out(oval[0][g]));
end
initial begin
ival = \'hx3x2x1x0;
#1 $display("ival = %h, oval = %h", ival, oval);
if (oval !== 64\'hzzzzzzzzxcxdxexf) begin
\t $display("FAILED -- oval=%h", oval);
\t $finish;
end
$display("PASSED");
$finish;
end
endmodule // main
module TEST (input wire [7:0] in, output wire [7:0] out);
assign out = ~in;
endmodule // TEST
|
// Copyright 2007, Martin Whitaker.
// This code may be freely copied for any purpose.
module unnamed_generate_block();
localparam up = 1;
wire [2:0] count1;
wire [2:0] count2;
wire [2:0] count3;
generate
if (up)
count_up counter(count1);
else
count_down counter(count1);
endgenerate
generate
if (up)
begin:genblk1
count_up counter(count2);
end
else
begin:genblk1
count_down counter(count2);
end
endgenerate
count_down genblk01(count3);
initial begin:genblk001
reg [2:0] count;
#1 count = 4;
#1 count = 5;
#1 count = 6;
#1 count = 7;
end
always @(genblk0001.counter.count) begin
$display(genblk0001.counter.count);
end
//initial begin
// $dumpfile("dump.vcd");
// $dumpvars;
//end
endmodule
module count_up(output reg [2:0] count);
initial begin
#1 count = 0;
#1 count = 1;
#1 count = 2;
#1 count = 3;
end
endmodule
module count_down(output reg [2:0] count);
initial begin
#1 count = 3;
#1 count = 2;
#1 count = 1;
#1 count = 0;
end
endmodule
|
module top;
reg [79:0] data = 0;
initial begin
data = data + 80\'h12345678901234567890;
if (data !== 80\'h12345678901234567890) $display("FAILED");
else $display("PASSED");
end
endmodule
|
\r
module main;\r
\r
int variable = 0;\r
\r
// A void function returns no value, so can be called\r
// like a task, but without a warning about unused\r
// results.\r
function void test_incr(input int arg);\r
variable = variable + arg;\r
endfunction // test_incr\r
\r
initial begin\r
variable = 0;\r
test_incr(5);\r
if (variable !== 5) begin\r
\t $display("FAILED");\r
\t $finish;\r
end\r
$display("PASSED");\r
end\r
\r
endmodule // main\r
|
module mod #(
parameter A = 1,
localparam B = A + 1,
parameter C = B - 1
) (
input [A-1:0] a,
input [B-1:0] b,
input [C-1:0] c
);
endmodule
module top();
reg [3:0] a = \'ha;
reg [4:0] b = \'hb;
reg [5:0] c = \'hc;
mod #(4, 6) m(a, b, c);
initial begin
$display("%0d %0d %0d", m.A, m.B, m.C);
$display("%0d %0d %0d", $bits(m.a), $bits(m.b), $bits(m.c));
if (m.A === 4 && $bits(m.a) === 4
&& m.B === 5 && $bits(m.b) === 5
&& m.C === 6 && $bits(m.c) === 6)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
module main;
reg clk;
localparam integer TEST = 100;
print #("PASSED", TEST) foo (clk);
initial begin
clk = 0;
#1 clk = 1;
#1 $finish;
end
endmodule // main
module print (input wire clk);
parameter message = "";
parameter number = 0;
always @(posedge clk) begin
if (number !== 100) begin
\t $display("FAILED -- number=%d\
", number);
\t $finish;
end
$display("%s", message);
end
endmodule // print
|
// Copyright (c) 2015 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place / Suite 330, Boston, MA 02111/1307, USA
// Example to test prefix for VTypeArray (and using function as index).
module test_prefix_aray();
logic [1:0] sel_word;
logic [31:0] out_word;
prefix_array dut(sel_word, out_word);
initial begin
sel_word = 2;
#1;
if(out_word !== 32\'d5) begin
$display("FAILED out_word = %d", out_word);
$finish();
end
$display("PASSED");
end
endmodule
|
module automatic_task();
task automatic fill_array;
input [7:0] value;
reg [7:0] array[3:0];
integer i;
fork
begin
#10 array[0] = value;
#10 array[1] = array[0];
#10 array[2] = array[1];
#10 array[3] = array[2];
end
begin
@(array[0]) $display(array[0], array[1], array[2], array[3]);
@(array[1]) $display(array[0], array[1], array[2], array[3]);
@(array[2]) $display(array[0], array[1], array[2], array[3]);
@(array[3]) $display(array[0], array[1], array[2], array[3]);
end
join
endtask
initial #1 fill_array(1);
initial #2 fill_array(2);
endmodule
|
module check (input signed [22:0] a, b, c);
wire signed [22:0] int_AB;
assign int_AB = a - b;
always @(a, b, int_AB, c) begin
#1;
if (int_AB !== c) begin
$display("ERROR");
$finish;
end
end
endmodule
module stimulus (output reg signed [22:0] A, B);
parameter MAX = 1 << 23;
parameter S = 10000;
int unsigned i;
initial begin
A = 0; B= 0;
for (i=0; i<S; i=i+1) begin
#1 A = $random % MAX;
B = $random % MAX;
end
#1 A = 0;
B = 0;
#1 A = 23\'h7fffff;
#1 B = 23\'h7fffff;
#1 B = 0;
// x and z injected on A
for (i=0; i<S/2; i=i+1) begin
#1 A = $random % MAX;
A = xz_inject (A);
end
// x and z injected on B
#1 A = 1;
for (i=0; i<S/2; i=i+1) begin
#1 B = $random % MAX;
B = xz_inject (B);
end
// x and z injected on A, B
for (i=0; i<S; i=i+1) begin
#1 A = $random % MAX;
B = $random % MAX;
A = xz_inject (A);
B = xz_inject (B);
end
end
// injects some x, z values on 23 bits arguments
function [22:0] xz_inject (input signed [22:0] value);
integer i, temp;
begin
temp = {$random};
for (i=0; i<23; i=i+1)
begin
if (temp[i] == 1\'b1)
begin
temp = $random;
if (temp <= 0)
value[i] = 1\'bx; // \'x noise
else
value[i] = 1\'bz; // \'z noise
end
end
xz_inject = value;
end
endfunction
endmodule
module test;
wire signed [22:0] a, b;
wire signed [22:0] r;
stimulus stim (.A(a), .B(b));
ssub23 duv (.a_i(a), .b_i(b), .c_o(r) );
check check (.a(a), .b(b), .c(r) );
initial begin
#40000;
$display("PASSED");
$finish;
end
endmodule
|
module main;
wire qh = 1\'bz;
wire [1:0] Q;
reg [2:0] D;
buft a({qh,Q}, D);
reg\t x;
//assign D[0] = x;
initial begin
D = 3\'bzz0;
#1 $display("Q=%b, D=%b", Q, D);
if (Q !== 2\'bz0) begin
\t $display("FAILED");
\t $finish;
end
D[0] = 1;
#1 $display("Q=%b, D=%b", Q, D);
if (Q !== 2\'bz1) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
end
endmodule // main
module buft(inout [2:0] T, input [2:0] D);
assign T = D;
endmodule // buft
|
// Check that non-blocking event controlled partial writes to a 4-state vector
// are correctly handlded.
module test;
reg failed = 1\'b0;
`define check(val, exp) \\
if (exp !== val) begin \\
$display("FAILED. Got %b, expected %b.", val, exp); \\
failed = 1\'b1; \\
end
reg [3:0] x;
integer i;
event e;
initial begin
// Immediate index
// Within bounds
x = \'hx;
x[2:1] <= @e 2\'b10;
-> e;
`check(x, 4\'bx10x)
// Partially oob at high and low side
x = \'hx;
x[4:-1] <= @e 6\'b101010;
-> e;
`check(x, 4\'b0101)
// Partially oob at low side
x = \'hx;
x[0:-1] <= @e 2\'b10;
-> e;
`check(x, 4\'bxxx1)
// Partially oob at high side
x = \'hx;
x[4:3] <= @e 2\'b01;
-> e;
`check(x, 4\'b1xxx)
// Fully oob at low side
x = \'hx;
x[-1:-2] <= @e 2\'b11;
-> e;
`check(x, 4\'bxxxx)
// Fully oob at high side
x = \'hx;
x[6:5] <= @e 2\'b11;
-> e;
`check(x, 4\'bxxxx)
// Variable index
// Within bounds
i = 1;
x = \'hx;
x[i+:2] <= @e 2\'b10;
-> e;
`check(x, 4\'bx10x)
// Partially oob at high and low side
i = -1;
x = \'hx;
x[i+:6] <= @e 6\'b101010;
-> e;
`check(x, 4\'b0101)
// Partially oob at low side
i = -1;
x = \'hx;
x[i+:2] <= @e 2\'b10;
-> e;
`check(x, 4\'bxxx1)
// Partially oob at high side
i = 3;
x = \'hx;
x[i+:2] <= @e 2\'b01;
-> e;
`check(x, 4\'b1xxx)
// Fully oob at low side
i = -2;
x = \'hx;
x[i+:2] <= @e 2\'b11;
-> e;
`check(x, 4\'bxxxx)
// Fully oob at high side
i = 5;
x = \'hx;
x[i+:2] <= @e 2\'b11;
-> e;
`check(x, 4\'bxxxx)
// Undefined index
i = \'hx;
x = \'hx;
x[i+:2] <= @e 2\'b11;
-> e;
`check(x, 4\'bxxxx)
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
// This module generate enable and two-bit selector for verifying a 2-to-4 decoder
module stimulus #(parameter M = 8, T = 10) (
output reg [1:0] sel,
output reg en
);
bit [2:0] i;
initial begin
sel = 0;
en = 1\'bx;
#T;
sel = 1;
#T;
sel = 2;
#T;
sel = 3;
#T;
sel = 2\'bxx;
#T;
en = 0;
#T;
en = 1;
#T;
en = 1\'bx;
#T;
for (i = 0; i < M; i=i+1) begin
#T;
{sel, en} = i;
end
end
endmodule
// This module always checks that y complies with a decoding operation
module check (input [1:0] sel, input en, input [0:3] y);
always @(sel, en, y) begin
if (en == 0) begin
#1;
if (y !== 4\'b0000) begin
$display("ERROR");
$finish;
end
else if (en == 1) begin
#1;
case (sel)
0: if (y !== 4\'b1000) begin
$display("ERROR");
$finish;
end
1: if (y !== 4\'b0100) begin
$display("ERROR");
$finish;
end
2: if (y !== 4\'b0010) begin
$display("ERROR");
$finish;
end
3: if (y !== 4\'b0001) begin
$display("ERROR");
$finish;
end
default: if (y !== 4\'b0000) begin
$display("ERROR");
$finish;
end
endcase
end // else
else begin
if (y !== 4\'b0000) begin
$display("ERROR");
$finish;
end
end
end // if
end
endmodule
module test;
parameter M = 8;
parameter T = 10;
parameter S = 4*M*T + 40;
wire [1:0] sel;
wire en;
wire [0:3] y;
stimulus #(M, T) stim (.sel(sel), .en(en) );
dec2to4 duv (.sel(sel), .en(en), .y(y) );
check check (.sel(sel), .en(en), .y(y) );
initial begin
#S;
$display("PASSED");
$finish;
end
endmodule
|
// Regression test for GitHub issue #62 : assert on invalid verilog input
module test();
reg [15:0] memory[3:0];
reg [15:0] vector;
reg [3:0] value;
initial begin
value = memory[0][0];
value = memory[0][0][3:0];
value = memory[0][0][0 +: 4];
value = memory[0][0][4 -: 4];
value = vector[0][0];
value = vector[0][3:0];
value = vector[0][0 +: 4];
value = vector[0][4 -: 4];
end
endmodule
|
// Regression test for GitHub issue 14 : Bug in processing 1\'b1 >= |1\'bx.
module bug();
wire y = 1\'b1 >= 1\'bx;
initial begin
#0 $display("%b", y);
if (y !== 1\'bx)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module test();
typedef bit [3:0] array_t[];
array_t array;
initial begin
array = 8'd1 << 4;
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always if ( constant) statement_1 else statement_2 ;
module main ;
reg [3:0] value1 ;
initial
\tbegin
value1 = 0;
# 5 ;
if(value1 != 4\'d4)
$display("FAILED - always 3.1.5C always if ( constant) statementelse ;");
else
$display("PASSED");
\t $finish;
end
always if( 1\'b1) begin
# 1;
value1 = value1 + 1;
end
else value1 = 0 ;
endmodule
|
/*
* Copyright (c) 2001 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* Catch problems with non-zero lsb values in l-value expressions.
*/
module main;
reg [7:1] a = 6\'b111111;
reg [7:1] b = 6\'b000010;
integer q;
reg [7:1] x;
reg\t PCLK = 1;
always @(posedge PCLK)
for (q=1; q<=7; q=q+1)
x[q] <= #1 a[q] & b[q];
always #5 PCLK = !PCLK;
initial begin
// $dumpfile("dump.vcd");
// $dumpvars(0, main);
#50 $display("done: x=%b", x);
if (x !== 6\'b000010)
\t$display("FAILED -- x = %b", x);
else
\t$display("PASSED");
$finish;
end
endmodule // main
|
module top;
reg a, b;
reg q, d;
event foo;
always_comb begin
q = d;
fork
$display("fork/join 1");
join
fork
$display("fork/join_any 1");
join_any
fork
$display("fork/join_none 1");
join_none
a <= @foo 1\'b1;
@(b) a <= repeat(2) @foo 1\'b0;
wait (!a) $display("wait");
end
initial #1 $display("Expect compile errors!");
endmodule
|
// These don't do anything useful, but check for compiler errors.
module test();
integer i;
always begin
for (i = 0; i < 10; i = i + 1) ;
end
always begin
repeat (1) ;
end
always begin
while (1) ;
end
always begin
do ; while (1);
end
always begin
forever ;
end
endmodule
|
module test ();
parameter t=0;
reg t_not, t_zero;
generate
if (!t) begin
initial t_not = 1;
end
endgenerate
generate
if (t==0) begin
initial t_zero = 1;
end
endgenerate
initial begin
\t#1 if (t_not !== 1) begin
\t\t$display("FAILED -- t_not=%b", t_not);
\t\t$finish;
\tend
\tif (t_zero !== 1) begin
\t\t$display("FAILED -- t_zero=%b", t_zero);
\t\t$finish;
\tend
\t$display("PASSED");
end
endmodule
|
//
// Copyright (c) 1999 Peter Monta ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module main;
reg [3:0] a,b;
wire c;
assign c = a && b;
initial begin
a = 4\'d3;
b = 4\'d6;
#1;
if (c!==1) begin
$display("FAILED");
$finish;
end
a = 4\'d0;
#1;
if (c!==0) begin
$display("FAILED");
$finish;
end
b = 4\'d0;
#1;
if (c!==0) begin
$display("FAILED");
$finish;
end
$display("PASSED");
end
endmodule
|
// Copyright (c) 2015 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place / Suite 330, Boston, MA 02111/1307, USA
// Test for concatenation of function call results.
module test_concat_func();
logic [7:0] in_word, out_word;
concat_func dut(in_word, out_word);
initial begin
in_word = 8\'b11101010;
#1;
if(out_word !== 8\'b11010010) begin
$display("FAILED out_word = %b", out_word);
$finish();
end
$display("PASSED");
end
endmodule
|
// A simple generate example for VHDL conversion
module main();
wire [39:0] data;
integer j;
generate
genvar i;
for (i = 0; i < 4; i = i + 1) begin
inc u(data[(i+1)*8 - 1:i*8], data[(i+2)*8 - 1:(i+1)*8]);
end
endgenerate
assign data[7:0] = 1;
initial begin
#1;
$display(data[7:0]);
$display(data[15:8]);
$display(data[23:16]);
$display(data[31:24]);
$display(data[39:32]);
end
endmodule // simple_gen
module inc(in, out);
input [7:0] in;
output [7:0] out;
assign out = in + 1;
endmodule // inc
|
`define PREFIX\t\tmy_prefix
`define SUFFIX\t\tmy_suffix
`define BACKTICK\t"`"
`define name1\t\t`PREFIX``_```SUFFIX
`define name2(p,s)\tp``_``s
`define stringify(text)\t`"text`"
module test();
initial begin
$display(`BACKTICK);
$display(`stringify(`name1));
$display(`stringify(`name2(`PREFIX, `SUFFIX)));
end
endmodule
|
// Check that a vector base typeof a dynamic array type is evaluated in the
// scope where the array type is declared.
localparam A = 8;
typedef logic [A-1:0] T[];
module test;
localparam A = 4;
T x;
initial begin
x = new [1];
x[0] = 8\'hff;
if (x[0] === 8\'hff) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
|
// Copyright 2008, Martin Whitaker.
// This file may be freely copied for any purpose.
module array_port_events();
reg [1:0]\tData[3:0];
reg [1:0]\tIndex;
reg [1:0]\tValue;
integer\t\ti;
integer\t\tj;
initial begin
for (i = 0; i < 4; i = i + 1) begin
Index = i;
for (j = 0; j < 4; j = j + 1) begin
Data[i] = i + j;
#2;
end
end
end
always @* begin
case (Index)
0 : Value = Data[0];
1 : Value = Data[1];
2 : Value = Data[2];
3 : Value = Data[3];
endcase
end
always @(Value) begin
#1 $display("%d", Value);
end
endmodule
|
module main;
parameter MAP = 16\'h0123;
parameter VAL = 32\'h44_33_22_11;
wire [31:0] value;
generate
genvar m, n;
for (m = 0 ; m < 4 ; m = m+1) begin : drv
\t for (n = 0 ; n < 8 ; n = n+1) begin : drv_n
\t assign value[8*MAP[4*m +: 4] + n] = VAL[8*m+n +: 1];
\t end
end
endgenerate
initial begin
#1 $display("value = %h", value);
if (value !== 32\'h11_22_33_44) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
/***********************************************************************
*
* Copyright (C) 2011 Adrian Wise
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
***********************************************************************
*
* This is a testbench exercising gate-level modelling of DTL gates,
* distilled down (as a test-case) from a much larger design.
* The gates can only pull down strongly to ground and have a weak
* pull-up.
*
* This illustrates a problem in the git master branch as of 24 December
* 2011, where a gate that does not pull-up strongly cannot drive a bit
* of a bus (to either logic level), but can drive a single-bit wire
* correctly.
*
* This is an extended version of the test case provided with the
* bug report, to cover part selects with a non-zero base, and to
* make the error checking a bit more robust.
**********************************************************************/
`timescale 1 ns / 100 ps
module dtl_inv (op, in1);
output op;
input in1;
not (strong0, pull1) #16 not1 (op, in1);
endmodule // dtl_inv
module top;
reg d;
wire w;
wire [1:0] b;
reg pass;
dtl_inv u_1 (.op(w), .in1(d));
dtl_inv u_2 (.op(b[0]), .in1(d));
dtl_inv u_3 (.op(b[1]), .in1(b[0]));
initial begin
pass = 1\'b1;
d = 1\'b0;
# 100;
if ((w !== 1\'b1) || (b[0] !== 1\'b1) || (b[1] !== 1\'b0)) begin
$display("Failed (w !== b[0]): d = %b, w = %b, b = %b", d, w, b);
pass = 1\'b0;
end
d = 1\'b1;
# 100;
if ((w !== 1\'b0) || (b[0] !== 1\'b0) || (b[1] !== 1\'b1)) begin
$display("Failed (w !== b[0]): d = %b, w = %b, b = %b", d, w, b);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule // top
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always @ (event_expression) reg_lvalue = boolean_expr ;
// D: Note that initial has to be before always to execute!
module main ;
reg [3:0] value1,value2;
initial
\tbegin
# 1;
if(value1 != 4\'bxxxx)
$display("FAILED - 3.1.4I - initial value not xxxx;\
");
value2 = 4\'b1;
#10 ;
if(value1 != 4\'h5)
$display("FAILED - 3.1.4I - always @ (event_expression) reg_lvalue = boolean_expr;\
");
value2 = 4\'b0;
#10 ;
if(value1 != 4\'hA)
$display("FAILED - 3.1.4I - always @ (event_expression) reg_lvalue = boolean_expr;\
");
else
begin
$display("PASSED\
");
end
$finish;
end
always # 10 value1 = ~value1;
endmodule
|
module top;
reg [79:0] str;
integer val;
initial begin
// This should be a not defined in any module message.
$this_icarus_call_should_not_exist;
str = "5";
// This should be a system function is being called as a task error.
$sscanf(str, "%d", val);
// This should be a system task is being called as a function error.
val = $display;
end
endmodule
|
module bug();
reg [7:0] memory[1:0];
reg index;
initial begin
index = 0;
memory[~index] = 1;
if (memory[1] === 1)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
// Check that non-blocking event control assignments to concatanations work as
// expected.
module test;
reg failed = 1\'b0;
`define check(val, exp) \\
if (val !== exp) begin \\
$display("FAILED. %s: expected %b, got %b.", `"val`", exp, val); \\
failed = 1\'b1; \\
end
reg [3:0] x;
reg [3:0] y;
reg [3:0] z[1:0];
integer i = 0;
event e;
initial begin
// Test all of
// * vector
// * vector part select
// * array element
// * array element part
// Immediate index
{z[1][1:0],z[0],y[1:0],x} <= @e 12\'h5a5;
#1
// Assignment must not occur until the event is triggered
`check(z[1], 4\'bxxxx)
`check(z[0], 4\'bxxxx)
`check(y, 4\'bxxxx)
`check(x, 4\'bxxxx)
->e;
`check(z[1], 4\'bxx01);
`check(z[0], 4\'b0110);
`check(y, 4\'bxx10);
`check(x, 4\'b0101);
x = 4\'hx;
y = 4\'hx;
z[0] = 4\'hx;
z[1] = 4\'hx;
// Immediate index reverse order
{x,y[1:0],z[0],z[1][1:0]} <= @e 12\'ha5a;
#1
`check(z[1], 4\'bxxxx)
`check(z[0], 4\'bxxxx)
`check(y, 4\'bxxxx)
`check(x, 4\'bxxxx)
->e;
`check(z[1], 4\'bxx10);
`check(z[0], 4\'b0110);
`check(y, 4\'bxx01);
`check(x, 4\'b1010);
x = 4\'hx;
y = 4\'hx;
z[0] = 4\'hx;
z[1] = 4\'hx;
// Variable index
{z[i+1][i+:2],z[i],y[i+:2],x} <= @e 12\'h5a5;
#1
`check(z[1], 4\'bxxxx)
`check(z[0], 4\'bxxxx)
`check(y, 4\'bxxxx)
`check(x, 4\'bxxxx)
->e;
`check(z[1], 4\'bxx01);
`check(z[0], 4\'b0110);
`check(y, 4\'bxx10);
`check(x, 4\'b0101);
x = 4\'hx;
y = 4\'hx;
z[0] = 4\'hx;
z[1] = 4\'hx;
// Variable index reverse order
{x,y[i+:2],z[i],z[i+1][i+:2]} <= @e 12\'ha5a;
#1
`check(z[1], 4\'bxxxx)
`check(z[0], 4\'bxxxx)
`check(y, 4\'bxxxx)
`check(x, 4\'bxxxx)
->e;
`check(z[1], 4\'bxx10);
`check(z[0], 4\'b0110);
`check(y, 4\'bxx01);
`check(x, 4\'b1010);
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
// Copyright 2008, Martin Whitaker.
// This file may be freely copied for any purpose.
module array_word_part_select();
reg pass = 1\'b1;
reg [3:0]\tData[15:0];
reg [3:0]\tIndex;
wire [2:0]\tValue;
assign Value = Data[Index][2:0];
integer\t\ti;
initial begin
for (i = 0; i < 16; i = i + 1) begin
Data[i] = i;
end
for (i = 0; i < 16; i = i + 1) begin
#2 Index = i;
end
#2 if (pass) $display("PASSED");
end
always @(Index) begin
// $display(Index,, Value);
#1 if (Value !== Index % 8) begin
$display("Failed: testing index %d, expected %d, got %d", Index,
Index % 8, Value);
pass = 1\'b0;
end
end
endmodule
|
/*
* This is a post-synthesis test for the blif01a.v test. Run this
* simulation in these steps:
*
* $ iverilog -tblif -o foo.blif blif01a.v
* $ abc
* abc 01> read_blif foo.blif
* abc 02> write_verilog foo.v
* abc 03> quit
* $ iverilog -g2009 -o foo.vvp blif02a_tb.v foo.v
* $ vvp foo.vvp
*/
module main;
parameter WID = 4;
reg [WID-1:0] A, B;
wire\t\t QE, QN, QGT, QGE;
cmpN ucmp(.\\A[3] (A[3]), .\\A[2] (A[2]), .\\A[1] (A[1]), .\\A[0] (A[0]),
\t .\\B[3] (B[3]), .\\B[2] (B[2]), .\\B[1] (B[1]), .\\B[0] (B[0]),
\t .QE(QE), .QN(QN), .QGT(QGT), .QGE(QGE));
int\t\t adx;
int\t\t bdx;
initial begin
for (bdx = 0 ; bdx[WID]==0 ; bdx = bdx+1) begin
\t for (adx = 0 ; adx[WID]==0 ; adx = adx+1) begin
\t A <= adx[WID-1:0];
\t B <= bdx[WID-1:0];
\t #1 ;
\t if (QE !== (adx[WID-1:0]==bdx[WID-1:0])) begin
\t $display("FAILED -- A=%b, B=%b, QE=%b", A, B, QE);
\t $finish;
\t end
\t if (QN !== (adx[WID-1:0]!=bdx[WID-1:0])) begin
\t $display("FAILED -- A=%b, B=%b, QN=%b", A, B, QN);
\t $finish;
\t end
\t if (QGT !== (adx[WID-1:0] > bdx[WID-1:0])) begin
\t $display("FAILED -- A=%b, B=%b, QGT=%b", A, B, QGT);
\t $finish;
\t end
\t if (QGE !== (adx[WID-1:0] >= bdx[WID-1:0])) begin
\t $display("FAILED -- A=%b, B=%b, QGE=%b", A, B, QGE);
\t $finish;
\t end
\t end
end
$display("PASSED");
end
endmodule // main
|
// Copyright (c) 2016 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for basic loops in VHDL.
module vhdl_loop_test;
logic start;
int counter;
vhdl_loop dut(start, counter);
initial begin
for(int i = 0; i < 5; ++i) begin
if(counter !== i) begin
$display("FAILED");
$finish();
end
#10;
end
$display("PASSED");
$finish();
end
endmodule
|
// Check variable initialisation in constant functions.
module constfunc8();
function real uninitialised_r(input dummy);
real value;
uninitialised_r = value;
endfunction
function [7:0] uninitialised_2(input dummy);
reg bool [5:0] value;
uninitialised_2 = {1\'b1, value, 1\'b1};
endfunction
function [7:0] uninitialised_4(input dummy);
reg [5:0] value;
uninitialised_4 = {1\'b1, value, 1\'b1};
endfunction
localparam result_r = uninitialised_r(0);
localparam result_2 = uninitialised_2(0);
localparam result_4 = uninitialised_4(0);
reg failed;
initial begin
failed = 0;
$display("%0g", result_r);
if (result_r != 0.0) failed = 1;
$display("%b", result_2);
if (result_2 !== 8\'b10000001) failed = 1;
$display("%b", result_4);
if (result_4 !== 8\'b1xxxxxx1) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module test();
task t(a, b);
$display(a,,b);
endtask
initial t(0, 1);
endmodule
|
module top;
reg passed;
reg pevt;
reg evt;
reg pedge;
reg nedge;
initial begin
passed = 1\'b1;
#1; // Check X to 0
{pedge, nedge} = 2\'b01;
evt = 1\'b0;
#1; // Check 0 to X
pevt = evt;
{pedge, nedge} = 2\'b10;
evt = 1\'bx;
#1; // Check X to 1
pevt = evt;
{pedge, nedge} = 2\'b10;
evt = 1\'b1;
#1; // Check 1 to X
pevt = evt;
{pedge, nedge} = 2\'b01;
evt = 1\'bx;
#1; // Check X to Z
pevt = evt;
{pedge, nedge} = 2\'b00;
evt = 1\'bz;
#1; // Check Z to X
pevt = evt;
{pedge, nedge} = 2\'b00;
evt = 1\'bx;
#1; // Check X to Z (again)
pevt = evt;
{pedge, nedge} = 2\'b00;
evt = 1\'bz;
#1; // Check Z to 0
pevt = evt;
{pedge, nedge} = 2\'b01;
evt = 1\'b0;
#1; // Check 0 to Z
pevt = evt;
{pedge, nedge} = 2\'b10;
evt = 1\'bz;
#1; // Check Z to 1
pevt = evt;
{pedge, nedge} = 2\'b10;
evt = 1\'b1;
#1; // Check 1 to Z
pevt = evt;
{pedge, nedge} = 2\'b01;
evt = 1\'bz;
#1; // Check Z to 1 (again)
pevt = evt;
{pedge, nedge} = 2\'b10;
evt = 1\'b1;
#1; // Check 1 to 0
pevt = evt;
{pedge, nedge} = 2\'b01;
evt = 1\'b0;
#1; // Check 0 to 1
pevt = evt;
{pedge, nedge} = 2\'b10;
evt = 1\'b1;
#1;
if (passed) $display("PASSED");
end
always @(posedge evt) begin
if (!pedge) begin
$display("Error: posedge detected for %b -> %b", pevt, evt);
passed = 1\'b0;
end
end
always @(negedge evt) begin
if (!nedge) begin
$display("Error: negedge detected for %b -> %b", pevt, evt);
passed = 1\'b0;
end
end
always @(edge evt) begin
if (!nedge && !pedge) begin
$display("Error: edge detected for %b -> %b", pevt, evt);
passed = 1\'b0;
end
end
always @(evt)
$display("Checking the %b -> %b event", pevt, evt);
endmodule
|
`begin_keywords "1364-2005"
module top;
reg [31:0] var;
initial begin
$monitor(var);
var = 0;
repeat (60) begin
#1 var = $urandom_range(16);
end
end
endmodule
`end_keywords
|
/*
* This test reflects the problem reported in PR#1115.
*/
module test;
reg[7:0] addr [0:2], pixel;
wire match0 = addr[0] == pixel;
initial begin
pixel = 1;
addr[0] = 1;
addr[1] = 2;
addr[2] = 3;
#1 if (match0 !== 1\'b1) begin
\t $display("FAILED -- match0 is %b", match0);
\t $finish;
end
$display("PASSED");
$finish;
end // initial begin
endmodule
|
module test;
wire w;
wire q;
reg g;
pullup(w);
bufif1(w, 1\'b1, g);
pmos(q, w, 1\'b0);
bufif0(q, 1\'b0, g);
initial
begin
g = 1;
#10
$display(q, w);\t// should print "11"
#20
g = 0;\t\t// w changes from St1 to Pu1
#30
$display(q, w);\t// should print "01"
if (q == 1\'b0)
$display("PASSED");
else
$display("FAILED");
#40
$finish;
end
endmodule
|
`define VUG_PCREL(u, uch) ({ {(uch - 12 - 1 > 0 ? uch - 12 - 1 : 1){u[11]}}, \\
u[10:0], 2\'b00 })
module t();
parameter uch = 16;
parameter u_hossz = 32;
parameter u_prefix = 3;
reg [u_hossz - u_prefix - 1:0] v_utas;
reg [uch - 1:0] v_cim;
wire [uch - 1:0] v_ugras_ide;
assign v_ugras_ide = v_cim + `VUG_PCREL(v_utas, uch);
initial
begin
\tv_utas = \'h0fff;
\tv_cim = \'h7;
\t#1;
\tif(v_ugras_ide !== \'h3)
\t\t$display("FAILED");
\telse
\t\t$display("PASSED");
\t$finish;
end
endmodule
|
// This just tests the compiler accepts the syntax. It needs to be improved
// when deferred assertions are supported.
module test();
integer i = 1;
initial begin
assert #0 (i == 1);
assert #0 (i == 0);
assert #0 (i == 1) else $display("Check 3 : this shouldn\'t be displayed");
assert #0 (i == 0) else $display("Check 4 : this should be displayed");
assert #0 (i == 1) $display("Check 5 : this should be displayed");
assert #0 (i == 0) $display("Check 6 : this shouldn\'t be displayed");
assert #0 (i == 1) $display("Check 7 : this should be displayed");
else $display("Check 7 : this shouldn\'t be displayed");
assert #0 (i == 0) $display("Check 8 : this shouldn\'t be displayed");
else $display("Check 8 : this should be displayed");
end
endmodule
|
/*
* P1800/D8 22.13
* "`__FILE__ expands to the name of the current input file, in the form of a
* string literal."
*/
module aaa;
initial begin
#1;
$display(`__FILE__);
end
endmodule
/*
* P1800/D8 22.13
* "`__LINE__ expands to the current input line number, in the form of
* a simple decimal number."
*/
module bbb;
initial begin
#2;
if(`__LINE__ !== 21 ||
`__LINE__ !== 22) begin
$display("FAIL"); $finish;
end
$display("PASSED");
end
endmodule
|
`timescale 1ns/10ps
module TBUF_X2 (A, EN, Z);
input A;
input EN;
output Z;
bufif1(Z, A, EN);
specify
(A => Z) = (0.1, 0.2);
(EN => Z) = (0.3, 0.4);
endspecify
endmodule
module ckt (out, in, en);
output out;
input in, en;
TBUF_X2 dut (.A ( in ) , .EN ( en ) , .Z ( out ) ) ;
endmodule
module top;
wire out;
reg in, en;
ckt dut(out, in, en);
initial begin
$monitor($realtime,,out,"=",in,,en);
$sdf_annotate("ivltests/br960d.sdf", dut);
in = 1\'b0;
en = 1\'b0;
$display("Max (X->Z)");
// X -> Z = max(enable))
#10;
en = 1\'b1;
$display("Fall (Z->0)");
// Z -> 0 = tr(enable)
#10;
en = 1\'b0;
$display("Rise (0->Z)");
// 0 -> Z = tr(enable)
#5;
in = 1\'b1;
#5;
en = 1\'b1;
$display("Rise (Z->1)");
// Z -> 1 = tr(enable)
#10;
en = 1\'b0;
$display("Fall (1->Z)");
// 1 -> Z = tr(enable)
#10;
end
endmodule
|
program main;
function real sum_array(real array[]);
int idx;
sum_array = 0.0;
for (idx = 0 ; idx < array.size() ; idx = idx+1)
\tsum_array = sum_array + array[idx];
endfunction // sum_array
real obj[];
real foo;
initial begin
foo = sum_array(\'{});
if (foo != 0.0) begin
\t $display("FAILED -- sum of empty array returns %0d", foo);
\t $finish;
end
obj = new[3];
obj = \'{1.0,2.0,3.0};
foo = sum_array(obj);
if (foo != 6.0) begin
\t $display("FAILED -- sum of \'{%f,%f,%f} is %0d", obj[0], obj[1], obj[2], foo);
\t $finish;
end
obj = new[3] (\'{4.0,5.0,6.0});
foo = sum_array(obj);
if (foo != 15.0) begin
\t $display("FAILED -- sum of \'{4,5,6} is %0d", foo);
\t $finish;
end
$display("PASSED");
end // initial begin
endprogram // main
|
module automatic test();
function static integer accumulate1(input integer value);
static int acc = 1;
acc = acc + value;
return acc;
endfunction
function integer accumulate2(input integer value);
int acc = 1;
acc = acc + value;
return acc;
endfunction
localparam value1 = accumulate1(2);
localparam value2 = accumulate1(3);
localparam value3 = accumulate2(2);
localparam value4 = accumulate2(3);
integer value;
reg failed = 0;
initial begin
$display("%d", value1);
if (value1 !== 3) failed = 1;
$display("%d", value2);
if (value2 !== 4) failed = 1;
$display("%d", value3);
if (value3 !== 3) failed = 1;
$display("%d", value4);
if (value4 !== 4) failed = 1;
value = accumulate1(2);
$display("%d", value);
if (value !== 3) failed = 1;
value = accumulate1(3);
$display("%d", value);
if (value !== 6) failed = 1;
value = accumulate2(2);
$display("%d", value);
if (value !== 3) failed = 1;
value = accumulate2(3);
$display("%d", value);
if (value !== 4) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
/*
* This tests a trivial class. This tests that properties can be
* given types, and that the types behave properly.
*/
program main;
// Trivial example of a class
class foo_t ;
string a;
string b;
endclass : foo_t // foo_t
foo_t obj;
initial begin
obj = new;
// Absent any other constructor, strings get initialized as nil.
if (obj.a != "" || obj.b != "") begin
\t $display("FAILED -- String property not initialized.");
\t $finish;
end
// This is the most trivial assignment of class properties.
obj.a = "Hello";
obj.b = "World";
$display("obj = {%0s, %0s}", obj.a, obj.b);
if (obj.a != "Hello" || obj.b != "World") begin
\t $display("FAILED -- assign to object: obj.a=%0s, obj.b=%0s", obj.a, obj.b);
\t $finish;
end
$display("PASSED");
$finish;
end
endprogram // main
|
module automatic_error();
reg global;
task automatic auto_task;
reg local;
begin:block
force local = global;
end
endtask
endmodule
|
module top;
integer a;
initial begin
a = 15'1;
a = 15'0;
a = 15'x;
a = 15'X;
a = 15'z;
a = 15'Z;
end
endmodule
|
/*
* Copyright (c) 2002 Tom Verbeure
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
\tinteger myInt;
\treg [39:0] myReg40;
\treg [0:39] myReg40r;
\treg [0:38] myReg39r;
\treg [13:0] myReg14;
\treg [7:0] myReg8;
\tinitial begin
\t\t$display("============================ myReg8 = 65");
\t\tmyReg8 = 65;
\t\t$display(">|A|");
\t\t$display("*|%c|", myReg8);
\t\t$display("============================ myReg40 = \\"12345\\"");
\t\tmyReg40 = "12345";
\t\t$display(">|5|");
\t\t$display("*|%c|", myReg40);
\t\t$display(">|5|");
\t\t$display("*|%s|", myReg40[7:0]);
\t\t$display("============================ myReg40r = \\"12345\\"");
\t\tmyReg40r = "12345";
\t\t$display(">|5|");
\t\t$display("*|%c|", myReg40r);
\t\t$display(">|1|");
\t\t$display("*|%c|", myReg40r[0:7]);
\t\t$display("============================ myReg39r = \\"12345\\"");
\t\tmyReg39r = "12345";
\t\t$display(">|5|");
\t\t$display("*|%c|", myReg39r);
\t\t$display(">|b|");
\t\t$display("*|%c|", myReg39r[0:7]);
\t\t$display("============================ myReg14 = 33*256+65");
\t\tmyReg14 = 33*256 + 65;
\t\t$display(">|A|");
\t\t$display("*|%c|", myReg14);
\t\t$display(">|!|");
\t\t$display("*|%c|", myReg14[13:8]);
\t\t$display("============================ myInt = 66*256 + 65");
\t\tmyInt = 66*256 + 65;
\t\t$display(">|A|");
\t\t$display("*|%c|", myInt);
\tend
endmodule
|
// Check behaviour with out-of-range and undefined array indices
// on LHS of blocking procedural assignment.
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
module top;
reg array1[2:1];
reg array2[1:0];
`ifndef VLOG95
real array3[2:1];
real array4[1:0];
`endif
integer index;
reg failed;
initial begin
failed = 0;
array1[1] = 1\'b0;
array1[2] = 1\'b0;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
array1[0] = 1\'b1; // Constant out of bounds select may be an error
`endif
$display("array = %b %b", array1[2], array1[1]);
if ((array1[1] !== 1\'b0) || (array1[2] !== 1\'b0)) failed = 1;
array1[1] = 1\'b0;
array1[2] = 1\'b0;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
array1[3] = 1\'b1; // Constant out of bounds select may be an error
`endif
$display("array = %b %b", array1[2], array1[1]);
if ((array1[1] !== 1\'b0) || (array1[2] !== 1\'b0)) failed = 1;
array2[0] = 1\'b0;
array2[1] = 1\'b0;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
array2[\'bx] = 1\'b1; // Constant undefined out of bounds select may be an error
`endif
$display("array = %b %b", array2[1], array2[0]);
if ((array2[0] !== 1\'b0) || (array2[1] !== 1\'b0)) failed = 1;
index = 0;
array1[1] = 1\'b0;
array1[2] = 1\'b0;
array1[index] = 1\'b1;
$display("array = %b %b", array1[2], array1[1]);
if ((array1[1] !== 1\'b0) || (array1[2] !== 1\'b0)) failed = 1;
index = 3;
array1[1] = 1\'b0;
array1[2] = 1\'b0;
array1[index] = 1\'b1;
$display("array = %b %b", array1[2], array1[1]);
if ((array1[1] !== 1\'b0) || (array1[2] !== 1\'b0)) failed = 1;
index = \'bx;
array2[0] = 1\'b0;
array2[1] = 1\'b0;
array2[index] = 1\'b1;
$display("array = %b %b", array2[1], array2[0]);
if ((array2[0] !== 1\'b0) || (array2[1] !== 1\'b0)) failed = 1;
`ifndef VLOG95
array3[1] = 0.0;
array3[2] = 0.0;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
array3[0] = 1.0; // Constant out of bounds select may be an error
`endif
$display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1;
array3[1] = 0.0;
array3[2] = 0.0;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
array3[3] = 1.0; // Constant out of bounds select may be an error
`endif
$display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1;
array4[0] = 0.0;
array4[1] = 0.0;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
array4[\'bx] = 1.0; // Constant undefined out of bounds select may be an error
`endif
$display("array = %0g %0g", array4[1], array4[0]);
if ((array4[0] != 0.0) || (array4[1] != 0.0)) failed = 1;
index = 0;
array3[1] = 0.0;
array3[2] = 0.0;
array3[index] = 1.0;
$display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1;
index = 3;
array3[1] = 0.0;
array3[2] = 0.0;
array3[index] = 1.0;
$display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1;
index = \'bx;
array4[0] = 0.0;
array4[1] = 0.0;
array4[index] = 1.0;
$display("array = %0g %0g", array4[1], array4[0]);
if ((array4[0] != 0.0) || (array4[1] != 0.0)) failed = 1;
`endif
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
// Check that a class constructor with non-ANSI port results in an error.
module test;
class C;
function new;
input x; // This is a syntax error
$display("FAILED");
endfunction
endclass
C c = new;
endmodule
|
module test();
string str;
reg [127:0] bitstr;
initial begin
str = "hello";
bitstr = str;
end
endmodule
|
module top_module(
input wire [2:0] N,
input wire [7:0] In,
output reg [7:0] Out
);
wire [N:0] Array[7:0];
assign Array[0][0] = In[0];
assign Array[0][7:1] = In[7:1];
initial begin
Out[0] = Array[0][0];
Out[7:1] = Array[0][7:1];
end
endmodule
|
module test_mux
(input wire [1:0] D0, D1,
input wire [1:0] S,
output reg [1:0] Q);
always @(*) begin
if (S[1]==1'b0)
\tcase (S[0])
\t 1'b0: Q = D0;
\t 1'b1: Q = D1;
\tendcase // case (S[0])
else
\tQ = 2'b0;
end
endmodule // test_mux
|
// Three basic tests in here:
// 1. byte must be initialised before any initial or always block
// 2. assignments to (unsigned) bytes with random numbers
// 3. assignments to (unsigned) bytes with random values including X and Z
module ibyte_test;
parameter TRIALS = 100;
parameter MAX = \'h7fffffff_ffffffff;
reg [63:0] ar; // should it be "reg unsigned [7:0] aw"?
reg [63:0] ar_xz; // same as above here?
reg [63:0] ar_expected; // and here
longint unsigned bu;
longint unsigned bu_xz;
integer i;
assign bu = ar;
assign bu_xz = ar_xz;
// all test
initial begin
// time 0 checkings (Section 6.4 of IEEE 1850 LRM)
if (bu !== 64\'b0 | bu_xz != 64\'b0)
begin
$display ("FAILED - time zero initialisation incorrect: %b %b", bu, bu_xz);
$finish;
end
// random numbers
for (i = 0; i< TRIALS; i = i+1)
begin
#1;
ar = {$random} % MAX;
#1;
if (bu !== ar)
begin
$display ("FAILED - incorrect assigment to byte: %b", bu);
$finish;
end
end
# 1;
// with \'x injections (Section 4.3.2 of IEEE 1850 LRM)
for (i = 0; i< TRIALS; i = i+1)
begin
#1;
ar = {$random} % MAX;
ar_xz = xz_inject (ar);
ar_expected = xz_expected (ar_xz);
#1;
if (bu_xz !== ar_expected) // \'x -> \'0, \'z -> \'0
begin
$display ("FAILED - incorrect assigment to byte (when \'x): %b", bu);
$finish;
end
end
# 1;
$display("PASSED");
end
// this returns X and Z states into bit random positions for a value
function [63:0] xz_inject (input [63:0] value); // should it be "input unsigned [7:0]" instead?
integer i, temp;
begin
temp = {$random} % MAX;
for (i=0; i<64; i=i+1)
begin
if (temp[i] == 1\'b1)
begin
temp = $random % MAX;
if (temp <= 0)
value[i] = 1\'bx; // \'x noise
else
value[i] = 1\'bz; // \'z noise
end
end
xz_inject = value;
end
endfunction
// this function returns bit positions with either X or Z to 0 for an input value
function [63:0] xz_expected (input [63:0] value_xz); // should it be "input unsigned [7:0] instead?
integer i;
begin
for (i=0; i<64; i=i+1)
begin
if (value_xz[i] === 1\'bx || value_xz[i] === 1\'bz )
value_xz[i] = 1\'b0; // forced to zero
end
xz_expected = value_xz;
end
endfunction
endmodule
|
module part2 (
\\6A_A ,
\\6Y_A ,
VCC ,
GND ,
\\6A_B ,
\\6Y_B ,
\\6A_C ,
\\6Y_C ,
\\6A_D ,
\\6Y_D ,
\\6A_E ,
// note: there is not a space character before the nl below
// no space character after nl also
\\6Y_E
) ;
input \\6A_A ;
output \\6Y_A ;
input VCC ;
input GND ;
input \\6A_B ;
output \\6Y_B ;
input \\6A_C ;
output \\6Y_C ;
input \\6A_D ;
output \\6Y_D ;
input \\6A_E ;
output \\6Y_E ;
assign \\6Y_A = ~\\6A_A ;
assign \\6Y_B = ~\\6A_B ;
assign \\6Y_C = ~\\6A_C ;
assign \\6Y_D = ~\\6A_D ;
assign \\6Y_E = ~\\6A_E ;
endmodule
|
/*
* Copyright (c) 1998-2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* SDW: Verify expression using bit-wise or in a parameter declaration
*/
module test;
parameter A0 = | 4\'b0001;
initial
begin
if(A0 !== 1\'b1)
$display("FAILED - bit-wise and in an expression .");
else
$display("PASSED");
end
endmodule
|
//
// Copyright (c) 2004 Stephen Williams <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module main;
reg C;
reg [1:0] in;
wire [1:0] out;
DFF u [1:0] (out, in, C);
initial begin
C <= 0;
in <= 2\'b00;
#10 C <= 1;
#10 if (out !== 2\'b00) begin
\t $display("FAILED -- out=%b, in=%b", out, in);
\t $finish;
end
C <= 0;
in <= 2\'b10;
#10 C <= 1;
#10 if (out !== 2\'b10) begin
\t $display("FAILED -- out=%b, in=%b", out, in);
\t $finish;
end
C <= 0;
in <= 2\'b01;
#10 C <= 1;
#10 if (out !== 2\'b01) begin
\t $display("FAILED -- out=%b, in=%b", out, in);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule // main
module DFF(output reg Q, input D, input C);
always @(posedge C)
Q <= D;
endmodule // DFF
|
/*
* Copyright (c) 2001 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* Bit select of a net (a wire) using the index of a for loop.
*/
module main;
// Make a vector of bits, an array of functors in practice, and
// create a net that hooks to that array backwards.
reg [5:1] vect = 5\'b10100;
wire [5:1] tmp = { vect[1], vect[2], vect[3], vect[4], vect[5] };
reg [2:0] idx;
initial begin
#1 $display("vect=%b, tmp=%b", vect, tmp);
for (idx = 1 ; idx <= 5 ; idx = idx + 1) begin
\t $display("idx=%d: vect=%b, tmp=%b", idx, vect[idx], tmp[idx]);
\t if (tmp[idx] !== vect[6-idx]) begin
\t $display("FAILED");
\t $finish;
\t end
end
$display("PASSED");
end
endmodule // main
|
// Check that it is an error to declare a non-ANSI module port with implicit
// packed dimensions if it is later redeclared as an integer typed variable.
// Even if the size of the packed dimensions matches that of the size of the
// integer type.
module test(x);
output [31:0] x;
integer x;
initial begin
$display("FAILED");
end
endmodule
|
/*
* Copyright (c) 2002 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
reg [7:0] testr;
wire [7:0] testw = {-5\'d1, -3\'sd1};
initial begin
#1 testr = {-5\'d1, -3\'sd1};
if (testr !== 8\'b11111_111) begin
\t $display("FAILED -- testr=%b", testr);
\t $finish;
end
if (testw !== 8\'b11111_111) begin
\t $display("FAILED -- testw=%b", testw);
\t $finish;
end
$display("testr=%b", testr);
$display("testw=%b", testw);
$display("PASSED");
end // initial begin
endmodule // main
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate variable right shift in assign
module main;
reg globvar;
reg [7:0] var1,var2,var3;
reg error;
wire [7:0] value;
assign value = var1 >> var2;
initial
begin
error = 0;
#1 ;
var1 = 8\'h80;
var2 = 8\'h7;
#1;
if(value !== 8\'h1)
begin
error = 1;
\t$display ("FAILED - 80 >> 7 is %h",value);
end
#1 ;
var1 = 8\'h80;
var2 = 8\'h6;
#1;
if(value !== 8\'h2)
begin
error = 1;
\t$display ("FAILED - 80 >> 6 is %h",value);
end
#1 ;
var1 = 8\'h80;
var2 = 8\'h5;
#1;
if(value !== 8\'h4)
begin
error = 1;
\t$display ("FAILED - 80 >> 5 is %h",value);
end
#1 ;
var1 = 8\'h80;
var2 = 8\'h4;
#1;
if(value !== 8\'h8)
begin
error = 1;
\t$display ("FAILED - 80 >> 4 is %h",value);
end
#1 ;
var1 = 8\'h80;
var2 = 8\'h3;
#1;
if(value !== 8\'h10)
begin
error = 1;
\t$display ("FAILED - 80 >> 3 is %h",value);
end
#1 ;
var1 = 8\'h80;
var2 = 8\'h2;
#1;
if(value !== 8\'h20)
begin
error = 1;
\t$display ("FAILED - 80 >> 2 is %h",value);
end
#1 ;
var1 = 8\'h80;
var2 = 8\'h1;
#1;
if(value !== 8\'h40)
begin
error = 1;
\t$display ("FAILED - 80 >> 1 is %h",value);
end
#1 ;
var1 = 8\'h80;
var2 = 8\'h0;
#1;
if(value !== 8\'h80)
begin
error = 1;
\t$display ("FAILED - 80 >> 0 is %h",value);
end
#1 ;
var1 = 8\'ha5;
var2 = 8\'h7;
#1;
if(value !== 8\'h01)
begin
error = 1;
\t$display ("FAILED - a5 >> 7 is %h",value);
end
#1 ;
var1 = 8\'ha5;
var2 = 8\'h1;
#1;
if(value !== 8\'h52)
begin
error = 1;
\t$display ("FAILED - aa >> 1 is %h",value);
end
if(error === 0)
$display("PASSED");
end
endmodule // main
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate inout with id(a,a) inout a; definition.
module id(a,a);
inout a;
endmodule
module top ();
wire b,c;
id i1(b,c);
reg a, error, ena_a,ena_b;
assign c = ena_a ? a : 1\'bz;
assign b = ena_b ? a : 1\'bz;
initial
begin
error = 0;
ena_a = 1\'b0;
ena_b = 1\'b0;
#1 ;
ena_a = 1\'b1;
#1 ;
a= 0;
#1;
if(b !== 1\'b0)
begin
error = 1;
$display("FAILED - b init value not 1\'b0 a=%b,b=%b,c=%b",a,b,c);
end
if(c !== 1\'b0)
begin
error = 1;
$display("FAILED - c init value not 1\'b0 a=%b,b=%b,c=%b",a,b,c);
end
#1 ;
a= 1;
#1;
if(b !== 1\'b1)
begin
error = 1;
$display("FAILED - b init value not 1\'b1 a=%b,b=%b,c=%b",a,b,c);
end
if(c !== 1\'b1)
begin
error = 1;
$display("FAILED - c init value not 1\'b1 a=%b,b=%b,c=%b",a,b,c);
end
#1 ;
ena_a = 1\'b0;
#1 ;
ena_b = 1\'b1;
#1 ;
a= 0;
#1;
if(b !== 1\'b0)
begin
error = 1;
$display("FAILED - b init value not 1\'b0 a=%b,b=%b,c=%b",a,b,c);
end
if(c !== 1\'b0)
begin
error = 1;
$display("FAILED - c init value not 1\'b0 a=%b,b=%b,c=%b",a,b,c);
end
#1 ;
a= 1;
#1;
if(b !== 1\'b1)
begin
error = 1;
$display("FAILED - b init value not 1\'b1 a=%b,b=%b,c=%b",a,b,c);
end
if(c !== 1\'b1)
begin
error = 1;
$display("FAILED - c init value not 1\'b1 a=%b,b=%b,c=%b",a,b,c);
end
if(error == 0)
$display("PASSED");
end
endmodule
|
// Verify that a zero width signal replication is handled correctly.
module top;
reg pass;
reg [31:0] in_full;
wire [31:0] pa_out_full, ca_out_full;
reg [29:0] in_part;
wire [31:0] pa_out_part, ca_out_part;
initial begin
pass = 1\'b1;
in_full = {16{2\'b10}};
in_part = {15{2\'b01}};
#1;
if (pa_out_full !== 32\'b10101010101010101010101010101010) begin
$display("Failed: pa_out_full, got %b", pa_out_full);
pass = 1\'b1;
end
if (ca_out_full !== 32\'b10101010101010101010101010101010) begin
$display("Failed: ca_out_full, got %b", ca_out_full);
pass = 1\'b1;
end
if (pa_out_part !== 32\'bxx010101010101010101010101010101) begin
$display("Failed: pa_out_part, got %b", pa_out_part);
pass = 1\'b1;
end
if (ca_out_part !== 32\'bzz010101010101010101010101010101) begin
$display("Failed: ca_out_part, got %b", ca_out_part);
pass = 1\'b1;
end
if (pass) $display("PASSED");
end
param #(32) full(pa_out_full, ca_out_full, in_full);
param #(30) part(pa_out_part, ca_out_part, in_part);
endmodule
module param #(parameter width = 32) (
output reg [31:0] pa_out,
output wire [31:0] ca_out,
input [width-1:0] in);
wire z_pad = 1\'bz;
wire x_pad = 1\'bx;
assign ca_out = {{32-width{z_pad}}, in};
always @* pa_out = {{32-width{x_pad}}, in};
endmodule
|
`timescale 1ns/10ps
module top;
reg pass;
real result;
initial begin
pass = 1\'b1;
result = $abstime;
if (result != 0.0) begin
$display("FAILED at time 0, expected 0.0, got %g", result);
pass = 1\'b0;
end
#10;
result = $abstime;
if ($abs(result-10e-9) > result*1e-9) begin
$display("FAILED at time 10ns, expected 1e-8, got %g", result);
pass = 1\'b0;
end
#999990;
result = $abstime;
if ($abs(result-0.001) > result*1e-9) begin
$display("FAILED at time 1ms, expected 0.001, got %g", result);
pass = 1\'b0;
end
`ifdef __ICARUS_UNSIZED__
#9999000000;
`else
#9999000000.0;
`endif
result = $abstime;
if ($abs(result-10.0) > result*1e-9) begin
$display("FAILED at time 10s, expected 10.0, got %g", result);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
//
// Copyright (c) 1999 Peter Monta ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module main;
wire [3:0] a,b,c,d,e,f;
ma a1(a);
ma #(4\'d9) a2(b);
mb #(4\'d12) b1(c);
mb b2(d);
mc #(4\'d2) c1(e,f);
initial begin
#1;
if (a===4\'d5 && b===4\'d9 && c===4\'d12 && d===4\'d7 && e===4\'d2 && f===4\'d3)
$display("PASSED");
else
$display("FAILED");
end
endmodule
module ma(x);
output [3:0] x;
parameter P = 4\'d5;
assign x = P;
endmodule
module mb(x);
output [3:0] x;
parameter Q = 4\'d7;
ma #(Q) a1(x);
endmodule
module mc(x,y);
output [3:0] x,y;
parameter R = 4\'d1;
parameter S = 4\'d3;
ma #(R) a1(x);
ma #(S) a2(y);
endmodule
|
module main;
reg [1:0] x;
reg [2:0] y;
initial begin
x = 1;
y = {1\'b0, x << 1};
if (y !== 3\'b010) begin
\t $display("FAILED -- y (%b) != 3\'b010", y);
\t $finish;
end
y = {1\'b0, x << 2};
if (y !== 3\'b000) begin
\t $display("FAILED -- y (%b) != 3\'b000", y);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
//
// SDW - Int type declaration/validation
//
// D: Assign a 16 bit vector to an int and observe the 0 extension.
// D: Assign a 32 bit vector to an int and observer same value.
// D: Add -1 + 1. Add 0 and -1...and observer correct values.
module main();
reg [15:0] a;
reg [31:0] b;
integer result;
integer int_a;
integer int_b;
initial // Excitation block
begin
a = 0;
b = 0;
result = 0;
# 5;\t\t\t// Assign a shorter value
a = 16\'h1234;\t// should see 0 extension in result
result = a;
# 5;\t\t\t// Assign a 32 bit vector
b = 32\'h12345678 ;
result = b;
# 5;\t\t\t// Validate sum basic integer arithmetic
int_a = -1 ;\t\t// pun intended!
int_b = 1;
result = int_a + int_b;
# 5;
int_a = 0;
int_b = -1;
result = int_a + int_b;
end
initial // Validation block
begin
#1 ;
#5 ;
if(result != 32\'h00001234)
begin
$display("FAILED - Bit extend wrong\
");
$finish ;
end
#5 ;
if(result != 32\'h12345678)
begin
$display("FAILED - 32 bit assign wrong\
");
$finish ;
end
#5 ;
if(result != 32\'h00000000)
begin
$display("FAILED - -1 + 1 = %h\
",result);
$finish ;
end
#5 ;
if(result != 32\'hffffffff)
begin
$display("FAILED - 0 - 1 = %h\
",result);
$finish ;
end
$display("PASSED\
");
$finish ;
end
endmodule
|
// Check that it is possible to declare the data type for an integer type module
// port before the direction for non-ANSI style port declarations.
module test(x);
integer x;
output x;
initial begin
if ($bits(x) == $bits(integer)) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
|
// Copyright (c) 2016 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Resize function test
module vhdl_resize_test;
logic signed [7:0] in;
logic signed [15:0] out;
vhdl_resize dut(in, out);
initial begin
in = -120;
#0;
if(out !== -115) begin
$display("FAILED 1: out = %d", out);
$finish();
end
in = 120;
#0;
if(out !== 125) begin
$display("FAILED 2: out = %d", out);
$finish();
end
$display("PASSED");
end
endmodule
|
module test;
parameter some = 4;
wire [some-1:0] flag1;
genvar i;
generate
for (i = 0; i < some; i = i + 1)
\tbegin : what
\t wire [some-1:0] slice;
\tend
endgenerate
generate
for (i = 0; i < some; i = i + 1)
\tbegin : ab
\t assign what[i].slice[i] = 1\'b1;
\t assign flag1[i] = &what[i].slice;
\tend
endgenerate
integer\t idx;
initial #1 begin
for (idx = 0 ; idx < some ; idx = idx+1) begin
\t if (flag1[idx] !== 1\'bx) begin
\t $display("FAILED -- flag1=%b", flag1);
\t $finish;
\t end
end
$display("PASSED");
$finish;
end
endmodule
|
/*
* Copyright (c) 2014 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
`default_nettype none
module main;
class test_t;
reg [1:0] a;
reg [2:0] b;
function new (int ax, int bx);
\t begin
\t a = ax;
\t b = bx;
\t end
endfunction // new
endclass // test_t
test_t foo [0:3][0:7], tmp;
bit [3:0] idx1, idx2;
initial begin
for (idx1 = 0 ; idx1 < 4 ; idx1 = idx1+1) begin
\t for (idx2 = 0 ; idx2 <= 7 ; idx2 = idx2+1)
\t foo[idx1][idx2] = new(idx1,idx2);
end
foreach (foo[ia,ib]) begin
\t if (ia > 3 || ib > 7) begin
\t $display("FAILED -- index out of range: ia=%0d, ib=%0d", ia, ib);
\t $finish;
\t end
\t tmp = foo[ia][ib];
\t if (tmp.a !== ia[1:0] || tmp.b !== ib[2:0]) begin
\t $display("FAILED -- foo[%0d][%0d] == %b", ia, ib, {tmp.a, tmp.b});
\t $finish;
\t end
\t foo[ia][ib] = null;
end
for (idx1 = 0 ; idx1 < 4 ; idx1 = idx1+1) begin
\t for (idx2 = 0 ; idx2 <= 7 ; idx2 = idx2+1)
\t if (foo[idx1][idx2] != null) begin
\t $display("FAILED -- foreach failed to visit foo[%0d][%0d]", idx1,idx2);
\t $finish;
\t end
end
$display("PASSED");
end
endmodule // main
|
module test();
wire a, b;
a__a a_(
.b_buf(b),
.b (a)
);
endmodule
module a__a(b_buf, b);
output b_buf;
input b;
endmodule
|
/*
* Copyright (c) 2000 Yasuhisa Kato <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module drvz( clk, iA, iC, ioS );
input clk, iA, iC ;
inout ioS ;
assign ioS = (iC) ? iA : \'bz ;
endmodule
module main;
reg clk, c ;
initial begin clk = 0 ; forever #5 clk = ~clk ; end
initial begin c = 0 ; #40 $finish(0); end
wire a, b, s ;
assign a = \'b0 ;
assign b = \'b1 ;
always @(posedge clk) c <= ~c ;
drvz M ( clk, a, c, s ) ;
drvz N ( clk, b, ~c, s ) ; // line(A)
always @(posedge clk)
$display("%b %b %b", s, a, b );
endmodule
// expected output
// 1 0 1
// 0 0 1
// 1 0 1
// 0 0 1
// ivl 0.3 result
// x 0 1
// 0 0 1
// x 0 1
// 0 0 1
|
module top_module(
input wire [2:0] N,
input wire [7:0] In,
output reg [7:0] Out
);
wire [7:0] Array[7:N];
assign Array[0][0] = In[0];
assign Array[0][7:1] = In[7:1];
initial begin
Out[0] = Array[0][0];
Out[7:1] = Array[0][7:1];
end
endmodule
|
// Copyright 2007, Martin Whitaker.
// This file may be freely copied for any purpose.
module memory_monitor();
reg [7:0] Memory[0:15];
reg [3:0] Index;
wire Flag1;
wire FlagI;
assign Flag1 = (Memory[1] == 0);
assign FlagI = (Memory[Index] == 0);
initial begin
Index = 1;
Memory[Index] = 0;
#1 $display("Flag1 = %b, FlagI = %b", Flag1, FlagI);
Memory[Index] = 1;
#1 $display("Flag1 = %b, FlagI = %b", Flag1, FlagI);
end
endmodule
|
typedef struct packed {
logic [1:0] hig;
logic [1:0] low;
} foo_t;
module main;
// This typedef should work, and should shadow the foo_t definition
// in the $root scope.
typedef struct packed {
logic [2:0] hig_x;
logic [2:0] low_x;
} foo_t;
foo_t foo;
initial begin
foo = 6\'b111000;
if ($bits(foo_t) != 6) begin
\t $display("FAILED -- Got wrong foo_t definition?");
\t $finish;
end
if ($bits(foo) != 6) begin
\t $display("FAILED -- $bits(foo)==%0d", $bits(foo));
\t $finish;
end
if (foo.hig_x !== 3\'b111) begin
\t $display("FAILED -- foo=%b, foo.hig_x=%b", foo, foo.hig_x);
\t $finish;
end
if (foo.low_x !== 3\'b000) begin
\t $display("FAILED -- foo=%b, foo.low_x=%b", foo, foo.low_x);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
module copy(inout [1:0] out, inout [1:0] in);
assign out = in;
endmodule
module top();
reg [2:0] r;
wire [1:0] i1;
wire [1:0] i2;
wire [1:0] i3;
wire [0:0] o1;
wire [1:0] o2;
wire [2:0] o3;
assign i1 = r;
assign i2 = r;
assign i3 = r;
copy copy1(o1, i1);
copy copy2(o2, i2);
copy copy3(o3, i3);
reg failed;
initial begin
failed = 0;
for (r = 0; r < 4; r = r + 1) begin
#1 $display("%b : %b %b : %b %b : %b %b", r[1:0], i1, o1, i2, o2, i3, o3);
if (o1 !== r[0]) failed = 1;
if (o2 !== r[1:0]) failed = 1;
if (o3 !== {1\'bz, r[1:0]}) failed = 1;
end
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module test();
reg [13:0] a;
reg b;
reg c;
always @(a or b)
begin
case ({1\'b0,~b,a[3:0]})
6\'b00_0000 : begin
c = 1\'b1;
end
default : begin
c = 1\'b0;
end
endcase
end
initial begin
#1 /* Wait for the always block above to get settled. */;
a = 0;
b = 0;
#1 if (c !== 0) begin
$display("FAILED - a=%b, b=%b, c=%b", a, b, c);
$finish;
end
b = 1;
#1 if (c !== 1) begin
$display("FAILED - a=%b, b=%b, c=%b", a, b, c);
$finish;
end
$display("PASSED");
end // initial begin
endmodule
|
/*
* 1364-2001 19.3.2 "An undefined text macro has no value, just as if it had
* never been defined."
*/
`define a 1
`ifdef a
`define b 1
`else
`define b 0
`endif
`undef a
`ifdef a
`define c 1
`else
`define c 0
`endif
module test;
initial begin
if(`a+1 !== 1) begin $display("FAIL"); $finish; end
if(`b+1 === 1) begin $display("FAIL"); $finish; end
if(`c+1 !== 1) begin $display("FAIL"); $finish; end
$display("PASSED");
end
endmodule
|
module top;
parameter cond = 1;
parameter value = 25;
parameter test = (cond) ? 5: 0;
defparam dut.lwrval = (cond == 1) ? 6: (100/value) + 0.5;
lower dut();
endmodule
module lower;
parameter lwrval = 4;
initial if (lwrval != 6.0) $display("FAILED"); else $display("PASSED");
endmodule
|
// Check that using a real type as the base type for an enum results in an
// error.
module test;
enum real {
A
} e;
initial begin
$display("FAILED");
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate variable left shift in assign
module main;
reg globvar;
reg [7:0] var1,var2,var3;
reg error;
wire [7:0] value;
assign value = var1 << var2;
initial
begin
error = 0;
#1 ;
var1 = 8\'h1;
var2 = 8\'h0;
#1;
if(value !== 8\'h1)
begin
error = 1;
\t$display ("FAILED - 1 << 0 is %h",value);
end
#1 ;
var1 = 8\'h1;
var2 = 8\'h1;
#1;
if(value !== 8\'h2)
begin
error = 1;
\t$display ("FAILED - 1 << 1 is %h",value);
end
#1 ;
var1 = 8\'h1;
var2 = 8\'h2;
#1;
if(value !== 8\'h4)
begin
error = 1;
\t$display ("FAILED - 1 << 2 is %h",value);
end
#1 ;
var1 = 8\'h1;
var2 = 8\'h3;
#1;
if(value !== 8\'h8)
begin
error = 1;
\t$display ("FAILED - 1 << 3 is %h",value);
end
#1 ;
var1 = 8\'h1;
var2 = 8\'h4;
#1;
if(value !== 8\'h10)
begin
error = 1;
\t$display ("FAILED - 1 << 4 is %h",value);
end
#1 ;
var1 = 8\'h1;
var2 = 8\'h5;
#1;
if(value !== 8\'h20)
begin
error = 1;
\t$display ("FAILED - 1 << 5 is %h",value);
end
#1 ;
var1 = 8\'h1;
var2 = 8\'h6;
#1;
if(value !== 8\'h40)
begin
error = 1;
\t$display ("FAILED - 1 << 6 is %h",value);
end
#1 ;
var1 = 8\'h1;
var2 = 8\'h7;
#1;
if(value !== 8\'h80)
begin
error = 1;
\t$display ("FAILED - 1 << 6 is %h",value);
end
#1 ;
var1 = 8\'ha5;
var2 = 8\'h7;
#1;
if(value !== 8\'h80)
begin
error = 1;
\t$display ("FAILED - a5 << 7 is %h",value);
end
#1 ;
var1 = 8\'ha5;
var2 = 8\'h1;
#1;
if(value !== 8\'h4a)
begin
error = 1;
\t$display ("FAILED - aa << 1 is %h",value);
end
if(error === 0)
$display("PASSED");
end
endmodule // main
|
// Check that the var keyword is supported for module ANSI output ports
bit failed = 1\'b0;
`define check(val, exp) \\
if (val !== exp) begin \\
$display("FAILED(%0d). \'%s\' expected %b, got %b", `__LINE__, `"val`", val, exp); \\
failed = 1\'b1; \\
end
module M #(
parameter VAL_X = 0,
parameter VAL_Y = 0,
parameter VAL_Z = 0,
parameter VAL_W = 0
) (
output var x,
output var [7:0] y,
output var signed [7:0] z,
output var logic [7:0] w
);
assign x = VAL_X;
assign y = VAL_Y;
assign z = VAL_Z;
assign w = VAL_W;
endmodule
module test;
logic x1;
logic x2;
logic [7:0] y1;
logic [7:0] y2;
logic signed [7:0] z1;
logic signed [7:0] z2;
logic [7:0] w1;
logic [7:0] w2;
M #(
.VAL_X (1\'b1),
.VAL_Y (10),
.VAL_Z (-1),
.VAL_W (20)
) i_m1 (
.x (x1),
.y (y1),
.z (z1),
.w (w1)
);
// The type for var should default to logic, check that the value can be X
M #(
.VAL_X (1\'bx),
.VAL_Y (8\'hxx),
.VAL_Z (8\'hxx),
.VAL_W (8\'hxx)
) i_m2 (
.x (x2),
.y (y2),
.z (z2),
.w (w2)
);
initial begin
`check(x1, 1\'b1)
`check(y1, 10)
`check(z1, -1)
`check(w1, 20)
`check(x2, 1\'bx)
`check(y2, 8\'hxx)
`check(z2, 8\'hxx)
`check(w2, 8\'hxx)
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
// Check that base class defined in a package is handled correctly
package P;
class B;
task check;
$display("PASSED");
endtask
endclass
endpackage
module test;
class B;
task check;
$display("FAILED");
endtask
endclass
class C extends P::B;
endclass
C c;
initial begin
c = new;
c.check();
end
endmodule
|
module tb;
parameter A = 34;
parameter B = 17;
parameter C = ((A+1)>>1) + (B-((A+1)>>1));
initial begin
if (C !== 17) begin
$display("FAILED -- C == %d (%b)", C, C);
$finish;
end
$display("PASSED");
$finish;
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate case/endcase w/ label list - no default
module main ();
reg error;
reg [2:0] val1,val2;
reg [2:0] result ;
always @( val1 or val2)
case (val1 & val2 )
3\'b000,3\'b001: result = 0;
3\'b101: result = 1 ;
3\'b110,3\'b111,3\'b100: result = 2;
endcase
initial
begin
error = 0;
val1 = 3\'b0;
val2 = 3\'b0;
#1 if(result !==0)
begin
$display("FAILED case 3.8B - case (expr) lab1: ");
error = 1;
end
val1 = 3\'b101;
val2 = 3\'b111;
#1 if(result !==1)
begin
$display("FAILED case 3.8B - case (expr) lab2: ");
error = 1;
end
val1 = 3\'b110;
#1 if(result !==2)
begin
$display("FAILED case 3.8B - case (expr) lab1: ");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
module main;
reg [5*8-1 : 0] hello;
initial begin
hello = "XXXXX";
if (hello !== "XXXXX") begin
\t $display("FAILED -- X = %h", hello);
\t $finish;
end
$hello_poke(hello);
if (hello !== "Hello") begin
\t $display("FAILED -- Hello = %h", hello);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
// Check that a assignment operator on a dynamic part select of an vector works
// if it happes after a comparison that sets vvp flag 4 to 0.
module test;
logic [7:0] a = 8\'h0;
initial begin
if (a == 0) begin
// Make sure that this update happens, even though the compare above
// cleared set vvp flag 4
a[a+:1] += 1;
end
if (a == 1) begin
$display("PASSED");
end else begin
$display("FAILED. Expected 1, got %0d", a);
end
end
endmodule
|
/*
* This is based on PR#1026.
*/
module main;
reg [4:0] index;
reg [31:0] foo;
initial begin
for (index = 0 ; index < 31 ; index = index + 1) begin
\t #1 $display("index=%d, foo=%b", index, foo);
end
$finish(0);
end
always @(*)
begin
\tfoo = 32\'b0;
\tfoo[index]=1\'b1;
end
endmodule
|
// Check that it is an error to specify a default value for inout port
// declarations.
module M (
inout [31:0] x, y = 1 // inout ports do not support default values
);
initial begin
$display("FAILED");
end
endmodule
module test;
wire [31:0] x, y;
M i_m (
.x(x),
.y(y)
);
endmodule
|
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